diff options
Diffstat (limited to 'drivers')
30 files changed, 499 insertions, 1913 deletions
diff --git a/drivers/clk/uniphier/Kconfig b/drivers/clk/uniphier/Kconfig index 0e90c01a9a..da3e355389 100644 --- a/drivers/clk/uniphier/Kconfig +++ b/drivers/clk/uniphier/Kconfig @@ -1,13 +1,10 @@ config CLK_UNIPHIER - bool + bool "Clock driver for UniPhier SoCs" + depends on ARCH_UNIPHIER select CLK select SPL_CLK - -menu "Clock drivers for UniPhier SoCs" - depends on CLK_UNIPHIER - -config CLK_UNIPHIER_MIO - bool "Clock driver for UniPhier Media I/O block" default y - -endmenu + help + Support for clock controllers on UniPhier SoCs. + Say Y if you want to control clocks provided by System Control + block, Media I/O block, Peripheral Block. diff --git a/drivers/clk/uniphier/Makefile b/drivers/clk/uniphier/Makefile index a3168f9bc1..ed623aa56f 100644 --- a/drivers/clk/uniphier/Makefile +++ b/drivers/clk/uniphier/Makefile @@ -1,3 +1,2 @@ -obj-y += clk-uniphier-core.o - -obj-$(CONFIG_CLK_UNIPHIER_MIO) += clk-uniphier-mio.o +obj-y += clk-uniphier-core.o +obj-y += clk-uniphier-mio.o diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c index 394832607e..8ad0242d2a 100644 --- a/drivers/clk/uniphier/clk-uniphier-core.c +++ b/drivers/clk/uniphier/clk-uniphier-core.c @@ -6,11 +6,11 @@ */ #include <common.h> +#include <clk-uclass.h> +#include <dm/device.h> #include <linux/bitops.h> #include <linux/io.h> #include <linux/sizes.h> -#include <clk-uclass.h> -#include <dm/device.h> #include "clk-uniphier.h" @@ -18,136 +18,106 @@ * struct uniphier_clk_priv - private data for UniPhier clock driver * * @base: base address of the clock provider - * @socdata: SoC specific data + * @data: SoC specific data */ struct uniphier_clk_priv { void __iomem *base; - const struct uniphier_clk_soc_data *socdata; + const struct uniphier_clk_data *data; }; -int uniphier_clk_probe(struct udevice *dev) +static int uniphier_clk_enable(struct clk *clk) { - struct uniphier_clk_priv *priv = dev_get_priv(dev); - fdt_addr_t addr; + struct uniphier_clk_priv *priv = dev_get_priv(clk->dev); + unsigned long id = clk->id; + const struct uniphier_clk_gate_data *p; - addr = dev_get_addr(dev->parent); - if (addr == FDT_ADDR_T_NONE) - return -EINVAL; + for (p = priv->data->gate; p->id != UNIPHIER_CLK_ID_END; p++) { + u32 val; - priv->base = devm_ioremap(dev, addr, SZ_4K); - if (!priv->base) - return -ENOMEM; + if (p->id != id) + continue; - priv->socdata = (void *)dev_get_driver_data(dev); + val = readl(priv->base + p->reg); + val |= BIT(p->bit); + writel(val, priv->base + p->reg); - return 0; + return 0; + } + + dev_err(priv->dev, "clk_id=%lu was not handled\n", id); + return -EINVAL; } -static int uniphier_clk_enable(struct clk *clk) +static const struct uniphier_clk_mux_data * +uniphier_clk_get_mux_data(struct uniphier_clk_priv *priv, unsigned long id) { - struct uniphier_clk_priv *priv = dev_get_priv(clk->dev); - const struct uniphier_clk_gate_data *gate = priv->socdata->gate; - unsigned int nr_gate = priv->socdata->nr_gate; - void __iomem *reg; - u32 mask, data, tmp; - int i; - - for (i = 0; i < nr_gate; i++) { - if (gate[i].index != clk->id) - continue; - - reg = priv->base + gate[i].reg; - mask = gate[i].mask; - data = gate[i].data & mask; + const struct uniphier_clk_mux_data *p; - tmp = readl(reg); - tmp &= ~mask; - tmp |= data & mask; - debug("%s: %p: %08x\n", __func__, reg, tmp); - writel(tmp, reg); + for (p = priv->data->mux; p->id != UNIPHIER_CLK_ID_END; p++) { + if (p->id == id) + return p; } - return 0; + return NULL; } static ulong uniphier_clk_get_rate(struct clk *clk) { struct uniphier_clk_priv *priv = dev_get_priv(clk->dev); - const struct uniphier_clk_rate_data *rdata = priv->socdata->rate; - unsigned int nr_rdata = priv->socdata->nr_rate; - void __iomem *reg; - u32 mask, data; - ulong matched_rate = 0; + const struct uniphier_clk_mux_data *mux; + u32 val; int i; - for (i = 0; i < nr_rdata; i++) { - if (rdata[i].index != clk->id) - continue; + mux = uniphier_clk_get_mux_data(priv, clk->id); + if (!mux) + return 0; - if (rdata[i].reg == UNIPHIER_CLK_RATE_IS_FIXED) - return rdata[i].rate; - - reg = priv->base + rdata[i].reg; - mask = rdata[i].mask; - data = rdata[i].data & mask; - if ((readl(reg) & mask) == data) { - if (matched_rate && rdata[i].rate != matched_rate) { - printf("failed to get clk rate for insane register values\n"); - return -EINVAL; - } - matched_rate = rdata[i].rate; - } - } + if (!mux->nr_muxs) /* fixed-rate */ + return mux->rates[0]; + + val = readl(priv->base + mux->reg); - debug("%s: rate = %lu\n", __func__, matched_rate); + for (i = 0; i < mux->nr_muxs; i++) + if ((mux->masks[i] & val) == mux->vals[i]) + return mux->rates[i]; - return matched_rate; + return -EINVAL; } static ulong uniphier_clk_set_rate(struct clk *clk, ulong rate) { struct uniphier_clk_priv *priv = dev_get_priv(clk->dev); - const struct uniphier_clk_rate_data *rdata = priv->socdata->rate; - unsigned int nr_rdata = priv->socdata->nr_rate; - void __iomem *reg; - u32 mask, data, tmp; + const struct uniphier_clk_mux_data *mux; + u32 val; + int i, best_rate_id = -1; ulong best_rate = 0; - int i; - /* first, decide the best match rate */ - for (i = 0; i < nr_rdata; i++) { - if (rdata[i].index != clk->id) - continue; + mux = uniphier_clk_get_mux_data(priv, clk->id); + if (!mux) + return 0; - if (rdata[i].reg == UNIPHIER_CLK_RATE_IS_FIXED) - return 0; + if (!mux->nr_muxs) /* fixed-rate */ + return mux->rates[0]; - if (rdata[i].rate > best_rate && rdata[i].rate <= rate) - best_rate = rdata[i].rate; + /* first, decide the best match rate */ + for (i = 0; i < mux->nr_muxs; i++) { + if (mux->rates[i] > best_rate && mux->rates[i] <= rate) { + best_rate = mux->rates[i]; + best_rate_id = i; + } } - if (!best_rate) - return -ENODEV; + if (best_rate_id < 0) + return -EINVAL; + + val = readl(priv->base + mux->reg); + val &= ~mux->masks[best_rate_id]; + val |= mux->vals[best_rate_id]; + writel(val, priv->base + mux->reg); debug("%s: requested rate = %lu, set rate = %lu\n", __func__, rate, best_rate); - /* second, really set registers */ - for (i = 0; i < nr_rdata; i++) { - if (rdata[i].index != clk->id || rdata[i].rate != best_rate) - continue; - - reg = priv->base + rdata[i].reg; - mask = rdata[i].mask; - data = rdata[i].data & mask; - - tmp = readl(reg); - tmp &= ~mask; - tmp |= data; - debug("%s: %p: %08x\n", __func__, reg, tmp); - writel(tmp, reg); - } - return best_rate; } @@ -157,6 +127,24 @@ const struct clk_ops uniphier_clk_ops = { .set_rate = uniphier_clk_set_rate, }; +static int uniphier_clk_probe(struct udevice *dev) +{ + struct uniphier_clk_priv *priv = dev_get_priv(dev); + fdt_addr_t addr; + + addr = dev_get_addr(dev->parent); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->base = devm_ioremap(dev, addr, SZ_4K); + if (!priv->base) + return -ENOMEM; + + priv->data = (void *)dev_get_driver_data(dev); + + return 0; +} + static const struct udevice_id uniphier_clk_match[] = { { .compatible = "socionext,uniphier-sld3-mio-clock", diff --git a/drivers/clk/uniphier/clk-uniphier-mio.c b/drivers/clk/uniphier/clk-uniphier-mio.c index c1e7197c1a..18e6856709 100644 --- a/drivers/clk/uniphier/clk-uniphier-mio.c +++ b/drivers/clk/uniphier/clk-uniphier-mio.c @@ -5,136 +5,81 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include <dm/device.h> - #include "clk-uniphier.h" -#define UNIPHIER_MIO_CLK_GATE_SD(ch, idx) \ - { \ - .index = (idx), \ - .reg = 0x20 + 0x200 * (ch), \ - .mask = 0x00000100, \ - .data = 0x00000100, \ - }, \ - { \ - .index = (idx), \ - .reg = 0x110 + 0x200 * (ch), \ - .mask = 0x00000001, \ - .data = 0x00000001, \ - } +#define UNIPHIER_MIO_CLK_SD_GATE(id, ch) \ + UNIPHIER_CLK_GATE((id), 0x20 + 0x200 * (ch), 8) -#define UNIPHIER_MIO_CLK_RATE_SD(ch, idx) \ - { \ - .index = (idx), \ - .reg = 0x30 + 0x200 * (ch), \ - .mask = 0x00031300, \ - .data = 0x00000000, \ - .rate = 44444444, \ - }, \ - { \ - .index = (idx), \ - .reg = 0x30 + 0x200 * (ch), \ - .mask = 0x00031300, \ - .data = 0x00010000, \ - .rate = 33333333, \ - }, \ - { \ - .index = (idx), \ - .reg = 0x30 + 0x200 * (ch), \ - .mask = 0x00031300, \ - .data = 0x00020000, \ - .rate = 50000000, \ - }, \ - { \ - .index = (idx), \ - .reg = 0x30 + 0x200 * (ch), \ - .mask = 0x00031300, \ - .data = 0x00020000, \ - .rate = 66666666, \ - }, \ - { \ - .index = (idx), \ - .reg = 0x30 + 0x200 * (ch), \ - .mask = 0x00031300, \ - .data = 0x00001000, \ - .rate = 100000000, \ - }, \ - { \ - .index = (idx), \ - .reg = 0x30 + 0x200 * (ch), \ - .mask = 0x00031300, \ - .data = 0x00001100, \ - .rate = 40000000, \ - }, \ - { \ - .index = (idx), \ - .reg = 0x30 + 0x200 * (ch), \ - .mask = 0x00031300, \ - .data = 0x00001200, \ - .rate = 25000000, \ - }, \ - { \ - .index = (idx), \ - .reg = 0x30 + 0x200 * (ch), \ - .mask = 0x00031300, \ - .data = 0x00001300, \ - .rate = 22222222, \ - } +#define UNIPHIER_MIO_CLK_USB2(id, ch) \ + UNIPHIER_CLK_GATE((id), 0x20 + 0x200 * (ch), 28) -#define UNIPHIER_MIO_CLK_GATE_USB(ch, idx) \ - { \ - .index = (idx), \ - .reg = 0x20 + 0x200 * (ch), \ - .mask = 0x30000000, \ - .data = 0x30000000, \ - }, \ - { \ - .index = (idx), \ - .reg = 0x110 + 0x200 * (ch), \ - .mask = 0x01000000, \ - .data = 0x01000000, \ - }, \ - { \ - .index = (idx), \ - .reg = 0x114 + 0x200 * (ch), \ - .mask = 0x00000001, \ - .data = 0x00000001, \ - } +#define UNIPHIER_MIO_CLK_USB2_PHY(id, ch) \ + UNIPHIER_CLK_GATE((id), 0x20 + 0x200 * (ch), 29) + +#define UNIPHIER_MIO_CLK_DMAC(id) \ + UNIPHIER_CLK_GATE((id), 0x20, 25) -#define UNIPHIER_MIO_CLK_GATE_DMAC(idx) \ - { \ - .index = (idx), \ - .reg = 0x20, \ - .mask = 0x02000000, \ - .data = 0x02000000, \ - }, \ - { \ - .index = (idx), \ - .reg = 0x110, \ - .mask = 0x00020000, \ - .data = 0x00020000, \ +#define UNIPHIER_MIO_CLK_SD_MUX(_id, ch) \ + { \ + .id = (_id), \ + .nr_muxs = 8, \ + .reg = 0x30 + 0x200 * (ch), \ + .masks = { \ + 0x00031000, \ + 0x00031000, \ + 0x00031000, \ + 0x00031000, \ + 0x00001300, \ + 0x00001300, \ + 0x00001300, \ + 0x00001300, \ + }, \ + .vals = { \ + 0x00000000, \ + 0x00010000, \ + 0x00020000, \ + 0x00030000, \ + 0x00001000, \ + 0x00001100, \ + 0x00001200, \ + 0x00001300, \ + }, \ + .rates = { \ + 44444444, \ + 33333333, \ + 50000000, \ + 66666666, \ + 100000000, \ + 40000000, \ + 25000000, \ + 22222222, \ + }, \ } static const struct uniphier_clk_gate_data uniphier_mio_clk_gate[] = { - UNIPHIER_MIO_CLK_GATE_SD(0, 0), - UNIPHIER_MIO_CLK_GATE_SD(1, 1), - UNIPHIER_MIO_CLK_GATE_SD(2, 2), /* for PH1-Pro4 only */ - UNIPHIER_MIO_CLK_GATE_USB(0, 3), - UNIPHIER_MIO_CLK_GATE_USB(1, 4), - UNIPHIER_MIO_CLK_GATE_USB(2, 5), - UNIPHIER_MIO_CLK_GATE_DMAC(6), - UNIPHIER_MIO_CLK_GATE_USB(3, 7), /* for PH1-sLD3 only */ + UNIPHIER_MIO_CLK_SD_GATE(0, 0), + UNIPHIER_MIO_CLK_SD_GATE(1, 1), + UNIPHIER_MIO_CLK_SD_GATE(2, 2), /* for PH1-Pro4 only */ + UNIPHIER_MIO_CLK_DMAC(7), + UNIPHIER_MIO_CLK_USB2(8, 0), + UNIPHIER_MIO_CLK_USB2(9, 1), + UNIPHIER_MIO_CLK_USB2(10, 2), + UNIPHIER_MIO_CLK_USB2(11, 3), /* for PH1-sLD3 only */ + UNIPHIER_MIO_CLK_USB2_PHY(12, 0), + UNIPHIER_MIO_CLK_USB2_PHY(13, 1), + UNIPHIER_MIO_CLK_USB2_PHY(14, 2), + UNIPHIER_MIO_CLK_USB2_PHY(15, 3), /* for PH1-sLD3 only */ + UNIPHIER_CLK_END }; -static const struct uniphier_clk_rate_data uniphier_mio_clk_rate[] = { - UNIPHIER_MIO_CLK_RATE_SD(0, 0), - UNIPHIER_MIO_CLK_RATE_SD(1, 1), - UNIPHIER_MIO_CLK_RATE_SD(2, 2), /* for PH1-Pro4 only */ +static const struct uniphier_clk_mux_data uniphier_mio_clk_mux[] = { + UNIPHIER_MIO_CLK_SD_MUX(0, 0), + UNIPHIER_MIO_CLK_SD_MUX(1, 1), + UNIPHIER_MIO_CLK_SD_MUX(2, 2), /* for PH1-Pro4 only */ + UNIPHIER_CLK_END }; -const struct uniphier_clk_soc_data uniphier_mio_clk_data = { +const struct uniphier_clk_data uniphier_mio_clk_data = { .gate = uniphier_mio_clk_gate, - .nr_gate = ARRAY_SIZE(uniphier_mio_clk_gate), - .rate = uniphier_mio_clk_rate, - .nr_rate = ARRAY_SIZE(uniphier_mio_clk_rate), + .mux = uniphier_mio_clk_mux, }; diff --git a/drivers/clk/uniphier/clk-uniphier.h b/drivers/clk/uniphier/clk-uniphier.h index 0b60337205..f9a560ee73 100644 --- a/drivers/clk/uniphier/clk-uniphier.h +++ b/drivers/clk/uniphier/clk-uniphier.h @@ -10,36 +10,46 @@ #include <linux/kernel.h> +#define UNIPHIER_CLK_MAX_NR_MUXS 8 + struct uniphier_clk_gate_data { - int index; + unsigned int id; unsigned int reg; - u32 mask; - u32 data; + unsigned int bit; }; -struct uniphier_clk_rate_data { - int index; +struct uniphier_clk_mux_data { + unsigned int id; + unsigned int nr_muxs; unsigned int reg; -#define UNIPHIER_CLK_RATE_IS_FIXED UINT_MAX - u32 mask; - u32 data; - unsigned long rate; + unsigned int masks[UNIPHIER_CLK_MAX_NR_MUXS]; + unsigned int vals[UNIPHIER_CLK_MAX_NR_MUXS]; + unsigned long rates[UNIPHIER_CLK_MAX_NR_MUXS]; }; -struct uniphier_clk_soc_data { +struct uniphier_clk_data { const struct uniphier_clk_gate_data *gate; - unsigned int nr_gate; - const struct uniphier_clk_rate_data *rate; - unsigned int nr_rate; + const struct uniphier_clk_mux_data *mux; }; -#define UNIPHIER_CLK_FIXED_RATE(i, f) \ +#define UNIPHIER_CLK_ID_END (unsigned int)(-1) + +#define UNIPHIER_CLK_END \ + { .id = UNIPHIER_CLK_ID_END } + +#define UNIPHIER_CLK_GATE(_id, _reg, _bit) \ + { \ + .id = (_id), \ + .reg = (_reg), \ + .bit = (_bit), \ + } + +#define UNIPHIER_CLK_FIXED_RATE(_id, _rate) \ { \ - .index = i, \ - .reg = UNIPHIER_CLK_RATE_IS_FIXED, \ - .rate = f, \ + .id = (_id), \ + .rates = {(_reg),}, \ } -extern const struct uniphier_clk_soc_data uniphier_mio_clk_data; +extern const struct uniphier_clk_data uniphier_mio_clk_data; #endif /* __CLK_UNIPHIER_H__ */ diff --git a/drivers/core/device.c b/drivers/core/device.c index 1935b8d46f..dcf5d9df7d 100644 --- a/drivers/core/device.c +++ b/drivers/core/device.c @@ -698,8 +698,8 @@ fdt_addr_t dev_get_addr_name(struct udevice *dev, const char *name) #if CONFIG_IS_ENABLED(OF_CONTROL) int index; - index = fdt_stringlist_search(gd->fdt_blob, dev->of_offset, "reg-names", - name); + index = fdt_stringlist_search(gd->fdt_blob, dev->of_offset, + "reg-names", name); if (index < 0) return index; diff --git a/drivers/cpu/cpu-uclass.c b/drivers/cpu/cpu-uclass.c index 7660f99ef5..c57ac16b3a 100644 --- a/drivers/cpu/cpu-uclass.c +++ b/drivers/cpu/cpu-uclass.c @@ -44,6 +44,16 @@ int cpu_get_count(struct udevice *dev) return ops->get_count(dev); } +int cpu_get_vendor(struct udevice *dev, char *buf, int size) +{ + struct cpu_ops *ops = cpu_get_ops(dev); + + if (!ops->get_vendor) + return -ENOSYS; + + return ops->get_vendor(dev, buf, size); +} + U_BOOT_DRIVER(cpu_bus) = { .name = "cpu_bus", .id = UCLASS_SIMPLE_BUS, diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index e60fd0a419..c68ff6420b 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -249,6 +249,7 @@ static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr, int alen, u8 *buffer, int len) { unsigned long start_time_rx; + unsigned int active = 0; #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW /* @@ -274,18 +275,28 @@ static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr, start_time_rx = get_timer(0); while (len) { - if (len == 1) - writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data); - else - writel(IC_CMD, &i2c_base->ic_cmd_data); + if (!active) { + /* + * Avoid writing to ic_cmd_data multiple times + * in case this loop spins too quickly and the + * ic_status RFNE bit isn't set after the first + * write. Subsequent writes to ic_cmd_data can + * trigger spurious i2c transfer. + */ + if (len == 1) + writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data); + else + writel(IC_CMD, &i2c_base->ic_cmd_data); + active = 1; + } if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) { *buffer++ = (uchar)readl(&i2c_base->ic_cmd_data); len--; start_time_rx = get_timer(0); - + active = 0; } else if (get_timer(start_time_rx) > I2C_BYTE_TO) { - return 1; + return 1; } } diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c index 77424cdcea..2fe5d61e26 100644 --- a/drivers/mmc/mmc-uclass.c +++ b/drivers/mmc/mmc-uclass.c @@ -116,13 +116,7 @@ int get_mmc_num(void) int mmc_get_next_devnum(void) { - int ret; - - ret = blk_find_max_devnum(IF_TYPE_MMC); - if (ret < 0) - return ret; - - return ret; + return blk_find_max_devnum(IF_TYPE_MMC); } struct blk_desc *mmc_get_blk_desc(struct mmc *mmc) @@ -243,7 +237,6 @@ static int mmc_select_hwpart(struct udevice *bdev, int hwpart) struct udevice *mmc_dev = dev_get_parent(bdev); struct mmc *mmc = mmc_get_mmc_dev(mmc_dev); struct blk_desc *desc = dev_get_uclass_platdata(bdev); - int ret; if (desc->hwpart == hwpart) return 0; @@ -251,11 +244,7 @@ static int mmc_select_hwpart(struct udevice *bdev, int hwpart) if (mmc->part_config == MMCPART_NOAVAILABLE) return -EMEDIUMTYPE; - ret = mmc_switch_part(mmc, hwpart); - if (ret) - return ret; - - return 0; + return mmc_switch_part(mmc, hwpart); } static const struct blk_ops mmc_blk_ops = { diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 0312da91af..4380c7c195 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -15,6 +15,7 @@ #include <errno.h> #include <mmc.h> #include <part.h> +#include <power/regulator.h> #include <malloc.h> #include <memalign.h> #include <linux/list.h> @@ -1582,6 +1583,31 @@ __weak void board_mmc_power_init(void) { } +static int mmc_power_init(struct mmc *mmc) +{ + board_mmc_power_init(); + +#if defined(CONFIG_DM_MMC) && defined(CONFIG_DM_REGULATOR) && \ + !defined(CONFIG_SPL_BUILD) + struct udevice *vmmc_supply; + int ret; + + ret = device_get_supply_regulator(mmc->dev, "vmmc-supply", + &vmmc_supply); + if (ret) { + debug("%s: No vmmc supply\n", mmc->dev->name); + return 0; + } + + ret = regulator_set_enable(vmmc_supply, true); + if (ret) { + puts("Error enabling VMMC supply\n"); + return ret; + } +#endif + return 0; +} + int mmc_start_init(struct mmc *mmc) { bool no_card; @@ -1606,7 +1632,9 @@ int mmc_start_init(struct mmc *mmc) #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT mmc_adapter_card_type_ident(); #endif - board_mmc_power_init(); + err = mmc_power_init(mmc); + if (err) + return err; #ifdef CONFIG_DM_MMC_OPS /* The device has already been probed ready for use */ diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 837c53842b..766e9eef84 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -242,6 +242,7 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT); #ifdef CONFIG_MMC_SDMA + trans_bytes = ALIGN(trans_bytes, CONFIG_SYS_CACHELINE_SIZE); flush_cache(start_addr, trans_bytes); #endif sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND); @@ -607,9 +608,11 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host, * In case of Host Controller v3.00, find out whether clock * multiplier is supported. */ - caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); - host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >> - SDHCI_CLOCK_MUL_SHIFT; + if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { + caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); + host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >> + SDHCI_CLOCK_MUL_SHIFT; + } return 0; } diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c index 5a3a4ff403..0a22e58295 100644 --- a/drivers/mmc/socfpga_dw_mmc.c +++ b/drivers/mmc/socfpga_dw_mmc.c @@ -151,7 +151,9 @@ U_BOOT_DRIVER(socfpga_dwmmc_drv) = { .id = UCLASS_MMC, .of_match = socfpga_dwmmc_ids, .ofdata_to_platdata = socfpga_dwmmc_ofdata_to_platdata, + .ops = &dm_dwmci_ops, .bind = socfpga_dwmmc_bind, .probe = socfpga_dwmmc_probe, .priv_auto_alloc_size = sizeof(struct dwmci_socfpga_priv_data), + .platdata_auto_alloc_size = sizeof(struct socfpga_dwmci_plat), }; diff --git a/drivers/net/ax88180.c b/drivers/net/ax88180.c index 43a67a514b..261fde00c1 100644 --- a/drivers/net/ax88180.c +++ b/drivers/net/ax88180.c @@ -698,11 +698,7 @@ static void ax88180_read_mac_addr (struct eth_device *dev) } } -/* -=========================================================================== -<<<<<< Exported SubProgram Bodies >>>>>> -=========================================================================== -*/ +/* Exported SubProgram Bodies */ int ax88180_initialize (bd_t * bis) { struct eth_device *dev; diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index 91570a2910..6ac8ba3721 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -457,7 +457,7 @@ static int parse_phy_pins(struct udevice *dev) int pin; pin_name = fdt_stringlist_get(gd->fdt_blob, offset, - "allwinner,pins", i, NULL); + "allwinner,pins", i, NULL); if (!pin_name) break; if (pin_name[0] != 'P') diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 9a7c187446..b8376b4f47 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -1,4 +1,12 @@ -menu "PCI" +menuconfig PCI + bool "PCI support" + default y if PPC || X86 + help + Enable support for PCI (Peripheral Interconnect Bus), a type of bus + used on some devices to allow the CPU to communicate with its + peripherals. + +if PCI config DM_PCI bool "Enable driver mode for PCI" @@ -18,6 +26,13 @@ config DM_PCI_COMPAT measure when porting a board to use driver model for PCI. Once the board is fully supported, this option should be disabled. +config PCI_PNP + bool "Enable Plug & Play support for PCI" + depends on PCI || DM_PCI + default y + help + Enable PCI memory and I/O space resource allocation and assignment. + config PCI_SANDBOX bool "Sandbox PCI support" depends on SANDBOX && DM_PCI @@ -46,4 +61,4 @@ config PCI_XILINX Enable support for the Xilinx AXI bridge for PCI express, an IP block which can be used on some generations of Xilinx FPGAs. -endmenu +endif diff --git a/drivers/pinctrl/exynos/pinctrl-exynos.c b/drivers/pinctrl/exynos/pinctrl-exynos.c index c9c13e6802..dd0a16ef5f 100644 --- a/drivers/pinctrl/exynos/pinctrl-exynos.c +++ b/drivers/pinctrl/exynos/pinctrl-exynos.c @@ -80,7 +80,7 @@ int exynos_pinctrl_set_state(struct udevice *dev, struct udevice *config) * refer to the following document for the pinctrl bindings * linux/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt */ - count = fdt_stringlist_count(fdt, node, "samsung,pins"); + count = fdt_stringlist_count(fdt, node, "samsung,pins"); if (count <= 0) return -EINVAL; diff --git a/drivers/pinctrl/pinctrl-generic.c b/drivers/pinctrl/pinctrl-generic.c index 482db295fe..3629322dbb 100644 --- a/drivers/pinctrl/pinctrl-generic.c +++ b/drivers/pinctrl/pinctrl-generic.c @@ -306,12 +306,12 @@ static int pinctrl_generic_set_state_subnode(struct udevice *dev, const char *name; int strings_count, selector, i, ret; - strings_count = fdt_stringlist_count(fdt, node, subnode_target_type); + strings_count = fdt_stringlist_count(fdt, node, subnode_target_type); if (strings_count < 0) { subnode_target_type = "groups"; is_group = true; - strings_count = fdt_stringlist_count(fdt, node, - subnode_target_type); + strings_count = fdt_stringlist_count(fdt, node, + subnode_target_type); if (strings_count < 0) { /* skip this node; may contain config child nodes */ return 0; diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier.h b/drivers/pinctrl/uniphier/pinctrl-uniphier.h index 5c3db2ab60..21e2d377b4 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier.h +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier.h @@ -91,7 +91,12 @@ struct uniphier_pinctrl_socdata { #define __UNIPHIER_PINMUX_FUNCTION(func) #func #ifdef CONFIG_SPL_BUILD -#define UNIPHIER_PINCTRL_GROUP(grp) { .name = NULL } + /* + * a tricky way to drop unneeded *_pins and *_muxvals arrays from SPL, + * suppressing "defined but not used" warnings. + */ +#define UNIPHIER_PINCTRL_GROUP(grp) \ + { .num_pins = ARRAY_SIZE(grp##_pins) + ARRAY_SIZE(grp##_muxvals) } #define UNIPHIER_PINMUX_FUNCTION(func) NULL #else #define UNIPHIER_PINCTRL_GROUP(grp) __UNIPHIER_PINCTRL_GROUP(grp) diff --git a/drivers/power/twl6030.c b/drivers/power/twl6030.c index 05c79be98f..cd532008bd 100644 --- a/drivers/power/twl6030.c +++ b/drivers/power/twl6030.c @@ -231,9 +231,9 @@ void twl6030_power_mmc_init(int dev_index) /* Enable P1 output for VMMC */ twl6030_i2c_write_u8(TWL6030_CHIP_PM, TWL6030_VMMC_CFG_STATE, TWL6030_CFG_STATE_P1 | TWL6030_CFG_STATE_ON); - - twl6030_i2c_read_u8(TWL6030_CHIP_PM, TWL6030_PH_STS_BOOT, &value); } else if (dev_index == 1) { + twl6030_i2c_read_u8(TWL6030_CHIP_PM, TWL6030_PH_STS_BOOT, + &value); /* BOOT2 indicates 1.8V/2.8V VAUX1 for eMMC */ if (value & TWL6030_PH_STS_BOOT2) { /* 1.8V voltage output for VAUX1 */ diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c index 19f38e162e..43c028ebe6 100644 --- a/drivers/serial/serial-uclass.c +++ b/drivers/serial/serial-uclass.c @@ -346,7 +346,7 @@ static int serial_post_probe(struct udevice *dev) static int serial_pre_remove(struct udevice *dev) { -#ifdef CONFIG_SYS_STDIO_DEREGISTER +#if CONFIG_IS_ENABLED(SYS_STDIO_DEREGISTER) struct serial_dev_priv *upriv = dev_get_uclass_priv(dev); if (stdio_deregister_dev(upriv->sdev, 0)) diff --git a/drivers/usb/host/isp116x-hcd.c b/drivers/usb/host/isp116x-hcd.c index 0556f328e4..32874d73de 100644 --- a/drivers/usb/host/isp116x-hcd.c +++ b/drivers/usb/host/isp116x-hcd.c @@ -428,10 +428,10 @@ static int isp116x_interrupt(struct isp116x *isp116x) isp116x_write_reg16(isp116x, HCuPINTENB, 0); irqstat = isp116x_read_reg16(isp116x, HCuPINT); isp116x_write_reg16(isp116x, HCuPINT, irqstat); - DBG(">>>>>> irqstat %x <<<<<<", irqstat); + DBG("------ irqstat %x ------", irqstat); if (irqstat & HCuPINT_ATL) { - DBG(">>>>>> HCuPINT_ATL <<<<<<"); + DBG("------ HCuPINT_ATL ------"); udelay(500); ret = 1; } @@ -439,7 +439,7 @@ static int isp116x_interrupt(struct isp116x *isp116x) if (irqstat & HCuPINT_OPR) { intstat = isp116x_read_reg32(isp116x, HCINTSTAT); isp116x_write_reg32(isp116x, HCINTSTAT, intstat); - DBG(">>>>>> HCuPINT_OPR %x <<<<<<", intstat); + DBG("------ HCuPINT_OPR %x ------", intstat); if (intstat & HCINT_UE) { ERR("unrecoverable error, controller disabled"); diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 86db0dac5a..577e6d7b39 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -434,4 +434,160 @@ config VIDEO_TEGRA124 source "drivers/video/bridge/Kconfig" +config VIDEO + bool "Enable legacy video support" + depends on !DM_VIDEO + help + Define this for video support, without using driver model. Some + drivers use this because they are not yet converted to driver + model. Video drivers typically provide a colour text console and + cursor. + +config CFB_CONSOLE + bool "Enable colour frame buffer console" + depends on VIDEO + default y if VIDEO + help + Enables the colour frame buffer driver. This supports colour + output on a bitmap display from an in-memory frame buffer. + Several colour devices are supported along with various options to + adjust the supported features. The driver is implemented in + cfb_console.c + + The following defines are needed (cf. smiLynxEM, i8042) + VIDEO_FB_LITTLE_ENDIAN graphic memory organisation + (default big endian) + VIDEO_HW_RECTFILL graphic chip supports + rectangle fill (cf. smiLynxEM) + VIDEO_HW_BITBLT graphic chip supports + bit-blit (cf. smiLynxEM) + VIDEO_VISIBLE_COLS visible pixel columns (cols=pitch) + VIDEO_VISIBLE_ROWS visible pixel rows + VIDEO_PIXEL_SIZE bytes per pixel + VIDEO_DATA_FORMAT graphic data format + (0-5, cf. cfb_console.c) + VIDEO_FB_ADRS framebuffer address + VIDEO_KBD_INIT_FCT keyboard int fct (i.e. rx51_kp_init()) + VIDEO_TSTC_FCT test char fct (i.e. rx51_kp_tstc) + VIDEO_GETC_FCT get char fct (i.e. rx51_kp_getc) + CONFIG_VIDEO_LOGO display Linux logo in upper left corner + CONFIG_VIDEO_BMP_LOGO use bmp_logo.h instead of linux_logo.h + for logo. Requires CONFIG_VIDEO_LOGO + CONFIG_CONSOLE_EXTRA_INFO + additional board info beside + the logo + CONFIG_HIDE_LOGO_VERSION + do not display bootloader + version string + + When CONFIG_CFB_CONSOLE is defined, the video console is the + default console. The serial console can be forced by setting the + environment 'console=serial'. + +config CFB_CONSOLE_ANSI + bool "Support ANSI escape sequences" + depends on CFB_CONSOLE + help + This allows the colour buffer frame buffer driver to support + a limited number of ANSI escape sequences (cursor control, + erase functions and limited graphics rendition control). Normal + output from U-Boot will pass through this filter. + +config VGA_AS_SINGLE_DEVICE + bool "Set the video as an output-only device" + depends on CFB_CONSOLE + default y + help + If enable the framebuffer device will be initialized as an + output-only device. The Keyboard driver will not be set up. This + may be used if you have no keyboard device, or more than one + (USB Keyboard, AT Keyboard). + +config VIDEO_SW_CURSOR + bool "Enable a software cursor" + depends on CFB_CONSOLE + default y if CFB_CONSOLE + help + This draws a cursor after the last character. No blinking is + provided. This makes it possible to see the current cursor + position when entering text on the console. It is recommended to + enable this. + +config CONSOLE_EXTRA_INFO + bool "Display additional board information" + depends on CFB_CONSOLE + help + Display additional board information strings that normally go to + the serial port. When this option is enabled, a board-specific + function video_get_info_str() is called to get the string for + each line of the display. The function should return the string, + which can be empty if there is nothing to display for that line. + +config CONSOLE_SCROLL_LINES + int "Number of lines to scroll the console by" + depends on CFB_CONSOLE || DM_VIDEO || LCD + default 1 + help + When the console need to be scrolled, this is the number of + lines to scroll by. It defaults to 1. Increasing this makes the + console jump but can help speed up operation when scrolling + is slow. + +config VIDEO_CT69000 + bool "Enable Chips & Technologies 69000 video driver" + depends on VIDEO + help + This enables a frame buffer driver for the Chips & Technologies + ct69000, a fairly old graphics device (circa 2000) which is used + on some hardware. It operates over the ISA bus, and supports + some acceleration features. + + For the CT69000 and SMI_LYNXEM drivers, videomode is + selected via environment 'videomode'. Two different ways + are possible: + - "videomode=num" 'num' is a standard LiLo mode numbers. + Following standard modes are supported (* is default): + + Colors 640x480 800x600 1024x768 1152x864 1280x1024 + -------------+--------------------------------------------- + 8 bits | 0x301* 0x303 0x305 0x161 0x307 + 15 bits | 0x310 0x313 0x316 0x162 0x319 + 16 bits | 0x311 0x314 0x317 0x163 0x31A + 24 bits | 0x312 0x315 0x318 ? 0x31B + -------------+--------------------------------------------- + (i.e. setenv videomode 317; saveenv; reset;) + + - "videomode=bootargs" all the video parameters are parsed + from the bootargs. (See drivers/video/videomodes.c) + +config SYS_CONSOLE_BG_COL + hex "Background colour" + depends on CFB_CONSOLE || VIDEO_CT69000 + default 0x00 + help + Defines the background colour for the console. The value is from + 0x00 to 0xff and the meaning depends on the graphics card. + Typically, 0x00 means black and 0xff means white. Do not set + the background and foreground to the same colour or you will see + nothing. + +config SYS_CONSOLE_FG_COL + hex "Foreground colour" + depends on CFB_CONSOLE || VIDEO_CT69000 + default 0xa0 + help + Defines the foreground colour for the console. The value is from + 0x00 to 0xff and the meaning depends on the graphics card. + Typically, 0x00 means black and 0xff means white. Do not set + the background and foreground to the same colour or you will see + nothing. + +config LCD + bool "Enable legacy LCD support" + help + Define this to enable LCD support (for output to LCD display). + You will also need to select an LCD driver using an additional + CONFIG option. See the README for details. Drives which have been + converted to driver model will instead used CONFIG_DM_VIDEO. + endmenu diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 4a4241750d..db34904a9a 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -40,7 +40,6 @@ obj-$(CONFIG_VIDEO_BCM2835) += bcm2835.o obj-$(CONFIG_VIDEO_COREBOOT) += coreboot.o obj-$(CONFIG_VIDEO_CT69000) += ct69000.o videomodes.o obj-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o -obj-$(CONFIG_VIDEO_IMX25LCDC) += imx25lcdc.o videomodes.o obj-$(CONFIG_VIDEO_LCD_ANX9804) += anx9804.o obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o @@ -50,11 +49,8 @@ obj-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o obj-$(CONFIG_VIDEO_MVEBU) += mvebu_lcd.o obj-$(CONFIG_VIDEO_MXS) += mxsfb.o videomodes.o obj-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o -obj-$(CONFIG_VIDEO_S3C) += s3c-fb.o videomodes.o obj-$(CONFIG_VIDEO_SANDBOX_SDL) += sandbox_sdl.o -obj-$(CONFIG_VIDEO_SED13806) += sed13806.o obj-$(CONFIG_VIDEO_SM501) += sm501.o -obj-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o videomodes.o obj-$(CONFIG_VIDEO_TEGRA20) += tegra.o obj-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index 30b53dbb80..c0b1b8dc17 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -27,7 +27,6 @@ * * (for SMI LynxE graphic chip) * - * CONFIG_VIDEO_SMI_LYNXEM - use graphic driver for SMI 710,712,810 * VIDEO_FB_LITTLE_ENDIAN - framebuffer organisation default: big endian * VIDEO_HW_RECTFILL - graphic driver supports hardware rectangle fill * VIDEO_HW_BITBLT - graphic driver supports hardware bit blt @@ -59,46 +58,21 @@ * info); * that fills a info buffer at i=row. * s.a: board/eltec/bab7xx. - * CONFIG_VGA_AS_SINGLE_DEVICE - If set the framebuffer device will be - * initialized as an output only device. - * The Keyboard driver will not be - * set-up. This may be used, if you have - * no or more than one Keyboard devices - * (USB Keyboard, AT Keyboard). * * CONFIG_VIDEO_SW_CURSOR: - Draws a cursor after the last * character. No blinking is provided. * Uses the macros CURSOR_SET and * CURSOR_OFF. - * - * CONFIG_VIDEO_HW_CURSOR: - Uses the hardware cursor capability - * of the graphic chip. Uses the macro - * CURSOR_SET. ATTENTION: If booting an - * OS, the display driver must disable - * the hardware register of the graphic - * chip. Otherwise a blinking field is - * displayed. */ #include <common.h> #include <fdtdec.h> #include <version.h> #include <malloc.h> +#include <video.h> #include <linux/compiler.h> /* - * Console device defines with SMI graphic - * Any other graphic must change this section - */ - -#ifdef CONFIG_VIDEO_SMI_LYNXEM - -#define VIDEO_FB_LITTLE_ENDIAN -#define VIDEO_HW_RECTFILL -#define VIDEO_HW_BITBLT -#endif - -/* * Defines for the CT69000 driver */ #ifdef CONFIG_VIDEO_CT69000 @@ -108,16 +82,7 @@ #define VIDEO_HW_BITBLT #endif -/* - * Defines for the SED13806 driver - */ -#ifdef CONFIG_VIDEO_SED13806 -#define VIDEO_FB_LITTLE_ENDIAN -#define VIDEO_HW_RECTFILL -#define VIDEO_HW_BITBLT -#endif - -#if defined(CONFIG_VIDEO_MXS) || defined(CONFIG_VIDEO_S3C) +#if defined(CONFIG_VIDEO_MXS) #define VIDEO_FB_16BPP_WORD_SWAP #endif @@ -177,18 +142,7 @@ #include <splash.h> #endif -/* - * Cursor definition: - * CONFIG_VIDEO_SW_CURSOR: Draws a cursor after the last character. No - * blinking is provided. Uses the macros CURSOR_SET - * and CURSOR_OFF. - * CONFIG_VIDEO_HW_CURSOR: Uses the hardware cursor capability of the - * graphic chip. Uses the macro CURSOR_SET. - * ATTENTION: If booting an OS, the display driver - * must disable the hardware register of the graphic - * chip. Otherwise a blinking field is displayed - */ -#if !defined(CONFIG_VIDEO_SW_CURSOR) && !defined(CONFIG_VIDEO_HW_CURSOR) +#if !defined(CONFIG_VIDEO_SW_CURSOR) /* no Cursor defined */ #define CURSOR_ON #define CURSOR_OFF @@ -196,10 +150,6 @@ #endif #if defined(CONFIG_VIDEO_SW_CURSOR) -#if defined(CONFIG_VIDEO_HW_CURSOR) -#error only one of CONFIG_VIDEO_SW_CURSOR or CONFIG_VIDEO_HW_CURSOR can be \ - defined -#endif void console_cursor(int state); #define CURSOR_ON console_cursor(1) @@ -207,17 +157,6 @@ void console_cursor(int state); #define CURSOR_SET video_set_cursor() #endif /* CONFIG_VIDEO_SW_CURSOR */ -#ifdef CONFIG_VIDEO_HW_CURSOR -#ifdef CURSOR_ON -#error only one of CONFIG_VIDEO_SW_CURSOR or CONFIG_VIDEO_HW_CURSOR can be \ - defined -#endif -#define CURSOR_ON -#define CURSOR_OFF -#define CURSOR_SET video_set_hw_cursor(console_col * VIDEO_FONT_WIDTH, \ - (console_row * VIDEO_FONT_HEIGHT) + video_logo_height) -#endif /* CONFIG_VIDEO_HW_CURSOR */ - #ifdef CONFIG_VIDEO_LOGO #ifdef CONFIG_VIDEO_BMP_LOGO #include <bmp_logo.h> @@ -297,16 +236,6 @@ void console_cursor(int state); #endif #endif -#ifdef CONFIG_CONSOLE_EXTRA_INFO -/* - * setup a board string: type, speed, etc. - * - * line_number: location to place info string beside logo - * info: buffer for info string - */ -extern void video_get_info_str(int line_number, char *info); -#endif - DECLARE_GLOBAL_DATA_PTR; /* Locals */ @@ -885,7 +814,7 @@ static void parse_putc(const char c) CURSOR_SET; } -static void video_putc(struct stdio_dev *dev, const char c) +static void cfb_video_putc(struct stdio_dev *dev, const char c) { #ifdef CONFIG_CFB_CONSOLE_ANSI int i; @@ -1099,7 +1028,7 @@ static void video_putc(struct stdio_dev *dev, const char c) flush_cache(VIDEO_FB_ADRS, VIDEO_SIZE); } -static void video_puts(struct stdio_dev *dev, const char *s) +static void cfb_video_puts(struct stdio_dev *dev, const char *s) { int flush = cfb_do_flush_cache; int count = strlen(s); @@ -1108,7 +1037,7 @@ static void video_puts(struct stdio_dev *dev, const char *s) cfb_do_flush_cache = 0; while (count--) - video_putc(dev, *s++); + cfb_video_putc(dev, *s++); if (flush) { cfb_do_flush_cache = flush; @@ -2075,7 +2004,7 @@ void video_clear(void) #endif } -static int video_init(void) +static int cfg_video_init(void) { unsigned char color8; @@ -2084,79 +2013,78 @@ static int video_init(void) return -1; video_fb_address = (void *) VIDEO_FB_ADRS; -#ifdef CONFIG_VIDEO_HW_CURSOR - video_init_hw_cursor(VIDEO_FONT_WIDTH, VIDEO_FONT_HEIGHT); -#endif cfb_do_flush_cache = cfb_fb_is_in_dram() && dcache_status(); /* Init drawing pats */ switch (VIDEO_DATA_FORMAT) { case GDF__8BIT_INDEX: - video_set_lut(0x01, CONSOLE_FG_COL, CONSOLE_FG_COL, - CONSOLE_FG_COL); - video_set_lut(0x00, CONSOLE_BG_COL, CONSOLE_BG_COL, - CONSOLE_BG_COL); + video_set_lut(0x01, CONFIG_SYS_CONSOLE_FG_COL, + CONFIG_SYS_CONSOLE_FG_COL, + CONFIG_SYS_CONSOLE_FG_COL); + video_set_lut(0x00, CONFIG_SYS_CONSOLE_BG_COL, + CONFIG_SYS_CONSOLE_BG_COL, + CONFIG_SYS_CONSOLE_BG_COL); fgx = 0x01010101; bgx = 0x00000000; break; case GDF__8BIT_332RGB: - color8 = ((CONSOLE_FG_COL & 0xe0) | - ((CONSOLE_FG_COL >> 3) & 0x1c) | - CONSOLE_FG_COL >> 6); + color8 = ((CONFIG_SYS_CONSOLE_FG_COL & 0xe0) | + ((CONFIG_SYS_CONSOLE_FG_COL >> 3) & 0x1c) | + CONFIG_SYS_CONSOLE_FG_COL >> 6); fgx = (color8 << 24) | (color8 << 16) | (color8 << 8) | color8; - color8 = ((CONSOLE_BG_COL & 0xe0) | - ((CONSOLE_BG_COL >> 3) & 0x1c) | - CONSOLE_BG_COL >> 6); + color8 = ((CONFIG_SYS_CONSOLE_BG_COL & 0xe0) | + ((CONFIG_SYS_CONSOLE_BG_COL >> 3) & 0x1c) | + CONFIG_SYS_CONSOLE_BG_COL >> 6); bgx = (color8 << 24) | (color8 << 16) | (color8 << 8) | color8; break; case GDF_15BIT_555RGB: - fgx = (((CONSOLE_FG_COL >> 3) << 26) | - ((CONSOLE_FG_COL >> 3) << 21) | - ((CONSOLE_FG_COL >> 3) << 16) | - ((CONSOLE_FG_COL >> 3) << 10) | - ((CONSOLE_FG_COL >> 3) << 5) | - (CONSOLE_FG_COL >> 3)); - bgx = (((CONSOLE_BG_COL >> 3) << 26) | - ((CONSOLE_BG_COL >> 3) << 21) | - ((CONSOLE_BG_COL >> 3) << 16) | - ((CONSOLE_BG_COL >> 3) << 10) | - ((CONSOLE_BG_COL >> 3) << 5) | - (CONSOLE_BG_COL >> 3)); + fgx = (((CONFIG_SYS_CONSOLE_FG_COL >> 3) << 26) | + ((CONFIG_SYS_CONSOLE_FG_COL >> 3) << 21) | + ((CONFIG_SYS_CONSOLE_FG_COL >> 3) << 16) | + ((CONFIG_SYS_CONSOLE_FG_COL >> 3) << 10) | + ((CONFIG_SYS_CONSOLE_FG_COL >> 3) << 5) | + (CONFIG_SYS_CONSOLE_FG_COL >> 3)); + bgx = (((CONFIG_SYS_CONSOLE_BG_COL >> 3) << 26) | + ((CONFIG_SYS_CONSOLE_BG_COL >> 3) << 21) | + ((CONFIG_SYS_CONSOLE_BG_COL >> 3) << 16) | + ((CONFIG_SYS_CONSOLE_BG_COL >> 3) << 10) | + ((CONFIG_SYS_CONSOLE_BG_COL >> 3) << 5) | + (CONFIG_SYS_CONSOLE_BG_COL >> 3)); break; case GDF_16BIT_565RGB: - fgx = (((CONSOLE_FG_COL >> 3) << 27) | - ((CONSOLE_FG_COL >> 2) << 21) | - ((CONSOLE_FG_COL >> 3) << 16) | - ((CONSOLE_FG_COL >> 3) << 11) | - ((CONSOLE_FG_COL >> 2) << 5) | - (CONSOLE_FG_COL >> 3)); - bgx = (((CONSOLE_BG_COL >> 3) << 27) | - ((CONSOLE_BG_COL >> 2) << 21) | - ((CONSOLE_BG_COL >> 3) << 16) | - ((CONSOLE_BG_COL >> 3) << 11) | - ((CONSOLE_BG_COL >> 2) << 5) | - (CONSOLE_BG_COL >> 3)); + fgx = (((CONFIG_SYS_CONSOLE_FG_COL >> 3) << 27) | + ((CONFIG_SYS_CONSOLE_FG_COL >> 2) << 21) | + ((CONFIG_SYS_CONSOLE_FG_COL >> 3) << 16) | + ((CONFIG_SYS_CONSOLE_FG_COL >> 3) << 11) | + ((CONFIG_SYS_CONSOLE_FG_COL >> 2) << 5) | + (CONFIG_SYS_CONSOLE_FG_COL >> 3)); + bgx = (((CONFIG_SYS_CONSOLE_BG_COL >> 3) << 27) | + ((CONFIG_SYS_CONSOLE_BG_COL >> 2) << 21) | + ((CONFIG_SYS_CONSOLE_BG_COL >> 3) << 16) | + ((CONFIG_SYS_CONSOLE_BG_COL >> 3) << 11) | + ((CONFIG_SYS_CONSOLE_BG_COL >> 2) << 5) | + (CONFIG_SYS_CONSOLE_BG_COL >> 3)); break; case GDF_32BIT_X888RGB: - fgx = (CONSOLE_FG_COL << 16) | - (CONSOLE_FG_COL << 8) | - CONSOLE_FG_COL; - bgx = (CONSOLE_BG_COL << 16) | - (CONSOLE_BG_COL << 8) | - CONSOLE_BG_COL; + fgx = (CONFIG_SYS_CONSOLE_FG_COL << 16) | + (CONFIG_SYS_CONSOLE_FG_COL << 8) | + CONFIG_SYS_CONSOLE_FG_COL; + bgx = (CONFIG_SYS_CONSOLE_BG_COL << 16) | + (CONFIG_SYS_CONSOLE_BG_COL << 8) | + CONFIG_SYS_CONSOLE_BG_COL; break; case GDF_24BIT_888RGB: - fgx = (CONSOLE_FG_COL << 24) | - (CONSOLE_FG_COL << 16) | - (CONSOLE_FG_COL << 8) | - CONSOLE_FG_COL; - bgx = (CONSOLE_BG_COL << 24) | - (CONSOLE_BG_COL << 16) | - (CONSOLE_BG_COL << 8) | - CONSOLE_BG_COL; + fgx = (CONFIG_SYS_CONSOLE_FG_COL << 24) | + (CONFIG_SYS_CONSOLE_FG_COL << 16) | + (CONFIG_SYS_CONSOLE_FG_COL << 8) | + CONFIG_SYS_CONSOLE_FG_COL; + bgx = (CONFIG_SYS_CONSOLE_BG_COL << 24) | + (CONFIG_SYS_CONSOLE_BG_COL << 16) | + (CONFIG_SYS_CONSOLE_BG_COL << 8) | + CONFIG_SYS_CONSOLE_BG_COL; break; } eorx = fgx ^ bgx; @@ -2202,7 +2130,7 @@ int drv_video_init(void) return 0; /* Init video chip - returns with framebuffer cleared */ - if (video_init() == -1) + if (cfg_video_init() == -1) return 0; if (board_cfb_skip()) @@ -2227,8 +2155,8 @@ int drv_video_init(void) memset(&console_dev, 0, sizeof(console_dev)); strcpy(console_dev.name, "vga"); console_dev.flags = DEV_FLAGS_OUTPUT; - console_dev.putc = video_putc; /* 'putc' function */ - console_dev.puts = video_puts; /* 'puts' function */ + console_dev.putc = cfb_video_putc; /* 'putc' function */ + console_dev.puts = cfb_video_puts; /* 'puts' function */ #if !defined(CONFIG_VGA_AS_SINGLE_DEVICE) if (have_keyboard && keyboard_ok) { diff --git a/drivers/video/ct69000.c b/drivers/video/ct69000.c index 22b34418e5..a74e4e6868 100644 --- a/drivers/video/ct69000.c +++ b/drivers/video/ct69000.c @@ -804,84 +804,6 @@ video_dump_reg (void) #endif -#ifdef CONFIG_VIDEO_HW_CURSOR -/*************************************************************** - * Set Hardware Cursor in Pixel - */ -void -video_set_hw_cursor (int x, int y) -{ - int sig_x = 0, sig_y = 0; - if (x < 0) { - x *= -1; - sig_x = 1; - } - if (y < 0) { - y *= -1; - sig_y = 1; - } - ctWrite_i (CT_XR_O, 0xa4, x & 0xff); - ctWrite_i (CT_XR_O, 0xa5, (x >> 8) & 0x7); - ctWrite_i (CT_XR_O, 0xa6, y & 0xff); - ctWrite_i (CT_XR_O, 0xa7, (y >> 8) & 0x7); -} - -/*************************************************************** - * Init Hardware Cursor. To know the size of the Cursor, - * we have to know the Font size. - */ -void -video_init_hw_cursor (int font_width, int font_height) -{ - unsigned char xr_80; - unsigned long *curs, pattern; - int i; - int cursor_start; - GraphicDevice *pGD = (GraphicDevice *) & ctfb; - - cursor_start = pGD->dprBase; - xr_80 = ctRead_i (CT_XR_O, 0x80); - /* set start address */ - ctWrite_i (CT_XR_O, 0xa2, (cursor_start >> 8) & 0xf0); - ctWrite_i (CT_XR_O, 0xa3, (cursor_start >> 16) & 0x3f); - /* set cursor shape */ - curs = (unsigned long *) cursor_start; - i = 0; - while (i < 0x400) { - curs[i++] = 0xffffffff; /* AND mask */ - curs[i++] = 0xffffffff; /* AND mask */ - curs[i++] = 0; /* XOR mask */ - curs[i++] = 0; /* XOR mask */ - /* Transparent */ - } - pattern = 0xffffffff >> font_width; - i = 0; - while (i < (font_height * 2)) { - curs[i++] = pattern; /* AND mask */ - curs[i++] = pattern; /* AND mask */ - curs[i++] = 0; /* XOR mask */ - curs[i++] = 0; /* XOR mask */ - /* Cursor Color 0 */ - } - /* set blink rate */ - ctWrite_i (CT_FP_O, 0x19, 0xf); - - /* set cursors colors */ - xr_80 = ctRead_i (CT_XR_O, 0x80); - xr_80 |= 0x1; /* alternate palette select */ - ctWrite_i (CT_XR_O, 0x80, xr_80); - video_set_lut (4, CONSOLE_FG_COL, CONSOLE_FG_COL, CONSOLE_FG_COL); - /* position 4 is color 0 cursor 0 */ - xr_80 &= 0xfe; /* normal palette select */ - ctWrite_i (CT_XR_O, 0x80, xr_80); - /* cursor enable */ - ctWrite_i (CT_XR_O, 0xa0, 0x91); - xr_80 |= 0x10; /* enable hwcursor */ - ctWrite_i (CT_XR_O, 0x80, xr_80); - video_set_hw_cursor (0, 0); -} -#endif /* CONFIG_VIDEO_HW_CURSOR */ - /*************************************************************** * Wait for BitBlt ready */ diff --git a/drivers/video/imx25lcdc.c b/drivers/video/imx25lcdc.c deleted file mode 100644 index ef5767baed..0000000000 --- a/drivers/video/imx25lcdc.c +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2011 - * Matthias Weisser <weisserm@arcor.de> - * - * SPDX-License-Identifier: GPL-2.0+ - * - * imx25lcdc.c - Graphic interface for i.MX25 lcd controller - */ - -#include <common.h> - -#include <malloc.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <video_fb.h> -#include "videomodes.h" - -/* - * 4MB (at the end of system RAM) - */ -#define VIDEO_MEM_SIZE 0x400000 - -#define FB_SYNC_CLK_INV (1<<16) /* pixel clock inverted */ - -/* - * Graphic Device - */ -static GraphicDevice imx25fb; - -void *video_hw_init(void) -{ - struct lcdc_regs *lcdc = (struct lcdc_regs *)IMX_LCDC_BASE; - struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE; - GraphicDevice *pGD = &imx25fb; - char *s; - u32 *videomem; - - memset(pGD, 0, sizeof(GraphicDevice)); - - pGD->gdfIndex = GDF_16BIT_565RGB; - pGD->gdfBytesPP = 2; - pGD->memSize = VIDEO_MEM_SIZE; - pGD->frameAdrs = PHYS_SDRAM + PHYS_SDRAM_SIZE - VIDEO_MEM_SIZE; - - videomem = (u32 *)pGD->frameAdrs; - - s = getenv("videomode"); - if (s != NULL) { - struct ctfb_res_modes var_mode; - u32 lsr, lpcr, lhcr, lvcr; - unsigned long div; - int bpp; - - /* Disable all clocks of the LCDC */ - writel(readl(&ccm->cgr0) & ~((1<<7) | (1<<24)), &ccm->cgr0); - writel(readl(&ccm->cgr1) & ~(1<<29), &ccm->cgr1); - - bpp = video_get_params(&var_mode, s); - - if (bpp == 0) { - var_mode.xres = 320; - var_mode.yres = 240; - var_mode.pixclock = 154000; - var_mode.left_margin = 68; - var_mode.right_margin = 20; - var_mode.upper_margin = 4; - var_mode.lower_margin = 18; - var_mode.hsync_len = 40; - var_mode.vsync_len = 6; - var_mode.sync = 0; - var_mode.vmode = 0; - } - - /* Fill memory with white */ - memset(videomem, 0xFF, var_mode.xres * var_mode.yres * 2); - - imx25fb.winSizeX = var_mode.xres; - imx25fb.winSizeY = var_mode.yres; - - /* LCD base clock is 66.6MHZ. We do calculations in kHz */ - div = 66000 / (1000000000L / var_mode.pixclock); - if (div > 63) - div = 63; - if (0 == div) - div = 1; - - lsr = ((var_mode.xres / 16) << 20) | - var_mode.yres; - lpcr = (1 << 31) | - (1 << 30) | - (5 << 25) | - (1 << 23) | - (1 << 22) | - (1 << 19) | - (1 << 7) | - div; - lhcr = (var_mode.right_margin << 0) | - (var_mode.left_margin << 8) | - (var_mode.hsync_len << 26); - - lvcr = (var_mode.lower_margin << 0) | - (var_mode.upper_margin << 8) | - (var_mode.vsync_len << 26); - - writel((uint32_t)videomem, &lcdc->lssar); - writel(lsr, &lcdc->lsr); - writel(var_mode.xres * 2 / 4, &lcdc->lvpwr); - writel(lpcr, &lcdc->lpcr); - writel(lhcr, &lcdc->lhcr); - writel(lvcr, &lcdc->lvcr); - writel(0x00040060, &lcdc->ldcr); - - writel(0xA90300, &lcdc->lpccr); - - /* Ensable all clocks of the LCDC */ - writel(readl(&ccm->cgr0) | ((1<<7) | (1<<24)), &ccm->cgr0); - writel(readl(&ccm->cgr1) | (1<<29), &ccm->cgr1); - } - - return pGD; -} diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c deleted file mode 100644 index bea3e69dd3..0000000000 --- a/drivers/video/s3c-fb.c +++ /dev/null @@ -1,172 +0,0 @@ -/* - * S3C24x0 LCD driver - * - * NOTE: Only 16/24 bpp operation with TFT LCD is supported. - * - * Copyright (C) 2014 Marek Vasut <marex@denx.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include <common.h> -#include <malloc.h> -#include <video_fb.h> - -#include <linux/errno.h> -#include <asm/io.h> -#include <asm/arch/s3c24x0_cpu.h> - -#include "videomodes.h" - -static GraphicDevice panel; - -/* S3C requires the FB to be 4MiB aligned. */ -#define S3CFB_ALIGN (4 << 20) - -#define S3CFB_LCDCON1_CLKVAL(x) ((x) << 8) -#define S3CFB_LCDCON1_PNRMODE_TFT (0x3 << 5) -#define S3CFB_LCDCON1_BPPMODE_TFT_16BPP (0xc << 1) -#define S3CFB_LCDCON1_BPPMODE_TFT_24BPP (0xd << 1) - -#define S3CFB_LCDCON2_VBPD(x) ((x) << 24) -#define S3CFB_LCDCON2_LINEVAL(x) ((x) << 14) -#define S3CFB_LCDCON2_VFPD(x) ((x) << 6) -#define S3CFB_LCDCON2_VSPW(x) ((x) << 0) - -#define S3CFB_LCDCON3_HBPD(x) ((x) << 19) -#define S3CFB_LCDCON3_HOZVAL(x) ((x) << 8) -#define S3CFB_LCDCON3_HFPD(x) ((x) << 0) - -#define S3CFB_LCDCON4_HSPW(x) ((x) << 0) - -#define S3CFB_LCDCON5_BPP24BL (1 << 12) -#define S3CFB_LCDCON5_FRM565 (1 << 11) -#define S3CFB_LCDCON5_HWSWP (1 << 0) - -#define PS2KHZ(ps) (1000000000UL / (ps)) - -/* - * Example: - * setenv videomode video=ctfb:x:800,y:480,depth:16,mode:0,\ - * pclk:30066,le:41,ri:89,up:45,lo:12, - * hs:1,vs:1,sync:100663296,vmode:0 - */ -static void s3c_lcd_init(GraphicDevice *panel, - struct ctfb_res_modes *mode, int bpp) -{ - uint32_t clk_divider; - struct s3c24x0_lcd *regs = s3c24x0_get_base_lcd(); - - /* Stop the controller. */ - clrbits_le32(®s->lcdcon1, 1); - - /* Calculate clock divider. */ - clk_divider = (get_HCLK() / PS2KHZ(mode->pixclock)) / 1000; - clk_divider = DIV_ROUND_UP(clk_divider, 2); - if (clk_divider) - clk_divider -= 1; - - /* Program LCD configuration. */ - switch (bpp) { - case 16: - writel(S3CFB_LCDCON1_BPPMODE_TFT_16BPP | - S3CFB_LCDCON1_PNRMODE_TFT | - S3CFB_LCDCON1_CLKVAL(clk_divider), - ®s->lcdcon1); - writel(S3CFB_LCDCON5_HWSWP | S3CFB_LCDCON5_FRM565, - ®s->lcdcon5); - break; - case 24: - writel(S3CFB_LCDCON1_BPPMODE_TFT_24BPP | - S3CFB_LCDCON1_PNRMODE_TFT | - S3CFB_LCDCON1_CLKVAL(clk_divider), - ®s->lcdcon1); - writel(S3CFB_LCDCON5_BPP24BL, ®s->lcdcon5); - break; - } - - writel(S3CFB_LCDCON2_LINEVAL(mode->yres - 1) | - S3CFB_LCDCON2_VBPD(mode->upper_margin - 1) | - S3CFB_LCDCON2_VFPD(mode->lower_margin - 1) | - S3CFB_LCDCON2_VSPW(mode->vsync_len - 1), - ®s->lcdcon2); - - writel(S3CFB_LCDCON3_HBPD(mode->right_margin - 1) | - S3CFB_LCDCON3_HFPD(mode->left_margin - 1) | - S3CFB_LCDCON3_HOZVAL(mode->xres - 1), - ®s->lcdcon3); - - writel(S3CFB_LCDCON4_HSPW(mode->hsync_len - 1), - ®s->lcdcon4); - - /* Write FB address. */ - writel(panel->frameAdrs >> 1, ®s->lcdsaddr1); - writel((panel->frameAdrs + - (mode->xres * mode->yres * panel->gdfBytesPP)) >> 1, - ®s->lcdsaddr2); - writel(mode->xres * bpp / 16, ®s->lcdsaddr3); - - /* Start the controller. */ - setbits_le32(®s->lcdcon1, 1); -} - -void *video_hw_init(void) -{ - int bpp = -1; - char *penv; - void *fb; - struct ctfb_res_modes mode; - - puts("Video: "); - - /* Suck display configuration from "videomode" variable */ - penv = getenv("videomode"); - if (!penv) { - puts("S3CFB: 'videomode' variable not set!\n"); - return NULL; - } - - bpp = video_get_params(&mode, penv); - - /* fill in Graphic device struct */ - sprintf(panel.modeIdent, "%dx%dx%d", mode.xres, mode.yres, bpp); - - panel.winSizeX = mode.xres; - panel.winSizeY = mode.yres; - panel.plnSizeX = mode.xres; - panel.plnSizeY = mode.yres; - - switch (bpp) { - case 24: - panel.gdfBytesPP = 4; - panel.gdfIndex = GDF_32BIT_X888RGB; - break; - case 16: - panel.gdfBytesPP = 2; - panel.gdfIndex = GDF_16BIT_565RGB; - break; - default: - printf("S3CFB: Invalid BPP specified! (bpp = %i)\n", bpp); - return NULL; - } - - panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP; - - /* Allocate framebuffer */ - fb = memalign(S3CFB_ALIGN, roundup(panel.memSize, S3CFB_ALIGN)); - if (!fb) { - printf("S3CFB: Error allocating framebuffer!\n"); - return NULL; - } - - /* Wipe framebuffer */ - memset(fb, 0, panel.memSize); - - panel.frameAdrs = (u32)fb; - - printf("%s\n", panel.modeIdent); - - /* Start framebuffer */ - s3c_lcd_init(&panel, &mode, bpp); - - return (void *)&panel; -} diff --git a/drivers/video/sed13806.c b/drivers/video/sed13806.c deleted file mode 100644 index cd7fac6f97..0000000000 --- a/drivers/video/sed13806.c +++ /dev/null @@ -1,286 +0,0 @@ -/* - * (C) Copyright 2002 - * Stäubli Faverges - <www.staubli.com> - * Pierre AUBERT p.aubert@staubli.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ -/* Video support for Epson SED13806 chipset */ - -#include <common.h> - -#include <video_fb.h> -#include <sed13806.h> - -#define readByte(ptrReg) \ - *(volatile unsigned char *)(sed13806.isaBase + ptrReg) - -#define writeByte(ptrReg,value) \ - *(volatile unsigned char *)(sed13806.isaBase + ptrReg) = value - -#define writeWord(ptrReg,value) \ - (*(volatile unsigned short *)(sed13806.isaBase + ptrReg) = ((value >> 8 ) & 0xff) | ((value << 8) & 0xff00)) - -GraphicDevice sed13806; - -/*----------------------------------------------------------------------------- - * EpsonSetRegs -- - *----------------------------------------------------------------------------- - */ -static void EpsonSetRegs (void) -{ - /* the content of the chipset register depends on the board (clocks, ...)*/ - const S1D_REGS *preg = board_get_regs (); - while (preg -> Index) { - writeByte (preg -> Index, preg -> Value); - preg ++; - } -} - -/*----------------------------------------------------------------------------- - * video_hw_init -- - *----------------------------------------------------------------------------- - */ -void *video_hw_init (void) -{ - unsigned int *vm, i; - - memset (&sed13806, 0, sizeof (GraphicDevice)); - - /* Initialization of the access to the graphic chipset - Retreive base address of the chipset - (see board/RPXClassic/eccx.c) */ - if ((sed13806.isaBase = board_video_init ()) == 0) { - return (NULL); - } - - sed13806.frameAdrs = sed13806.isaBase + FRAME_BUFFER_OFFSET; - sed13806.winSizeX = board_get_width (); - sed13806.winSizeY = board_get_height (); - -#if defined(CONFIG_VIDEO_SED13806_8BPP) - sed13806.gdfIndex = GDF__8BIT_INDEX; - sed13806.gdfBytesPP = 1; - -#elif defined(CONFIG_VIDEO_SED13806_16BPP) - sed13806.gdfIndex = GDF_16BIT_565RGB; - sed13806.gdfBytesPP = 2; - -#else -#error Unsupported SED13806 BPP -#endif - - sed13806.memSize = sed13806.winSizeX * sed13806.winSizeY * sed13806.gdfBytesPP; - - /* Load SED registers */ - EpsonSetRegs (); - - /* (see board/RPXClassic/RPXClassic.c) */ - board_validate_screen (sed13806.isaBase); - - /* Clear video memory */ - i = sed13806.memSize/4; - vm = (unsigned int *)sed13806.frameAdrs; - while(i--) - *vm++ = 0; - - - return (&sed13806); -} -/*----------------------------------------------------------------------------- - * Epson_wait_idle -- Wait for hardware to become idle - *----------------------------------------------------------------------------- - */ -static void Epson_wait_idle (void) -{ - while (readByte (BLT_CTRL0) & 0x80); - - /* Read a word in the BitBLT memory area to shutdown the BitBLT engine */ - *(volatile unsigned short *)(sed13806.isaBase + BLT_REG); -} - -/*----------------------------------------------------------------------------- - * video_hw_bitblt -- - *----------------------------------------------------------------------------- - */ -void video_hw_bitblt ( - unsigned int bpp, /* bytes per pixel */ - unsigned int src_x, /* source pos x */ - unsigned int src_y, /* source pos y */ - unsigned int dst_x, /* dest pos x */ - unsigned int dst_y, /* dest pos y */ - unsigned int dim_x, /* frame width */ - unsigned int dim_y /* frame height */ - ) -{ - register GraphicDevice *pGD = (GraphicDevice *)&sed13806; - unsigned long srcAddr, dstAddr; - unsigned int stride = bpp * pGD -> winSizeX; - - srcAddr = (src_y * stride) + (src_x * bpp); - dstAddr = (dst_y * stride) + (dst_x * bpp); - - Epson_wait_idle (); - - writeByte(BLT_ROP,0x0C); /* source */ - writeByte(BLT_OP,0x02);/* move blit in positive direction with ROP */ - writeWord(BLT_MEM_OFF0, stride / 2); - if (pGD -> gdfIndex == GDF__8BIT_INDEX) { - writeByte(BLT_CTRL1,0x00); - } - else { - writeByte(BLT_CTRL1,0x01); - } - - writeWord(BLT_WIDTH0,(dim_x - 1)); - writeWord(BLT_HEIGHT0,(dim_y - 1)); - - /* set up blit registers */ - writeByte(BLT_SRC_ADDR0,srcAddr); - writeByte(BLT_SRC_ADDR1,srcAddr>>8); - writeByte(BLT_SRC_ADDR2,srcAddr>>16); - - writeByte(BLT_DST_ADDR0,dstAddr); - writeByte(BLT_DST_ADDR1,dstAddr>>8); - writeByte(BLT_DST_ADDR2,dstAddr>>16); - - /* Engage the blt engine */ - /* rectangular region for src and dst */ - writeByte(BLT_CTRL0,0x80); - - /* wait untill current blits finished */ - Epson_wait_idle (); -} -/*----------------------------------------------------------------------------- - * video_hw_rectfill -- - *----------------------------------------------------------------------------- - */ -void video_hw_rectfill ( - unsigned int bpp, /* bytes per pixel */ - unsigned int dst_x, /* dest pos x */ - unsigned int dst_y, /* dest pos y */ - unsigned int dim_x, /* frame width */ - unsigned int dim_y, /* frame height */ - unsigned int color /* fill color */ - ) -{ - register GraphicDevice *pGD = (GraphicDevice *)&sed13806; - unsigned long dstAddr; - unsigned int stride = bpp * pGD -> winSizeX; - - dstAddr = (dst_y * stride) + (dst_x * bpp); - - Epson_wait_idle (); - - /* set up blit registers */ - writeByte(BLT_DST_ADDR0,dstAddr); - writeByte(BLT_DST_ADDR1,dstAddr>>8); - writeByte(BLT_DST_ADDR2,dstAddr>>16); - - writeWord(BLT_WIDTH0,(dim_x - 1)); - writeWord(BLT_HEIGHT0,(dim_y - 1)); - writeWord(BLT_FGCOLOR0,color); - - writeByte(BLT_OP,0x0C); /* solid fill */ - writeWord(BLT_MEM_OFF0,stride / 2); - - if (pGD -> gdfIndex == GDF__8BIT_INDEX) { - writeByte(BLT_CTRL1,0x00); - } - else { - writeByte(BLT_CTRL1,0x01); - } - - /* Engage the blt engine */ - /* rectangular region for src and dst */ - writeByte(BLT_CTRL0,0x80); - - /* wait untill current blits finished */ - Epson_wait_idle (); -} - -/*----------------------------------------------------------------------------- - * video_set_lut -- - *----------------------------------------------------------------------------- - */ -void video_set_lut ( - unsigned int index, /* color number */ - unsigned char r, /* red */ - unsigned char g, /* green */ - unsigned char b /* blue */ - ) -{ - writeByte(REG_LUT_ADDR, index ); - writeByte(REG_LUT_DATA, r); - writeByte(REG_LUT_DATA, g); - writeByte(REG_LUT_DATA, b); -} -#ifdef CONFIG_VIDEO_HW_CURSOR -/*----------------------------------------------------------------------------- - * video_set_hw_cursor -- - *----------------------------------------------------------------------------- - */ -void video_set_hw_cursor (int x, int y) -{ - writeByte (LCD_CURSOR_XL, (x & 0xff)); - writeByte (LCD_CURSOR_XM, (x >> 8)); - writeByte (LCD_CURSOR_YL, (y & 0xff)); - writeByte (LCD_CURSOR_YM, (y >> 8)); -} - -/*----------------------------------------------------------------------------- - * video_init_hw_cursor -- - *----------------------------------------------------------------------------- - */ -void video_init_hw_cursor (int font_width, int font_height) -{ - volatile unsigned char *ptr; - unsigned char pattern; - int i; - - - /* Init cursor content - Cursor size is 64x64 pixels - Start of the cursor memory depends on panel type (dual panel ...) */ - if ((i = readByte (LCD_CURSOR_START)) == 0) { - ptr = (unsigned char *)(sed13806.frameAdrs + DEFAULT_VIDEO_MEMORY_SIZE - HWCURSORSIZE); - } - else { - ptr = (unsigned char *)(sed13806.frameAdrs + DEFAULT_VIDEO_MEMORY_SIZE - (i * 8192)); - } - - /* Fill the first line and the first empty line after cursor */ - for (i = 0, pattern = 0; i < 64; i++) { - if (i < font_width) { - /* Invert background */ - pattern |= 0x3; - - } - else { - /* Background */ - pattern |= 0x2; - } - if ((i & 3) == 3) { - *ptr = pattern; - *(ptr + font_height * 16) = 0xaa; - ptr ++; - pattern = 0; - } - pattern <<= 2; - } - - /* Duplicate this line */ - for (i = 1; i < font_height; i++) { - memcpy ((void *)ptr, (void *)(ptr - 16), 16); - ptr += 16; - } - - for (; i < 64; i++) { - memcpy ((void *)(ptr + 16), (void *)ptr, 16); - ptr += 16; - } - - /* Select cursor mode */ - writeByte (LCD_CURSOR_CNTL, 1); -} -#endif diff --git a/drivers/video/smiLynxEM.c b/drivers/video/smiLynxEM.c deleted file mode 100644 index 1880cccac2..0000000000 --- a/drivers/video/smiLynxEM.c +++ /dev/null @@ -1,835 +0,0 @@ -/* - * (C) Copyright 1997-2002 ELTEC Elektronik AG - * Frank Gottschling <fgottschling@eltec.de> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * smiLynxEM.c - * - * Silicon Motion graphic interface for sm810/sm710/sm712 accelerator - * - * modification history - * -------------------- - * 04-18-2002 Rewritten for U-Boot <fgottschling@eltec.de>. - * - * 18-03-2004 - Unify videomodes handling with the ct69000 - * - The video output can be set via the variable "videoout" - * in the environment. - * videoout=1 output on LCD - * videoout=2 output on CRT (default value) - * <p.aubert@staubli.com> - */ - -#include <common.h> - -#include <pci.h> -#include <video_fb.h> -#include "videomodes.h" -/* - * Export Graphic Device - */ -GraphicDevice smi; - -/* - * SMI 710/712 have 4MB internal RAM; SMI 810 2MB internal + 2MB external - */ -#define VIDEO_MEM_SIZE 0x400000 - - -/* - * ISA mapped regs - */ -#define SMI_INDX_C4 (pGD->isaBase + 0x03c4) /* index reg */ -#define SMI_DATA_C5 (pGD->isaBase + 0x03c5) /* data reg */ -#define SMI_INDX_D4 (pGD->isaBase + 0x03d4) /* index reg */ -#define SMI_DATA_D5 (pGD->isaBase + 0x03d5) /* data reg */ -#define SMI_ISR1 (pGD->isaBase + 0x03ca) -#define SMI_INDX_CE (pGD->isaBase + 0x03ce) /* index reg */ -#define SMI_DATA_CF (pGD->isaBase + 0x03cf) /* data reg */ -#define SMI_LOCK_REG (pGD->isaBase + 0x03c3) /* unlock/lock ext crt reg */ -#define SMI_MISC_REG (pGD->isaBase + 0x03c2) /* misc reg */ -#define SMI_LUT_MASK (pGD->isaBase + 0x03c6) /* lut mask reg */ -#define SMI_LUT_START (pGD->isaBase + 0x03c8) /* lut start index */ -#define SMI_LUT_RGB (pGD->isaBase + 0x03c9) /* lut colors auto incr.*/ -#define SMI_INDX_ATTR (pGD->isaBase + 0x03c0) /* attributes index reg */ - -/* - * Video processor control - */ -typedef struct { - unsigned int control; - unsigned int colorKey; - unsigned int colorKeyMask; - unsigned int start; - unsigned short offset; - unsigned short width; - unsigned int fifoPrio; - unsigned int fifoERL; - unsigned int YUVtoRGB; -} SmiVideoProc; - -/* - * Video window control - */ -typedef struct { - unsigned short top; - unsigned short left; - unsigned short bottom; - unsigned short right; - unsigned int srcStart; - unsigned short width; - unsigned short offset; - unsigned char hStretch; - unsigned char vStretch; -} SmiVideoWin; - -/* - * Capture port control - */ -typedef struct { - unsigned int control; - unsigned short topClip; - unsigned short leftClip; - unsigned short srcHeight; - unsigned short srcWidth; - unsigned int srcBufStart1; - unsigned int srcBufStart2; - unsigned short srcOffset; - unsigned short fifoControl; -} SmiCapturePort; - - -/* - * Register values for common video modes - */ -static char SMI_SCR[] = { - /* all modes */ - 0x10, 0xff, 0x11, 0xff, 0x12, 0xff, 0x13, 0xff, 0x15, 0x90, - 0x17, 0x20, 0x18, 0xb1, 0x19, 0x00, -}; -static char SMI_EXT_CRT[] = { - 0x31, 0x00, 0x32, 0x00, 0x33, 0x00, 0x34, 0x00, 0x35, 0x00, - 0x36, 0x00, 0x3b, 0x00, 0x3c, 0x00, 0x3d, 0x00, 0x3e, 0x00, 0x3f, 0x00, -}; -static char SMI_ATTR [] = { - 0x00, 0x00, 0x01, 0x01, 0x02, 0x02, 0x03, 0x03, 0x04, 0x04, 0x05, 0x05, - 0x06, 0x06, 0x07, 0x07, 0x08, 0x08, 0x09, 0x09, 0x0a, 0x0a, 0x0b, 0x0b, - 0x0c, 0x0c, 0x0d, 0x0d, 0x0e, 0x0e, 0x0f, 0x0f, 0x10, 0x41, 0x11, 0x00, - 0x12, 0x0f, 0x13, 0x00, 0x14, 0x00, -}; -static char SMI_GCR[18] = { - 0x00, 0x00, 0x01, 0x00, 0x02, 0x00, 0x03, 0x00, 0x04, 0x00, 0x05, 0x40, - 0x06, 0x05, 0x07, 0x0f, 0x08, 0xff, -}; -static char SMI_SEQR[] = { - 0x00, 0x00, 0x01, 0x01, 0x02, 0x0f, 0x03, 0x03, 0x04, 0x0e, 0x00, 0x03, -}; -static char SMI_PCR [] = { - 0x20, 0x04, 0x21, 0x30, 0x22, 0x00, 0x23, 0x00, 0x24, 0x00, -}; -static char SMI_MCR[] = { - 0x60, 0x01, 0x61, 0x00, -}; - -static char SMI_HCR[] = { - 0x80, 0xff, 0x81, 0x07, 0x82, 0x00, 0x83, 0xff, 0x84, 0xff, 0x88, 0x00, - 0x89, 0x02, 0x8a, 0x80, 0x8b, 0x01, 0x8c, 0xff, 0x8d, 0x00, -}; - - -/******************************************************************************* - * - * Write SMI ISA register - */ -static void smiWrite (unsigned short index, char reg, char val) -{ - register GraphicDevice *pGD = (GraphicDevice *)&smi; - - out8 ((pGD->isaBase + index), reg); - out8 ((pGD->isaBase + index + 1), val); -} - -/******************************************************************************* - * - * Write a table of SMI ISA register - */ -static void smiLoadRegs ( - unsigned int iReg, - unsigned int dReg, - char *regTab, - unsigned int tabSize - ) -{ - register GraphicDevice *pGD = (GraphicDevice *)&smi; - register int i; - - for (i=0; i<tabSize; i+=2) { - if (iReg == SMI_INDX_ATTR) { - /* Reset the Flip Flop */ - in8 (SMI_ISR1); - out8 (iReg, regTab[i]); - out8 (iReg, regTab[i+1]); - } else { - out8 (iReg, regTab[i]); - out8 (dReg, regTab[i+1]); - } - } -} - -/******************************************************************************* - * - * Init capture port registers - */ -static void smiInitCapturePort (void) -{ - SmiCapturePort smiCP = { 0x01400600, 0x30, 0x40, 480, 640, 0, 0, 2560, 6 }; - register GraphicDevice *pGD = (GraphicDevice *)&smi; - register SmiCapturePort *pCP = (SmiCapturePort *)&smiCP; - - out32r ((pGD->cprBase + 0x0004), ((pCP->topClip<<16) | pCP->leftClip)); - out32r ((pGD->cprBase + 0x0008), ((pCP->srcHeight<<16) | pCP->srcWidth)); - out32r ((pGD->cprBase + 0x000c), pCP->srcBufStart1/8); - out32r ((pGD->cprBase + 0x0010), pCP->srcBufStart2/8); - out32r ((pGD->cprBase + 0x0014), pCP->srcOffset/8); - out32r ((pGD->cprBase + 0x0018), pCP->fifoControl); - out32r ((pGD->cprBase + 0x0000), pCP->control); -} - - -/******************************************************************************* - * - * Init video processor registers - */ -static void smiInitVideoProcessor (void) -{ - SmiVideoProc smiVP = { 0x100000, 0, 0, 0, 0, 1600, 0x1200543, 4, 0xededed }; - SmiVideoWin smiVW = { 0, 0, 599, 799, 0, 1600, 0, 0, 0 }; - register GraphicDevice *pGD = (GraphicDevice *)&smi; - register SmiVideoProc *pVP = (SmiVideoProc *)&smiVP; - register SmiVideoWin *pVWin = (SmiVideoWin *)&smiVW; - - pVP->width = pGD->plnSizeX * pGD->gdfBytesPP; - pVP->control |= pGD->gdfIndex << 16; - pVWin->bottom = pGD->winSizeY - 1; - pVWin->right = pGD->winSizeX - 1; - pVWin->width = pVP->width; - - /* color key */ - out32r ((pGD->vprBase + 0x0004), pVP->colorKey); - - /* color key mask */ - out32r ((pGD->vprBase + 0x0008), pVP->colorKeyMask); - - /* data src start adrs */ - out32r ((pGD->vprBase + 0x000c), pVP->start / 8); - - /* data width and offset */ - out32r ((pGD->vprBase + 0x0010), - ((pVP->offset / 8 * pGD->gdfBytesPP) << 16) | - (pGD->plnSizeX / 8 * pGD->gdfBytesPP)); - - /* video window 1 */ - out32r ((pGD->vprBase + 0x0014), - ((pVWin->top << 16) | pVWin->left)); - - out32r ((pGD->vprBase + 0x0018), - ((pVWin->bottom << 16) | pVWin->right)); - - out32r ((pGD->vprBase + 0x001c), pVWin->srcStart / 8); - - out32r ((pGD->vprBase + 0x0020), - (((pVWin->offset / 8) << 16) | (pVWin->width / 8))); - - out32r ((pGD->vprBase + 0x0024), - (((pVWin->hStretch) << 8) | pVWin->vStretch)); - - /* video window 2 */ - out32r ((pGD->vprBase + 0x0028), - ((pVWin->top << 16) | pVWin->left)); - - out32r ((pGD->vprBase + 0x002c), - ((pVWin->bottom << 16) | pVWin->right)); - - out32r ((pGD->vprBase + 0x0030), - pVWin->srcStart / 8); - - out32r ((pGD->vprBase + 0x0034), - (((pVWin->offset / 8) << 16) | (pVWin->width / 8))); - - out32r ((pGD->vprBase + 0x0038), - (((pVWin->hStretch) << 8) | pVWin->vStretch)); - - /* fifo prio control */ - out32r ((pGD->vprBase + 0x0054), pVP->fifoPrio); - - /* fifo empty request levell */ - out32r ((pGD->vprBase + 0x0058), pVP->fifoERL); - - /* conversion constant */ - out32r ((pGD->vprBase + 0x005c), pVP->YUVtoRGB); - - /* vpr control word */ - out32r ((pGD->vprBase + 0x0000), pVP->control); -} - -/****************************************************************************** - * - * Init drawing engine registers - */ -static void smiInitDrawingEngine (void) -{ - GraphicDevice *pGD = (GraphicDevice *)&smi; - unsigned int val; - - /* don't start now */ - out32r ((pGD->dprBase + 0x000c), 0x000f0000); - - /* set rop2 to copypen */ - val = 0xffff3ff0 & in32r ((pGD->dprBase + 0x000c)); - out32r ((pGD->dprBase + 0x000c), (val | 0x8000 | 0x0c)); - - /* set clip rect */ - out32r ((pGD->dprBase + 0x002c), 0); - out32r ((pGD->dprBase + 0x0030), - ((pGD->winSizeY<<16) | pGD->winSizeX * pGD->gdfBytesPP )); - - /* src row pitch */ - val = 0xffff0000 & (in32r ((pGD->dprBase + 0x0010))); - out32r ((pGD->dprBase + 0x0010), - (val | pGD->plnSizeX * pGD->gdfBytesPP)); - - /* dst row pitch */ - val = 0x0000ffff & (in32r ((pGD->dprBase + 0x0010))); - out32r ((pGD->dprBase + 0x0010), - (((pGD->plnSizeX * pGD->gdfBytesPP)<<16) | val)); - - /* window width src/dst */ - out32r ((pGD->dprBase + 0x003c), - (((pGD->plnSizeX * pGD->gdfBytesPP & 0x0fff)<<16) | - (pGD->plnSizeX * pGD->gdfBytesPP & 0x0fff))); - out16r ((pGD->dprBase + 0x001e), 0x0000); - - /* src base adrs */ - out32r ((pGD->dprBase + 0x0040), - (((pGD->frameAdrs/8) & 0x000fffff))); - - /* dst base adrs */ - out32r ((pGD->dprBase + 0x0044), - (((pGD->frameAdrs/8) & 0x000fffff))); - - /* foreground color */ - out32r ((pGD->dprBase + 0x0014), pGD->fg); - - /* background color */ - out32r ((pGD->dprBase + 0x0018), pGD->bg); - - /* xcolor */ - out32r ((pGD->dprBase + 0x0020), 0x00ffffff); - - /* xcolor mask */ - out32r ((pGD->dprBase + 0x0024), 0x00ffffff); - - /* bit mask */ - out32r ((pGD->dprBase + 0x0028), 0x00ffffff); - - /* load mono pattern */ - out32r ((pGD->dprBase + 0x0034), 0); - out32r ((pGD->dprBase + 0x0038), 0); -} - -static struct pci_device_id supported[] = { - { PCI_VENDOR_ID_SMI, PCI_DEVICE_ID_SMI_710 }, - { PCI_VENDOR_ID_SMI, PCI_DEVICE_ID_SMI_712 }, - { PCI_VENDOR_ID_SMI, PCI_DEVICE_ID_SMI_810 }, - { } -}; - -/*****************************************************************************/ -static void smiLoadMsr (struct ctfb_res_modes *mode) -{ - unsigned char h_synch_high, v_synch_high; - register GraphicDevice *pGD = (GraphicDevice *)&smi; - - h_synch_high = (mode->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 0x40; /* horizontal Synch High active */ - v_synch_high = (mode->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 0x80; /* vertical Synch High active */ - out8 (SMI_MISC_REG, (h_synch_high | v_synch_high | 0x29)); - /* upper64K==0x20, CLC2select==0x08, RAMenable==0x02!(todo), CGA==0x01 - * Selects the upper 64KB page.Bit5=1 - * CLK2 (left reserved in standard VGA) Bit3|2=1|0 - * Disables CPU access to frame buffer. Bit1=0 - * Sets the I/O address decode for ST01, FCR, and all CR registers - * to the 3Dx I/O address range (CGA emulation). Bit0=1 - */ -} -/*****************************************************************************/ -static void smiLoadCrt (struct ctfb_res_modes *var, int bits_per_pixel) -{ - unsigned char cr[0x7a]; - int i; - unsigned int hd, hs, he, ht, hbs, hbe; /* Horizontal. */ - unsigned int vd, vs, ve, vt, vbs, vbe; /* vertical */ - unsigned int bpp, wd, dblscan, interlaced; - - const int LineCompare = 0x3ff; - unsigned int TextScanLines = 1; /* this is in fact a vertical zoom factor */ - register GraphicDevice *pGD = (GraphicDevice *)&smi; - - /* Horizontal */ - hd = (var->xres) / 8; /* HDisp. */ - hs = (var->xres + var->right_margin) / 8; /* HsStrt */ - he = (var->xres + var->right_margin + var->hsync_len) / 8; /* HsEnd */ - ht = (var->left_margin + var->xres + var->right_margin + var->hsync_len) / 8; /* HTotal */ - /* Blank */ - hbs = hd; - hbe = 0; /* Blank end at 0 */ - - /* Vertical */ - vd = var->yres; /* VDisplay */ - vs = var->yres + var->lower_margin; /* VSyncStart */ - ve = var->yres + var->lower_margin + var->vsync_len; /* VSyncEnd */ - vt = var->upper_margin + var->yres + var->lower_margin + var->vsync_len; /* VTotal */ - vbs = vd; - vbe = 0; - - bpp = bits_per_pixel; - dblscan = (var->vmode & FB_VMODE_DOUBLE) ? 1 : 0; - interlaced = var->vmode & FB_VMODE_INTERLACED; - - - if (bpp == 15) - bpp = 16; - wd = var->xres * bpp / 64; /* double words per line */ - if (interlaced) { /* we divide all vertical timings, exept vd */ - vs >>= 1; - vbs >>= 1; - ve >>= 1; - vt >>= 1; - } - - memset (cr, 0, sizeof (cr)); - cr[0x00] = ht - 5; - cr[0x01] = hd - 1; - cr[0x02] = hbs - 1; - cr[0x03] = (hbe & 0x1F); - cr[0x04] = hs; - cr[0x05] = ((hbe & 0x20) << 2) | (he & 0x1f); - - cr[0x06] = (vt - 2) & 0xFF; - cr[0x07] = (((vt - 2) & 0x100) >> 8) - | (((vd - 1) & 0x100) >> 7) - | ((vs & 0x100) >> 6) - | (((vbs - 1) & 0x100) >> 5) - | ((LineCompare & 0x100) >> 4) - | (((vt - 2) & 0x200) >> 4) - | (((vd - 1) & 0x200) >> 3) - | ((vs & 0x200) >> 2); - - cr[0x30] = ((vt - 2) & 0x400) >> 7 - | (((vd - 1) & 0x400) >> 8) - | (((vbs - 1) & 0x400) >> 9) - | ((vs & 0x400) >> 10) - | (interlaced) ? 0x80 : 0; - - - cr[0x08] = 0x00; - cr[0x09] = (dblscan << 7) - | ((LineCompare & 0x200) >> 3) - | (((vbs - 1) & 0x200) >> 4) - | (TextScanLines - 1); - - cr[0x10] = vs & 0xff; /* VSyncPulseStart */ - cr[0x11] = (ve & 0x0f); - cr[0x12] = (vd - 1) & 0xff; /* LineCount */ - cr[0x13] = wd & 0xff; - cr[0x14] = 0x40; - cr[0x15] = (vbs - 1) & 0xff; - cr[0x16] = vbe & 0xff; - cr[0x17] = 0xe3; /* but it does not work */ - cr[0x18] = 0xff & LineCompare; - cr[0x22] = 0x00; /* todo? */ - - - /* now set the registers */ - for (i = 0; i <= 0x18; i++) { /*CR00 .. CR18 */ - smiWrite (SMI_INDX_D4, i, cr[i]); - } - i = 0x22; /*CR22 */ - smiWrite (SMI_INDX_D4, i, cr[i]); - i = 0x30; /*CR30 */ - smiWrite (SMI_INDX_D4, i, cr[i]); -} - -/*****************************************************************************/ -#define REF_FREQ 14318180 -#define PMIN 1 -#define PMAX 255 -#define QMIN 1 -#define QMAX 63 - -static unsigned int FindPQ (unsigned int freq, unsigned int *pp, unsigned int *pq) -{ - unsigned int n = QMIN, m = 0; - long long int L = 0, P = freq, Q = REF_FREQ, H = P >> 1; - long long int D = 0x7ffffffffffffffLL; - - for (n = QMIN; n <= QMAX; n++) { - m = PMIN; /* p/q ~ freq/ref -> p*ref-freq*q ~ 0 */ - L = P * n - m * Q; - while (L > 0 && m < PMAX) { - L -= REF_FREQ; /* difference is greater as 0 subtract fref */ - m++; /* and increment m */ - } - /* difference is less or equal than 0 or m > maximum */ - if (m > PMAX) - break; /* no solution: if we increase n we get the same situation */ - /* L is <= 0 now */ - if (-L > H && m > PMIN) { /* if difference > the half fref */ - L += REF_FREQ; /* we take the situation before */ - m--; /* because its closer to 0 */ - } - L = (L < 0) ? -L : +L; /* absolute value */ - if (D < L) /* if last difference was better take next n */ - continue; - D = L; - *pp = m; - *pq = n; /* keep improved data */ - if (D == 0) - break; /* best result we can get */ - } - return (unsigned int) (0xffffffff & D); -} - -/*****************************************************************************/ -static void smiLoadCcr (struct ctfb_res_modes *var, unsigned short device_id) -{ - unsigned int p = 0; - unsigned int q = 0; - long long freq; - register GraphicDevice *pGD = (GraphicDevice *)&smi; - - smiWrite (SMI_INDX_C4, 0x65, 0); - smiWrite (SMI_INDX_C4, 0x66, 0); - smiWrite (SMI_INDX_C4, 0x68, 0x50); - if (device_id == PCI_DEVICE_ID_SMI_810) { - smiWrite (SMI_INDX_C4, 0x69, 0x3); - } else { - smiWrite (SMI_INDX_C4, 0x69, 0x0); - } - - /* Memory clock */ - switch (device_id) { - case PCI_DEVICE_ID_SMI_710 : - smiWrite (SMI_INDX_C4, 0x6a, 0x75); - break; - case PCI_DEVICE_ID_SMI_712 : - smiWrite (SMI_INDX_C4, 0x6a, 0x80); - break; - default : - smiWrite (SMI_INDX_C4, 0x6a, 0x53); - break; - } - smiWrite (SMI_INDX_C4, 0x6b, 0x15); - - /* VCLK */ - freq = 1000000000000LL / var -> pixclock; - - FindPQ ((unsigned int)freq, &p, &q); - - smiWrite (SMI_INDX_C4, 0x6c, p); - smiWrite (SMI_INDX_C4, 0x6d, q); - -} - -/******************************************************************************* - * - * Init video chip with common Linux graphic modes (lilo) - */ -void *video_hw_init (void) -{ - GraphicDevice *pGD = (GraphicDevice *)&smi; - unsigned short device_id; - pci_dev_t devbusfn; - int videomode; - unsigned long t1, hsynch, vsynch; - unsigned int pci_mem_base, *vm; - char *penv; - int tmp, i, bits_per_pixel; - struct ctfb_res_modes *res_mode; - struct ctfb_res_modes var_mode; - unsigned char videoout; - - /* Search for video chip */ - printf("Video: "); - - if ((devbusfn = pci_find_devices(supported, 0)) < 0) - { - printf ("Controller not found !\n"); - return (NULL); - } - - /* PCI setup */ - pci_write_config_dword (devbusfn, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); - pci_read_config_word (devbusfn, PCI_DEVICE_ID, &device_id); - pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &pci_mem_base); - pci_mem_base = pci_mem_to_phys (devbusfn, pci_mem_base); - - tmp = 0; - - videomode = CONFIG_SYS_DEFAULT_VIDEO_MODE; - /* get video mode via environment */ - if ((penv = getenv ("videomode")) != NULL) { - /* deceide if it is a string */ - if (penv[0] <= '9') { - videomode = (int) simple_strtoul (penv, NULL, 16); - tmp = 1; - } - } else { - tmp = 1; - } - if (tmp) { - /* parameter are vesa modes */ - /* search params */ - for (i = 0; i < VESA_MODES_COUNT; i++) { - if (vesa_modes[i].vesanr == videomode) - break; - } - if (i == VESA_MODES_COUNT) { - printf ("no VESA Mode found, switching to mode 0x%x ", CONFIG_SYS_DEFAULT_VIDEO_MODE); - i = 0; - } - res_mode = - (struct ctfb_res_modes *) &res_mode_init[vesa_modes[i]. - resindex]; - bits_per_pixel = vesa_modes[i].bits_per_pixel; - } else { - - res_mode = (struct ctfb_res_modes *) &var_mode; - bits_per_pixel = video_get_params (res_mode, penv); - } - - /* calculate hsynch and vsynch freq (info only) */ - t1 = (res_mode->left_margin + res_mode->xres + - res_mode->right_margin + res_mode->hsync_len) / 8; - t1 *= 8; - t1 *= res_mode->pixclock; - t1 /= 1000; - hsynch = 1000000000L / t1; - t1 *= - (res_mode->upper_margin + res_mode->yres + - res_mode->lower_margin + res_mode->vsync_len); - t1 /= 1000; - vsynch = 1000000000L / t1; - - /* fill in Graphic device struct */ - sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres, - res_mode->yres, bits_per_pixel, (hsynch / 1000), - (vsynch / 1000)); - printf ("%s\n", pGD->modeIdent); - pGD->winSizeX = res_mode->xres; - pGD->winSizeY = res_mode->yres; - pGD->plnSizeX = res_mode->xres; - pGD->plnSizeY = res_mode->yres; - switch (bits_per_pixel) { - case 8: - pGD->gdfBytesPP = 1; - pGD->gdfIndex = GDF__8BIT_INDEX; - break; - case 15: - pGD->gdfBytesPP = 2; - pGD->gdfIndex = GDF_15BIT_555RGB; - break; - case 16: - pGD->gdfBytesPP = 2; - pGD->gdfIndex = GDF_16BIT_565RGB; - break; - case 24: - pGD->gdfBytesPP = 3; - pGD->gdfIndex = GDF_24BIT_888RGB; - break; - } - - pGD->isaBase = CONFIG_SYS_ISA_IO; - pGD->pciBase = pci_mem_base; - pGD->dprBase = (pci_mem_base + 0x400000 + 0x8000); - pGD->vprBase = (pci_mem_base + 0x400000 + 0xc000); - pGD->cprBase = (pci_mem_base + 0x400000 + 0xe000); - pGD->frameAdrs = pci_mem_base; - pGD->memSize = VIDEO_MEM_SIZE; - - /* Set up hardware : select color mode, - set Register base to isa 3dx for 3?x regs*/ - out8 (SMI_MISC_REG, 0x01); - - /* Turn off display */ - smiWrite (SMI_INDX_C4, 0x01, 0x20); - - /* Unlock ext. crt regs */ - out8 (SMI_LOCK_REG, 0x40); - - /* Unlock crt regs 0-7 */ - smiWrite (SMI_INDX_D4, 0x11, 0x0e); - - /* Sytem Control Register */ - smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5, SMI_SCR, sizeof(SMI_SCR)); - - /* extented CRT Register */ - smiLoadRegs (SMI_INDX_D4, SMI_DATA_D5, SMI_EXT_CRT, sizeof(SMI_EXT_CRT)); - - /* Attributes controller registers */ - smiLoadRegs (SMI_INDX_ATTR, SMI_INDX_ATTR, SMI_ATTR, sizeof(SMI_ATTR)); - - /* Graphics Controller Register */ - smiLoadRegs (SMI_INDX_CE, SMI_DATA_CF, SMI_GCR, sizeof(SMI_GCR)); - - /* Sequencer Register */ - smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5, SMI_SEQR, sizeof(SMI_SEQR)); - - /* Power Control Register */ - smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5, SMI_PCR, sizeof(SMI_PCR)); - - /* Memory Control Register */ - /* Register MSR62 is a power on configurable register. We don't */ - /* modify it */ - smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5, SMI_MCR, sizeof(SMI_MCR)); - - /* Set misc output register */ - smiLoadMsr (res_mode); - - /* Set CRT and Clock control registers */ - smiLoadCrt (res_mode, bits_per_pixel); - - smiLoadCcr (res_mode, device_id); - - /* Hardware Cusor Register */ - smiLoadRegs (SMI_INDX_C4, SMI_DATA_C5, SMI_HCR, sizeof(SMI_HCR)); - - /* Enable Display */ - videoout = 2; /* Default output is CRT */ - if ((penv = getenv ("videoout")) != NULL) { - /* deceide if it is a string */ - videoout = (int) simple_strtoul (penv, NULL, 16); - } - smiWrite (SMI_INDX_C4, 0x31, videoout); - - /* Video processor default setup */ - smiInitVideoProcessor (); - - /* Capture port default setup */ - smiInitCapturePort (); - - /* Drawing engine default setup */ - smiInitDrawingEngine (); - - /* Turn on display */ - smiWrite (0x3c4, 0x01, 0x01); - - /* Clear video memory */ - i = pGD->memSize/4; - vm = (unsigned int *)pGD->pciBase; - while(i--) - *vm++ = 0; - return ((void*)&smi); -} - -/******************************************************************************* - * - * Drawing engine fill on screen region - */ -void video_hw_rectfill ( - unsigned int bpp, /* bytes per pixel */ - unsigned int dst_x, /* dest pos x */ - unsigned int dst_y, /* dest pos y */ - unsigned int dim_x, /* frame width */ - unsigned int dim_y, /* frame height */ - unsigned int color /* fill color */ - ) -{ - register GraphicDevice *pGD = (GraphicDevice *)&smi; - register unsigned int control; - - dim_x *= bpp; - - out32r ((pGD->dprBase + 0x0014), color); - out32r ((pGD->dprBase + 0x0004), ((dst_x<<16) | dst_y)); - out32r ((pGD->dprBase + 0x0008), ((dim_x<<16) | dim_y)); - - control = 0x0000ffff & in32r ((pGD->dprBase + 0x000c)); - - control |= 0x80010000; - - out32r ((pGD->dprBase + 0x000c), control); - - /* Wait for drawing processor */ - do - { - out8 ((pGD->isaBase + 0x3c4), 0x16); - } while (in8 (pGD->isaBase + 0x3c5) & 0x08); -} - -/******************************************************************************* - * - * Drawing engine bitblt with screen region - */ -void video_hw_bitblt ( - unsigned int bpp, /* bytes per pixel */ - unsigned int src_x, /* source pos x */ - unsigned int src_y, /* source pos y */ - unsigned int dst_x, /* dest pos x */ - unsigned int dst_y, /* dest pos y */ - unsigned int dim_x, /* frame width */ - unsigned int dim_y /* frame height */ - ) -{ - register GraphicDevice *pGD = (GraphicDevice *)&smi; - register unsigned int control; - - dim_x *= bpp; - - if ((src_y<dst_y) || ((src_y==dst_y) && (src_x<dst_x))) - { - out32r ((pGD->dprBase + 0x0000), (((src_x+dim_x-1)<<16) | (src_y+dim_y-1))); - out32r ((pGD->dprBase + 0x0004), (((dst_x+dim_x-1)<<16) | (dst_y+dim_y-1))); - control = 0x88000000; - } else { - out32r ((pGD->dprBase + 0x0000), ((src_x<<16) | src_y)); - out32r ((pGD->dprBase + 0x0004), ((dst_x<<16) | dst_y)); - control = 0x80000000; - } - - out32r ((pGD->dprBase + 0x0008), ((dim_x<<16) | dim_y)); - control |= (0x0000ffff & in32r ((pGD->dprBase + 0x000c))); - out32r ((pGD->dprBase + 0x000c), control); - - /* Wait for drawing processor */ - do - { - out8 ((pGD->isaBase + 0x3c4), 0x16); - } while (in8 (pGD->isaBase + 0x3c5) & 0x08); -} - -/******************************************************************************* - * - * Set a RGB color in the LUT (8 bit index) - */ -void video_set_lut ( - unsigned int index, /* color number */ - unsigned char r, /* red */ - unsigned char g, /* green */ - unsigned char b /* blue */ - ) -{ - register GraphicDevice *pGD = (GraphicDevice *)&smi; - - out8 (SMI_LUT_MASK, 0xff); - - out8 (SMI_LUT_START, (char)index); - - out8 (SMI_LUT_RGB, r>>2); /* red */ - udelay (10); - out8 (SMI_LUT_RGB, g>>2); /* green */ - udelay (10); - out8 (SMI_LUT_RGB, b>>2); /* blue */ - udelay (10); -} diff --git a/drivers/video/sunxi_display.c b/drivers/video/sunxi_display.c index 6cba1b95a1..6f8ee01c10 100644 --- a/drivers/video/sunxi_display.c +++ b/drivers/video/sunxi_display.c @@ -1563,7 +1563,7 @@ int sunxi_simplefb_setup(void *blob) "allwinner,simple-framebuffer"); while (offset >= 0) { ret = fdt_stringlist_search(blob, offset, "allwinner,pipeline", - pipeline); + pipeline); if (ret == 0) break; offset = fdt_node_offset_by_compatible(blob, offset, |