diff options
Diffstat (limited to 'drivers')
272 files changed, 14420 insertions, 2266 deletions
diff --git a/drivers/Kconfig b/drivers/Kconfig index f6003a0a593..4f844699555 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -68,6 +68,8 @@ source "drivers/spi/Kconfig" source "drivers/spmi/Kconfig" +source "drivers/sysreset/Kconfig" + source "drivers/thermal/Kconfig" source "drivers/timer/Kconfig" diff --git a/drivers/Makefile b/drivers/Makefile index 17239588570..7861d346036 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -19,14 +19,15 @@ obj-$(CONFIG_ARMADA_38X) += ddr/marvell/a38x/ obj-$(CONFIG_ARMADA_XP) += ddr/marvell/axp/ obj-$(CONFIG_ALTERA_SDRAM) += ddr/altera/ obj-$(CONFIG_SPL_SERIAL_SUPPORT) += serial/ -obj-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += mtd/spi/ obj-$(CONFIG_SPL_SPI_SUPPORT) += spi/ obj-$(CONFIG_SPL_POWER_SUPPORT) += power/ power/pmic/ obj-$(CONFIG_SPL_POWER_SUPPORT) += power/regulator/ +obj-$(CONFIG_SPL_DRIVERS_MISC_SUPPORT) += misc/ sysreset/ obj-$(CONFIG_SPL_MTD_SUPPORT) += mtd/ obj-$(CONFIG_SPL_NAND_SUPPORT) += mtd/nand/ -obj-$(CONFIG_SPL_DRIVERS_MISC_SUPPORT) += misc/ obj-$(CONFIG_SPL_ONENAND_SUPPORT) += mtd/onenand/ +obj-$(CONFIG_SPL_SPI_FLASH_SUPPORT) += mtd/spi/ +obj-$(CONFIG_SPL_UBI) += mtd/ubispl/ obj-$(CONFIG_SPL_DMA_SUPPORT) += dma/ obj-$(CONFIG_SPL_ETH_SUPPORT) += net/ obj-$(CONFIG_SPL_ETH_SUPPORT) += net/phy/ @@ -58,6 +59,7 @@ obj-$(CONFIG_X86) += pch/ obj-y += rtc/ obj-y += sound/ obj-y += spmi/ +obj-y += sysreset/ obj-y += timer/ obj-y += tpm/ obj-y += twserial/ diff --git a/drivers/bios_emulator/x86emu/sys.c b/drivers/bios_emulator/x86emu/sys.c index 0ba9c0c105d..c2db1213fe6 100644 --- a/drivers/bios_emulator/x86emu/sys.c +++ b/drivers/bios_emulator/x86emu/sys.c @@ -35,7 +35,7 @@ * Description: This file includes subroutines which are related to * programmed I/O and memory access. Included in this module * are default functions that do nothing. For real uses these -* functions will have to be overriden by the user library. +* functions will have to be overridden by the user library. * ****************************************************************************/ diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 6eee8eb369b..8f3b96a9736 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -20,7 +20,9 @@ config SPL_CLK setting up clocks within SPL, and allows the same drivers to be used as U-Boot proper. +source "drivers/clk/tegra/Kconfig" source "drivers/clk/uniphier/Kconfig" source "drivers/clk/exynos/Kconfig" +source "drivers/clk/at91/Kconfig" endmenu diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index f7a88912e06..778d7486f06 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -6,10 +6,12 @@ # obj-$(CONFIG_CLK) += clk-uclass.o clk_fixed_rate.o -obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o -obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o +obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ obj-$(CONFIG_SANDBOX) += clk_sandbox.o obj-$(CONFIG_SANDBOX) += clk_sandbox_test.o obj-$(CONFIG_MACH_PIC32) += clk_pic32.o + +obj-y += tegra/ obj-$(CONFIG_CLK_UNIPHIER) += uniphier/ obj-$(CONFIG_CLK_EXYNOS) += exynos/ +obj-$(CONFIG_CLK_AT91) += at91/ diff --git a/drivers/clk/at91/Kconfig b/drivers/clk/at91/Kconfig new file mode 100644 index 00000000000..10050d8a442 --- /dev/null +++ b/drivers/clk/at91/Kconfig @@ -0,0 +1,43 @@ +config CLK_AT91 + bool "AT91 clock drivers" + depends on CLK + help + This option is used to enable the AT91 clock driver. + The driver supports the AT91 clock generator, including + the oscillators and PLLs, such as main clock, slow clock, + PLLA, UTMI PLL. Clocks can also be a source clock of other + clocks a tree structure, such as master clock, usb device + clock, matrix clock and generic clock. + Devices can use a common clock API to request a particular + clock, enable it and get its rate. + +config AT91_UTMI + bool "Support UTMI PLL Clock" + depends on CLK_AT91 + help + This option is used to enable the AT91 UTMI PLL clock + driver. It is the clock provider of USB, and UPLLCK is the + output of 480 MHz UTMI PLL, The souce clock of the UTMI + PLL is the main clock, so the main clock must select the + fast crystal oscillator to meet the frequency accuracy + required by USB. + +config AT91_H32MX + bool "Support H32MX 32-bit Matrix Clock" + depends on CLK_AT91 + help + This option is used to enable the AT91 H32MX matrixes + clock driver. There are H64MX and H32MX matrixes clocks, + H64MX 64-bit matrix clocks are MCK. The H32MX 32-bit + matrix clock is to be configured as MCK if MCK does not + exceed 83 MHz, else it is to be configured as MCK/2. + +config AT91_GENERIC_CLK + bool "Support Generic Clock" + depends on CLK_AT91 + help + This option is used to enable the AT91 generic clock + driver. Some peripherals may need a second clock source + that may be different from the system clock. This second + clock is the generic clock (GCLK) and is managed by + the PMC via PMC_PCR register. diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile new file mode 100644 index 00000000000..fbe3cb65815 --- /dev/null +++ b/drivers/clk/at91/Makefile @@ -0,0 +1,11 @@ +# +# Makefile for at91 specific clk +# + +obj-y += pmc.o sckc.o +obj-y += clk-slow.o clk-main.o clk-plla.o clk-master.o +obj-y += clk-system.o clk-peripheral.o + +obj-$(CONFIG_AT91_UTMI) += clk-utmi.o +obj-$(CONFIG_AT91_H32MX) += clk-h32mx.o +obj-$(CONFIG_AT91_GENERIC_CLK) += clk-generated.o diff --git a/drivers/clk/at91/clk-generated.c b/drivers/clk/at91/clk-generated.c new file mode 100644 index 00000000000..f6164cc8ca1 --- /dev/null +++ b/drivers/clk/at91/clk-generated.c @@ -0,0 +1,162 @@ +/* + * Copyright (C) 2016 Atmel Corporation + * Wenyou.Yang <wenyou.yang@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm/device.h> +#include <linux/io.h> +#include <mach/at91_pmc.h> +#include "pmc.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define GENERATED_SOURCE_MAX 6 +#define GENERATED_MAX_DIV 255 + +struct generated_clk_priv { + u32 num_parents; +}; + +static ulong generated_clk_get_rate(struct clk *clk) +{ + struct pmc_platdata *plat = dev_get_platdata(clk->dev); + struct at91_pmc *pmc = plat->reg_base; + struct clk parent; + u32 tmp, gckdiv; + u8 parent_id; + int ret; + + writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr); + tmp = readl(&pmc->pcr); + parent_id = (tmp >> AT91_PMC_PCR_GCKCSS_OFFSET) & + AT91_PMC_PCR_GCKCSS_MASK; + gckdiv = (tmp >> AT91_PMC_PCR_GCKDIV_OFFSET) & AT91_PMC_PCR_GCKDIV_MASK; + + ret = clk_get_by_index(clk->dev, parent_id, &parent); + if (ret) + return 0; + + return clk_get_rate(&parent) / (gckdiv + 1); +} + +static ulong generated_clk_set_rate(struct clk *clk, ulong rate) +{ + struct pmc_platdata *plat = dev_get_platdata(clk->dev); + struct at91_pmc *pmc = plat->reg_base; + struct generated_clk_priv *priv = dev_get_priv(clk->dev); + struct clk parent, best_parent; + ulong tmp_rate, best_rate = rate, parent_rate; + int tmp_diff, best_diff = -1; + u32 div, best_div = 0; + u8 best_parent_id = 0; + u8 i; + u32 tmp; + int ret; + + for (i = 0; i < priv->num_parents; i++) { + ret = clk_get_by_index(clk->dev, i, &parent); + if (ret) + return ret; + + parent_rate = clk_get_rate(&parent); + if (IS_ERR_VALUE(parent_rate)) + return parent_rate; + + for (div = 1; div < GENERATED_MAX_DIV + 2; div++) { + tmp_rate = DIV_ROUND_CLOSEST(parent_rate, div); + if (rate < tmp_rate) + continue; + tmp_diff = rate - tmp_rate; + + if (best_diff < 0 || best_diff > tmp_diff) { + best_rate = tmp_rate; + best_diff = tmp_diff; + + best_div = div - 1; + best_parent = parent; + best_parent_id = i; + } + + if (!best_diff || tmp_rate < rate) + break; + } + + if (!best_diff) + break; + } + + debug("GCK: best parent: %s, best_rate = %ld, best_div = %d\n", + best_parent.dev->name, best_rate, best_div); + + ret = clk_enable(&best_parent); + if (ret) + return ret; + + writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr); + tmp = readl(&pmc->pcr); + tmp &= ~(AT91_PMC_PCR_GCKDIV | AT91_PMC_PCR_GCKCSS); + tmp |= AT91_PMC_PCR_GCKCSS_(best_parent_id) | + AT91_PMC_PCR_CMD_WRITE | + AT91_PMC_PCR_GCKDIV_(best_div) | + AT91_PMC_PCR_GCKEN; + writel(tmp, &pmc->pcr); + + while (!(readl(&pmc->sr) & AT91_PMC_GCKRDY)) + ; + + return 0; +} + +static struct clk_ops generated_clk_ops = { + .get_rate = generated_clk_get_rate, + .set_rate = generated_clk_set_rate, +}; + +static int generated_clk_ofdata_to_platdata(struct udevice *dev) +{ + struct generated_clk_priv *priv = dev_get_priv(dev); + u32 cells[GENERATED_SOURCE_MAX]; + u32 num_parents; + + num_parents = fdtdec_get_int_array_count(gd->fdt_blob, dev->of_offset, + "clocks", cells, + GENERATED_SOURCE_MAX); + + if (!num_parents) + return -1; + + priv->num_parents = num_parents; + + return 0; +} + +static int generated_clk_bind(struct udevice *dev) +{ + return at91_pmc_clk_node_bind(dev); +} + +static int generated_clk_probe(struct udevice *dev) +{ + return at91_pmc_core_probe(dev); +} + +static const struct udevice_id generated_clk_match[] = { + { .compatible = "atmel,sama5d2-clk-generated" }, + {} +}; + +U_BOOT_DRIVER(generated_clk) = { + .name = "generated-clk", + .id = UCLASS_CLK, + .of_match = generated_clk_match, + .bind = generated_clk_bind, + .probe = generated_clk_probe, + .ofdata_to_platdata = generated_clk_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct generated_clk_priv), + .platdata_auto_alloc_size = sizeof(struct pmc_platdata), + .ops = &generated_clk_ops, +}; diff --git a/drivers/clk/at91/clk-h32mx.c b/drivers/clk/at91/clk-h32mx.c new file mode 100644 index 00000000000..1a304bab212 --- /dev/null +++ b/drivers/clk/at91/clk-h32mx.c @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2016 Atmel Corporation + * Wenyou.Yang <wenyou.yang@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm/device.h> +#include <dm/util.h> +#include <linux/io.h> +#include <mach/at91_pmc.h> +#include "pmc.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define H32MX_MAX_FREQ 90000000 + +static ulong sama5d4_h32mx_clk_get_rate(struct clk *clk) +{ + struct pmc_platdata *plat = dev_get_platdata(clk->dev); + struct at91_pmc *pmc = plat->reg_base; + ulong rate = gd->arch.mck_rate_hz; + + if (readl(&pmc->mckr) & AT91_PMC_MCKR_H32MXDIV) + rate /= 2; + + if (rate > H32MX_MAX_FREQ) + dm_warn("H32MX clock is too fast\n"); + + return rate; +} + +static struct clk_ops sama5d4_h32mx_clk_ops = { + .get_rate = sama5d4_h32mx_clk_get_rate, +}; + +static int sama5d4_h32mx_clk_probe(struct udevice *dev) +{ + return at91_pmc_core_probe(dev); +} + +static const struct udevice_id sama5d4_h32mx_clk_match[] = { + { .compatible = "atmel,sama5d4-clk-h32mx" }, + {} +}; + +U_BOOT_DRIVER(sama5d4_h32mx_clk) = { + .name = "sama5d4-h32mx-clk", + .id = UCLASS_CLK, + .of_match = sama5d4_h32mx_clk_match, + .probe = sama5d4_h32mx_clk_probe, + .platdata_auto_alloc_size = sizeof(struct pmc_platdata), + .ops = &sama5d4_h32mx_clk_ops, +}; diff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c new file mode 100644 index 00000000000..252d076bd50 --- /dev/null +++ b/drivers/clk/at91/clk-main.c @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2016 Atmel Corporation + * Wenyou.Yang <wenyou.yang@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm/device.h> +#include <linux/io.h> +#include <mach/at91_pmc.h> +#include "pmc.h" + +DECLARE_GLOBAL_DATA_PTR; + +static int main_osc_clk_enable(struct clk *clk) +{ + struct pmc_platdata *plat = dev_get_platdata(clk->dev); + struct at91_pmc *pmc = plat->reg_base; + + if (readl(&pmc->sr) & AT91_PMC_MOSCSELS) + return 0; + + return -EINVAL; +} + +static ulong main_osc_clk_get_rate(struct clk *clk) +{ + return gd->arch.main_clk_rate_hz; +} + +static struct clk_ops main_osc_clk_ops = { + .enable = main_osc_clk_enable, + .get_rate = main_osc_clk_get_rate, +}; + +static int main_osc_clk_probe(struct udevice *dev) +{ + return at91_pmc_core_probe(dev); +} + +static const struct udevice_id main_osc_clk_match[] = { + { .compatible = "atmel,at91sam9x5-clk-main" }, + {} +}; + +U_BOOT_DRIVER(at91sam9x5_main_osc_clk) = { + .name = "at91sam9x5-main-osc-clk", + .id = UCLASS_CLK, + .of_match = main_osc_clk_match, + .probe = main_osc_clk_probe, + .platdata_auto_alloc_size = sizeof(struct pmc_platdata), + .ops = &main_osc_clk_ops, +}; diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c new file mode 100644 index 00000000000..284b2482712 --- /dev/null +++ b/drivers/clk/at91/clk-master.c @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2016 Atmel Corporation + * Wenyou.Yang <wenyou.yang@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm/device.h> + +DECLARE_GLOBAL_DATA_PTR; + +static ulong at91_master_clk_get_rate(struct clk *clk) +{ + return gd->arch.mck_rate_hz; +} + +static struct clk_ops at91_master_clk_ops = { + .get_rate = at91_master_clk_get_rate, +}; + +static const struct udevice_id at91_master_clk_match[] = { + { .compatible = "atmel,at91sam9x5-clk-master" }, + {} +}; + +U_BOOT_DRIVER(at91_master_clk) = { + .name = "at91-master-clk", + .id = UCLASS_CLK, + .of_match = at91_master_clk_match, + .ops = &at91_master_clk_ops, +}; diff --git a/drivers/clk/at91/clk-peripheral.c b/drivers/clk/at91/clk-peripheral.c new file mode 100644 index 00000000000..16688e90b41 --- /dev/null +++ b/drivers/clk/at91/clk-peripheral.c @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2016 Atmel Corporation + * Wenyou.Yang <wenyou.yang@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm/device.h> +#include <linux/io.h> +#include <mach/at91_pmc.h> +#include "pmc.h" + +#define PERIPHERAL_ID_MIN 2 +#define PERIPHERAL_ID_MAX 31 +#define PERIPHERAL_MASK(id) (1 << ((id) & PERIPHERAL_ID_MAX)) + +static int sam9x5_periph_clk_enable(struct clk *clk) +{ + struct pmc_platdata *plat = dev_get_platdata(clk->dev); + struct at91_pmc *pmc = plat->reg_base; + + if (clk->id < PERIPHERAL_ID_MIN) + return -1; + + writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr); + setbits_le32(&pmc->pcr, AT91_PMC_PCR_CMD_WRITE | AT91_PMC_PCR_EN); + + return 0; +} + +static struct clk_ops sam9x5_periph_clk_ops = { + .enable = sam9x5_periph_clk_enable, +}; + +static int sam9x5_periph_clk_bind(struct udevice *dev) +{ + return at91_pmc_clk_node_bind(dev); +} + +static int sam9x5_periph_clk_probe(struct udevice *dev) +{ + return at91_pmc_core_probe(dev); +} + +static const struct udevice_id sam9x5_periph_clk_match[] = { + { .compatible = "atmel,at91sam9x5-clk-peripheral" }, + {} +}; + +U_BOOT_DRIVER(sam9x5_periph_clk) = { + .name = "sam9x5-periph-clk", + .id = UCLASS_CLK, + .of_match = sam9x5_periph_clk_match, + .bind = sam9x5_periph_clk_bind, + .probe = sam9x5_periph_clk_probe, + .platdata_auto_alloc_size = sizeof(struct pmc_platdata), + .ops = &sam9x5_periph_clk_ops, +}; diff --git a/drivers/clk/at91/clk-plla.c b/drivers/clk/at91/clk-plla.c new file mode 100644 index 00000000000..2a713997412 --- /dev/null +++ b/drivers/clk/at91/clk-plla.c @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2016 Atmel Corporation + * Wenyou.Yang <wenyou.yang@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm/device.h> +#include <linux/io.h> +#include <mach/at91_pmc.h> +#include "pmc.h" + +DECLARE_GLOBAL_DATA_PTR; + +static int plla_clk_enable(struct clk *clk) +{ + struct pmc_platdata *plat = dev_get_platdata(clk->dev); + struct at91_pmc *pmc = plat->reg_base; + + if (readl(&pmc->sr) & AT91_PMC_LOCKA) + return 0; + + return -EINVAL; +} + +static ulong plla_clk_get_rate(struct clk *clk) +{ + return gd->arch.plla_rate_hz; +} + +static struct clk_ops plla_clk_ops = { + .enable = plla_clk_enable, + .get_rate = plla_clk_get_rate, +}; + +static int plla_clk_probe(struct udevice *dev) +{ + return at91_pmc_core_probe(dev); +} + +static const struct udevice_id plla_clk_match[] = { + { .compatible = "atmel,sama5d3-clk-pll" }, + {} +}; + +U_BOOT_DRIVER(at91_plla_clk) = { + .name = "at91-plla-clk", + .id = UCLASS_CLK, + .of_match = plla_clk_match, + .probe = plla_clk_probe, + .platdata_auto_alloc_size = sizeof(struct pmc_platdata), + .ops = &plla_clk_ops, +}; diff --git a/drivers/clk/at91/clk-slow.c b/drivers/clk/at91/clk-slow.c new file mode 100644 index 00000000000..f7666b4041c --- /dev/null +++ b/drivers/clk/at91/clk-slow.c @@ -0,0 +1,37 @@ +/* + * Copyright (C) 2016 Atmel Corporation + * Wenyou.Yang <wenyou.yang@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm/device.h> + +static int at91_slow_clk_enable(struct clk *clk) +{ + return 0; +} + +static ulong at91_slow_clk_get_rate(struct clk *clk) +{ + return CONFIG_SYS_AT91_SLOW_CLOCK; +} + +static struct clk_ops at91_slow_clk_ops = { + .enable = at91_slow_clk_enable, + .get_rate = at91_slow_clk_get_rate, +}; + +static const struct udevice_id at91_slow_clk_match[] = { + { .compatible = "atmel,at91sam9x5-clk-slow" }, + {} +}; + +U_BOOT_DRIVER(at91_slow_clk) = { + .name = "at91-slow-clk", + .id = UCLASS_CLK, + .of_match = at91_slow_clk_match, + .ops = &at91_slow_clk_ops, +}; diff --git a/drivers/clk/at91/clk-system.c b/drivers/clk/at91/clk-system.c new file mode 100644 index 00000000000..fa80bade7a9 --- /dev/null +++ b/drivers/clk/at91/clk-system.c @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2016 Atmel Corporation + * Wenyou.Yang <wenyou.yang@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm/device.h> +#include <linux/io.h> +#include <mach/at91_pmc.h> +#include "pmc.h" + +#define SYSTEM_MAX_ID 31 + +static inline int is_pck(int id) +{ + return (id >= 8) && (id <= 15); +} + +static int at91_system_clk_enable(struct clk *clk) +{ + struct pmc_platdata *plat = dev_get_platdata(clk->dev); + struct at91_pmc *pmc = plat->reg_base; + u32 mask; + + if (clk->id > SYSTEM_MAX_ID) + return -EINVAL; + + mask = BIT(clk->id); + + writel(mask, &pmc->scer); + + /** + * For the programmable clocks the Ready status in the PMC + * status register should be checked after enabling. + * For other clocks this is unnecessary. + */ + if (!is_pck(clk->id)) + return 0; + + while (!(readl(&pmc->sr) & mask)) + ; + + return 0; +} + +static struct clk_ops at91_system_clk_ops = { + .enable = at91_system_clk_enable, +}; + +static int at91_system_clk_bind(struct udevice *dev) +{ + return at91_pmc_clk_node_bind(dev); +} + +static int at91_system_clk_probe(struct udevice *dev) +{ + return at91_pmc_core_probe(dev); +} + +static const struct udevice_id at91_system_clk_match[] = { + { .compatible = "atmel,at91rm9200-clk-system" }, + {} +}; + +U_BOOT_DRIVER(at91_system_clk) = { + .name = "at91-system-clk", + .id = UCLASS_CLK, + .of_match = at91_system_clk_match, + .bind = at91_system_clk_bind, + .probe = at91_system_clk_probe, + .platdata_auto_alloc_size = sizeof(struct pmc_platdata), + .ops = &at91_system_clk_ops, +}; diff --git a/drivers/clk/at91/clk-utmi.c b/drivers/clk/at91/clk-utmi.c new file mode 100644 index 00000000000..369a6870d87 --- /dev/null +++ b/drivers/clk/at91/clk-utmi.c @@ -0,0 +1,67 @@ +/* + * Copyright (C) 2016 Atmel Corporation + * Wenyou.Yang <wenyou.yang@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm/device.h> +#include <linux/io.h> +#include <mach/at91_pmc.h> +#include "pmc.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define UTMI_FIXED_MUL 40 + +static int utmi_clk_enable(struct clk *clk) +{ + struct pmc_platdata *plat = dev_get_platdata(clk->dev); + struct at91_pmc *pmc = plat->reg_base; + u32 tmp; + + if (readl(&pmc->sr) & AT91_PMC_LOCKU) + return 0; + + tmp = readl(&pmc->uckr); + tmp |= AT91_PMC_UPLLEN | + AT91_PMC_UPLLCOUNT | + AT91_PMC_BIASEN; + writel(tmp, &pmc->uckr); + + while (!(readl(&pmc->sr) & AT91_PMC_LOCKU)) + ; + + return 0; +} + +static ulong utmi_clk_get_rate(struct clk *clk) +{ + return gd->arch.main_clk_rate_hz * UTMI_FIXED_MUL; +} + +static struct clk_ops utmi_clk_ops = { + .enable = utmi_clk_enable, + .get_rate = utmi_clk_get_rate, +}; + +static int utmi_clk_probe(struct udevice *dev) +{ + return at91_pmc_core_probe(dev); +} + +static const struct udevice_id utmi_clk_match[] = { + { .compatible = "atmel,at91sam9x5-clk-utmi" }, + {} +}; + +U_BOOT_DRIVER(at91sam9x5_utmi_clk) = { + .name = "at91sam9x5-utmi-clk", + .id = UCLASS_CLK, + .of_match = utmi_clk_match, + .probe = utmi_clk_probe, + .platdata_auto_alloc_size = sizeof(struct pmc_platdata), + .ops = &utmi_clk_ops, +}; diff --git a/drivers/clk/at91/pmc.c b/drivers/clk/at91/pmc.c new file mode 100644 index 00000000000..a08d7e82eb3 --- /dev/null +++ b/drivers/clk/at91/pmc.c @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2016 Atmel Corporation + * Wenyou.Yang <wenyou.yang@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm/device.h> +#include <dm/lists.h> +#include <dm/root.h> +#include "pmc.h" + +DECLARE_GLOBAL_DATA_PTR; + +static int at91_pmc_bind(struct udevice *dev) +{ + return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false); +} + +static const struct udevice_id at91_pmc_match[] = { + { .compatible = "atmel,sama5d2-pmc" }, + {} +}; + +U_BOOT_DRIVER(at91_pmc) = { + .name = "at91-pmc-core", + .id = UCLASS_CLK, + .of_match = at91_pmc_match, + .bind = at91_pmc_bind, +}; + +int at91_pmc_core_probe(struct udevice *dev) +{ + struct pmc_platdata *plat = dev_get_platdata(dev); + + dev = dev_get_parent(dev); + + plat->reg_base = (struct at91_pmc *)dev_get_addr_ptr(dev); + + return 0; +} + +int at91_pmc_clk_node_bind(struct udevice *dev) +{ + const void *fdt = gd->fdt_blob; + int offset = dev->of_offset; + const char *name; + int ret; + + for (offset = fdt_first_subnode(fdt, offset); + offset > 0; + offset = fdt_next_subnode(fdt, offset)) { + name = fdt_get_name(fdt, offset, NULL); + if (!name) + return -EINVAL; + + ret = device_bind_driver_to_node(dev, "clk", name, + offset, NULL); + if (ret) + return ret; + } + + return 0; +} + +U_BOOT_DRIVER(clk_generic) = { + .id = UCLASS_CLK, + .name = "clk", +}; diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h new file mode 100644 index 00000000000..5444c84db66 --- /dev/null +++ b/drivers/clk/at91/pmc.h @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2016 Atmel Corporation + * Wenyou.Yang <wenyou.yang@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __AT91_PMC_H__ +#define __AT91_PMC_H__ + +struct pmc_platdata { + struct at91_pmc *reg_base; +}; + +int at91_pmc_core_probe(struct udevice *dev); +int at91_pmc_clk_node_bind(struct udevice *dev); + +#endif diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c new file mode 100644 index 00000000000..b207611de1c --- /dev/null +++ b/drivers/clk/at91/sckc.c @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2016 Atmel Corporation + * Wenyou.Yang <wenyou.yang@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm/device.h> +#include <dm/root.h> + +DECLARE_GLOBAL_DATA_PTR; + +static int at91_sckc_clk_bind(struct udevice *dev) +{ + return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false); +} + +static const struct udevice_id at91_sckc_clk_match[] = { + { .compatible = "atmel,at91sam9x5-sckc" }, + {} +}; + +U_BOOT_DRIVER(at91_sckc_clk) = { + .name = "at91_sckc_clk", + .id = UCLASS_CLK, + .of_match = at91_sckc_clk_match, + .bind = at91_sckc_clk_bind, +}; diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 6e4d67220a1..4d78e3fcac4 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -10,6 +10,7 @@ #include <clk.h> #include <clk-uclass.h> #include <dm.h> +#include <dt-structs.h> #include <errno.h> DECLARE_GLOBAL_DATA_PTR; @@ -20,31 +21,22 @@ static inline struct clk_ops *clk_dev_ops(struct udevice *dev) } #if CONFIG_IS_ENABLED(OF_CONTROL) -#ifdef CONFIG_SPL_BUILD -int clk_get_by_index(struct udevice *dev, int index, struct clk *clk) +# if CONFIG_IS_ENABLED(OF_PLATDATA) +int clk_get_by_index_platdata(struct udevice *dev, int index, + struct phandle_2_cell *cells, struct clk *clk) { int ret; - u32 cell[2]; if (index != 0) return -ENOSYS; - assert(clk); ret = uclass_get_device(UCLASS_CLK, 0, &clk->dev); if (ret) return ret; - ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, "clocks", - cell, 2); - if (ret) - return ret; - clk->id = cell[1]; - return 0; -} + clk->id = cells[0].id; -int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk) -{ - return -ENOSYS; + return 0; } -#else +# else static int clk_of_xlate_default(struct clk *clk, struct fdtdec_phandle_args *args) { @@ -101,6 +93,7 @@ int clk_get_by_index(struct udevice *dev, int index, struct clk *clk) return clk_request(dev_clk, clk); } +# endif /* OF_PLATDATA */ int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk) { @@ -117,8 +110,7 @@ int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk) return clk_get_by_index(dev, index, clk); } -#endif -#endif +#endif /* OF_CONTROL */ int clk_request(struct udevice *dev, struct clk *clk) { diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c index 797e5379075..9c4d2b322f7 100644 --- a/drivers/clk/clk_fixed_rate.c +++ b/drivers/clk/clk_fixed_rate.c @@ -30,9 +30,11 @@ const struct clk_ops clk_fixed_rate_ops = { static int clk_fixed_rate_ofdata_to_platdata(struct udevice *dev) { +#if !CONFIG_IS_ENABLED(OF_PLATDATA) to_clk_fixed_rate(dev)->fixed_rate = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "clock-frequency", 0); +#endif return 0; } diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile new file mode 100644 index 00000000000..1f8e41739d6 --- /dev/null +++ b/drivers/clk/rockchip/Makefile @@ -0,0 +1,9 @@ +# +# Copyright (c) 2016 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o +obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o +obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o diff --git a/drivers/clk/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c index 6202c9da5da..8899b0c62db 100644 --- a/drivers/clk/clk_rk3036.c +++ b/drivers/clk/rockchip/clk_rk3036.c @@ -15,6 +15,7 @@ #include <asm/arch/hardware.h> #include <dm/lists.h> #include <dt-bindings/clock/rk3036-cru.h> +#include <linux/log2.h> DECLARE_GLOBAL_DATA_PTR; @@ -48,11 +49,6 @@ enum { static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1); static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); -static inline unsigned int log2(unsigned int value) -{ - return fls(value) - 1; -} - void *rockchip_get_cru(void) { struct udevice *dev; @@ -177,11 +173,11 @@ static void rkclk_init(struct rk3036_cru *cru) aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); - hclk_div = log2(PERI_ACLK_HZ / PERI_HCLK_HZ); + hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); assert((1 << hclk_div) * PERI_HCLK_HZ == PERI_ACLK_HZ && (pclk_div < 0x4)); - pclk_div = log2(PERI_ACLK_HZ / PERI_PCLK_HZ); + pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); assert((1 << pclk_div) * PERI_PCLK_HZ == PERI_ACLK_HZ && pclk_div < 0x8); diff --git a/drivers/clk/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c index 2285453e8de..c07203d84b9 100644 --- a/drivers/clk/clk_rk3288.c +++ b/drivers/clk/rockchip/clk_rk3288.c @@ -7,7 +7,9 @@ #include <common.h> #include <clk-uclass.h> #include <dm.h> +#include <dt-structs.h> #include <errno.h> +#include <mapmem.h> #include <syscon.h> #include <asm/io.h> #include <asm/arch/clock.h> @@ -18,9 +20,16 @@ #include <dm/device-internal.h> #include <dm/lists.h> #include <dm/uclass-internal.h> +#include <linux/log2.h> DECLARE_GLOBAL_DATA_PTR; +struct rk3288_clk_plat { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_rockchip_rk3288_cru dtd; +#endif +}; + struct rk3288_clk_priv { struct rk3288_grf *grf; struct rk3288_cru *cru; @@ -39,7 +48,7 @@ enum { OUTPUT_MAX_HZ = 2200U * 1000000, OUTPUT_MIN_HZ = 27500000, FREF_MAX_HZ = 2200U * 1000000, - FREF_MIN_HZ = 269 * 1000000, + FREF_MIN_HZ = 269 * 1000, }; enum { @@ -137,7 +146,7 @@ void *rockchip_get_cru(void) struct udevice *dev; int ret; - ret = uclass_get_device(UCLASS_CLK, 0, &dev); + ret = rockchip_get_clk(&dev); if (ret) return ERR_PTR(ret); @@ -178,11 +187,6 @@ static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id, return 0; } -static inline unsigned int log2(unsigned int value) -{ - return fls(value) - 1; -} - static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf, unsigned int hz) { @@ -413,11 +417,11 @@ static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf) aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); - hclk_div = log2(PERI_ACLK_HZ / PERI_HCLK_HZ); + hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); assert((1 << hclk_div) * PERI_HCLK_HZ == PERI_ACLK_HZ && (hclk_div < 0x4)); - pclk_div = log2(PERI_ACLK_HZ / PERI_PCLK_HZ); + pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); assert((1 << pclk_div) * PERI_PCLK_HZ == PERI_ACLK_HZ && (pclk_div < 0x4)); @@ -439,7 +443,7 @@ static void rkclk_init(struct rk3288_cru *cru, struct rk3288_grf *grf) } #endif -void rkclk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf) +void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf) { /* pll enter slow-mode */ rk_clrsetreg(&cru->cru_mode_con, @@ -783,13 +787,30 @@ static struct clk_ops rk3288_clk_ops = { .set_rate = rk3288_clk_set_rate, }; -static int rk3288_clk_probe(struct udevice *dev) +static int rk3288_clk_ofdata_to_platdata(struct udevice *dev) { +#if !CONFIG_IS_ENABLED(OF_PLATDATA) struct rk3288_clk_priv *priv = dev_get_priv(dev); priv->cru = (struct rk3288_cru *)dev_get_addr(dev); +#endif + + return 0; +} + +static int rk3288_clk_probe(struct udevice *dev) +{ + struct rk3288_clk_priv *priv = dev_get_priv(dev); + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + if (IS_ERR(priv->grf)) + return PTR_ERR(priv->grf); #ifdef CONFIG_SPL_BUILD +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct rk3288_clk_plat *plat = dev_get_platdata(dev); + + priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); +#endif rkclk_init(priv->cru, priv->grf); #endif @@ -813,12 +834,14 @@ static const struct udevice_id rk3288_clk_ids[] = { { } }; -U_BOOT_DRIVER(clk_rk3288) = { - .name = "clk_rk3288", +U_BOOT_DRIVER(rockchip_rk3288_cru) = { + .name = "rockchip_rk3288_cru", .id = UCLASS_CLK, .of_match = rk3288_clk_ids, .priv_auto_alloc_size = sizeof(struct rk3288_clk_priv), + .platdata_auto_alloc_size = sizeof(struct rk3288_clk_plat), .ops = &rk3288_clk_ops, .bind = rk3288_clk_bind, + .ofdata_to_platdata = rk3288_clk_ofdata_to_platdata, .probe = rk3288_clk_probe, }; diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c new file mode 100644 index 00000000000..0b4ea828f60 --- /dev/null +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -0,0 +1,832 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <errno.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3399.h> +#include <asm/arch/hardware.h> +#include <dm/lists.h> +#include <dt-bindings/clock/rk3399-cru.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct rk3399_clk_priv { + struct rk3399_cru *cru; + ulong rate; +}; + +struct pll_div { + u32 refdiv; + u32 fbdiv; + u32 postdiv1; + u32 postdiv2; + u32 frac; +}; + +#define RATE_TO_DIV(input_rate, output_rate) \ + ((input_rate) / (output_rate) - 1); +#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) + +#define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\ + .refdiv = _refdiv,\ + .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ),\ + .postdiv1 = _postdiv1, .postdiv2 = _postdiv2}; + +static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); +static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2); +static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1); + +static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1); +static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1); + +static const struct pll_div *apll_l_cfgs[] = { + [APLL_L_1600_MHZ] = &apll_l_1600_cfg, + [APLL_L_600_MHZ] = &apll_l_600_cfg, +}; + +enum { + /* PLL_CON0 */ + PLL_FBDIV_MASK = 0xfff, + PLL_FBDIV_SHIFT = 0, + + /* PLL_CON1 */ + PLL_POSTDIV2_SHIFT = 12, + PLL_POSTDIV2_MASK = 0x7 << PLL_POSTDIV2_SHIFT, + PLL_POSTDIV1_SHIFT = 8, + PLL_POSTDIV1_MASK = 0x7 << PLL_POSTDIV1_SHIFT, + PLL_REFDIV_MASK = 0x3f, + PLL_REFDIV_SHIFT = 0, + + /* PLL_CON2 */ + PLL_LOCK_STATUS_SHIFT = 31, + PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT, + PLL_FRACDIV_MASK = 0xffffff, + PLL_FRACDIV_SHIFT = 0, + + /* PLL_CON3 */ + PLL_MODE_SHIFT = 8, + PLL_MODE_MASK = 3 << PLL_MODE_SHIFT, + PLL_MODE_SLOW = 0, + PLL_MODE_NORM, + PLL_MODE_DEEP, + PLL_DSMPD_SHIFT = 3, + PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT, + PLL_INTEGER_MODE = 1, + + /* PMUCRU_CLKSEL_CON0 */ + PMU_PCLK_DIV_CON_MASK = 0x1f, + PMU_PCLK_DIV_CON_SHIFT = 0, + + /* PMUCRU_CLKSEL_CON1 */ + SPI3_PLL_SEL_SHIFT = 7, + SPI3_PLL_SEL_MASK = 1 << SPI3_PLL_SEL_SHIFT, + SPI3_PLL_SEL_24M = 0, + SPI3_PLL_SEL_PPLL = 1, + SPI3_DIV_CON_SHIFT = 0x0, + SPI3_DIV_CON_MASK = 0x7f, + + /* PMUCRU_CLKSEL_CON2 */ + I2C_DIV_CON_MASK = 0x7f, + I2C8_DIV_CON_SHIFT = 8, + I2C0_DIV_CON_SHIFT = 0, + + /* PMUCRU_CLKSEL_CON3 */ + I2C4_DIV_CON_SHIFT = 0, + + /* CLKSEL_CON0 */ + ACLKM_CORE_L_DIV_CON_SHIFT = 8, + ACLKM_CORE_L_DIV_CON_MASK = 0x1f << ACLKM_CORE_L_DIV_CON_SHIFT, + CLK_CORE_L_PLL_SEL_SHIFT = 6, + CLK_CORE_L_PLL_SEL_MASK = 3 << CLK_CORE_L_PLL_SEL_SHIFT, + CLK_CORE_L_PLL_SEL_ALPLL = 0x0, + CLK_CORE_L_PLL_SEL_ABPLL = 0x1, + CLK_CORE_L_PLL_SEL_DPLL = 0x10, + CLK_CORE_L_PLL_SEL_GPLL = 0x11, + CLK_CORE_L_DIV_MASK = 0x1f, + CLK_CORE_L_DIV_SHIFT = 0, + + /* CLKSEL_CON1 */ + PCLK_DBG_L_DIV_SHIFT = 0x8, + PCLK_DBG_L_DIV_MASK = 0x1f << PCLK_DBG_L_DIV_SHIFT, + ATCLK_CORE_L_DIV_SHIFT = 0, + ATCLK_CORE_L_DIV_MASK = 0x1f << ATCLK_CORE_L_DIV_SHIFT, + + /* CLKSEL_CON14 */ + PCLK_PERIHP_DIV_CON_SHIFT = 12, + PCLK_PERIHP_DIV_CON_MASK = 0x7 << PCLK_PERIHP_DIV_CON_SHIFT, + HCLK_PERIHP_DIV_CON_SHIFT = 8, + HCLK_PERIHP_DIV_CON_MASK = 3 << HCLK_PERIHP_DIV_CON_SHIFT, + ACLK_PERIHP_PLL_SEL_SHIFT = 7, + ACLK_PERIHP_PLL_SEL_MASK = 1 << ACLK_PERIHP_PLL_SEL_SHIFT, + ACLK_PERIHP_PLL_SEL_CPLL = 0, + ACLK_PERIHP_PLL_SEL_GPLL = 1, + ACLK_PERIHP_DIV_CON_SHIFT = 0, + ACLK_PERIHP_DIV_CON_MASK = 0x1f, + + /* CLKSEL_CON21 */ + ACLK_EMMC_PLL_SEL_SHIFT = 7, + ACLK_EMMC_PLL_SEL_MASK = 0x1 << ACLK_EMMC_PLL_SEL_SHIFT, + ACLK_EMMC_PLL_SEL_GPLL = 0x1, + ACLK_EMMC_DIV_CON_SHIFT = 0, + ACLK_EMMC_DIV_CON_MASK = 0x1f, + + /* CLKSEL_CON22 */ + CLK_EMMC_PLL_SHIFT = 8, + CLK_EMMC_PLL_MASK = 0x7 << CLK_EMMC_PLL_SHIFT, + CLK_EMMC_PLL_SEL_GPLL = 0x1, + CLK_EMMC_PLL_SEL_24M = 0x5, + CLK_EMMC_DIV_CON_SHIFT = 0, + CLK_EMMC_DIV_CON_MASK = 0x7f << CLK_EMMC_DIV_CON_SHIFT, + + /* CLKSEL_CON23 */ + PCLK_PERILP0_DIV_CON_SHIFT = 12, + PCLK_PERILP0_DIV_CON_MASK = 0x7 << PCLK_PERILP0_DIV_CON_SHIFT, + HCLK_PERILP0_DIV_CON_SHIFT = 8, + HCLK_PERILP0_DIV_CON_MASK = 3 << HCLK_PERILP0_DIV_CON_SHIFT, + ACLK_PERILP0_PLL_SEL_SHIFT = 7, + ACLK_PERILP0_PLL_SEL_MASK = 1 << ACLK_PERILP0_PLL_SEL_SHIFT, + ACLK_PERILP0_PLL_SEL_CPLL = 0, + ACLK_PERILP0_PLL_SEL_GPLL = 1, + ACLK_PERILP0_DIV_CON_SHIFT = 0, + ACLK_PERILP0_DIV_CON_MASK = 0x1f, + + /* CLKSEL_CON25 */ + PCLK_PERILP1_DIV_CON_SHIFT = 8, + PCLK_PERILP1_DIV_CON_MASK = 0x7 << PCLK_PERILP1_DIV_CON_SHIFT, + HCLK_PERILP1_PLL_SEL_SHIFT = 7, + HCLK_PERILP1_PLL_SEL_MASK = 1 << HCLK_PERILP1_PLL_SEL_SHIFT, + HCLK_PERILP1_PLL_SEL_CPLL = 0, + HCLK_PERILP1_PLL_SEL_GPLL = 1, + HCLK_PERILP1_DIV_CON_SHIFT = 0, + HCLK_PERILP1_DIV_CON_MASK = 0x1f, + + /* CLKSEL_CON26 */ + CLK_SARADC_DIV_CON_SHIFT = 8, + CLK_SARADC_DIV_CON_MASK = 0xff << CLK_SARADC_DIV_CON_SHIFT, + + /* CLKSEL_CON27 */ + CLK_TSADC_SEL_X24M = 0x0, + CLK_TSADC_SEL_SHIFT = 15, + CLK_TSADC_SEL_MASK = 1 << CLK_TSADC_SEL_SHIFT, + CLK_TSADC_DIV_CON_SHIFT = 0, + CLK_TSADC_DIV_CON_MASK = 0x3ff, + + /* CLKSEL_CON47 & CLKSEL_CON48 */ + ACLK_VOP_PLL_SEL_SHIFT = 6, + ACLK_VOP_PLL_SEL_MASK = 0x3 << ACLK_VOP_PLL_SEL_SHIFT, + ACLK_VOP_PLL_SEL_CPLL = 0x1, + ACLK_VOP_DIV_CON_SHIFT = 0, + ACLK_VOP_DIV_CON_MASK = 0x1f << ACLK_VOP_DIV_CON_SHIFT, + + /* CLKSEL_CON49 & CLKSEL_CON50 */ + DCLK_VOP_DCLK_SEL_SHIFT = 11, + DCLK_VOP_DCLK_SEL_MASK = 1 << DCLK_VOP_DCLK_SEL_SHIFT, + DCLK_VOP_DCLK_SEL_DIVOUT = 0, + DCLK_VOP_PLL_SEL_SHIFT = 8, + DCLK_VOP_PLL_SEL_MASK = 3 << DCLK_VOP_PLL_SEL_SHIFT, + DCLK_VOP_PLL_SEL_VPLL = 0, + DCLK_VOP_DIV_CON_MASK = 0xff, + DCLK_VOP_DIV_CON_SHIFT = 0, + + /* CLKSEL_CON58 */ + CLK_SPI_PLL_SEL_MASK = 1, + CLK_SPI_PLL_SEL_CPLL = 0, + CLK_SPI_PLL_SEL_GPLL = 1, + CLK_SPI_PLL_DIV_CON_MASK = 0x7f, + CLK_SPI5_PLL_DIV_CON_SHIFT = 8, + CLK_SPI5_PLL_SEL_SHIFT = 15, + + /* CLKSEL_CON59 */ + CLK_SPI1_PLL_SEL_SHIFT = 15, + CLK_SPI1_PLL_DIV_CON_SHIFT = 8, + CLK_SPI0_PLL_SEL_SHIFT = 7, + CLK_SPI0_PLL_DIV_CON_SHIFT = 0, + + /* CLKSEL_CON60 */ + CLK_SPI4_PLL_SEL_SHIFT = 15, + CLK_SPI4_PLL_DIV_CON_SHIFT = 8, + CLK_SPI2_PLL_SEL_SHIFT = 7, + CLK_SPI2_PLL_DIV_CON_SHIFT = 0, + + /* CLKSEL_CON61 */ + CLK_I2C_PLL_SEL_MASK = 1, + CLK_I2C_PLL_SEL_CPLL = 0, + CLK_I2C_PLL_SEL_GPLL = 1, + CLK_I2C5_PLL_SEL_SHIFT = 15, + CLK_I2C5_DIV_CON_SHIFT = 8, + CLK_I2C1_PLL_SEL_SHIFT = 7, + CLK_I2C1_DIV_CON_SHIFT = 0, + + /* CLKSEL_CON62 */ + CLK_I2C6_PLL_SEL_SHIFT = 15, + CLK_I2C6_DIV_CON_SHIFT = 8, + CLK_I2C2_PLL_SEL_SHIFT = 7, + CLK_I2C2_DIV_CON_SHIFT = 0, + + /* CLKSEL_CON63 */ + CLK_I2C7_PLL_SEL_SHIFT = 15, + CLK_I2C7_DIV_CON_SHIFT = 8, + CLK_I2C3_PLL_SEL_SHIFT = 7, + CLK_I2C3_DIV_CON_SHIFT = 0, + + /* CRU_SOFTRST_CON4 */ + RESETN_DDR0_REQ_SHIFT = 8, + RESETN_DDR0_REQ_MASK = 1 << RESETN_DDR0_REQ_SHIFT, + RESETN_DDRPHY0_REQ_SHIFT = 9, + RESETN_DDRPHY0_REQ_MASK = 1 << RESETN_DDRPHY0_REQ_SHIFT, + RESETN_DDR1_REQ_SHIFT = 12, + RESETN_DDR1_REQ_MASK = 1 << RESETN_DDR1_REQ_SHIFT, + RESETN_DDRPHY1_REQ_SHIFT = 13, + RESETN_DDRPHY1_REQ_MASK = 1 << RESETN_DDRPHY1_REQ_SHIFT, +}; + +#define VCO_MAX_KHZ (3200 * (MHz / KHz)) +#define VCO_MIN_KHZ (800 * (MHz / KHz)) +#define OUTPUT_MAX_KHZ (3200 * (MHz / KHz)) +#define OUTPUT_MIN_KHZ (16 * (MHz / KHz)) + +/* + * the div restructions of pll in integer mode, these are defined in + * * CRU_*PLL_CON0 or PMUCRU_*PLL_CON0 + */ +#define PLL_DIV_MIN 16 +#define PLL_DIV_MAX 3200 + +/* + * How to calculate the PLL(from TRM V0.3 Part 1 Page 63): + * Formulas also embedded within the Fractional PLL Verilog model: + * If DSMPD = 1 (DSM is disabled, "integer mode") + * FOUTVCO = FREF / REFDIV * FBDIV + * FOUTPOSTDIV = FOUTVCO / POSTDIV1 / POSTDIV2 + * Where: + * FOUTVCO = Fractional PLL non-divided output frequency + * FOUTPOSTDIV = Fractional PLL divided output frequency + * (output of second post divider) + * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input) + * REFDIV = Fractional PLL input reference clock divider + * FBDIV = Integer value programmed into feedback divide + * + */ +static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div) +{ + /* All 8 PLLs have same VCO and output frequency range restrictions. */ + u32 vco_khz = OSC_HZ / 1000 * div->fbdiv / div->refdiv; + u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2; + + debug("PLL at %p: fbdiv=%d, refdiv=%d, postdiv1=%d, " + "postdiv2=%d, vco=%u khz, output=%u khz\n", + pll_con, div->fbdiv, div->refdiv, div->postdiv1, + div->postdiv2, vco_khz, output_khz); + assert(vco_khz >= VCO_MIN_KHZ && vco_khz <= VCO_MAX_KHZ && + output_khz >= OUTPUT_MIN_KHZ && output_khz <= OUTPUT_MAX_KHZ && + div->fbdiv >= PLL_DIV_MIN && div->fbdiv <= PLL_DIV_MAX); + + /* + * When power on or changing PLL setting, + * we must force PLL into slow mode to ensure output stable clock. + */ + rk_clrsetreg(&pll_con[3], PLL_MODE_MASK, + PLL_MODE_SLOW << PLL_MODE_SHIFT); + + /* use integer mode */ + rk_clrsetreg(&pll_con[3], PLL_DSMPD_MASK, + PLL_INTEGER_MODE << PLL_DSMPD_SHIFT); + + rk_clrsetreg(&pll_con[0], PLL_FBDIV_MASK, + div->fbdiv << PLL_FBDIV_SHIFT); + rk_clrsetreg(&pll_con[1], + PLL_POSTDIV2_MASK | PLL_POSTDIV1_MASK | + PLL_REFDIV_MASK | PLL_REFDIV_SHIFT, + (div->postdiv2 << PLL_POSTDIV2_SHIFT) | + (div->postdiv1 << PLL_POSTDIV1_SHIFT) | + (div->refdiv << PLL_REFDIV_SHIFT)); + + /* waiting for pll lock */ + while (!(readl(&pll_con[2]) & (1 << PLL_LOCK_STATUS_SHIFT))) + udelay(1); + + /* pll enter normal mode */ + rk_clrsetreg(&pll_con[3], PLL_MODE_MASK, + PLL_MODE_NORM << PLL_MODE_SHIFT); +} + +static int pll_para_config(u32 freq_hz, struct pll_div *div) +{ + u32 ref_khz = OSC_HZ / KHz, refdiv, fbdiv = 0; + u32 postdiv1, postdiv2 = 1; + u32 fref_khz; + u32 diff_khz, best_diff_khz; + const u32 max_refdiv = 63, max_fbdiv = 3200, min_fbdiv = 16; + const u32 max_postdiv1 = 7, max_postdiv2 = 7; + u32 vco_khz; + u32 freq_khz = freq_hz / KHz; + + if (!freq_hz) { + printf("%s: the frequency can't be 0 Hz\n", __func__); + return -1; + } + + postdiv1 = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz); + if (postdiv1 > max_postdiv1) { + postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); + postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2); + } + + vco_khz = freq_khz * postdiv1 * postdiv2; + + if (vco_khz < VCO_MIN_KHZ || vco_khz > VCO_MAX_KHZ || + postdiv2 > max_postdiv2) { + printf("%s: Cannot find out a supported VCO" + " for Frequency (%uHz).\n", __func__, freq_hz); + return -1; + } + + div->postdiv1 = postdiv1; + div->postdiv2 = postdiv2; + + best_diff_khz = vco_khz; + for (refdiv = 1; refdiv < max_refdiv && best_diff_khz; refdiv++) { + fref_khz = ref_khz / refdiv; + + fbdiv = vco_khz / fref_khz; + if ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv)) + continue; + diff_khz = vco_khz - fbdiv * fref_khz; + if (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) { + fbdiv++; + diff_khz = fref_khz - diff_khz; + } + + if (diff_khz >= best_diff_khz) + continue; + + best_diff_khz = diff_khz; + div->refdiv = refdiv; + div->fbdiv = fbdiv; + } + + if (best_diff_khz > 4 * (MHz/KHz)) { + printf("%s: Failed to match output frequency %u, " + "difference is %u Hz,exceed 4MHZ\n", __func__, freq_hz, + best_diff_khz * KHz); + return -1; + } + return 0; +} + +static void rkclk_init(struct rk3399_cru *cru) +{ + u32 aclk_div; + u32 hclk_div; + u32 pclk_div; + + /* + * some cru registers changed by bootrom, we'd better reset them to + * reset/default values described in TRM to avoid confusion in kernel. + * Please consider these three lines as a fix of bootrom bug. + */ + rk_clrsetreg(&cru->clksel_con[12], 0xffff, 0x4101); + rk_clrsetreg(&cru->clksel_con[19], 0xffff, 0x033f); + rk_clrsetreg(&cru->clksel_con[56], 0x0003, 0x0003); + + /* configure gpll cpll */ + rkclk_set_pll(&cru->gpll_con[0], &gpll_init_cfg); + rkclk_set_pll(&cru->cpll_con[0], &cpll_init_cfg); + + /* configure perihp aclk, hclk, pclk */ + aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1; + assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); + + hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1; + assert((hclk_div + 1) * PERIHP_HCLK_HZ == + PERIHP_ACLK_HZ && (hclk_div < 0x4)); + + pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1; + assert((pclk_div + 1) * PERIHP_PCLK_HZ == + PERIHP_ACLK_HZ && (pclk_div < 0x7)); + + rk_clrsetreg(&cru->clksel_con[14], + PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK | + ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK, + pclk_div << PCLK_PERIHP_DIV_CON_SHIFT | + hclk_div << HCLK_PERIHP_DIV_CON_SHIFT | + ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT | + aclk_div << ACLK_PERIHP_DIV_CON_SHIFT); + + /* configure perilp0 aclk, hclk, pclk */ + aclk_div = GPLL_HZ / PERILP0_ACLK_HZ - 1; + assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); + + hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1; + assert((hclk_div + 1) * PERILP0_HCLK_HZ == + PERILP0_ACLK_HZ && (hclk_div < 0x4)); + + pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1; + assert((pclk_div + 1) * PERILP0_PCLK_HZ == + PERILP0_ACLK_HZ && (pclk_div < 0x7)); + + rk_clrsetreg(&cru->clksel_con[23], + PCLK_PERILP0_DIV_CON_MASK | HCLK_PERILP0_DIV_CON_MASK | + ACLK_PERILP0_PLL_SEL_MASK | ACLK_PERILP0_DIV_CON_MASK, + pclk_div << PCLK_PERILP0_DIV_CON_SHIFT | + hclk_div << HCLK_PERILP0_DIV_CON_SHIFT | + ACLK_PERILP0_PLL_SEL_GPLL << ACLK_PERILP0_PLL_SEL_SHIFT | + aclk_div << ACLK_PERILP0_DIV_CON_SHIFT); + + /* perilp1 hclk select gpll as source */ + hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1; + assert((hclk_div + 1) * PERILP1_HCLK_HZ == + GPLL_HZ && (hclk_div < 0x1f)); + + pclk_div = PERILP1_HCLK_HZ / PERILP1_HCLK_HZ - 1; + assert((pclk_div + 1) * PERILP1_HCLK_HZ == + PERILP1_HCLK_HZ && (hclk_div < 0x7)); + + rk_clrsetreg(&cru->clksel_con[25], + PCLK_PERILP1_DIV_CON_MASK | HCLK_PERILP1_DIV_CON_MASK | + HCLK_PERILP1_PLL_SEL_MASK, + pclk_div << PCLK_PERILP1_DIV_CON_SHIFT | + hclk_div << HCLK_PERILP1_DIV_CON_SHIFT | + HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT); +} + +void rk3399_configure_cpu(struct rk3399_cru *cru, + enum apll_l_frequencies apll_l_freq) +{ + u32 aclkm_div; + u32 pclk_dbg_div; + u32 atclk_div; + + rkclk_set_pll(&cru->apll_l_con[0], apll_l_cfgs[apll_l_freq]); + + aclkm_div = APLL_HZ / ACLKM_CORE_HZ - 1; + assert((aclkm_div + 1) * ACLKM_CORE_HZ == APLL_HZ && + aclkm_div < 0x1f); + + pclk_dbg_div = APLL_HZ / PCLK_DBG_HZ - 1; + assert((pclk_dbg_div + 1) * PCLK_DBG_HZ == APLL_HZ && + pclk_dbg_div < 0x1f); + + atclk_div = APLL_HZ / ATCLK_CORE_HZ - 1; + assert((atclk_div + 1) * ATCLK_CORE_HZ == APLL_HZ && + atclk_div < 0x1f); + + rk_clrsetreg(&cru->clksel_con[0], + ACLKM_CORE_L_DIV_CON_MASK | CLK_CORE_L_PLL_SEL_MASK | + CLK_CORE_L_DIV_MASK, + aclkm_div << ACLKM_CORE_L_DIV_CON_SHIFT | + CLK_CORE_L_PLL_SEL_ALPLL << CLK_CORE_L_PLL_SEL_SHIFT | + 0 << CLK_CORE_L_DIV_SHIFT); + + rk_clrsetreg(&cru->clksel_con[1], + PCLK_DBG_L_DIV_MASK | ATCLK_CORE_L_DIV_MASK, + pclk_dbg_div << PCLK_DBG_L_DIV_SHIFT | + atclk_div << ATCLK_CORE_L_DIV_SHIFT); +} +#define I2C_CLK_REG_MASK(bus) \ + (I2C_DIV_CON_MASK << \ + CLK_I2C ##bus## _DIV_CON_SHIFT | \ + CLK_I2C_PLL_SEL_MASK << \ + CLK_I2C ##bus## _PLL_SEL_SHIFT) + +#define I2C_CLK_REG_VALUE(bus, clk_div) \ + ((clk_div - 1) << \ + CLK_I2C ##bus## _DIV_CON_SHIFT | \ + CLK_I2C_PLL_SEL_GPLL << \ + CLK_I2C ##bus## _PLL_SEL_SHIFT) + +#define I2C_CLK_DIV_VALUE(con, bus) \ + (con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & \ + I2C_DIV_CON_MASK; + +static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id) +{ + u32 div, con; + + switch (clk_id) { + case SCLK_I2C1: + con = readl(&cru->clksel_con[61]); + div = I2C_CLK_DIV_VALUE(con, 1); + break; + case SCLK_I2C2: + con = readl(&cru->clksel_con[62]); + div = I2C_CLK_DIV_VALUE(con, 2); + break; + case SCLK_I2C3: + con = readl(&cru->clksel_con[63]); + div = I2C_CLK_DIV_VALUE(con, 3); + break; + case SCLK_I2C5: + con = readl(&cru->clksel_con[61]); + div = I2C_CLK_DIV_VALUE(con, 5); + break; + case SCLK_I2C6: + con = readl(&cru->clksel_con[62]); + div = I2C_CLK_DIV_VALUE(con, 6); + break; + case SCLK_I2C7: + con = readl(&cru->clksel_con[63]); + div = I2C_CLK_DIV_VALUE(con, 7); + break; + default: + printf("do not support this i2c bus\n"); + return -EINVAL; + } + + return DIV_TO_RATE(GPLL_HZ, div); +} + +static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz) +{ + int src_clk_div; + + /* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll*/ + src_clk_div = GPLL_HZ / hz; + assert(src_clk_div - 1 < 127); + + switch (clk_id) { + case SCLK_I2C1: + rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(1), + I2C_CLK_REG_VALUE(1, src_clk_div)); + break; + case SCLK_I2C2: + rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(2), + I2C_CLK_REG_VALUE(2, src_clk_div)); + break; + case SCLK_I2C3: + rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(3), + I2C_CLK_REG_VALUE(3, src_clk_div)); + break; + case SCLK_I2C5: + rk_clrsetreg(&cru->clksel_con[61], I2C_CLK_REG_MASK(5), + I2C_CLK_REG_VALUE(5, src_clk_div)); + break; + case SCLK_I2C6: + rk_clrsetreg(&cru->clksel_con[62], I2C_CLK_REG_MASK(6), + I2C_CLK_REG_VALUE(6, src_clk_div)); + break; + case SCLK_I2C7: + rk_clrsetreg(&cru->clksel_con[63], I2C_CLK_REG_MASK(7), + I2C_CLK_REG_VALUE(7, src_clk_div)); + break; + default: + printf("do not support this i2c bus\n"); + return -EINVAL; + } + + return DIV_TO_RATE(GPLL_HZ, src_clk_div); +} + +static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz) +{ + struct pll_div vpll_config = {0}; + int aclk_vop = 198*MHz; + void *aclkreg_addr, *dclkreg_addr; + u32 div; + + switch (clk_id) { + case DCLK_VOP0: + aclkreg_addr = &cru->clksel_con[47]; + dclkreg_addr = &cru->clksel_con[49]; + break; + case DCLK_VOP1: + aclkreg_addr = &cru->clksel_con[48]; + dclkreg_addr = &cru->clksel_con[50]; + break; + default: + return -EINVAL; + } + /* vop aclk source clk: cpll */ + div = CPLL_HZ / aclk_vop; + assert(div - 1 < 32); + + rk_clrsetreg(aclkreg_addr, + ACLK_VOP_PLL_SEL_MASK | ACLK_VOP_DIV_CON_MASK, + ACLK_VOP_PLL_SEL_CPLL << ACLK_VOP_PLL_SEL_SHIFT | + (div - 1) << ACLK_VOP_DIV_CON_SHIFT); + + /* vop dclk source from vpll, and equals to vpll(means div == 1) */ + if (pll_para_config(hz, &vpll_config)) + return -1; + + rkclk_set_pll(&cru->vpll_con[0], &vpll_config); + + rk_clrsetreg(dclkreg_addr, + DCLK_VOP_DCLK_SEL_MASK | DCLK_VOP_PLL_SEL_MASK| + DCLK_VOP_DIV_CON_MASK, + DCLK_VOP_DCLK_SEL_DIVOUT << DCLK_VOP_DCLK_SEL_SHIFT | + DCLK_VOP_PLL_SEL_VPLL << DCLK_VOP_PLL_SEL_SHIFT | + (1 - 1) << DCLK_VOP_DIV_CON_SHIFT); + + return hz; +} + +static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id) +{ + u32 div, con; + + switch (clk_id) { + case SCLK_SDMMC: + con = readl(&cru->clksel_con[16]); + break; + case SCLK_EMMC: + con = readl(&cru->clksel_con[21]); + break; + default: + return -EINVAL; + } + div = (con & CLK_EMMC_DIV_CON_MASK) >> CLK_EMMC_DIV_CON_SHIFT; + + if ((con & CLK_EMMC_PLL_MASK) >> CLK_EMMC_PLL_SHIFT + == CLK_EMMC_PLL_SEL_24M) + return DIV_TO_RATE(24*1024*1024, div); + else + return DIV_TO_RATE(GPLL_HZ, div); +} + +static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru, + ulong clk_id, ulong set_rate) +{ + int src_clk_div; + int aclk_emmc = 198*MHz; + + switch (clk_id) { + case SCLK_SDMMC: + /* Select clk_sdmmc source from GPLL by default */ + src_clk_div = GPLL_HZ / set_rate; + + if (src_clk_div > 127) { + /* use 24MHz source for 400KHz clock */ + src_clk_div = 24*1024*1024 / set_rate; + rk_clrsetreg(&cru->clksel_con[16], + CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, + CLK_EMMC_PLL_SEL_24M << CLK_EMMC_PLL_SHIFT | + (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); + } else { + rk_clrsetreg(&cru->clksel_con[16], + CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, + CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT | + (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); + } + break; + case SCLK_EMMC: + /* Select aclk_emmc source from GPLL */ + src_clk_div = GPLL_HZ / aclk_emmc; + assert(src_clk_div - 1 < 31); + + rk_clrsetreg(&cru->clksel_con[21], + ACLK_EMMC_PLL_SEL_MASK | ACLK_EMMC_DIV_CON_MASK, + ACLK_EMMC_PLL_SEL_GPLL << ACLK_EMMC_PLL_SEL_SHIFT | + (src_clk_div - 1) << ACLK_EMMC_DIV_CON_SHIFT); + + /* Select clk_emmc source from GPLL too */ + src_clk_div = GPLL_HZ / set_rate; + assert(src_clk_div - 1 < 127); + + rk_clrsetreg(&cru->clksel_con[22], + CLK_EMMC_PLL_MASK | CLK_EMMC_DIV_CON_MASK, + CLK_EMMC_PLL_SEL_GPLL << CLK_EMMC_PLL_SHIFT | + (src_clk_div - 1) << CLK_EMMC_DIV_CON_SHIFT); + break; + default: + return -EINVAL; + } + return rk3399_mmc_get_clk(cru, clk_id); +} + +static ulong rk3399_clk_get_rate(struct clk *clk) +{ + struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); + ulong rate = 0; + + switch (clk->id) { + case 0 ... 63: + return 0; + case SCLK_SDMMC: + case SCLK_EMMC: + rate = rk3399_mmc_get_clk(priv->cru, clk->id); + break; + case SCLK_I2C1: + case SCLK_I2C2: + case SCLK_I2C3: + case SCLK_I2C5: + case SCLK_I2C6: + case SCLK_I2C7: + rate = rk3399_i2c_get_clk(priv->cru, clk->id); + break; + case DCLK_VOP0: + case DCLK_VOP1: + break; + default: + return -ENOENT; + } + + return rate; +} + +static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) +{ + struct rk3399_clk_priv *priv = dev_get_priv(clk->dev); + ulong ret = 0; + + switch (clk->id) { + case 0 ... 63: + return 0; + case SCLK_SDMMC: + case SCLK_EMMC: + ret = rk3399_mmc_set_clk(priv->cru, clk->id, rate); + break; + case SCLK_I2C1: + case SCLK_I2C2: + case SCLK_I2C3: + case SCLK_I2C5: + case SCLK_I2C6: + case SCLK_I2C7: + ret = rk3399_i2c_set_clk(priv->cru, clk->id, rate); + break; + case DCLK_VOP0: + case DCLK_VOP1: + rate = rk3399_vop_set_clk(priv->cru, clk->id, rate); + break; + default: + return -ENOENT; + } + + return ret; +} + +static struct clk_ops rk3399_clk_ops = { + .get_rate = rk3399_clk_get_rate, + .set_rate = rk3399_clk_set_rate, +}; + +void *rockchip_get_cru(void) +{ + struct udevice *dev; + fdt_addr_t *addr; + int ret; + + ret = uclass_get_device_by_name(UCLASS_CLK, "clk_rk3399", &dev); + if (ret) + return ERR_PTR(ret); + + addr = dev_get_addr_ptr(dev); + if ((fdt_addr_t)addr == FDT_ADDR_T_NONE) + return ERR_PTR(-EINVAL); + + return addr; +} + +static int rk3399_clk_probe(struct udevice *dev) +{ + struct rk3399_clk_priv *priv = dev_get_priv(dev); + + rkclk_init(priv->cru); + + return 0; +} + +static int rk3399_clk_ofdata_to_platdata(struct udevice *dev) +{ + struct rk3399_clk_priv *priv = dev_get_priv(dev); + + priv->cru = (struct rk3399_cru *)dev_get_addr(dev); + + return 0; +} + +static int rk3399_clk_bind(struct udevice *dev) +{ + int ret; + + /* The reset driver does not have a device node, so bind it here */ + ret = device_bind_driver(gd->dm_root, "rk3399_sysreset", "reset", &dev); + if (ret) + printf("Warning: No RK3399 reset driver: ret=%d\n", ret); + + return 0; +} + +static const struct udevice_id rk3399_clk_ids[] = { + { .compatible = "rockchip,rk3399-cru" }, + { } +}; + +U_BOOT_DRIVER(clk_rk3399) = { + .name = "clk_rk3399", + .id = UCLASS_CLK, + .of_match = rk3399_clk_ids, + .priv_auto_alloc_size = sizeof(struct rk3399_clk_priv), + .ofdata_to_platdata = rk3399_clk_ofdata_to_platdata, + .ops = &rk3399_clk_ops, + .bind = rk3399_clk_bind, + .probe = rk3399_clk_probe, +}; diff --git a/drivers/clk/tegra/Kconfig b/drivers/clk/tegra/Kconfig new file mode 100644 index 00000000000..659fe022c2a --- /dev/null +++ b/drivers/clk/tegra/Kconfig @@ -0,0 +1,6 @@ +config TEGRA186_CLOCK + bool "Enable Tegra186 BPMP-based clock driver" + depends on TEGRA186_BPMP + help + Enable support for manipulating Tegra's on-SoC clocks via IPC + requests to the BPMP (Boot and Power Management Processor). diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile new file mode 100644 index 00000000000..f32998ccc27 --- /dev/null +++ b/drivers/clk/tegra/Makefile @@ -0,0 +1,5 @@ +# Copyright (c) 2016, NVIDIA CORPORATION. +# +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_TEGRA186_CLOCK) += tegra186-clk.o diff --git a/drivers/clk/tegra/tegra186-clk.c b/drivers/clk/tegra/tegra186-clk.c new file mode 100644 index 00000000000..075cb464cf6 --- /dev/null +++ b/drivers/clk/tegra/tegra186-clk.c @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <misc.h> +#include <asm/arch-tegra/bpmp_abi.h> + +static ulong tegra186_clk_get_rate(struct clk *clk) +{ + struct mrq_clk_request req; + struct mrq_clk_response resp; + int ret; + + debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev, + clk->id); + + req.cmd_and_id = (CMD_CLK_GET_RATE << 24) | clk->id; + + ret = misc_call(clk->dev->parent, MRQ_CLK, &req, sizeof(req), &resp, + sizeof(resp)); + if (ret < 0) + return ret; + + return resp.clk_get_rate.rate; +} + +static ulong tegra186_clk_set_rate(struct clk *clk, ulong rate) +{ + struct mrq_clk_request req; + struct mrq_clk_response resp; + int ret; + + debug("%s(clk=%p, rate=%lu) (dev=%p, id=%lu)\n", __func__, clk, rate, + clk->dev, clk->id); + + req.cmd_and_id = (CMD_CLK_SET_RATE << 24) | clk->id; + req.clk_set_rate.rate = rate; + + ret = misc_call(clk->dev->parent, MRQ_CLK, &req, sizeof(req), &resp, + sizeof(resp)); + if (ret < 0) + return ret; + + return resp.clk_set_rate.rate; +} + +static int tegra186_clk_en_dis(struct clk *clk, + enum mrq_reset_commands cmd) +{ + struct mrq_clk_request req; + struct mrq_clk_response resp; + int ret; + + req.cmd_and_id = (cmd << 24) | clk->id; + + ret = misc_call(clk->dev->parent, MRQ_CLK, &req, sizeof(req), &resp, + sizeof(resp)); + if (ret < 0) + return ret; + + return 0; +} + +static int tegra186_clk_enable(struct clk *clk) +{ + debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev, + clk->id); + + return tegra186_clk_en_dis(clk, CMD_CLK_ENABLE); +} + +static int tegra186_clk_disable(struct clk *clk) +{ + debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev, + clk->id); + + return tegra186_clk_en_dis(clk, CMD_CLK_DISABLE); +} + +static struct clk_ops tegra186_clk_ops = { + .get_rate = tegra186_clk_get_rate, + .set_rate = tegra186_clk_set_rate, + .enable = tegra186_clk_enable, + .disable = tegra186_clk_disable, +}; + +static int tegra186_clk_probe(struct udevice *dev) +{ + debug("%s(dev=%p)\n", __func__, dev); + + return 0; +} + +U_BOOT_DRIVER(tegra186_clk) = { + .name = "tegra186_clk", + .id = UCLASS_CLK, + .probe = tegra186_clk_probe, + .ops = &tegra186_clk_ops, +}; diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c index 2f5d4d83910..a91924e8a4e 100644 --- a/drivers/clk/uniphier/clk-uniphier-core.c +++ b/drivers/clk/uniphier/clk-uniphier-core.c @@ -1,11 +1,11 @@ /* - * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> -#include <mapmem.h> #include <linux/bitops.h> #include <linux/io.h> #include <linux/sizes.h> @@ -137,7 +137,7 @@ int uniphier_clk_probe(struct udevice *dev) if (addr == FDT_ADDR_T_NONE) return -EINVAL; - priv->base = map_sysmem(addr, SZ_4K); + priv->base = devm_ioremap(dev, addr, SZ_4K); if (!priv->base) return -ENOMEM; @@ -145,12 +145,3 @@ int uniphier_clk_probe(struct udevice *dev) return 0; } - -int uniphier_clk_remove(struct udevice *dev) -{ - struct uniphier_clk_priv *priv = dev_get_priv(dev); - - unmap_sysmem(priv->base); - - return 0; -} diff --git a/drivers/clk/uniphier/clk-uniphier-mio.c b/drivers/clk/uniphier/clk-uniphier-mio.c index 2dd3fc074a7..2eea5ebc2ae 100644 --- a/drivers/clk/uniphier/clk-uniphier-mio.c +++ b/drivers/clk/uniphier/clk-uniphier-mio.c @@ -1,5 +1,6 @@ /* - * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -179,7 +180,6 @@ U_BOOT_DRIVER(uniphier_mio_clk) = { .id = UCLASS_CLK, .of_match = uniphier_mio_clk_match, .probe = uniphier_clk_probe, - .remove = uniphier_clk_remove, .priv_auto_alloc_size = sizeof(struct uniphier_clk_priv), .ops = &uniphier_clk_ops, }; diff --git a/drivers/clk/uniphier/clk-uniphier.h b/drivers/clk/uniphier/clk-uniphier.h index 560b3f81129..18aa88849b3 100644 --- a/drivers/clk/uniphier/clk-uniphier.h +++ b/drivers/clk/uniphier/clk-uniphier.h @@ -1,5 +1,6 @@ /* - * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -52,6 +53,5 @@ struct uniphier_clk_priv { extern const struct clk_ops uniphier_clk_ops; int uniphier_clk_probe(struct udevice *dev); -int uniphier_clk_remove(struct udevice *dev); #endif /* __CLK_UNIPHIER_H__ */ diff --git a/drivers/core/device-remove.c b/drivers/core/device-remove.c index 0e56b23fbbf..a7f77b4a21d 100644 --- a/drivers/core/device-remove.c +++ b/drivers/core/device-remove.c @@ -112,7 +112,7 @@ int device_unbind(struct udevice *dev) devres_release_all(dev); - if (dev->flags & DM_NAME_ALLOCED) + if (dev->flags & DM_FLAG_NAME_ALLOCED) free((char *)dev->name); free(dev); diff --git a/drivers/core/device.c b/drivers/core/device.c index eb75b1734f9..b737f1c7890 100644 --- a/drivers/core/device.c +++ b/drivers/core/device.c @@ -10,6 +10,7 @@ */ #include <common.h> +#include <asm/io.h> #include <fdtdec.h> #include <fdt_support.h> #include <malloc.h> @@ -29,7 +30,7 @@ DECLARE_GLOBAL_DATA_PTR; static int device_bind_common(struct udevice *parent, const struct driver *drv, const char *name, void *platdata, ulong driver_data, int of_offset, - struct udevice **devp) + uint of_platdata_size, struct udevice **devp) { struct udevice *dev; struct uclass *uc; @@ -83,12 +84,29 @@ static int device_bind_common(struct udevice *parent, const struct driver *drv, } } - if (!dev->platdata && drv->platdata_auto_alloc_size) { - dev->flags |= DM_FLAG_ALLOC_PDATA; - dev->platdata = calloc(1, drv->platdata_auto_alloc_size); - if (!dev->platdata) { - ret = -ENOMEM; - goto fail_alloc1; + if (drv->platdata_auto_alloc_size) { + bool alloc = !platdata; + + if (CONFIG_IS_ENABLED(OF_PLATDATA)) { + if (of_platdata_size) { + dev->flags |= DM_FLAG_OF_PLATDATA; + if (of_platdata_size < + drv->platdata_auto_alloc_size) + alloc = true; + } + } + if (alloc) { + dev->flags |= DM_FLAG_ALLOC_PDATA; + dev->platdata = calloc(1, + drv->platdata_auto_alloc_size); + if (!dev->platdata) { + ret = -ENOMEM; + goto fail_alloc1; + } + if (CONFIG_IS_ENABLED(OF_PLATDATA) && platdata) { + memcpy(dev->platdata, platdata, + of_platdata_size); + } } } @@ -201,14 +219,14 @@ int device_bind_with_driver_data(struct udevice *parent, struct udevice **devp) { return device_bind_common(parent, drv, name, NULL, driver_data, - of_offset, devp); + of_offset, 0, devp); } int device_bind(struct udevice *parent, const struct driver *drv, const char *name, void *platdata, int of_offset, struct udevice **devp) { - return device_bind_common(parent, drv, name, platdata, 0, of_offset, + return device_bind_common(parent, drv, name, platdata, 0, of_offset, 0, devp); } @@ -216,6 +234,7 @@ int device_bind_by_name(struct udevice *parent, bool pre_reloc_only, const struct driver_info *info, struct udevice **devp) { struct driver *drv; + uint platdata_size = 0; drv = lists_driver_lookup_name(info->name); if (!drv) @@ -223,8 +242,11 @@ int device_bind_by_name(struct udevice *parent, bool pre_reloc_only, if (pre_reloc_only && !(drv->flags & DM_FLAG_PRE_RELOC)) return -EPERM; - return device_bind(parent, drv, info->name, (void *)info->platdata, - -1, devp); +#if CONFIG_IS_ENABLED(OF_PLATDATA) + platdata_size = info->platdata_size; +#endif + return device_bind_common(parent, drv, info->name, + (void *)info->platdata, 0, -1, platdata_size, devp); } static void *alloc_priv(int size, uint flags) @@ -607,7 +629,7 @@ const char *dev_get_uclass_name(struct udevice *dev) fdt_addr_t dev_get_addr_index(struct udevice *dev, int index) { -#if CONFIG_IS_ENABLED(OF_CONTROL) +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) fdt_addr_t addr; if (CONFIG_IS_ENABLED(OF_TRANSLATE)) { @@ -649,7 +671,7 @@ fdt_addr_t dev_get_addr_index(struct udevice *dev, int index) addr = fdtdec_get_addr_size_auto_parent(gd->fdt_blob, dev->parent->of_offset, dev->of_offset, "reg", - index, NULL); + index, NULL, false); if (CONFIG_IS_ENABLED(SIMPLE_BUS) && addr != FDT_ADDR_T_NONE) { if (device_get_uclass_id(dev->parent) == UCLASS_SIMPLE_BUS) @@ -697,6 +719,16 @@ void *dev_get_addr_ptr(struct udevice *dev) return (void *)(uintptr_t)dev_get_addr_index(dev, 0); } +void *dev_map_physmem(struct udevice *dev, unsigned long size) +{ + fdt_addr_t addr = dev_get_addr(dev); + + if (addr == FDT_ADDR_T_NONE) + return NULL; + + return map_physmem(addr, size, MAP_NOCACHE); +} + bool device_has_children(struct udevice *dev) { return !list_empty(&dev->child_head); @@ -727,7 +759,7 @@ bool device_is_last_sibling(struct udevice *dev) void device_set_name_alloced(struct udevice *dev) { - dev->flags |= DM_NAME_ALLOCED; + dev->flags |= DM_FLAG_NAME_ALLOCED; } int device_set_name(struct udevice *dev, const char *name) diff --git a/drivers/core/lists.c b/drivers/core/lists.c index 0c277177909..6a634e69518 100644 --- a/drivers/core/lists.c +++ b/drivers/core/lists.c @@ -99,7 +99,7 @@ int device_bind_driver_to_node(struct udevice *parent, const char *drv_name, return 0; } -#if CONFIG_IS_ENABLED(OF_CONTROL) +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) /** * driver_check_compatible() - Check if a driver is compatible with this node * diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c index 519832f1733..0299ff08793 100644 --- a/drivers/core/regmap.c +++ b/drivers/core/regmap.c @@ -15,6 +15,49 @@ DECLARE_GLOBAL_DATA_PTR; +static struct regmap *regmap_alloc_count(int count) +{ + struct regmap *map; + + map = malloc(sizeof(struct regmap)); + if (!map) + return NULL; + if (count <= 1) { + map->range = &map->base_range; + } else { + map->range = malloc(count * sizeof(struct regmap_range)); + if (!map->range) { + free(map); + return NULL; + } + } + map->range_count = count; + + return map; +} + +#if CONFIG_IS_ENABLED(OF_PLATDATA) +int regmap_init_mem_platdata(struct udevice *dev, u32 *reg, int count, + struct regmap **mapp) +{ + struct regmap_range *range; + struct regmap *map; + + map = regmap_alloc_count(count); + if (!map) + return -ENOMEM; + + map->base = *reg; + for (range = map->range; count > 0; reg += 2, range++, count--) { + range->start = *reg; + range->size = reg[1]; + } + + *mapp = map; + + return 0; +} +#else int regmap_init_mem(struct udevice *dev, struct regmap **mapp) { const void *blob = gd->fdt_blob; @@ -37,22 +80,11 @@ int regmap_init_mem(struct udevice *dev, struct regmap **mapp) if (!cell || !count) return -EINVAL; - map = malloc(sizeof(struct regmap)); + map = regmap_alloc_count(count); if (!map) return -ENOMEM; - if (count <= 1) { - map->range = &map->base_range; - } else { - map->range = malloc(count * sizeof(struct regmap_range)); - if (!map->range) { - free(map); - return -ENOMEM; - } - } - map->base = fdtdec_get_number(cell, addr_len); - map->range_count = count; for (range = map->range; count > 0; count--, cell += both_len, range++) { @@ -64,6 +96,7 @@ int regmap_init_mem(struct udevice *dev, struct regmap **mapp) return 0; } +#endif void *regmap_get_range(struct regmap *map, unsigned int range_num) { diff --git a/drivers/core/root.c b/drivers/core/root.c index 95886add238..33dc9c0b2db 100644 --- a/drivers/core/root.c +++ b/drivers/core/root.c @@ -188,7 +188,7 @@ int dm_scan_platdata(bool pre_reloc_only) return ret; } -#if CONFIG_IS_ENABLED(OF_CONTROL) +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) int dm_scan_fdt_node(struct udevice *parent, const void *blob, int offset, bool pre_reloc_only) { @@ -218,6 +218,15 @@ int dm_scan_fdt_node(struct udevice *parent, const void *blob, int offset, return ret; } +int dm_scan_fdt_dev(struct udevice *dev) +{ + if (dev->of_offset == -1) + return 0; + + return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, + gd->flags & GD_FLG_RELOC ? false : true); +} + int dm_scan_fdt(const void *blob, bool pre_reloc_only) { return dm_scan_fdt_node(gd->dm_root, blob, 0, pre_reloc_only); @@ -244,7 +253,7 @@ int dm_init_and_scan(bool pre_reloc_only) return ret; } - if (CONFIG_IS_ENABLED(OF_CONTROL)) { + if (CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)) { ret = dm_scan_fdt(gd->fdt_blob, pre_reloc_only); if (ret) { debug("dm_scan_fdt() failed: %d\n", ret); diff --git a/drivers/core/simple-bus.c b/drivers/core/simple-bus.c index 1a9c864ef37..5c955da3346 100644 --- a/drivers/core/simple-bus.c +++ b/drivers/core/simple-bus.c @@ -6,7 +6,6 @@ #include <common.h> #include <dm.h> -#include <dm/root.h> DECLARE_GLOBAL_DATA_PTR; @@ -41,7 +40,7 @@ static int simple_bus_post_bind(struct udevice *dev) plat->size = cell[2]; } - return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false); + return dm_scan_fdt_dev(dev); } UCLASS_DRIVER(simple_bus) = { diff --git a/drivers/core/syscon-uclass.c b/drivers/core/syscon-uclass.c index e03f46af573..01bd9683a7a 100644 --- a/drivers/core/syscon-uclass.c +++ b/drivers/core/syscon-uclass.c @@ -29,7 +29,20 @@ static int syscon_pre_probe(struct udevice *dev) { struct syscon_uc_info *priv = dev_get_uclass_priv(dev); + /* + * With OF_PLATDATA we really have no way of knowing the format of + * the device-specific platform data. So we assume that it starts with + * a 'reg' member, and this holds a single address and size. Drivers + * using OF_PLATDATA will need to ensure that this is true. + */ +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct syscon_base_platdata *plat = dev_get_platdata(dev); + + return regmap_init_mem_platdata(dev, plat->reg, ARRAY_SIZE(plat->reg), + &priv->regmap); +#else return regmap_init_mem(dev, &priv->regmap); +#endif } int syscon_get_by_driver_data(ulong driver_data, struct udevice **devp) diff --git a/drivers/core/uclass.c b/drivers/core/uclass.c index 1141ce1ba3c..de602ae52dc 100644 --- a/drivers/core/uclass.c +++ b/drivers/core/uclass.c @@ -311,6 +311,26 @@ static int uclass_find_device_by_phandle(enum uclass_id id, } #endif +int uclass_get_device_by_driver(enum uclass_id id, + const struct driver *find_drv, + struct udevice **devp) +{ + struct udevice *dev; + struct uclass *uc; + int ret; + + ret = uclass_get(id, &uc); + if (ret) + return ret; + + list_for_each_entry(dev, &uc->dev_head, uclass_node) { + if (dev->driver == find_drv) + return uclass_get_device_tail(dev, 0, devp); + } + + return -ENODEV; +} + int uclass_get_device_tail(struct udevice *dev, int ret, struct udevice **devp) { diff --git a/drivers/crypto/fsl/desc.h b/drivers/crypto/fsl/desc.h index 1ac3a09dffe..081bce53cff 100644 --- a/drivers/crypto/fsl/desc.h +++ b/drivers/crypto/fsl/desc.h @@ -107,7 +107,7 @@ */ #define HDR_REVERSE 0x00000800 -/* Propogate DNR property to SharedDesc */ +/* Propagate DNR property to SharedDesc */ #define HDR_PROP_DNR 0x00000800 /* JobDesc/SharedDesc share property */ diff --git a/drivers/crypto/fsl/fsl_blob.c b/drivers/crypto/fsl/fsl_blob.c index 8b259212723..d24b8fc045d 100644 --- a/drivers/crypto/fsl/fsl_blob.c +++ b/drivers/crypto/fsl/fsl_blob.c @@ -18,7 +18,7 @@ int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len) int ret, i = 0; u32 *desc; - printf("\nDecapsulating data to form blob\n"); + printf("\nDecapsulating blob to get data\n"); desc = malloc(sizeof(int) * MAX_CAAM_DESCSIZE); if (!desc) { debug("Not enough memory for descriptor allocation\n"); @@ -27,12 +27,15 @@ int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len) inline_cnstr_jobdesc_blob_decap(desc, key_mod, src, dst, len); + debug("Descriptor dump:\n"); for (i = 0; i < 14; i++) - printf("%x\n", *(desc + i)); + debug("Word[%d]: %08x\n", i, *(desc + i)); ret = run_descriptor_jr(desc); if (ret) printf("Error in Decapsulation %d\n", ret); + else + printf("Decapsulation Success\n"); free(desc); return ret; @@ -51,12 +54,16 @@ int blob_encap(u8 *key_mod, u8 *src, u8 *dst, u32 len) } inline_cnstr_jobdesc_blob_encap(desc, key_mod, src, dst, len); + + debug("Descriptor dump:\n"); for (i = 0; i < 14; i++) - printf("%x\n", *(desc + i)); + debug("Word[%d]: %08x\n", i, *(desc + i)); ret = run_descriptor_jr(desc); if (ret) printf("Error in Encapsulation %d\n", ret); + else + printf("Encapsulation Success\n"); free(desc); return ret; diff --git a/drivers/crypto/fsl/fsl_rsa.c b/drivers/crypto/fsl/fsl_rsa.c index cf1c4c1d458..5471504b6e9 100644 --- a/drivers/crypto/fsl/fsl_rsa.c +++ b/drivers/crypto/fsl/fsl_rsa.c @@ -53,6 +53,7 @@ U_BOOT_DRIVER(fsl_rsa_mod_exp) = { .name = "fsl_rsa_mod_exp", .id = UCLASS_MOD_EXP, .ops = &fsl_mod_exp_ops, + .flags = DM_FLAG_PRE_RELOC, }; U_BOOT_DEVICE(fsl_rsa) = { diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index 510fa4e3760..4a8cc3295a4 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -599,10 +599,27 @@ int sec_init_idx(uint8_t sec_idx) sec_out32(&sec->mcfgr, mcr); #ifdef CONFIG_FSL_CORENET +#ifdef CONFIG_SPL_BUILD + /* + * For SPL Build, Set the Liodns in SEC JR0 for + * creating PAMU entries corresponding to these. + * For normal build, these are set in set_liodns(). + */ + liodn_ns = CONFIG_SPL_JR0_LIODN_NS & JRNSLIODN_MASK; + liodn_s = CONFIG_SPL_JR0_LIODN_S & JRSLIODN_MASK; + + liodnr = sec_in32(&sec->jrliodnr[0].ls) & + ~(JRNSLIODN_MASK | JRSLIODN_MASK); + liodnr = liodnr | + (liodn_ns << JRNSLIODN_SHIFT) | + (liodn_s << JRSLIODN_SHIFT); + sec_out32(&sec->jrliodnr[0].ls, liodnr); +#else liodnr = sec_in32(&sec->jrliodnr[0].ls); liodn_ns = (liodnr & JRNSLIODN_MASK) >> JRNSLIODN_SHIFT; liodn_s = (liodnr & JRSLIODN_MASK) >> JRSLIODN_SHIFT; #endif +#endif ret = jr_init(sec_idx); if (ret < 0) { diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index 1d5cec662ce..24fd36602d2 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -709,7 +709,7 @@ static void set_timing_cfg_2(const unsigned int ctrl_num, | ((add_lat_mclk & 0xf) << 28) | ((cpo & 0x1f) << 23) | ((wr_lat & 0xf) << 19) - | ((wr_lat & 0x10) << 18) + | (((wr_lat & 0x10) >> 4) << 18) | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT) | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT) | ((cke_pls & 0x7) << 6) @@ -2212,7 +2212,7 @@ static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en, * Write leveling start time * The value use for the DQS_ADJUST for the first sample * when write leveling is enabled. It probably needs to be - * overriden per platform. + * overridden per platform. */ wrlvl_start = 0x8; /* diff --git a/drivers/dfu/dfu_mmc.c b/drivers/dfu/dfu_mmc.c index 78724e467b2..926ccbd2ef5 100644 --- a/drivers/dfu/dfu_mmc.c +++ b/drivers/dfu/dfu_mmc.c @@ -49,7 +49,7 @@ static int mmc_block_op(enum dfu_op op, struct dfu_entity *dfu, } if (dfu->data.mmc.hw_partition >= 0) { - part_num_bkp = mmc->block_dev.hwpart; + part_num_bkp = mmc_get_blk_desc(mmc)->hwpart; ret = blk_select_hwpart_devnum(IF_TYPE_MMC, dfu->data.mmc.dev_num, dfu->data.mmc.hw_partition); @@ -62,12 +62,11 @@ static int mmc_block_op(enum dfu_op op, struct dfu_entity *dfu, dfu->data.mmc.dev_num, blk_start, blk_count, buf); switch (op) { case DFU_OP_READ: - n = mmc->block_dev.block_read(&mmc->block_dev, blk_start, - blk_count, buf); + n = blk_dread(mmc_get_blk_desc(mmc), blk_start, blk_count, buf); break; case DFU_OP_WRITE: - n = mmc->block_dev.block_write(&mmc->block_dev, blk_start, - blk_count, buf); + n = blk_dwrite(mmc_get_blk_desc(mmc), blk_start, blk_count, + buf); break; default: error("Operation not supported\n"); @@ -356,7 +355,7 @@ int dfu_fill_entity_mmc(struct dfu_entity *dfu, char *devstr, char *s) } else if (!strcmp(entity_type, "part")) { disk_partition_t partinfo; - struct blk_desc *blk_dev = &mmc->block_dev; + struct blk_desc *blk_dev = mmc_get_blk_desc(mmc); int mmcdev = second_arg; int mmcpart = third_arg; diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c index 7e2f3e17a76..e0fb1b4e783 100644 --- a/drivers/fpga/fpga.c +++ b/drivers/fpga/fpga.c @@ -31,7 +31,7 @@ static void fpga_no_sup(char *fn, char *msg) else if (msg) printf("No support for %s.\n", msg); else - printf("No FPGA suport!\n"); + printf("No FPGA support!\n"); } diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 73b862dc0b2..8d9ab5237e8 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -30,7 +30,7 @@ config DWAPB_GPIO config ATMEL_PIO4 bool "ATMEL PIO4 driver" - depends on DM + depends on DM_GPIO default n help Say yes here to support the Atmel PIO4 driver. @@ -79,6 +79,13 @@ config PM8916_GPIO Power and reset buttons are placed in "pm8916_key" bank and have gpio numbers 0 and 1 respectively. +config PCF8575_GPIO + bool "PCF8575 I2C GPIO Expander driver" + depends on DM_GPIO && DM_I2C + help + Support for PCF8575 I2C 16-bit GPIO expander. Most of these + chips are from NXP and TI. + config ROCKCHIP_GPIO bool "Rockchip GPIO driver" depends on DM_GPIO diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 792d19186aa..89392264a4a 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -56,4 +56,5 @@ obj-$(CONFIG_HIKEY_GPIO) += hi6220_gpio.o obj-$(CONFIG_PIC32_GPIO) += pic32_gpio.o obj-$(CONFIG_MVEBU_GPIO) += mvebu_gpio.o obj-$(CONFIG_MSM_GPIO) += msm_gpio.o +obj-$(CONFIG_$(SPL_)PCF8575_GPIO) += pcf8575_gpio.o obj-$(CONFIG_PM8916_GPIO) += pm8916_gpio.o diff --git a/drivers/gpio/atmel_pio4.c b/drivers/gpio/atmel_pio4.c index d71f5259a34..7adea885650 100644 --- a/drivers/gpio/atmel_pio4.c +++ b/drivers/gpio/atmel_pio4.c @@ -7,45 +7,16 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> +#include <clk.h> #include <dm.h> +#include <fdtdec.h> +#include <dm/root.h> #include <asm/arch/hardware.h> +#include <asm/gpio.h> #include <mach/gpio.h> #include <mach/atmel_pio4.h> -#define ATMEL_PIO4_PINS_PER_BANK 32 - -/* - * Register Field Definitions - */ -#define ATMEL_PIO4_CFGR_FUNC (0x7 << 0) -#define ATMEL_PIO4_CFGR_FUNC_GPIO (0x0 << 0) -#define ATMEL_PIO4_CFGR_FUNC_PERIPH_A (0x1 << 0) -#define ATMEL_PIO4_CFGR_FUNC_PERIPH_B (0x2 << 0) -#define ATMEL_PIO4_CFGR_FUNC_PERIPH_C (0x3 << 0) -#define ATMEL_PIO4_CFGR_FUNC_PERIPH_D (0x4 << 0) -#define ATMEL_PIO4_CFGR_FUNC_PERIPH_E (0x5 << 0) -#define ATMEL_PIO4_CFGR_FUNC_PERIPH_F (0x6 << 0) -#define ATMEL_PIO4_CFGR_FUNC_PERIPH_G (0x7 << 0) -#define ATMEL_PIO4_CFGR_DIR (0x1 << 8) -#define ATMEL_PIO4_CFGR_PUEN (0x1 << 9) -#define ATMEL_PIO4_CFGR_PDEN (0x1 << 10) -#define ATMEL_PIO4_CFGR_IFEN (0x1 << 12) -#define ATMEL_PIO4_CFGR_IFSCEN (0x1 << 13) -#define ATMEL_PIO4_CFGR_OPD (0x1 << 14) -#define ATMEL_PIO4_CFGR_SCHMITT (0x1 << 15) -#define ATMEL_PIO4_CFGR_DRVSTR (0x3 << 16) -#define ATMEL_PIO4_CFGR_DRVSTR_LOW0 (0x0 << 16) -#define ATMEL_PIO4_CFGR_DRVSTR_LOW1 (0x1 << 16) -#define ATMEL_PIO4_CFGR_DRVSTR_MEDIUM (0x2 << 16) -#define ATMEL_PIO4_CFGR_DRVSTR_HIGH (0x3 << 16) -#define ATMEL_PIO4_CFGR_EVTSEL (0x7 << 24) -#define ATMEL_PIO4_CFGR_EVTSEL_FALLING (0x0 << 24) -#define ATMEL_PIO4_CFGR_EVTSEL_RISING (0x1 << 24) -#define ATMEL_PIO4_CFGR_EVTSEL_BOTH (0x2 << 24) -#define ATMEL_PIO4_CFGR_EVTSEL_LOW (0x3 << 24) -#define ATMEL_PIO4_CFGR_EVTSEL_HIGH (0x4 << 24) -#define ATMEL_PIO4_CFGR_PCFS (0x1 << 29) -#define ATMEL_PIO4_CFGR_ICFS (0x1 << 30) +DECLARE_GLOBAL_DATA_PTR; static struct atmel_pio4_port *atmel_pio4_port_base(u32 port) { @@ -79,7 +50,7 @@ static int atmel_pio4_config_io_func(u32 port, u32 pin, struct atmel_pio4_port *port_base; u32 reg, mask; - if (pin >= ATMEL_PIO4_PINS_PER_BANK) + if (pin >= ATMEL_PIO_NPINS_PER_BANK) return -ENODEV; port_base = atmel_pio4_port_base(port); @@ -88,7 +59,7 @@ static int atmel_pio4_config_io_func(u32 port, u32 pin, mask = 1 << pin; reg = func; - reg |= use_pullup ? ATMEL_PIO4_CFGR_PUEN : 0; + reg |= use_pullup ? ATMEL_PIO_PUEN_MASK : 0; writel(mask, &port_base->mskr); writel(reg, &port_base->cfgr); @@ -99,56 +70,56 @@ static int atmel_pio4_config_io_func(u32 port, u32 pin, int atmel_pio4_set_gpio(u32 port, u32 pin, u32 use_pullup) { return atmel_pio4_config_io_func(port, pin, - ATMEL_PIO4_CFGR_FUNC_GPIO, + ATMEL_PIO_CFGR_FUNC_GPIO, use_pullup); } int atmel_pio4_set_a_periph(u32 port, u32 pin, u32 use_pullup) { return atmel_pio4_config_io_func(port, pin, - ATMEL_PIO4_CFGR_FUNC_PERIPH_A, + ATMEL_PIO_CFGR_FUNC_PERIPH_A, use_pullup); } int atmel_pio4_set_b_periph(u32 port, u32 pin, u32 use_pullup) { return atmel_pio4_config_io_func(port, pin, - ATMEL_PIO4_CFGR_FUNC_PERIPH_B, + ATMEL_PIO_CFGR_FUNC_PERIPH_B, use_pullup); } int atmel_pio4_set_c_periph(u32 port, u32 pin, u32 use_pullup) { return atmel_pio4_config_io_func(port, pin, - ATMEL_PIO4_CFGR_FUNC_PERIPH_C, + ATMEL_PIO_CFGR_FUNC_PERIPH_C, use_pullup); } int atmel_pio4_set_d_periph(u32 port, u32 pin, u32 use_pullup) { return atmel_pio4_config_io_func(port, pin, - ATMEL_PIO4_CFGR_FUNC_PERIPH_D, + ATMEL_PIO_CFGR_FUNC_PERIPH_D, use_pullup); } int atmel_pio4_set_e_periph(u32 port, u32 pin, u32 use_pullup) { return atmel_pio4_config_io_func(port, pin, - ATMEL_PIO4_CFGR_FUNC_PERIPH_E, + ATMEL_PIO_CFGR_FUNC_PERIPH_E, use_pullup); } int atmel_pio4_set_f_periph(u32 port, u32 pin, u32 use_pullup) { return atmel_pio4_config_io_func(port, pin, - ATMEL_PIO4_CFGR_FUNC_PERIPH_F, + ATMEL_PIO_CFGR_FUNC_PERIPH_F, use_pullup); } int atmel_pio4_set_g_periph(u32 port, u32 pin, u32 use_pullup) { return atmel_pio4_config_io_func(port, pin, - ATMEL_PIO4_CFGR_FUNC_PERIPH_G, + ATMEL_PIO_CFGR_FUNC_PERIPH_G, use_pullup); } @@ -157,7 +128,7 @@ int atmel_pio4_set_pio_output(u32 port, u32 pin, u32 value) struct atmel_pio4_port *port_base; u32 reg, mask; - if (pin >= ATMEL_PIO4_PINS_PER_BANK) + if (pin >= ATMEL_PIO_NPINS_PER_BANK) return -ENODEV; port_base = atmel_pio4_port_base(port); @@ -165,7 +136,7 @@ int atmel_pio4_set_pio_output(u32 port, u32 pin, u32 value) return -ENODEV; mask = 0x01 << pin; - reg = ATMEL_PIO4_CFGR_FUNC_GPIO | ATMEL_PIO4_CFGR_DIR; + reg = ATMEL_PIO_CFGR_FUNC_GPIO | ATMEL_PIO_DIR_MASK; writel(mask, &port_base->mskr); writel(reg, &port_base->cfgr); @@ -183,7 +154,7 @@ int atmel_pio4_get_pio_input(u32 port, u32 pin) struct atmel_pio4_port *port_base; u32 reg, mask; - if (pin >= ATMEL_PIO4_PINS_PER_BANK) + if (pin >= ATMEL_PIO_NPINS_PER_BANK) return -ENODEV; port_base = atmel_pio4_port_base(port); @@ -191,7 +162,7 @@ int atmel_pio4_get_pio_input(u32 port, u32 pin) return -ENODEV; mask = 0x01 << pin; - reg = ATMEL_PIO4_CFGR_FUNC_GPIO; + reg = ATMEL_PIO_CFGR_FUNC_GPIO; writel(mask, &port_base->mskr); writel(reg, &port_base->cfgr); @@ -200,15 +171,37 @@ int atmel_pio4_get_pio_input(u32 port, u32 pin) } #ifdef CONFIG_DM_GPIO + +struct atmel_pioctrl_data { + u32 nbanks; +}; + +struct atmel_pio4_platdata { + struct atmel_pio4_port *reg_base; +}; + +static struct atmel_pio4_port *atmel_pio4_bank_base(struct udevice *dev, + u32 bank) +{ + struct atmel_pio4_platdata *plat = dev_get_platdata(dev); + struct atmel_pio4_port *port_base = + (struct atmel_pio4_port *)((u32)plat->reg_base + + ATMEL_PIO_BANK_OFFSET * bank); + + return port_base; +} + static int atmel_pio4_direction_input(struct udevice *dev, unsigned offset) { - struct at91_port_platdata *plat = dev_get_platdata(dev); - struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr; - u32 mask = 0x01 << offset; - u32 reg = ATMEL_PIO4_CFGR_FUNC_GPIO; + u32 bank = ATMEL_PIO_BANK(offset); + u32 line = ATMEL_PIO_LINE(offset); + struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank); + u32 mask = BIT(line); writel(mask, &port_base->mskr); - writel(reg, &port_base->cfgr); + + clrbits_le32(&port_base->cfgr, + ATMEL_PIO_CFGR_FUNC_MASK | ATMEL_PIO_DIR_MASK); return 0; } @@ -216,13 +209,15 @@ static int atmel_pio4_direction_input(struct udevice *dev, unsigned offset) static int atmel_pio4_direction_output(struct udevice *dev, unsigned offset, int value) { - struct at91_port_platdata *plat = dev_get_platdata(dev); - struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr; - u32 mask = 0x01 << offset; - u32 reg = ATMEL_PIO4_CFGR_FUNC_GPIO | ATMEL_PIO4_CFGR_DIR; + u32 bank = ATMEL_PIO_BANK(offset); + u32 line = ATMEL_PIO_LINE(offset); + struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank); + u32 mask = BIT(line); writel(mask, &port_base->mskr); - writel(reg, &port_base->cfgr); + + clrsetbits_le32(&port_base->cfgr, + ATMEL_PIO_CFGR_FUNC_MASK, ATMEL_PIO_DIR_MASK); if (value) writel(mask, &port_base->sodr); @@ -234,9 +229,10 @@ static int atmel_pio4_direction_output(struct udevice *dev, static int atmel_pio4_get_value(struct udevice *dev, unsigned offset) { - struct at91_port_platdata *plat = dev_get_platdata(dev); - struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr; - u32 mask = 0x01 << offset; + u32 bank = ATMEL_PIO_BANK(offset); + u32 line = ATMEL_PIO_LINE(offset); + struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank); + u32 mask = BIT(line); return (readl(&port_base->pdsr) & mask) ? 1 : 0; } @@ -244,9 +240,10 @@ static int atmel_pio4_get_value(struct udevice *dev, unsigned offset) static int atmel_pio4_set_value(struct udevice *dev, unsigned offset, int value) { - struct at91_port_platdata *plat = dev_get_platdata(dev); - struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr; - u32 mask = 0x01 << offset; + u32 bank = ATMEL_PIO_BANK(offset); + u32 line = ATMEL_PIO_LINE(offset); + struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank); + u32 mask = BIT(line); if (value) writel(mask, &port_base->sodr); @@ -258,14 +255,15 @@ static int atmel_pio4_set_value(struct udevice *dev, static int atmel_pio4_get_function(struct udevice *dev, unsigned offset) { - struct at91_port_platdata *plat = dev_get_platdata(dev); - struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr; - u32 mask = 0x01 << offset; + u32 bank = ATMEL_PIO_BANK(offset); + u32 line = ATMEL_PIO_LINE(offset); + struct atmel_pio4_port *port_base = atmel_pio4_bank_base(dev, bank); + u32 mask = BIT(line); writel(mask, &port_base->mskr); return (readl(&port_base->cfgr) & - ATMEL_PIO4_CFGR_DIR) ? GPIOF_OUTPUT : GPIOF_INPUT; + ATMEL_PIO_DIR_MASK) ? GPIOF_OUTPUT : GPIOF_INPUT; } static const struct dm_gpio_ops atmel_pio4_ops = { @@ -276,21 +274,82 @@ static const struct dm_gpio_ops atmel_pio4_ops = { .get_function = atmel_pio4_get_function, }; +static int atmel_pio4_bind(struct udevice *dev) +{ + return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false); +} + static int atmel_pio4_probe(struct udevice *dev) { - struct at91_port_platdata *plat = dev_get_platdata(dev); + struct atmel_pio4_platdata *plat = dev_get_platdata(dev); struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct atmel_pioctrl_data *pioctrl_data; + struct udevice *dev_clk; + struct clk clk; + fdt_addr_t addr_base; + u32 nbanks; + int periph; + int ret; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret) + return ret; + + periph = fdtdec_get_uint(gd->fdt_blob, clk.dev->of_offset, "reg", -1); + if (periph < 0) + return -EINVAL; + + dev_clk = dev_get_parent(clk.dev); + ret = clk_request(dev_clk, &clk); + if (ret) + return ret; + + clk.id = periph; + ret = clk_enable(&clk); + if (ret) + return ret; + + clk_free(&clk); + + addr_base = dev_get_addr(dev); + if (addr_base == FDT_ADDR_T_NONE) + return -EINVAL; + + plat->reg_base = (struct atmel_pio4_port *)addr_base; - uc_priv->bank_name = plat->bank_name; - uc_priv->gpio_count = ATMEL_PIO4_PINS_PER_BANK; + pioctrl_data = (struct atmel_pioctrl_data *)dev_get_driver_data(dev); + nbanks = pioctrl_data->nbanks; + + uc_priv->bank_name = fdt_get_name(gd->fdt_blob, dev->of_offset, NULL); + uc_priv->gpio_count = nbanks * ATMEL_PIO_NPINS_PER_BANK; return 0; } +/* + * The number of banks can be different from a SoC to another one. + * We can have up to 16 banks. + */ +static const struct atmel_pioctrl_data atmel_sama5d2_pioctrl_data = { + .nbanks = 4, +}; + +static const struct udevice_id atmel_pio4_ids[] = { + { + .compatible = "atmel,sama5d2-gpio", + .data = (ulong)&atmel_sama5d2_pioctrl_data, + }, + {} +}; + U_BOOT_DRIVER(gpio_atmel_pio4) = { .name = "gpio_atmel_pio4", .id = UCLASS_GPIO, .ops = &atmel_pio4_ops, .probe = atmel_pio4_probe, + .bind = atmel_pio4_bind, + .of_match = atmel_pio4_ids, + .platdata_auto_alloc_size = sizeof(struct atmel_pio4_platdata), }; + #endif diff --git a/drivers/gpio/gpio-uniphier.c b/drivers/gpio/gpio-uniphier.c index bde51eab15b..afb27a396ff 100644 --- a/drivers/gpio/gpio-uniphier.c +++ b/drivers/gpio/gpio-uniphier.c @@ -1,12 +1,12 @@ /* - * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> #include <dm/device.h> -#include <mapmem.h> #include <linux/bitops.h> #include <linux/io.h> #include <linux/sizes.h> @@ -99,7 +99,7 @@ static int uniphier_gpio_probe(struct udevice *dev) if (addr == FDT_ADDR_T_NONE) return -EINVAL; - priv->base = map_sysmem(addr, SZ_8); + priv->base = devm_ioremap(dev, addr, SZ_8); if (!priv->base) return -ENOMEM; @@ -119,15 +119,6 @@ static int uniphier_gpio_probe(struct udevice *dev) return 0; } -static int uniphier_gpio_remove(struct udevice *dev) -{ - struct uniphier_gpio_priv *priv = dev_get_priv(dev); - - unmap_sysmem(priv->base); - - return 0; -} - /* .data = the number of GPIO banks */ static const struct udevice_id uniphier_gpio_match[] = { { .compatible = "socionext,uniphier-gpio" }, @@ -139,7 +130,6 @@ U_BOOT_DRIVER(uniphier_gpio) = { .id = UCLASS_GPIO, .of_match = uniphier_gpio_match, .probe = uniphier_gpio_probe, - .remove = uniphier_gpio_remove, .priv_auto_alloc_size = sizeof(struct uniphier_gpio_priv), .ops = &uniphier_gpio_ops, }; diff --git a/drivers/gpio/mpc85xx_gpio.c b/drivers/gpio/mpc85xx_gpio.c index 04773e2b31c..168c696c4dc 100644 --- a/drivers/gpio/mpc85xx_gpio.c +++ b/drivers/gpio/mpc85xx_gpio.c @@ -163,23 +163,41 @@ static int mpc85xx_gpio_get_function(struct udevice *dev, unsigned gpio) return dir ? GPIOF_OUTPUT : GPIOF_INPUT; } +#if CONFIG_IS_ENABLED(OF_CONTROL) static int mpc85xx_gpio_ofdata_to_platdata(struct udevice *dev) { - struct mpc85xx_gpio_data *data = dev_get_priv(dev); + struct mpc85xx_gpio_plat *plat = dev_get_platdata(dev); fdt_addr_t addr; fdt_size_t size; addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, dev->of_offset, - "reg", 0, &size); + "reg", 0, &size, false); - data->addr = addr; - data->base = map_sysmem(CONFIG_SYS_IMMR + addr, size); + plat->addr = addr; + plat->size = size; + plat->ngpios = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "ngpios", 32); - if (!data->base) + return 0; +} +#endif + +static int mpc85xx_gpio_platdata_to_priv(struct udevice *dev) +{ + struct mpc85xx_gpio_data *priv = dev_get_priv(dev); + struct mpc85xx_gpio_plat *plat = dev_get_platdata(dev); + unsigned long size = plat->size; + + if (size == 0) + size = 0x100; + + priv->addr = plat->addr; + priv->base = map_sysmem(CONFIG_SYS_IMMR + plat->addr, size); + + if (!priv->base) return -ENOMEM; - data->gpio_count = fdtdec_get_int(gd->fdt_blob, dev->of_offset, - "ngpios", 32); - data->dat_shadow = 0; + priv->gpio_count = plat->ngpios; + priv->dat_shadow = 0; return 0; } @@ -190,6 +208,8 @@ static int mpc85xx_gpio_probe(struct udevice *dev) struct mpc85xx_gpio_data *data = dev_get_priv(dev); char name[32], *str; + mpc85xx_gpio_platdata_to_priv(dev); + snprintf(name, sizeof(name), "MPC@%lx_", data->addr); str = strdup(name); @@ -221,8 +241,11 @@ U_BOOT_DRIVER(gpio_mpc85xx) = { .name = "gpio_mpc85xx", .id = UCLASS_GPIO, .ops = &gpio_mpc85xx_ops, +#if CONFIG_IS_ENABLED(OF_CONTROL) .ofdata_to_platdata = mpc85xx_gpio_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct mpc85xx_gpio_plat), .of_match = mpc85xx_gpio_ids, +#endif .probe = mpc85xx_gpio_probe, .priv_auto_alloc_size = sizeof(struct mpc85xx_gpio_data), }; diff --git a/drivers/gpio/pcf8575_gpio.c b/drivers/gpio/pcf8575_gpio.c new file mode 100644 index 00000000000..2bda0ff9966 --- /dev/null +++ b/drivers/gpio/pcf8575_gpio.c @@ -0,0 +1,180 @@ +/* + * PCF8575 I2C GPIO EXPANDER DRIVER + * + * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * Vignesh R <vigneshr@ti.com> + * + * SPDX-License-Identifier: GPL-2.0 + * + * + * Driver for TI PCF-8575 16-bit I2C gpio expander. Based on + * gpio-pcf857x Linux Kernel(v4.7) driver. + * + * Copyright (C) 2007 David Brownell + * + */ + +/* + * NOTE: The driver and devicetree bindings are borrowed from Linux + * Kernel, but driver does not support all PCF857x devices. It currently + * supports PCF8575 16-bit expander by TI and NXP. + * + * TODO(vigneshr@ti.com): + * Support 8 bit PCF857x compatible expanders. + */ + +#include <common.h> +#include <dm.h> +#include <i2c.h> +#include <asm-generic/gpio.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct pcf8575_chip { + int gpio_count; /* No. GPIOs supported by the chip */ + + /* NOTE: these chips have strange "quasi-bidirectional" I/O pins. + * We can't actually know whether a pin is configured (a) as output + * and driving the signal low, or (b) as input and reporting a low + * value ... without knowing the last value written since the chip + * came out of reset (if any). We can't read the latched output. + * In short, the only reliable solution for setting up pin direction + * is to do it explicitly. + * + * Using "out" avoids that trouble. When left initialized to zero, + * our software copy of the "latch" then matches the chip's all-ones + * reset state. Otherwise it flags pins to be driven low. + */ + unsigned int out; /* software latch */ + const char *bank_name; /* Name of the expander bank */ +}; + +/* Read/Write to 16-bit I/O expander */ + +static int pcf8575_i2c_write_le16(struct udevice *dev, unsigned int word) +{ + struct dm_i2c_chip *chip = dev_get_parent_platdata(dev); + u8 buf[2] = { word & 0xff, word >> 8, }; + int ret; + + ret = dm_i2c_write(dev, 0, buf, 2); + if (ret) + printf("%s i2c write failed to addr %x\n", __func__, + chip->chip_addr); + + return ret; +} + +static int pcf8575_i2c_read_le16(struct udevice *dev) +{ + struct dm_i2c_chip *chip = dev_get_parent_platdata(dev); + u8 buf[2]; + int ret; + + ret = dm_i2c_read(dev, 0, buf, 2); + if (ret) { + printf("%s i2c read failed from addr %x\n", __func__, + chip->chip_addr); + return ret; + } + + return (buf[1] << 8) | buf[0]; +} + +static int pcf8575_direction_input(struct udevice *dev, unsigned offset) +{ + struct pcf8575_chip *plat = dev_get_platdata(dev); + int status; + + plat->out |= BIT(offset); + status = pcf8575_i2c_write_le16(dev, plat->out); + + return status; +} + +static int pcf8575_direction_output(struct udevice *dev, + unsigned int offset, int value) +{ + struct pcf8575_chip *plat = dev_get_platdata(dev); + int ret; + + if (value) + plat->out |= BIT(offset); + else + plat->out &= ~BIT(offset); + + ret = pcf8575_i2c_write_le16(dev, plat->out); + + return ret; +} + +static int pcf8575_get_value(struct udevice *dev, unsigned int offset) +{ + int value; + + value = pcf8575_i2c_read_le16(dev); + + return (value < 0) ? value : ((value & BIT(offset)) >> offset); +} + +static int pcf8575_set_value(struct udevice *dev, unsigned int offset, + int value) +{ + return pcf8575_direction_output(dev, offset, value); +} + +static int pcf8575_ofdata_platdata(struct udevice *dev) +{ + struct pcf8575_chip *plat = dev_get_platdata(dev); + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + + int n_latch; + + uc_priv->gpio_count = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "gpio-count", 16); + uc_priv->bank_name = fdt_getprop(gd->fdt_blob, dev->of_offset, + "gpio-bank-name", NULL); + if (!uc_priv->bank_name) + uc_priv->bank_name = fdt_get_name(gd->fdt_blob, + dev->of_offset, NULL); + + n_latch = fdtdec_get_uint(gd->fdt_blob, dev->of_offset, + "lines-initial-states", 0); + plat->out = ~n_latch; + + return 0; +} + +static int pcf8575_gpio_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + + debug("%s GPIO controller with %d gpios probed\n", + uc_priv->bank_name, uc_priv->gpio_count); + + return 0; +} + +static const struct dm_gpio_ops pcf8575_gpio_ops = { + .direction_input = pcf8575_direction_input, + .direction_output = pcf8575_direction_output, + .get_value = pcf8575_get_value, + .set_value = pcf8575_set_value, +}; + +static const struct udevice_id pcf8575_gpio_ids[] = { + { .compatible = "nxp,pcf8575" }, + { .compatible = "ti,pcf8575" }, + { } +}; + +U_BOOT_DRIVER(gpio_pcf8575) = { + .name = "gpio_pcf8575", + .id = UCLASS_GPIO, + .ops = &pcf8575_gpio_ops, + .of_match = pcf8575_gpio_ids, + .ofdata_to_platdata = pcf8575_ofdata_platdata, + .probe = pcf8575_gpio_probe, + .platdata_auto_alloc_size = sizeof(struct pcf8575_chip), +}; diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c index 94abbeb39ad..e8accaa3330 100644 --- a/drivers/gpio/sunxi_gpio.c +++ b/drivers/gpio/sunxi_gpio.c @@ -19,6 +19,7 @@ #include <asm/io.h> #include <asm/gpio.h> #include <dm/device-internal.h> +#include <dt-bindings/gpio/gpio.h> DECLARE_GLOBAL_DATA_PTR; @@ -215,12 +216,27 @@ static int sunxi_gpio_get_function(struct udevice *dev, unsigned offset) return GPIOF_FUNC; } +static int sunxi_gpio_xlate(struct udevice *dev, struct gpio_desc *desc, + struct fdtdec_phandle_args *args) +{ + int ret; + + ret = device_get_child(dev, args->args[0], &desc->dev); + if (ret) + return ret; + desc->offset = args->args[1]; + desc->flags = args->args[2] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0; + + return 0; +} + static const struct dm_gpio_ops gpio_sunxi_ops = { .direction_input = sunxi_gpio_direction_input, .direction_output = sunxi_gpio_direction_output, .get_value = sunxi_gpio_get_value, .set_value = sunxi_gpio_set_value, .get_function = sunxi_gpio_get_function, + .xlate = sunxi_gpio_xlate, }; /** diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 6e22bbadff2..1537b673fe1 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -58,6 +58,16 @@ config DM_I2C_GPIO bindings are supported. Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt +config SYS_I2C_AT91 + bool "Atmel I2C driver" + depends on DM_I2C && ARCH_AT91 + help + Add support for the Atmel I2C driver. A serious problem is that there + is no documented way to issue repeated START conditions for more than + two messages, as needed to support combined I2C messages. Use the + i2c-gpio driver unless your system can cope with this limitation. + Binding info: doc/device-tree-bindings/i2c/i2c-at91.txt + config SYS_I2C_FSL bool "Freescale I2C bus driver" depends on DM_I2C @@ -154,6 +164,23 @@ config SYS_I2C_UNIPHIER_F Support for UniPhier FIFO-builtin I2C controller driver. This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs. +config SYS_I2C_MVTWSI + bool "Marvell I2C driver" + depends on DM_I2C + help + Support for Marvell I2C controllers as used on the orion5x and + kirkwood SoC families. + +config TEGRA186_BPMP_I2C + bool "Enable Tegra186 BPMP-based I2C driver" + depends on TEGRA186_BPMP + help + Support for Tegra I2C controllers managed by the BPMP (Boot and + Power Management Processor). On Tegra186, some I2C controllers are + directly controlled by the main CPU, whereas others are controlled + by the BPMP, and can only be accessed by the main CPU via IPC + requests to the BPMP. This driver covers the latter case. + source "drivers/i2c/muxes/Kconfig" endmenu diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 167424db982..2987081991e 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o obj-$(CONFIG_SYS_I2C) += i2c_core.o +obj-$(CONFIG_SYS_I2C_AT91) += at91_i2c.o obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o @@ -41,5 +42,6 @@ obj-$(CONFIG_SYS_I2C_TEGRA) += tegra_i2c.o obj-$(CONFIG_SYS_I2C_UNIPHIER) += i2c-uniphier.o obj-$(CONFIG_SYS_I2C_UNIPHIER_F) += i2c-uniphier-f.o obj-$(CONFIG_SYS_I2C_ZYNQ) += zynq_i2c.o +obj-$(CONFIG_TEGRA186_BPMP_I2C) += tegra186_bpmp_i2c.o obj-$(CONFIG_I2C_MUX) += muxes/ diff --git a/drivers/i2c/at91_i2c.c b/drivers/i2c/at91_i2c.c new file mode 100644 index 00000000000..8e9c3ad5523 --- /dev/null +++ b/drivers/i2c/at91_i2c.c @@ -0,0 +1,338 @@ +/* + * Atmel I2C driver. + * + * (C) Copyright 2016 Songjun Wu <songjun.wu@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/io.h> +#include <common.h> +#include <clk_client.h> +#include <dm.h> +#include <errno.h> +#include <fdtdec.h> +#include <i2c.h> +#include <linux/bitops.h> +#include <mach/clk.h> + +#include "at91_i2c.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define I2C_TIMEOUT_MS 100 + +static int at91_wait_for_xfer(struct at91_i2c_bus *bus, u32 status) +{ + struct at91_i2c_regs *reg = bus->regs; + ulong start_time = get_timer(0); + u32 sr; + + bus->status = 0; + + do { + sr = readl(®->sr); + bus->status |= sr; + + if (sr & TWI_SR_NACK) + return -EREMOTEIO; + else if (sr & status) + return 0; + } while (get_timer(start_time) < I2C_TIMEOUT_MS); + + return -ETIMEDOUT; +} + +static int at91_i2c_xfer_msg(struct at91_i2c_bus *bus, struct i2c_msg *msg) +{ + struct at91_i2c_regs *reg = bus->regs; + bool is_read = msg->flags & I2C_M_RD; + u32 i; + int ret = 0; + + readl(®->sr); + if (is_read) { + writel(TWI_CR_START, ®->cr); + + for (i = 0; !ret && i < (msg->len - 1); i++) { + ret = at91_wait_for_xfer(bus, TWI_SR_RXRDY); + msg->buf[i] = readl(®->rhr); + } + + if (ret) + goto error; + + writel(TWI_CR_STOP, ®->cr); + + ret = at91_wait_for_xfer(bus, TWI_SR_RXRDY); + if (ret) + goto error; + + msg->buf[i] = readl(®->rhr); + + } else { + writel(msg->buf[0], ®->thr); + for (i = 1; !ret && (i < msg->len); i++) { + writel(msg->buf[i], ®->thr); + ret = at91_wait_for_xfer(bus, TWI_SR_TXRDY); + } + + if (ret) + goto error; + + writel(TWI_CR_STOP, ®->cr); + } + + if (!ret) + ret = at91_wait_for_xfer(bus, TWI_SR_TXCOMP); + + if (ret) + goto error; + + if (bus->status & (TWI_SR_OVRE | TWI_SR_UNRE | TWI_SR_LOCK)) { + ret = -EIO; + goto error; + } + + return 0; + +error: + if (bus->status & TWI_SR_LOCK) + writel(TWI_CR_LOCKCLR, ®->cr); + + return ret; +} + +static int at91_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs) +{ + struct at91_i2c_bus *bus = dev_get_priv(dev); + struct at91_i2c_regs *reg = bus->regs; + struct i2c_msg *m_start = msg; + bool is_read; + u32 int_addr_flag = 0; + int ret = 0; + + if (nmsgs == 2) { + int internal_address = 0; + int i; + + /* 1st msg is put into the internal address, start with 2nd */ + m_start = &msg[1]; + + /* the max length of internal address is 3 bytes */ + if (msg->len > 3) + return -EFAULT; + + for (i = 0; i < msg->len; ++i) { + const unsigned addr = msg->buf[msg->len - 1 - i]; + + internal_address |= addr << (8 * i); + int_addr_flag += TWI_MMR_IADRSZ_1; + } + + writel(internal_address, ®->iadr); + } + + is_read = m_start->flags & I2C_M_RD; + + writel((m_start->addr << 16) | int_addr_flag | + (is_read ? TWI_MMR_MREAD : 0), ®->mmr); + + ret = at91_i2c_xfer_msg(bus, m_start); + + return ret; +} + +/* + * Calculate symmetric clock as stated in datasheet: + * twi_clk = F_MAIN / (2 * (cdiv * (1 << ckdiv) + offset)) + */ +static void at91_calc_i2c_clock(struct udevice *dev, int i2c_clk) +{ + struct at91_i2c_bus *bus = dev_get_priv(dev); + const struct at91_i2c_pdata *pdata = bus->pdata; + int offset = pdata->clk_offset; + int max_ckdiv = pdata->clk_max_div; + int ckdiv, cdiv, div; + unsigned long src_rate; + + src_rate = bus->bus_clk_rate; + + div = max(0, (int)DIV_ROUND_UP(src_rate, 2 * i2c_clk) - offset); + ckdiv = fls(div >> 8); + cdiv = div >> ckdiv; + + if (ckdiv > max_ckdiv) { + ckdiv = max_ckdiv; + cdiv = 255; + } + + bus->speed = DIV_ROUND_UP(src_rate, + (cdiv * (1 << ckdiv) + offset) * 2); + + bus->cwgr_val = (ckdiv << 16) | (cdiv << 8) | cdiv; +} + +static int at91_i2c_enable_clk(struct udevice *dev) +{ + struct at91_i2c_bus *bus = dev_get_priv(dev); + struct udevice *dev_clk; + struct clk clk; + ulong clk_rate; + int periph; + int ret; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret) + return -EINVAL; + + periph = fdtdec_get_uint(gd->fdt_blob, clk.dev->of_offset, "reg", -1); + if (periph < 0) + return -EINVAL; + + dev_clk = dev_get_parent(clk.dev); + ret = clk_request(dev_clk, &clk); + if (ret) + return ret; + + clk.id = periph; + ret = clk_enable(&clk); + if (ret) + return ret; + + ret = clk_get_by_index(dev_clk, 0, &clk); + if (ret) + return ret; + + clk_rate = clk_get_rate(&clk); + if (!clk_rate) + return -ENODEV; + + bus->bus_clk_rate = clk_rate; + + clk_free(&clk); + + return 0; +} + +static int at91_i2c_probe(struct udevice *dev, uint chip, uint chip_flags) +{ + struct at91_i2c_bus *bus = dev_get_priv(dev); + struct at91_i2c_regs *reg = bus->regs; + int ret; + + ret = at91_i2c_enable_clk(dev); + if (ret) + return ret; + + writel(TWI_CR_SWRST, ®->cr); + + at91_calc_i2c_clock(dev, bus->clock_frequency); + + writel(bus->cwgr_val, ®->cwgr); + writel(TWI_CR_MSEN, ®->cr); + writel(TWI_CR_SVDIS, ®->cr); + + return 0; +} + +static int at91_i2c_set_bus_speed(struct udevice *dev, unsigned int speed) +{ + struct at91_i2c_bus *bus = dev_get_priv(dev); + + at91_calc_i2c_clock(dev, speed); + + writel(bus->cwgr_val, &bus->regs->cwgr); + + return 0; +} + +int at91_i2c_get_bus_speed(struct udevice *dev) +{ + struct at91_i2c_bus *bus = dev_get_priv(dev); + + return bus->speed; +} + +static int at91_i2c_ofdata_to_platdata(struct udevice *dev) +{ + const void *blob = gd->fdt_blob; + struct at91_i2c_bus *bus = dev_get_priv(dev); + int node = dev->of_offset; + + bus->regs = (struct at91_i2c_regs *)dev_get_addr(dev); + bus->pdata = (struct at91_i2c_pdata *)dev_get_driver_data(dev); + bus->clock_frequency = fdtdec_get_int(blob, node, + "clock-frequency", 100000); + + return 0; +} + +static const struct dm_i2c_ops at91_i2c_ops = { + .xfer = at91_i2c_xfer, + .probe_chip = at91_i2c_probe, + .set_bus_speed = at91_i2c_set_bus_speed, + .get_bus_speed = at91_i2c_get_bus_speed, +}; + +static const struct at91_i2c_pdata at91rm9200_config = { + .clk_max_div = 5, + .clk_offset = 3, +}; + +static const struct at91_i2c_pdata at91sam9261_config = { + .clk_max_div = 5, + .clk_offset = 4, +}; + +static const struct at91_i2c_pdata at91sam9260_config = { + .clk_max_div = 7, + .clk_offset = 4, +}; + +static const struct at91_i2c_pdata at91sam9g20_config = { + .clk_max_div = 7, + .clk_offset = 4, +}; + +static const struct at91_i2c_pdata at91sam9g10_config = { + .clk_max_div = 7, + .clk_offset = 4, +}; + +static const struct at91_i2c_pdata at91sam9x5_config = { + .clk_max_div = 7, + .clk_offset = 4, +}; + +static const struct at91_i2c_pdata sama5d4_config = { + .clk_max_div = 7, + .clk_offset = 4, +}; + +static const struct at91_i2c_pdata sama5d2_config = { + .clk_max_div = 7, + .clk_offset = 3, +}; + +static const struct udevice_id at91_i2c_ids[] = { +{ .compatible = "atmel,at91rm9200-i2c", .data = (long)&at91rm9200_config }, +{ .compatible = "atmel,at91sam9260-i2c", .data = (long)&at91sam9260_config }, +{ .compatible = "atmel,at91sam9261-i2c", .data = (long)&at91sam9261_config }, +{ .compatible = "atmel,at91sam9g20-i2c", .data = (long)&at91sam9g20_config }, +{ .compatible = "atmel,at91sam9g10-i2c", .data = (long)&at91sam9g10_config }, +{ .compatible = "atmel,at91sam9x5-i2c", .data = (long)&at91sam9x5_config }, +{ .compatible = "atmel,sama5d4-i2c", .data = (long)&sama5d4_config }, +{ .compatible = "atmel,sama5d2-i2c", .data = (long)&sama5d2_config }, +{ } +}; + +U_BOOT_DRIVER(i2c_at91) = { + .name = "i2c_at91", + .id = UCLASS_I2C, + .of_match = at91_i2c_ids, + .ofdata_to_platdata = at91_i2c_ofdata_to_platdata, + .per_child_auto_alloc_size = sizeof(struct dm_i2c_chip), + .priv_auto_alloc_size = sizeof(struct at91_i2c_bus), + .ops = &at91_i2c_ops, +}; diff --git a/drivers/i2c/at91_i2c.h b/drivers/i2c/at91_i2c.h new file mode 100644 index 00000000000..87f02bfaf3f --- /dev/null +++ b/drivers/i2c/at91_i2c.h @@ -0,0 +1,77 @@ +#ifndef _AT91_I2C_H +#define _AT91_I2C_H + +#define TWI_CR_START BIT(0) /* Send a Start Condition */ +#define TWI_CR_MSEN BIT(2) /* Master Transfer Enable */ +#define TWI_CR_STOP BIT(1) /* Send a Stop Condition */ +#define TWI_CR_SVDIS BIT(5) /* Slave Transfer Disable */ +#define TWI_CR_SWRST BIT(7) /* Software Reset */ +#define TWI_CR_ACMEN BIT(16) /* Alternative Command Mode Enable */ +#define TWI_CR_ACMDIS BIT(17) /* Alternative Command Mode Disable */ +#define TWI_CR_LOCKCLR BIT(26) /* Lock Clear */ + +#define TWI_MMR_MREAD BIT(12) /* Master Read Direction */ +#define TWI_MMR_IADRSZ_1 BIT(8) /* Internal Device Address Size */ + +#define TWI_SR_TXCOMP BIT(0) /* Transmission Complete */ +#define TWI_SR_RXRDY BIT(1) /* Receive Holding Register Ready */ +#define TWI_SR_TXRDY BIT(2) /* Transmit Holding Register Ready */ +#define TWI_SR_OVRE BIT(6) /* Overrun Error */ +#define TWI_SR_UNRE BIT(7) /* Underrun Error */ +#define TWI_SR_NACK BIT(8) /* Not Acknowledged */ +#define TWI_SR_LOCK BIT(23) /* TWI Lock due to Frame Errors */ + +#define TWI_ACR_DATAL(len) ((len) & 0xff) +#define TWI_ACR_DIR_READ BIT(8) + +#define TWI_CWGR_HOLD_MAX 0x1f +#define TWI_CWGR_HOLD(x) (((x) & TWI_CWGR_HOLD_MAX) << 24) + +struct at91_i2c_regs { + u32 cr; + u32 mmr; + u32 smr; + u32 iadr; + u32 cwgr; + u32 rev_0[3]; + u32 sr; + u32 ier; + u32 idr; + u32 imr; + u32 rhr; + u32 thr; + u32 smbtr; + u32 rev_1; + u32 acr; + u32 filtr; + u32 rev_2; + u32 swmr; + u32 fmr; + u32 flr; + u32 rev_3; + u32 fsr; + u32 fier; + u32 fidr; + u32 fimr; + u32 rev_4[29]; + u32 wpmr; + u32 wpsr; + u32 rev_5[6]; +}; + +struct at91_i2c_pdata { + unsigned clk_max_div; + unsigned clk_offset; +}; + +struct at91_i2c_bus { + struct at91_i2c_regs *regs; + u32 status; + ulong bus_clk_rate; + u32 clock_frequency; + u32 speed; + u32 cwgr_val; + const struct at91_i2c_pdata *pdata; +}; + +#endif diff --git a/drivers/i2c/cros_ec_ldo.c b/drivers/i2c/cros_ec_ldo.c index b817c61f1c5..a4cd6604065 100644 --- a/drivers/i2c/cros_ec_ldo.c +++ b/drivers/i2c/cros_ec_ldo.c @@ -72,6 +72,5 @@ U_BOOT_DRIVER(cros_ec_ldo) = { .name = "cros_ec_ldo_tunnel", .id = UCLASS_I2C, .of_match = cros_ec_i2c_ids, - .per_child_auto_alloc_size = sizeof(struct dm_i2c_chip), .ops = &cros_ec_i2c_ops, }; diff --git a/drivers/i2c/cros_ec_tunnel.c b/drivers/i2c/cros_ec_tunnel.c index 7ab1fd898ad..e2c6e447951 100644 --- a/drivers/i2c/cros_ec_tunnel.c +++ b/drivers/i2c/cros_ec_tunnel.c @@ -36,6 +36,5 @@ U_BOOT_DRIVER(cros_ec_tunnel) = { .name = "cros_ec_tunnel", .id = UCLASS_I2C, .of_match = cros_ec_i2c_ids, - .per_child_auto_alloc_size = sizeof(struct dm_i2c_chip), .ops = &cros_ec_i2c_ops, }; diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index b8cc647bd39..c3f826d68c7 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -583,12 +583,11 @@ static int fsl_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) static int fsl_i2c_ofdata_to_platdata(struct udevice *bus) { struct fsl_i2c_dev *dev = dev_get_priv(bus); - u64 reg; - u32 addr, size; + fdt_addr_t addr; + fdt_size_t size; - reg = fdtdec_get_addr(gd->fdt_blob, bus->of_offset, "reg"); - addr = reg >> 32; - size = reg & 0xFFFFFFFF; + addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, bus->of_offset, + "reg", 0, &size, false); dev->base = map_sysmem(CONFIG_SYS_IMMR + addr, size); diff --git a/drivers/i2c/i2c-uclass-compat.c b/drivers/i2c/i2c-uclass-compat.c index 5606d1f807f..de78db6a887 100644 --- a/drivers/i2c/i2c-uclass-compat.c +++ b/drivers/i2c/i2c-uclass-compat.c @@ -9,7 +9,7 @@ #include <errno.h> #include <i2c.h> -static int cur_busnum; +static int cur_busnum __attribute__((section(".data"))); static int i2c_compat_get_device(uint chip_addr, int alen, struct udevice **devp) diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c index 50b99ead3d9..dbd3789747d 100644 --- a/drivers/i2c/i2c-uclass.c +++ b/drivers/i2c/i2c-uclass.c @@ -12,7 +12,6 @@ #include <malloc.h> #include <dm/device-internal.h> #include <dm/lists.h> -#include <dm/root.h> DECLARE_GLOBAL_DATA_PTR; @@ -467,6 +466,7 @@ int i2c_deblock(struct udevice *bus) return ops->deblock(bus); } +#if CONFIG_IS_ENABLED(OF_CONTROL) int i2c_chip_ofdata_to_platdata(const void *blob, int node, struct dm_i2c_chip *chip) { @@ -482,38 +482,43 @@ int i2c_chip_ofdata_to_platdata(const void *blob, int node, return 0; } +#endif static int i2c_post_probe(struct udevice *dev) { +#if CONFIG_IS_ENABLED(OF_CONTROL) struct dm_i2c_bus *i2c = dev_get_uclass_priv(dev); i2c->speed_hz = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "clock-frequency", 100000); return dm_i2c_set_bus_speed(dev, i2c->speed_hz); -} - -static int i2c_post_bind(struct udevice *dev) -{ - /* Scan the bus for devices */ - return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false); +#else + return 0; +#endif } static int i2c_child_post_bind(struct udevice *dev) { +#if CONFIG_IS_ENABLED(OF_CONTROL) struct dm_i2c_chip *plat = dev_get_parent_platdata(dev); if (dev->of_offset == -1) return 0; return i2c_chip_ofdata_to_platdata(gd->fdt_blob, dev->of_offset, plat); +#else + return 0; +#endif } UCLASS_DRIVER(i2c) = { .id = UCLASS_I2C, .name = "i2c", .flags = DM_UC_FLAG_SEQ_ALIAS, - .post_bind = i2c_post_bind, +#if CONFIG_IS_ENABLED(OF_CONTROL) + .post_bind = dm_scan_fdt_dev, +#endif .post_probe = i2c_post_probe, .per_device_auto_alloc_size = sizeof(struct dm_i2c_bus), .per_child_platdata_auto_alloc_size = sizeof(struct dm_i2c_chip), diff --git a/drivers/i2c/i2c-uniphier-f.c b/drivers/i2c/i2c-uniphier-f.c index aebdcfcec30..a56e058d569 100644 --- a/drivers/i2c/i2c-uniphier-f.c +++ b/drivers/i2c/i2c-uniphier-f.c @@ -1,5 +1,7 @@ /* - * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2014 Panasonic Corporation + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -13,7 +15,6 @@ #include <dm/root.h> #include <i2c.h> #include <fdtdec.h> -#include <mapmem.h> struct uniphier_fi2c_regs { u32 cr; /* control register */ @@ -118,7 +119,7 @@ static int uniphier_fi2c_probe(struct udevice *dev) if (addr == FDT_ADDR_T_NONE) return -EINVAL; - priv->regs = map_sysmem(addr, SZ_128); + priv->regs = devm_ioremap(dev, addr, SZ_128); if (!priv->regs) return -ENOMEM; @@ -134,15 +135,6 @@ static int uniphier_fi2c_probe(struct udevice *dev) return 0; } -static int uniphier_fi2c_remove(struct udevice *dev) -{ - struct uniphier_fi2c_dev *priv = dev_get_priv(dev); - - unmap_sysmem(priv->regs); - - return 0; -} - static int wait_for_irq(struct uniphier_fi2c_dev *dev, u32 flags, bool *stop) { @@ -359,7 +351,6 @@ U_BOOT_DRIVER(uniphier_fi2c) = { .id = UCLASS_I2C, .of_match = uniphier_fi2c_of_match, .probe = uniphier_fi2c_probe, - .remove = uniphier_fi2c_remove, .priv_auto_alloc_size = sizeof(struct uniphier_fi2c_dev), .ops = &uniphier_fi2c_ops, }; diff --git a/drivers/i2c/i2c-uniphier.c b/drivers/i2c/i2c-uniphier.c index f8221da82e4..39a3ebdfc16 100644 --- a/drivers/i2c/i2c-uniphier.c +++ b/drivers/i2c/i2c-uniphier.c @@ -1,5 +1,7 @@ /* - * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2014 Panasonic Corporation + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -13,7 +15,6 @@ #include <dm/root.h> #include <i2c.h> #include <fdtdec.h> -#include <mapmem.h> struct uniphier_i2c_regs { u32 dtrm; /* data transmission */ @@ -53,7 +54,7 @@ static int uniphier_i2c_probe(struct udevice *dev) if (addr == FDT_ADDR_T_NONE) return -EINVAL; - priv->regs = map_sysmem(addr, SZ_64); + priv->regs = devm_ioremap(dev, addr, SZ_64); if (!priv->regs) return -ENOMEM; @@ -65,15 +66,6 @@ static int uniphier_i2c_probe(struct udevice *dev) return 0; } -static int uniphier_i2c_remove(struct udevice *dev) -{ - struct uniphier_i2c_dev *priv = dev_get_priv(dev); - - unmap_sysmem(priv->regs); - - return 0; -} - static int send_and_recv_byte(struct uniphier_i2c_dev *dev, u32 dtrm) { writel(dtrm, &dev->regs->dtrm); @@ -220,7 +212,6 @@ U_BOOT_DRIVER(uniphier_i2c) = { .id = UCLASS_I2C, .of_match = uniphier_i2c_of_match, .probe = uniphier_i2c_probe, - .remove = uniphier_i2c_remove, .priv_auto_alloc_size = sizeof(struct uniphier_i2c_dev), .ops = &uniphier_i2c_ops, }; diff --git a/drivers/i2c/intel_i2c.c b/drivers/i2c/intel_i2c.c index 3d777ff23e0..a0182dc1cc1 100644 --- a/drivers/i2c/intel_i2c.c +++ b/drivers/i2c/intel_i2c.c @@ -2,54 +2,290 @@ * Copyright (c) 2015 Google, Inc * Written by Simon Glass <sjg@chromium.org> * + * SMBus block read/write support added by Stefan Roese: + * Copyright (C) 2016 Stefan Roese <sr@denx.de> + * * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> #include <dm.h> #include <i2c.h> +#include <pci.h> #include <asm/io.h> -#include <asm/arch/pch.h> -int intel_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) +/* PCI Configuration Space (D31:F3): SMBus */ +#define SMB_BASE 0x20 +#define HOSTC 0x40 +#define HST_EN (1 << 0) +#define SMB_RCV_SLVA 0x09 + +/* SMBus I/O bits. */ +#define SMBHSTSTAT 0x0 +#define SMBHSTCTL 0x2 +#define SMBHSTCMD 0x3 +#define SMBXMITADD 0x4 +#define SMBHSTDAT0 0x5 +#define SMBHSTDAT1 0x6 +#define SMBBLKDAT 0x7 +#define SMBTRNSADD 0x9 +#define SMBSLVDATA 0xa +#define SMBAUXCTL 0xd +#define SMLINK_PIN_CTL 0xe +#define SMBUS_PIN_CTL 0xf + +/* I801 Hosts Status register bits */ +#define SMBHSTSTS_BYTE_DONE 0x80 +#define SMBHSTSTS_INUSE_STS 0x40 +#define SMBHSTSTS_SMBALERT_STS 0x20 +#define SMBHSTSTS_FAILED 0x10 +#define SMBHSTSTS_BUS_ERR 0x08 +#define SMBHSTSTS_DEV_ERR 0x04 +#define SMBHSTSTS_INTR 0x02 +#define SMBHSTSTS_HOST_BUSY 0x01 + +/* I801 Host Control register bits */ +#define SMBHSTCNT_INTREN 0x01 +#define SMBHSTCNT_KILL 0x02 +#define SMBHSTCNT_LAST_BYTE 0x20 +#define SMBHSTCNT_START 0x40 +#define SMBHSTCNT_PEC_EN 0x80 /* ICH3 and later */ + +/* Auxiliary control register bits, ICH4+ only */ +#define SMBAUXCTL_CRC 1 +#define SMBAUXCTL_E32B 2 + +#define SMBUS_TIMEOUT 100 /* 100 ms */ + +struct intel_i2c { + u32 base; + int running; +}; + +static int smbus_wait_until_ready(u32 base) { - return -ENOSYS; + unsigned long ts; + u8 byte; + + ts = get_timer(0); + do { + byte = inb(base + SMBHSTSTAT); + if (!(byte & 1)) + return 0; + } while (get_timer(ts) < SMBUS_TIMEOUT); + + return -ETIMEDOUT; } -int intel_i2c_probe_chip(struct udevice *bus, uint chip_addr, uint chip_flags) +static int smbus_wait_until_done(u32 base) { - return -ENOSYS; + unsigned long ts; + u8 byte; + + ts = get_timer(0); + do { + byte = inb(base + SMBHSTSTAT); + if (!((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0)) + return 0; + } while (get_timer(ts) < SMBUS_TIMEOUT); + + return -ETIMEDOUT; } -int intel_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) +static int smbus_block_read(u32 base, u8 dev, u8 *buffer, + int offset, int len) { + u8 buf_temp[32]; + int count; + int i; + + debug("%s (%d): dev=0x%x offs=0x%x len=0x%x\n", + __func__, __LINE__, dev, offset, len); + if (smbus_wait_until_ready(base) < 0) + return -ETIMEDOUT; + + /* Setup transaction */ + + /* Reset the data buffer index */ + inb(base + SMBHSTCTL); + + /* Set the device I'm talking too */ + outb(((dev & 0x7f) << 1) | 1, base + SMBXMITADD); + /* Set the command/address... */ + outb(offset & 0xff, base + SMBHSTCMD); + /* Set up for a block read */ + outb((inb(base + SMBHSTCTL) & (~(0x7) << 2)) | (0x5 << 2), + (base + SMBHSTCTL)); + /* Clear any lingering errors, so the transaction will run */ + outb(inb(base + SMBHSTSTAT), base + SMBHSTSTAT); + + /* Start the command */ + outb((inb(base + SMBHSTCTL) | SMBHSTCNT_START), base + SMBHSTCTL); + + /* Poll for transaction completion */ + if (smbus_wait_until_done(base) < 0) { + printf("SMBUS read transaction timeout (dev=0x%x)\n", dev); + return -ETIMEDOUT; + } + + count = inb(base + SMBHSTDAT0); + debug("%s (%d): count=%d (len=%d)\n", __func__, __LINE__, count, len); + if (count == 0) { + debug("ERROR: len=0 on read\n"); + return -EIO; + } + + if (count < len) { + debug("ERROR: too few bytes read\n"); + return -EIO; + } + + if (count > 32) { + debug("ERROR: count=%d too high\n", count); + return -EIO; + } + + /* Read all available bytes from buffer */ + for (i = 0; i < count; i++) + buf_temp[i] = inb(base + SMBBLKDAT); + + memcpy(buffer, buf_temp, len); + + /* Return results of transaction */ + if (!(inb(base + SMBHSTSTAT) & SMBHSTSTS_INTR)) + return -EIO; + return 0; } -static int intel_i2c_probe(struct udevice *dev) +static int smbus_block_write(u32 base, u8 dev, u8 *buffer, + int offset, int len) { + int i; + + debug("%s (%d): dev=0x%x offs=0x%x len=0x%x\n", + __func__, __LINE__, dev, offset, len); + if (smbus_wait_until_ready(base) < 0) + return -ETIMEDOUT; + + /* Setup transaction */ + /* Set the device I'm talking too */ + outb(((dev & 0x7f) << 1) & ~0x01, base + SMBXMITADD); + /* Set the command/address... */ + outb(offset, base + SMBHSTCMD); + /* Set up for a block write */ + outb((inb(base + SMBHSTCTL) & (~(0x7) << 2)) | (0x5 << 2), + (base + SMBHSTCTL)); + /* Clear any lingering errors, so the transaction will run */ + outb(inb(base + SMBHSTSTAT), base + SMBHSTSTAT); + + /* Write count in DAT0 register */ + outb(len, base + SMBHSTDAT0); + + /* Write data bytes... */ + for (i = 0; i < len; i++) + outb(*buffer++, base + SMBBLKDAT); + + /* Start the command */ + outb((inb(base + SMBHSTCTL) | SMBHSTCNT_START), base + SMBHSTCTL); + + /* Poll for transaction completion */ + if (smbus_wait_until_done(base) < 0) { + printf("SMBUS write transaction timeout (dev=0x%x)\n", dev); + return -ETIMEDOUT; + } + + /* Return results of transaction */ + if (!(inb(base + SMBHSTSTAT) & SMBHSTSTS_INTR)) + return -EIO; + + return 0; +} + +static int intel_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) +{ + struct intel_i2c *i2c = dev_get_priv(bus); + struct i2c_msg *dmsg, *omsg, dummy; + + debug("i2c_xfer: %d messages\n", nmsgs); + + memset(&dummy, 0, sizeof(struct i2c_msg)); + /* - * So far this is just setup code for ivybridge SMbus. When we have - * a full I2C driver this may need to be moved, generalised or made - * dependant on a particular compatible string. - * - * Set SMBus I/O base + * We expect either two messages (one with an offset and one with the + * actucal data) or one message (just data) */ - dm_pci_write_config32(dev, SMB_BASE, - SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO); + if (nmsgs > 2 || nmsgs == 0) { + debug("%s: Only one or two messages are supported", __func__); + return -EIO; + } + + omsg = nmsgs == 1 ? &dummy : msg; + dmsg = nmsgs == 1 ? msg : msg + 1; + + if (dmsg->flags & I2C_M_RD) + return smbus_block_read(i2c->base, dmsg->addr, &dmsg->buf[0], + omsg->buf[0], dmsg->len); + else + return smbus_block_write(i2c->base, dmsg->addr, &dmsg->buf[1], + dmsg->buf[0], dmsg->len - 1); +} + +static int intel_i2c_probe_chip(struct udevice *bus, uint chip_addr, + uint chip_flags) +{ + struct intel_i2c *i2c = dev_get_priv(bus); + u8 buf[4]; + + return smbus_block_read(i2c->base, chip_addr, buf, 0, 1); +} + +static int intel_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) +{ + return 0; +} + +static int intel_i2c_probe(struct udevice *dev) +{ + struct intel_i2c *priv = dev_get_priv(dev); + u32 base; + + /* Save base address from PCI BAR */ + priv->base = (u32)dm_pci_map_bar(dev, PCI_BASE_ADDRESS_4, + PCI_REGION_IO); + base = priv->base; /* Set SMBus enable. */ dm_pci_write_config8(dev, HOSTC, HST_EN); - /* Set SMBus I/O space enable. */ - dm_pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO); + /* Disable interrupts */ + outb(inb(base + SMBHSTCTL) & ~SMBHSTCNT_INTREN, base + SMBHSTCTL); - /* Disable interrupt generation. */ - outb(0, SMBUS_IO_BASE + SMBHSTCTL); + /* Set 32-byte data buffer mode */ + outb(inb(base + SMBAUXCTL) | SMBAUXCTL_E32B, base + SMBAUXCTL); - /* Clear any lingering errors, so transactions can run. */ - outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); - debug("SMBus controller enabled\n"); + return 0; +} + +static int intel_i2c_bind(struct udevice *dev) +{ + static int num_cards __attribute__ ((section(".data"))); + char name[20]; + + /* Create a unique device name for PCI type devices */ + if (device_is_on_pci_bus(dev)) { + /* + * ToDo: + * Setting req_seq in the driver is probably not recommended. + * But without a DT alias the number is not configured. And + * using this driver is impossible for PCIe I2C devices. + * This can be removed, once a better (correct) way for this + * is found and implemented. + */ + dev->req_seq = num_cards; + sprintf(name, "intel_i2c#%u", num_cards++); + device_set_name(dev, name); + } return 0; } @@ -69,7 +305,18 @@ U_BOOT_DRIVER(intel_i2c) = { .name = "i2c_intel", .id = UCLASS_I2C, .of_match = intel_i2c_ids, - .per_child_auto_alloc_size = sizeof(struct dm_i2c_chip), .ops = &intel_i2c_ops, + .priv_auto_alloc_size = sizeof(struct intel_i2c), + .bind = intel_i2c_bind, .probe = intel_i2c_probe, }; + +static struct pci_device_id intel_smbus_pci_supported[] = { + /* Intel BayTrail SMBus on the PCI bus */ + { PCI_VDEVICE(INTEL, 0x0f12) }, + /* Intel IvyBridge (Panther Point PCH) SMBus on the PCI bus */ + { PCI_VDEVICE(INTEL, 0x1e22) }, + {}, +}; + +U_BOOT_PCI_DEVICE(intel_i2c, intel_smbus_pci_supported); diff --git a/drivers/i2c/muxes/i2c-mux-uclass.c b/drivers/i2c/muxes/i2c-mux-uclass.c index 3f52bff2fb0..7a698b62b5a 100644 --- a/drivers/i2c/muxes/i2c-mux-uclass.c +++ b/drivers/i2c/muxes/i2c-mux-uclass.c @@ -183,7 +183,6 @@ static const struct dm_i2c_ops i2c_mux_bus_ops = { U_BOOT_DRIVER(i2c_mux_bus) = { .name = "i2c_mux_bus_drv", .id = UCLASS_I2C, - .per_child_auto_alloc_size = sizeof(struct dm_i2c_chip), .ops = &i2c_mux_bus_ops, }; diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c index bf4443287fd..ab7481a0d4a 100644 --- a/drivers/i2c/mvtwsi.c +++ b/drivers/i2c/mvtwsi.c @@ -12,12 +12,19 @@ #include <i2c.h> #include <asm/errno.h> #include <asm/io.h> +#include <linux/compat.h> +#ifdef CONFIG_DM_I2C +#include <dm.h> +#endif + +DECLARE_GLOBAL_DATA_PTR; /* - * include a file that will provide CONFIG_I2C_MVTWSI_BASE* - * and possibly other settings + * Include a file that will provide CONFIG_I2C_MVTWSI_BASE*, and possibly other + * settings */ +#ifndef CONFIG_DM_I2C #if defined(CONFIG_ORION5X) #include <asm/arch/orion5x.h> #elif (defined(CONFIG_KIRKWOOD) || defined(CONFIG_ARCH_MVEBU)) @@ -27,6 +34,7 @@ #else #error Driver mvtwsi not supported by SoC or board #endif +#endif /* CONFIG_DM_I2C */ /* * TWSI register structure @@ -51,8 +59,8 @@ struct mvtwsi_registers { u32 data; u32 control; union { - u32 status; /* when reading */ - u32 baudrate; /* when writing */ + u32 status; /* When reading */ + u32 baudrate; /* When writing */ }; u32 xtnd_slave_addr; u32 reserved[2]; @@ -61,20 +69,43 @@ struct mvtwsi_registers { #endif +#ifdef CONFIG_DM_I2C +struct mvtwsi_i2c_dev { + /* TWSI Register base for the device */ + struct mvtwsi_registers *base; + /* Number of the device (determined from cell-index property) */ + int index; + /* The I2C slave address for the device */ + u8 slaveadd; + /* The configured I2C speed in Hz */ + uint speed; + /* The current length of a clock period (depending on speed) */ + uint tick; +}; +#endif /* CONFIG_DM_I2C */ + /* - * Control register fields + * enum mvtwsi_ctrl_register_fields - Bit masks for flags in the control + * register */ - -#define MVTWSI_CONTROL_ACK 0x00000004 -#define MVTWSI_CONTROL_IFLG 0x00000008 -#define MVTWSI_CONTROL_STOP 0x00000010 -#define MVTWSI_CONTROL_START 0x00000020 -#define MVTWSI_CONTROL_TWSIEN 0x00000040 -#define MVTWSI_CONTROL_INTEN 0x00000080 +enum mvtwsi_ctrl_register_fields { + /* Acknowledge bit */ + MVTWSI_CONTROL_ACK = 0x00000004, + /* Interrupt flag */ + MVTWSI_CONTROL_IFLG = 0x00000008, + /* Stop bit */ + MVTWSI_CONTROL_STOP = 0x00000010, + /* Start bit */ + MVTWSI_CONTROL_START = 0x00000020, + /* I2C enable */ + MVTWSI_CONTROL_TWSIEN = 0x00000040, + /* Interrupt enable */ + MVTWSI_CONTROL_INTEN = 0x00000080, +}; /* - * On sun6i and newer IFLG is a write-clear bit which is cleared by writing 1, - * on other platforms it is a normal r/w bit which is cleared by writing 0. + * On sun6i and newer, IFLG is a write-clear bit, which is cleared by writing 1; + * on other platforms, it is a normal r/w bit, which is cleared by writing 0. */ #ifdef CONFIG_SUNXI_GEN_SUN6I @@ -84,53 +115,95 @@ struct mvtwsi_registers { #endif /* - * Status register values -- only those expected in normal master - * operation on non-10-bit-address devices; whatever status we don't - * expect in nominal conditions (bus errors, arbitration losses, - * missing ACKs...) we just pass back to the caller as an error + * enum mvstwsi_status_values - Possible values of I2C controller's status + * register + * + * Only those statuses expected in normal master operation on + * non-10-bit-address devices are specified. + * + * Every status that's unexpected during normal operation (bus errors, + * arbitration losses, missing ACKs...) is passed back to the caller as an error * code. */ +enum mvstwsi_status_values { + /* START condition transmitted */ + MVTWSI_STATUS_START = 0x08, + /* Repeated START condition transmitted */ + MVTWSI_STATUS_REPEATED_START = 0x10, + /* Address + write bit transmitted, ACK received */ + MVTWSI_STATUS_ADDR_W_ACK = 0x18, + /* Data transmitted, ACK received */ + MVTWSI_STATUS_DATA_W_ACK = 0x28, + /* Address + read bit transmitted, ACK received */ + MVTWSI_STATUS_ADDR_R_ACK = 0x40, + /* Address + read bit transmitted, ACK not received */ + MVTWSI_STATUS_ADDR_R_NAK = 0x48, + /* Data received, ACK transmitted */ + MVTWSI_STATUS_DATA_R_ACK = 0x50, + /* Data received, ACK not transmitted */ + MVTWSI_STATUS_DATA_R_NAK = 0x58, + /* No relevant status */ + MVTWSI_STATUS_IDLE = 0xF8, +}; -#define MVTWSI_STATUS_START 0x08 -#define MVTWSI_STATUS_REPEATED_START 0x10 -#define MVTWSI_STATUS_ADDR_W_ACK 0x18 -#define MVTWSI_STATUS_DATA_W_ACK 0x28 -#define MVTWSI_STATUS_ADDR_R_ACK 0x40 -#define MVTWSI_STATUS_ADDR_R_NAK 0x48 -#define MVTWSI_STATUS_DATA_R_ACK 0x50 -#define MVTWSI_STATUS_DATA_R_NAK 0x58 -#define MVTWSI_STATUS_IDLE 0xF8 +/* + * enum mvstwsi_ack_flags - Determine whether a read byte should be + * acknowledged or not. + */ +enum mvtwsi_ack_flags { + /* Send NAK after received byte */ + MVTWSI_READ_NAK = 0, + /* Send ACK after received byte */ + MVTWSI_READ_ACK = 1, +}; /* - * MVTWSI controller base + * calc_tick() - Calculate the duration of a clock cycle from the I2C speed + * + * @speed: The speed in Hz to calculate the clock cycle duration for. + * @return The duration of a clock cycle in ns. */ +inline uint calc_tick(uint speed) +{ + /* One tick = the duration of a period at the specified speed in ns (we + * add 100 ns to be on the safe side) */ + return (1000000000u / speed) + 100; +} +#ifndef CONFIG_DM_I2C + +/* + * twsi_get_base() - Get controller register base for specified adapter + * + * @adap: Adapter to get the register base for. + * @return Register base for the specified adapter. + */ static struct mvtwsi_registers *twsi_get_base(struct i2c_adapter *adap) { switch (adap->hwadapnr) { #ifdef CONFIG_I2C_MVTWSI_BASE0 case 0: - return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE0; + return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE0; #endif #ifdef CONFIG_I2C_MVTWSI_BASE1 case 1: - return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE1; + return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE1; #endif #ifdef CONFIG_I2C_MVTWSI_BASE2 case 2: - return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE2; + return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE2; #endif #ifdef CONFIG_I2C_MVTWSI_BASE3 case 3: - return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE3; + return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE3; #endif #ifdef CONFIG_I2C_MVTWSI_BASE4 case 4: - return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE4; + return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE4; #endif #ifdef CONFIG_I2C_MVTWSI_BASE5 case 5: - return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE5; + return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE5; #endif default: printf("Missing mvtwsi controller %d base\n", adap->hwadapnr); @@ -139,30 +212,48 @@ static struct mvtwsi_registers *twsi_get_base(struct i2c_adapter *adap) return NULL; } +#endif /* - * Returned statuses are 0 for success and nonzero otherwise. - * Currently, cmd_i2c and cmd_eeprom do not interpret an error status. - * Thus to ease debugging, the return status contains some debug info: - * - bits 31..24 are error class: 1 is timeout, 2 is 'status mismatch'. - * - bits 23..16 are the last value of the control register. - * - bits 15..8 are the last value of the status register. - * - bits 7..0 are the expected value of the status register. + * enum mvtwsi_error_class - types of I2C errors */ +enum mvtwsi_error_class { + /* The controller returned a different status than expected */ + MVTWSI_ERROR_WRONG_STATUS = 0x01, + /* The controller timed out */ + MVTWSI_ERROR_TIMEOUT = 0x02, +}; -#define MVTWSI_ERROR_WRONG_STATUS 0x01 -#define MVTWSI_ERROR_TIMEOUT 0x02 - -#define MVTWSI_ERROR(ec, lc, ls, es) (((ec << 24) & 0xFF000000) | \ - ((lc << 16) & 0x00FF0000) | ((ls<<8) & 0x0000FF00) | (es & 0xFF)) +/* + * mvtwsi_error() - Build I2C return code from error information + * + * For debugging purposes, this function packs some information of an occurred + * error into a return code. These error codes are returned from I2C API + * functions (i2c_{read,write}, dm_i2c_{read,write}, etc.). + * + * @ec: The error class of the error (enum mvtwsi_error_class). + * @lc: The last value of the control register. + * @ls: The last value of the status register. + * @es: The expected value of the status register. + * @return The generated error code. + */ +inline uint mvtwsi_error(uint ec, uint lc, uint ls, uint es) +{ + return ((ec << 24) & 0xFF000000) + | ((lc << 16) & 0x00FF0000) + | ((ls << 8) & 0x0000FF00) + | (es & 0xFF); +} /* - * Wait for IFLG to raise, or return 'timeout'; then if status is as expected, - * return 0 (ok) or return 'wrong status'. + * twsi_wait() - Wait for I2C bus interrupt flag and check status, or time out. + * + * @return Zero if status is as expected, or a non-zero code if either a time + * out occurred, or the status was not the expected one. */ -static int twsi_wait(struct i2c_adapter *adap, int expected_status) +static int twsi_wait(struct mvtwsi_registers *twsi, int expected_status, + uint tick) { - struct mvtwsi_registers *twsi = twsi_get_base(adap); int control, status; int timeout = 1000; @@ -173,105 +264,140 @@ static int twsi_wait(struct i2c_adapter *adap, int expected_status) if (status == expected_status) return 0; else - return MVTWSI_ERROR( + return mvtwsi_error( MVTWSI_ERROR_WRONG_STATUS, control, status, expected_status); } - udelay(10); /* one clock cycle at 100 kHz */ + ndelay(tick); /* One clock cycle */ } while (timeout--); status = readl(&twsi->status); - return MVTWSI_ERROR( - MVTWSI_ERROR_TIMEOUT, control, status, expected_status); + return mvtwsi_error(MVTWSI_ERROR_TIMEOUT, control, status, + expected_status); } /* - * Assert the START condition, either in a single I2C transaction - * or inside back-to-back ones (repeated starts). + * twsi_start() - Assert a START condition on the bus. + * + * This function is used in both single I2C transactions and inside + * back-to-back transactions (repeated starts). + * + * @twsi: The MVTWSI register structure to use. + * @expected_status: The I2C bus status expected to be asserted after the + * operation completion. + * @tick: The duration of a clock cycle at the current I2C speed. + * @return Zero if status is as expected, or a non-zero code if either a time + * out occurred or the status was not the expected one. */ -static int twsi_start(struct i2c_adapter *adap, int expected_status, u8 *flags) +static int twsi_start(struct mvtwsi_registers *twsi, int expected_status, + uint tick) { - struct mvtwsi_registers *twsi = twsi_get_base(adap); - - /* globally set TWSIEN in case it was not */ - *flags |= MVTWSI_CONTROL_TWSIEN; - /* assert START */ - writel(*flags | MVTWSI_CONTROL_START | - MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control); - /* wait for controller to process START */ - return twsi_wait(adap, expected_status); + /* Assert START */ + writel(MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_START | + MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control); + /* Wait for controller to process START */ + return twsi_wait(twsi, expected_status, tick); } /* - * Send a byte (i2c address or data). + * twsi_send() - Send a byte on the I2C bus. + * + * The byte may be part of an address byte or data. + * + * @twsi: The MVTWSI register structure to use. + * @byte: The byte to send. + * @expected_status: The I2C bus status expected to be asserted after the + * operation completion. + * @tick: The duration of a clock cycle at the current I2C speed. + * @return Zero if status is as expected, or a non-zero code if either a time + * out occurred or the status was not the expected one. */ -static int twsi_send(struct i2c_adapter *adap, u8 byte, int expected_status, - u8 *flags) +static int twsi_send(struct mvtwsi_registers *twsi, u8 byte, + int expected_status, uint tick) { - struct mvtwsi_registers *twsi = twsi_get_base(adap); - - /* put byte in data register for sending */ + /* Write byte to data register for sending */ writel(byte, &twsi->data); - /* clear any pending interrupt -- that'll cause sending */ - writel(*flags | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control); - /* wait for controller to receive byte and check ACK */ - return twsi_wait(adap, expected_status); + /* Clear any pending interrupt -- that will cause sending */ + writel(MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_CLEAR_IFLG, + &twsi->control); + /* Wait for controller to receive byte, and check ACK */ + return twsi_wait(twsi, expected_status, tick); } /* - * Receive a byte. - * Global mvtwsi_control_flags variable says if we should ack or nak. + * twsi_recv() - Receive a byte on the I2C bus. + * + * The static variable mvtwsi_control_flags controls whether we ack or nak. + * + * @twsi: The MVTWSI register structure to use. + * @byte: The byte to send. + * @ack_flag: Flag that determines whether the received byte should + * be acknowledged by the controller or not (sent ACK/NAK). + * @tick: The duration of a clock cycle at the current I2C speed. + * @return Zero if status is as expected, or a non-zero code if either a time + * out occurred or the status was not the expected one. */ -static int twsi_recv(struct i2c_adapter *adap, u8 *byte, u8 *flags) +static int twsi_recv(struct mvtwsi_registers *twsi, u8 *byte, int ack_flag, + uint tick) { - struct mvtwsi_registers *twsi = twsi_get_base(adap); - int expected_status, status; - - /* compute expected status based on ACK bit in global control flags */ - if (*flags & MVTWSI_CONTROL_ACK) - expected_status = MVTWSI_STATUS_DATA_R_ACK; - else - expected_status = MVTWSI_STATUS_DATA_R_NAK; - /* acknowledge *previous state* and launch receive */ - writel(*flags | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control); - /* wait for controller to receive byte and assert ACK or NAK */ - status = twsi_wait(adap, expected_status); - /* if we did receive expected byte then store it */ + int expected_status, status, control; + + /* Compute expected status based on passed ACK flag */ + expected_status = ack_flag ? MVTWSI_STATUS_DATA_R_ACK : + MVTWSI_STATUS_DATA_R_NAK; + /* Acknowledge *previous state*, and launch receive */ + control = MVTWSI_CONTROL_TWSIEN; + control |= ack_flag == MVTWSI_READ_ACK ? MVTWSI_CONTROL_ACK : 0; + writel(control | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control); + /* Wait for controller to receive byte, and assert ACK or NAK */ + status = twsi_wait(twsi, expected_status, tick); + /* If we did receive the expected byte, store it */ if (status == 0) *byte = readl(&twsi->data); - /* return status */ return status; } /* - * Assert the STOP condition. - * This is also used to force the bus back in idle (SDA=SCL=1). + * twsi_stop() - Assert a STOP condition on the bus. + * + * This function is also used to force the bus back to idle state (SDA = + * SCL = 1). + * + * @twsi: The MVTWSI register structure to use. + * @tick: The duration of a clock cycle at the current I2C speed. + * @return Zero if the operation succeeded, or a non-zero code if a time out + * occurred. */ -static int twsi_stop(struct i2c_adapter *adap, int status) +static int twsi_stop(struct mvtwsi_registers *twsi, uint tick) { - struct mvtwsi_registers *twsi = twsi_get_base(adap); int control, stop_status; + int status = 0; int timeout = 1000; - /* assert STOP */ + /* Assert STOP */ control = MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_STOP; writel(control | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control); - /* wait for IDLE; IFLG won't rise so twsi_wait() is no use. */ + /* Wait for IDLE; IFLG won't rise, so we can't use twsi_wait() */ do { stop_status = readl(&twsi->status); if (stop_status == MVTWSI_STATUS_IDLE) break; - udelay(10); /* one clock cycle at 100 kHz */ + ndelay(tick); /* One clock cycle */ } while (timeout--); control = readl(&twsi->control); if (stop_status != MVTWSI_STATUS_IDLE) - if (status == 0) - status = MVTWSI_ERROR( - MVTWSI_ERROR_TIMEOUT, - control, status, MVTWSI_STATUS_IDLE); + status = mvtwsi_error(MVTWSI_ERROR_TIMEOUT, + control, status, MVTWSI_STATUS_IDLE); return status; } -static unsigned int twsi_calc_freq(const int n, const int m) +/* + * twsi_calc_freq() - Compute I2C frequency depending on m and n parameters. + * + * @n: Parameter 'n' for the frequency calculation algorithm. + * @m: Parameter 'm' for the frequency calculation algorithm. + * @return The I2C frequency corresponding to the passed m and n parameters. + */ +static uint twsi_calc_freq(const int n, const int m) { #ifdef CONFIG_SUNXI return CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n)); @@ -281,176 +407,303 @@ static unsigned int twsi_calc_freq(const int n, const int m) } /* - * Reset controller. - * Controller reset also resets the baud rate and slave address, so - * they must be re-established afterwards. + * twsi_reset() - Reset the I2C controller. + * + * Resetting the controller also resets the baud rate and slave address, hence + * they must be re-established after the reset. + * + * @twsi: The MVTWSI register structure to use. */ -static void twsi_reset(struct i2c_adapter *adap) +static void twsi_reset(struct mvtwsi_registers *twsi) { - struct mvtwsi_registers *twsi = twsi_get_base(adap); - - /* reset controller */ + /* Reset controller */ writel(0, &twsi->soft_reset); - /* wait 2 ms -- this is what the Marvell LSP does */ + /* Wait 2 ms -- this is what the Marvell LSP does */ udelay(20000); } /* - * I2C init called by cmd_i2c when doing 'i2c reset'. - * Sets baud to the highest possible value not exceeding requested one. + * __twsi_i2c_set_bus_speed() - Set the speed of the I2C controller. + * + * This function sets baud rate to the highest possible value that does not + * exceed the requested rate. + * + * @twsi: The MVTWSI register structure to use. + * @requested_speed: The desired frequency the controller should run at + * in Hz. + * @return The actual frequency the controller was configured to. */ -static unsigned int twsi_i2c_set_bus_speed(struct i2c_adapter *adap, - unsigned int requested_speed) +static uint __twsi_i2c_set_bus_speed(struct mvtwsi_registers *twsi, + uint requested_speed) { - struct mvtwsi_registers *twsi = twsi_get_base(adap); - unsigned int tmp_speed, highest_speed, n, m; - unsigned int baud = 0x44; /* baudrate at controller reset */ + uint tmp_speed, highest_speed, n, m; + uint baud = 0x44; /* Baud rate after controller reset */ - /* use actual speed to collect progressively higher values */ highest_speed = 0; - /* compute m, n setting for highest speed not above requested speed */ + /* Successively try m, n combinations, and use the combination + * resulting in the largest speed that's not above the requested + * speed */ for (n = 0; n < 8; n++) { for (m = 0; m < 16; m++) { tmp_speed = twsi_calc_freq(n, m); - if ((tmp_speed <= requested_speed) - && (tmp_speed > highest_speed)) { + if ((tmp_speed <= requested_speed) && + (tmp_speed > highest_speed)) { highest_speed = tmp_speed; baud = (m << 3) | n; } } } writel(baud, &twsi->baudrate); - return 0; + + /* Wait for controller for one tick */ +#ifdef CONFIG_DM_I2C + ndelay(calc_tick(highest_speed)); +#else + ndelay(10000); +#endif + return highest_speed; } -static void twsi_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) +/* + * __twsi_i2c_init() - Initialize the I2C controller. + * + * @twsi: The MVTWSI register structure to use. + * @speed: The initial frequency the controller should run at + * in Hz. + * @slaveadd: The I2C address to be set for the I2C master. + * @actual_speed: A output parameter that receives the actual frequency + * in Hz the controller was set to by the function. + * @return Zero if the operation succeeded, or a non-zero code if a time out + * occurred. + */ +static void __twsi_i2c_init(struct mvtwsi_registers *twsi, int speed, + int slaveadd, uint *actual_speed) { - struct mvtwsi_registers *twsi = twsi_get_base(adap); - - /* reset controller */ - twsi_reset(adap); - /* set speed */ - twsi_i2c_set_bus_speed(adap, speed); - /* set slave address even though we don't use it */ + /* Reset controller */ + twsi_reset(twsi); + /* Set speed */ + *actual_speed = __twsi_i2c_set_bus_speed(twsi, speed); + /* Set slave address; even though we don't use it */ writel(slaveadd, &twsi->slave_address); writel(0, &twsi->xtnd_slave_addr); - /* assert STOP but don't care for the result */ - (void) twsi_stop(adap, 0); + /* Assert STOP, but don't care for the result */ +#ifdef CONFIG_DM_I2C + (void) twsi_stop(twsi, calc_tick(*actual_speed)); +#else + (void) twsi_stop(twsi, 10000); +#endif } /* - * Begin I2C transaction with expected start status, at given address. - * Common to i2c_probe, i2c_read and i2c_write. - * Expected address status will derive from direction bit (bit 0) in addr. + * i2c_begin() - Start a I2C transaction. + * + * Begin a I2C transaction with a given expected start status and chip address. + * A START is asserted, and the address byte is sent to the I2C controller. The + * expected address status will be derived from the direction bit (bit 0) of + * the address byte. + * + * @twsi: The MVTWSI register structure to use. + * @expected_start_status: The I2C status the controller is expected to + * assert after the address byte was sent. + * @addr: The address byte to be sent. + * @tick: The duration of a clock cycle at the current + * I2C speed. + * @return Zero if the operation succeeded, or a non-zero code if a time out or + * unexpected I2C status occurred. */ -static int i2c_begin(struct i2c_adapter *adap, int expected_start_status, - u8 addr, u8 *flags) +static int i2c_begin(struct mvtwsi_registers *twsi, int expected_start_status, + u8 addr, uint tick) { int status, expected_addr_status; - /* compute expected address status from direction bit in addr */ - if (addr & 1) /* reading */ + /* Compute the expected address status from the direction bit in + * the address byte */ + if (addr & 1) /* Reading */ expected_addr_status = MVTWSI_STATUS_ADDR_R_ACK; - else /* writing */ + else /* Writing */ expected_addr_status = MVTWSI_STATUS_ADDR_W_ACK; - /* assert START */ - status = twsi_start(adap, expected_start_status, flags); - /* send out the address if the start went well */ + /* Assert START */ + status = twsi_start(twsi, expected_start_status, tick); + /* Send out the address if the start went well */ if (status == 0) - status = twsi_send(adap, addr, expected_addr_status, - flags); - /* return ok or status of first failure to caller */ + status = twsi_send(twsi, addr, expected_addr_status, tick); + /* Return 0, or the status of the first failure */ return status; } /* - * I2C probe called by cmd_i2c when doing 'i2c probe'. - * Begin read, nak data byte, end. + * __twsi_i2c_probe_chip() - Probe the given I2C chip address. + * + * This function begins a I2C read transaction, does a dummy read and NAKs; if + * the procedure succeeds, the chip is considered to be present. + * + * @twsi: The MVTWSI register structure to use. + * @chip: The chip address to probe. + * @tick: The duration of a clock cycle at the current I2C speed. + * @return Zero if the operation succeeded, or a non-zero code if a time out or + * unexpected I2C status occurred. */ -static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip) +static int __twsi_i2c_probe_chip(struct mvtwsi_registers *twsi, uchar chip, + uint tick) { u8 dummy_byte; - u8 flags = 0; int status; - /* begin i2c read */ - status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1) | 1, &flags); - /* dummy read was accepted: receive byte but NAK it. */ + /* Begin i2c read */ + status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1) | 1, tick); + /* Dummy read was accepted: receive byte, but NAK it. */ if (status == 0) - status = twsi_recv(adap, &dummy_byte, &flags); + status = twsi_recv(twsi, &dummy_byte, MVTWSI_READ_NAK, tick); /* Stop transaction */ - twsi_stop(adap, 0); - /* return 0 or status of first failure */ + twsi_stop(twsi, tick); + /* Return 0, or the status of the first failure */ return status; } /* - * I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c - * Begin write, send address byte(s), begin read, receive data bytes, end. - * - * NOTE: some EEPROMS want a stop right before the second start, while - * some will choke if it is there. Deciding which we should do is eeprom - * stuff, not i2c, but at the moment the APIs won't let us put it in - * cmd_eeprom, so we have to choose here, and for the moment that'll be - * a repeated start without a preceding stop. + * __twsi_i2c_read() - Read data from a I2C chip. + * + * This function begins a I2C write transaction, and transmits the address + * bytes; then begins a I2C read transaction, and receives the data bytes. + * + * NOTE: Some devices want a stop right before the second start, while some + * will choke if it is there. Since deciding this is not yet supported in + * higher level APIs, we need to make a decision here, and for the moment that + * will be a repeated start without a preceding stop. + * + * @twsi: The MVTWSI register structure to use. + * @chip: The chip address to read from. + * @addr: The address bytes to send. + * @alen: The length of the address bytes in bytes. + * @data: The buffer to receive the data read from the chip (has to have + * a size of at least 'length' bytes). + * @length: The amount of data to be read from the chip in bytes. + * @tick: The duration of a clock cycle at the current I2C speed. + * @return Zero if the operation succeeded, or a non-zero code if a time out or + * unexpected I2C status occurred. */ -static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, - int alen, uchar *data, int length) +static int __twsi_i2c_read(struct mvtwsi_registers *twsi, uchar chip, + u8 *addr, int alen, uchar *data, int length, + uint tick) { - int status; - u8 flags = 0; - - /* begin i2c write to send the address bytes */ - status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1), &flags); - /* send addr bytes */ - while ((status == 0) && alen--) - status = twsi_send(adap, addr >> (8*alen), - MVTWSI_STATUS_DATA_W_ACK, &flags); - /* begin i2c read to receive eeprom data bytes */ - if (status == 0) - status = i2c_begin(adap, MVTWSI_STATUS_REPEATED_START, - (chip << 1) | 1, &flags); - /* prepare ACK if at least one byte must be received */ - if (length > 0) - flags |= MVTWSI_CONTROL_ACK; - /* now receive actual bytes */ - while ((status == 0) && length--) { - /* reset NAK if we if no more to read now */ - if (length == 0) - flags &= ~MVTWSI_CONTROL_ACK; - /* read current byte */ - status = twsi_recv(adap, data++, &flags); + int status = 0; + int stop_status; + int expected_start = MVTWSI_STATUS_START; + + if (alen > 0) { + /* Begin i2c write to send the address bytes */ + status = i2c_begin(twsi, expected_start, (chip << 1), tick); + /* Send address bytes */ + while ((status == 0) && alen--) + status = twsi_send(twsi, *(addr++), + MVTWSI_STATUS_DATA_W_ACK, tick); + /* Send repeated STARTs after the initial START */ + expected_start = MVTWSI_STATUS_REPEATED_START; } + /* Begin i2c read to receive data bytes */ + if (status == 0) + status = i2c_begin(twsi, expected_start, (chip << 1) | 1, tick); + /* Receive actual data bytes; set NAK if we if we have nothing more to + * read */ + while ((status == 0) && length--) + status = twsi_recv(twsi, data++, + length > 0 ? + MVTWSI_READ_ACK : MVTWSI_READ_NAK, tick); /* Stop transaction */ - status = twsi_stop(adap, status); - /* return 0 or status of first failure */ - return status; + stop_status = twsi_stop(twsi, tick); + /* Return 0, or the status of the first failure */ + return status != 0 ? status : stop_status; } /* - * I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c - * Begin write, send address byte(s), send data bytes, end. + * __twsi_i2c_write() - Send data to a I2C chip. + * + * This function begins a I2C write transaction, and transmits the address + * bytes; then begins a new I2C write transaction, and sends the data bytes. + * + * @twsi: The MVTWSI register structure to use. + * @chip: The chip address to read from. + * @addr: The address bytes to send. + * @alen: The length of the address bytes in bytes. + * @data: The buffer containing the data to be sent to the chip. + * @length: The length of data to be sent to the chip in bytes. + * @tick: The duration of a clock cycle at the current I2C speed. + * @return Zero if the operation succeeded, or a non-zero code if a time out or + * unexpected I2C status occurred. */ -static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, - int alen, uchar *data, int length) +static int __twsi_i2c_write(struct mvtwsi_registers *twsi, uchar chip, + u8 *addr, int alen, uchar *data, int length, + uint tick) { - int status; - u8 flags = 0; - - /* begin i2c write to send the eeprom adress bytes then data bytes */ - status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1), &flags); - /* send addr bytes */ - while ((status == 0) && alen--) - status = twsi_send(adap, addr >> (8*alen), - MVTWSI_STATUS_DATA_W_ACK, &flags); - /* send data bytes */ + int status, stop_status; + + /* Begin i2c write to send first the address bytes, then the + * data bytes */ + status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1), tick); + /* Send address bytes */ + while ((status == 0) && (alen-- > 0)) + status = twsi_send(twsi, *(addr++), MVTWSI_STATUS_DATA_W_ACK, + tick); + /* Send data bytes */ while ((status == 0) && (length-- > 0)) - status = twsi_send(adap, *(data++), MVTWSI_STATUS_DATA_W_ACK, - &flags); + status = twsi_send(twsi, *(data++), MVTWSI_STATUS_DATA_W_ACK, + tick); /* Stop transaction */ - status = twsi_stop(adap, status); - /* return 0 or status of first failure */ - return status; + stop_status = twsi_stop(twsi, tick); + /* Return 0, or the status of the first failure */ + return status != 0 ? status : stop_status; +} + +#ifndef CONFIG_DM_I2C +static void twsi_i2c_init(struct i2c_adapter *adap, int speed, + int slaveadd) +{ + struct mvtwsi_registers *twsi = twsi_get_base(adap); + __twsi_i2c_init(twsi, speed, slaveadd, NULL); +} + +static uint twsi_i2c_set_bus_speed(struct i2c_adapter *adap, + uint requested_speed) +{ + struct mvtwsi_registers *twsi = twsi_get_base(adap); + __twsi_i2c_set_bus_speed(twsi, requested_speed); + return 0; +} + +static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip) +{ + struct mvtwsi_registers *twsi = twsi_get_base(adap); + return __twsi_i2c_probe_chip(twsi, chip, 10000); +} + +static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, + int alen, uchar *data, int length) +{ + struct mvtwsi_registers *twsi = twsi_get_base(adap); + u8 addr_bytes[4]; + + addr_bytes[0] = (addr >> 0) & 0xFF; + addr_bytes[1] = (addr >> 8) & 0xFF; + addr_bytes[2] = (addr >> 16) & 0xFF; + addr_bytes[3] = (addr >> 24) & 0xFF; + + return __twsi_i2c_read(twsi, chip, addr_bytes, alen, data, length, + 10000); +} + +static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, + int alen, uchar *data, int length) +{ + struct mvtwsi_registers *twsi = twsi_get_base(adap); + u8 addr_bytes[4]; + + addr_bytes[0] = (addr >> 0) & 0xFF; + addr_bytes[1] = (addr >> 8) & 0xFF; + addr_bytes[2] = (addr >> 16) & 0xFF; + addr_bytes[3] = (addr >> 24) & 0xFF; + + return __twsi_i2c_write(twsi, chip, addr_bytes, alen, data, length, + 10000); } #ifdef CONFIG_I2C_MVTWSI_BASE0 @@ -494,3 +747,99 @@ U_BOOT_I2C_ADAP_COMPLETE(twsi5, twsi_i2c_init, twsi_i2c_probe, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 5) #endif +#else /* CONFIG_DM_I2C */ + +static int mvtwsi_i2c_probe_chip(struct udevice *bus, u32 chip_addr, + u32 chip_flags) +{ + struct mvtwsi_i2c_dev *dev = dev_get_priv(bus); + return __twsi_i2c_probe_chip(dev->base, chip_addr, dev->tick); +} + +static int mvtwsi_i2c_set_bus_speed(struct udevice *bus, uint speed) +{ + struct mvtwsi_i2c_dev *dev = dev_get_priv(bus); + + dev->speed = __twsi_i2c_set_bus_speed(dev->base, speed); + dev->tick = calc_tick(dev->speed); + + return 0; +} + +static int mvtwsi_i2c_ofdata_to_platdata(struct udevice *bus) +{ + struct mvtwsi_i2c_dev *dev = dev_get_priv(bus); + + dev->base = dev_get_addr_ptr(bus); + + if (!dev->base) + return -ENOMEM; + + dev->index = fdtdec_get_int(gd->fdt_blob, bus->of_offset, + "cell-index", -1); + dev->slaveadd = fdtdec_get_int(gd->fdt_blob, bus->of_offset, + "u-boot,i2c-slave-addr", 0x0); + dev->speed = fdtdec_get_int(gd->fdt_blob, bus->of_offset, + "clock-frequency", 100000); + return 0; +} + +static int mvtwsi_i2c_probe(struct udevice *bus) +{ + struct mvtwsi_i2c_dev *dev = dev_get_priv(bus); + uint actual_speed; + + __twsi_i2c_init(dev->base, dev->speed, dev->slaveadd, &actual_speed); + dev->speed = actual_speed; + dev->tick = calc_tick(dev->speed); + return 0; +} + +static int mvtwsi_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) +{ + struct mvtwsi_i2c_dev *dev = dev_get_priv(bus); + struct i2c_msg *dmsg, *omsg, dummy; + + memset(&dummy, 0, sizeof(struct i2c_msg)); + + /* We expect either two messages (one with an offset and one with the + * actual data) or one message (just data or offset/data combined) */ + if (nmsgs > 2 || nmsgs == 0) { + debug("%s: Only one or two messages are supported.", __func__); + return -1; + } + + omsg = nmsgs == 1 ? &dummy : msg; + dmsg = nmsgs == 1 ? msg : msg + 1; + + if (dmsg->flags & I2C_M_RD) + return __twsi_i2c_read(dev->base, dmsg->addr, omsg->buf, + omsg->len, dmsg->buf, dmsg->len, + dev->tick); + else + return __twsi_i2c_write(dev->base, dmsg->addr, omsg->buf, + omsg->len, dmsg->buf, dmsg->len, + dev->tick); +} + +static const struct dm_i2c_ops mvtwsi_i2c_ops = { + .xfer = mvtwsi_i2c_xfer, + .probe_chip = mvtwsi_i2c_probe_chip, + .set_bus_speed = mvtwsi_i2c_set_bus_speed, +}; + +static const struct udevice_id mvtwsi_i2c_ids[] = { + { .compatible = "marvell,mv64xxx-i2c", }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(i2c_mvtwsi) = { + .name = "i2c_mvtwsi", + .id = UCLASS_I2C, + .of_match = mvtwsi_i2c_ids, + .probe = mvtwsi_i2c_probe, + .ofdata_to_platdata = mvtwsi_i2c_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct mvtwsi_i2c_dev), + .ops = &mvtwsi_i2c_ops, +}; +#endif /* CONFIG_DM_I2C */ diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index a7f3fb4a799..00063431040 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -39,6 +39,7 @@ */ #include <common.h> +#include <dm.h> #include <i2c.h> #include <asm/arch/i2c.h> @@ -53,10 +54,14 @@ DECLARE_GLOBAL_DATA_PTR; /* Absolutely safe for status update at 100 kHz I2C: */ #define I2C_WAIT 200 -static int wait_for_bb(struct i2c_adapter *adap); -static struct i2c *omap24_get_base(struct i2c_adapter *adap); -static u16 wait_for_event(struct i2c_adapter *adap); -static void flush_fifo(struct i2c_adapter *adap); +struct omap_i2c { + struct udevice *clk; + struct i2c *regs; + unsigned int speed; + int waitdelay; + int clk_id; +}; + static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed) { unsigned int sampleclk, prescaler; @@ -90,9 +95,96 @@ static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed) } return -1; } -static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed) + +/* + * Wait for the bus to be free by checking the Bus Busy (BB) + * bit to become clear + */ +static int wait_for_bb(struct i2c *i2c_base, int waitdelay) +{ + int timeout = I2C_TIMEOUT; + u16 stat; + + writew(0xFFFF, &i2c_base->stat); /* clear current interrupts...*/ +#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) + while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) { +#else + /* Read RAW status */ + while ((stat = readw(&i2c_base->irqstatus_raw) & + I2C_STAT_BB) && timeout--) { +#endif + writew(stat, &i2c_base->stat); + udelay(waitdelay); + } + + if (timeout <= 0) { + printf("Timed out in wait_for_bb: status=%04x\n", + stat); + return 1; + } + writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/ + return 0; +} + +/* + * Wait for the I2C controller to complete current action + * and update status + */ +static u16 wait_for_event(struct i2c *i2c_base, int waitdelay) +{ + u16 status; + int timeout = I2C_TIMEOUT; + + do { + udelay(waitdelay); +#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) + status = readw(&i2c_base->stat); +#else + /* Read RAW status */ + status = readw(&i2c_base->irqstatus_raw); +#endif + } while (!(status & + (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY | + I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK | + I2C_STAT_AL)) && timeout--); + + if (timeout <= 0) { + printf("Timed out in wait_for_event: status=%04x\n", + status); + /* + * If status is still 0 here, probably the bus pads have + * not been configured for I2C, and/or pull-ups are missing. + */ + printf("Check if pads/pull-ups of bus are properly configured\n"); + writew(0xFFFF, &i2c_base->stat); + status = 0; + } + + return status; +} + +static void flush_fifo(struct i2c *i2c_base) +{ + u16 stat; + + /* + * note: if you try and read data when its not there or ready + * you get a bus error + */ + while (1) { + stat = readw(&i2c_base->stat); + if (stat == I2C_STAT_RRDY) { + readb(&i2c_base->data); + writew(I2C_STAT_RRDY, &i2c_base->stat); + udelay(1000); + } else + break; + } +} + +static int __omap24_i2c_setspeed(struct i2c *i2c_base, uint speed, + int *waitdelay) { - struct i2c *i2c_base = omap24_get_base(adap); int psc, fsscll = 0, fssclh = 0; int hsscll = 0, hssclh = 0; u32 scll = 0, sclh = 0; @@ -142,8 +234,7 @@ static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed) } } - adap->speed = speed; - adap->waitdelay = (10000000 / speed) * 2; /* wait for 20 clkperiods */ + *waitdelay = (10000000 / speed) * 2; /* wait for 20 clkperiods */ writew(0, &i2c_base->con); writew(psc, &i2c_base->psc); writew(scll, &i2c_base->scll); @@ -154,9 +245,8 @@ static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed) return 0; } -static void omap24_i2c_deblock(struct i2c_adapter *adap) +static void omap24_i2c_deblock(struct i2c *i2c_base) { - struct i2c *i2c_base = omap24_get_base(adap); int i; u16 systest; u16 orgsystest; @@ -200,9 +290,9 @@ static void omap24_i2c_deblock(struct i2c_adapter *adap) writew(orgsystest, &i2c_base->systest); } -static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) +static void __omap24_i2c_init(struct i2c *i2c_base, int speed, int slaveadd, + int *waitdelay) { - struct i2c *i2c_base = omap24_get_base(adap); int timeout = I2C_TIMEOUT; int deblock = 1; @@ -224,7 +314,7 @@ retry: udelay(1000); } - if (0 != omap24_i2c_setspeed(adap, speed)) { + if (0 != __omap24_i2c_setspeed(i2c_base, speed, waitdelay)) { printf("ERROR: failed to setup I2C bus-speed!\n"); return; } @@ -241,45 +331,24 @@ retry: I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie); #endif udelay(1000); - flush_fifo(adap); + flush_fifo(i2c_base); writew(0xFFFF, &i2c_base->stat); /* Handle possible failed I2C state */ - if (wait_for_bb(adap)) + if (wait_for_bb(i2c_base, *waitdelay)) if (deblock == 1) { - omap24_i2c_deblock(adap); + omap24_i2c_deblock(i2c_base); deblock = 0; goto retry; } } -static void flush_fifo(struct i2c_adapter *adap) -{ - struct i2c *i2c_base = omap24_get_base(adap); - u16 stat; - - /* - * note: if you try and read data when its not there or ready - * you get a bus error - */ - while (1) { - stat = readw(&i2c_base->stat); - if (stat == I2C_STAT_RRDY) { - readb(&i2c_base->data); - writew(I2C_STAT_RRDY, &i2c_base->stat); - udelay(1000); - } else - break; - } -} - /* * i2c_probe: Use write access. Allows to identify addresses that are * write-only (like the config register of dual-port EEPROMs) */ -static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip) +static int __omap24_i2c_probe(struct i2c *i2c_base, int waitdelay, uchar chip) { - struct i2c *i2c_base = omap24_get_base(adap); u16 status; int res = 1; /* default = fail */ @@ -287,7 +356,7 @@ static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip) return res; /* Wait until bus is free */ - if (wait_for_bb(adap)) + if (wait_for_bb(i2c_base, waitdelay)) return res; /* No data transfer, slave addr only */ @@ -296,7 +365,7 @@ static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip) writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP, &i2c_base->con); - status = wait_for_event(adap); + status = wait_for_event(i2c_base, waitdelay); if ((status & ~I2C_STAT_XRDY) == 0 || (status & I2C_STAT_AL)) { /* @@ -306,8 +375,8 @@ static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip) * following 'if' section: */ if (status == I2C_STAT_XRDY) - printf("i2c_probe: pads on bus %d probably not configured (status=0x%x)\n", - adap->hwadapnr, status); + printf("i2c_probe: pads on bus probably not configured (status=0x%x)\n", + status); goto pr_exit; } @@ -315,7 +384,7 @@ static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip) /* Check for ACK (!NAK) */ if (!(status & I2C_STAT_NACK)) { res = 0; /* Device found */ - udelay(adap->waitdelay);/* Required by AM335X in SPL */ + udelay(waitdelay);/* Required by AM335X in SPL */ /* Abort transfer (force idle state) */ writew(I2C_CON_MST | I2C_CON_TRX, &i2c_base->con); /* Reset */ udelay(1000); @@ -323,7 +392,7 @@ static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip) I2C_CON_STP, &i2c_base->con); /* STP */ } pr_exit: - flush_fifo(adap); + flush_fifo(i2c_base); writew(0xFFFF, &i2c_base->stat); return res; } @@ -341,10 +410,9 @@ pr_exit: * or that do not need a register address at all (such as some clock * distributors). */ -static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, - int alen, uchar *buffer, int len) +static int __omap24_i2c_read(struct i2c *i2c_base, int waitdelay, uchar chip, + uint addr, int alen, uchar *buffer, int len) { - struct i2c *i2c_base = omap24_get_base(adap); int i2c_error = 0; u16 status; @@ -389,7 +457,7 @@ static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, #endif /* Wait until bus not busy */ - if (wait_for_bb(adap)) + if (wait_for_bb(i2c_base, waitdelay)) return 1; /* Zero, one or two bytes reg address (offset) */ @@ -410,12 +478,12 @@ static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, #endif /* Send register offset */ while (1) { - status = wait_for_event(adap); + status = wait_for_event(i2c_base, waitdelay); /* Try to identify bus that is not padconf'd for I2C */ if (status == I2C_STAT_XRDY) { i2c_error = 2; - printf("i2c_read (addr phase): pads on bus %d probably not configured (status=0x%x)\n", - adap->hwadapnr, status); + printf("i2c_read (addr phase): pads on bus probably not configured (status=0x%x)\n", + status); goto rd_exit; } if (status == 0 || (status & I2C_STAT_NACK)) { @@ -450,7 +518,7 @@ static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, /* Receive data */ while (1) { - status = wait_for_event(adap); + status = wait_for_event(i2c_base, waitdelay); /* * Try to identify bus that is not padconf'd for I2C. This * state could be left over from previous transactions if @@ -458,8 +526,8 @@ static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, */ if (status == I2C_STAT_XRDY) { i2c_error = 2; - printf("i2c_read (data phase): pads on bus %d probably not configured (status=0x%x)\n", - adap->hwadapnr, status); + printf("i2c_read (data phase): pads on bus probably not configured (status=0x%x)\n", + status); goto rd_exit; } if (status == 0 || (status & I2C_STAT_NACK)) { @@ -477,16 +545,15 @@ static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, } rd_exit: - flush_fifo(adap); + flush_fifo(i2c_base); writew(0xFFFF, &i2c_base->stat); return i2c_error; } /* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */ -static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, - int alen, uchar *buffer, int len) +static int __omap24_i2c_write(struct i2c *i2c_base, int waitdelay, uchar chip, + uint addr, int alen, uchar *buffer, int len) { - struct i2c *i2c_base = omap24_get_base(adap); int i; u16 status; int i2c_error = 0; @@ -536,7 +603,7 @@ static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, #endif /* Wait until bus not busy */ - if (wait_for_bb(adap)) + if (wait_for_bb(i2c_base, waitdelay)) return 1; /* Start address phase - will write regoffset + len bytes data */ @@ -549,12 +616,12 @@ static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, while (alen) { /* Must write reg offset (one or two bytes) */ - status = wait_for_event(adap); + status = wait_for_event(i2c_base, waitdelay); /* Try to identify bus that is not padconf'd for I2C */ if (status == I2C_STAT_XRDY) { i2c_error = 2; - printf("i2c_write: pads on bus %d probably not configured (status=0x%x)\n", - adap->hwadapnr, status); + printf("i2c_write: pads on bus probably not configured (status=0x%x)\n", + status); goto wr_exit; } if (status == 0 || (status & I2C_STAT_NACK)) { @@ -576,7 +643,7 @@ static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, } /* Address phase is over, now write data */ for (i = 0; i < len; i++) { - status = wait_for_event(adap); + status = wait_for_event(i2c_base, waitdelay); if (status == 0 || (status & I2C_STAT_NACK)) { i2c_error = 1; printf("i2c_write: error waiting for data ACK (status=0x%x)\n", @@ -598,87 +665,22 @@ static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, * transferred on the bus. */ do { - status = wait_for_event(adap); + status = wait_for_event(i2c_base, waitdelay); } while (!(status & I2C_STAT_ARDY) && timeout--); if (timeout <= 0) printf("i2c_write: timed out writig last byte!\n"); wr_exit: - flush_fifo(adap); + flush_fifo(i2c_base); writew(0xFFFF, &i2c_base->stat); return i2c_error; } +#ifndef CONFIG_DM_I2C /* - * Wait for the bus to be free by checking the Bus Busy (BB) - * bit to become clear - */ -static int wait_for_bb(struct i2c_adapter *adap) -{ - struct i2c *i2c_base = omap24_get_base(adap); - int timeout = I2C_TIMEOUT; - u16 stat; - - writew(0xFFFF, &i2c_base->stat); /* clear current interrupts...*/ -#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) - while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) { -#else - /* Read RAW status */ - while ((stat = readw(&i2c_base->irqstatus_raw) & - I2C_STAT_BB) && timeout--) { -#endif - writew(stat, &i2c_base->stat); - udelay(adap->waitdelay); - } - - if (timeout <= 0) { - printf("Timed out in wait_for_bb: status=%04x\n", - stat); - return 1; - } - writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/ - return 0; -} - -/* - * Wait for the I2C controller to complete current action - * and update status + * The legacy I2C functions. These need to get removed once + * all users of this driver are converted to DM. */ -static u16 wait_for_event(struct i2c_adapter *adap) -{ - struct i2c *i2c_base = omap24_get_base(adap); - u16 status; - int timeout = I2C_TIMEOUT; - - do { - udelay(adap->waitdelay); -#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) - status = readw(&i2c_base->stat); -#else - /* Read RAW status */ - status = readw(&i2c_base->irqstatus_raw); -#endif - } while (!(status & - (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY | - I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK | - I2C_STAT_AL)) && timeout--); - - if (timeout <= 0) { - printf("Timed out in wait_for_event: status=%04x\n", - status); - /* - * If status is still 0 here, probably the bus pads have - * not been configured for I2C, and/or pull-ups are missing. - */ - printf("Check if pads/pull-ups of bus %d are properly configured\n", - adap->hwadapnr); - writew(0xFFFF, &i2c_base->stat); - status = 0; - } - - return status; -} - static struct i2c *omap24_get_base(struct i2c_adapter *adap) { switch (adap->hwadapnr) { @@ -710,6 +712,56 @@ static struct i2c *omap24_get_base(struct i2c_adapter *adap) return NULL; } + +static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, + int alen, uchar *buffer, int len) +{ + struct i2c *i2c_base = omap24_get_base(adap); + + return __omap24_i2c_read(i2c_base, adap->waitdelay, chip, addr, + alen, buffer, len); +} + + +static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, + int alen, uchar *buffer, int len) +{ + struct i2c *i2c_base = omap24_get_base(adap); + + return __omap24_i2c_write(i2c_base, adap->waitdelay, chip, addr, + alen, buffer, len); +} + +static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed) +{ + struct i2c *i2c_base = omap24_get_base(adap); + int ret; + + ret = __omap24_i2c_setspeed(i2c_base, speed, &adap->waitdelay); + if (ret) { + error("%s: set i2c speed failed\n", __func__); + return ret; + } + + adap->speed = speed; + + return 0; +} + +static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) +{ + struct i2c *i2c_base = omap24_get_base(adap); + + return __omap24_i2c_init(i2c_base, speed, slaveadd, &adap->waitdelay); +} + +static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip) +{ + struct i2c *i2c_base = omap24_get_base(adap); + + return __omap24_i2c_probe(i2c_base, adap->waitdelay, chip); +} + #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED1) #define CONFIG_SYS_OMAP24_I2C_SPEED1 CONFIG_SYS_OMAP24_I2C_SPEED #endif @@ -769,3 +821,92 @@ U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe, #endif #endif #endif + +#else /* CONFIG_DM_I2C */ + +static int omap_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) +{ + struct omap_i2c *priv = dev_get_priv(bus); + int ret; + + debug("i2c_xfer: %d messages\n", nmsgs); + for (; nmsgs > 0; nmsgs--, msg++) { + debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len); + if (msg->flags & I2C_M_RD) { + ret = __omap24_i2c_read(priv->regs, priv->waitdelay, + msg->addr, 0, 0, msg->buf, + msg->len); + } else { + ret = __omap24_i2c_write(priv->regs, priv->waitdelay, + msg->addr, 0, 0, msg->buf, + msg->len); + } + if (ret) { + debug("i2c_write: error sending\n"); + return -EREMOTEIO; + } + } + + return 0; +} + +static int omap_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) +{ + struct omap_i2c *priv = dev_get_priv(bus); + + priv->speed = speed; + + return __omap24_i2c_setspeed(priv->regs, speed, &priv->waitdelay); +} + +static int omap_i2c_probe_chip(struct udevice *bus, uint chip_addr, + uint chip_flags) +{ + struct omap_i2c *priv = dev_get_priv(bus); + + return __omap24_i2c_probe(priv->regs, priv->waitdelay, chip_addr); +} + +static int omap_i2c_probe(struct udevice *bus) +{ + struct omap_i2c *priv = dev_get_priv(bus); + + __omap24_i2c_init(priv->regs, priv->speed, 0, &priv->waitdelay); + + return 0; +} + +static int omap_i2c_ofdata_to_platdata(struct udevice *bus) +{ + struct omap_i2c *priv = dev_get_priv(bus); + + priv->regs = map_physmem(dev_get_addr(bus), sizeof(void *), + MAP_NOCACHE); + priv->speed = CONFIG_SYS_OMAP24_I2C_SPEED; + + return 0; +} + +static const struct dm_i2c_ops omap_i2c_ops = { + .xfer = omap_i2c_xfer, + .probe_chip = omap_i2c_probe_chip, + .set_bus_speed = omap_i2c_set_bus_speed, +}; + +static const struct udevice_id omap_i2c_ids[] = { + { .compatible = "ti,omap4-i2c" }, + { } +}; + +U_BOOT_DRIVER(i2c_omap) = { + .name = "i2c_omap", + .id = UCLASS_I2C, + .of_match = omap_i2c_ids, + .ofdata_to_platdata = omap_i2c_ofdata_to_platdata, + .probe = omap_i2c_probe, + .priv_auto_alloc_size = sizeof(struct omap_i2c), + .ops = &omap_i2c_ops, + .flags = DM_FLAG_PRE_RELOC, +}; + +#endif /* CONFIG_DM_I2C */ diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c index dc9b661c1cf..eab49d09bab 100644 --- a/drivers/i2c/s3c24x0_i2c.c +++ b/drivers/i2c/s3c24x0_i2c.c @@ -1433,7 +1433,6 @@ U_BOOT_DRIVER(i2c_s3c) = { .id = UCLASS_I2C, .of_match = s3c_i2c_ids, .ofdata_to_platdata = s3c_i2c_ofdata_to_platdata, - .per_child_auto_alloc_size = sizeof(struct dm_i2c_chip), .priv_auto_alloc_size = sizeof(struct s3c24x0_i2c_bus), .ops = &s3c_i2c_ops, }; @@ -1458,7 +1457,6 @@ U_BOOT_DRIVER(hs_i2c) = { .id = UCLASS_I2C, .of_match = exynos_hs_i2c_ids, .ofdata_to_platdata = s3c_i2c_ofdata_to_platdata, - .per_child_auto_alloc_size = sizeof(struct dm_i2c_chip), .priv_auto_alloc_size = sizeof(struct s3c24x0_i2c_bus), .ops = &exynos_hs_i2c_ops, }; diff --git a/drivers/i2c/sandbox_i2c.c b/drivers/i2c/sandbox_i2c.c index 2c84c41643c..4696a1ae62a 100644 --- a/drivers/i2c/sandbox_i2c.c +++ b/drivers/i2c/sandbox_i2c.c @@ -14,7 +14,6 @@ #include <asm/test.h> #include <dm/lists.h> #include <dm/device-internal.h> -#include <dm/root.h> DECLARE_GLOBAL_DATA_PTR; @@ -33,8 +32,7 @@ static int get_emul(struct udevice *dev, struct udevice **devp, *opsp = NULL; plat = dev_get_parent_platdata(dev); if (!plat->emul) { - ret = dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, - false); + ret = dm_scan_fdt_dev(dev); if (ret) return ret; diff --git a/drivers/i2c/tegra186_bpmp_i2c.c b/drivers/i2c/tegra186_bpmp_i2c.c new file mode 100644 index 00000000000..88e8413d9e0 --- /dev/null +++ b/drivers/i2c/tegra186_bpmp_i2c.c @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <dm.h> +#include <i2c.h> +#include <misc.h> +#include <asm/arch-tegra/bpmp_abi.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct tegra186_bpmp_i2c { + uint32_t bpmp_bus_id; +}; + +static inline void serialize_u16(uint8_t **p, uint16_t val) +{ + (*p)[0] = val & 0xff; + (*p)[1] = val >> 8; + (*p) += 2; +} + +/* These just happen to have the same values as I2C_M_* and SERIALI2C_* */ +#define SUPPORTED_FLAGS \ + (I2C_M_TEN | \ + I2C_M_RD | \ + I2C_M_STOP | \ + I2C_M_NOSTART | \ + I2C_M_REV_DIR_ADDR | \ + I2C_M_IGNORE_NAK | \ + I2C_M_NO_RD_ACK | \ + I2C_M_RECV_LEN) + +static int tegra186_bpmp_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, + int nmsgs) +{ + struct tegra186_bpmp_i2c *priv = dev_get_priv(dev); + struct mrq_i2c_request req; + struct mrq_i2c_response resp; + uint8_t *p; + int left, i, ret; + + req.cmd = CMD_I2C_XFER; + req.xfer.bus_id = priv->bpmp_bus_id; + p = &req.xfer.data_buf[0]; + left = ARRAY_SIZE(req.xfer.data_buf); + for (i = 0; i < nmsgs; i++) { + int len = 6; + if (!(msg[i].flags & I2C_M_RD)) + len += msg[i].len; + if ((len >= BIT(16)) || (len > left)) + return -ENOSPC; + + if (msg[i].flags & ~SUPPORTED_FLAGS) + return -EINVAL; + + serialize_u16(&p, msg[i].addr); + serialize_u16(&p, msg[i].flags); + serialize_u16(&p, msg[i].len); + if (!(msg[i].flags & I2C_M_RD)) { + memcpy(p, msg[i].buf, msg[i].len); + p += msg[i].len; + } + } + req.xfer.data_size = p - &req.xfer.data_buf[0]; + + ret = misc_call(dev->parent, MRQ_I2C, &req, sizeof(req), &resp, + sizeof(resp)); + if (ret < 0) + return ret; + + p = &resp.xfer.data_buf[0]; + left = resp.xfer.data_size; + if (left > ARRAY_SIZE(resp.xfer.data_buf)) + return -EINVAL; + for (i = 0; i < nmsgs; i++) { + if (msg[i].flags & I2C_M_RD) { + memcpy(msg[i].buf, p, msg[i].len); + p += msg[i].len; + } + } + + return 0; +} + +static int tegra186_bpmp_i2c_probe(struct udevice *dev) +{ + struct tegra186_bpmp_i2c *priv = dev_get_priv(dev); + int ret; + struct fdtdec_phandle_args args; + + ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev->of_offset, + "nvidia,bpmp", NULL, 0, 0, &args); + if (ret < 0) { + debug("%s: fdtdec_parse_phandle_with_args() failed: %d\n", + __func__, ret); + return ret; + } + + priv->bpmp_bus_id = fdtdec_get_uint(gd->fdt_blob, dev->of_offset, + "nvidia,bpmp-bus-id", U32_MAX); + if (priv->bpmp_bus_id == U32_MAX) { + debug("%s: could not parse nvidia,bpmp-bus-id\n", __func__); + return -ENODEV; + } + + return 0; +} + +static const struct dm_i2c_ops tegra186_bpmp_i2c_ops = { + .xfer = tegra186_bpmp_i2c_xfer, +}; + +static const struct udevice_id tegra186_bpmp_i2c_ids[] = { + { .compatible = "nvidia,tegra186-bpmp-i2c" }, + { } +}; + +U_BOOT_DRIVER(i2c_gpio) = { + .name = "tegra186_bpmp_i2c", + .id = UCLASS_I2C, + .of_match = tegra186_bpmp_i2c_ids, + .probe = tegra186_bpmp_i2c_probe, + .priv_auto_alloc_size = sizeof(struct tegra186_bpmp_i2c), + .ops = &tegra186_bpmp_i2c_ops, +}; diff --git a/drivers/i2c/tegra_i2c.c b/drivers/i2c/tegra_i2c.c index 2fa07f9c57c..31ba263b729 100644 --- a/drivers/i2c/tegra_i2c.c +++ b/drivers/i2c/tegra_i2c.c @@ -12,13 +12,27 @@ #include <fdtdec.h> #include <i2c.h> #include <asm/io.h> +#ifdef CONFIG_TEGRA186 +#include <clk.h> +#include <reset.h> +#else #include <asm/arch/clock.h> #include <asm/arch/funcmux.h> -#include <asm/arch/gpio.h> #include <asm/arch/pinmux.h> #include <asm/arch-tegra/clk_rst.h> +#endif +#include <asm/arch/gpio.h> #include <asm/arch-tegra/tegra_i2c.h> +/* + * FIXME: TODO: This driver contains a number of ifdef CONFIG_TEGRA186 that + * should not be present. These are needed because newer Tegra SoCs support + * only the standard clock/reset APIs, whereas older Tegra SoCs support only + * a custom Tegra-specific API. ASAP the older Tegra SoCs' code should be + * fixed to implement the standard APIs, and all drivers converted to solely + * use the new standard APIs, with no ifdefs. + */ + DECLARE_GLOBAL_DATA_PTR; enum i2c_type { @@ -30,7 +44,12 @@ enum i2c_type { /* Information about i2c controller */ struct i2c_bus { int id; +#ifdef CONFIG_TEGRA186 + struct reset_ctl reset_ctl; + struct clk clk; +#else enum periph_id periph_id; +#endif int speed; int pinmux_config; struct i2c_control *control; @@ -62,12 +81,41 @@ static void set_packet_mode(struct i2c_bus *i2c_bus) static void i2c_reset_controller(struct i2c_bus *i2c_bus) { /* Reset I2C controller. */ +#ifdef CONFIG_TEGRA186 + reset_assert(&i2c_bus->reset_ctl); + udelay(1); + reset_deassert(&i2c_bus->reset_ctl); + udelay(1); +#else reset_periph(i2c_bus->periph_id, 1); +#endif /* re-program config register to packet mode */ set_packet_mode(i2c_bus); } +#ifdef CONFIG_TEGRA186 +static int i2c_init_clock(struct i2c_bus *i2c_bus, unsigned rate) +{ + int ret; + + ret = reset_assert(&i2c_bus->reset_ctl); + if (ret) + return ret; + ret = clk_enable(&i2c_bus->clk); + if (ret) + return ret; + ret = clk_set_rate(&i2c_bus->clk, rate); + if (IS_ERR_VALUE(ret)) + return ret; + ret = reset_deassert(&i2c_bus->reset_ctl); + if (ret) + return ret; + + return 0; +} +#endif + static void i2c_init_controller(struct i2c_bus *i2c_bus) { if (!i2c_bus->speed) @@ -78,8 +126,12 @@ static void i2c_init_controller(struct i2c_bus *i2c_bus) * here, in section 23.3.1, but in fact we seem to need a factor of * 16 to get the right frequency. */ +#ifdef CONFIG_TEGRA186 + i2c_init_clock(i2c_bus, i2c_bus->speed * 2 * 8); +#else clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH, i2c_bus->speed * 2 * 8); +#endif if (i2c_bus->type == TYPE_114) { /* @@ -94,12 +146,17 @@ static void i2c_init_controller(struct i2c_bus *i2c_bus) * is running, we hang, and we need it for the new calc. */ int clk_div_stdfst_mode = readl(&i2c_bus->regs->clk_div) >> 16; + unsigned rate = CLK_MULT_STD_FAST_MODE * + (clk_div_stdfst_mode + 1) * i2c_bus->speed * 2; debug("%s: CLK_DIV_STD_FAST_MODE setting = %d\n", __func__, clk_div_stdfst_mode); +#ifdef CONFIG_TEGRA186 + i2c_init_clock(i2c_bus, rate); +#else clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH, - CLK_MULT_STD_FAST_MODE * (clk_div_stdfst_mode + 1) * - i2c_bus->speed * 2); + rate); +#endif } /* Reset I2C controller. */ @@ -112,7 +169,9 @@ static void i2c_init_controller(struct i2c_bus *i2c_bus) setbits_le32(&dvc->ctrl3, DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK); } +#ifndef CONFIG_TEGRA186 funcmux_select(i2c_bus->periph_id, i2c_bus->pinmux_config); +#endif } static void send_packet_headers( @@ -333,8 +392,12 @@ static int tegra_i2c_set_bus_speed(struct udevice *dev, unsigned int speed) static int tegra_i2c_probe(struct udevice *dev) { struct i2c_bus *i2c_bus = dev_get_priv(dev); +#ifdef CONFIG_TEGRA186 + int ret; +#else const void *blob = gd->fdt_blob; int node = dev->of_offset; +#endif bool is_dvc; i2c_bus->id = dev->seq; @@ -345,6 +408,18 @@ static int tegra_i2c_probe(struct udevice *dev) * We don't have a binding for pinmux yet. Leave it out for now. So * far no one needs anything other than the default. */ +#ifdef CONFIG_TEGRA186 + ret = reset_get_by_name(dev, "i2c", &i2c_bus->reset_ctl); + if (ret) { + error("reset_get_by_name() failed: %d\n", ret); + return ret; + } + ret = clk_get_by_name(dev, "i2c", &i2c_bus->clk); + if (ret) { + error("clk_get_by_name() failed: %d\n", ret); + return ret; + } +#else i2c_bus->pinmux_config = FUNCMUX_DEFAULT; i2c_bus->periph_id = clock_decode_periph_id(blob, node); @@ -359,6 +434,7 @@ static int tegra_i2c_probe(struct udevice *dev) */ if (i2c_bus->periph_id == -1) return -EINVAL; +#endif is_dvc = dev_get_driver_data(dev) == TYPE_DVC; if (is_dvc) { @@ -370,7 +446,12 @@ static int tegra_i2c_probe(struct udevice *dev) i2c_init_controller(i2c_bus); debug("%s: controller bus %d at %p, periph_id %d, speed %d: ", is_dvc ? "dvc" : "i2c", dev->seq, i2c_bus->regs, - i2c_bus->periph_id, i2c_bus->speed); +#ifndef CONFIG_TEGRA186 + i2c_bus->periph_id, +#else + -1, +#endif + i2c_bus->speed); return 0; } diff --git a/drivers/mailbox/tegra-hsp.c b/drivers/mailbox/tegra-hsp.c index 5c781a50b6a..3d0362d5874 100644 --- a/drivers/mailbox/tegra-hsp.c +++ b/drivers/mailbox/tegra-hsp.c @@ -8,7 +8,19 @@ #include <asm/io.h> #include <dm.h> #include <mailbox-uclass.h> -#include <dt-bindings/mailbox/tegra-hsp.h> +#include <dt-bindings/mailbox/tegra186-hsp.h> + +#define TEGRA_HSP_INT_DIMENSIONING 0x380 +#define TEGRA_HSP_INT_DIMENSIONING_NSI_SHIFT 16 +#define TEGRA_HSP_INT_DIMENSIONING_NSI_MASK 0xf +#define TEGRA_HSP_INT_DIMENSIONING_NDB_SHIFT 12 +#define TEGRA_HSP_INT_DIMENSIONING_NDB_MASK 0xf +#define TEGRA_HSP_INT_DIMENSIONING_NAS_SHIFT 8 +#define TEGRA_HSP_INT_DIMENSIONING_NAS_MASK 0xf +#define TEGRA_HSP_INT_DIMENSIONING_NSS_SHIFT 4 +#define TEGRA_HSP_INT_DIMENSIONING_NSS_MASK 0xf +#define TEGRA_HSP_INT_DIMENSIONING_NSM_SHIFT 0 +#define TEGRA_HSP_INT_DIMENSIONING_NSM_MASK 0xf #define TEGRA_HSP_DB_REG_TRIGGER 0x0 #define TEGRA_HSP_DB_REG_ENABLE 0x4 @@ -51,7 +63,7 @@ static void tegra_hsp_writel(struct tegra_hsp *thsp, uint32_t val, static int tegra_hsp_db_id(ulong chan_id) { switch (chan_id) { - case TEGRA_HSP_MASTER_BPMP: + case (HSP_MBOX_TYPE_DB << 16) | HSP_DB_MASTER_BPMP: return TEGRA_HSP_DB_ID_BPMP; default: debug("Invalid channel ID\n"); @@ -59,6 +71,21 @@ static int tegra_hsp_db_id(ulong chan_id) } } +static int tegra_hsp_of_xlate(struct mbox_chan *chan, + struct fdtdec_phandle_args *args) +{ + debug("%s(chan=%p)\n", __func__, chan); + + if (args->args_count != 2) { + debug("Invaild args_count: %d\n", args->args_count); + return -EINVAL; + } + + chan->id = (args->args[0] << 16) | args->args[1]; + + return 0; +} + static int tegra_hsp_request(struct mbox_chan *chan) { int db_id; @@ -121,6 +148,7 @@ static int tegra_hsp_bind(struct udevice *dev) static int tegra_hsp_probe(struct udevice *dev) { struct tegra_hsp *thsp = dev_get_priv(dev); + u32 val; int nr_sm, nr_ss, nr_as; debug("%s(dev=%p)\n", __func__, dev); @@ -129,12 +157,14 @@ static int tegra_hsp_probe(struct udevice *dev) if (thsp->regs == FDT_ADDR_T_NONE) return -ENODEV; - nr_sm = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "nvidia,num-SM", - 0); - nr_ss = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "nvidia,num-SS", - 0); - nr_as = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "nvidia,num-AS", - 0); + val = readl(thsp->regs + TEGRA_HSP_INT_DIMENSIONING); + nr_sm = (val >> TEGRA_HSP_INT_DIMENSIONING_NSM_SHIFT) & + TEGRA_HSP_INT_DIMENSIONING_NSM_MASK; + nr_ss = (val >> TEGRA_HSP_INT_DIMENSIONING_NSS_SHIFT) & + TEGRA_HSP_INT_DIMENSIONING_NSS_MASK; + nr_as = (val >> TEGRA_HSP_INT_DIMENSIONING_NAS_SHIFT) & + TEGRA_HSP_INT_DIMENSIONING_NAS_MASK; + thsp->db_base = (1 + (nr_sm >> 1) + nr_ss + nr_as) << 16; return 0; @@ -146,6 +176,7 @@ static const struct udevice_id tegra_hsp_ids[] = { }; struct mbox_ops tegra_hsp_mbox_ops = { + .of_xlate = tegra_hsp_of_xlate, .request = tegra_hsp_request, .free = tegra_hsp_free, .send = tegra_hsp_send, diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 2373037685c..89904898355 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -90,6 +90,14 @@ config MXC_OCOTP Programmable memory pages that are stored on the some Freescale i.MX processors. +config NUVOTON_NCT6102D + bool "Enable Nuvoton NCT6102D Super I/O driver" + help + If you say Y here, you will get support for the Nuvoton + NCT6102D Super I/O driver. This can be used to enable or + disable the legacy UART, the watchdog or other devices + in the Nuvoton Super IO chips on X86 platforms. + config PWRSEQ bool "Enable power-sequencing drivers" depends on DM @@ -121,14 +129,17 @@ config PCA9551_I2C_ADDR help The I2C address of the PCA9551 LED controller. -config SYSRESET - bool "Enable support for system reset drivers" - depends on DM +config TEGRA186_BPMP + bool "Enable support for the Tegra186 BPMP driver" + depends on TEGRA186 help - Enable system reset drivers which can be used to reset the CPU or - board. Each driver can provide a reset method which will be called - to effect a reset. The uclass will try all available drivers when - reset_walk() is called. + The Tegra BPMP (Boot and Power Management Processor) is a separate + auxiliary CPU embedded into Tegra to perform power management work, + and controls related features such as clocks, resets, power domains, + PMIC I2C bus, etc. This driver provides the core low-level + communication path by which feature-specific drivers (such as clock) + can make requests to the BPMP. This driver is similar to an MFD + driver in the Linux kernel. config WINBOND_W83627 bool "Enable Winbond Super I/O driver" @@ -144,4 +155,9 @@ config QFW Hidden option to enable QEMU fw_cfg interface. This will be selected by either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE. +config I2C_EEPROM + bool "Enable driver for generic I2C-attached EEPROMs" + depends on MISC + help + Enable a generic driver for EEPROMs attached via I2C. endmenu diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 066639ba1f1..c0e5f03f8cb 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -24,23 +24,30 @@ obj-$(CONFIG_I2C_EEPROM) += i2c_eeprom.o obj-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o obj-$(CONFIG_MXC_OCOTP) += mxc_ocotp.o obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o +obj-$(CONFIG_NUVOTON_NCT6102D) += nuvoton_nct6102d.o obj-$(CONFIG_NS87308) += ns87308.o obj-$(CONFIG_PDSP188x) += pdsp188x.o obj-$(CONFIG_$(SPL_)PWRSEQ) += pwrseq-uclass.o -obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o ifdef CONFIG_DM_I2C +ifndef CONFIG_SPL_BUILD obj-$(CONFIG_SANDBOX) += i2c_eeprom_emul.o endif +endif obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o obj-$(CONFIG_SMSC_SIO1007) += smsc_sio1007.o obj-$(CONFIG_STATUS_LED) += status_led.o obj-$(CONFIG_SANDBOX) += swap_case.o +ifdef CONFIG_SPL_OF_PLATDATA +ifdef CONFIG_SPL_BUILD +obj-$(CONFIG_SANDBOX) += spltest_sandbox.o +endif +endif obj-$(CONFIG_SANDBOX) += syscon_sandbox.o +obj-$(CONFIG_TEGRA186_BPMP) += tegra186_bpmp.o obj-$(CONFIG_TWL4030_LED) += twl4030_led.o obj-$(CONFIG_FSL_IFC) += fsl_ifc.o obj-$(CONFIG_FSL_SEC_MON) += fsl_sec_mon.o obj-$(CONFIG_PCA9551_LED) += pca9551_led.o -obj-$(CONFIG_SYSRESET) += sysreset-uclass.o obj-$(CONFIG_FSL_DEVICE_DISABLE) += fsl_devdis.o obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o obj-$(CONFIG_QFW) += qfw.o diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c index e3229efed0b..aea8d61f347 100644 --- a/drivers/misc/cros_ec.c +++ b/drivers/misc/cros_ec.c @@ -26,7 +26,6 @@ #include <asm/io.h> #include <asm-generic/gpio.h> #include <dm/device-internal.h> -#include <dm/root.h> #include <dm/uclass-internal.h> #ifdef DEBUG_TRACE @@ -1450,12 +1449,6 @@ static int do_cros_ec(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return ret; } -int cros_ec_post_bind(struct udevice *dev) -{ - /* Scan for available EC devices (e.g. I2C tunnel) */ - return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false); -} - U_BOOT_CMD( crosec, 6, 1, do_cros_ec, "CROS-EC utility command", @@ -1482,5 +1475,5 @@ UCLASS_DRIVER(cros_ec) = { .id = UCLASS_CROS_EC, .name = "cros_ec", .per_device_auto_alloc_size = sizeof(struct cros_ec_dev), - .post_bind = cros_ec_post_bind, + .post_bind = dm_scan_fdt_dev, }; diff --git a/drivers/misc/cros_ec_sandbox.c b/drivers/misc/cros_ec_sandbox.c index 98f19a68bf6..c4fbca0d3ae 100644 --- a/drivers/misc/cros_ec_sandbox.c +++ b/drivers/misc/cros_ec_sandbox.c @@ -517,6 +517,7 @@ int cros_ec_probe(struct udevice *dev) struct ec_state *ec = dev->priv; struct cros_ec_dev *cdev = dev->uclass_priv; const void *blob = gd->fdt_blob; + struct udevice *keyb_dev; int node; int err; @@ -525,7 +526,15 @@ int cros_ec_probe(struct udevice *dev) if (err) return err; - node = fdtdec_next_compatible(blob, 0, COMPAT_GOOGLE_CROS_EC_KEYB); + node = -1; + for (device_find_first_child(dev, &keyb_dev); + keyb_dev; + device_find_next_child(&keyb_dev)) { + if (device_get_uclass_id(keyb_dev) == UCLASS_KEYBOARD) { + node = keyb_dev->of_offset; + break; + } + } if (node < 0) { debug("%s: No cros_ec keyboard found\n", __func__); } else if (keyscan_read_fdt_matrix(ec, blob, node)) { diff --git a/drivers/misc/i2c_eeprom.c b/drivers/misc/i2c_eeprom.c index 814134a2cb1..c9f4174bad4 100644 --- a/drivers/misc/i2c_eeprom.c +++ b/drivers/misc/i2c_eeprom.c @@ -13,7 +13,7 @@ static int i2c_eeprom_read(struct udevice *dev, int offset, uint8_t *buf, int size) { - return -ENODEV; + return dm_i2c_read(dev, offset, buf, size); } static int i2c_eeprom_write(struct udevice *dev, int offset, @@ -27,23 +27,46 @@ struct i2c_eeprom_ops i2c_eeprom_std_ops = { .write = i2c_eeprom_write, }; +static int i2c_eeprom_std_ofdata_to_platdata(struct udevice *dev) +{ + struct i2c_eeprom *priv = dev_get_priv(dev); + u64 data = dev_get_driver_data(dev); + + /* 6 bit -> page size of up to 2^63 (should be sufficient) */ + priv->pagewidth = data & 0x3F; + priv->pagesize = (1 << priv->pagewidth); + + return 0; +} + int i2c_eeprom_std_probe(struct udevice *dev) { return 0; } static const struct udevice_id i2c_eeprom_std_ids[] = { - { .compatible = "i2c-eeprom" }, + { .compatible = "i2c-eeprom", .data = 0 }, + { .compatible = "atmel,24c01a", .data = 3 }, + { .compatible = "atmel,24c02", .data = 3 }, + { .compatible = "atmel,24c04", .data = 4 }, + { .compatible = "atmel,24c08a", .data = 4 }, + { .compatible = "atmel,24c16a", .data = 4 }, + { .compatible = "atmel,24c32", .data = 5 }, + { .compatible = "atmel,24c64", .data = 5 }, + { .compatible = "atmel,24c128", .data = 6 }, + { .compatible = "atmel,24c256", .data = 6 }, + { .compatible = "atmel,24c512", .data = 6 }, { } }; U_BOOT_DRIVER(i2c_eeprom_std) = { - .name = "i2c_eeprom", - .id = UCLASS_I2C_EEPROM, - .of_match = i2c_eeprom_std_ids, - .probe = i2c_eeprom_std_probe, - .priv_auto_alloc_size = sizeof(struct i2c_eeprom), - .ops = &i2c_eeprom_std_ops, + .name = "i2c_eeprom", + .id = UCLASS_I2C_EEPROM, + .of_match = i2c_eeprom_std_ids, + .probe = i2c_eeprom_std_probe, + .ofdata_to_platdata = i2c_eeprom_std_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct i2c_eeprom), + .ops = &i2c_eeprom_std_ops, }; UCLASS_DRIVER(i2c_eeprom) = { diff --git a/drivers/misc/misc-uclass.c b/drivers/misc/misc-uclass.c index 13a6ea508b1..d9eea3dac5c 100644 --- a/drivers/misc/misc-uclass.c +++ b/drivers/misc/misc-uclass.c @@ -45,6 +45,17 @@ int misc_ioctl(struct udevice *dev, unsigned long request, void *buf) return ops->ioctl(dev, request, buf); } +int misc_call(struct udevice *dev, int msgid, void *tx_msg, int tx_size, + void *rx_msg, int rx_size) +{ + const struct misc_ops *ops = device_get_ops(dev); + + if (!ops->call) + return -ENOSYS; + + return ops->call(dev, msgid, tx_msg, tx_size, rx_msg, rx_size); +} + UCLASS_DRIVER(misc) = { .id = UCLASS_MISC, .name = "misc", diff --git a/drivers/misc/nuvoton_nct6102d.c b/drivers/misc/nuvoton_nct6102d.c new file mode 100644 index 00000000000..ced70f178b3 --- /dev/null +++ b/drivers/misc/nuvoton_nct6102d.c @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2016 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <nuvoton_nct6102d.h> +#include <asm/io.h> +#include <asm/pnp_def.h> + +static void superio_outb(int reg, int val) +{ + outb(reg, NCT_EFER); + outb(val, NCT_EFDR); +} + +static inline int superio_inb(int reg) +{ + outb(reg, NCT_EFER); + return inb(NCT_EFDR); +} + +static int superio_enter(void) +{ + outb(NCT_ENTRY_KEY, NCT_EFER); /* Enter extended function mode */ + outb(NCT_ENTRY_KEY, NCT_EFER); /* Again according to manual */ + + return 0; +} + +static void superio_select(int ld) +{ + superio_outb(NCT_LD_SELECT_REG, ld); +} + +static void superio_exit(void) +{ + outb(NCT_EXIT_KEY, NCT_EFER); /* Leave extended function mode */ +} + +/* + * The Nuvoton NCT6102D starts per default after reset with both, + * the internal watchdog and the internal legacy UART enabled. This + * code provides a function to disable the watchdog. + */ +int nct6102d_wdt_disable(void) +{ + superio_enter(); + /* Select logical device for WDT */ + superio_select(NCT6102D_LD_WDT); + superio_outb(NCT6102D_WDT_TIMEOUT, 0x00); + superio_exit(); + + return 0; +} diff --git a/drivers/misc/spltest_sandbox.c b/drivers/misc/spltest_sandbox.c new file mode 100644 index 00000000000..1fef8252ab8 --- /dev/null +++ b/drivers/misc/spltest_sandbox.c @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2016 Google, Inc + * Written by Simon Glass <sjg@chromium.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <dt-structs.h> + +DECLARE_GLOBAL_DATA_PTR; + +static int sandbox_spl_probe(struct udevice *dev) +{ + struct dtd_sandbox_spl_test *plat = dev_get_platdata(dev); + int i; + + printf("of-platdata probe:\n"); + printf("bool %d\n", plat->boolval); + + printf("byte %02x\n", plat->byteval); + printf("bytearray"); + for (i = 0; i < sizeof(plat->bytearray); i++) + printf(" %02x", plat->bytearray[i]); + printf("\n"); + + printf("int %d\n", plat->intval); + printf("intarray"); + for (i = 0; i < ARRAY_SIZE(plat->intarray); i++) + printf(" %d", plat->intarray[i]); + printf("\n"); + + printf("longbytearray"); + for (i = 0; i < sizeof(plat->longbytearray); i++) + printf(" %02x", plat->longbytearray[i]); + printf("\n"); + + printf("string %s\n", plat->stringval); + printf("stringarray"); + for (i = 0; i < ARRAY_SIZE(plat->stringarray); i++) + printf(" \"%s\"", plat->stringarray[i]); + printf("\n"); + + return 0; +} + +U_BOOT_DRIVER(sandbox_spl_test) = { + .name = "sandbox_spl_test", + .id = UCLASS_MISC, + .flags = DM_FLAG_PRE_RELOC, + .probe = sandbox_spl_probe, +}; diff --git a/drivers/misc/tegra186_bpmp.c b/drivers/misc/tegra186_bpmp.c new file mode 100644 index 00000000000..f4ddbea3760 --- /dev/null +++ b/drivers/misc/tegra186_bpmp.c @@ -0,0 +1,257 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <dm.h> +#include <dm/lists.h> +#include <dm/root.h> +#include <mailbox.h> +#include <misc.h> +#include <asm/arch-tegra/bpmp_abi.h> +#include <asm/arch-tegra/ivc.h> + +#define BPMP_IVC_FRAME_COUNT 1 +#define BPMP_IVC_FRAME_SIZE 128 + +#define BPMP_FLAG_DO_ACK BIT(0) +#define BPMP_FLAG_RING_DOORBELL BIT(1) + +DECLARE_GLOBAL_DATA_PTR; + +struct tegra186_bpmp { + struct mbox_chan mbox; + struct tegra_ivc ivc; +}; + +static int tegra186_bpmp_call(struct udevice *dev, int mrq, void *tx_msg, + int tx_size, void *rx_msg, int rx_size) +{ + struct tegra186_bpmp *priv = dev_get_priv(dev); + int ret, err; + void *ivc_frame; + struct mrq_request *req; + struct mrq_response *resp; + ulong start_time; + + debug("%s(dev=%p, mrq=%u, tx_msg=%p, tx_size=%d, rx_msg=%p, rx_size=%d) (priv=%p)\n", + __func__, dev, mrq, tx_msg, tx_size, rx_msg, rx_size, priv); + + if ((tx_size > BPMP_IVC_FRAME_SIZE) || (rx_size > BPMP_IVC_FRAME_SIZE)) + return -EINVAL; + + ret = tegra_ivc_write_get_next_frame(&priv->ivc, &ivc_frame); + if (ret) { + error("tegra_ivc_write_get_next_frame() failed: %d\n", ret); + return ret; + } + + req = ivc_frame; + req->mrq = mrq; + req->flags = BPMP_FLAG_DO_ACK | BPMP_FLAG_RING_DOORBELL; + memcpy(req + 1, tx_msg, tx_size); + + ret = tegra_ivc_write_advance(&priv->ivc); + if (ret) { + error("tegra_ivc_write_advance() failed: %d\n", ret); + return ret; + } + + start_time = timer_get_us(); + for (;;) { + ret = tegra_ivc_channel_notified(&priv->ivc); + if (ret) { + error("tegra_ivc_channel_notified() failed: %d\n", ret); + return ret; + } + + ret = tegra_ivc_read_get_next_frame(&priv->ivc, &ivc_frame); + if (!ret) + break; + + /* Timeout 20ms; roughly 10x current max observed duration */ + if ((timer_get_us() - start_time) > 20 * 1000) { + error("tegra_ivc_read_get_next_frame() timed out (%d)\n", + ret); + return -ETIMEDOUT; + } + } + + resp = ivc_frame; + err = resp->err; + if (!err && rx_msg && rx_size) + memcpy(rx_msg, resp + 1, rx_size); + + ret = tegra_ivc_read_advance(&priv->ivc); + if (ret) { + error("tegra_ivc_write_advance() failed: %d\n", ret); + return ret; + } + + if (err) { + error("BPMP responded with error %d\n", err); + /* err isn't a U-Boot error code, so don't that */ + return -EIO; + } + + return rx_size; +} + +/** + * The BPMP exposes multiple different services. We create a sub-device for + * each separate type of service, since each device must be of the appropriate + * UCLASS. + */ +static int tegra186_bpmp_bind(struct udevice *dev) +{ + int ret; + struct udevice *child; + + debug("%s(dev=%p)\n", __func__, dev); + + ret = device_bind_driver_to_node(dev, "tegra186_clk", "tegra186_clk", + dev->of_offset, &child); + if (ret) + return ret; + + ret = device_bind_driver_to_node(dev, "tegra186_reset", + "tegra186_reset", dev->of_offset, + &child); + if (ret) + return ret; + + ret = device_bind_driver_to_node(dev, "tegra186_power_domain", + "tegra186_power_domain", + dev->of_offset, &child); + if (ret) + return ret; + + ret = dm_scan_fdt_dev(dev); + if (ret) + return ret; + + return 0; +} + +static ulong tegra186_bpmp_get_shmem(struct udevice *dev, int index) +{ + int ret; + struct fdtdec_phandle_args args; + fdt_addr_t reg; + + ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev->of_offset, + "shmem", NULL, 0, index, &args); + if (ret < 0) { + error("fdtdec_parse_phandle_with_args() failed: %d\n", ret); + return ret; + } + + reg = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, args.node, + "reg", 0, NULL, true); + if (reg == FDT_ADDR_T_NONE) { + error("fdtdec_get_addr_size_auto_noparent() failed\n"); + return -ENODEV; + } + + return reg; +} + +static void tegra186_bpmp_ivc_notify(struct tegra_ivc *ivc) +{ + struct tegra186_bpmp *priv = + container_of(ivc, struct tegra186_bpmp, ivc); + int ret; + + ret = mbox_send(&priv->mbox, NULL); + if (ret) + error("mbox_send() failed: %d\n", ret); +} + +static int tegra186_bpmp_probe(struct udevice *dev) +{ + struct tegra186_bpmp *priv = dev_get_priv(dev); + int ret; + ulong tx_base, rx_base, start_time; + + debug("%s(dev=%p) (priv=%p)\n", __func__, dev, priv); + + ret = mbox_get_by_index(dev, 0, &priv->mbox); + if (ret) { + error("mbox_get_by_index() failed: %d\n", ret); + return ret; + } + + tx_base = tegra186_bpmp_get_shmem(dev, 0); + if (IS_ERR_VALUE(tx_base)) { + error("tegra186_bpmp_get_shmem failed for tx_base\n"); + return tx_base; + } + rx_base = tegra186_bpmp_get_shmem(dev, 1); + if (IS_ERR_VALUE(rx_base)) { + error("tegra186_bpmp_get_shmem failed for rx_base\n"); + return rx_base; + } + debug("shmem: rx=%lx, tx=%lx\n", rx_base, tx_base); + + ret = tegra_ivc_init(&priv->ivc, rx_base, tx_base, BPMP_IVC_FRAME_COUNT, + BPMP_IVC_FRAME_SIZE, tegra186_bpmp_ivc_notify); + if (ret) { + error("tegra_ivc_init() failed: %d\n", ret); + return ret; + } + + tegra_ivc_channel_reset(&priv->ivc); + start_time = timer_get_us(); + for (;;) { + ret = tegra_ivc_channel_notified(&priv->ivc); + if (!ret) + break; + + /* Timeout 100ms */ + if ((timer_get_us() - start_time) > 100 * 1000) { + error("Initial IVC reset timed out (%d)\n", ret); + ret = -ETIMEDOUT; + goto err_free_mbox; + } + } + + return 0; + +err_free_mbox: + mbox_free(&priv->mbox); + + return ret; +} + +static int tegra186_bpmp_remove(struct udevice *dev) +{ + struct tegra186_bpmp *priv = dev_get_priv(dev); + + debug("%s(dev=%p) (priv=%p)\n", __func__, dev, priv); + + mbox_free(&priv->mbox); + + return 0; +} + +static struct misc_ops tegra186_bpmp_ops = { + .call = tegra186_bpmp_call, +}; + +static const struct udevice_id tegra186_bpmp_ids[] = { + { .compatible = "nvidia,tegra186-bpmp" }, + { } +}; + +U_BOOT_DRIVER(tegra186_bpmp) = { + .name = "tegra186_bpmp", + .id = UCLASS_MISC, + .of_match = tegra186_bpmp_ids, + .bind = tegra186_bpmp_bind, + .probe = tegra186_bpmp_probe, + .remove = tegra186_bpmp_remove, + .ops = &tegra186_bpmp_ops, + .priv_auto_alloc_size = sizeof(struct tegra186_bpmp), +}; diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index c80efc39a79..3616deedf37 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -10,21 +10,40 @@ config DM_MMC bool "Enable MMC controllers using Driver Model" depends on DM help - This enables the MultiMediaCard (MMC) uclass which suports MMC and + This enables the MultiMediaCard (MMC) uclass which supports MMC and Secure Digital I/O (SDIO) cards. Both removable (SD, micro-SD, etc.) and non-removable (e.g. eMMC chip) devices are supported. These appear as block devices in U-Boot and can support filesystems such as EXT4 and FAT. +config DM_MMC_OPS + bool "Support MMC controller operations using Driver Model" + depends on DM_MMC + help + Driver model provides a means of supporting device operations. This + option moves MMC operations under the control of driver model. The + option will be removed as soon as all DM_MMC drivers use it, as it + will the only supported behaviour. + config MSM_SDHCI bool "Qualcomm SDHCI controller" - depends on DM_MMC + depends on DM_MMC && BLK && DM_MMC_OPS help Enables support for SDHCI 2.0 controller present on some Qualcomm Snapdragon devices. This device is compatible with eMMC v4.5 and SD 3.0 specifications. Both SD and eMMC devices are supported. Card-detect gpios are not supported. +config ATMEL_SDHCI + bool "Atmel SDHCI controller support" + depends on DM_MMC && BLK && DM_MMC_OPS && ARCH_AT91 + help + This enables support for the Atmel SDHCI controller, which supports + the embedded MultiMedia Card (e.MMC) Specification V4.51, the SD + Memory Card Specification V3.0, and the SDIO V3.0 specification. + It is compliant with the SD Host Controller Standard V3.0 + specification. + config ROCKCHIP_DWMMC bool "Rockchip SD/MMC controller support" depends on DM_MMC && OF_CONTROL @@ -52,6 +71,12 @@ config ZYNQ_SDHCI help Support for Arasan SDHCI host controller on Zynq/ZynqMP ARM SoCs platform +config ROCKCHIP_SDHCI + bool "Arasan SDHCI controller for Rockchip support" + depends on DM_MMC && BLK && DM_MMC_OPS + help + Support for Arasan SDHCI host controller on Rockchip ARM SoCs platform + config MMC_UNIPHIER bool "UniPhier SD/MMC Host Controller support" depends on ARCH_UNIPHIER diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 3da4817a189..18351fb48a8 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -25,6 +25,9 @@ obj-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o obj-$(CONFIG_FTSDC010) += ftsdc010_mci.o obj-$(CONFIG_FTSDC021) += ftsdc021_sdhci.o obj-$(CONFIG_GENERIC_MMC) += mmc.o +ifdef CONFIG_SUPPORT_EMMC_BOOT +obj-$(CONFIG_GENERIC_MMC) += mmc_boot.o +endif obj-$(CONFIG_GENERIC_ATMEL_MCI) += gen_atmel_mci.o obj-$(CONFIG_KONA_SDHCI) += kona_sdhci.o obj-$(CONFIG_MMC_SPI) += mmc_spi.o @@ -53,6 +56,7 @@ obj-$(CONFIG_SPEAR_SDHCI) += spear_sdhci.o obj-$(CONFIG_TEGRA_MMC) += tegra_mmc.o obj-$(CONFIG_MMC_UNIPHIER) += uniphier-sd.o obj-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o +obj-$(CONFIG_ROCKCHIP_SDHCI) += rockchip_sdhci.o ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o diff --git a/drivers/mmc/arm_pl180_mmci.c b/drivers/mmc/arm_pl180_mmci.c index 8f2694f14c0..e64ac3c9939 100644 --- a/drivers/mmc/arm_pl180_mmci.c +++ b/drivers/mmc/arm_pl180_mmci.c @@ -37,7 +37,7 @@ static int wait_for_command_end(struct mmc *dev, struct mmc_cmd *cmd) writel(statusmask, &host->base->status_clear); if (hoststatus & SDI_STA_CTIMEOUT) { debug("CMD%d time out\n", cmd->cmdidx); - return TIMEOUT; + return -ETIMEDOUT; } else if ((hoststatus & SDI_STA_CCRCFAIL) && (cmd->resp_type & MMC_RSP_CRC)) { printf("CMD%d CRC error\n", cmd->cmdidx); diff --git a/drivers/mmc/atmel_sdhci.c b/drivers/mmc/atmel_sdhci.c index 24b68b640bb..dd6bd33515c 100644 --- a/drivers/mmc/atmel_sdhci.c +++ b/drivers/mmc/atmel_sdhci.c @@ -6,12 +6,15 @@ */ #include <common.h> +#include <clk.h> +#include <dm.h> #include <malloc.h> #include <sdhci.h> #include <asm/arch/clk.h> #define ATMEL_SDHC_MIN_FREQ 400000 +#ifndef CONFIG_DM_MMC int atmel_sdhci_init(void *regbase, u32 id) { struct sdhci_host *host; @@ -38,3 +41,123 @@ int atmel_sdhci_init(void *regbase, u32 id) return 0; } + +#else + +DECLARE_GLOBAL_DATA_PTR; + +struct atmel_sdhci_plat { + struct mmc_config cfg; + struct mmc mmc; +}; + +static int atmel_sdhci_get_clk(struct udevice *dev, int index, struct clk *clk) +{ + struct udevice *dev_clk; + int periph, ret; + + ret = clk_get_by_index(dev, index, clk); + if (ret) + return ret; + + periph = fdtdec_get_uint(gd->fdt_blob, clk->dev->of_offset, "reg", -1); + if (periph < 0) + return -EINVAL; + + dev_clk = dev_get_parent(clk->dev); + ret = clk_request(dev_clk, clk); + if (ret) + return ret; + + clk->id = periph; + + return 0; +} + +static int atmel_sdhci_probe(struct udevice *dev) +{ + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct atmel_sdhci_plat *plat = dev_get_platdata(dev); + struct sdhci_host *host = dev_get_priv(dev); + u32 max_clk; + u32 caps, caps_1; + u32 clk_base, clk_mul; + ulong gck_rate; + struct clk clk; + int ret; + + ret = atmel_sdhci_get_clk(dev, 0, &clk); + if (ret) + return ret; + + ret = clk_enable(&clk); + if (ret) + return ret; + + host->name = dev->name; + host->ioaddr = (void *)dev_get_addr(dev); + + host->quirks = 0; + host->bus_width = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "bus-width", 4); + + caps = sdhci_readl(host, SDHCI_CAPABILITIES); + clk_base = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; + caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); + clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT; + gck_rate = clk_base * 1000000 * (clk_mul + 1); + + ret = atmel_sdhci_get_clk(dev, 1, &clk); + if (ret) + return ret; + + ret = clk_set_rate(&clk, gck_rate); + if (ret) + return ret; + + max_clk = clk_get_rate(&clk); + if (!max_clk) + return -EINVAL; + + ret = sdhci_setup_cfg(&plat->cfg, host, max_clk, ATMEL_SDHC_MIN_FREQ); + if (ret) + return ret; + + host->mmc = &plat->mmc; + host->mmc->dev = dev; + host->mmc->priv = host; + upriv->mmc = host->mmc; + + clk_free(&clk); + + return sdhci_probe(dev); +} + +static int atmel_sdhci_bind(struct udevice *dev) +{ + struct atmel_sdhci_plat *plat = dev_get_platdata(dev); + int ret; + + ret = sdhci_bind(dev, &plat->mmc, &plat->cfg); + if (ret) + return ret; + + return 0; +} + +static const struct udevice_id atmel_sdhci_ids[] = { + { .compatible = "atmel,sama5d2-sdhci" }, + { } +}; + +U_BOOT_DRIVER(atmel_sdhci_drv) = { + .name = "atmel_sdhci", + .id = UCLASS_MMC, + .of_match = atmel_sdhci_ids, + .ops = &sdhci_ops, + .bind = atmel_sdhci_bind, + .probe = atmel_sdhci_probe, + .priv_auto_alloc_size = sizeof(struct sdhci_host), + .platdata_auto_alloc_size = sizeof(struct atmel_sdhci_plat), +}; +#endif diff --git a/drivers/mmc/bfin_sdh.c b/drivers/mmc/bfin_sdh.c index 9bdfbbca011..0e493dae0ec 100644 --- a/drivers/mmc/bfin_sdh.c +++ b/drivers/mmc/bfin_sdh.c @@ -109,9 +109,9 @@ sdh_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd) } if (status & CMD_TIME_OUT) - ret = TIMEOUT; + ret = -ETIMEDOUT; else if (status & CMD_CRC_FAIL && flags & MMC_RSP_CRC) - ret = COMM_ERR; + ret = -ECOMM; else ret = 0; @@ -136,7 +136,7 @@ static int sdh_setup_data(struct mmc *mmc, struct mmc_data *data) /* Don't support write yet. */ if (data->flags & MMC_DATA_WRITE) - return UNUSABLE_ERR; + return -EOPNOTSUPP; #ifndef RSI_BLKSZ data_ctl |= ((ffs(data->blocksize) - 1) << 4); #else @@ -194,10 +194,10 @@ static int bfin_sdh_request(struct mmc *mmc, struct mmc_cmd *cmd, if (status & DAT_TIME_OUT) { bfin_write_SDH_STATUS_CLR(DAT_TIMEOUT_STAT); - ret |= TIMEOUT; + ret = -ETIMEDOUT; } else if (status & (DAT_CRC_FAIL | RX_OVERRUN)) { bfin_write_SDH_STATUS_CLR(DAT_CRC_FAIL_STAT | RX_OVERRUN_STAT); - ret |= COMM_ERR; + ret = -ECOMM; } else bfin_write_SDH_STATUS_CLR(DAT_BLK_END_STAT | DAT_END_STAT); diff --git a/drivers/mmc/davinci_mmc.c b/drivers/mmc/davinci_mmc.c index aae00e9dab3..b495c7564cb 100644 --- a/drivers/mmc/davinci_mmc.c +++ b/drivers/mmc/davinci_mmc.c @@ -9,6 +9,7 @@ #include <config.h> #include <common.h> #include <command.h> +#include <errno.h> #include <mmc.h> #include <part.h> #include <malloc.h> @@ -66,7 +67,7 @@ dmmc_wait_fifo_status(volatile struct davinci_mmc_regs *regs, uint status) udelay(100); if (wdog == 0) - return COMM_ERR; + return -ECOMM; return 0; } @@ -80,7 +81,7 @@ static int dmmc_busy_wait(volatile struct davinci_mmc_regs *regs) udelay(10); if (wdog == 0) - return COMM_ERR; + return -ECOMM; return 0; } @@ -99,7 +100,7 @@ static int dmmc_check_status(volatile struct davinci_mmc_regs *regs, return 0; } else if (mmcstatus & st_error) { if (mmcstatus & MMCST0_TOUTRS) - return TIMEOUT; + return -ETIMEDOUT; printf("[ ST0 ERROR %x]\n", mmcstatus); /* * Ignore CRC errors as some MMC cards fail to @@ -107,7 +108,7 @@ static int dmmc_check_status(volatile struct davinci_mmc_regs *regs, */ if (mmcstatus & MMCST0_CRCRS) return 0; - return COMM_ERR; + return -ECOMM; } udelay(10); @@ -116,7 +117,7 @@ static int dmmc_check_status(volatile struct davinci_mmc_regs *regs, printf("Status %x Timeout ST0:%x ST1:%x\n", st_ready, mmcstatus, get_val(®s->mmcst1)); - return COMM_ERR; + return -ECOMM; } /* diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c index af6e04aa28b..afc674dd143 100644 --- a/drivers/mmc/dw_mmc.c +++ b/drivers/mmc/dw_mmc.c @@ -13,7 +13,6 @@ #include <memalign.h> #include <mmc.h> #include <dwmmc.h> -#include <asm-generic/errno.h> #define PAGE_SIZE 4096 @@ -120,12 +119,14 @@ static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data) } if (host->fifo_mode && size) { + len = 0; if (data->flags == MMC_DATA_READ) { if ((dwmci_readl(host, DWMCI_RINTSTS) & DWMCI_INTMSK_RXDR)) { len = dwmci_readl(host, DWMCI_STATUS); len = (len >> DWMCI_FIFO_SHIFT) & DWMCI_FIFO_MASK; + len = min(size, len); for (i = 0; i < len; i++) *buf++ = dwmci_readl(host, DWMCI_DATA); @@ -139,6 +140,7 @@ static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data) len = fifo_depth - ((len >> DWMCI_FIFO_SHIFT) & DWMCI_FIFO_MASK); + len = min(size, len); for (i = 0; i < len; i++) dwmci_writel(host, DWMCI_DATA, *buf++); @@ -159,7 +161,7 @@ static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data) if (get_timer(start) > timeout) { debug("%s: Timeout waiting for data!\n", __func__); - ret = TIMEOUT; + ret = -ETIMEDOUT; break; } } @@ -181,14 +183,21 @@ static int dwmci_set_transfer_mode(struct dwmci_host *host, return mode; } +#ifdef CONFIG_DM_MMC_OPS +static int dwmci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + struct mmc *mmc = mmc_get_mmc_dev(dev); +#else static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { +#endif struct dwmci_host *host = mmc->priv; ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac, data ? DIV_ROUND_UP(data->blocks, 8) : 0); int ret = 0, flags = 0, i; - unsigned int timeout = 100000; + unsigned int timeout = 500; u32 retry = 100000; u32 mask, ctrl; ulong start = get_timer(0); @@ -197,7 +206,7 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) { if (get_timer(start) > timeout) { debug("%s: Timeout on data busy\n", __func__); - return TIMEOUT; + return -ETIMEDOUT; } } @@ -263,7 +272,7 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, if (i == retry) { debug("%s: Timeout.\n", __func__); - return TIMEOUT; + return -ETIMEDOUT; } if (mask & DWMCI_INTMSK_RTO) { @@ -276,7 +285,7 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, * CMD8, please keep that in mind. */ debug("%s: Response Timeout.\n", __func__); - return TIMEOUT; + return -ETIMEDOUT; } else if (mask & DWMCI_INTMSK_RE) { debug("%s: Response Error.\n", __func__); return -EIO; @@ -373,8 +382,14 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq) return 0; } +#ifdef CONFIG_DM_MMC_OPS +static int dwmci_set_ios(struct udevice *dev) +{ + struct mmc *mmc = mmc_get_mmc_dev(dev); +#else static void dwmci_set_ios(struct mmc *mmc) { +#endif struct dwmci_host *host = (struct dwmci_host *)mmc->priv; u32 ctype, regs; @@ -405,6 +420,9 @@ static void dwmci_set_ios(struct mmc *mmc) if (host->clksel) host->clksel(host); +#ifdef CONFIG_DM_MMC_OPS + return 0; +#endif } static int dwmci_init(struct mmc *mmc) @@ -448,17 +466,34 @@ static int dwmci_init(struct mmc *mmc) return 0; } +#ifdef CONFIG_DM_MMC_OPS +int dwmci_probe(struct udevice *dev) +{ + struct mmc *mmc = mmc_get_mmc_dev(dev); + + return dwmci_init(mmc); +} + +const struct dm_mmc_ops dm_dwmci_ops = { + .send_cmd = dwmci_send_cmd, + .set_ios = dwmci_set_ios, +}; + +#else static const struct mmc_ops dwmci_ops = { .send_cmd = dwmci_send_cmd, .set_ios = dwmci_set_ios, .init = dwmci_init, }; +#endif void dwmci_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth, uint caps, u32 max_clk, u32 min_clk) { cfg->name = name; +#ifndef CONFIG_DM_MMC_OPS cfg->ops = &dwmci_ops; +#endif cfg->f_min = min_clk; cfg->f_max = max_clk; diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index 863bbb3f64b..57271f18b0b 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -10,12 +10,12 @@ #include <fdtdec.h> #include <libfdt.h> #include <malloc.h> +#include <errno.h> #include <asm/arch/dwmmc.h> #include <asm/arch/clk.h> #include <asm/arch/pinmux.h> #include <asm/arch/power.h> #include <asm/gpio.h> -#include <asm-generic/errno.h> #define DWMMC_MAX_CH_NUM 4 #define DWMMC_MAX_FREQ 52000000 @@ -23,8 +23,21 @@ #define DWMMC_MMC0_SDR_TIMING_VAL 0x03030001 #define DWMMC_MMC2_SDR_TIMING_VAL 0x03020001 +#ifdef CONFIG_DM_MMC +#include <dm.h> +DECLARE_GLOBAL_DATA_PTR; + +struct exynos_mmc_plat { + struct mmc_config cfg; + struct mmc mmc; +}; +#endif + /* Exynos implmentation specific drver private data */ struct dwmci_exynos_priv_data { +#ifdef CONFIG_DM_MMC + struct dwmci_host host; +#endif u32 sdr_timing; }; @@ -80,11 +93,10 @@ static void exynos_dwmci_board_init(struct dwmci_host *host) exynos_dwmci_clksel(host); } -static int exynos_dwmci_core_init(struct dwmci_host *host, int index) +static int exynos_dwmci_core_init(struct dwmci_host *host) { unsigned int div; unsigned long freq, sclk; - struct dwmci_exynos_priv_data *priv = host->priv; if (host->bus_hz) freq = host->bus_hz; @@ -92,10 +104,10 @@ static int exynos_dwmci_core_init(struct dwmci_host *host, int index) freq = DWMMC_MAX_FREQ; /* request mmc clock vlaue of 52MHz. */ - sclk = get_mmc_clk(index); + sclk = get_mmc_clk(host->dev_index); div = DIV_ROUND_UP(sclk, freq); /* set the clock divisor for mmc */ - set_mmc_clk(index, div); + set_mmc_clk(host->dev_index, div); host->name = "EXYNOS DWMMC"; #ifdef CONFIG_EXYNOS5420 @@ -103,78 +115,35 @@ static int exynos_dwmci_core_init(struct dwmci_host *host, int index) #endif host->board_init = exynos_dwmci_board_init; - if (!priv->sdr_timing) { - if (index == 0) - priv->sdr_timing = DWMMC_MMC0_SDR_TIMING_VAL; - else if (index == 2) - priv->sdr_timing = DWMMC_MMC2_SDR_TIMING_VAL; - } - host->caps = MMC_MODE_DDR_52MHz; host->clksel = exynos_dwmci_clksel; - host->dev_index = index; host->get_mmc_clk = exynos_dwmci_get_clk; + +#ifndef CONFIG_DM_MMC /* Add the mmc channel to be registered with mmc core */ if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) { - printf("DWMMC%d registration failed\n", index); + printf("DWMMC%d registration failed\n", host->dev_index); return -1; } - return 0; -} - -/* - * This function adds the mmc channel to be registered with mmc core. - * index - mmc channel number. - * regbase - register base address of mmc channel specified in 'index'. - * bus_width - operating bus width of mmc channel specified in 'index'. - * clksel - value to be written into CLKSEL register in case of FDT. - * NULL in case od non-FDT. - */ -int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel) -{ - struct dwmci_host *host = NULL; - struct dwmci_exynos_priv_data *priv; - - host = malloc(sizeof(struct dwmci_host)); - if (!host) { - error("dwmci_host malloc fail!\n"); - return -ENOMEM; - } - - priv = malloc(sizeof(struct dwmci_exynos_priv_data)); - if (!priv) { - error("dwmci_exynos_priv_data malloc fail!\n"); - return -ENOMEM; - } - - host->ioaddr = (void *)regbase; - host->buswidth = bus_width; - - if (clksel) - priv->sdr_timing = clksel; - - host->priv = priv; +#endif - return exynos_dwmci_core_init(host, index); + return 0; } -#if CONFIG_IS_ENABLED(OF_CONTROL) static struct dwmci_host dwmci_host[DWMMC_MAX_CH_NUM]; static int do_dwmci_init(struct dwmci_host *host) { - int index, flag, err; - - index = host->dev_index; + int flag, err; flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE; err = exynos_pinmux_config(host->dev_id, flag); if (err) { - printf("DWMMC%d not configure\n", index); + printf("DWMMC%d not configure\n", host->dev_index); return err; } - return exynos_dwmci_core_init(host, index); + return exynos_dwmci_core_init(host); } static int exynos_dwmci_get_config(const void *blob, int node, @@ -197,13 +166,14 @@ static int exynos_dwmci_get_config(const void *blob, int node, if (host->dev_index == host->dev_id) host->dev_index = host->dev_id - PERIPH_ID_SDMMC0; - /* Get the bus width from the device node */ - host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 0); - if (host->buswidth <= 0) { - printf("DWMMC%d: Can't get bus-width\n", host->dev_index); + if (host->dev_index > 4) { + printf("DWMMC%d: Can't get the dev index\n", host->dev_index); return -EINVAL; } + /* Get the bus width from the device node (Default is 4bit buswidth) */ + host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 4); + /* Set the base address from the device node */ base = fdtdec_get_addr(blob, node, "reg"); if (!base) { @@ -265,15 +235,13 @@ static int exynos_dwmci_process_node(const void *blob, int exynos_dwmmc_init(const void *blob) { - int compat_id; int node_list[DWMMC_MAX_CH_NUM]; int boot_dev_node; int err = 0, count; - compat_id = COMPAT_SAMSUNG_EXYNOS_DWMMC; - count = fdtdec_find_aliases_for_id(blob, "mmc", - compat_id, node_list, DWMMC_MAX_CH_NUM); + COMPAT_SAMSUNG_EXYNOS_DWMMC, node_list, + DWMMC_MAX_CH_NUM); /* For DWMMC always set boot device as mmc 0 */ if (count >= 3 && get_boot_mode() == BOOT_MODE_SD) { @@ -286,4 +254,58 @@ int exynos_dwmmc_init(const void *blob) return err; } + +#ifdef CONFIG_DM_MMC +static int exynos_dwmmc_probe(struct udevice *dev) +{ + struct exynos_mmc_plat *plat = dev_get_platdata(dev); + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct dwmci_exynos_priv_data *priv = dev_get_priv(dev); + struct dwmci_host *host = &priv->host; + int err; + + err = exynos_dwmci_get_config(gd->fdt_blob, dev->of_offset, host); + if (err) + return err; + err = do_dwmci_init(host); + if (err) + return err; + + dwmci_setup_cfg(&plat->cfg, host->name, host->buswidth, host->caps, + DWMMC_MAX_FREQ, DWMMC_MIN_FREQ); + host->mmc = &plat->mmc; + host->mmc->priv = &priv->host; + host->priv = dev; + upriv->mmc = host->mmc; + + return dwmci_probe(dev); +} + +static int exynos_dwmmc_bind(struct udevice *dev) +{ + struct exynos_mmc_plat *plat = dev_get_platdata(dev); + int ret; + + ret = dwmci_bind(dev, &plat->mmc, &plat->cfg); + if (ret) + return ret; + + return 0; +} + +static const struct udevice_id exynos_dwmmc_ids[] = { + { .compatible = "samsung,exynos4412-dw-mshc" }, + { } +}; + +U_BOOT_DRIVER(exynos_dwmmc_drv) = { + .name = "exynos_dwmmc", + .id = UCLASS_MMC, + .of_match = exynos_dwmmc_ids, + .bind = exynos_dwmmc_bind, + .ops = &dm_dwmci_ops, + .probe = exynos_dwmmc_probe, + .priv_auto_alloc_size = sizeof(struct dwmci_exynos_priv_data), + .platdata_auto_alloc_size = sizeof(struct exynos_mmc_plat), +}; #endif diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index a865c7b47bd..103b32e9cf7 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -12,11 +12,11 @@ #include <config.h> #include <common.h> #include <command.h> +#include <errno.h> #include <hwconfig.h> #include <mmc.h> #include <part.h> #include <malloc.h> -#include <mmc.h> #include <fsl_esdhc.h> #include <fdt_support.h> #include <asm/io.h> @@ -253,7 +253,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) if ((esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL) == 0) { printf("\nThe SD card is locked. Can not write to a locked card.\n\n"); - return TIMEOUT; + return -ETIMEDOUT; } } @@ -411,12 +411,12 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) irqstat = esdhc_read32(®s->irqstat); if (irqstat & CMD_ERR) { - err = COMM_ERR; + err = -ECOMM; goto out; } if (irqstat & IRQSTAT_CTOE) { - err = TIMEOUT; + err = -ETIMEDOUT; goto out; } @@ -442,7 +442,7 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) if (timeout <= 0) { printf("Timeout waiting for DAT0 to go high!\n"); - err = TIMEOUT; + err = -ETIMEDOUT; goto out; } } @@ -471,12 +471,12 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) irqstat = esdhc_read32(®s->irqstat); if (irqstat & IRQSTAT_DTOE) { - err = TIMEOUT; + err = -ETIMEDOUT; goto out; } if (irqstat & DATA_ERR) { - err = COMM_ERR; + err = -ECOMM; goto out; } } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE); diff --git a/drivers/mmc/ftsdc010_mci.c b/drivers/mmc/ftsdc010_mci.c index a620678e5f9..c02740f0efb 100644 --- a/drivers/mmc/ftsdc010_mci.c +++ b/drivers/mmc/ftsdc010_mci.c @@ -34,7 +34,7 @@ static inline int ftsdc010_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd) { struct ftsdc010_chip *chip = mmc->priv; struct ftsdc010_mmc __iomem *regs = chip->regs; - int ret = TIMEOUT; + int ret = -ETIMEDOUT; uint32_t ts, st; uint32_t cmd = FTSDC010_CMD_IDX(mmc_cmd->cmdidx); uint32_t arg = mmc_cmd->cmdarg; @@ -126,7 +126,7 @@ static void ftsdc010_clkset(struct mmc *mmc, uint32_t rate) static int ftsdc010_wait(struct ftsdc010_mmc __iomem *regs, uint32_t mask) { - int ret = TIMEOUT; + int ret = -ETIMEDOUT; uint32_t st, ts; for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) { @@ -151,7 +151,7 @@ static int ftsdc010_wait(struct ftsdc010_mmc __iomem *regs, uint32_t mask) static int ftsdc010_request(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { - int ret = UNUSABLE_ERR; + int ret = -EOPNOTSUPP; uint32_t len = 0; struct ftsdc010_chip *chip = mmc->priv; struct ftsdc010_mmc __iomem *regs = chip->regs; @@ -279,7 +279,7 @@ static int ftsdc010_init(struct mmc *mmc) uint32_t ts; if (readl(®s->status) & FTSDC010_STATUS_CARD_DETECT) - return NO_CARD_ERR; + return -ENOMEDIUM; if (readl(®s->status) & FTSDC010_STATUS_WRITE_PROT) { printf("ftsdc010: write protected\n"); @@ -297,7 +297,7 @@ static int ftsdc010_init(struct mmc *mmc) } if (readl(®s->cmd) & FTSDC010_CMD_SDC_RST) { printf("ftsdc010: reset failed\n"); - return UNUSABLE_ERR; + return -EOPNOTSUPP; } /* 2. enter low speed mode (400k card detection) */ diff --git a/drivers/mmc/gen_atmel_mci.c b/drivers/mmc/gen_atmel_mci.c index 0474a154843..69770df44d8 100644 --- a/drivers/mmc/gen_atmel_mci.c +++ b/drivers/mmc/gen_atmel_mci.c @@ -213,7 +213,7 @@ mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) if (!priv->initialized) { puts ("MCI not initialized!\n"); - return COMM_ERR; + return -ECOMM; } /* Figure out the transfer arguments */ @@ -238,10 +238,10 @@ mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) if ((status & error_flags) & MMCI_BIT(RTOE)) { dump_cmd(cmdr, cmd->cmdarg, status, "Command Time Out"); - return TIMEOUT; + return -ETIMEDOUT; } else if (status & error_flags) { dump_cmd(cmdr, cmd->cmdarg, status, "Command Failed"); - return COMM_ERR; + return -ECOMM; } /* Copy the response to the response buffer */ @@ -303,7 +303,7 @@ mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) if (status) { dump_cmd(cmdr, cmd->cmdarg, status, "Data Transfer Failed"); - return COMM_ERR; + return -ECOMM; } } @@ -315,7 +315,7 @@ mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) if (status & error_flags) { dump_cmd(cmdr, cmd->cmdarg, status, "DTIP Wait Failed"); - return COMM_ERR; + return -ECOMM; } i++; } while ((status & MMCI_BIT(DTIP)) && i < 10000); diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c index 1b967d982bc..425abb1b9ef 100644 --- a/drivers/mmc/mmc-uclass.c +++ b/drivers/mmc/mmc-uclass.c @@ -8,8 +8,76 @@ #include <common.h> #include <mmc.h> #include <dm.h> +#include <dm/device-internal.h> #include <dm/lists.h> #include <dm/root.h> +#include "mmc_private.h" + +#ifdef CONFIG_DM_MMC_OPS +int dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + struct mmc *mmc = mmc_get_mmc_dev(dev); + struct dm_mmc_ops *ops = mmc_get_ops(dev); + int ret; + + mmmc_trace_before_send(mmc, cmd); + if (ops->send_cmd) + ret = ops->send_cmd(dev, cmd, data); + else + ret = -ENOSYS; + mmmc_trace_after_send(mmc, cmd, ret); + + return ret; +} + +int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) +{ + return dm_mmc_send_cmd(mmc->dev, cmd, data); +} + +int dm_mmc_set_ios(struct udevice *dev) +{ + struct dm_mmc_ops *ops = mmc_get_ops(dev); + + if (!ops->set_ios) + return -ENOSYS; + return ops->set_ios(dev); +} + +int mmc_set_ios(struct mmc *mmc) +{ + return dm_mmc_set_ios(mmc->dev); +} + +int dm_mmc_get_wp(struct udevice *dev) +{ + struct dm_mmc_ops *ops = mmc_get_ops(dev); + + if (!ops->get_wp) + return -ENOSYS; + return ops->get_wp(dev); +} + +int mmc_getwp(struct mmc *mmc) +{ + return dm_mmc_get_wp(mmc->dev); +} + +int dm_mmc_get_cd(struct udevice *dev) +{ + struct dm_mmc_ops *ops = mmc_get_ops(dev); + + if (!ops->get_cd) + return -ENOSYS; + return ops->get_cd(dev); +} + +int mmc_getcd(struct mmc *mmc) +{ + return dm_mmc_get_cd(mmc->dev); +} +#endif struct mmc *mmc_get_mmc_dev(struct udevice *dev) { @@ -43,18 +111,18 @@ struct mmc *find_mmc_device(int dev_num) int get_mmc_num(void) { - return max(blk_find_max_devnum(IF_TYPE_MMC), 0); + return max((blk_find_max_devnum(IF_TYPE_MMC) + 1), 0); } int mmc_get_next_devnum(void) { int ret; - ret = get_mmc_num(); + ret = blk_find_max_devnum(IF_TYPE_MMC); if (ret < 0) return ret; - return ret + 1; + return ret; } struct blk_desc *mmc_get_blk_desc(struct mmc *mmc) @@ -101,7 +169,7 @@ void print_mmc_devices(char separator) for (uclass_first_device(UCLASS_MMC, &dev); dev; - uclass_next_device(&dev)) { + uclass_next_device(&dev), first = false) { struct mmc *m = mmc_get_mmc_dev(dev); if (!first) { @@ -125,6 +193,84 @@ void print_mmc_devices(char separator) #else void print_mmc_devices(char separator) { } #endif + +int mmc_bind(struct udevice *dev, struct mmc *mmc, const struct mmc_config *cfg) +{ + struct blk_desc *bdesc; + struct udevice *bdev; + int ret; + + ret = blk_create_devicef(dev, "mmc_blk", "blk", IF_TYPE_MMC, -1, 512, + 0, &bdev); + if (ret) { + debug("Cannot create block device\n"); + return ret; + } + bdesc = dev_get_uclass_platdata(bdev); + mmc->cfg = cfg; + mmc->priv = dev; + + /* the following chunk was from mmc_register() */ + + /* Setup dsr related values */ + mmc->dsr_imp = 0; + mmc->dsr = 0xffffffff; + /* Setup the universal parts of the block interface just once */ + bdesc->removable = 1; + + /* setup initial part type */ + bdesc->part_type = cfg->part_type; + mmc->dev = dev; + + return 0; +} + +int mmc_unbind(struct udevice *dev) +{ + struct udevice *bdev; + + device_find_first_child(dev, &bdev); + if (bdev) { + device_remove(bdev); + device_unbind(bdev); + } + + return 0; +} + +static int mmc_select_hwpart(struct udevice *bdev, int hwpart) +{ + struct udevice *mmc_dev = dev_get_parent(bdev); + struct mmc *mmc = mmc_get_mmc_dev(mmc_dev); + struct blk_desc *desc = dev_get_uclass_platdata(bdev); + int ret; + + if (desc->hwpart == hwpart) + return 0; + + if (mmc->part_config == MMCPART_NOAVAILABLE) + return -EMEDIUMTYPE; + + ret = mmc_switch_part(mmc, hwpart); + if (ret) + return ret; + + return 0; +} + +static const struct blk_ops mmc_blk_ops = { + .read = mmc_bread, +#ifndef CONFIG_SPL_BUILD + .write = mmc_bwrite, +#endif + .select_hwpart = mmc_select_hwpart, +}; + +U_BOOT_DRIVER(mmc_blk) = { + .name = "mmc_blk", + .id = UCLASS_BLK, + .ops = &mmc_blk_ops, +}; #endif /* CONFIG_BLK */ U_BOOT_DRIVER(mmc) = { diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index aabfc711e5d..43ea0bba763 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -21,6 +21,7 @@ #include <div64.h> #include "mmc_private.h" +#ifndef CONFIG_DM_MMC_OPS __weak int board_mmc_getwp(struct mmc *mmc) { return -1; @@ -46,18 +47,20 @@ __weak int board_mmc_getcd(struct mmc *mmc) { return -1; } +#endif -int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) +#ifdef CONFIG_MMC_TRACE +void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd) { - int ret; + printf("CMD_SEND:%d\n", cmd->cmdidx); + printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg); +} -#ifdef CONFIG_MMC_TRACE +void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret) +{ int i; u8 *ptr; - printf("CMD_SEND:%d\n", cmd->cmdidx); - printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg); - ret = mmc->cfg->ops->send_cmd(mmc, cmd, data); if (ret) { printf("\t\tRET\t\t\t %d\n", ret); } else { @@ -103,19 +106,34 @@ int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) break; } } -#else - ret = mmc->cfg->ops->send_cmd(mmc, cmd, data); +} + +void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd) +{ + int status; + + status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9; + printf("CURR STATE:%d\n", status); +} #endif + +#ifndef CONFIG_DM_MMC_OPS +int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) +{ + int ret; + + mmmc_trace_before_send(mmc, cmd); + ret = mmc->cfg->ops->send_cmd(mmc, cmd, data); + mmmc_trace_after_send(mmc, cmd, ret); + return ret; } +#endif int mmc_send_status(struct mmc *mmc, int timeout) { struct mmc_cmd cmd; int err, retries = 5; -#ifdef CONFIG_MMC_TRACE - int status; -#endif cmd.cmdidx = MMC_CMD_SEND_STATUS; cmd.resp_type = MMC_RSP_R1; @@ -134,7 +152,7 @@ int mmc_send_status(struct mmc *mmc, int timeout) printf("Status Error: 0x%08X\n", cmd.response[0]); #endif - return COMM_ERR; + return -ECOMM; } } else if (--retries < 0) return err; @@ -145,15 +163,12 @@ int mmc_send_status(struct mmc *mmc, int timeout) udelay(1000); } -#ifdef CONFIG_MMC_TRACE - status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9; - printf("CURR STATE:%d\n", status); -#endif + mmc_trace_state(mmc, &cmd); if (timeout <= 0) { #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) printf("Timeout waiting card ready\n"); #endif - return TIMEOUT; + return -ETIMEDOUT; } return 0; @@ -215,11 +230,10 @@ static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start, } #ifdef CONFIG_BLK -static ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, - void *dst) +ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst) #else -static ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, - lbaint_t blkcnt, void *dst) +ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt, + void *dst) #endif { #ifdef CONFIG_BLK @@ -330,7 +344,7 @@ static int sd_send_op_cond(struct mmc *mmc) break; if (timeout-- <= 0) - return UNUSABLE_ERR; + return -EOPNOTSUPP; udelay(1000); } @@ -408,6 +422,9 @@ static int mmc_complete_op_cond(struct mmc *mmc) mmc->op_cond_pending = 0; if (!(mmc->ocr & OCR_BUSY)) { + /* Some cards seem to need this */ + mmc_go_idle(mmc); + start = get_timer(0); while (1) { err = mmc_send_op_cond_iter(mmc, 1); @@ -416,7 +433,7 @@ static int mmc_complete_op_cond(struct mmc *mmc) if (mmc->ocr & OCR_BUSY) break; if (get_timer(start) > timeout) - return UNUSABLE_ERR; + return -EOPNOTSUPP; udelay(100); } } @@ -464,8 +481,7 @@ static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd) return err; } - -static int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) +int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) { struct mmc_cmd cmd; int timeout = 1000; @@ -566,7 +582,7 @@ static int mmc_set_capacity(struct mmc *mmc, int part_num) return 0; } -static int mmc_switch_part(struct mmc *mmc, unsigned int part_num) +int mmc_switch_part(struct mmc *mmc, unsigned int part_num) { int ret; @@ -586,49 +602,6 @@ static int mmc_switch_part(struct mmc *mmc, unsigned int part_num) return ret; } -#ifdef CONFIG_BLK -static int mmc_select_hwpart(struct udevice *bdev, int hwpart) -{ - struct udevice *mmc_dev = dev_get_parent(bdev); - struct mmc *mmc = mmc_get_mmc_dev(mmc_dev); - struct blk_desc *desc = dev_get_uclass_platdata(bdev); - int ret; - - if (desc->hwpart == hwpart) - return 0; - - if (mmc->part_config == MMCPART_NOAVAILABLE) - return -EMEDIUMTYPE; - - ret = mmc_switch_part(mmc, hwpart); - if (ret) - return ret; - - return 0; -} -#else -static int mmc_select_hwpartp(struct blk_desc *desc, int hwpart) -{ - struct mmc *mmc = find_mmc_device(desc->devnum); - int ret; - - if (!mmc) - return -ENODEV; - - if (mmc->block_dev.hwpart == hwpart) - return 0; - - if (mmc->part_config == MMCPART_NOAVAILABLE) - return -EMEDIUMTYPE; - - ret = mmc_switch_part(mmc, hwpart); - if (ret) - return ret; - - return 0; -} -#endif - int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf, enum mmc_hwpart_conf_mode mode) @@ -823,6 +796,7 @@ int mmc_hwpart_config(struct mmc *mmc, return 0; } +#ifndef CONFIG_DM_MMC_OPS int mmc_getcd(struct mmc *mmc) { int cd; @@ -838,6 +812,7 @@ int mmc_getcd(struct mmc *mmc) return cd; } +#endif static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp) { @@ -1001,11 +976,13 @@ static const u8 multipliers[] = { 80, }; +#ifndef CONFIG_DM_MMC_OPS static void mmc_set_ios(struct mmc *mmc) { if (mmc->cfg->ops->set_ios) mmc->cfg->ops->set_ios(mmc); } +#endif void mmc_set_clock(struct mmc *mmc, uint clock) { @@ -1455,7 +1432,7 @@ static int mmc_startup(struct mmc *mmc) &test_csd[EXT_CSD_SEC_CNT], 4) == 0) break; else - err = SWITCH_ERR; + err = -EBADMSG; } if (err) @@ -1525,122 +1502,13 @@ static int mmc_send_if_cond(struct mmc *mmc) return err; if ((cmd.response[0] & 0xff) != 0xaa) - return UNUSABLE_ERR; + return -EOPNOTSUPP; else mmc->version = SD_VERSION_2; return 0; } -#ifdef CONFIG_BLK -int mmc_bind(struct udevice *dev, struct mmc *mmc, const struct mmc_config *cfg) -{ - struct blk_desc *bdesc; - struct udevice *bdev; - int ret; - - ret = blk_create_devicef(dev, "mmc_blk", "blk", IF_TYPE_MMC, -1, 512, - 0, &bdev); - if (ret) { - debug("Cannot create block device\n"); - return ret; - } - bdesc = dev_get_uclass_platdata(bdev); - mmc->cfg = cfg; - mmc->priv = dev; - - /* the following chunk was from mmc_register() */ - - /* Setup dsr related values */ - mmc->dsr_imp = 0; - mmc->dsr = 0xffffffff; - /* Setup the universal parts of the block interface just once */ - bdesc->removable = 1; - - /* setup initial part type */ - bdesc->part_type = cfg->part_type; - mmc->dev = dev; - - return 0; -} - -int mmc_unbind(struct udevice *dev) -{ - struct udevice *bdev; - - device_find_first_child(dev, &bdev); - if (bdev) { - device_remove(bdev); - device_unbind(bdev); - } - - return 0; -} - -#else -struct mmc *mmc_create(const struct mmc_config *cfg, void *priv) -{ - struct blk_desc *bdesc; - struct mmc *mmc; - - /* quick validation */ - if (cfg == NULL || cfg->ops == NULL || cfg->ops->send_cmd == NULL || - cfg->f_min == 0 || cfg->f_max == 0 || cfg->b_max == 0) - return NULL; - - mmc = calloc(1, sizeof(*mmc)); - if (mmc == NULL) - return NULL; - - mmc->cfg = cfg; - mmc->priv = priv; - - /* the following chunk was mmc_register() */ - - /* Setup dsr related values */ - mmc->dsr_imp = 0; - mmc->dsr = 0xffffffff; - /* Setup the universal parts of the block interface just once */ - bdesc = mmc_get_blk_desc(mmc); - bdesc->if_type = IF_TYPE_MMC; - bdesc->removable = 1; - bdesc->devnum = mmc_get_next_devnum(); - bdesc->block_read = mmc_bread; - bdesc->block_write = mmc_bwrite; - bdesc->block_erase = mmc_berase; - - /* setup initial part type */ - bdesc->part_type = mmc->cfg->part_type; - mmc_list_add(mmc); - - return mmc; -} - -void mmc_destroy(struct mmc *mmc) -{ - /* only freeing memory for now */ - free(mmc); -} -#endif - -#ifndef CONFIG_BLK -static int mmc_get_dev(int dev, struct blk_desc **descp) -{ - struct mmc *mmc = find_mmc_device(dev); - int ret; - - if (!mmc) - return -ENODEV; - ret = mmc_init(mmc); - if (ret) - return ret; - - *descp = &mmc->block_dev; - - return 0; -} -#endif - /* board-specific MMC power initializations. */ __weak void board_mmc_power_init(void) { @@ -1648,15 +1516,20 @@ __weak void board_mmc_power_init(void) int mmc_start_init(struct mmc *mmc) { + bool no_card; int err; /* we pretend there's no card when init is NULL */ - if (mmc_getcd(mmc) == 0 || mmc->cfg->ops->init == NULL) { + no_card = mmc_getcd(mmc) == 0; +#ifndef CONFIG_DM_MMC_OPS + no_card = no_card || (mmc->cfg->ops->init == NULL); +#endif + if (no_card) { mmc->has_init = 0; #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) printf("MMC: no card present\n"); #endif - return NO_CARD_ERR; + return -ENOMEDIUM; } if (mmc->has_init) @@ -1667,12 +1540,14 @@ int mmc_start_init(struct mmc *mmc) #endif board_mmc_power_init(); +#ifdef CONFIG_DM_MMC_OPS + /* The device has already been probed ready for use */ +#else /* made sure it's not NULL earlier */ err = mmc->cfg->ops->init(mmc); - if (err) return err; - +#endif mmc->ddr_mode = 0; mmc_set_bus_width(mmc, 1); mmc_set_clock(mmc, 1); @@ -1693,14 +1568,14 @@ int mmc_start_init(struct mmc *mmc) err = sd_send_op_cond(mmc); /* If the command timed out, we check for an MMC card */ - if (err == TIMEOUT) { + if (err == -ETIMEDOUT) { err = mmc_send_op_cond(mmc); if (err) { #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) printf("Card did not respond to voltage select!\n"); #endif - return UNUSABLE_ERR; + return -EOPNOTSUPP; } } @@ -1839,148 +1714,3 @@ int mmc_initialize(bd_t *bis) mmc_do_preinit(); return 0; } - -#ifdef CONFIG_SUPPORT_EMMC_BOOT -/* - * This function changes the size of boot partition and the size of rpmb - * partition present on EMMC devices. - * - * Input Parameters: - * struct *mmc: pointer for the mmc device strcuture - * bootsize: size of boot partition - * rpmbsize: size of rpmb partition - * - * Returns 0 on success. - */ - -int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, - unsigned long rpmbsize) -{ - int err; - struct mmc_cmd cmd; - - /* Only use this command for raw EMMC moviNAND. Enter backdoor mode */ - cmd.cmdidx = MMC_CMD_RES_MAN; - cmd.resp_type = MMC_RSP_R1b; - cmd.cmdarg = MMC_CMD62_ARG1; - - err = mmc_send_cmd(mmc, &cmd, NULL); - if (err) { - debug("mmc_boot_partition_size_change: Error1 = %d\n", err); - return err; - } - - /* Boot partition changing mode */ - cmd.cmdidx = MMC_CMD_RES_MAN; - cmd.resp_type = MMC_RSP_R1b; - cmd.cmdarg = MMC_CMD62_ARG2; - - err = mmc_send_cmd(mmc, &cmd, NULL); - if (err) { - debug("mmc_boot_partition_size_change: Error2 = %d\n", err); - return err; - } - /* boot partition size is multiple of 128KB */ - bootsize = (bootsize * 1024) / 128; - - /* Arg: boot partition size */ - cmd.cmdidx = MMC_CMD_RES_MAN; - cmd.resp_type = MMC_RSP_R1b; - cmd.cmdarg = bootsize; - - err = mmc_send_cmd(mmc, &cmd, NULL); - if (err) { - debug("mmc_boot_partition_size_change: Error3 = %d\n", err); - return err; - } - /* RPMB partition size is multiple of 128KB */ - rpmbsize = (rpmbsize * 1024) / 128; - /* Arg: RPMB partition size */ - cmd.cmdidx = MMC_CMD_RES_MAN; - cmd.resp_type = MMC_RSP_R1b; - cmd.cmdarg = rpmbsize; - - err = mmc_send_cmd(mmc, &cmd, NULL); - if (err) { - debug("mmc_boot_partition_size_change: Error4 = %d\n", err); - return err; - } - return 0; -} - -/* - * Modify EXT_CSD[177] which is BOOT_BUS_WIDTH - * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH - * and BOOT_MODE. - * - * Returns 0 on success. - */ -int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode) -{ - int err; - - err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH, - EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) | - EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) | - EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width)); - - if (err) - return err; - return 0; -} - -/* - * Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG) - * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and - * PARTITION_ACCESS. - * - * Returns 0 on success. - */ -int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access) -{ - int err; - - err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF, - EXT_CSD_BOOT_ACK(ack) | - EXT_CSD_BOOT_PART_NUM(part_num) | - EXT_CSD_PARTITION_ACCESS(access)); - - if (err) - return err; - return 0; -} - -/* - * Modify EXT_CSD[162] which is RST_n_FUNCTION based on the given value - * for enable. Note that this is a write-once field for non-zero values. - * - * Returns 0 on success. - */ -int mmc_set_rst_n_function(struct mmc *mmc, u8 enable) -{ - return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_RST_N_FUNCTION, - enable); -} -#endif - -#ifdef CONFIG_BLK -static const struct blk_ops mmc_blk_ops = { - .read = mmc_bread, - .write = mmc_bwrite, - .select_hwpart = mmc_select_hwpart, -}; - -U_BOOT_DRIVER(mmc_blk) = { - .name = "mmc_blk", - .id = UCLASS_BLK, - .ops = &mmc_blk_ops, -}; -#else -U_BOOT_LEGACY_BLK(mmc) = { - .if_typename = "mmc", - .if_type = IF_TYPE_MMC, - .max_devs = -1, - .get_dev = mmc_get_dev, - .select_hwpart = mmc_select_hwpartp, -}; -#endif diff --git a/drivers/mmc/mmc_boot.c b/drivers/mmc/mmc_boot.c new file mode 100644 index 00000000000..756a9824e3e --- /dev/null +++ b/drivers/mmc/mmc_boot.c @@ -0,0 +1,131 @@ +/* + * Copyright (C) 2016 Google, Inc + * Written by Amar <amarendra.xt@samsung.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <mmc.h> +#include "mmc_private.h" + +/* + * This function changes the size of boot partition and the size of rpmb + * partition present on EMMC devices. + * + * Input Parameters: + * struct *mmc: pointer for the mmc device strcuture + * bootsize: size of boot partition + * rpmbsize: size of rpmb partition + * + * Returns 0 on success. + */ + +int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, + unsigned long rpmbsize) +{ + int err; + struct mmc_cmd cmd; + + /* Only use this command for raw EMMC moviNAND. Enter backdoor mode */ + cmd.cmdidx = MMC_CMD_RES_MAN; + cmd.resp_type = MMC_RSP_R1b; + cmd.cmdarg = MMC_CMD62_ARG1; + + err = mmc_send_cmd(mmc, &cmd, NULL); + if (err) { + debug("mmc_boot_partition_size_change: Error1 = %d\n", err); + return err; + } + + /* Boot partition changing mode */ + cmd.cmdidx = MMC_CMD_RES_MAN; + cmd.resp_type = MMC_RSP_R1b; + cmd.cmdarg = MMC_CMD62_ARG2; + + err = mmc_send_cmd(mmc, &cmd, NULL); + if (err) { + debug("mmc_boot_partition_size_change: Error2 = %d\n", err); + return err; + } + /* boot partition size is multiple of 128KB */ + bootsize = (bootsize * 1024) / 128; + + /* Arg: boot partition size */ + cmd.cmdidx = MMC_CMD_RES_MAN; + cmd.resp_type = MMC_RSP_R1b; + cmd.cmdarg = bootsize; + + err = mmc_send_cmd(mmc, &cmd, NULL); + if (err) { + debug("mmc_boot_partition_size_change: Error3 = %d\n", err); + return err; + } + /* RPMB partition size is multiple of 128KB */ + rpmbsize = (rpmbsize * 1024) / 128; + /* Arg: RPMB partition size */ + cmd.cmdidx = MMC_CMD_RES_MAN; + cmd.resp_type = MMC_RSP_R1b; + cmd.cmdarg = rpmbsize; + + err = mmc_send_cmd(mmc, &cmd, NULL); + if (err) { + debug("mmc_boot_partition_size_change: Error4 = %d\n", err); + return err; + } + return 0; +} + +/* + * Modify EXT_CSD[177] which is BOOT_BUS_WIDTH + * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH + * and BOOT_MODE. + * + * Returns 0 on success. + */ +int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode) +{ + int err; + + err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH, + EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) | + EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) | + EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width)); + + if (err) + return err; + return 0; +} + +/* + * Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG) + * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and + * PARTITION_ACCESS. + * + * Returns 0 on success. + */ +int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access) +{ + int err; + + err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF, + EXT_CSD_BOOT_ACK(ack) | + EXT_CSD_BOOT_PART_NUM(part_num) | + EXT_CSD_PARTITION_ACCESS(access)); + + if (err) + return err; + return 0; +} + +/* + * Modify EXT_CSD[162] which is RST_n_FUNCTION based on the given value + * for enable. Note that this is a write-once field for non-zero values. + * + * Returns 0 on success. + */ +int mmc_set_rst_n_function(struct mmc *mmc, u8 enable) +{ + return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_RST_N_FUNCTION, + enable); +} diff --git a/drivers/mmc/mmc_legacy.c b/drivers/mmc/mmc_legacy.c index 3ec649f2b82..25361d10f60 100644 --- a/drivers/mmc/mmc_legacy.c +++ b/drivers/mmc/mmc_legacy.c @@ -6,7 +6,9 @@ */ #include <common.h> +#include <malloc.h> #include <mmc.h> +#include "mmc_private.h" static struct list_head mmc_devices; static int cur_dev_num = -1; @@ -106,3 +108,97 @@ void print_mmc_devices(char separator) #else void print_mmc_devices(char separator) { } #endif + +struct mmc *mmc_create(const struct mmc_config *cfg, void *priv) +{ + struct blk_desc *bdesc; + struct mmc *mmc; + + /* quick validation */ + if (cfg == NULL || cfg->f_min == 0 || + cfg->f_max == 0 || cfg->b_max == 0) + return NULL; + +#ifndef CONFIG_DM_MMC_OPS + if (cfg->ops == NULL || cfg->ops->send_cmd == NULL) + return NULL; +#endif + + mmc = calloc(1, sizeof(*mmc)); + if (mmc == NULL) + return NULL; + + mmc->cfg = cfg; + mmc->priv = priv; + + /* the following chunk was mmc_register() */ + + /* Setup dsr related values */ + mmc->dsr_imp = 0; + mmc->dsr = 0xffffffff; + /* Setup the universal parts of the block interface just once */ + bdesc = mmc_get_blk_desc(mmc); + bdesc->if_type = IF_TYPE_MMC; + bdesc->removable = 1; + bdesc->devnum = mmc_get_next_devnum(); + bdesc->block_read = mmc_bread; + bdesc->block_write = mmc_bwrite; + bdesc->block_erase = mmc_berase; + + /* setup initial part type */ + bdesc->part_type = mmc->cfg->part_type; + mmc_list_add(mmc); + + return mmc; +} + +void mmc_destroy(struct mmc *mmc) +{ + /* only freeing memory for now */ + free(mmc); +} + +static int mmc_select_hwpartp(struct blk_desc *desc, int hwpart) +{ + struct mmc *mmc = find_mmc_device(desc->devnum); + int ret; + + if (!mmc) + return -ENODEV; + + if (mmc->block_dev.hwpart == hwpart) + return 0; + + if (mmc->part_config == MMCPART_NOAVAILABLE) + return -EMEDIUMTYPE; + + ret = mmc_switch_part(mmc, hwpart); + if (ret) + return ret; + + return 0; +} + +static int mmc_get_dev(int dev, struct blk_desc **descp) +{ + struct mmc *mmc = find_mmc_device(dev); + int ret; + + if (!mmc) + return -ENODEV; + ret = mmc_init(mmc); + if (ret) + return ret; + + *descp = &mmc->block_dev; + + return 0; +} + +U_BOOT_LEGACY_BLK(mmc) = { + .if_typename = "mmc", + .if_type = IF_TYPE_MMC, + .max_devs = -1, + .get_dev = mmc_get_dev, + .select_hwpart = mmc_select_hwpartp, +}; diff --git a/drivers/mmc/mmc_private.h b/drivers/mmc/mmc_private.h index 9f0d5c2384a..49ec022a9e9 100644 --- a/drivers/mmc/mmc_private.h +++ b/drivers/mmc/mmc_private.h @@ -20,6 +20,14 @@ extern int mmc_set_blocklen(struct mmc *mmc, int len); void mmc_adapter_card_type_ident(void); #endif +#ifdef CONFIG_BLK +ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, + void *dst); +#else +ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt, + void *dst); +#endif + #ifndef CONFIG_SPL_BUILD unsigned long mmc_berase(struct blk_desc *block_dev, lbaint_t start, @@ -65,6 +73,25 @@ static inline ulong mmc_bwrite(struct blk_desc *block_dev, lbaint_t start, #endif /* CONFIG_SPL_BUILD */ +#ifdef CONFIG_MMC_TRACE +void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd); +void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret); +void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd); +#else +static inline void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd) +{ +} + +static inline void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, + int ret) +{ +} + +static inline void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd) +{ +} +#endif + /** * mmc_get_next_devnum() - Get the next available MMC device number * @@ -89,4 +116,24 @@ void mmc_list_init(void); */ void mmc_list_add(struct mmc *mmc); +/** + * mmc_switch_part() - Switch to a new MMC hardware partition + * + * @mmc: MMC device + * @part_num: Hardware partition number + * @return 0 if OK, -ve on error + */ +int mmc_switch_part(struct mmc *mmc, unsigned int part_num); + +/** + * mmc_switch() - Issue and MMC switch mode command + * + * @mmc: MMC device + * @set: Unused + * @index: Cmdarg index + * @value: Cmdarg value + * @return 0 if OK, -ve on error + */ +int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value); + #endif /* _MMC_PRIVATE_H_ */ diff --git a/drivers/mmc/mmc_spi.c b/drivers/mmc/mmc_spi.c index 7547e1aef88..25101179f65 100644 --- a/drivers/mmc/mmc_spi.c +++ b/drivers/mmc/mmc_spi.c @@ -5,6 +5,7 @@ * Licensed under the GPL-2 or later. */ #include <common.h> +#include <errno.h> #include <malloc.h> #include <part.h> #include <mmc.h> @@ -182,13 +183,13 @@ static int mmc_spi_request(struct mmc *mmc, struct mmc_cmd *cmd, spi_cs_activate(spi); r1 = mmc_spi_sendcmd(mmc, cmd->cmdidx, cmd->cmdarg); if (r1 == 0xff) { /* no response */ - ret = NO_CARD_ERR; + ret = -ENOMEDIUM; goto done; } else if (r1 & R1_SPI_COM_CRC) { - ret = COMM_ERR; + ret = -ECOMM; goto done; } else if (r1 & ~R1_SPI_IDLE) { /* other errors */ - ret = TIMEOUT; + ret = -ETIMEDOUT; goto done; } else if (cmd->resp_type == MMC_RSP_R2) { r1 = mmc_spi_readdata(mmc, cmd->response, 1, 16); @@ -225,9 +226,9 @@ static int mmc_spi_request(struct mmc *mmc, struct mmc_cmd *cmd, data->blocks, data->blocksize, (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK)); if (r1 & R1_SPI_COM_CRC) - ret = COMM_ERR; + ret = -ECOMM; else if (r1) /* other errors */ - ret = TIMEOUT; + ret = -ETIMEDOUT; } done: spi_cs_deactivate(spi); diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c index 96dcdbec519..8d4399e9675 100644 --- a/drivers/mmc/msm_sdhci.c +++ b/drivers/mmc/msm_sdhci.c @@ -36,6 +36,11 @@ /* Non standard (?) SDHCI register */ #define SDHCI_VENDOR_SPEC_CAPABILITIES0 0x11c +struct msm_sdhc_plat { + struct mmc_config cfg; + struct mmc mmc; +}; + struct msm_sdhc { struct sdhci_host host; void *base; @@ -81,9 +86,12 @@ static int msm_sdc_clk_init(struct udevice *dev) static int msm_sdc_probe(struct udevice *dev) { + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct msm_sdhc_plat *plat = dev_get_platdata(dev); struct msm_sdhc *prv = dev_get_priv(dev); struct sdhci_host *host = &prv->host; u32 core_version, core_minor, core_major; + u32 caps; int ret; host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_BROKEN_R1B; @@ -127,7 +135,7 @@ static int msm_sdc_probe(struct udevice *dev) * controller versions and must be explicitly enabled. */ if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) { - u32 caps = readl(host->ioaddr + SDHCI_CAPABILITIES); + caps = readl(host->ioaddr + SDHCI_CAPABILITIES); caps |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT; writel(caps, host->ioaddr + SDHCI_VENDOR_SPEC_CAPABILITIES0); } @@ -135,13 +143,15 @@ static int msm_sdc_probe(struct udevice *dev) /* Set host controller version */ host->version = sdhci_readw(host, SDHCI_HOST_VERSION); - /* automatically detect max and min speed */ - ret = add_sdhci(host, 0, 0); + ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0); + host->mmc = &plat->mmc; if (ret) return ret; + host->mmc->priv = &prv->host; host->mmc->dev = dev; + upriv->mmc = host->mmc; - return 0; + return sdhci_probe(dev); } static int msm_sdc_remove(struct udevice *dev) @@ -168,7 +178,8 @@ static int msm_ofdata_to_platdata(struct udevice *dev) priv->base = (void *)fdtdec_get_addr_size_auto_parent(gd->fdt_blob, parent->of_offset, dev->of_offset, - "reg", 1, NULL); + "reg", 1, NULL, + false); if (priv->base == (void *)FDT_ADDR_T_NONE || host->ioaddr == (void *)FDT_ADDR_T_NONE) return -EINVAL; @@ -176,6 +187,18 @@ static int msm_ofdata_to_platdata(struct udevice *dev) return 0; } +static int msm_sdc_bind(struct udevice *dev) +{ + struct msm_sdhc_plat *plat = dev_get_platdata(dev); + int ret; + + ret = sdhci_bind(dev, &plat->mmc, &plat->cfg); + if (ret) + return ret; + + return 0; +} + static const struct udevice_id msm_mmc_ids[] = { { .compatible = "qcom,sdhci-msm-v4" }, { } @@ -186,7 +209,10 @@ U_BOOT_DRIVER(msm_sdc_drv) = { .id = UCLASS_MMC, .of_match = msm_mmc_ids, .ofdata_to_platdata = msm_ofdata_to_platdata, + .ops = &sdhci_ops, + .bind = msm_sdc_bind, .probe = msm_sdc_probe, .remove = msm_sdc_remove, .priv_auto_alloc_size = sizeof(struct msm_sdhc), + .platdata_auto_alloc_size = sizeof(struct msm_sdhc_plat), }; diff --git a/drivers/mmc/mvebu_mmc.c b/drivers/mmc/mvebu_mmc.c index 056aef5bef0..a2792ac4ecb 100644 --- a/drivers/mmc/mvebu_mmc.c +++ b/drivers/mmc/mvebu_mmc.c @@ -9,6 +9,7 @@ */ #include <common.h> +#include <errno.h> #include <malloc.h> #include <part.h> #include <mmc.h> @@ -172,15 +173,15 @@ static int mvebu_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, (SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT)) { debug("%s: command READ timed out\n", DRIVER_NAME); - return TIMEOUT; + return -ETIMEDOUT; } debug("%s: command READ error\n", DRIVER_NAME); - return COMM_ERR; + return -ECOMM; } if ((get_timer(0) - start) > TIMEOUT_DELAY) { debug("%s: command timed out\n", DRIVER_NAME); - return TIMEOUT; + return -ETIMEDOUT; } } @@ -232,7 +233,7 @@ static int mvebu_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, if (mvebu_mmc_read(SDIO_ERR_INTR_STATUS) & (SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT)) - return TIMEOUT; + return -ETIMEDOUT; return 0; } diff --git a/drivers/mmc/mxcmmc.c b/drivers/mmc/mxcmmc.c index 561b2045986..8038f904524 100644 --- a/drivers/mmc/mxcmmc.c +++ b/drivers/mmc/mxcmmc.c @@ -211,11 +211,11 @@ static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat) } else if (stat & STATUS_CRC_WRITE_ERR) { u32 err_code = (stat >> 9) & 0x3; if (err_code == 2) /* No CRC response */ - data_error = TIMEOUT; + data_error = -ETIMEDOUT; else data_error = -EILSEQ; } else if (stat & STATUS_TIME_OUT_READ) { - data_error = TIMEOUT; + data_error = -ETIMEDOUT; } else { data_error = -EIO; } @@ -238,7 +238,7 @@ static int mxcmci_read_response(struct mxcmci_host *host, unsigned int stat) if (stat & STATUS_TIME_OUT_RESP) { printf("CMD TIMEOUT\n"); - return TIMEOUT; + return -ETIMEDOUT; } else if (stat & STATUS_RESP_CRC_ERR && cmd->resp_type & MMC_RSP_CRC) { printf("cmd crc error\n"); return -EILSEQ; diff --git a/drivers/mmc/mxsmmc.c b/drivers/mmc/mxsmmc.c index 9fa87d57173..40f3eaaa864 100644 --- a/drivers/mmc/mxsmmc.c +++ b/drivers/mmc/mxsmmc.c @@ -84,7 +84,7 @@ static int mxsmmc_send_cmd_pio(struct mxsmmc_priv *priv, struct mmc_data *data) } } - return timeout ? 0 : COMM_ERR; + return timeout ? 0 : -ECOMM; } static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data) @@ -120,7 +120,7 @@ static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data) mxs_dma_desc_append(dmach, priv->desc); if (mxs_dma_go(dmach)) { bounce_buffer_stop(&bbstate); - return COMM_ERR; + return -ECOMM; } bounce_buffer_stop(&bbstate); @@ -158,13 +158,13 @@ mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) if (!timeout) { printf("MMC%d: Bus busy timeout!\n", mmc->block_dev.devnum); - return TIMEOUT; + return -ETIMEDOUT; } /* See if card is present */ if (!mxsmmc_cd(priv)) { printf("MMC%d: No card detected!\n", mmc->block_dev.devnum); - return NO_CARD_ERR; + return -ENOMEDIUM; } /* Start building CTRL0 contents */ @@ -203,7 +203,7 @@ mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) priv->mmc_is_wp(mmc->block_dev.devnum)) { printf("MMC%d: Can not write a locked card!\n", mmc->block_dev.devnum); - return UNUSABLE_ERR; + return -EOPNOTSUPP; } ctrl0 |= SSP_CTRL0_DATA_XFER; @@ -244,21 +244,21 @@ mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) if (!timeout) { printf("MMC%d: Command %d busy\n", mmc->block_dev.devnum, cmd->cmdidx); - return TIMEOUT; + return -ETIMEDOUT; } /* Check command timeout */ if (reg & SSP_STATUS_RESP_TIMEOUT) { printf("MMC%d: Command %d timeout (status 0x%08x)\n", mmc->block_dev.devnum, cmd->cmdidx, reg); - return TIMEOUT; + return -ETIMEDOUT; } /* Check command errors */ if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) { printf("MMC%d: Command %d error (status 0x%08x)!\n", mmc->block_dev.devnum, cmd->cmdidx, reg); - return COMM_ERR; + return -ECOMM; } /* Copy response to response buffer */ @@ -298,7 +298,7 @@ mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) { printf("MMC%d: Data error with command %d (status 0x%08x)!\n", mmc->block_dev.devnum, cmd->cmdidx, reg); - return COMM_ERR; + return -ECOMM; } return 0; diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index d007b562936..fceafe1f156 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -231,7 +231,7 @@ static int omap_hsmmc_init_setup(struct mmc *mmc) while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) { if (get_timer(0) - start > MAX_RETRY_MS) { printf("%s: timedout waiting for cc2!\n", __func__); - return TIMEOUT; + return -ETIMEDOUT; } } writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl); @@ -240,7 +240,7 @@ static int omap_hsmmc_init_setup(struct mmc *mmc) if (get_timer(0) - start > MAX_RETRY_MS) { printf("%s: timedout waiting for softresetall!\n", __func__); - return TIMEOUT; + return -ETIMEDOUT; } } writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl); @@ -262,7 +262,7 @@ static int omap_hsmmc_init_setup(struct mmc *mmc) while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) { if (get_timer(0) - start > MAX_RETRY_MS) { printf("%s: timedout waiting for ics!\n", __func__); - return TIMEOUT; + return -ETIMEDOUT; } } writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); @@ -337,7 +337,7 @@ static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, if (get_timer(0) - start > MAX_RETRY_MS) { printf("%s: timedout waiting on cmd inhibit to clear\n", __func__); - return TIMEOUT; + return -ETIMEDOUT; } } writel(0xFFFFFFFF, &mmc_base->stat); @@ -346,7 +346,7 @@ static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, if (get_timer(0) - start > MAX_RETRY_MS) { printf("%s: timedout waiting for STAT (%x) to clear\n", __func__, readl(&mmc_base->stat)); - return TIMEOUT; + return -ETIMEDOUT; } } /* @@ -410,13 +410,13 @@ static int omap_hsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, mmc_stat = readl(&mmc_base->stat); if (get_timer(0) - start > MAX_RETRY_MS) { printf("%s : timeout: No status update\n", __func__); - return TIMEOUT; + return -ETIMEDOUT; } } while (!mmc_stat); if ((mmc_stat & IE_CTO) != 0) { mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC); - return TIMEOUT; + return -ETIMEDOUT; } else if ((mmc_stat & ERRI_MASK) != 0) return -1; @@ -464,7 +464,7 @@ static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size) if (get_timer(0) - start > MAX_RETRY_MS) { printf("%s: timedout waiting for status!\n", __func__); - return TIMEOUT; + return -ETIMEDOUT; } } while (mmc_stat == 0); @@ -519,7 +519,7 @@ static int mmc_write_data(struct hsmmc *mmc_base, const char *buf, if (get_timer(0) - start > MAX_RETRY_MS) { printf("%s: timedout waiting for status!\n", __func__); - return TIMEOUT; + return -ETIMEDOUT; } } while (mmc_stat == 0); @@ -801,7 +801,9 @@ static int omap_hsmmc_ofdata_to_platdata(struct udevice *dev) cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; +#ifdef OMAP_HSMMC_USE_GPIO priv->cd_inverted = fdtdec_get_bool(fdt, node, "cd-inverted"); +#endif return 0; } diff --git a/drivers/mmc/rockchip_dw_mmc.c b/drivers/mmc/rockchip_dw_mmc.c index d41d60ce358..020a59b9218 100644 --- a/drivers/mmc/rockchip_dw_mmc.c +++ b/drivers/mmc/rockchip_dw_mmc.c @@ -7,8 +7,10 @@ #include <common.h> #include <clk.h> #include <dm.h> +#include <dt-structs.h> #include <dwmmc.h> #include <errno.h> +#include <mapmem.h> #include <pwrseq.h> #include <syscon.h> #include <asm/gpio.h> @@ -19,6 +21,9 @@ DECLARE_GLOBAL_DATA_PTR; struct rockchip_mmc_plat { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_rockchip_rk3288_dw_mshc dtplat; +#endif struct mmc_config cfg; struct mmc mmc; }; @@ -26,6 +31,9 @@ struct rockchip_mmc_plat { struct rockchip_dwmmc_priv { struct clk clk; struct dwmci_host host; + int fifo_depth; + bool fifo_mode; + u32 minmax[2]; }; static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq) @@ -45,6 +53,7 @@ static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq) static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev) { +#if !CONFIG_IS_ENABLED(OF_PLATDATA) struct rockchip_dwmmc_priv *priv = dev_get_priv(dev); struct dwmci_host *host = &priv->host; @@ -61,40 +70,54 @@ static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev) else host->dev_index = 1; + priv->fifo_depth = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "fifo-depth", 0); + if (priv->fifo_depth < 0) + return -EINVAL; + priv->fifo_mode = fdtdec_get_bool(gd->fdt_blob, dev->of_offset, + "fifo-mode"); + if (fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, + "clock-freq-min-max", priv->minmax, 2)) + return -EINVAL; +#endif return 0; } static int rockchip_dwmmc_probe(struct udevice *dev) { -#ifdef CONFIG_BLK struct rockchip_mmc_plat *plat = dev_get_platdata(dev); -#endif struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); struct rockchip_dwmmc_priv *priv = dev_get_priv(dev); struct dwmci_host *host = &priv->host; struct udevice *pwr_dev __maybe_unused; - u32 minmax[2]; int ret; - int fifo_depth; +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_rockchip_rk3288_dw_mshc *dtplat = &plat->dtplat; + + host->name = dev->name; + host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]); + host->buswidth = dtplat->bus_width; + host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk; + host->priv = dev; + host->dev_index = 0; + priv->fifo_depth = dtplat->fifo_depth; + priv->fifo_mode = 0; + memcpy(priv->minmax, dtplat->clock_freq_min_max, sizeof(priv->minmax)); + + ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk); + if (ret < 0) + return ret; +#else ret = clk_get_by_index(dev, 0, &priv->clk); if (ret < 0) return ret; - - if (fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, - "clock-freq-min-max", minmax, 2)) - return -EINVAL; - - fifo_depth = fdtdec_get_int(gd->fdt_blob, dev->of_offset, - "fifo-depth", 0); - if (fifo_depth < 0) - return -EINVAL; - +#endif host->fifoth_val = MSIZE(0x2) | - RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2); + RX_WMARK(priv->fifo_depth / 2 - 1) | + TX_WMARK(priv->fifo_depth / 2); - if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "fifo-mode")) - host->fifo_mode = true; + host->fifo_mode = priv->fifo_mode; #ifdef CONFIG_PWRSEQ /* Enable power if needed */ @@ -106,33 +129,24 @@ static int rockchip_dwmmc_probe(struct udevice *dev) return ret; } #endif -#ifdef CONFIG_BLK dwmci_setup_cfg(&plat->cfg, dev->name, host->buswidth, host->caps, - minmax[1], minmax[0]); + priv->minmax[1], priv->minmax[0]); host->mmc = &plat->mmc; -#else - ret = add_dwmci(host, minmax[1], minmax[0]); - if (ret) - return ret; - -#endif host->mmc->priv = &priv->host; host->mmc->dev = dev; upriv->mmc = host->mmc; - return 0; + return dwmci_probe(dev); } static int rockchip_dwmmc_bind(struct udevice *dev) { -#ifdef CONFIG_BLK struct rockchip_mmc_plat *plat = dev_get_platdata(dev); int ret; ret = dwmci_bind(dev, &plat->mmc, &plat->cfg); if (ret) return ret; -#endif return 0; } @@ -143,10 +157,11 @@ static const struct udevice_id rockchip_dwmmc_ids[] = { }; U_BOOT_DRIVER(rockchip_dwmmc_drv) = { - .name = "rockchip_dwmmc", + .name = "rockchip_rk3288_dw_mshc", .id = UCLASS_MMC, .of_match = rockchip_dwmmc_ids, .ofdata_to_platdata = rockchip_dwmmc_ofdata_to_platdata, + .ops = &dm_dwmci_ops, .bind = rockchip_dwmmc_bind, .probe = rockchip_dwmmc_probe, .priv_auto_alloc_size = sizeof(struct rockchip_dwmmc_priv), diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c new file mode 100644 index 00000000000..624029bd20a --- /dev/null +++ b/drivers/mmc/rockchip_sdhci.c @@ -0,0 +1,89 @@ +/* + * (C) Copyright 2016 Fuzhou Rockchip Electronics Co., Ltd + * + * Rockchip SD Host Controller Interface + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <fdtdec.h> +#include <libfdt.h> +#include <malloc.h> +#include <sdhci.h> + +/* 400KHz is max freq for card ID etc. Use that as min */ +#define EMMC_MIN_FREQ 400000 + +struct rockchip_sdhc_plat { + struct mmc_config cfg; + struct mmc mmc; +}; + +struct rockchip_sdhc { + struct sdhci_host host; + void *base; +}; + +static int arasan_sdhci_probe(struct udevice *dev) +{ + struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); + struct rockchip_sdhc_plat *plat = dev_get_platdata(dev); + struct rockchip_sdhc *prv = dev_get_priv(dev); + struct sdhci_host *host = &prv->host; + int ret; + + host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD; + + ret = sdhci_setup_cfg(&plat->cfg, host, CONFIG_ROCKCHIP_SDHCI_MAX_FREQ, + EMMC_MIN_FREQ); + + host->mmc = &plat->mmc; + if (ret) + return ret; + host->mmc->priv = &prv->host; + host->mmc->dev = dev; + upriv->mmc = host->mmc; + + return sdhci_probe(dev); +} + +static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev) +{ + struct sdhci_host *host = dev_get_priv(dev); + + host->name = dev->name; + host->ioaddr = dev_get_addr_ptr(dev); + + return 0; +} + +static int rockchip_sdhci_bind(struct udevice *dev) +{ + struct rockchip_sdhc_plat *plat = dev_get_platdata(dev); + int ret; + + ret = sdhci_bind(dev, &plat->mmc, &plat->cfg); + if (ret) + return ret; + + return 0; +} + +static const struct udevice_id arasan_sdhci_ids[] = { + { .compatible = "arasan,sdhci-5.1" }, + { } +}; + +U_BOOT_DRIVER(arasan_sdhci_drv) = { + .name = "arasan_sdhci", + .id = UCLASS_MMC, + .of_match = arasan_sdhci_ids, + .ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata, + .ops = &sdhci_ops, + .bind = rockchip_sdhci_bind, + .probe = arasan_sdhci_probe, + .priv_auto_alloc_size = sizeof(struct rockchip_sdhc), + .platdata_auto_alloc_size = sizeof(struct rockchip_sdhc_plat), +}; diff --git a/drivers/mmc/s3c_sdi.c b/drivers/mmc/s3c_sdi.c index 02d1138a5fd..1b8358a7bc1 100644 --- a/drivers/mmc/s3c_sdi.c +++ b/drivers/mmc/s3c_sdi.c @@ -133,7 +133,7 @@ s3cmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) if (!timeout) { puts("S3C SDI: Command timed out!\n"); - ret = TIMEOUT; + ret = -ETIMEDOUT; goto error; } @@ -196,7 +196,7 @@ s3cmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) if (!timeout) { puts("S3C SDI: Command timed out!\n"); - ret = TIMEOUT; + ret = -ETIMEDOUT; goto error; } diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c index 44353c72f4d..3bace21a046 100644 --- a/drivers/mmc/s5p_sdhci.c +++ b/drivers/mmc/s5p_sdhci.c @@ -68,7 +68,7 @@ static int s5p_sdhci_core_init(struct sdhci_host *host) host->name = S5P_NAME; host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE | - SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR | + SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_USE_WIDE8; host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; host->version = sdhci_readw(host, SDHCI_HOST_VERSION); diff --git a/drivers/mmc/sandbox_mmc.c b/drivers/mmc/sandbox_mmc.c index 7da059c43cd..5f1333b7480 100644 --- a/drivers/mmc/sandbox_mmc.c +++ b/drivers/mmc/sandbox_mmc.c @@ -25,7 +25,7 @@ struct sandbox_mmc_plat { * This emulate an SD card version 2. Single-block reads result in zero data. * Multiple-block reads return a test string. */ -static int sandbox_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, +static int sandbox_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, struct mmc_data *data) { switch (cmd->cmdidx) { @@ -85,25 +85,20 @@ static int sandbox_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, return 0; } -static void sandbox_mmc_set_ios(struct mmc *mmc) -{ -} - -static int sandbox_mmc_init(struct mmc *mmc) +static int sandbox_mmc_set_ios(struct udevice *dev) { return 0; } -static int sandbox_mmc_getcd(struct mmc *mmc) +static int sandbox_mmc_get_cd(struct udevice *dev) { return 1; } -static const struct mmc_ops sandbox_mmc_ops = { +static const struct dm_mmc_ops sandbox_mmc_ops = { .send_cmd = sandbox_mmc_send_cmd, .set_ios = sandbox_mmc_set_ios, - .init = sandbox_mmc_init, - .getcd = sandbox_mmc_getcd, + .get_cd = sandbox_mmc_get_cd, }; int sandbox_mmc_probe(struct udevice *dev) @@ -120,7 +115,6 @@ int sandbox_mmc_bind(struct udevice *dev) int ret; cfg->name = dev->name; - cfg->ops = &sandbox_mmc_ops; cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT; cfg->voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34; cfg->f_min = 1000000; @@ -150,6 +144,7 @@ U_BOOT_DRIVER(mmc_sandbox) = { .name = "mmc_sandbox", .id = UCLASS_MMC, .of_match = sandbox_mmc_ids, + .ops = &sandbox_mmc_ops, .bind = sandbox_mmc_bind, .unbind = sandbox_mmc_unbind, .probe = sandbox_mmc_probe, diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index 604f18dcc96..7ddb549e03c 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -9,6 +9,7 @@ */ #include <common.h> +#include <errno.h> #include <malloc.h> #include <mmc.h> #include <sdhci.h> @@ -129,9 +130,17 @@ static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data, #define CONFIG_SDHCI_CMD_DEFAULT_TIMEOUT 100 #define SDHCI_READ_STATUS_TIMEOUT 1000 +#ifdef CONFIG_DM_MMC_OPS +static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + struct mmc *mmc = mmc_get_mmc_dev(dev); + +#else static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, - struct mmc_data *data) + struct mmc_data *data) { +#endif struct sdhci_host *host = mmc->priv; unsigned int stat = 0; int ret = 0; @@ -161,7 +170,7 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, cmd_timeout); } else { puts("timeout.\n"); - return COMM_ERR; + return -ECOMM; } } time++; @@ -175,7 +184,8 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, flags = SDHCI_CMD_RESP_LONG; else if (cmd->resp_type & MMC_RSP_BUSY) { flags = SDHCI_CMD_RESP_SHORT_BUSY; - mask |= SDHCI_INT_DATA_END; + if (data) + mask |= SDHCI_INT_DATA_END; } else flags = SDHCI_CMD_RESP_SHORT; @@ -243,17 +253,17 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, stat = sdhci_readl(host, SDHCI_INT_STATUS); if (stat & SDHCI_INT_ERROR) break; - } while (((stat & mask) != mask) && - (get_timer(start) < SDHCI_READ_STATUS_TIMEOUT)); - if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) { - if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) - return 0; - else { - printf("%s: Timeout for status update!\n", __func__); - return TIMEOUT; + if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) { + if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) { + return 0; + } else { + printf("%s: Timeout for status update!\n", + __func__); + return -ETIMEDOUT; + } } - } + } while ((stat & mask) != mask); if ((stat & (SDHCI_INT_ERROR | mask)) == mask) { sdhci_cmd_done(host, cmd); @@ -279,9 +289,9 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd, sdhci_reset(host, SDHCI_RESET_CMD); sdhci_reset(host, SDHCI_RESET_DATA); if (stat & SDHCI_INT_TIMEOUT) - return TIMEOUT; + return -ETIMEDOUT; else - return COMM_ERR; + return -ECOMM; } static int sdhci_set_clock(struct mmc *mmc, unsigned int clock) @@ -304,7 +314,7 @@ static int sdhci_set_clock(struct mmc *mmc, unsigned int clock) } reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL); - reg &= ~SDHCI_CLOCK_CARD_EN; + reg &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN); sdhci_writew(host, reg, SDHCI_CLOCK_CONTROL); if (clock == 0) @@ -389,8 +399,14 @@ static void sdhci_set_power(struct sdhci_host *host, unsigned short power) sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); } +#ifdef CONFIG_DM_MMC_OPS +static int sdhci_set_ios(struct udevice *dev) +{ + struct mmc *mmc = mmc_get_mmc_dev(dev); +#else static void sdhci_set_ios(struct mmc *mmc) { +#endif u32 ctrl; struct sdhci_host *host = mmc->priv; @@ -426,6 +442,9 @@ static void sdhci_set_ios(struct mmc *mmc) ctrl &= ~SDHCI_CTRL_HISPD; sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); +#ifdef CONFIG_DM_MMC_OPS + return 0; +#endif } static int sdhci_init(struct mmc *mmc) @@ -472,80 +491,109 @@ static int sdhci_init(struct mmc *mmc) return 0; } +#ifdef CONFIG_DM_MMC_OPS +int sdhci_probe(struct udevice *dev) +{ + struct mmc *mmc = mmc_get_mmc_dev(dev); + return sdhci_init(mmc); +} + +const struct dm_mmc_ops sdhci_ops = { + .send_cmd = sdhci_send_command, + .set_ios = sdhci_set_ios, +}; +#else static const struct mmc_ops sdhci_ops = { .send_cmd = sdhci_send_command, .set_ios = sdhci_set_ios, .init = sdhci_init, }; +#endif -int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk) +int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host, + u32 max_clk, u32 min_clk) { - unsigned int caps; - - host->cfg.name = host->name; - host->cfg.ops = &sdhci_ops; + u32 caps; caps = sdhci_readl(host, SDHCI_CAPABILITIES); -#ifdef CONFIG_MMC_SDMA - if (!(caps & SDHCI_CAN_DO_SDMA)) { - printf("%s: Your controller doesn't support SDMA!!\n", - __func__); - return -1; - } -#endif + host->version = sdhci_readw(host, SDHCI_HOST_VERSION); + cfg->name = host->name; +#ifndef CONFIG_DM_MMC_OPS + cfg->ops = &sdhci_ops; +#endif if (max_clk) - host->cfg.f_max = max_clk; + cfg->f_max = max_clk; else { if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) - host->cfg.f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK) - >> SDHCI_CLOCK_BASE_SHIFT; + cfg->f_max = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> + SDHCI_CLOCK_BASE_SHIFT; else - host->cfg.f_max = (caps & SDHCI_CLOCK_BASE_MASK) - >> SDHCI_CLOCK_BASE_SHIFT; - host->cfg.f_max *= 1000000; - } - if (host->cfg.f_max == 0) { - printf("%s: Hardware doesn't specify base clock frequency\n", - __func__); - return -1; + cfg->f_max = (caps & SDHCI_CLOCK_BASE_MASK) >> + SDHCI_CLOCK_BASE_SHIFT; + cfg->f_max *= 1000000; } + if (cfg->f_max == 0) + return -EINVAL; if (min_clk) - host->cfg.f_min = min_clk; + cfg->f_min = min_clk; else { if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) - host->cfg.f_min = host->cfg.f_max / - SDHCI_MAX_DIV_SPEC_300; + cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300; else - host->cfg.f_min = host->cfg.f_max / - SDHCI_MAX_DIV_SPEC_200; + cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200; } - - host->cfg.voltages = 0; + cfg->voltages = 0; if (caps & SDHCI_CAN_VDD_330) - host->cfg.voltages |= MMC_VDD_32_33 | MMC_VDD_33_34; + cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34; if (caps & SDHCI_CAN_VDD_300) - host->cfg.voltages |= MMC_VDD_29_30 | MMC_VDD_30_31; + cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31; if (caps & SDHCI_CAN_VDD_180) - host->cfg.voltages |= MMC_VDD_165_195; - - if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE) - host->cfg.voltages |= host->voltages; + cfg->voltages |= MMC_VDD_165_195; - host->cfg.host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT; + cfg->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT; if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) { if (caps & SDHCI_CAN_DO_8BIT) - host->cfg.host_caps |= MMC_MODE_8BIT; + cfg->host_caps |= MMC_MODE_8BIT; } - if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) - host->cfg.host_caps &= ~(MMC_MODE_HS | MMC_MODE_HS_52MHz); - if (host->host_caps) - host->cfg.host_caps |= host->host_caps; + cfg->host_caps |= host->host_caps; + + + cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; - host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; + return 0; +} + +#ifdef CONFIG_BLK +int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg) +{ + return mmc_bind(dev, mmc, cfg); +} +#else +int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk) +{ +#ifdef CONFIG_MMC_SDMA + unsigned int caps; + + caps = sdhci_readl(host, SDHCI_CAPABILITIES); + if (!(caps & SDHCI_CAN_DO_SDMA)) { + printf("%s: Your controller doesn't support SDMA!!\n", + __func__); + return -1; + } +#endif + + if (sdhci_setup_cfg(&host->cfg, host, max_clk, min_clk)) { + printf("%s: Hardware doesn't specify base clock frequency\n", + __func__); + return -EINVAL; + } + + if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE) + host->cfg.voltages |= host->voltages; sdhci_reset(host, SDHCI_RESET_ALL); @@ -557,3 +605,4 @@ int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk) return 0; } +#endif diff --git a/drivers/mmc/sh_mmcif.c b/drivers/mmc/sh_mmcif.c index 001bf185a72..bc4b3448119 100644 --- a/drivers/mmc/sh_mmcif.c +++ b/drivers/mmc/sh_mmcif.c @@ -168,7 +168,7 @@ static int sh_mmcif_error_manage(struct sh_mmcif_host *host) if (state2 & STS2_CRC_ERR) ret = -EILSEQ; else if (state2 & STS2_TIMEOUT_ERR) - ret = TIMEOUT; + ret = -ETIMEDOUT; else ret = -EILSEQ; return ret; @@ -483,7 +483,7 @@ static int sh_mmcif_start_cmd(struct sh_mmcif_host *host, case MMC_CMD_ALL_SEND_CID: case MMC_CMD_SELECT_CARD: case MMC_CMD_APP_CMD: - ret = TIMEOUT; + ret = -ETIMEDOUT; break; default: printf(DRIVER_NAME": Cmd(d'%d) err\n", cmd->cmdidx); @@ -520,14 +520,14 @@ static int sh_mmcif_request(struct mmc *mmc, struct mmc_cmd *cmd, switch (cmd->cmdidx) { case MMC_CMD_APP_CMD: - return TIMEOUT; + return -ETIMEDOUT; case MMC_CMD_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */ if (data) /* ext_csd */ break; else /* send_if_cond cmd (not support) */ - return TIMEOUT; + return -ETIMEDOUT; default: break; } diff --git a/drivers/mmc/sh_sdhi.c b/drivers/mmc/sh_sdhi.c index e9d99a2bf83..ea82e2b449d 100644 --- a/drivers/mmc/sh_sdhi.c +++ b/drivers/mmc/sh_sdhi.c @@ -232,7 +232,7 @@ static int sh_sdhi_error_manage(struct sh_sdhi_host *host) e_state2 = sh_sdhi_readw(host, SDHI_ERR_STS2); if (e_state2 & ERR_STS2_SYS_ERROR) { if (e_state2 & ERR_STS2_RES_STOP_TIMEOUT) - ret = TIMEOUT; + ret = -ETIMEDOUT; else ret = -EILSEQ; debug("%s: ERR_STS2 = %04x\n", @@ -246,7 +246,7 @@ static int sh_sdhi_error_manage(struct sh_sdhi_host *host) if (e_state1 & ERR_STS1_CRC_ERROR || e_state1 & ERR_STS1_CMD_ERROR) ret = -EILSEQ; else - ret = TIMEOUT; + ret = -ETIMEDOUT; debug("%s: ERR_STS1 = %04x\n", DRIVER_NAME, sh_sdhi_readw(host, SDHI_ERR_STS1)); @@ -567,7 +567,7 @@ static int sh_sdhi_start_cmd(struct sh_sdhi_host *host, case MMC_CMD_SELECT_CARD: case SD_CMD_SEND_IF_COND: case MMC_CMD_APP_CMD: - ret = TIMEOUT; + ret = -ETIMEDOUT; break; default: debug(DRIVER_NAME": Cmd(d'%d) err\n", opc); diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c index 6a0e9719b8a..8a9630208c5 100644 --- a/drivers/mmc/socfpga_dw_mmc.c +++ b/drivers/mmc/socfpga_dw_mmc.c @@ -22,6 +22,11 @@ static const struct socfpga_clock_manager *clock_manager_base = static const struct socfpga_system_manager *system_manager_base = (void *)SOCFPGA_SYSMGR_ADDRESS; +struct socfpga_dwmci_plat { + struct mmc_config cfg; + struct mmc mmc; +}; + /* socfpga implmentation specific driver private data */ struct dwmci_socfpga_priv_data { struct dwmci_host host; @@ -98,21 +103,45 @@ static int socfpga_dwmmc_ofdata_to_platdata(struct udevice *dev) static int socfpga_dwmmc_probe(struct udevice *dev) { +#ifdef CONFIG_BLK + struct socfpga_dwmci_plat *plat = dev_get_platdata(dev); +#endif struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev); struct dwmci_host *host = &priv->host; + +#ifdef CONFIG_BLK + dwmci_setup_cfg(&plat->cfg, dev->name, host->buswidth, host->caps, + host->bus_hz, 400000); + host->mmc = &plat->mmc; +#else int ret; ret = add_dwmci(host, host->bus_hz, 400000); if (ret) return ret; - +#endif + host->mmc->priv = &priv->host; upriv->mmc = host->mmc; host->mmc->dev = dev; return 0; } +static int socfpga_dwmmc_bind(struct udevice *dev) +{ +#ifdef CONFIG_BLK + struct socfpga_dwmci_plat *plat = dev_get_platdata(dev); + int ret; + + ret = dwmci_bind(dev, &plat->mmc, &plat->cfg); + if (ret) + return ret; +#endif + + return 0; +} + static const struct udevice_id socfpga_dwmmc_ids[] = { { .compatible = "altr,socfpga-dw-mshc" }, { } @@ -123,6 +152,7 @@ U_BOOT_DRIVER(socfpga_dwmmc_drv) = { .id = UCLASS_MMC, .of_match = socfpga_dwmmc_ids, .ofdata_to_platdata = socfpga_dwmmc_ofdata_to_platdata, + .bind = socfpga_dwmmc_bind, .probe = socfpga_dwmmc_probe, .priv_auto_alloc_size = sizeof(struct dwmci_socfpga_priv_data), }; diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index ce2dc4ae41c..6953accce12 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -269,18 +269,18 @@ static int mmc_trans_data_by_cpu(struct mmc *mmc, struct mmc_data *data) unsigned i; unsigned *buff = (unsigned int *)(reading ? data->dest : data->src); unsigned byte_cnt = data->blocksize * data->blocks; - unsigned timeout_msecs = byte_cnt >> 8; - if (timeout_msecs < 2000) - timeout_msecs = 2000; + unsigned timeout_usecs = (byte_cnt >> 8) * 1000; + if (timeout_usecs < 2000000) + timeout_usecs = 2000000; /* Always read / write data through the CPU */ setbits_le32(&mmchost->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB); for (i = 0; i < (byte_cnt >> 2); i++) { while (readl(&mmchost->reg->status) & status_bit) { - if (!timeout_msecs--) + if (!timeout_usecs--) return -1; - udelay(1000); + udelay(1); } if (reading) @@ -304,7 +304,7 @@ static int mmc_rint_wait(struct mmc *mmc, unsigned int timeout_msecs, (status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) { debug("%s timeout %x\n", what, status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT); - return TIMEOUT; + return -ETIMEDOUT; } udelay(1000); } while (!(status & done_bit)); @@ -375,7 +375,7 @@ static int sunxi_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, if (ret) { error = readl(&mmchost->reg->rint) & \ SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT; - error = TIMEOUT; + error = -ETIMEDOUT; goto out; } } @@ -402,7 +402,7 @@ static int sunxi_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, status = readl(&mmchost->reg->status); if (!timeout_msecs--) { debug("busy timeout\n"); - error = TIMEOUT; + error = -ETIMEDOUT; goto out; } udelay(1000); @@ -445,23 +445,6 @@ static int sunxi_mmc_getcd(struct mmc *mmc) return !gpio_get_value(cd_pin); } -int sunxi_mmc_has_egon_boot_signature(struct mmc *mmc) -{ - char *buf = malloc(512); - int valid_signature = 0; - - if (buf == NULL) - panic("Failed to allocate memory\n"); - - if (mmc_getcd(mmc) && mmc_init(mmc) == 0 && - mmc->block_dev.block_read(&mmc->block_dev, 16, 1, buf) == 1 && - strncmp(&buf[4], "eGON.BT0", 8) == 0) - valid_signature = 1; - - free(buf); - return valid_signature; -} - static const struct mmc_ops sunxi_mmc_ops = { .send_cmd = sunxi_mmc_send_cmd, .set_ios = sunxi_mmc_set_ios, diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c index c9d9432e5e8..f0a39a63c64 100644 --- a/drivers/mmc/tegra_mmc.c +++ b/drivers/mmc/tegra_mmc.c @@ -9,6 +9,8 @@ #include <bouncebuf.h> #include <common.h> +#include <dm/device.h> +#include <errno.h> #include <asm/gpio.h> #include <asm/io.h> #ifndef CONFIG_TEGRA186 @@ -19,6 +21,15 @@ #include <asm/arch-tegra/tegra_mmc.h> #include <mmc.h> +/* + * FIXME: TODO: This driver contains a number of ifdef CONFIG_TEGRA186 that + * should not be present. These are needed because newer Tegra SoCs support + * only the standard clock/reset APIs, whereas older Tegra SoCs support only + * a custom Tegra-specific API. ASAP the older Tegra SoCs' code should be + * fixed to implement the standard APIs, and all drivers converted to solely + * use the new standard APIs, with no ifdefs. + */ + DECLARE_GLOBAL_DATA_PTR; struct mmc_host mmc_host[CONFIG_SYS_MMC_MAX_DEVICE]; @@ -216,14 +227,14 @@ static int mmc_send_cmd_bounced(struct mmc *mmc, struct mmc_cmd *cmd, if (i == retry) { printf("%s: waiting for status update\n", __func__); writel(mask, &host->reg->norintsts); - return TIMEOUT; + return -ETIMEDOUT; } if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) { /* Timeout Error */ debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx); writel(mask, &host->reg->norintsts); - return TIMEOUT; + return -ETIMEDOUT; } else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) { /* Error Interrupt */ debug("error: %08x cmd %d\n", mask, cmd->cmdidx); @@ -257,7 +268,7 @@ static int mmc_send_cmd_bounced(struct mmc *mmc, struct mmc_cmd *cmd, if (i == retry) { printf("%s: card is still busy\n", __func__); writel(mask, &host->reg->norintsts); - return TIMEOUT; + return -ETIMEDOUT; } cmd->response[0] = readl(&host->reg->rspreg0); @@ -359,11 +370,14 @@ static void mmc_change_clock(struct mmc_host *host, uint clock) */ if (clock == 0) goto out; -#ifndef CONFIG_TEGRA186 +#ifdef CONFIG_TEGRA186 + { + ulong rate = clk_set_rate(&host->clk, clock); + div = (rate + clock - 1) / clock; + } +#else clock_adjust_periph_pll_div(host->mmc_id, CLOCK_ID_PERIPH, clock, &div); -#else - div = (20000000 + clock - 1) / clock; #endif debug("div = %d\n", div); @@ -538,6 +552,9 @@ static int do_mmc_init(int dev_index, bool removable) { struct mmc_host *host; struct mmc *mmc; +#ifdef CONFIG_TEGRA186 + int ret; +#endif /* DT should have been read & host config filled in */ host = &mmc_host[dev_index]; @@ -549,7 +566,21 @@ static int do_mmc_init(int dev_index, bool removable) gpio_get_number(&host->cd_gpio)); host->clock = 0; -#ifndef CONFIG_TEGRA186 + +#ifdef CONFIG_TEGRA186 + ret = reset_assert(&host->reset_ctl); + if (ret) + return ret; + ret = clk_enable(&host->clk); + if (ret) + return ret; + ret = clk_set_rate(&host->clk, 20000000); + if (IS_ERR_VALUE(ret)) + return ret; + ret = reset_deassert(&host->reset_ctl); + if (ret) + return ret; +#else clock_start_periph_pll(host->mmc_id, CLOCK_ID_PERIPH, 20000000); #endif @@ -576,11 +607,7 @@ static int do_mmc_init(int dev_index, bool removable) * (actually 52MHz) */ host->cfg.f_min = 375000; -#ifndef CONFIG_TEGRA186 host->cfg.f_max = 48000000; -#else - host->cfg.f_max = 375000; -#endif host->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; @@ -612,7 +639,27 @@ static int mmc_get_config(const void *blob, int node, struct mmc_host *host, return -FDT_ERR_NOTFOUND; } -#ifndef CONFIG_TEGRA186 +#ifdef CONFIG_TEGRA186 + { + /* + * FIXME: This variable should go away when the MMC device + * actually is a udevice. + */ + struct udevice dev; + int ret; + dev.of_offset = node; + ret = reset_get_by_name(&dev, "sdmmc", &host->reset_ctl); + if (ret) { + debug("reset_get_by_index() failed: %d\n", ret); + return ret; + } + ret = clk_get_by_name(&dev, "sdmmc", &host->clk); + if (ret) { + debug("clk_get_by_index() failed: %d\n", ret); + return ret; + } + } +#else host->mmc_id = clock_decode_periph_id(blob, node); if (host->mmc_id == PERIPH_ID_NONE) { debug("%s: could not decode periph id\n", __func__); diff --git a/drivers/mmc/uniphier-sd.c b/drivers/mmc/uniphier-sd.c index 152e9873970..2a4837840a9 100644 --- a/drivers/mmc/uniphier-sd.c +++ b/drivers/mmc/uniphier-sd.c @@ -1,5 +1,6 @@ /* - * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -7,7 +8,6 @@ #include <common.h> #include <clk.h> #include <fdtdec.h> -#include <mapmem.h> #include <mmc.h> #include <dm/device.h> #include <linux/compat.h> @@ -162,7 +162,7 @@ static int uniphier_sd_check_error(struct uniphier_sd_priv *priv) * display error log since this might be a part of sequence to * distinguish between SD and MMC. */ - return TIMEOUT; + return -ETIMEDOUT; } if (info2 & UNIPHIER_SD_INFO2_ERR_TO) { @@ -660,7 +660,7 @@ int uniphier_sd_probe(struct udevice *dev) if (base == FDT_ADDR_T_NONE) return -EINVAL; - priv->regbase = map_sysmem(base, SZ_2K); + priv->regbase = devm_ioremap(dev, base, SZ_2K); if (!priv->regbase) return -ENOMEM; @@ -735,7 +735,6 @@ int uniphier_sd_remove(struct udevice *dev) { struct uniphier_sd_priv *priv = dev_get_priv(dev); - unmap_sysmem(priv->regbase); mmc_destroy(priv->mmc); return 0; diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index d405929b641..3815b943292 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -17,10 +17,17 @@ # define CONFIG_ZYNQ_SDHCI_MIN_FREQ 0 #endif +struct arasan_sdhci_plat { + struct mmc_config cfg; + struct mmc mmc; +}; + static int arasan_sdhci_probe(struct udevice *dev) { + struct arasan_sdhci_plat *plat = dev_get_platdata(dev); struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); struct sdhci_host *host = dev_get_priv(dev); + int ret; host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_BROKEN_R1B; @@ -31,13 +38,16 @@ static int arasan_sdhci_probe(struct udevice *dev) host->version = sdhci_readw(host, SDHCI_HOST_VERSION); - add_sdhci(host, CONFIG_ZYNQ_SDHCI_MAX_FREQ, - CONFIG_ZYNQ_SDHCI_MIN_FREQ); - - upriv->mmc = host->mmc; + ret = sdhci_setup_cfg(&plat->cfg, host, CONFIG_ZYNQ_SDHCI_MAX_FREQ, + CONFIG_ZYNQ_SDHCI_MIN_FREQ); + host->mmc = &plat->mmc; + if (ret) + return ret; + host->mmc->priv = host; host->mmc->dev = dev; + upriv->mmc = host->mmc; - return 0; + return sdhci_probe(dev); } static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev) @@ -50,6 +60,18 @@ static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev) return 0; } +static int arasan_sdhci_bind(struct udevice *dev) +{ + struct arasan_sdhci_plat *plat = dev_get_platdata(dev); + int ret; + + ret = sdhci_bind(dev, &plat->mmc, &plat->cfg); + if (ret) + return ret; + + return 0; +} + static const struct udevice_id arasan_sdhci_ids[] = { { .compatible = "arasan,sdhci-8.9a" }, { } @@ -60,6 +82,9 @@ U_BOOT_DRIVER(arasan_sdhci_drv) = { .id = UCLASS_MMC, .of_match = arasan_sdhci_ids, .ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata, + .ops = &sdhci_ops, + .bind = arasan_sdhci_bind, .probe = arasan_sdhci_probe, .priv_auto_alloc_size = sizeof(struct sdhci_host), + .platdata_auto_alloc_size = sizeof(struct arasan_sdhci_plat), }; diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 8ccaff0e63a..33c4a9342f8 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -608,7 +608,7 @@ static int flash_full_status_check (flash_info_t * info, flash_sect_t sector, case CFI_CMDSET_INTEL_EXTENDED: case CFI_CMDSET_INTEL_STANDARD: if ((retcode == ERR_OK) - && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) { + && !flash_isset(info, sector, 0, FLASH_STATUS_DONE)) { retcode = ERR_INVAL; printf ("Flash %s error at address %lx\n", prompt, info->start[sector]); diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 8c46a2ff8e1..5ce7d6d06ce 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -64,12 +64,14 @@ config NAND_PXA3XX PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2). config NAND_SUNXI - bool "Support for NAND on Allwinner SoCs in SPL" + bool "Support for NAND on Allwinner SoCs" depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I select SYS_NAND_SELF_INIT ---help--- - Enable support for NAND. This option allows SPL to read from - sunxi NAND using DMA transfers. + Enable support for NAND. This option enables the standard and + SPL drivers. + The SPL driver only supports reading from the NAND using DMA + transfers. config NAND_ARASAN bool "Configure Arasan Nand" diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 837d397bdaf..1df9273cdd1 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -66,6 +66,7 @@ obj-$(CONFIG_TEGRA_NAND) += tegra_nand.o obj-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o obj-$(CONFIG_NAND_OMAP_ELM) += omap_elm.o obj-$(CONFIG_NAND_PLAT) += nand_plat.o +obj-$(CONFIG_NAND_SUNXI) += sunxi_nand.o else # minimal SPL drivers diff --git a/drivers/mtd/nand/fsl_ifc_spl.c b/drivers/mtd/nand/fsl_ifc_spl.c index cbeb74a5bb8..4e49a4e1546 100644 --- a/drivers/mtd/nand/fsl_ifc_spl.c +++ b/drivers/mtd/nand/fsl_ifc_spl.c @@ -11,6 +11,9 @@ #include <asm/io.h> #include <fsl_ifc.h> #include <linux/mtd/nand.h> +#ifdef CONFIG_CHAIN_OF_TRUST +#include <fsl_validate.h> +#endif static inline int is_blank(uchar *addr, int page_size) { @@ -268,6 +271,27 @@ void nand_boot(void) */ flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE); #endif + +#ifdef CONFIG_CHAIN_OF_TRUST + /* + * U-Boot header is appended at end of U-boot image, so + * calculate U-boot header address using U-boot header size. + */ +#define CONFIG_U_BOOT_HDR_ADDR \ + ((CONFIG_SYS_NAND_U_BOOT_START + \ + CONFIG_SYS_NAND_U_BOOT_SIZE) - \ + CONFIG_U_BOOT_HDR_SIZE) + spl_validate_uboot(CONFIG_U_BOOT_HDR_ADDR, + CONFIG_SYS_NAND_U_BOOT_START); + /* + * In case of failure in validation, spl_validate_uboot would + * not return back in case of Production environment with ITS=1. + * Thus U-Boot will not start. + * In Development environment (ITS=0 and SB_EN=1), the function + * may return back in case of non-fatal failures. + */ +#endif + uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START; uboot(); } diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c index c90a3a7bd2c..94fc5c18a07 100644 --- a/drivers/mtd/nand/mxs_nand.c +++ b/drivers/mtd/nand/mxs_nand.c @@ -976,7 +976,7 @@ static int mxs_nand_block_bad(struct mtd_info *mtd, loff_t ofs) * counted, so we know the physical geometry. This enables us to make some * important configuration decisions. * - * The return value of this function propogates directly back to this driver's + * The return value of this function propagates directly back to this driver's * call to nand_scan(). Anything other than zero will cause this driver to * tear everything down and declare failure. */ diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 689716753ae..d1287bc3be9 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -29,6 +29,9 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt #include <common.h> +#if CONFIG_IS_ENABLED(OF_CONTROL) +#include <fdtdec.h> +#endif #include <malloc.h> #include <watchdog.h> #include <linux/err.h> @@ -2411,7 +2414,7 @@ static int nand_do_write_ops(struct mtd_info *mtd, loff_t to, int cached = writelen > bytes && page != blockmask; uint8_t *wbuf = buf; int use_bufpoi; - int part_pagewr = (column || writelen < (mtd->writesize - 1)); + int part_pagewr = (column || writelen < mtd->writesize); if (part_pagewr) use_bufpoi = 1; @@ -3763,6 +3766,66 @@ ident_done: return type; } +#if CONFIG_IS_ENABLED(OF_CONTROL) +DECLARE_GLOBAL_DATA_PTR; + +static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, int node) +{ + int ret, ecc_mode = -1, ecc_strength, ecc_step; + const void *blob = gd->fdt_blob; + const char *str; + + ret = fdtdec_get_int(blob, node, "nand-bus-width", -1); + if (ret == 16) + chip->options |= NAND_BUSWIDTH_16; + + if (fdtdec_get_bool(blob, node, "nand-on-flash-bbt")) + chip->bbt_options |= NAND_BBT_USE_FLASH; + + str = fdt_getprop(blob, node, "nand-ecc-mode", NULL); + if (str) { + if (!strcmp(str, "none")) + ecc_mode = NAND_ECC_NONE; + else if (!strcmp(str, "soft")) + ecc_mode = NAND_ECC_SOFT; + else if (!strcmp(str, "hw")) + ecc_mode = NAND_ECC_HW; + else if (!strcmp(str, "hw_syndrome")) + ecc_mode = NAND_ECC_HW_SYNDROME; + else if (!strcmp(str, "hw_oob_first")) + ecc_mode = NAND_ECC_HW_OOB_FIRST; + else if (!strcmp(str, "soft_bch")) + ecc_mode = NAND_ECC_SOFT_BCH; + } + + + ecc_strength = fdtdec_get_int(blob, node, "nand-ecc-strength", -1); + ecc_step = fdtdec_get_int(blob, node, "nand-ecc-step-size", -1); + + if ((ecc_step >= 0 && !(ecc_strength >= 0)) || + (!(ecc_step >= 0) && ecc_strength >= 0)) { + pr_err("must set both strength and step size in DT\n"); + return -EINVAL; + } + + if (ecc_mode >= 0) + chip->ecc.mode = ecc_mode; + + if (ecc_strength >= 0) + chip->ecc.strength = ecc_strength; + + if (ecc_step > 0) + chip->ecc.size = ecc_step; + + return 0; +} +#else +static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, int node) +{ + return 0; +} +#endif /* CONFIG_IS_ENABLED(OF_CONTROL) */ + /** * nand_scan_ident - [NAND Interface] Scan for the NAND device * @mtd: MTD device structure @@ -3779,6 +3842,13 @@ int nand_scan_ident(struct mtd_info *mtd, int maxchips, int i, nand_maf_id, nand_dev_id; struct nand_chip *chip = mtd_to_nand(mtd); struct nand_flash_dev *type; + int ret; + + if (chip->flash_node) { + ret = nand_dt_init(mtd, chip, chip->flash_node); + if (ret) + return ret; + } /* Set the default functions */ nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16); diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c index 561d2cd63bb..ce0a14e28ab 100644 --- a/drivers/mtd/nand/nand_ids.c +++ b/drivers/mtd/nand/nand_ids.c @@ -62,6 +62,10 @@ struct nand_flash_dev nand_flash_ids[] = { { .id = {0xad, 0xde, 0x94, 0xda, 0x74, 0xc4} }, SZ_8K, SZ_8K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640, NAND_ECC_INFO(40, SZ_1K), 4 }, + {"H27QCG8T2E5R‐BCF 64G 3.3V 8-bit", + { .id = {0xad, 0xde, 0x14, 0xa7, 0x42, 0x4a} }, + SZ_16K, SZ_8K, SZ_4M, NAND_NEED_SCRAMBLING, 6, 1664, + NAND_ECC_INFO(56, SZ_1K), 1 }, LEGACY_ID_NAND("NAND 4MiB 5V 8-bit", 0x6B, 4, SZ_8K, SP_OPTIONS), LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS), diff --git a/drivers/mtd/nand/nand_spl_simple.c b/drivers/mtd/nand/nand_spl_simple.c index 60a76070733..55f48d3a142 100644 --- a/drivers/mtd/nand/nand_spl_simple.c +++ b/drivers/mtd/nand/nand_spl_simple.c @@ -209,6 +209,68 @@ static int nand_read_page(int block, int page, void *dst) } #endif +#ifdef CONFIG_SPL_UBI +/* + * Temporary storage for non NAND page aligned and non NAND page sized + * reads. Note: This does not support runtime detected FLASH yet, but + * that should be reasonably easy to fix by making the buffer large + * enough :) + */ +static u8 scratch_buf[CONFIG_SYS_NAND_PAGE_SIZE]; + +/** + * nand_spl_read_block - Read data from physical eraseblock into a buffer + * @block: Number of the physical eraseblock + * @offset: Data offset from the start of @peb + * @len: Data size to read + * @dst: Address of the destination buffer + * + * This could be further optimized if we'd have a subpage read + * function in the simple code. On NAND which allows subpage reads + * this would spare quite some time to readout e.g. the VID header of + * UBI. + * + * Notes: + * @offset + @len are not allowed to be larger than a physical + * erase block. No sanity check done for simplicity reasons. + * + * To support runtime detected flash this needs to be extended by + * information about the actual flash geometry, but thats beyond the + * scope of this effort and for most applications where fast boot is + * required it is not an issue anyway. + */ +int nand_spl_read_block(int block, int offset, int len, void *dst) +{ + int page, read; + + /* Calculate the page number */ + page = offset / CONFIG_SYS_NAND_PAGE_SIZE; + + /* Offset to the start of a flash page */ + offset = offset % CONFIG_SYS_NAND_PAGE_SIZE; + + while (len) { + /* + * Non page aligned reads go to the scratch buffer. + * Page aligned reads go directly to the destination. + */ + if (offset || len < CONFIG_SYS_NAND_PAGE_SIZE) { + nand_read_page(block, page, scratch_buf); + read = min(len, CONFIG_SYS_NAND_PAGE_SIZE - offset); + memcpy(dst, scratch_buf + offset, read); + offset = 0; + } else { + nand_read_page(block, page, dst); + read = CONFIG_SYS_NAND_PAGE_SIZE; + } + page++; + len -= read; + dst += read; + } + return 0; +} +#endif + int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) { unsigned int block, lastblock; diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c index 67f293dcd01..6e201d68e51 100644 --- a/drivers/mtd/nand/omap_gpmc.c +++ b/drivers/mtd/nand/omap_gpmc.c @@ -264,7 +264,8 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, { struct nand_chip *chip = mtd_to_nand(mtd); struct omap_nand_info *info = nand_get_controller_data(chip); - uint32_t *ptr, val = 0; + const uint32_t *ptr; + uint32_t val = 0; int8_t i = 0, j; switch (info->ecc_scheme) { diff --git a/drivers/mtd/nand/sunxi_nand.c b/drivers/mtd/nand/sunxi_nand.c new file mode 100644 index 00000000000..c4e2cd7f552 --- /dev/null +++ b/drivers/mtd/nand/sunxi_nand.c @@ -0,0 +1,1845 @@ +/* + * Copyright (C) 2013 Boris BREZILLON <b.brezillon.dev@gmail.com> + * Copyright (C) 2015 Roy Spliet <r.spliet@ultimaker.com> + * + * Derived from: + * https://github.com/yuq/sunxi-nfc-mtd + * Copyright (C) 2013 Qiang Yu <yuq825@gmail.com> + * + * https://github.com/hno/Allwinner-Info + * Copyright (C) 2013 Henrik Nordström <Henrik Nordström> + * + * Copyright (C) 2013 Dmitriy B. <rzk333@gmail.com> + * Copyright (C) 2013 Sergey Lapin <slapin@ossfans.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <fdtdec.h> +#include <memalign.h> +#include <nand.h> + +#include <linux/kernel.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/nand.h> +#include <linux/mtd/partitions.h> +#include <linux/io.h> + +#include <asm/gpio.h> +#include <asm/arch/clock.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define NFC_REG_CTL 0x0000 +#define NFC_REG_ST 0x0004 +#define NFC_REG_INT 0x0008 +#define NFC_REG_TIMING_CTL 0x000C +#define NFC_REG_TIMING_CFG 0x0010 +#define NFC_REG_ADDR_LOW 0x0014 +#define NFC_REG_ADDR_HIGH 0x0018 +#define NFC_REG_SECTOR_NUM 0x001C +#define NFC_REG_CNT 0x0020 +#define NFC_REG_CMD 0x0024 +#define NFC_REG_RCMD_SET 0x0028 +#define NFC_REG_WCMD_SET 0x002C +#define NFC_REG_IO_DATA 0x0030 +#define NFC_REG_ECC_CTL 0x0034 +#define NFC_REG_ECC_ST 0x0038 +#define NFC_REG_DEBUG 0x003C +#define NFC_REG_ECC_ERR_CNT(x) ((0x0040 + (x)) & ~0x3) +#define NFC_REG_USER_DATA(x) (0x0050 + ((x) * 4)) +#define NFC_REG_SPARE_AREA 0x00A0 +#define NFC_REG_PAT_ID 0x00A4 +#define NFC_RAM0_BASE 0x0400 +#define NFC_RAM1_BASE 0x0800 + +/* define bit use in NFC_CTL */ +#define NFC_EN BIT(0) +#define NFC_RESET BIT(1) +#define NFC_BUS_WIDTH_MSK BIT(2) +#define NFC_BUS_WIDTH_8 (0 << 2) +#define NFC_BUS_WIDTH_16 (1 << 2) +#define NFC_RB_SEL_MSK BIT(3) +#define NFC_RB_SEL(x) ((x) << 3) +#define NFC_CE_SEL_MSK (0x7 << 24) +#define NFC_CE_SEL(x) ((x) << 24) +#define NFC_CE_CTL BIT(6) +#define NFC_PAGE_SHIFT_MSK (0xf << 8) +#define NFC_PAGE_SHIFT(x) (((x) < 10 ? 0 : (x) - 10) << 8) +#define NFC_SAM BIT(12) +#define NFC_RAM_METHOD BIT(14) +#define NFC_DEBUG_CTL BIT(31) + +/* define bit use in NFC_ST */ +#define NFC_RB_B2R BIT(0) +#define NFC_CMD_INT_FLAG BIT(1) +#define NFC_DMA_INT_FLAG BIT(2) +#define NFC_CMD_FIFO_STATUS BIT(3) +#define NFC_STA BIT(4) +#define NFC_NATCH_INT_FLAG BIT(5) +#define NFC_RB_STATE(x) BIT(x + 8) + +/* define bit use in NFC_INT */ +#define NFC_B2R_INT_ENABLE BIT(0) +#define NFC_CMD_INT_ENABLE BIT(1) +#define NFC_DMA_INT_ENABLE BIT(2) +#define NFC_INT_MASK (NFC_B2R_INT_ENABLE | \ + NFC_CMD_INT_ENABLE | \ + NFC_DMA_INT_ENABLE) + +/* define bit use in NFC_TIMING_CTL */ +#define NFC_TIMING_CTL_EDO BIT(8) + +/* define NFC_TIMING_CFG register layout */ +#define NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD) \ + (((tWB) & 0x3) | (((tADL) & 0x3) << 2) | \ + (((tWHR) & 0x3) << 4) | (((tRHW) & 0x3) << 6) | \ + (((tCAD) & 0x7) << 8)) + +/* define bit use in NFC_CMD */ +#define NFC_CMD_LOW_BYTE_MSK 0xff +#define NFC_CMD_HIGH_BYTE_MSK (0xff << 8) +#define NFC_CMD(x) (x) +#define NFC_ADR_NUM_MSK (0x7 << 16) +#define NFC_ADR_NUM(x) (((x) - 1) << 16) +#define NFC_SEND_ADR BIT(19) +#define NFC_ACCESS_DIR BIT(20) +#define NFC_DATA_TRANS BIT(21) +#define NFC_SEND_CMD1 BIT(22) +#define NFC_WAIT_FLAG BIT(23) +#define NFC_SEND_CMD2 BIT(24) +#define NFC_SEQ BIT(25) +#define NFC_DATA_SWAP_METHOD BIT(26) +#define NFC_ROW_AUTO_INC BIT(27) +#define NFC_SEND_CMD3 BIT(28) +#define NFC_SEND_CMD4 BIT(29) +#define NFC_CMD_TYPE_MSK (0x3 << 30) +#define NFC_NORMAL_OP (0 << 30) +#define NFC_ECC_OP (1 << 30) +#define NFC_PAGE_OP (2 << 30) + +/* define bit use in NFC_RCMD_SET */ +#define NFC_READ_CMD_MSK 0xff +#define NFC_RND_READ_CMD0_MSK (0xff << 8) +#define NFC_RND_READ_CMD1_MSK (0xff << 16) + +/* define bit use in NFC_WCMD_SET */ +#define NFC_PROGRAM_CMD_MSK 0xff +#define NFC_RND_WRITE_CMD_MSK (0xff << 8) +#define NFC_READ_CMD0_MSK (0xff << 16) +#define NFC_READ_CMD1_MSK (0xff << 24) + +/* define bit use in NFC_ECC_CTL */ +#define NFC_ECC_EN BIT(0) +#define NFC_ECC_PIPELINE BIT(3) +#define NFC_ECC_EXCEPTION BIT(4) +#define NFC_ECC_BLOCK_SIZE_MSK BIT(5) +#define NFC_ECC_BLOCK_512 (1 << 5) +#define NFC_RANDOM_EN BIT(9) +#define NFC_RANDOM_DIRECTION BIT(10) +#define NFC_ECC_MODE_MSK (0xf << 12) +#define NFC_ECC_MODE(x) ((x) << 12) +#define NFC_RANDOM_SEED_MSK (0x7fff << 16) +#define NFC_RANDOM_SEED(x) ((x) << 16) + +/* define bit use in NFC_ECC_ST */ +#define NFC_ECC_ERR(x) BIT(x) +#define NFC_ECC_PAT_FOUND(x) BIT(x + 16) +#define NFC_ECC_ERR_CNT(b, x) (((x) >> ((b) * 8)) & 0xff) + +#define NFC_DEFAULT_TIMEOUT_MS 1000 + +#define NFC_SRAM_SIZE 1024 + +#define NFC_MAX_CS 7 + +/* + * Ready/Busy detection type: describes the Ready/Busy detection modes + * + * @RB_NONE: no external detection available, rely on STATUS command + * and software timeouts + * @RB_NATIVE: use sunxi NAND controller Ready/Busy support. The Ready/Busy + * pin of the NAND flash chip must be connected to one of the + * native NAND R/B pins (those which can be muxed to the NAND + * Controller) + * @RB_GPIO: use a simple GPIO to handle Ready/Busy status. The Ready/Busy + * pin of the NAND flash chip must be connected to a GPIO capable + * pin. + */ +enum sunxi_nand_rb_type { + RB_NONE, + RB_NATIVE, + RB_GPIO, +}; + +/* + * Ready/Busy structure: stores information related to Ready/Busy detection + * + * @type: the Ready/Busy detection mode + * @info: information related to the R/B detection mode. Either a gpio + * id or a native R/B id (those supported by the NAND controller). + */ +struct sunxi_nand_rb { + enum sunxi_nand_rb_type type; + union { + struct gpio_desc gpio; + int nativeid; + } info; +}; + +/* + * Chip Select structure: stores information related to NAND Chip Select + * + * @cs: the NAND CS id used to communicate with a NAND Chip + * @rb: the Ready/Busy description + */ +struct sunxi_nand_chip_sel { + u8 cs; + struct sunxi_nand_rb rb; +}; + +/* + * sunxi HW ECC infos: stores information related to HW ECC support + * + * @mode: the sunxi ECC mode field deduced from ECC requirements + * @layout: the OOB layout depending on the ECC requirements and the + * selected ECC mode + */ +struct sunxi_nand_hw_ecc { + int mode; + struct nand_ecclayout layout; +}; + +/* + * NAND chip structure: stores NAND chip device related information + * + * @node: used to store NAND chips into a list + * @nand: base NAND chip structure + * @mtd: base MTD structure + * @clk_rate: clk_rate required for this NAND chip + * @timing_cfg TIMING_CFG register value for this NAND chip + * @selected: current active CS + * @nsels: number of CS lines required by the NAND chip + * @sels: array of CS lines descriptions + */ +struct sunxi_nand_chip { + struct list_head node; + struct nand_chip nand; + unsigned long clk_rate; + u32 timing_cfg; + u32 timing_ctl; + int selected; + int addr_cycles; + u32 addr[2]; + int cmd_cycles; + u8 cmd[2]; + int nsels; + struct sunxi_nand_chip_sel sels[0]; +}; + +static inline struct sunxi_nand_chip *to_sunxi_nand(struct nand_chip *nand) +{ + return container_of(nand, struct sunxi_nand_chip, nand); +} + +/* + * NAND Controller structure: stores sunxi NAND controller information + * + * @controller: base controller structure + * @dev: parent device (used to print error messages) + * @regs: NAND controller registers + * @ahb_clk: NAND Controller AHB clock + * @mod_clk: NAND Controller mod clock + * @assigned_cs: bitmask describing already assigned CS lines + * @clk_rate: NAND controller current clock rate + * @chips: a list containing all the NAND chips attached to + * this NAND controller + * @complete: a completion object used to wait for NAND + * controller events + */ +struct sunxi_nfc { + struct nand_hw_control controller; + struct device *dev; + void __iomem *regs; + struct clk *ahb_clk; + struct clk *mod_clk; + unsigned long assigned_cs; + unsigned long clk_rate; + struct list_head chips; +}; + +static inline struct sunxi_nfc *to_sunxi_nfc(struct nand_hw_control *ctrl) +{ + return container_of(ctrl, struct sunxi_nfc, controller); +} + +static void sunxi_nfc_set_clk_rate(unsigned long hz) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + int div_m, div_n; + + div_m = (clock_get_pll6() + hz - 1) / hz; + for (div_n = 0; div_n < 3 && div_m > 16; div_n++) { + if (div_m % 2) + div_m++; + div_m >>= 1; + } + if (div_m > 16) + div_m = 16; + + /* config mod clock */ + writel(CCM_NAND_CTRL_ENABLE | CCM_NAND_CTRL_PLL6 | + CCM_NAND_CTRL_N(div_n) | CCM_NAND_CTRL_M(div_m), + &ccm->nand0_clk_cfg); + + /* gate on nand clock */ + setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_NAND0)); +#ifdef CONFIG_MACH_SUN9I + setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA)); +#else + setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA)); +#endif +} + +static int sunxi_nfc_wait_int(struct sunxi_nfc *nfc, u32 flags, + unsigned int timeout_ms) +{ + unsigned int timeout_ticks; + u32 time_start, status; + int ret = -ETIMEDOUT; + + if (!timeout_ms) + timeout_ms = NFC_DEFAULT_TIMEOUT_MS; + + timeout_ticks = (timeout_ms * CONFIG_SYS_HZ) / 1000; + + time_start = get_timer(0); + + do { + status = readl(nfc->regs + NFC_REG_ST); + if ((status & flags) == flags) { + ret = 0; + break; + } + + udelay(1); + } while (get_timer(time_start) < timeout_ticks); + + writel(status & flags, nfc->regs + NFC_REG_ST); + + return ret; +} + +static int sunxi_nfc_wait_cmd_fifo_empty(struct sunxi_nfc *nfc) +{ + unsigned long timeout = (CONFIG_SYS_HZ * + NFC_DEFAULT_TIMEOUT_MS) / 1000; + u32 time_start; + + time_start = get_timer(0); + do { + if (!(readl(nfc->regs + NFC_REG_ST) & NFC_CMD_FIFO_STATUS)) + return 0; + } while (get_timer(time_start) < timeout); + + dev_err(nfc->dev, "wait for empty cmd FIFO timedout\n"); + return -ETIMEDOUT; +} + +static int sunxi_nfc_rst(struct sunxi_nfc *nfc) +{ + unsigned long timeout = (CONFIG_SYS_HZ * + NFC_DEFAULT_TIMEOUT_MS) / 1000; + u32 time_start; + + writel(0, nfc->regs + NFC_REG_ECC_CTL); + writel(NFC_RESET, nfc->regs + NFC_REG_CTL); + + time_start = get_timer(0); + do { + if (!(readl(nfc->regs + NFC_REG_CTL) & NFC_RESET)) + return 0; + } while (get_timer(time_start) < timeout); + + dev_err(nfc->dev, "wait for NAND controller reset timedout\n"); + return -ETIMEDOUT; +} + +static int sunxi_nfc_dev_ready(struct mtd_info *mtd) +{ + struct nand_chip *nand = mtd_to_nand(mtd); + struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand); + struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller); + struct sunxi_nand_rb *rb; + unsigned long timeo = (sunxi_nand->nand.state == FL_ERASING ? 400 : 20); + int ret; + + if (sunxi_nand->selected < 0) + return 0; + + rb = &sunxi_nand->sels[sunxi_nand->selected].rb; + + switch (rb->type) { + case RB_NATIVE: + ret = !!(readl(nfc->regs + NFC_REG_ST) & + NFC_RB_STATE(rb->info.nativeid)); + if (ret) + break; + + sunxi_nfc_wait_int(nfc, NFC_RB_B2R, timeo); + ret = !!(readl(nfc->regs + NFC_REG_ST) & + NFC_RB_STATE(rb->info.nativeid)); + break; + case RB_GPIO: + ret = dm_gpio_get_value(&rb->info.gpio); + break; + case RB_NONE: + default: + ret = 0; + dev_err(nfc->dev, "cannot check R/B NAND status!\n"); + break; + } + + return ret; +} + +static void sunxi_nfc_select_chip(struct mtd_info *mtd, int chip) +{ + struct nand_chip *nand = mtd_to_nand(mtd); + struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand); + struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller); + struct sunxi_nand_chip_sel *sel; + u32 ctl; + + if (chip > 0 && chip >= sunxi_nand->nsels) + return; + + if (chip == sunxi_nand->selected) + return; + + ctl = readl(nfc->regs + NFC_REG_CTL) & + ~(NFC_PAGE_SHIFT_MSK | NFC_CE_SEL_MSK | NFC_RB_SEL_MSK | NFC_EN); + + if (chip >= 0) { + sel = &sunxi_nand->sels[chip]; + + ctl |= NFC_CE_SEL(sel->cs) | NFC_EN | + NFC_PAGE_SHIFT(nand->page_shift - 10); + if (sel->rb.type == RB_NONE) { + nand->dev_ready = NULL; + } else { + nand->dev_ready = sunxi_nfc_dev_ready; + if (sel->rb.type == RB_NATIVE) + ctl |= NFC_RB_SEL(sel->rb.info.nativeid); + } + + writel(mtd->writesize, nfc->regs + NFC_REG_SPARE_AREA); + + if (nfc->clk_rate != sunxi_nand->clk_rate) { + sunxi_nfc_set_clk_rate(sunxi_nand->clk_rate); + nfc->clk_rate = sunxi_nand->clk_rate; + } + } + + writel(sunxi_nand->timing_ctl, nfc->regs + NFC_REG_TIMING_CTL); + writel(sunxi_nand->timing_cfg, nfc->regs + NFC_REG_TIMING_CFG); + writel(ctl, nfc->regs + NFC_REG_CTL); + + sunxi_nand->selected = chip; +} + +static void sunxi_nfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) +{ + struct nand_chip *nand = mtd_to_nand(mtd); + struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand); + struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller); + int ret; + int cnt; + int offs = 0; + u32 tmp; + + while (len > offs) { + cnt = min(len - offs, NFC_SRAM_SIZE); + + ret = sunxi_nfc_wait_cmd_fifo_empty(nfc); + if (ret) + break; + + writel(cnt, nfc->regs + NFC_REG_CNT); + tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD; + writel(tmp, nfc->regs + NFC_REG_CMD); + + ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0); + if (ret) + break; + + if (buf) + memcpy_fromio(buf + offs, nfc->regs + NFC_RAM0_BASE, + cnt); + offs += cnt; + } +} + +static void sunxi_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, + int len) +{ + struct nand_chip *nand = mtd_to_nand(mtd); + struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand); + struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller); + int ret; + int cnt; + int offs = 0; + u32 tmp; + + while (len > offs) { + cnt = min(len - offs, NFC_SRAM_SIZE); + + ret = sunxi_nfc_wait_cmd_fifo_empty(nfc); + if (ret) + break; + + writel(cnt, nfc->regs + NFC_REG_CNT); + memcpy_toio(nfc->regs + NFC_RAM0_BASE, buf + offs, cnt); + tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | + NFC_ACCESS_DIR; + writel(tmp, nfc->regs + NFC_REG_CMD); + + ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0); + if (ret) + break; + + offs += cnt; + } +} + +static uint8_t sunxi_nfc_read_byte(struct mtd_info *mtd) +{ + uint8_t ret; + + sunxi_nfc_read_buf(mtd, &ret, 1); + + return ret; +} + +static void sunxi_nfc_cmd_ctrl(struct mtd_info *mtd, int dat, + unsigned int ctrl) +{ + struct nand_chip *nand = mtd_to_nand(mtd); + struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(nand); + struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller); + int ret; + u32 tmp; + + ret = sunxi_nfc_wait_cmd_fifo_empty(nfc); + if (ret) + return; + + if (ctrl & NAND_CTRL_CHANGE) { + tmp = readl(nfc->regs + NFC_REG_CTL); + if (ctrl & NAND_NCE) + tmp |= NFC_CE_CTL; + else + tmp &= ~NFC_CE_CTL; + writel(tmp, nfc->regs + NFC_REG_CTL); + } + + if (dat == NAND_CMD_NONE && (ctrl & NAND_NCE) && + !(ctrl & (NAND_CLE | NAND_ALE))) { + u32 cmd = 0; + + if (!sunxi_nand->addr_cycles && !sunxi_nand->cmd_cycles) + return; + + if (sunxi_nand->cmd_cycles--) + cmd |= NFC_SEND_CMD1 | sunxi_nand->cmd[0]; + + if (sunxi_nand->cmd_cycles--) { + cmd |= NFC_SEND_CMD2; + writel(sunxi_nand->cmd[1], + nfc->regs + NFC_REG_RCMD_SET); + } + + sunxi_nand->cmd_cycles = 0; + + if (sunxi_nand->addr_cycles) { + cmd |= NFC_SEND_ADR | + NFC_ADR_NUM(sunxi_nand->addr_cycles); + writel(sunxi_nand->addr[0], + nfc->regs + NFC_REG_ADDR_LOW); + } + + if (sunxi_nand->addr_cycles > 4) + writel(sunxi_nand->addr[1], + nfc->regs + NFC_REG_ADDR_HIGH); + + writel(cmd, nfc->regs + NFC_REG_CMD); + sunxi_nand->addr[0] = 0; + sunxi_nand->addr[1] = 0; + sunxi_nand->addr_cycles = 0; + sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0); + } + + if (ctrl & NAND_CLE) { + sunxi_nand->cmd[sunxi_nand->cmd_cycles++] = dat; + } else if (ctrl & NAND_ALE) { + sunxi_nand->addr[sunxi_nand->addr_cycles / 4] |= + dat << ((sunxi_nand->addr_cycles % 4) * 8); + sunxi_nand->addr_cycles++; + } +} + +/* These seed values have been extracted from Allwinner's BSP */ +static const u16 sunxi_nfc_randomizer_page_seeds[] = { + 0x2b75, 0x0bd0, 0x5ca3, 0x62d1, 0x1c93, 0x07e9, 0x2162, 0x3a72, + 0x0d67, 0x67f9, 0x1be7, 0x077d, 0x032f, 0x0dac, 0x2716, 0x2436, + 0x7922, 0x1510, 0x3860, 0x5287, 0x480f, 0x4252, 0x1789, 0x5a2d, + 0x2a49, 0x5e10, 0x437f, 0x4b4e, 0x2f45, 0x216e, 0x5cb7, 0x7130, + 0x2a3f, 0x60e4, 0x4dc9, 0x0ef0, 0x0f52, 0x1bb9, 0x6211, 0x7a56, + 0x226d, 0x4ea7, 0x6f36, 0x3692, 0x38bf, 0x0c62, 0x05eb, 0x4c55, + 0x60f4, 0x728c, 0x3b6f, 0x2037, 0x7f69, 0x0936, 0x651a, 0x4ceb, + 0x6218, 0x79f3, 0x383f, 0x18d9, 0x4f05, 0x5c82, 0x2912, 0x6f17, + 0x6856, 0x5938, 0x1007, 0x61ab, 0x3e7f, 0x57c2, 0x542f, 0x4f62, + 0x7454, 0x2eac, 0x7739, 0x42d4, 0x2f90, 0x435a, 0x2e52, 0x2064, + 0x637c, 0x66ad, 0x2c90, 0x0bad, 0x759c, 0x0029, 0x0986, 0x7126, + 0x1ca7, 0x1605, 0x386a, 0x27f5, 0x1380, 0x6d75, 0x24c3, 0x0f8e, + 0x2b7a, 0x1418, 0x1fd1, 0x7dc1, 0x2d8e, 0x43af, 0x2267, 0x7da3, + 0x4e3d, 0x1338, 0x50db, 0x454d, 0x764d, 0x40a3, 0x42e6, 0x262b, + 0x2d2e, 0x1aea, 0x2e17, 0x173d, 0x3a6e, 0x71bf, 0x25f9, 0x0a5d, + 0x7c57, 0x0fbe, 0x46ce, 0x4939, 0x6b17, 0x37bb, 0x3e91, 0x76db, +}; + +/* + * sunxi_nfc_randomizer_ecc512_seeds and sunxi_nfc_randomizer_ecc1024_seeds + * have been generated using + * sunxi_nfc_randomizer_step(seed, (step_size * 8) + 15), which is what + * the randomizer engine does internally before de/scrambling OOB data. + * + * Those tables are statically defined to avoid calculating randomizer state + * at runtime. + */ +static const u16 sunxi_nfc_randomizer_ecc512_seeds[] = { + 0x3346, 0x367f, 0x1f18, 0x769a, 0x4f64, 0x068c, 0x2ef1, 0x6b64, + 0x28a9, 0x15d7, 0x30f8, 0x3659, 0x53db, 0x7c5f, 0x71d4, 0x4409, + 0x26eb, 0x03cc, 0x655d, 0x47d4, 0x4daa, 0x0877, 0x712d, 0x3617, + 0x3264, 0x49aa, 0x7f9e, 0x588e, 0x4fbc, 0x7176, 0x7f91, 0x6c6d, + 0x4b95, 0x5fb7, 0x3844, 0x4037, 0x0184, 0x081b, 0x0ee8, 0x5b91, + 0x293d, 0x1f71, 0x0e6f, 0x402b, 0x5122, 0x1e52, 0x22be, 0x3d2d, + 0x75bc, 0x7c60, 0x6291, 0x1a2f, 0x61d4, 0x74aa, 0x4140, 0x29ab, + 0x472d, 0x2852, 0x017e, 0x15e8, 0x5ec2, 0x17cf, 0x7d0f, 0x06b8, + 0x117a, 0x6b94, 0x789b, 0x3126, 0x6ac5, 0x5be7, 0x150f, 0x51f8, + 0x7889, 0x0aa5, 0x663d, 0x77e8, 0x0b87, 0x3dcb, 0x360d, 0x218b, + 0x512f, 0x7dc9, 0x6a4d, 0x630a, 0x3547, 0x1dd2, 0x5aea, 0x69a5, + 0x7bfa, 0x5e4f, 0x1519, 0x6430, 0x3a0e, 0x5eb3, 0x5425, 0x0c7a, + 0x5540, 0x3670, 0x63c1, 0x31e9, 0x5a39, 0x2de7, 0x5979, 0x2891, + 0x1562, 0x014b, 0x5b05, 0x2756, 0x5a34, 0x13aa, 0x6cb5, 0x2c36, + 0x5e72, 0x1306, 0x0861, 0x15ef, 0x1ee8, 0x5a37, 0x7ac4, 0x45dd, + 0x44c4, 0x7266, 0x2f41, 0x3ccc, 0x045e, 0x7d40, 0x7c66, 0x0fa0, +}; + +static const u16 sunxi_nfc_randomizer_ecc1024_seeds[] = { + 0x2cf5, 0x35f1, 0x63a4, 0x5274, 0x2bd2, 0x778b, 0x7285, 0x32b6, + 0x6a5c, 0x70d6, 0x757d, 0x6769, 0x5375, 0x1e81, 0x0cf3, 0x3982, + 0x6787, 0x042a, 0x6c49, 0x1925, 0x56a8, 0x40a9, 0x063e, 0x7bd9, + 0x4dbf, 0x55ec, 0x672e, 0x7334, 0x5185, 0x4d00, 0x232a, 0x7e07, + 0x445d, 0x6b92, 0x528f, 0x4255, 0x53ba, 0x7d82, 0x2a2e, 0x3a4e, + 0x75eb, 0x450c, 0x6844, 0x1b5d, 0x581a, 0x4cc6, 0x0379, 0x37b2, + 0x419f, 0x0e92, 0x6b27, 0x5624, 0x01e3, 0x07c1, 0x44a5, 0x130c, + 0x13e8, 0x5910, 0x0876, 0x60c5, 0x54e3, 0x5b7f, 0x2269, 0x509f, + 0x7665, 0x36fd, 0x3e9a, 0x0579, 0x6295, 0x14ef, 0x0a81, 0x1bcc, + 0x4b16, 0x64db, 0x0514, 0x4f07, 0x0591, 0x3576, 0x6853, 0x0d9e, + 0x259f, 0x38b7, 0x64fb, 0x3094, 0x4693, 0x6ddd, 0x29bb, 0x0bc8, + 0x3f47, 0x490e, 0x0c0e, 0x7933, 0x3c9e, 0x5840, 0x398d, 0x3e68, + 0x4af1, 0x71f5, 0x57cf, 0x1121, 0x64eb, 0x3579, 0x15ac, 0x584d, + 0x5f2a, 0x47e2, 0x6528, 0x6eac, 0x196e, 0x6b96, 0x0450, 0x0179, + 0x609c, 0x06e1, 0x4626, 0x42c7, 0x273e, 0x486f, 0x0705, 0x1601, + 0x145b, 0x407e, 0x062b, 0x57a5, 0x53f9, 0x5659, 0x4410, 0x3ccd, +}; + +static u16 sunxi_nfc_randomizer_step(u16 state, int count) +{ + state &= 0x7fff; + + /* + * This loop is just a simple implementation of a Fibonacci LFSR using + * the x16 + x15 + 1 polynomial. + */ + while (count--) + state = ((state >> 1) | + (((state ^ (state >> 1)) & 1) << 14)) & 0x7fff; + + return state; +} + +static u16 sunxi_nfc_randomizer_state(struct mtd_info *mtd, int page, bool ecc) +{ + const u16 *seeds = sunxi_nfc_randomizer_page_seeds; + int mod = mtd->erasesize / mtd->writesize; + + if (mod > ARRAY_SIZE(sunxi_nfc_randomizer_page_seeds)) + mod = ARRAY_SIZE(sunxi_nfc_randomizer_page_seeds); + + if (ecc) { + if (mtd->ecc_step_size == 512) + seeds = sunxi_nfc_randomizer_ecc512_seeds; + else + seeds = sunxi_nfc_randomizer_ecc1024_seeds; + } + + return seeds[page % mod]; +} + +static void sunxi_nfc_randomizer_config(struct mtd_info *mtd, + int page, bool ecc) +{ + struct nand_chip *nand = mtd_to_nand(mtd); + struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller); + u32 ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL); + u16 state; + + if (!(nand->options & NAND_NEED_SCRAMBLING)) + return; + + ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL); + state = sunxi_nfc_randomizer_state(mtd, page, ecc); + ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_RANDOM_SEED_MSK; + writel(ecc_ctl | NFC_RANDOM_SEED(state), nfc->regs + NFC_REG_ECC_CTL); +} + +static void sunxi_nfc_randomizer_enable(struct mtd_info *mtd) +{ + struct nand_chip *nand = mtd_to_nand(mtd); + struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller); + + if (!(nand->options & NAND_NEED_SCRAMBLING)) + return; + + writel(readl(nfc->regs + NFC_REG_ECC_CTL) | NFC_RANDOM_EN, + nfc->regs + NFC_REG_ECC_CTL); +} + +static void sunxi_nfc_randomizer_disable(struct mtd_info *mtd) +{ + struct nand_chip *nand = mtd_to_nand(mtd); + struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller); + + if (!(nand->options & NAND_NEED_SCRAMBLING)) + return; + + writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_RANDOM_EN, + nfc->regs + NFC_REG_ECC_CTL); +} + +static void sunxi_nfc_randomize_bbm(struct mtd_info *mtd, int page, u8 *bbm) +{ + u16 state = sunxi_nfc_randomizer_state(mtd, page, true); + + bbm[0] ^= state; + bbm[1] ^= sunxi_nfc_randomizer_step(state, 8); +} + +static void sunxi_nfc_randomizer_write_buf(struct mtd_info *mtd, + const uint8_t *buf, int len, + bool ecc, int page) +{ + sunxi_nfc_randomizer_config(mtd, page, ecc); + sunxi_nfc_randomizer_enable(mtd); + sunxi_nfc_write_buf(mtd, buf, len); + sunxi_nfc_randomizer_disable(mtd); +} + +static void sunxi_nfc_randomizer_read_buf(struct mtd_info *mtd, uint8_t *buf, + int len, bool ecc, int page) +{ + sunxi_nfc_randomizer_config(mtd, page, ecc); + sunxi_nfc_randomizer_enable(mtd); + sunxi_nfc_read_buf(mtd, buf, len); + sunxi_nfc_randomizer_disable(mtd); +} + +static void sunxi_nfc_hw_ecc_enable(struct mtd_info *mtd) +{ + struct nand_chip *nand = mtd_to_nand(mtd); + struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller); + struct sunxi_nand_hw_ecc *data = nand->ecc.priv; + u32 ecc_ctl; + + ecc_ctl = readl(nfc->regs + NFC_REG_ECC_CTL); + ecc_ctl &= ~(NFC_ECC_MODE_MSK | NFC_ECC_PIPELINE | + NFC_ECC_BLOCK_SIZE_MSK); + ecc_ctl |= NFC_ECC_EN | NFC_ECC_MODE(data->mode) | NFC_ECC_EXCEPTION; + + if (nand->ecc.size == 512) + ecc_ctl |= NFC_ECC_BLOCK_512; + + writel(ecc_ctl, nfc->regs + NFC_REG_ECC_CTL); +} + +static void sunxi_nfc_hw_ecc_disable(struct mtd_info *mtd) +{ + struct nand_chip *nand = mtd_to_nand(mtd); + struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller); + + writel(readl(nfc->regs + NFC_REG_ECC_CTL) & ~NFC_ECC_EN, + nfc->regs + NFC_REG_ECC_CTL); +} + +static inline void sunxi_nfc_user_data_to_buf(u32 user_data, u8 *buf) +{ + buf[0] = user_data; + buf[1] = user_data >> 8; + buf[2] = user_data >> 16; + buf[3] = user_data >> 24; +} + +static int sunxi_nfc_hw_ecc_read_chunk(struct mtd_info *mtd, + u8 *data, int data_off, + u8 *oob, int oob_off, + int *cur_off, + unsigned int *max_bitflips, + bool bbm, int page) +{ + struct nand_chip *nand = mtd_to_nand(mtd); + struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller); + struct nand_ecc_ctrl *ecc = &nand->ecc; + int raw_mode = 0; + u32 status; + int ret; + + if (*cur_off != data_off) + nand->cmdfunc(mtd, NAND_CMD_RNDOUT, data_off, -1); + + sunxi_nfc_randomizer_read_buf(mtd, NULL, ecc->size, false, page); + + if (data_off + ecc->size != oob_off) + nand->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_off, -1); + + ret = sunxi_nfc_wait_cmd_fifo_empty(nfc); + if (ret) + return ret; + + sunxi_nfc_randomizer_enable(mtd); + writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | NFC_ECC_OP, + nfc->regs + NFC_REG_CMD); + + ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0); + sunxi_nfc_randomizer_disable(mtd); + if (ret) + return ret; + + *cur_off = oob_off + ecc->bytes + 4; + + status = readl(nfc->regs + NFC_REG_ECC_ST); + if (status & NFC_ECC_PAT_FOUND(0)) { + u8 pattern = 0xff; + + if (unlikely(!(readl(nfc->regs + NFC_REG_PAT_ID) & 0x1))) + pattern = 0x0; + + memset(data, pattern, ecc->size); + memset(oob, pattern, ecc->bytes + 4); + + return 1; + } + + ret = NFC_ECC_ERR_CNT(0, readl(nfc->regs + NFC_REG_ECC_ERR_CNT(0))); + + memcpy_fromio(data, nfc->regs + NFC_RAM0_BASE, ecc->size); + + nand->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_off, -1); + sunxi_nfc_randomizer_read_buf(mtd, oob, ecc->bytes + 4, true, page); + + if (status & NFC_ECC_ERR(0)) { + /* + * Re-read the data with the randomizer disabled to identify + * bitflips in erased pages. + */ + if (nand->options & NAND_NEED_SCRAMBLING) { + nand->cmdfunc(mtd, NAND_CMD_RNDOUT, data_off, -1); + nand->read_buf(mtd, data, ecc->size); + nand->cmdfunc(mtd, NAND_CMD_RNDOUT, oob_off, -1); + nand->read_buf(mtd, oob, ecc->bytes + 4); + } + + ret = nand_check_erased_ecc_chunk(data, ecc->size, + oob, ecc->bytes + 4, + NULL, 0, ecc->strength); + if (ret >= 0) + raw_mode = 1; + } else { + /* + * The engine protects 4 bytes of OOB data per chunk. + * Retrieve the corrected OOB bytes. + */ + sunxi_nfc_user_data_to_buf(readl(nfc->regs + + NFC_REG_USER_DATA(0)), + oob); + + /* De-randomize the Bad Block Marker. */ + if (bbm && nand->options & NAND_NEED_SCRAMBLING) + sunxi_nfc_randomize_bbm(mtd, page, oob); + } + + if (ret < 0) { + mtd->ecc_stats.failed++; + } else { + mtd->ecc_stats.corrected += ret; + *max_bitflips = max_t(unsigned int, *max_bitflips, ret); + } + + return raw_mode; +} + +static void sunxi_nfc_hw_ecc_read_extra_oob(struct mtd_info *mtd, + u8 *oob, int *cur_off, + bool randomize, int page) +{ + struct nand_chip *nand = mtd_to_nand(mtd); + struct nand_ecc_ctrl *ecc = &nand->ecc; + int offset = ((ecc->bytes + 4) * ecc->steps); + int len = mtd->oobsize - offset; + + if (len <= 0) + return; + + if (*cur_off != offset) + nand->cmdfunc(mtd, NAND_CMD_RNDOUT, + offset + mtd->writesize, -1); + + if (!randomize) + sunxi_nfc_read_buf(mtd, oob + offset, len); + else + sunxi_nfc_randomizer_read_buf(mtd, oob + offset, len, + false, page); + + *cur_off = mtd->oobsize + mtd->writesize; +} + +static inline u32 sunxi_nfc_buf_to_user_data(const u8 *buf) +{ + return buf[0] | (buf[1] << 8) | (buf[2] << 16) | (buf[3] << 24); +} + +static int sunxi_nfc_hw_ecc_write_chunk(struct mtd_info *mtd, + const u8 *data, int data_off, + const u8 *oob, int oob_off, + int *cur_off, bool bbm, + int page) +{ + struct nand_chip *nand = mtd_to_nand(mtd); + struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller); + struct nand_ecc_ctrl *ecc = &nand->ecc; + int ret; + + if (data_off != *cur_off) + nand->cmdfunc(mtd, NAND_CMD_RNDIN, data_off, -1); + + sunxi_nfc_randomizer_write_buf(mtd, data, ecc->size, false, page); + + /* Fill OOB data in */ + if ((nand->options & NAND_NEED_SCRAMBLING) && bbm) { + u8 user_data[4]; + + memcpy(user_data, oob, 4); + sunxi_nfc_randomize_bbm(mtd, page, user_data); + writel(sunxi_nfc_buf_to_user_data(user_data), + nfc->regs + NFC_REG_USER_DATA(0)); + } else { + writel(sunxi_nfc_buf_to_user_data(oob), + nfc->regs + NFC_REG_USER_DATA(0)); + } + + if (data_off + ecc->size != oob_off) + nand->cmdfunc(mtd, NAND_CMD_RNDIN, oob_off, -1); + + ret = sunxi_nfc_wait_cmd_fifo_empty(nfc); + if (ret) + return ret; + + sunxi_nfc_randomizer_enable(mtd); + writel(NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | + NFC_ACCESS_DIR | NFC_ECC_OP, + nfc->regs + NFC_REG_CMD); + + ret = sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0); + sunxi_nfc_randomizer_disable(mtd); + if (ret) + return ret; + + *cur_off = oob_off + ecc->bytes + 4; + + return 0; +} + +static void sunxi_nfc_hw_ecc_write_extra_oob(struct mtd_info *mtd, + u8 *oob, int *cur_off, + int page) +{ + struct nand_chip *nand = mtd_to_nand(mtd); + struct nand_ecc_ctrl *ecc = &nand->ecc; + int offset = ((ecc->bytes + 4) * ecc->steps); + int len = mtd->oobsize - offset; + + if (len <= 0) + return; + + if (*cur_off != offset) + nand->cmdfunc(mtd, NAND_CMD_RNDIN, + offset + mtd->writesize, -1); + + sunxi_nfc_randomizer_write_buf(mtd, oob + offset, len, false, page); + + *cur_off = mtd->oobsize + mtd->writesize; +} + +static int sunxi_nfc_hw_ecc_read_page(struct mtd_info *mtd, + struct nand_chip *chip, uint8_t *buf, + int oob_required, int page) +{ + struct nand_ecc_ctrl *ecc = &chip->ecc; + unsigned int max_bitflips = 0; + int ret, i, cur_off = 0; + bool raw_mode = false; + + sunxi_nfc_hw_ecc_enable(mtd); + + for (i = 0; i < ecc->steps; i++) { + int data_off = i * ecc->size; + int oob_off = i * (ecc->bytes + 4); + u8 *data = buf + data_off; + u8 *oob = chip->oob_poi + oob_off; + + ret = sunxi_nfc_hw_ecc_read_chunk(mtd, data, data_off, oob, + oob_off + mtd->writesize, + &cur_off, &max_bitflips, + !i, page); + if (ret < 0) + return ret; + else if (ret) + raw_mode = true; + } + + if (oob_required) + sunxi_nfc_hw_ecc_read_extra_oob(mtd, chip->oob_poi, &cur_off, + !raw_mode, page); + + sunxi_nfc_hw_ecc_disable(mtd); + + return max_bitflips; +} + +static int sunxi_nfc_hw_ecc_read_subpage(struct mtd_info *mtd, + struct nand_chip *chip, + uint32_t data_offs, uint32_t readlen, + uint8_t *bufpoi, int page) +{ + struct nand_ecc_ctrl *ecc = &chip->ecc; + int ret, i, cur_off = 0; + unsigned int max_bitflips = 0; + + sunxi_nfc_hw_ecc_enable(mtd); + + chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page); + for (i = data_offs / ecc->size; + i < DIV_ROUND_UP(data_offs + readlen, ecc->size); i++) { + int data_off = i * ecc->size; + int oob_off = i * (ecc->bytes + 4); + u8 *data = bufpoi + data_off; + u8 *oob = chip->oob_poi + oob_off; + + ret = sunxi_nfc_hw_ecc_read_chunk(mtd, data, data_off, + oob, oob_off + mtd->writesize, + &cur_off, &max_bitflips, !i, page); + if (ret < 0) + return ret; + } + + sunxi_nfc_hw_ecc_disable(mtd); + + return max_bitflips; +} + +static int sunxi_nfc_hw_ecc_write_page(struct mtd_info *mtd, + struct nand_chip *chip, + const uint8_t *buf, int oob_required, + int page) +{ + struct nand_ecc_ctrl *ecc = &chip->ecc; + int ret, i, cur_off = 0; + + sunxi_nfc_hw_ecc_enable(mtd); + + for (i = 0; i < ecc->steps; i++) { + int data_off = i * ecc->size; + int oob_off = i * (ecc->bytes + 4); + const u8 *data = buf + data_off; + const u8 *oob = chip->oob_poi + oob_off; + + ret = sunxi_nfc_hw_ecc_write_chunk(mtd, data, data_off, oob, + oob_off + mtd->writesize, + &cur_off, !i, page); + if (ret) + return ret; + } + + if (oob_required || (chip->options & NAND_NEED_SCRAMBLING)) + sunxi_nfc_hw_ecc_write_extra_oob(mtd, chip->oob_poi, + &cur_off, page); + + sunxi_nfc_hw_ecc_disable(mtd); + + return 0; +} + +static int sunxi_nfc_hw_ecc_write_subpage(struct mtd_info *mtd, + struct nand_chip *chip, + u32 data_offs, u32 data_len, + const u8 *buf, int oob_required, + int page) +{ + struct nand_ecc_ctrl *ecc = &chip->ecc; + int ret, i, cur_off = 0; + + sunxi_nfc_hw_ecc_enable(mtd); + + for (i = data_offs / ecc->size; + i < DIV_ROUND_UP(data_offs + data_len, ecc->size); i++) { + int data_off = i * ecc->size; + int oob_off = i * (ecc->bytes + 4); + const u8 *data = buf + data_off; + const u8 *oob = chip->oob_poi + oob_off; + + ret = sunxi_nfc_hw_ecc_write_chunk(mtd, data, data_off, oob, + oob_off + mtd->writesize, + &cur_off, !i, page); + if (ret) + return ret; + } + + sunxi_nfc_hw_ecc_disable(mtd); + + return 0; +} + +static int sunxi_nfc_hw_syndrome_ecc_read_page(struct mtd_info *mtd, + struct nand_chip *chip, + uint8_t *buf, int oob_required, + int page) +{ + struct nand_ecc_ctrl *ecc = &chip->ecc; + unsigned int max_bitflips = 0; + int ret, i, cur_off = 0; + bool raw_mode = false; + + sunxi_nfc_hw_ecc_enable(mtd); + + for (i = 0; i < ecc->steps; i++) { + int data_off = i * (ecc->size + ecc->bytes + 4); + int oob_off = data_off + ecc->size; + u8 *data = buf + (i * ecc->size); + u8 *oob = chip->oob_poi + (i * (ecc->bytes + 4)); + + ret = sunxi_nfc_hw_ecc_read_chunk(mtd, data, data_off, oob, + oob_off, &cur_off, + &max_bitflips, !i, page); + if (ret < 0) + return ret; + else if (ret) + raw_mode = true; + } + + if (oob_required) + sunxi_nfc_hw_ecc_read_extra_oob(mtd, chip->oob_poi, &cur_off, + !raw_mode, page); + + sunxi_nfc_hw_ecc_disable(mtd); + + return max_bitflips; +} + +static int sunxi_nfc_hw_syndrome_ecc_write_page(struct mtd_info *mtd, + struct nand_chip *chip, + const uint8_t *buf, + int oob_required, int page) +{ + struct nand_ecc_ctrl *ecc = &chip->ecc; + int ret, i, cur_off = 0; + + sunxi_nfc_hw_ecc_enable(mtd); + + for (i = 0; i < ecc->steps; i++) { + int data_off = i * (ecc->size + ecc->bytes + 4); + int oob_off = data_off + ecc->size; + const u8 *data = buf + (i * ecc->size); + const u8 *oob = chip->oob_poi + (i * (ecc->bytes + 4)); + + ret = sunxi_nfc_hw_ecc_write_chunk(mtd, data, data_off, + oob, oob_off, &cur_off, + false, page); + if (ret) + return ret; + } + + if (oob_required || (chip->options & NAND_NEED_SCRAMBLING)) + sunxi_nfc_hw_ecc_write_extra_oob(mtd, chip->oob_poi, + &cur_off, page); + + sunxi_nfc_hw_ecc_disable(mtd); + + return 0; +} + +static const s32 tWB_lut[] = {6, 12, 16, 20}; +static const s32 tRHW_lut[] = {4, 8, 12, 20}; + +static int _sunxi_nand_lookup_timing(const s32 *lut, int lut_size, u32 duration, + u32 clk_period) +{ + u32 clk_cycles = DIV_ROUND_UP(duration, clk_period); + int i; + + for (i = 0; i < lut_size; i++) { + if (clk_cycles <= lut[i]) + return i; + } + + /* Doesn't fit */ + return -EINVAL; +} + +#define sunxi_nand_lookup_timing(l, p, c) \ + _sunxi_nand_lookup_timing(l, ARRAY_SIZE(l), p, c) + +static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip, + const struct nand_sdr_timings *timings) +{ + u32 min_clk_period = 0; + s32 tWB, tADL, tWHR, tRHW, tCAD; + + /* T1 <=> tCLS */ + if (timings->tCLS_min > min_clk_period) + min_clk_period = timings->tCLS_min; + + /* T2 <=> tCLH */ + if (timings->tCLH_min > min_clk_period) + min_clk_period = timings->tCLH_min; + + /* T3 <=> tCS */ + if (timings->tCS_min > min_clk_period) + min_clk_period = timings->tCS_min; + + /* T4 <=> tCH */ + if (timings->tCH_min > min_clk_period) + min_clk_period = timings->tCH_min; + + /* T5 <=> tWP */ + if (timings->tWP_min > min_clk_period) + min_clk_period = timings->tWP_min; + + /* T6 <=> tWH */ + if (timings->tWH_min > min_clk_period) + min_clk_period = timings->tWH_min; + + /* T7 <=> tALS */ + if (timings->tALS_min > min_clk_period) + min_clk_period = timings->tALS_min; + + /* T8 <=> tDS */ + if (timings->tDS_min > min_clk_period) + min_clk_period = timings->tDS_min; + + /* T9 <=> tDH */ + if (timings->tDH_min > min_clk_period) + min_clk_period = timings->tDH_min; + + /* T10 <=> tRR */ + if (timings->tRR_min > (min_clk_period * 3)) + min_clk_period = DIV_ROUND_UP(timings->tRR_min, 3); + + /* T11 <=> tALH */ + if (timings->tALH_min > min_clk_period) + min_clk_period = timings->tALH_min; + + /* T12 <=> tRP */ + if (timings->tRP_min > min_clk_period) + min_clk_period = timings->tRP_min; + + /* T13 <=> tREH */ + if (timings->tREH_min > min_clk_period) + min_clk_period = timings->tREH_min; + + /* T14 <=> tRC */ + if (timings->tRC_min > (min_clk_period * 2)) + min_clk_period = DIV_ROUND_UP(timings->tRC_min, 2); + + /* T15 <=> tWC */ + if (timings->tWC_min > (min_clk_period * 2)) + min_clk_period = DIV_ROUND_UP(timings->tWC_min, 2); + + /* T16 - T19 + tCAD */ + tWB = sunxi_nand_lookup_timing(tWB_lut, timings->tWB_max, + min_clk_period); + if (tWB < 0) { + dev_err(nfc->dev, "unsupported tWB\n"); + return tWB; + } + + tADL = DIV_ROUND_UP(timings->tADL_min, min_clk_period) >> 3; + if (tADL > 3) { + dev_err(nfc->dev, "unsupported tADL\n"); + return -EINVAL; + } + + tWHR = DIV_ROUND_UP(timings->tWHR_min, min_clk_period) >> 3; + if (tWHR > 3) { + dev_err(nfc->dev, "unsupported tWHR\n"); + return -EINVAL; + } + + tRHW = sunxi_nand_lookup_timing(tRHW_lut, timings->tRHW_min, + min_clk_period); + if (tRHW < 0) { + dev_err(nfc->dev, "unsupported tRHW\n"); + return tRHW; + } + + /* + * TODO: according to ONFI specs this value only applies for DDR NAND, + * but Allwinner seems to set this to 0x7. Mimic them for now. + */ + tCAD = 0x7; + + /* TODO: A83 has some more bits for CDQSS, CS, CLHZ, CCS, WC */ + chip->timing_cfg = NFC_TIMING_CFG(tWB, tADL, tWHR, tRHW, tCAD); + + /* + * ONFI specification 3.1, paragraph 4.15.2 dictates that EDO data + * output cycle timings shall be used if the host drives tRC less than + * 30 ns. + */ + chip->timing_ctl = (timings->tRC_min < 30000) ? NFC_TIMING_CTL_EDO : 0; + + /* Convert min_clk_period from picoseconds to nanoseconds */ + min_clk_period = DIV_ROUND_UP(min_clk_period, 1000); + + /* + * Convert min_clk_period into a clk frequency, then get the + * appropriate rate for the NAND controller IP given this formula + * (specified in the datasheet): + * nand clk_rate = min_clk_rate + */ + chip->clk_rate = 1000000000L / min_clk_period; + + return 0; +} + +static int sunxi_nand_chip_init_timings(struct sunxi_nand_chip *chip) +{ + struct mtd_info *mtd = nand_to_mtd(&chip->nand); + const struct nand_sdr_timings *timings; + int ret; + int mode; + + mode = onfi_get_async_timing_mode(&chip->nand); + if (mode == ONFI_TIMING_MODE_UNKNOWN) { + mode = chip->nand.onfi_timing_mode_default; + } else { + uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {}; + int i; + + mode = fls(mode) - 1; + if (mode < 0) + mode = 0; + + feature[0] = mode; + for (i = 0; i < chip->nsels; i++) { + chip->nand.select_chip(mtd, i); + ret = chip->nand.onfi_set_features(mtd, + &chip->nand, + ONFI_FEATURE_ADDR_TIMING_MODE, + feature); + chip->nand.select_chip(mtd, -1); + if (ret) + return ret; + } + } + + timings = onfi_async_timing_mode_to_sdr_timings(mode); + if (IS_ERR(timings)) + return PTR_ERR(timings); + + return sunxi_nand_chip_set_timings(chip, timings); +} + +static int sunxi_nand_hw_common_ecc_ctrl_init(struct mtd_info *mtd, + struct nand_ecc_ctrl *ecc) +{ + static const u8 strengths[] = { 16, 24, 28, 32, 40, 48, 56, 60, 64 }; + struct sunxi_nand_hw_ecc *data; + struct nand_ecclayout *layout; + int nsectors; + int ret; + int i; + + data = kzalloc(sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + if (ecc->size != 512 && ecc->size != 1024) + return -EINVAL; + + /* Prefer 1k ECC chunk over 512 ones */ + if (ecc->size == 512 && mtd->writesize > 512) { + ecc->size = 1024; + ecc->strength *= 2; + } + + /* Add ECC info retrieval from DT */ + for (i = 0; i < ARRAY_SIZE(strengths); i++) { + if (ecc->strength <= strengths[i]) + break; + } + + if (i >= ARRAY_SIZE(strengths)) { + dev_err(nfc->dev, "unsupported strength\n"); + ret = -ENOTSUPP; + goto err; + } + + data->mode = i; + + /* HW ECC always request ECC bytes for 1024 bytes blocks */ + ecc->bytes = DIV_ROUND_UP(ecc->strength * fls(8 * 1024), 8); + + /* HW ECC always work with even numbers of ECC bytes */ + ecc->bytes = ALIGN(ecc->bytes, 2); + + layout = &data->layout; + nsectors = mtd->writesize / ecc->size; + + if (mtd->oobsize < ((ecc->bytes + 4) * nsectors)) { + ret = -EINVAL; + goto err; + } + + layout->eccbytes = (ecc->bytes * nsectors); + + ecc->layout = layout; + ecc->priv = data; + + return 0; + +err: + kfree(data); + + return ret; +} + +#ifndef __UBOOT__ +static void sunxi_nand_hw_common_ecc_ctrl_cleanup(struct nand_ecc_ctrl *ecc) +{ + kfree(ecc->priv); +} +#endif /* __UBOOT__ */ + +static int sunxi_nand_hw_ecc_ctrl_init(struct mtd_info *mtd, + struct nand_ecc_ctrl *ecc) +{ + struct nand_ecclayout *layout; + int nsectors; + int i, j; + int ret; + + ret = sunxi_nand_hw_common_ecc_ctrl_init(mtd, ecc); + if (ret) + return ret; + + ecc->read_page = sunxi_nfc_hw_ecc_read_page; + ecc->write_page = sunxi_nfc_hw_ecc_write_page; + ecc->read_subpage = sunxi_nfc_hw_ecc_read_subpage; + ecc->write_subpage = sunxi_nfc_hw_ecc_write_subpage; + layout = ecc->layout; + nsectors = mtd->writesize / ecc->size; + + for (i = 0; i < nsectors; i++) { + if (i) { + layout->oobfree[i].offset = + layout->oobfree[i - 1].offset + + layout->oobfree[i - 1].length + + ecc->bytes; + layout->oobfree[i].length = 4; + } else { + /* + * The first 2 bytes are used for BB markers, hence we + * only have 2 bytes available in the first user data + * section. + */ + layout->oobfree[i].length = 2; + layout->oobfree[i].offset = 2; + } + + for (j = 0; j < ecc->bytes; j++) + layout->eccpos[(ecc->bytes * i) + j] = + layout->oobfree[i].offset + + layout->oobfree[i].length + j; + } + + if (mtd->oobsize > (ecc->bytes + 4) * nsectors) { + layout->oobfree[nsectors].offset = + layout->oobfree[nsectors - 1].offset + + layout->oobfree[nsectors - 1].length + + ecc->bytes; + layout->oobfree[nsectors].length = mtd->oobsize - + ((ecc->bytes + 4) * nsectors); + } + + return 0; +} + +static int sunxi_nand_hw_syndrome_ecc_ctrl_init(struct mtd_info *mtd, + struct nand_ecc_ctrl *ecc) +{ + struct nand_ecclayout *layout; + int nsectors; + int i; + int ret; + + ret = sunxi_nand_hw_common_ecc_ctrl_init(mtd, ecc); + if (ret) + return ret; + + ecc->prepad = 4; + ecc->read_page = sunxi_nfc_hw_syndrome_ecc_read_page; + ecc->write_page = sunxi_nfc_hw_syndrome_ecc_write_page; + + layout = ecc->layout; + nsectors = mtd->writesize / ecc->size; + + for (i = 0; i < (ecc->bytes * nsectors); i++) + layout->eccpos[i] = i; + + layout->oobfree[0].length = mtd->oobsize - i; + layout->oobfree[0].offset = i; + + return 0; +} + +#ifndef __UBOOT__ +static void sunxi_nand_ecc_cleanup(struct nand_ecc_ctrl *ecc) +{ + switch (ecc->mode) { + case NAND_ECC_HW: + case NAND_ECC_HW_SYNDROME: + sunxi_nand_hw_common_ecc_ctrl_cleanup(ecc); + break; + case NAND_ECC_NONE: + kfree(ecc->layout); + default: + break; + } +} +#endif /* __UBOOT__ */ + +static int sunxi_nand_ecc_init(struct mtd_info *mtd, struct nand_ecc_ctrl *ecc) +{ + struct nand_chip *nand = mtd_to_nand(mtd); + int ret; + + if (!ecc->size) { + ecc->size = nand->ecc_step_ds; + ecc->strength = nand->ecc_strength_ds; + } + + if (!ecc->size || !ecc->strength) + return -EINVAL; + + switch (ecc->mode) { + case NAND_ECC_SOFT_BCH: + break; + case NAND_ECC_HW: + ret = sunxi_nand_hw_ecc_ctrl_init(mtd, ecc); + if (ret) + return ret; + break; + case NAND_ECC_HW_SYNDROME: + ret = sunxi_nand_hw_syndrome_ecc_ctrl_init(mtd, ecc); + if (ret) + return ret; + break; + case NAND_ECC_NONE: + ecc->layout = kzalloc(sizeof(*ecc->layout), GFP_KERNEL); + if (!ecc->layout) + return -ENOMEM; + ecc->layout->oobfree[0].length = mtd->oobsize; + case NAND_ECC_SOFT: + break; + default: + return -EINVAL; + } + + return 0; +} + +static int sunxi_nand_chip_init(int node, struct sunxi_nfc *nfc, int devnum) +{ + const struct nand_sdr_timings *timings; + const void *blob = gd->fdt_blob; + struct sunxi_nand_chip *chip; + struct mtd_info *mtd; + struct nand_chip *nand; + int nsels; + int ret; + int i; + u32 cs[8], rb[8]; + + if (!fdt_getprop(blob, node, "reg", &nsels)) + return -EINVAL; + + nsels /= sizeof(u32); + if (!nsels || nsels > 8) { + dev_err(dev, "invalid reg property size\n"); + return -EINVAL; + } + + chip = kzalloc(sizeof(*chip) + + (nsels * sizeof(struct sunxi_nand_chip_sel)), + GFP_KERNEL); + if (!chip) { + dev_err(dev, "could not allocate chip\n"); + return -ENOMEM; + } + + chip->nsels = nsels; + chip->selected = -1; + + for (i = 0; i < nsels; i++) { + cs[i] = -1; + rb[i] = -1; + } + + ret = fdtdec_get_int_array(gd->fdt_blob, node, "reg", cs, nsels); + if (ret) { + dev_err(dev, "could not retrieve reg property: %d\n", ret); + return ret; + } + + ret = fdtdec_get_int_array(gd->fdt_blob, node, "allwinner,rb", rb, + nsels); + if (ret) { + dev_err(dev, "could not retrieve reg property: %d\n", ret); + return ret; + } + + for (i = 0; i < nsels; i++) { + int tmp = cs[i]; + + if (tmp > NFC_MAX_CS) { + dev_err(dev, + "invalid reg value: %u (max CS = 7)\n", + tmp); + return -EINVAL; + } + + if (test_and_set_bit(tmp, &nfc->assigned_cs)) { + dev_err(dev, "CS %d already assigned\n", tmp); + return -EINVAL; + } + + chip->sels[i].cs = tmp; + + tmp = rb[i]; + if (tmp >= 0 && tmp < 2) { + chip->sels[i].rb.type = RB_NATIVE; + chip->sels[i].rb.info.nativeid = tmp; + } else { + ret = gpio_request_by_name_nodev(blob, node, + "rb-gpios", i, + &chip->sels[i].rb.info.gpio, + GPIOD_IS_IN); + if (ret) + chip->sels[i].rb.type = RB_GPIO; + else + chip->sels[i].rb.type = RB_NONE; + } + } + + timings = onfi_async_timing_mode_to_sdr_timings(0); + if (IS_ERR(timings)) { + ret = PTR_ERR(timings); + dev_err(dev, + "could not retrieve timings for ONFI mode 0: %d\n", + ret); + return ret; + } + + ret = sunxi_nand_chip_set_timings(chip, timings); + if (ret) { + dev_err(dev, "could not configure chip timings: %d\n", ret); + return ret; + } + + nand = &chip->nand; + /* Default tR value specified in the ONFI spec (chapter 4.15.1) */ + nand->chip_delay = 200; + nand->controller = &nfc->controller; + /* + * Set the ECC mode to the default value in case nothing is specified + * in the DT. + */ + nand->ecc.mode = NAND_ECC_HW; + nand->flash_node = node; + nand->select_chip = sunxi_nfc_select_chip; + nand->cmd_ctrl = sunxi_nfc_cmd_ctrl; + nand->read_buf = sunxi_nfc_read_buf; + nand->write_buf = sunxi_nfc_write_buf; + nand->read_byte = sunxi_nfc_read_byte; + + mtd = nand_to_mtd(nand); + ret = nand_scan_ident(mtd, nsels, NULL); + if (ret) + return ret; + + if (nand->bbt_options & NAND_BBT_USE_FLASH) + nand->bbt_options |= NAND_BBT_NO_OOB; + + if (nand->options & NAND_NEED_SCRAMBLING) + nand->options |= NAND_NO_SUBPAGE_WRITE; + + nand->options |= NAND_SUBPAGE_READ; + + ret = sunxi_nand_chip_init_timings(chip); + if (ret) { + dev_err(dev, "could not configure chip timings: %d\n", ret); + return ret; + } + + ret = sunxi_nand_ecc_init(mtd, &nand->ecc); + if (ret) { + dev_err(dev, "ECC init failed: %d\n", ret); + return ret; + } + + ret = nand_scan_tail(mtd); + if (ret) { + dev_err(dev, "nand_scan_tail failed: %d\n", ret); + return ret; + } + + ret = nand_register(devnum, mtd); + if (ret) { + dev_err(dev, "failed to register mtd device: %d\n", ret); + return ret; + } + + list_add_tail(&chip->node, &nfc->chips); + + return 0; +} + +static int sunxi_nand_chips_init(int node, struct sunxi_nfc *nfc) +{ + const void *blob = gd->fdt_blob; + int nand_node; + int ret, i = 0; + + for (nand_node = fdt_first_subnode(blob, node); nand_node >= 0; + nand_node = fdt_next_subnode(blob, nand_node)) + i++; + + if (i > 8) { + dev_err(dev, "too many NAND chips: %d (max = 8)\n", i); + return -EINVAL; + } + + i = 0; + for (nand_node = fdt_first_subnode(blob, node); nand_node >= 0; + nand_node = fdt_next_subnode(blob, nand_node)) { + ret = sunxi_nand_chip_init(nand_node, nfc, i++); + if (ret) + return ret; + } + + return 0; +} + +#ifndef __UBOOT__ +static void sunxi_nand_chips_cleanup(struct sunxi_nfc *nfc) +{ + struct sunxi_nand_chip *chip; + + while (!list_empty(&nfc->chips)) { + chip = list_first_entry(&nfc->chips, struct sunxi_nand_chip, + node); + nand_release(&chip->mtd); + sunxi_nand_ecc_cleanup(&chip->nand.ecc); + list_del(&chip->node); + kfree(chip); + } +} +#endif /* __UBOOT__ */ + +void sunxi_nand_init(void) +{ + const void *blob = gd->fdt_blob; + struct sunxi_nfc *nfc; + fdt_addr_t regs; + int node; + int ret; + + nfc = kzalloc(sizeof(*nfc), GFP_KERNEL); + if (!nfc) + return; + + spin_lock_init(&nfc->controller.lock); + init_waitqueue_head(&nfc->controller.wq); + INIT_LIST_HEAD(&nfc->chips); + + node = fdtdec_next_compatible(blob, 0, COMPAT_SUNXI_NAND); + if (node < 0) { + pr_err("unable to find nfc node in device tree\n"); + goto err; + } + + if (!fdtdec_get_is_enabled(blob, node)) { + pr_err("nfc disabled in device tree\n"); + goto err; + } + + regs = fdtdec_get_addr(blob, node, "reg"); + if (regs == FDT_ADDR_T_NONE) { + pr_err("unable to find nfc address in device tree\n"); + goto err; + } + + nfc->regs = (void *)regs; + + ret = sunxi_nfc_rst(nfc); + if (ret) + goto err; + + ret = sunxi_nand_chips_init(node, nfc); + if (ret) { + dev_err(dev, "failed to init nand chips\n"); + goto err; + } + + return; + +err: + kfree(nfc); +} + +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Boris BREZILLON"); +MODULE_DESCRIPTION("Allwinner NAND Flash Controller driver"); diff --git a/drivers/mtd/nand/tegra_nand.c b/drivers/mtd/nand/tegra_nand.c index 2032f658129..38bd7a5578b 100644 --- a/drivers/mtd/nand/tegra_nand.c +++ b/drivers/mtd/nand/tegra_nand.c @@ -884,7 +884,7 @@ static void setup_timing(unsigned timing[FDT_NAND_TIMING_COUNT], * Decode NAND parameters from the device tree * * @param blob Device tree blob - * @param node Node containing "nand-flash" compatble node + * @param node Node containing "nand-flash" compatible node * @return 0 if ok, -ve on error (FDT_ERR_...) */ static int fdt_decode_nand(const void *blob, int node, struct fdt_nand *config) diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c index 03deabce102..0e35dc5b88f 100644 --- a/drivers/mtd/onenand/onenand_base.c +++ b/drivers/mtd/onenand/onenand_base.c @@ -20,6 +20,7 @@ */ #include <common.h> +#include <watchdog.h> #include <linux/compat.h> #include <linux/mtd/mtd.h> #include "linux/mtd/flashchip.h" @@ -467,15 +468,18 @@ static int onenand_read_ecc(struct onenand_chip *this) static int onenand_wait(struct mtd_info *mtd, int state) { struct onenand_chip *this = mtd->priv; - unsigned int flags = ONENAND_INT_MASTER; unsigned int interrupt = 0; unsigned int ctrl; - while (1) { + /* Wait at most 20ms ... */ + u32 timeo = (CONFIG_SYS_HZ * 20) / 1000; + u32 time_start = get_timer(0); + do { + WATCHDOG_RESET(); + if (get_timer(time_start) > timeo) + return -EIO; interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT); - if (interrupt & flags) - break; - } + } while ((interrupt & ONENAND_INT_MASTER) == 0); ctrl = this->read_word(this->base + ONENAND_REG_CTRL_STATUS); @@ -1154,15 +1158,18 @@ int onenand_read_oob(struct mtd_info *mtd, loff_t from, static int onenand_bbt_wait(struct mtd_info *mtd, int state) { struct onenand_chip *this = mtd->priv; - unsigned int flags = ONENAND_INT_MASTER; unsigned int interrupt; unsigned int ctrl; - while (1) { + /* Wait at most 20ms ... */ + u32 timeo = (CONFIG_SYS_HZ * 20) / 1000; + u32 time_start = get_timer(0); + do { + WATCHDOG_RESET(); + if (get_timer(time_start) > timeo) + return ONENAND_BBT_READ_FATAL_ERROR; interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT); - if (interrupt & flags) - break; - } + } while ((interrupt & ONENAND_INT_MASTER) == 0); /* To get correct interrupt status in timeout case */ interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT); @@ -2536,7 +2543,8 @@ static int onenand_chip_probe(struct mtd_info *mtd) this->write_word(ONENAND_CMD_RESET, this->base + ONENAND_BOOTRAM); /* Wait reset */ - this->wait(mtd, FL_RESETING); + if (this->wait(mtd, FL_RESETING)) + return -ENXIO; /* Restore system configuration 1 */ this->write_word(syscfg, this->base + ONENAND_REG_SYS_CFG1); @@ -2649,6 +2657,7 @@ int onenand_probe(struct mtd_info *mtd) mtd->_sync = onenand_sync; mtd->_block_isbad = onenand_block_isbad; mtd->_block_markbad = onenand_block_markbad; + mtd->writebufsize = mtd->writesize; return 0; } diff --git a/drivers/mtd/onenand/onenand_spl.c b/drivers/mtd/onenand/onenand_spl.c index fe6b7d923cc..1925f41d8a2 100644 --- a/drivers/mtd/onenand/onenand_spl.c +++ b/drivers/mtd/onenand/onenand_spl.c @@ -93,6 +93,54 @@ static int onenand_spl_read_page(uint32_t block, uint32_t page, uint32_t *buf, return 0; } +#ifdef CONFIG_SPL_UBI +/* Temporary storage for non page aligned and non page sized reads. */ +static u8 scratch_buf[PAGE_4K]; + +/** + * onenand_spl_read_block - Read data from physical eraseblock into a buffer + * @block: Number of the physical eraseblock + * @offset: Data offset from the start of @peb + * @len: Data size to read + * @dst: Address of the destination buffer + * + * Notes: + * @offset + @len are not allowed to be larger than a physical + * erase block. No sanity check done for simplicity reasons. + */ +int onenand_spl_read_block(int block, int offset, int len, void *dst) +{ + int page, read, psize; + + psize = onenand_spl_get_geometry(); + /* Calculate the page number */ + page = offset / psize; + /* Offset to the start of a flash page */ + offset = offset % psize; + + while (len) { + /* + * Non page aligned reads go to the scratch buffer. + * Page aligned reads go directly to the destination. + */ + if (offset || len < psize) { + onenand_spl_read_page(block, page, + (uint32_t *)scratch_buf, psize); + read = min(len, psize - offset); + memcpy(dst, scratch_buf + offset, read); + offset = 0; + } else { + onenand_spl_read_page(block, page, dst, psize); + read = psize; + } + page++; + len -= read; + dst += read; + } + return 0; +} +#endif + void onenand_spl_load_image(uint32_t offs, uint32_t size, void *dst) { uint32_t *addr = (uint32_t *)dst; diff --git a/drivers/mtd/onenand/onenand_uboot.c b/drivers/mtd/onenand/onenand_uboot.c index ae60c3bb71d..c15ec9df079 100644 --- a/drivers/mtd/onenand/onenand_uboot.c +++ b/drivers/mtd/onenand/onenand_uboot.c @@ -24,33 +24,33 @@ static __attribute__((unused)) char dev_name[] = "onenand0"; void onenand_init(void) { + int err = 0; memset(&onenand_mtd, 0, sizeof(struct mtd_info)); memset(&onenand_chip, 0, sizeof(struct onenand_chip)); onenand_mtd.priv = &onenand_chip; #ifdef CONFIG_USE_ONENAND_BOARD_INIT - /* - * It's used for some board init required - */ - onenand_board_init(&onenand_mtd); + /* It's used for some board init required */ + err = onenand_board_init(&onenand_mtd); #else onenand_chip.base = (void *) CONFIG_SYS_ONENAND_BASE; #endif - onenand_scan(&onenand_mtd, 1); + if (!err && !(onenand_scan(&onenand_mtd, 1))) { - if (onenand_chip.device_id & DEVICE_IS_FLEXONENAND) - puts("Flex-"); - puts("OneNAND: "); - print_size(onenand_chip.chipsize, "\n"); + if (onenand_chip.device_id & DEVICE_IS_FLEXONENAND) + puts("Flex-"); + puts("OneNAND: "); #ifdef CONFIG_MTD_DEVICE - /* - * Add MTD device so that we can reference it later - * via the mtdcore infrastructure (e.g. ubi). - */ - onenand_mtd.name = dev_name; - add_mtd_device(&onenand_mtd); + /* + * Add MTD device so that we can reference it later + * via the mtdcore infrastructure (e.g. ubi). + */ + onenand_mtd.name = dev_name; + add_mtd_device(&onenand_mtd); #endif + } + print_size(onenand_chip.chipsize, "\n"); } diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index 3f7433cbc21..1f23c8e34e6 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -128,4 +128,16 @@ config SPI_FLASH_MTD If unsure, say N +if SPL + +config SPL_SPI_SUNXI + bool "Support for SPI Flash on Allwinner SoCs in SPL" + depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_H3 || MACH_SUN50I + ---help--- + Enable support for SPI Flash. This option allows SPL to read from + sunxi SPI Flash. It uses the same method as the boot ROM, so does + not need any extra configuration. + +endif + endmenu # menu "SPI Flash Support" diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile index c665836f956..6f47a66f400 100644 --- a/drivers/mtd/spi/Makefile +++ b/drivers/mtd/spi/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_DM_SPI_FLASH) += sf-uclass.o ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_SPI_LOAD) += spi_spl_load.o obj-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o +obj-$(CONFIG_SPL_SPI_SUNXI) += sunxi_spi_spl.o endif obj-$(CONFIG_SPI_FLASH) += sf_probe.o spi_flash.o sf_params.o sf.o diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c index c577d9ed6c9..70ca236aced 100644 --- a/drivers/mtd/spi/sf_params.c +++ b/drivers/mtd/spi/sf_params.c @@ -22,7 +22,8 @@ const struct spi_flash_params spi_flash_params_table[] = { {"AT45DB161D", 0x1f2600, 0x0, 64 * 1024, 32, RD_NORM, SECT_4K}, {"AT45DB321D", 0x1f2700, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K}, {"AT45DB641D", 0x1f2800, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K}, - {"AT25DF321", 0x1f4701, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K}, + {"AT25DF321A", 0x1f4701, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K}, + {"AT25DF321", 0x1f4700, 0x0, 64 * 1024, 64, RD_NORM, SECT_4K}, {"AT26DF081A", 0x1f4501, 0x0, 64 * 1024, 16, RD_NORM, SECT_4K}, #endif #ifdef CONFIG_SPI_FLASH_EON /* EON */ @@ -84,6 +85,7 @@ const struct spi_flash_params spi_flash_params_table[] = { {"M25P64", 0x202017, 0x0, 64 * 1024, 128, RD_NORM, 0}, {"M25P128", 0x202018, 0x0, 256 * 1024, 64, RD_NORM, 0}, {"M25PX64", 0x207117, 0x0, 64 * 1024, 128, RD_NORM, SECT_4K}, + {"N25Q016A", 0x20bb15, 0x0, 64 * 1024, 32, RD_NORM, SECT_4K}, {"N25Q32", 0x20ba16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K}, {"N25Q32A", 0x20bb16, 0x0, 64 * 1024, 64, RD_FULL, WR_QPP | SECT_4K}, {"N25Q64", 0x20ba17, 0x0, 64 * 1024, 128, RD_FULL, WR_QPP | SECT_4K}, diff --git a/drivers/mtd/spi/sunxi_spi_spl.c b/drivers/mtd/spi/sunxi_spi_spl.c new file mode 100644 index 00000000000..e3ded5b4e81 --- /dev/null +++ b/drivers/mtd/spi/sunxi_spi_spl.c @@ -0,0 +1,283 @@ +/* + * Copyright (C) 2016 Siarhei Siamashka <siarhei.siamashka@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spl.h> +#include <asm/gpio.h> +#include <asm/io.h> + +#ifdef CONFIG_SPL_OS_BOOT +#error CONFIG_SPL_OS_BOOT is not supported yet +#endif + +/* + * This is a very simple U-Boot image loading implementation, trying to + * replicate what the boot ROM is doing when loading the SPL. Because we + * know the exact pins where the SPI Flash is connected and also know + * that the Read Data Bytes (03h) command is supported, the hardware + * configuration is very simple and we don't need the extra flexibility + * of the SPI framework. Moreover, we rely on the default settings of + * the SPI controler hardware registers and only adjust what needs to + * be changed. This is good for the code size and this implementation + * adds less than 400 bytes to the SPL. + * + * There are two variants of the SPI controller in Allwinner SoCs: + * A10/A13/A20 (sun4i variant) and everything else (sun6i variant). + * Both of them are supported. + * + * The pin mixing part is SoC specific and only A10/A13/A20/H3/A64 are + * supported at the moment. + */ + +/*****************************************************************************/ +/* SUN4I variant of the SPI controller */ +/*****************************************************************************/ + +#define SUN4I_SPI0_CCTL (0x01C05000 + 0x1C) +#define SUN4I_SPI0_CTL (0x01C05000 + 0x08) +#define SUN4I_SPI0_RX (0x01C05000 + 0x00) +#define SUN4I_SPI0_TX (0x01C05000 + 0x04) +#define SUN4I_SPI0_FIFO_STA (0x01C05000 + 0x28) +#define SUN4I_SPI0_BC (0x01C05000 + 0x20) +#define SUN4I_SPI0_TC (0x01C05000 + 0x24) + +#define SUN4I_CTL_ENABLE BIT(0) +#define SUN4I_CTL_MASTER BIT(1) +#define SUN4I_CTL_TF_RST BIT(8) +#define SUN4I_CTL_RF_RST BIT(9) +#define SUN4I_CTL_XCH BIT(10) + +/*****************************************************************************/ +/* SUN6I variant of the SPI controller */ +/*****************************************************************************/ + +#define SUN6I_SPI0_CCTL (0x01C68000 + 0x24) +#define SUN6I_SPI0_GCR (0x01C68000 + 0x04) +#define SUN6I_SPI0_TCR (0x01C68000 + 0x08) +#define SUN6I_SPI0_FIFO_STA (0x01C68000 + 0x1C) +#define SUN6I_SPI0_MBC (0x01C68000 + 0x30) +#define SUN6I_SPI0_MTC (0x01C68000 + 0x34) +#define SUN6I_SPI0_BCC (0x01C68000 + 0x38) +#define SUN6I_SPI0_TXD (0x01C68000 + 0x200) +#define SUN6I_SPI0_RXD (0x01C68000 + 0x300) + +#define SUN6I_CTL_ENABLE BIT(0) +#define SUN6I_CTL_MASTER BIT(1) +#define SUN6I_CTL_SRST BIT(31) +#define SUN6I_TCR_XCH BIT(31) + +/*****************************************************************************/ + +#define CCM_AHB_GATING0 (0x01C20000 + 0x60) +#define CCM_SPI0_CLK (0x01C20000 + 0xA0) +#define SUN6I_BUS_SOFT_RST_REG0 (0x01C20000 + 0x2C0) + +#define AHB_RESET_SPI0_SHIFT 20 +#define AHB_GATE_OFFSET_SPI0 20 + +#define SPI0_CLK_DIV_BY_2 0x1000 +#define SPI0_CLK_DIV_BY_4 0x1001 + +/*****************************************************************************/ + +/* + * Allwinner A10/A20 SoCs were using pins PC0,PC1,PC2,PC23 for booting + * from SPI Flash, everything else is using pins PC0,PC1,PC2,PC3. + */ +static void spi0_pinmux_setup(unsigned int pin_function) +{ + unsigned int pin; + + for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(2); pin++) + sunxi_gpio_set_cfgpin(pin, pin_function); + + if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I)) + sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_function); + else + sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function); +} + +/* + * Setup 6 MHz from OSC24M (because the BROM is doing the same). + */ +static void spi0_enable_clock(void) +{ + /* Deassert SPI0 reset on SUN6I */ + if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) + setbits_le32(SUN6I_BUS_SOFT_RST_REG0, + (1 << AHB_RESET_SPI0_SHIFT)); + + /* Open the SPI0 gate */ + setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); + + /* Divide by 4 */ + writel(SPI0_CLK_DIV_BY_4, IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) ? + SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL); + /* 24MHz from OSC24M */ + writel((1 << 31), CCM_SPI0_CLK); + + if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) { + /* Enable SPI in the master mode and do a soft reset */ + setbits_le32(SUN6I_SPI0_GCR, SUN6I_CTL_MASTER | + SUN6I_CTL_ENABLE | + SUN6I_CTL_SRST); + /* Wait for completion */ + while (readl(SUN6I_SPI0_GCR) & SUN6I_CTL_SRST) + ; + } else { + /* Enable SPI in the master mode and reset FIFO */ + setbits_le32(SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | + SUN4I_CTL_ENABLE | + SUN4I_CTL_TF_RST | + SUN4I_CTL_RF_RST); + } +} + +static void spi0_disable_clock(void) +{ + /* Disable the SPI0 controller */ + if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) + clrbits_le32(SUN6I_SPI0_GCR, SUN6I_CTL_MASTER | + SUN6I_CTL_ENABLE); + else + clrbits_le32(SUN4I_SPI0_CTL, SUN4I_CTL_MASTER | + SUN4I_CTL_ENABLE); + + /* Disable the SPI0 clock */ + writel(0, CCM_SPI0_CLK); + + /* Close the SPI0 gate */ + clrbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0)); + + /* Assert SPI0 reset on SUN6I */ + if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) + clrbits_le32(SUN6I_BUS_SOFT_RST_REG0, + (1 << AHB_RESET_SPI0_SHIFT)); +} + +static int spi0_init(void) +{ + unsigned int pin_function = SUNXI_GPC_SPI0; + if (IS_ENABLED(CONFIG_MACH_SUN50I)) + pin_function = SUN50I_GPC_SPI0; + + spi0_pinmux_setup(pin_function); + spi0_enable_clock(); +} + +static void spi0_deinit(void) +{ + /* New SoCs can disable pins, older could only set them as input */ + unsigned int pin_function = SUNXI_GPIO_INPUT; + if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) + pin_function = SUNXI_GPIO_DISABLE; + + spi0_disable_clock(); + spi0_pinmux_setup(pin_function); +} + +/*****************************************************************************/ + +#define SPI_READ_MAX_SIZE 60 /* FIFO size, minus 4 bytes of the header */ + +static void sunxi_spi0_read_data(u8 *buf, u32 addr, u32 bufsize, + u32 spi_ctl_reg, + u32 spi_ctl_xch_bitmask, + u32 spi_fifo_reg, + u32 spi_tx_reg, + u32 spi_rx_reg, + u32 spi_bc_reg, + u32 spi_tc_reg, + u32 spi_bcc_reg) +{ + writel(4 + bufsize, spi_bc_reg); /* Burst counter (total bytes) */ + writel(4, spi_tc_reg); /* Transfer counter (bytes to send) */ + if (spi_bcc_reg) + writel(4, spi_bcc_reg); /* SUN6I also needs this */ + + /* Send the Read Data Bytes (03h) command header */ + writeb(0x03, spi_tx_reg); + writeb((u8)(addr >> 16), spi_tx_reg); + writeb((u8)(addr >> 8), spi_tx_reg); + writeb((u8)(addr), spi_tx_reg); + + /* Start the data transfer */ + setbits_le32(spi_ctl_reg, spi_ctl_xch_bitmask); + + /* Wait until everything is received in the RX FIFO */ + while ((readl(spi_fifo_reg) & 0x7F) < 4 + bufsize) + ; + + /* Skip 4 bytes */ + readl(spi_rx_reg); + + /* Read the data */ + while (bufsize-- > 0) + *buf++ = readb(spi_rx_reg); + + /* tSHSL time is up to 100 ns in various SPI flash datasheets */ + udelay(1); +} + +static void spi0_read_data(void *buf, u32 addr, u32 len) +{ + u8 *buf8 = buf; + u32 chunk_len; + + while (len > 0) { + chunk_len = len; + if (chunk_len > SPI_READ_MAX_SIZE) + chunk_len = SPI_READ_MAX_SIZE; + + if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) { + sunxi_spi0_read_data(buf8, addr, chunk_len, + SUN6I_SPI0_TCR, + SUN6I_TCR_XCH, + SUN6I_SPI0_FIFO_STA, + SUN6I_SPI0_TXD, + SUN6I_SPI0_RXD, + SUN6I_SPI0_MBC, + SUN6I_SPI0_MTC, + SUN6I_SPI0_BCC); + } else { + sunxi_spi0_read_data(buf8, addr, chunk_len, + SUN4I_SPI0_CTL, + SUN4I_CTL_XCH, + SUN4I_SPI0_FIFO_STA, + SUN4I_SPI0_TX, + SUN4I_SPI0_RX, + SUN4I_SPI0_BC, + SUN4I_SPI0_TC, + 0); + } + + len -= chunk_len; + buf8 += chunk_len; + addr += chunk_len; + } +} + +/*****************************************************************************/ + +int spl_spi_load_image(void) +{ + int err; + struct image_header *header; + header = (struct image_header *)(CONFIG_SYS_TEXT_BASE); + + spi0_init(); + + spi0_read_data((void *)header, CONFIG_SYS_SPI_U_BOOT_OFFS, 0x40); + err = spl_parse_image_header(header); + if (err) + return err; + + spi0_read_data((void *)spl_image.load_addr, CONFIG_SYS_SPI_U_BOOT_OFFS, + spl_image.size); + + spi0_deinit(); + return 0; +} diff --git a/drivers/mtd/ubispl/Makefile b/drivers/mtd/ubispl/Makefile new file mode 100644 index 00000000000..740dbed12ab --- /dev/null +++ b/drivers/mtd/ubispl/Makefile @@ -0,0 +1 @@ +obj-y += ubispl.o ../ubi/crc32.o diff --git a/drivers/mtd/ubispl/ubi-wrapper.h b/drivers/mtd/ubispl/ubi-wrapper.h new file mode 100644 index 00000000000..72b9dcb76d9 --- /dev/null +++ b/drivers/mtd/ubispl/ubi-wrapper.h @@ -0,0 +1,106 @@ +/* + * The parts taken from the kernel implementation are: + * + * Copyright (c) International Business Machines Corp., 2006 + * + * UBISPL specific defines: + * + * Copyright (c) Thomas Gleixner <tglx@linutronix.de> + * + * SPDX-License-Identifier: GPL 2.0+ BSD-3-Clause + */ + +/* + * Contains various defines copy&pasted from ubi.h and ubi-user.h to make + * the upstream fastboot code happy. + */ +#ifndef __UBOOT_UBI_WRAPPER_H +#define __UBOOT_UBI_WRAPPER_H + +/* + * Error codes returned by the I/O sub-system. + * + * UBI_IO_FF: the read region of flash contains only 0xFFs + * UBI_IO_FF_BITFLIPS: the same as %UBI_IO_FF, but also also there was a data + * integrity error reported by the MTD driver + * (uncorrectable ECC error in case of NAND) + * UBI_IO_BAD_HDR: the EC or VID header is corrupted (bad magic or CRC) + * UBI_IO_BAD_HDR_EBADMSG: the same as %UBI_IO_BAD_HDR, but also there was a + * data integrity error reported by the MTD driver + * (uncorrectable ECC error in case of NAND) + * UBI_IO_BITFLIPS: bit-flips were detected and corrected + * + * UBI_FASTMAP_ANCHOR: u-boot SPL add on to tell the caller that the fastmap + * anchor block has been found + * + * Note, it is probably better to have bit-flip and ebadmsg as flags which can + * be or'ed with other error code. But this is a big change because there are + * may callers, so it does not worth the risk of introducing a bug + */ +enum { + UBI_IO_FF = 1, + UBI_IO_FF_BITFLIPS, + UBI_IO_BAD_HDR, + UBI_IO_BAD_HDR_EBADMSG, + UBI_IO_BITFLIPS, + UBI_FASTMAP_ANCHOR, +}; + +/* + * UBI volume type constants. + * + * @UBI_DYNAMIC_VOLUME: dynamic volume + * @UBI_STATIC_VOLUME: static volume + */ +enum { + UBI_DYNAMIC_VOLUME = 3, + UBI_STATIC_VOLUME = 4, +}; + +/* + * Return codes of the fastmap sub-system + * + * UBI_NO_FASTMAP: No fastmap super block was found + * UBI_BAD_FASTMAP: A fastmap was found but it's unusable + */ +enum { + UBI_NO_FASTMAP = 1, + UBI_BAD_FASTMAP, +}; + +/** + * struct ubi_fastmap_layout - in-memory fastmap data structure. + * @e: PEBs used by the current fastmap + * @to_be_tortured: if non-zero tortured this PEB + * @used_blocks: number of used PEBs + * @max_pool_size: maximal size of the user pool + * @max_wl_pool_size: maximal size of the pool used by the WL sub-system + */ +struct ubi_fastmap_layout { + struct ubi_wl_entry *e[UBI_FM_MAX_BLOCKS]; + int to_be_tortured[UBI_FM_MAX_BLOCKS]; + int used_blocks; + int max_pool_size; + int max_wl_pool_size; +}; + +/** + * struct ubi_fm_pool - in-memory fastmap pool + * @pebs: PEBs in this pool + * @used: number of used PEBs + * @size: total number of PEBs in this pool + * @max_size: maximal size of the pool + * + * A pool gets filled with up to max_size. + * If all PEBs within the pool are used a new fastmap will be written + * to the flash and the pool gets refilled with empty PEBs. + * + */ +struct ubi_fm_pool { + int pebs[UBI_FM_MAX_POOL_SIZE]; + int used; + int size; + int max_size; +}; + +#endif diff --git a/drivers/mtd/ubispl/ubispl.c b/drivers/mtd/ubispl/ubispl.c new file mode 100644 index 00000000000..a81a8e715da --- /dev/null +++ b/drivers/mtd/ubispl/ubispl.c @@ -0,0 +1,926 @@ +/* + * Copyright (c) Thomas Gleixner <tglx@linutronix.de> + * + * The parts taken from the kernel implementation are: + * + * Copyright (c) International Business Machines Corp., 2006 + * + * SPDX-License-Identifier: GPL 2.0+ BSD-3-Clause + */ + +#include <common.h> +#include <errno.h> +#include <ubispl.h> + +#include <linux/crc32.h> + +#include "ubispl.h" + +/** + * ubi_calc_fm_size - calculates the fastmap size in bytes for an UBI device. + * @ubi: UBI device description object + */ +static size_t ubi_calc_fm_size(struct ubi_scan_info *ubi) +{ + size_t size; + + size = sizeof(struct ubi_fm_sb) + + sizeof(struct ubi_fm_hdr) + + sizeof(struct ubi_fm_scan_pool) + + sizeof(struct ubi_fm_scan_pool) + + (ubi->peb_count * sizeof(struct ubi_fm_ec)) + + (sizeof(struct ubi_fm_eba) + + (ubi->peb_count * sizeof(__be32))) + + sizeof(struct ubi_fm_volhdr) * UBI_MAX_VOLUMES; + return roundup(size, ubi->leb_size); +} + +static int ubi_io_read(struct ubi_scan_info *ubi, void *buf, int pnum, + unsigned long from, unsigned long len) +{ + return ubi->read(pnum + ubi->peb_offset, from, len, buf); +} + +static int ubi_io_is_bad(struct ubi_scan_info *ubi, int peb) +{ + return peb >= ubi->peb_count || peb < 0; +} + +static int ubi_io_read_vid_hdr(struct ubi_scan_info *ubi, int pnum, + struct ubi_vid_hdr *vh, int unused) +{ + u32 magic; + int res; + + /* No point in rescanning a corrupt block */ + if (test_bit(pnum, ubi->corrupt)) + return UBI_IO_BAD_HDR; + /* + * If the block has been scanned already, no need to rescan + */ + if (test_and_set_bit(pnum, ubi->scanned)) + return 0; + + res = ubi_io_read(ubi, vh, pnum, ubi->vid_offset, sizeof(*vh)); + + /* + * Bad block, unrecoverable ECC error, skip the block + */ + if (res) { + ubi_dbg("Skipping bad or unreadable block %d", pnum); + vh->magic = 0; + generic_set_bit(pnum, ubi->corrupt); + return res; + } + + /* Magic number available ? */ + magic = be32_to_cpu(vh->magic); + if (magic != UBI_VID_HDR_MAGIC) { + generic_set_bit(pnum, ubi->corrupt); + if (magic == 0xffffffff) + return UBI_IO_FF; + ubi_msg("Bad magic in block 0%d %08x", pnum, magic); + return UBI_IO_BAD_HDR; + } + + /* Header CRC correct ? */ + if (crc32(UBI_CRC32_INIT, vh, UBI_VID_HDR_SIZE_CRC) != + be32_to_cpu(vh->hdr_crc)) { + ubi_msg("Bad CRC in block 0%d", pnum); + generic_set_bit(pnum, ubi->corrupt); + return UBI_IO_BAD_HDR; + } + + ubi_dbg("RV: pnum: %i sqnum %llu", pnum, be64_to_cpu(vh->sqnum)); + + return 0; +} + +static int ubi_rescan_fm_vid_hdr(struct ubi_scan_info *ubi, + struct ubi_vid_hdr *vh, + u32 fm_pnum, u32 fm_vol_id, u32 fm_lnum) +{ + int res; + + if (ubi_io_is_bad(ubi, fm_pnum)) + return -EINVAL; + + res = ubi_io_read_vid_hdr(ubi, fm_pnum, vh, 0); + if (!res) { + /* Check volume id, volume type and lnum */ + if (be32_to_cpu(vh->vol_id) == fm_vol_id && + vh->vol_type == UBI_VID_STATIC && + be32_to_cpu(vh->lnum) == fm_lnum) + return 0; + ubi_dbg("RS: PEB %u vol: %u : %u typ %u lnum %u %u", + fm_pnum, fm_vol_id, vh->vol_type, + be32_to_cpu(vh->vol_id), + fm_lnum, be32_to_cpu(vh->lnum)); + } + return res; +} + +/* Insert the logic block into the volume info */ +static int ubi_add_peb_to_vol(struct ubi_scan_info *ubi, + struct ubi_vid_hdr *vh, u32 vol_id, + u32 pnum, u32 lnum) +{ + struct ubi_vol_info *vi = ubi->volinfo + vol_id; + u32 *ltp; + + /* + * If the volume is larger than expected, yell and give up :( + */ + if (lnum >= UBI_MAX_VOL_LEBS) { + ubi_warn("Vol: %u LEB %d > %d", vol_id, lnum, UBI_MAX_VOL_LEBS); + return -EINVAL; + } + + ubi_dbg("SC: Add PEB %u to Vol %u as LEB %u fnd %d sc %d", + pnum, vol_id, lnum, !!test_bit(lnum, vi->found), + !!test_bit(pnum, ubi->scanned)); + + /* Points to the translation entry */ + ltp = vi->lebs_to_pebs + lnum; + + /* If the block is already assigned, check sqnum */ + if (__test_and_set_bit(lnum, vi->found)) { + u32 cur_pnum = *ltp; + struct ubi_vid_hdr *cur = ubi->blockinfo + cur_pnum; + + /* + * If the current block hase not yet been scanned, we + * need to do that. The other block might be stale or + * the current block corrupted and the FM not yet + * updated. + */ + if (!test_bit(cur_pnum, ubi->scanned)) { + /* + * If the scan fails, we use the valid block + */ + if (ubi_rescan_fm_vid_hdr(ubi, cur, cur_pnum, vol_id, + lnum)) { + *ltp = pnum; + return 0; + } + } + + /* + * Should not happen .... + */ + if (test_bit(cur_pnum, ubi->corrupt)) { + *ltp = pnum; + return 0; + } + + ubi_dbg("Vol %u LEB %u PEB %u->sqnum %llu NPEB %u->sqnum %llu", + vol_id, lnum, cur_pnum, be64_to_cpu(cur->sqnum), pnum, + be64_to_cpu(vh->sqnum)); + + /* + * Compare sqnum and take the newer one + */ + if (be64_to_cpu(cur->sqnum) < be64_to_cpu(vh->sqnum)) + *ltp = pnum; + } else { + *ltp = pnum; + if (lnum > vi->last_block) + vi->last_block = lnum; + } + + return 0; +} + +static int ubi_scan_vid_hdr(struct ubi_scan_info *ubi, struct ubi_vid_hdr *vh, + u32 pnum) +{ + u32 vol_id, lnum; + int res; + + if (ubi_io_is_bad(ubi, pnum)) + return -EINVAL; + + res = ubi_io_read_vid_hdr(ubi, pnum, vh, 0); + if (res) + return res; + + /* Get volume id */ + vol_id = be32_to_cpu(vh->vol_id); + + /* If this is the fastmap anchor, return right away */ + if (vol_id == UBI_FM_SB_VOLUME_ID) + return ubi->fm_enabled ? UBI_FASTMAP_ANCHOR : 0; + + /* We only care about static volumes with an id < UBI_SPL_VOL_IDS */ + if (vol_id >= UBI_SPL_VOL_IDS || vh->vol_type != UBI_VID_STATIC) + return 0; + + /* We are only interested in the volumes to load */ + if (!test_bit(vol_id, ubi->toload)) + return 0; + + lnum = be32_to_cpu(vh->lnum); + return ubi_add_peb_to_vol(ubi, vh, vol_id, pnum, lnum); +} + +static int assign_aeb_to_av(struct ubi_scan_info *ubi, u32 pnum, u32 lnum, + u32 vol_id, u32 vol_type, u32 used) +{ + struct ubi_vid_hdr *vh; + + if (ubi_io_is_bad(ubi, pnum)) + return -EINVAL; + + ubi->fastmap_pebs++; + + if (vol_id >= UBI_SPL_VOL_IDS || vol_type != UBI_STATIC_VOLUME) + return 0; + + /* We are only interested in the volumes to load */ + if (!test_bit(vol_id, ubi->toload)) + return 0; + + vh = ubi->blockinfo + pnum; + + return ubi_scan_vid_hdr(ubi, vh, pnum); +} + +static int scan_pool(struct ubi_scan_info *ubi, __be32 *pebs, int pool_size) +{ + struct ubi_vid_hdr *vh; + u32 pnum; + int i; + + ubi_dbg("Scanning pool size: %d", pool_size); + + for (i = 0; i < pool_size; i++) { + pnum = be32_to_cpu(pebs[i]); + + if (ubi_io_is_bad(ubi, pnum)) { + ubi_err("FM: Bad PEB in fastmap pool! %u", pnum); + return UBI_BAD_FASTMAP; + } + + vh = ubi->blockinfo + pnum; + /* + * We allow the scan to fail here. The loader will notice + * and look for a replacement. + */ + ubi_scan_vid_hdr(ubi, vh, pnum); + } + return 0; +} + +/* + * Fastmap code is stolen from Linux kernel and this stub structure is used + * to make it happy. + */ +struct ubi_attach_info { + int i; +}; + +static int ubi_attach_fastmap(struct ubi_scan_info *ubi, + struct ubi_attach_info *ai, + struct ubi_fastmap_layout *fm) +{ + struct ubi_fm_hdr *fmhdr; + struct ubi_fm_scan_pool *fmpl1, *fmpl2; + struct ubi_fm_ec *fmec; + struct ubi_fm_volhdr *fmvhdr; + struct ubi_fm_eba *fm_eba; + int ret, i, j, pool_size, wl_pool_size; + size_t fm_pos = 0, fm_size = ubi->fm_size; + void *fm_raw = ubi->fm_buf; + + memset(ubi->fm_used, 0, sizeof(ubi->fm_used)); + + fm_pos += sizeof(struct ubi_fm_sb); + if (fm_pos >= fm_size) + goto fail_bad; + + fmhdr = (struct ubi_fm_hdr *)(fm_raw + fm_pos); + fm_pos += sizeof(*fmhdr); + if (fm_pos >= fm_size) + goto fail_bad; + + if (be32_to_cpu(fmhdr->magic) != UBI_FM_HDR_MAGIC) { + ubi_err("bad fastmap header magic: 0x%x, expected: 0x%x", + be32_to_cpu(fmhdr->magic), UBI_FM_HDR_MAGIC); + goto fail_bad; + } + + fmpl1 = (struct ubi_fm_scan_pool *)(fm_raw + fm_pos); + fm_pos += sizeof(*fmpl1); + if (fm_pos >= fm_size) + goto fail_bad; + if (be32_to_cpu(fmpl1->magic) != UBI_FM_POOL_MAGIC) { + ubi_err("bad fastmap pool magic: 0x%x, expected: 0x%x", + be32_to_cpu(fmpl1->magic), UBI_FM_POOL_MAGIC); + goto fail_bad; + } + + fmpl2 = (struct ubi_fm_scan_pool *)(fm_raw + fm_pos); + fm_pos += sizeof(*fmpl2); + if (fm_pos >= fm_size) + goto fail_bad; + if (be32_to_cpu(fmpl2->magic) != UBI_FM_POOL_MAGIC) { + ubi_err("bad fastmap pool magic: 0x%x, expected: 0x%x", + be32_to_cpu(fmpl2->magic), UBI_FM_POOL_MAGIC); + goto fail_bad; + } + + pool_size = be16_to_cpu(fmpl1->size); + wl_pool_size = be16_to_cpu(fmpl2->size); + fm->max_pool_size = be16_to_cpu(fmpl1->max_size); + fm->max_wl_pool_size = be16_to_cpu(fmpl2->max_size); + + if (pool_size > UBI_FM_MAX_POOL_SIZE || pool_size < 0) { + ubi_err("bad pool size: %i", pool_size); + goto fail_bad; + } + + if (wl_pool_size > UBI_FM_MAX_POOL_SIZE || wl_pool_size < 0) { + ubi_err("bad WL pool size: %i", wl_pool_size); + goto fail_bad; + } + + if (fm->max_pool_size > UBI_FM_MAX_POOL_SIZE || + fm->max_pool_size < 0) { + ubi_err("bad maximal pool size: %i", fm->max_pool_size); + goto fail_bad; + } + + if (fm->max_wl_pool_size > UBI_FM_MAX_POOL_SIZE || + fm->max_wl_pool_size < 0) { + ubi_err("bad maximal WL pool size: %i", fm->max_wl_pool_size); + goto fail_bad; + } + + /* read EC values from free list */ + for (i = 0; i < be32_to_cpu(fmhdr->free_peb_count); i++) { + fmec = (struct ubi_fm_ec *)(fm_raw + fm_pos); + fm_pos += sizeof(*fmec); + if (fm_pos >= fm_size) + goto fail_bad; + } + + /* read EC values from used list */ + for (i = 0; i < be32_to_cpu(fmhdr->used_peb_count); i++) { + fmec = (struct ubi_fm_ec *)(fm_raw + fm_pos); + fm_pos += sizeof(*fmec); + if (fm_pos >= fm_size) + goto fail_bad; + + generic_set_bit(be32_to_cpu(fmec->pnum), ubi->fm_used); + } + + /* read EC values from scrub list */ + for (i = 0; i < be32_to_cpu(fmhdr->scrub_peb_count); i++) { + fmec = (struct ubi_fm_ec *)(fm_raw + fm_pos); + fm_pos += sizeof(*fmec); + if (fm_pos >= fm_size) + goto fail_bad; + } + + /* read EC values from erase list */ + for (i = 0; i < be32_to_cpu(fmhdr->erase_peb_count); i++) { + fmec = (struct ubi_fm_ec *)(fm_raw + fm_pos); + fm_pos += sizeof(*fmec); + if (fm_pos >= fm_size) + goto fail_bad; + } + + /* Iterate over all volumes and read their EBA table */ + for (i = 0; i < be32_to_cpu(fmhdr->vol_count); i++) { + u32 vol_id, vol_type, used, reserved; + + fmvhdr = (struct ubi_fm_volhdr *)(fm_raw + fm_pos); + fm_pos += sizeof(*fmvhdr); + if (fm_pos >= fm_size) + goto fail_bad; + + if (be32_to_cpu(fmvhdr->magic) != UBI_FM_VHDR_MAGIC) { + ubi_err("bad fastmap vol header magic: 0x%x, " \ + "expected: 0x%x", + be32_to_cpu(fmvhdr->magic), UBI_FM_VHDR_MAGIC); + goto fail_bad; + } + + vol_id = be32_to_cpu(fmvhdr->vol_id); + vol_type = fmvhdr->vol_type; + used = be32_to_cpu(fmvhdr->used_ebs); + + fm_eba = (struct ubi_fm_eba *)(fm_raw + fm_pos); + fm_pos += sizeof(*fm_eba); + fm_pos += (sizeof(__be32) * be32_to_cpu(fm_eba->reserved_pebs)); + if (fm_pos >= fm_size) + goto fail_bad; + + if (be32_to_cpu(fm_eba->magic) != UBI_FM_EBA_MAGIC) { + ubi_err("bad fastmap EBA header magic: 0x%x, " \ + "expected: 0x%x", + be32_to_cpu(fm_eba->magic), UBI_FM_EBA_MAGIC); + goto fail_bad; + } + + reserved = be32_to_cpu(fm_eba->reserved_pebs); + ubi_dbg("FA: vol %u used %u res: %u", vol_id, used, reserved); + for (j = 0; j < reserved; j++) { + int pnum = be32_to_cpu(fm_eba->pnum[j]); + + if ((int)be32_to_cpu(fm_eba->pnum[j]) < 0) + continue; + + if (!__test_and_clear_bit(pnum, ubi->fm_used)) + continue; + + /* + * We only handle static volumes so used_ebs + * needs to be handed in. And we do not assign + * the reserved blocks + */ + if (j >= used) + continue; + + ret = assign_aeb_to_av(ubi, pnum, j, vol_id, + vol_type, used); + if (!ret) + continue; + + /* + * Nasty: The fastmap claims that the volume + * has one block more than it, but that block + * is always empty and the other blocks have + * the correct number of total LEBs in the + * headers. Deal with it. + */ + if (ret != UBI_IO_FF && j != used - 1) + goto fail_bad; + ubi_dbg("FA: Vol: %u Ignoring empty LEB %d of %d", + vol_id, j, used); + } + } + + ret = scan_pool(ubi, fmpl1->pebs, pool_size); + if (ret) + goto fail; + + ret = scan_pool(ubi, fmpl2->pebs, wl_pool_size); + if (ret) + goto fail; + +#ifdef CHECKME + /* + * If fastmap is leaking PEBs (must not happen), raise a + * fat warning and fall back to scanning mode. + * We do this here because in ubi_wl_init() it's too late + * and we cannot fall back to scanning. + */ + if (WARN_ON(count_fastmap_pebs(ai) != ubi->peb_count - + ai->bad_peb_count - fm->used_blocks)) + goto fail_bad; +#endif + + return 0; + +fail_bad: + ret = UBI_BAD_FASTMAP; +fail: + return ret; +} + +static int ubi_scan_fastmap(struct ubi_scan_info *ubi, + struct ubi_attach_info *ai, + int fm_anchor) +{ + struct ubi_fm_sb *fmsb, *fmsb2; + struct ubi_vid_hdr *vh; + struct ubi_fastmap_layout *fm; + int i, used_blocks, pnum, ret = 0; + size_t fm_size; + __be32 crc, tmp_crc; + unsigned long long sqnum = 0; + + fmsb = &ubi->fm_sb; + fm = &ubi->fm_layout; + + ret = ubi_io_read(ubi, fmsb, fm_anchor, ubi->leb_start, sizeof(*fmsb)); + if (ret && ret != UBI_IO_BITFLIPS) + goto free_fm_sb; + else if (ret == UBI_IO_BITFLIPS) + fm->to_be_tortured[0] = 1; + + if (be32_to_cpu(fmsb->magic) != UBI_FM_SB_MAGIC) { + ubi_err("bad super block magic: 0x%x, expected: 0x%x", + be32_to_cpu(fmsb->magic), UBI_FM_SB_MAGIC); + ret = UBI_BAD_FASTMAP; + goto free_fm_sb; + } + + if (fmsb->version != UBI_FM_FMT_VERSION) { + ubi_err("bad fastmap version: %i, expected: %i", + fmsb->version, UBI_FM_FMT_VERSION); + ret = UBI_BAD_FASTMAP; + goto free_fm_sb; + } + + used_blocks = be32_to_cpu(fmsb->used_blocks); + if (used_blocks > UBI_FM_MAX_BLOCKS || used_blocks < 1) { + ubi_err("number of fastmap blocks is invalid: %i", used_blocks); + ret = UBI_BAD_FASTMAP; + goto free_fm_sb; + } + + fm_size = ubi->leb_size * used_blocks; + if (fm_size != ubi->fm_size) { + ubi_err("bad fastmap size: %zi, expected: %zi", fm_size, + ubi->fm_size); + ret = UBI_BAD_FASTMAP; + goto free_fm_sb; + } + + vh = &ubi->fm_vh; + + for (i = 0; i < used_blocks; i++) { + pnum = be32_to_cpu(fmsb->block_loc[i]); + + if (ubi_io_is_bad(ubi, pnum)) { + ret = UBI_BAD_FASTMAP; + goto free_hdr; + } + +#ifdef LATER + int image_seq; + ret = ubi_io_read_ec_hdr(ubi, pnum, ech, 0); + if (ret && ret != UBI_IO_BITFLIPS) { + ubi_err("unable to read fastmap block# %i EC (PEB: %i)", + i, pnum); + if (ret > 0) + ret = UBI_BAD_FASTMAP; + goto free_hdr; + } else if (ret == UBI_IO_BITFLIPS) + fm->to_be_tortured[i] = 1; + + image_seq = be32_to_cpu(ech->image_seq); + if (!ubi->image_seq) + ubi->image_seq = image_seq; + /* + * Older UBI implementations have image_seq set to zero, so + * we shouldn't fail if image_seq == 0. + */ + if (image_seq && (image_seq != ubi->image_seq)) { + ubi_err("wrong image seq:%d instead of %d", + be32_to_cpu(ech->image_seq), ubi->image_seq); + ret = UBI_BAD_FASTMAP; + goto free_hdr; + } +#endif + ret = ubi_io_read_vid_hdr(ubi, pnum, vh, 0); + if (ret && ret != UBI_IO_BITFLIPS) { + ubi_err("unable to read fastmap block# %i (PEB: %i)", + i, pnum); + goto free_hdr; + } + + /* + * Mainline code rescans the anchor header. We've done + * that already so we merily copy it over. + */ + if (pnum == fm_anchor) + memcpy(vh, ubi->blockinfo + pnum, sizeof(*fm)); + + if (i == 0) { + if (be32_to_cpu(vh->vol_id) != UBI_FM_SB_VOLUME_ID) { + ubi_err("bad fastmap anchor vol_id: 0x%x," \ + " expected: 0x%x", + be32_to_cpu(vh->vol_id), + UBI_FM_SB_VOLUME_ID); + ret = UBI_BAD_FASTMAP; + goto free_hdr; + } + } else { + if (be32_to_cpu(vh->vol_id) != UBI_FM_DATA_VOLUME_ID) { + ubi_err("bad fastmap data vol_id: 0x%x," \ + " expected: 0x%x", + be32_to_cpu(vh->vol_id), + UBI_FM_DATA_VOLUME_ID); + ret = UBI_BAD_FASTMAP; + goto free_hdr; + } + } + + if (sqnum < be64_to_cpu(vh->sqnum)) + sqnum = be64_to_cpu(vh->sqnum); + + ret = ubi_io_read(ubi, ubi->fm_buf + (ubi->leb_size * i), pnum, + ubi->leb_start, ubi->leb_size); + if (ret && ret != UBI_IO_BITFLIPS) { + ubi_err("unable to read fastmap block# %i (PEB: %i, " \ + "err: %i)", i, pnum, ret); + goto free_hdr; + } + } + + fmsb2 = (struct ubi_fm_sb *)(ubi->fm_buf); + tmp_crc = be32_to_cpu(fmsb2->data_crc); + fmsb2->data_crc = 0; + crc = crc32(UBI_CRC32_INIT, ubi->fm_buf, fm_size); + if (crc != tmp_crc) { + ubi_err("fastmap data CRC is invalid"); + ubi_err("CRC should be: 0x%x, calc: 0x%x", tmp_crc, crc); + ret = UBI_BAD_FASTMAP; + goto free_hdr; + } + + fmsb2->sqnum = sqnum; + + fm->used_blocks = used_blocks; + + ret = ubi_attach_fastmap(ubi, ai, fm); + if (ret) { + if (ret > 0) + ret = UBI_BAD_FASTMAP; + goto free_hdr; + } + + ubi->fm = fm; + ubi->fm_pool.max_size = ubi->fm->max_pool_size; + ubi->fm_wl_pool.max_size = ubi->fm->max_wl_pool_size; + ubi_msg("attached by fastmap %uMB %u blocks", + ubi->fsize_mb, ubi->peb_count); + ubi_dbg("fastmap pool size: %d", ubi->fm_pool.max_size); + ubi_dbg("fastmap WL pool size: %d", ubi->fm_wl_pool.max_size); + +out: + if (ret) + ubi_err("Attach by fastmap failed, doing a full scan!"); + return ret; + +free_hdr: +free_fm_sb: + goto out; +} + +/* + * Scan the flash and attempt to attach via fastmap + */ +static void ipl_scan(struct ubi_scan_info *ubi) +{ + unsigned int pnum; + int res; + + /* + * Scan first for the fastmap super block + */ + for (pnum = 0; pnum < UBI_FM_MAX_START; pnum++) { + res = ubi_scan_vid_hdr(ubi, ubi->blockinfo + pnum, pnum); + /* + * We ignore errors here as we are meriliy scanning + * the headers. + */ + if (res != UBI_FASTMAP_ANCHOR) + continue; + + /* + * If fastmap is disabled, continue scanning. This + * might happen because the previous attempt failed or + * the caller disabled it right away. + */ + if (!ubi->fm_enabled) + continue; + + /* + * Try to attach the fastmap, if that fails continue + * scanning. + */ + if (!ubi_scan_fastmap(ubi, NULL, pnum)) + return; + /* + * Fastmap failed. Clear everything we have and start + * over. We are paranoid and do not trust anything. + */ + memset(ubi->volinfo, 0, sizeof(ubi->volinfo)); + pnum = 0; + break; + } + + /* + * Continue scanning, ignore errors, we might find what we are + * looking for, + */ + for (; pnum < ubi->peb_count; pnum++) + ubi_scan_vid_hdr(ubi, ubi->blockinfo + pnum, pnum); +} + +/* + * Load a logical block of a volume into memory + */ +static int ubi_load_block(struct ubi_scan_info *ubi, uint8_t *laddr, + struct ubi_vol_info *vi, u32 vol_id, u32 lnum, + u32 last) +{ + struct ubi_vid_hdr *vh, *vrepl; + u32 pnum, crc, dlen; + +retry: + /* + * If this is a fastmap run, we try to rescan full, otherwise + * we simply give up. + */ + if (!test_bit(lnum, vi->found)) { + ubi_warn("LEB %d of %d is missing", lnum, last); + return -EINVAL; + } + + pnum = vi->lebs_to_pebs[lnum]; + + ubi_dbg("Load vol %u LEB %u PEB %u", vol_id, lnum, pnum); + + if (ubi_io_is_bad(ubi, pnum)) { + ubi_warn("Corrupted mapping block %d PB %d\n", lnum, pnum); + return -EINVAL; + } + + if (test_bit(pnum, ubi->corrupt)) + goto find_other; + + /* + * Lets try to read that block + */ + vh = ubi->blockinfo + pnum; + + if (!test_bit(pnum, ubi->scanned)) { + ubi_warn("Vol: %u LEB %u PEB %u not yet scanned", vol_id, + lnum, pnum); + if (ubi_rescan_fm_vid_hdr(ubi, vh, pnum, vol_id, lnum)) + goto find_other; + } + + /* + * Check, if the total number of blocks is correct + */ + if (be32_to_cpu(vh->used_ebs) != last) { + ubi_dbg("Block count missmatch."); + ubi_dbg("vh->used_ebs: %d nrblocks: %d", + be32_to_cpu(vh->used_ebs), last); + generic_set_bit(pnum, ubi->corrupt); + goto find_other; + } + + /* + * Get the data length of this block. + */ + dlen = be32_to_cpu(vh->data_size); + + /* + * Read the data into RAM. We ignore the return value + * here as the only thing which might go wrong are + * bitflips. Try nevertheless. + */ + ubi_io_read(ubi, laddr, pnum, ubi->leb_start, dlen); + + /* Calculate CRC over the data */ + crc = crc32(UBI_CRC32_INIT, laddr, dlen); + + if (crc != be32_to_cpu(vh->data_crc)) { + ubi_warn("Vol: %u LEB %u PEB %u data CRC failure", vol_id, + lnum, pnum); + generic_set_bit(pnum, ubi->corrupt); + goto find_other; + } + + /* We are good. Return the data length we read */ + return dlen; + +find_other: + ubi_dbg("Find replacement for LEB %u PEB %u", lnum, pnum); + generic_clear_bit(lnum, vi->found); + vrepl = NULL; + + for (pnum = 0; pnum < ubi->peb_count; pnum++) { + struct ubi_vid_hdr *tmp = ubi->blockinfo + pnum; + u32 t_vol_id = be32_to_cpu(tmp->vol_id); + u32 t_lnum = be32_to_cpu(tmp->lnum); + + if (test_bit(pnum, ubi->corrupt)) + continue; + + if (t_vol_id != vol_id || t_lnum != lnum) + continue; + + if (!test_bit(pnum, ubi->scanned)) { + ubi_warn("Vol: %u LEB %u PEB %u not yet scanned", + vol_id, lnum, pnum); + if (ubi_rescan_fm_vid_hdr(ubi, tmp, pnum, vol_id, lnum)) + continue; + } + + /* + * We found one. If its the first, assign it otherwise + * compare the sqnum + */ + generic_set_bit(lnum, vi->found); + + if (!vrepl) { + vrepl = tmp; + continue; + } + + if (be64_to_cpu(vrepl->sqnum) < be64_to_cpu(tmp->sqnum)) + vrepl = tmp; + } + + if (vrepl) { + /* Update the vi table */ + pnum = vrepl - ubi->blockinfo; + vi->lebs_to_pebs[lnum] = pnum; + ubi_dbg("Trying PEB %u for LEB %u", pnum, lnum); + vh = vrepl; + } + goto retry; +} + +/* + * Load a volume into RAM + */ +static int ipl_load(struct ubi_scan_info *ubi, const u32 vol_id, uint8_t *laddr) +{ + struct ubi_vol_info *vi; + u32 lnum, last, len; + + if (vol_id >= UBI_SPL_VOL_IDS) + return -EINVAL; + + len = 0; + vi = ubi->volinfo + vol_id; + last = vi->last_block + 1; + + /* Read the blocks to RAM, check CRC */ + for (lnum = 0 ; lnum < last; lnum++) { + int res = ubi_load_block(ubi, laddr, vi, vol_id, lnum, last); + + if (res < 0) { + ubi_warn("Failed to load volume %u", vol_id); + return res; + } + /* res is the data length of the read block */ + laddr += res; + len += res; + } + return len; +} + +int ubispl_load_volumes(struct ubispl_info *info, struct ubispl_load *lvols, + int nrvols) +{ + struct ubi_scan_info *ubi = info->ubi; + int res, i, fastmap = info->fastmap; + u32 fsize; + +retry: + /* + * We do a partial initializiation of @ubi. Cleaning fm_buf is + * not necessary. + */ + memset(ubi, 0, offsetof(struct ubi_scan_info, fm_buf)); + + ubi->read = info->read; + + /* Precalculate the offsets */ + ubi->vid_offset = info->vid_offset; + ubi->leb_start = info->leb_start; + ubi->leb_size = info->peb_size - ubi->leb_start; + ubi->peb_count = info->peb_count; + ubi->peb_offset = info->peb_offset; + + fsize = info->peb_size * info->peb_count; + ubi->fsize_mb = fsize >> 20; + + /* Fastmap init */ + ubi->fm_size = ubi_calc_fm_size(ubi); + ubi->fm_enabled = fastmap; + + for (i = 0; i < nrvols; i++) { + struct ubispl_load *lv = lvols + i; + + generic_set_bit(lv->vol_id, ubi->toload); + } + + ipl_scan(ubi); + + for (i = 0; i < nrvols; i++) { + struct ubispl_load *lv = lvols + i; + + ubi_msg("Loading VolId #%d", lv->vol_id); + res = ipl_load(ubi, lv->vol_id, lv->load_addr); + if (res < 0) { + if (fastmap) { + fastmap = 0; + goto retry; + } + ubi_warn("Failed"); + return res; + } + } + return 0; +} diff --git a/drivers/mtd/ubispl/ubispl.h b/drivers/mtd/ubispl/ubispl.h new file mode 100644 index 00000000000..9227881f63e --- /dev/null +++ b/drivers/mtd/ubispl/ubispl.h @@ -0,0 +1,136 @@ +/* + * Copyright (c) Thomas Gleixner <tglx@linutronix.de> + * + * SPDX-License-Identifier: GPL 2.0+ BSD-3-Clause + */ + +#ifndef _UBOOT_MTD_UBISPL_H +#define _UBOOT_MTD_UBISPL_H + +#include "../ubi/ubi-media.h" +#include "ubi-wrapper.h" + +/* + * The maximum number of volume ids we scan. So you can load volume id + * 0 to (CONFIG_SPL_UBI_VOL_ID_MAX - 1) + */ +#define UBI_SPL_VOL_IDS CONFIG_SPL_UBI_VOL_IDS +/* + * The size of the read buffer for the fastmap blocks. In theory up to + * UBI_FM_MAX_BLOCKS * CONFIG_SPL_MAX_PEB_SIZE. In practice today + * one or two blocks. + */ +#define UBI_FM_BUF_SIZE (UBI_FM_MAX_BLOCKS*CONFIG_SPL_UBI_MAX_PEB_SIZE) +/* + * The size of the bitmaps for the attach/ scan + */ +#define UBI_FM_BM_SIZE ((CONFIG_SPL_UBI_MAX_PEBS / BITS_PER_LONG) + 1) +/* + * The maximum number of logical erase blocks per loadable volume + */ +#define UBI_MAX_VOL_LEBS CONFIG_SPL_UBI_MAX_VOL_LEBS +/* + * The bitmap size for the above to denote the found blocks inside the volume + */ +#define UBI_VOL_BM_SIZE ((UBI_MAX_VOL_LEBS / BITS_PER_LONG) + 1) + +/** + * struct ubi_vol_info - UBISPL internal volume represenation + * @last_block: The last block (highest LEB) found for this volume + * @found: Bitmap to mark found LEBS + * @lebs_to_pebs: LEB to PEB translation table + */ +struct ubi_vol_info { + u32 last_block; + unsigned long found[UBI_VOL_BM_SIZE]; + u32 lebs_to_pebs[UBI_MAX_VOL_LEBS]; +}; + +/** + * struct ubi_scan_info - UBISPL internal data for FM attach and full scan + * + * @read: Read function to access the flash provided by the caller + * @peb_count: Number of physical erase blocks in the UBI FLASH area + * aka MTD partition. + * @peb_offset: Offset of PEB0 in the UBI FLASH area (aka MTD partition) + * to the real start of the FLASH in erase blocks. + * @fsize_mb: Size of the scanned FLASH area in MB (stats only) + * @vid_offset: Offset from the start of a PEB to the VID header + * @leb_start: Offset from the start of a PEB to the data area + * @leb_size: Size of the data area + * + * @fastmap_pebs: Counter of PEBs "attached" by fastmap + * @fastmap_anchor: The anchor PEB of the fastmap + * @fm_sb: The fastmap super block data + * @fm_vh: The fastmap VID header + * @fm: Pointer to the fastmap layout + * @fm_layout: The fastmap layout itself + * @fm_pool: The pool of PEBs to scan at fastmap attach time + * @fm_wl_pool: The pool of PEBs scheduled for wearleveling + * + * @fm_enabled: Indicator whether fastmap attachment is enabled. + * @fm_used: Bitmap to indicate the PEBS covered by fastmap + * @scanned: Bitmap to indicate the PEBS of which the VID header + * hase been physically scanned. + * @corrupt: Bitmap to indicate corrupt blocks + * @toload: Bitmap to indicate the volumes which should be loaded + * + * @blockinfo: The vid headers of the scanned blocks + * @volinfo: The volume information of the interesting (toload) + * volumes + * + * @fm_buf: The large fastmap attach buffer + */ +struct ubi_scan_info { + ubispl_read_flash read; + unsigned int fsize_mb; + unsigned int peb_count; + unsigned int peb_offset; + + unsigned long vid_offset; + unsigned long leb_start; + unsigned long leb_size; + + /* Fastmap: The upstream required fields */ + int fastmap_pebs; + int fastmap_anchor; + size_t fm_size; + struct ubi_fm_sb fm_sb; + struct ubi_vid_hdr fm_vh; + struct ubi_fastmap_layout *fm; + struct ubi_fastmap_layout fm_layout; + struct ubi_fm_pool fm_pool; + struct ubi_fm_pool fm_wl_pool; + + /* Fastmap: UBISPL specific data */ + int fm_enabled; + unsigned long fm_used[UBI_FM_BM_SIZE]; + unsigned long scanned[UBI_FM_BM_SIZE]; + unsigned long corrupt[UBI_FM_BM_SIZE]; + unsigned long toload[UBI_FM_BM_SIZE]; + + /* Data for storing the VID and volume information */ + struct ubi_vol_info volinfo[UBI_SPL_VOL_IDS]; + struct ubi_vid_hdr blockinfo[CONFIG_SPL_UBI_MAX_PEBS]; + + /* The large buffer for the fastmap */ + uint8_t fm_buf[UBI_FM_BUF_SIZE]; +}; + +#ifdef CFG_DEBUG +#define ubi_dbg(fmt, ...) printf("UBI: debug:" fmt "\n", ##__VA_ARGS__) +#else +#define ubi_dbg(fmt, ...) +#endif + +#ifdef CONFIG_UBI_SILENCE_MSG +#define ubi_msg(fmt, ...) +#else +#define ubi_msg(fmt, ...) printf("UBI: " fmt "\n", ##__VA_ARGS__) +#endif +/* UBI warning messages */ +#define ubi_warn(fmt, ...) printf("UBI warning: " fmt "\n", ##__VA_ARGS__) +/* UBI error messages */ +#define ubi_err(fmt, ...) printf("UBI error: " fmt "\n", ##__VA_ARGS__) + +#endif diff --git a/drivers/net/4xx_enet.c b/drivers/net/4xx_enet.c index bc52ed35ccb..b71848168a6 100644 --- a/drivers/net/4xx_enet.c +++ b/drivers/net/4xx_enet.c @@ -283,10 +283,9 @@ static void mal_err (struct eth_device *dev, unsigned long isr, static void emac_err (struct eth_device *dev, unsigned long isr); extern int phy_setup_aneg (char *devname, unsigned char addr); -extern int emac4xx_miiphy_read (const char *devname, unsigned char addr, - unsigned char reg, unsigned short *value); -extern int emac4xx_miiphy_write (const char *devname, unsigned char addr, - unsigned char reg, unsigned short value); +int emac4xx_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg); +int emac4xx_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg, + u16 value); int board_emac_count(void); @@ -2015,8 +2014,17 @@ int ppc_4xx_eth_initialize (bd_t * bis) eth_register(dev); #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - miiphy_register(dev->name, - emac4xx_miiphy_read, emac4xx_miiphy_write); + int retval; + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; + strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); + mdiodev->read = emac4xx_miiphy_read; + mdiodev->write = emac4xx_miiphy_write; + + retval = mdio_register(mdiodev); + if (retval < 0) + return retval; #endif if (0 == virgin) { diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index c1cb689ccf3..be3ed73e522 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -124,6 +124,11 @@ config ETH_DESIGNWARE 100Mbit and 1 Gbit operation. You must enable CONFIG_PHYLIB to provide the PHY (physical media interface). +config ETHOC + bool "OpenCores 10/100 Mbps Ethernet MAC" + help + This MAC is present in OpenRISC and Xtensa XTFPGA boards. + config MVPP2 bool "Marvell Armada 375 network interface support" depends on ARMADA_375 @@ -152,6 +157,15 @@ config RTL8169 This driver supports Realtek 8169 series gigabit ethernet family of PCI/PCIe chipsets/adapters. +config SUN8I_EMAC + bool "Allwinner Sun8i Ethernet MAC support" + depends on DM_ETH + select PHYLIB + help + This driver supports the Allwinner based SUN8I/SUN50I Ethernet MAC. + It can be found in H3/A64/A83T based SoCs and compatible with both + External and Internal PHY's. + config XILINX_AXIEMAC depends on DM_ETH && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP) select PHYLIB diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 57025921698..a4485266d45 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_E1000) += e1000.o obj-$(CONFIG_E1000_SPI) += e1000_spi.o obj-$(CONFIG_EEPRO100) += eepro100.o obj-$(CONFIG_SUNXI_EMAC) += sunxi_emac.o +obj-$(CONFIG_SUN8I_EMAC) += sun8i_emac.o obj-$(CONFIG_ENC28J60) += enc28j60.o obj-$(CONFIG_EP93XX) += ep93xx_eth.o obj-$(CONFIG_ETHOC) += ethoc.o diff --git a/drivers/net/armada100_fec.c b/drivers/net/armada100_fec.c index e6a62525be0..ba2cb1ad6db 100644 --- a/drivers/net/armada100_fec.c +++ b/drivers/net/armada100_fec.c @@ -57,18 +57,19 @@ static int armdfec_phy_timeout(u32 *reg, u32 flag, int cond) return !timeout; } -static int smi_reg_read(const char *devname, u8 phy_addr, u8 phy_reg, - u16 *value) +static int smi_reg_read(struct mii_dev *bus, int phy_addr, int devad, + int phy_reg) { - struct eth_device *dev = eth_get_dev_by_name(devname); + u16 value = 0; + struct eth_device *dev = eth_get_dev_by_name(bus->name); struct armdfec_device *darmdfec = to_darmdfec(dev); struct armdfec_reg *regs = darmdfec->regs; u32 val; if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) { val = readl(®s->phyadr); - *value = val & 0x1f; - return 0; + value = val & 0x1f; + return value; } /* check parameters */ @@ -99,15 +100,15 @@ static int smi_reg_read(const char *devname, u8 phy_addr, u8 phy_reg, return -1; } val = readl(®s->smi); - *value = val & 0xffff; + value = val & 0xffff; - return 0; + return value; } -static int smi_reg_write(const char *devname, - u8 phy_addr, u8 phy_reg, u16 value) +static int smi_reg_write(struct mii_dev *bus, int phy_addr, int devad, + int phy_reg, u16 value) { - struct eth_device *dev = eth_get_dev_by_name(devname); + struct eth_device *dev = eth_get_dev_by_name(bus->name); struct armdfec_device *darmdfec = to_darmdfec(dev); struct armdfec_reg *regs = darmdfec->regs; @@ -711,7 +712,17 @@ int armada100_fec_register(unsigned long base_addr) eth_register(dev); #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - miiphy_register(dev->name, smi_reg_read, smi_reg_write); + int retval; + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; + strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); + mdiodev->read = smi_reg_read; + mdiodev->write = smi_reg_write; + + retval = mdio_register(mdiodev); + if (retval < 0) + return retval; #endif return 0; diff --git a/drivers/net/at91_emac.c b/drivers/net/at91_emac.c index 91516001909..be3d82e67ea 100644 --- a/drivers/net/at91_emac.c +++ b/drivers/net/at91_emac.c @@ -159,23 +159,23 @@ at91_emac_t *get_emacbase_by_name(const char *devname) return (at91_emac_t *) netdev->iobase; } -int at91emac_mii_read(const char *devname, unsigned char addr, - unsigned char reg, unsigned short *value) +int at91emac_mii_read(struct mii_dev *bus, int addr, int devad, int reg) { + unsigned short value = 0; at91_emac_t *emac; - emac = get_emacbase_by_name(devname); - at91emac_read(emac , addr, reg, value); - return 0; + emac = get_emacbase_by_name(bus->name); + at91emac_read(emac , addr, reg, &value); + return value; } -int at91emac_mii_write(const char *devname, unsigned char addr, - unsigned char reg, unsigned short value) +int at91emac_mii_write(struct mii_dev *bus, int addr, int devad, int reg, + u16 value) { at91_emac_t *emac; - emac = get_emacbase_by_name(devname); + emac = get_emacbase_by_name(bus->name); at91emac_write(emac, addr, reg, value); return 0; } @@ -502,7 +502,17 @@ int at91emac_register(bd_t *bis, unsigned long iobase) eth_register(dev); #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - miiphy_register(dev->name, at91emac_mii_read, at91emac_mii_write); + int retval; + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; + strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); + mdiodev->read = at91emac_mii_read; + mdiodev->write = at91emac_mii_write; + + retval = mdio_register(mdiodev); + if (retval < 0) + return retval; #endif return 1; } diff --git a/drivers/net/bcm-sf2-eth-gmac.c b/drivers/net/bcm-sf2-eth-gmac.c index 977feec3511..f2853cfad25 100644 --- a/drivers/net/bcm-sf2-eth-gmac.c +++ b/drivers/net/bcm-sf2-eth-gmac.c @@ -596,12 +596,10 @@ bool gmac_mii_busywait(unsigned int timeout) return tmp & (1 << GMAC_MII_BUSY_SHIFT); } -int gmac_miiphy_read(const char *devname, unsigned char phyaddr, - unsigned char reg, unsigned short *value) +int gmac_miiphy_read(struct mii_dev *bus, int phyaddr, int devad, int reg) { uint32_t tmp = 0; - - (void)devname; + u16 value = 0; /* Busy wait timeout is 1ms */ if (gmac_mii_busywait(1000)) { @@ -621,18 +619,16 @@ int gmac_miiphy_read(const char *devname, unsigned char phyaddr, return -1; } - *value = readl(GMAC_MII_DATA_ADDR) & 0xffff; - debug("MII read data 0x%x\n", *value); - return 0; + value = readl(GMAC_MII_DATA_ADDR) & 0xffff; + debug("MII read data 0x%x\n", value); + return value; } -int gmac_miiphy_write(const char *devname, unsigned char phyaddr, - unsigned char reg, unsigned short value) +int gmac_miiphy_write(struct mii_dev *bus, int phyaddr, int devad, int reg, + u16 value) { uint32_t tmp = 0; - (void)devname; - /* Busy wait timeout is 1ms */ if (gmac_mii_busywait(1000)) { error("%s: Prepare MII write: MII/MDIO busy\n", __func__); diff --git a/drivers/net/bcm-sf2-eth.c b/drivers/net/bcm-sf2-eth.c index eab4c1f9003..e2747365a20 100644 --- a/drivers/net/bcm-sf2-eth.c +++ b/drivers/net/bcm-sf2-eth.c @@ -244,7 +244,18 @@ int bcm_sf2_eth_register(bd_t *bis, u8 dev_num) eth_register(dev); #ifdef CONFIG_CMD_MII - miiphy_register(dev->name, eth->miiphy_read, eth->miiphy_write); + int retval; + struct mii_dev *mdiodev = mdio_alloc(); + + if (!mdiodev) + return -ENOMEM; + strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); + mdiodev->read = eth->miiphy_read; + mdiodev->write = eth->miiphy_write; + + retval = mdio_register(mdiodev); + if (retval < 0) + return retval; #endif /* Initialization */ diff --git a/drivers/net/bcm-sf2-eth.h b/drivers/net/bcm-sf2-eth.h index 49a58361326..6104affc51c 100644 --- a/drivers/net/bcm-sf2-eth.h +++ b/drivers/net/bcm-sf2-eth.h @@ -54,10 +54,10 @@ struct eth_info { struct phy_device *port[BCM_ETH_MAX_PORT_NUM]; int port_num; - int (*miiphy_read)(const char *devname, unsigned char phyaddr, - unsigned char reg, unsigned short *value); - int (*miiphy_write)(const char *devname, unsigned char phyaddr, - unsigned char reg, unsigned short value); + int (*miiphy_read)(struct mii_dev *bus, int phyaddr, int devad, + int reg); + int (*miiphy_write)(struct mii_dev *bus, int phyaddr, int devad, + int reg, u16 value); int (*mac_init)(struct eth_device *dev); int (*enable_mac)(void); diff --git a/drivers/net/bfin_mac.c b/drivers/net/bfin_mac.c index 61cb1b0cdad..26a626b4cbd 100644 --- a/drivers/net/bfin_mac.c +++ b/drivers/net/bfin_mac.c @@ -13,6 +13,7 @@ #include <command.h> #include <malloc.h> #include <miiphy.h> +#include <linux/mdio.h> #include <linux/mii.h> #include <asm/blackfin.h> @@ -72,18 +73,20 @@ static int bfin_miiphy_wait(void) return 0; } -static int bfin_miiphy_read(const char *devname, uchar addr, uchar reg, ushort *val) +static int bfin_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg) { + ushort val = 0; if (bfin_miiphy_wait()) return 1; bfin_write_EMAC_STAADD(SET_PHYAD(addr) | SET_REGAD(reg) | STABUSY); if (bfin_miiphy_wait()) return 1; - *val = bfin_read_EMAC_STADAT(); - return 0; + val = bfin_read_EMAC_STADAT(); + return val; } -static int bfin_miiphy_write(const char *devname, uchar addr, uchar reg, ushort val) +static int bfin_miiphy_write(struct mii_dev *bus, int addr, int devad, + int reg, u16 val) { if (bfin_miiphy_wait()) return 1; @@ -113,7 +116,19 @@ int bfin_EMAC_initialize(bd_t *bis) eth_register(dev); #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - miiphy_register(dev->name, bfin_miiphy_read, bfin_miiphy_write); + int retval; + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; + strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); + mdiodev->read = bfin_miiphy_read; + mdiodev->write = bfin_miiphy_write; + + retval = mdio_register(mdiodev); + if (retval < 0) + return retval; + + dev->priv = mdiodev; #endif return 0; @@ -222,8 +237,9 @@ static int bfin_EMAC_recv(struct eth_device *dev) static int bfin_miiphy_init(struct eth_device *dev, int *opmode) { const unsigned short pins[] = CONFIG_BFIN_MAC_PINS; - u16 phydat; + int phydat; size_t count; + struct mii_dev *mdiodev = dev->priv; /* Enable PHY output */ bfin_write_VR_CTL(bfin_read_VR_CTL() | CLKBUFOE); @@ -236,12 +252,15 @@ static int bfin_miiphy_init(struct eth_device *dev, int *opmode) bfin_write_EMAC_SYSCTL(RXDWA | RXCKS | SET_MDCDIV(MDC_FREQ_TO_DIV(CONFIG_PHY_CLOCK_FREQ))); /* turn on auto-negotiation and wait for link to come up */ - bfin_miiphy_write(dev->name, CONFIG_PHY_ADDR, MII_BMCR, BMCR_ANENABLE); + bfin_miiphy_write(mdiodev, CONFIG_PHY_ADDR, MDIO_DEVAD_NONE, MII_BMCR, + BMCR_ANENABLE); count = 0; while (1) { ++count; - if (bfin_miiphy_read(dev->name, CONFIG_PHY_ADDR, MII_BMSR, &phydat)) - return -1; + phydat = bfin_miiphy_read(mdiodev, CONFIG_PHY_ADDR, + MDIO_DEVAD_NONE, MII_BMSR); + if (phydat < 0) + return phydat; if (phydat & BMSR_LSTATUS) break; if (count > 30000) { @@ -252,8 +271,10 @@ static int bfin_miiphy_init(struct eth_device *dev, int *opmode) } /* see what kind of link we have */ - if (bfin_miiphy_read(dev->name, CONFIG_PHY_ADDR, MII_LPA, &phydat)) - return -1; + phydat = bfin_miiphy_read(mdiodev, CONFIG_PHY_ADDR, MDIO_DEVAD_NONE, + MII_LPA); + if (phydat < 0) + return phydat; if (phydat & LPA_DUPLEX) *opmode = FDMODE; else diff --git a/drivers/net/cpsw.c b/drivers/net/cpsw.c index 2ce4ec69f1d..81ccc61a60d 100644 --- a/drivers/net/cpsw.c +++ b/drivers/net/cpsw.c @@ -22,6 +22,7 @@ #include <netdev.h> #include <cpsw.h> #include <asm/errno.h> +#include <asm/gpio.h> #include <asm/io.h> #include <phy.h> #include <asm/arch/cpu.h> @@ -907,7 +908,7 @@ static int _cpsw_send(struct cpsw_priv *priv, void *packet, int length) int timeout = CPDMA_TIMEOUT; flush_dcache_range((unsigned long)packet, - (unsigned long)packet + length); + (unsigned long)packet + ALIGN(length, PKTALIGN)); /* first reap completed packets */ while (timeout-- && @@ -1145,19 +1146,22 @@ static const struct eth_ops cpsw_eth_ops = { static inline fdt_addr_t cpsw_get_addr_by_node(const void *fdt, int node) { - return fdtdec_get_addr_size_auto_noparent(fdt, node, "reg", 0, NULL); + return fdtdec_get_addr_size_auto_noparent(fdt, node, "reg", 0, NULL, + false); } static int cpsw_eth_ofdata_to_platdata(struct udevice *dev) { struct eth_pdata *pdata = dev_get_platdata(dev); struct cpsw_priv *priv = dev_get_priv(dev); + struct gpio_desc *mode_gpios; const char *phy_mode; const void *fdt = gd->fdt_blob; int node = dev->of_offset; int subnode; int slave_index = 0; int active_slave; + int num_mode_gpios; int ret; pdata->iobase = dev_get_addr(dev); @@ -1203,6 +1207,15 @@ static int cpsw_eth_ofdata_to_platdata(struct udevice *dev) return -ENOENT; } + num_mode_gpios = gpio_get_list_count(dev, "mode-gpios"); + if (num_mode_gpios > 0) { + mode_gpios = malloc(sizeof(struct gpio_desc) * + num_mode_gpios); + gpio_request_list_by_name(dev, "mode-gpios", mode_gpios, + num_mode_gpios, GPIOD_IS_OUT); + free(mode_gpios); + } + active_slave = fdtdec_get_int(fdt, node, "active_slave", 0); priv->data.active_slave = active_slave; diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c index b0304984028..ca457b85d21 100644 --- a/drivers/net/davinci_emac.c +++ b/drivers/net/davinci_emac.c @@ -243,11 +243,10 @@ int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data) if (tmp & MDIO_USERACCESS0_ACK) { *data = tmp & 0xffff; - return(1); + return 0; } - *data = -1; - return(0); + return -EIO; } /* Write to a PHY register via MDIO inteface. Blocks until operation is complete. */ @@ -268,7 +267,7 @@ int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data) while (readl(&adap_mdio->USERACCESS0) & MDIO_USERACCESS0_GO) ; - return(1); + return 0; } /* PHY functions for a generic PHY */ @@ -390,14 +389,20 @@ static int gen_auto_negotiate(int phy_addr) #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) -static int davinci_mii_phy_read(const char *devname, unsigned char addr, unsigned char reg, unsigned short *value) +static int davinci_mii_phy_read(struct mii_dev *bus, int addr, int devad, + int reg) { - return(davinci_eth_phy_read(addr, reg, value) ? 0 : 1); + unsigned short value = 0; + int retval = davinci_eth_phy_read(addr, reg, &value); + if (retval < 0) + return retval; + return value; } -static int davinci_mii_phy_write(const char *devname, unsigned char addr, unsigned char reg, unsigned short value) +static int davinci_mii_phy_write(struct mii_dev *bus, int addr, int devad, + int reg, u16 value) { - return(davinci_eth_phy_write(addr, reg, value) ? 0 : 1); + return davinci_eth_phy_write(addr, reg, value); } #endif @@ -883,8 +888,17 @@ int davinci_emac_initialize(void) debug("Ethernet PHY: %s\n", phy[i].name); - miiphy_register(phy[i].name, davinci_mii_phy_read, - davinci_mii_phy_write); + int retval; + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; + strncpy(mdiodev->name, phy[i].name, MDIO_NAME_LEN); + mdiodev->read = davinci_mii_phy_read; + mdiodev->write = davinci_mii_phy_write; + + retval = mdio_register(mdiodev); + if (retval < 0) + return retval; } #if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 196989b3864..3332ad95d46 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -5513,7 +5513,8 @@ static int do_e1000(cmd_tbl_t *cmdtp, int flag, struct udevice *dev; char name[30]; int ret; -#else +#endif +#if !defined(CONFIG_DM_ETH) || defined(CONFIG_E1000_SPI) struct e1000_hw *hw; #endif int cardnum; @@ -5549,6 +5550,9 @@ static int do_e1000(cmd_tbl_t *cmdtp, int flag, } #ifdef CONFIG_E1000_SPI +#ifdef CONFIG_DM_ETH + hw = dev_get_priv(dev); +#endif /* Handle the "SPI" subcommand */ if (!strcmp(argv[2], "spi")) return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3); diff --git a/drivers/net/e1000_spi.c b/drivers/net/e1000_spi.c index 576ddb8b242..cb5f93d6523 100644 --- a/drivers/net/e1000_spi.c +++ b/drivers/net/e1000_spi.c @@ -94,17 +94,17 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, /* Make sure it has an SPI chip */ if (hw->eeprom.type != e1000_eeprom_spi) { - E1000_ERR(hw->nic, "No attached SPI EEPROM found!\n"); + E1000_ERR(hw, "No attached SPI EEPROM found!\n"); return NULL; } /* Argument sanity checks */ if (cs != 0) { - E1000_ERR(hw->nic, "No such SPI chip: %u\n", cs); + E1000_ERR(hw, "No such SPI chip: %u\n", cs); return NULL; } if (mode != SPI_MODE_0) { - E1000_ERR(hw->nic, "Only SPI MODE-0 is supported!\n"); + E1000_ERR(hw, "Only SPI MODE-0 is supported!\n"); return NULL; } @@ -124,7 +124,7 @@ int spi_claim_bus(struct spi_slave *spi) struct e1000_hw *hw = e1000_hw_from_spi(spi); if (e1000_acquire_eeprom(hw)) { - E1000_ERR(hw->nic, "EEPROM SPI cannot be acquired!\n"); + E1000_ERR(hw, "EEPROM SPI cannot be acquired!\n"); return -1; } @@ -342,41 +342,41 @@ static int do_e1000_spi_show(cmd_tbl_t *cmdtp, struct e1000_hw *hw, /* Extra sanity checks */ if (!length) { - E1000_ERR(hw->nic, "Requested zero-sized dump!\n"); + E1000_ERR(hw, "Requested zero-sized dump!\n"); return 1; } if ((0x10000 < length) || (0x10000 - length < offset)) { - E1000_ERR(hw->nic, "Can't dump past 0xFFFF!\n"); + E1000_ERR(hw, "Can't dump past 0xFFFF!\n"); return 1; } /* Allocate a buffer to hold stuff */ buffer = malloc(length); if (!buffer) { - E1000_ERR(hw->nic, "Out of Memory!\n"); + E1000_ERR(hw, "Out of Memory!\n"); return 1; } /* Acquire the EEPROM and perform the dump */ if (e1000_acquire_eeprom(hw)) { - E1000_ERR(hw->nic, "EEPROM SPI cannot be acquired!\n"); + E1000_ERR(hw, "EEPROM SPI cannot be acquired!\n"); free(buffer); return 1; } err = e1000_spi_eeprom_dump(hw, buffer, offset, length, true); e1000_release_eeprom(hw); if (err) { - E1000_ERR(hw->nic, "Interrupted!\n"); + E1000_ERR(hw, "Interrupted!\n"); free(buffer); return 1; } /* Now hexdump the result */ printf("%s: ===== Intel e1000 EEPROM (0x%04hX - 0x%04hX) =====", - hw->nic->name, offset, offset + length - 1); + hw->name, offset, offset + length - 1); for (i = 0; i < length; i++) { if ((i & 0xF) == 0) - printf("\n%s: %04hX: ", hw->nic->name, offset + i); + printf("\n%s: %04hX: ", hw->name, offset + i); else if ((i & 0xF) == 0x8) printf(" "); printf(" %02hx", buffer[i]); @@ -407,29 +407,29 @@ static int do_e1000_spi_dump(cmd_tbl_t *cmdtp, struct e1000_hw *hw, /* Extra sanity checks */ if (!length) { - E1000_ERR(hw->nic, "Requested zero-sized dump!\n"); + E1000_ERR(hw, "Requested zero-sized dump!\n"); return 1; } if ((0x10000 < length) || (0x10000 - length < offset)) { - E1000_ERR(hw->nic, "Can't dump past 0xFFFF!\n"); + E1000_ERR(hw, "Can't dump past 0xFFFF!\n"); return 1; } /* Acquire the EEPROM */ if (e1000_acquire_eeprom(hw)) { - E1000_ERR(hw->nic, "EEPROM SPI cannot be acquired!\n"); + E1000_ERR(hw, "EEPROM SPI cannot be acquired!\n"); return 1; } /* Perform the programming operation */ if (e1000_spi_eeprom_dump(hw, dest, offset, length, true) < 0) { - E1000_ERR(hw->nic, "Interrupted!\n"); + E1000_ERR(hw, "Interrupted!\n"); e1000_release_eeprom(hw); return 1; } e1000_release_eeprom(hw); - printf("%s: ===== EEPROM DUMP COMPLETE =====\n", hw->nic->name); + printf("%s: ===== EEPROM DUMP COMPLETE =====\n", hw->name); return 0; } @@ -452,19 +452,19 @@ static int do_e1000_spi_program(cmd_tbl_t *cmdtp, struct e1000_hw *hw, /* Acquire the EEPROM */ if (e1000_acquire_eeprom(hw)) { - E1000_ERR(hw->nic, "EEPROM SPI cannot be acquired!\n"); + E1000_ERR(hw, "EEPROM SPI cannot be acquired!\n"); return 1; } /* Perform the programming operation */ if (e1000_spi_eeprom_program(hw, source, offset, length, true) < 0) { - E1000_ERR(hw->nic, "Interrupted!\n"); + E1000_ERR(hw, "Interrupted!\n"); e1000_release_eeprom(hw); return 1; } e1000_release_eeprom(hw); - printf("%s: ===== EEPROM PROGRAMMED =====\n", hw->nic->name); + printf("%s: ===== EEPROM PROGRAMMED =====\n", hw->name); return 0; } @@ -488,19 +488,19 @@ static int do_e1000_spi_checksum(cmd_tbl_t *cmdtp, struct e1000_hw *hw, length = sizeof(uint16_t) * (EEPROM_CHECKSUM_REG + 1); buffer = malloc(length); if (!buffer) { - E1000_ERR(hw->nic, "Unable to allocate EEPROM buffer!\n"); + E1000_ERR(hw, "Unable to allocate EEPROM buffer!\n"); return 1; } /* Acquire the EEPROM */ if (e1000_acquire_eeprom(hw)) { - E1000_ERR(hw->nic, "EEPROM SPI cannot be acquired!\n"); + E1000_ERR(hw, "EEPROM SPI cannot be acquired!\n"); return 1; } /* Read the EEPROM */ if (e1000_spi_eeprom_dump(hw, buffer, 0, length, true) < 0) { - E1000_ERR(hw->nic, "Interrupted!\n"); + E1000_ERR(hw, "Interrupted!\n"); e1000_release_eeprom(hw); return 1; } @@ -514,15 +514,15 @@ static int do_e1000_spi_checksum(cmd_tbl_t *cmdtp, struct e1000_hw *hw, /* Verify it! */ if (checksum_reg == checksum) { printf("%s: INFO: EEPROM checksum is correct! (0x%04hx)\n", - hw->nic->name, checksum); + hw->name, checksum); e1000_release_eeprom(hw); return 0; } /* Hrm, verification failed, print an error */ - E1000_ERR(hw->nic, "EEPROM checksum is incorrect!\n"); - E1000_ERR(hw->nic, " ...register was 0x%04hx, calculated 0x%04hx\n", - checksum_reg, checksum); + E1000_ERR(hw, "EEPROM checksum is incorrect!\n"); + E1000_ERR(hw, " ...register was 0x%04hx, calculated 0x%04hx\n", + checksum_reg, checksum); /* If they didn't ask us to update it, just return an error */ if (!upd) { @@ -531,11 +531,11 @@ static int do_e1000_spi_checksum(cmd_tbl_t *cmdtp, struct e1000_hw *hw, } /* Ok, correct it! */ - printf("%s: Reprogramming the EEPROM checksum...\n", hw->nic->name); + printf("%s: Reprogramming the EEPROM checksum...\n", hw->name); buffer[i] = cpu_to_le16(checksum); if (e1000_spi_eeprom_program(hw, &buffer[i], i * sizeof(uint16_t), sizeof(uint16_t), true)) { - E1000_ERR(hw->nic, "Interrupted!\n"); + E1000_ERR(hw, "Interrupted!\n"); e1000_release_eeprom(hw); return 1; } @@ -554,7 +554,8 @@ int do_e1000_spi(cmd_tbl_t *cmdtp, struct e1000_hw *hw, /* Make sure it has an SPI chip */ if (hw->eeprom.type != e1000_eeprom_spi) { - E1000_ERR(hw->nic, "No attached SPI EEPROM found!\n"); + E1000_ERR(hw, "No attached SPI EEPROM found (%d)!\n", + hw->eeprom.type); return 1; } diff --git a/drivers/net/eepro100.c b/drivers/net/eepro100.c index d4a6386810b..0f350cba53e 100644 --- a/drivers/net/eepro100.c +++ b/drivers/net/eepro100.c @@ -334,34 +334,35 @@ static struct eth_device* verify_phyaddr (const char *devname, return dev; } -static int eepro100_miiphy_read(const char *devname, unsigned char addr, - unsigned char reg, unsigned short *value) +static int eepro100_miiphy_read(struct mii_dev *bus, int addr, int devad, + int reg) { + unsigned short value = 0; struct eth_device *dev; - dev = verify_phyaddr(devname, addr); + dev = verify_phyaddr(bus->name, addr); if (dev == NULL) return -1; - if (get_phyreg(dev, addr, reg, value) != 0) { - printf("%s: mii read timeout!\n", devname); + if (get_phyreg(dev, addr, reg, &value) != 0) { + printf("%s: mii read timeout!\n", bus->name); return -1; } - return 0; + return value; } -static int eepro100_miiphy_write(const char *devname, unsigned char addr, - unsigned char reg, unsigned short value) +static int eepro100_miiphy_write(struct mii_dev *bus, int addr, int devad, + int reg, u16 value) { struct eth_device *dev; - dev = verify_phyaddr(devname, addr); + dev = verify_phyaddr(bus->name, addr); if (dev == NULL) return -1; if (set_phyreg(dev, addr, reg, value) != 0) { - printf("%s: mii write timeout!\n", devname); + printf("%s: mii write timeout!\n", bus->name); return -1; } @@ -451,8 +452,17 @@ int eepro100_initialize (bd_t * bis) #if defined (CONFIG_MII) || defined(CONFIG_CMD_MII) /* register mii command access routines */ - miiphy_register(dev->name, - eepro100_miiphy_read, eepro100_miiphy_write); + int retval; + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; + strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); + mdiodev->read = eepro100_miiphy_read; + mdiodev->write = eepro100_miiphy_write; + + retval = mdio_register(mdiodev); + if (retval < 0) + return retval; #endif card_number++; diff --git a/drivers/net/enc28j60.c b/drivers/net/enc28j60.c index 611eabb5460..2fe323a85a5 100644 --- a/drivers/net/enc28j60.c +++ b/drivers/net/enc28j60.c @@ -742,9 +742,10 @@ static int enc_initcheck(enc_dev_t *enc, const enum enc_initstate requiredstate) * * This function is registered with miiphy_register(). */ -int enc_miiphy_read(const char *devname, u8 phy_adr, u8 reg, u16 *value) +int enc_miiphy_read(struct mii_dev *bus, int phy_adr, int devad, int reg) { - struct eth_device *dev = eth_get_dev_by_name(devname); + u16 value = 0; + struct eth_device *dev = eth_get_dev_by_name(bus->name); enc_dev_t *enc; if (!dev || phy_adr != 0) @@ -757,9 +758,9 @@ int enc_miiphy_read(const char *devname, u8 phy_adr, u8 reg, u16 *value) enc_release_bus(enc); return -1; } - *value = enc_phy_read(enc, reg); + value = enc_phy_read(enc, reg); enc_release_bus(enc); - return 0; + return value; } /* @@ -767,9 +768,10 @@ int enc_miiphy_read(const char *devname, u8 phy_adr, u8 reg, u16 *value) * * This function is registered with miiphy_register(). */ -int enc_miiphy_write(const char *devname, u8 phy_adr, u8 reg, u16 value) +int enc_miiphy_write(struct mii_dev *bus, int phy_adr, int devad, int reg, + u16 value) { - struct eth_device *dev = eth_get_dev_by_name(devname); + struct eth_device *dev = eth_get_dev_by_name(bus->name); enc_dev_t *enc; if (!dev || phy_adr != 0) @@ -958,7 +960,17 @@ int enc28j60_initialize(unsigned int bus, unsigned int cs, sprintf(dev->name, "enc%i.%i", bus, cs); eth_register(dev); #if defined(CONFIG_CMD_MII) - miiphy_register(dev->name, enc_miiphy_read, enc_miiphy_write); + int retval; + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; + strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); + mdiodev->read = enc_miiphy_read; + mdiodev->write = enc_miiphy_write; + + retval = mdio_register(mdiodev); + if (retval < 0) + return retval; #endif return 0; } diff --git a/drivers/net/ep93xx_eth.c b/drivers/net/ep93xx_eth.c index a3721c5513c..a94191b9e67 100644 --- a/drivers/net/ep93xx_eth.c +++ b/drivers/net/ep93xx_eth.c @@ -30,10 +30,10 @@ #define GET_REGS(eth_dev) (GET_PRIV(eth_dev)->regs) /* ep93xx_miiphy ops forward declarations */ -static int ep93xx_miiphy_read(const char * const dev, unsigned char const addr, - unsigned char const reg, unsigned short * const value); -static int ep93xx_miiphy_write(const char * const dev, unsigned char const addr, - unsigned char const reg, unsigned short const value); +static int ep93xx_miiphy_read(struct mii_dev *bus, int addr, int devad, + int reg); +static int ep93xx_miiphy_write(struct mii_dev *bus, int addr, int devad, + int reg, u16 value); #if defined(EP93XX_MAC_DEBUG) /** @@ -421,7 +421,17 @@ eth_send_out: #if defined(CONFIG_MII) int ep93xx_miiphy_initialize(bd_t * const bd) { - miiphy_register("ep93xx_eth0", ep93xx_miiphy_read, ep93xx_miiphy_write); + int retval; + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; + strncpy(mdiodev->name, "ep93xx_eth0", MDIO_NAME_LEN); + mdiodev->read = ep93xx_miiphy_read; + mdiodev->write = ep93xx_miiphy_write; + + retval = mdio_register(mdiodev); + if (retval < 0) + return retval; return 0; } #endif @@ -542,9 +552,10 @@ eth_init_done: /** * Read a 16-bit value from an MII register. */ -static int ep93xx_miiphy_read(const char * const dev, unsigned char const addr, - unsigned char const reg, unsigned short * const value) +static int ep93xx_miiphy_read(struct mii_dev *bus, int addr, int devad, + int reg) { + unsigned short value = 0; struct mac_regs *mac = (struct mac_regs *)MAC_BASE; int ret = -1; uint32_t self_ctl; @@ -552,10 +563,9 @@ static int ep93xx_miiphy_read(const char * const dev, unsigned char const addr, debug("+ep93xx_miiphy_read"); /* Parameter checks */ - BUG_ON(dev == NULL); + BUG_ON(bus->name == NULL); BUG_ON(addr > MII_ADDRESS_MAX); BUG_ON(reg > MII_REGISTER_MAX); - BUG_ON(value == NULL); /* * Save the current SelfCTL register value. Set MAC to suppress @@ -579,7 +589,7 @@ static int ep93xx_miiphy_read(const char * const dev, unsigned char const addr, while (readl(&mac->miists) & MIISTS_BUSY) ; /* noop */ - *value = (unsigned short)readl(&mac->miidata); + value = (unsigned short)readl(&mac->miidata); /* Restore the saved SelfCTL value and return. */ writel(self_ctl, &mac->selfctl); @@ -588,14 +598,16 @@ static int ep93xx_miiphy_read(const char * const dev, unsigned char const addr, /* Fall through */ debug("-ep93xx_miiphy_read"); - return ret; + if (ret < 0) + return ret; + return value; } /** * Write a 16-bit value to an MII register. */ -static int ep93xx_miiphy_write(const char * const dev, unsigned char const addr, - unsigned char const reg, unsigned short const value) +static int ep93xx_miiphy_write(struct mii_dev *bus, int addr, int devad, + int reg, u16 value) { struct mac_regs *mac = (struct mac_regs *)MAC_BASE; int ret = -1; @@ -604,7 +616,7 @@ static int ep93xx_miiphy_write(const char * const dev, unsigned char const addr, debug("+ep93xx_miiphy_write"); /* Parameter checks */ - BUG_ON(dev == NULL); + BUG_ON(bus->name == NULL); BUG_ON(addr > MII_ADDRESS_MAX); BUG_ON(reg > MII_REGISTER_MAX); diff --git a/drivers/net/ethoc.c b/drivers/net/ethoc.c index edb3c808fa1..ad8c462a609 100644 --- a/drivers/net/ethoc.c +++ b/drivers/net/ethoc.c @@ -5,19 +5,20 @@ * Copyright (C) 2008-2009 Avionic Design GmbH * Thierry Reding <thierry.reding@avionic-design.de> * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw> + * Copyright (C) 2016 Cadence Design Systems Inc. * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> -#include <command.h> +#include <dm/device.h> +#include <dm/platform_data/net_ethoc.h> +#include <linux/io.h> #include <malloc.h> #include <net.h> #include <miiphy.h> -#include <asm/io.h> #include <asm/cache.h> +#include <wait_bit.h> /* register offsets */ #define MODER 0x00 @@ -162,6 +163,7 @@ #define ETHOC_BD_BASE 0x400 #define ETHOC_TIMEOUT (HZ / 2) #define ETHOC_MII_TIMEOUT (1 + (HZ / 5)) +#define ETHOC_IOSIZE 0x54 /** * struct ethoc - driver-private device structure @@ -177,6 +179,14 @@ struct ethoc { u32 dty_tx; u32 num_rx; u32 cur_rx; + void __iomem *iobase; + void __iomem *packet; + phys_addr_t packet_phys; + +#ifdef CONFIG_PHYLIB + struct mii_dev *bus; + struct phy_device *phydev; +#endif }; /** @@ -189,65 +199,68 @@ struct ethoc_bd { u32 addr; }; -static inline u32 ethoc_read(struct eth_device *dev, size_t offset) +static inline u32 *ethoc_reg(struct ethoc *priv, size_t offset) { - return readl(dev->iobase + offset); + return priv->iobase + offset; } -static inline void ethoc_write(struct eth_device *dev, size_t offset, u32 data) +static inline u32 ethoc_read(struct ethoc *priv, size_t offset) { - writel(data, dev->iobase + offset); + return readl(ethoc_reg(priv, offset)); } -static inline void ethoc_read_bd(struct eth_device *dev, int index, +static inline void ethoc_write(struct ethoc *priv, size_t offset, u32 data) +{ + writel(data, ethoc_reg(priv, offset)); +} + +static inline void ethoc_read_bd(struct ethoc *priv, int index, struct ethoc_bd *bd) { size_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd)); - bd->stat = ethoc_read(dev, offset + 0); - bd->addr = ethoc_read(dev, offset + 4); + bd->stat = ethoc_read(priv, offset + 0); + bd->addr = ethoc_read(priv, offset + 4); } -static inline void ethoc_write_bd(struct eth_device *dev, int index, +static inline void ethoc_write_bd(struct ethoc *priv, int index, const struct ethoc_bd *bd) { size_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd)); - ethoc_write(dev, offset + 0, bd->stat); - ethoc_write(dev, offset + 4, bd->addr); + ethoc_write(priv, offset + 0, bd->stat); + ethoc_write(priv, offset + 4, bd->addr); } -static int ethoc_set_mac_address(struct eth_device *dev) +static int ethoc_write_hwaddr_common(struct ethoc *priv, u8 *mac) { - u8 *mac = dev->enetaddr; - - ethoc_write(dev, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) | + ethoc_write(priv, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | (mac[5] << 0)); - ethoc_write(dev, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0)); + ethoc_write(priv, MAC_ADDR1, (mac[0] << 8) | (mac[1] << 0)); return 0; } -static inline void ethoc_ack_irq(struct eth_device *dev, u32 mask) +static inline void ethoc_ack_irq(struct ethoc *priv, u32 mask) { - ethoc_write(dev, INT_SOURCE, mask); + ethoc_write(priv, INT_SOURCE, mask); } -static inline void ethoc_enable_rx_and_tx(struct eth_device *dev) +static inline void ethoc_enable_rx_and_tx(struct ethoc *priv) { - u32 mode = ethoc_read(dev, MODER); + u32 mode = ethoc_read(priv, MODER); mode |= MODER_RXEN | MODER_TXEN; - ethoc_write(dev, MODER, mode); + ethoc_write(priv, MODER, mode); } -static inline void ethoc_disable_rx_and_tx(struct eth_device *dev) +static inline void ethoc_disable_rx_and_tx(struct ethoc *priv) { - u32 mode = ethoc_read(dev, MODER); + u32 mode = ethoc_read(priv, MODER); mode &= ~(MODER_RXEN | MODER_TXEN); - ethoc_write(dev, MODER, mode); + ethoc_write(priv, MODER, mode); } -static int ethoc_init_ring(struct eth_device *dev) +static int ethoc_init_ring(struct ethoc *priv) { - struct ethoc *priv = (struct ethoc *)dev->priv; struct ethoc_bd bd; + phys_addr_t addr = priv->packet_phys; int i; priv->cur_tx = 0; @@ -256,66 +269,92 @@ static int ethoc_init_ring(struct eth_device *dev) /* setup transmission buffers */ bd.stat = TX_BD_IRQ | TX_BD_CRC; + bd.addr = 0; for (i = 0; i < priv->num_tx; i++) { + if (addr) { + bd.addr = addr; + addr += PKTSIZE_ALIGN; + } if (i == priv->num_tx - 1) bd.stat |= TX_BD_WRAP; - ethoc_write_bd(dev, i, &bd); + ethoc_write_bd(priv, i, &bd); } bd.stat = RX_BD_EMPTY | RX_BD_IRQ; for (i = 0; i < priv->num_rx; i++) { - bd.addr = (u32)net_rx_packets[i]; + if (addr) { + bd.addr = addr; + addr += PKTSIZE_ALIGN; + } else { + bd.addr = virt_to_phys(net_rx_packets[i]); + } if (i == priv->num_rx - 1) bd.stat |= RX_BD_WRAP; - flush_dcache_range(bd.addr, bd.addr + PKTSIZE_ALIGN); - ethoc_write_bd(dev, priv->num_tx + i, &bd); + flush_dcache_range((ulong)net_rx_packets[i], + (ulong)net_rx_packets[i] + PKTSIZE_ALIGN); + ethoc_write_bd(priv, priv->num_tx + i, &bd); } return 0; } -static int ethoc_reset(struct eth_device *dev) +static int ethoc_reset(struct ethoc *priv) { u32 mode; /* TODO: reset controller? */ - ethoc_disable_rx_and_tx(dev); + ethoc_disable_rx_and_tx(priv); /* TODO: setup registers */ /* enable FCS generation and automatic padding */ - mode = ethoc_read(dev, MODER); + mode = ethoc_read(priv, MODER); mode |= MODER_CRC | MODER_PAD; - ethoc_write(dev, MODER, mode); + ethoc_write(priv, MODER, mode); /* set full-duplex mode */ - mode = ethoc_read(dev, MODER); + mode = ethoc_read(priv, MODER); mode |= MODER_FULLD; - ethoc_write(dev, MODER, mode); - ethoc_write(dev, IPGT, 0x15); + ethoc_write(priv, MODER, mode); + ethoc_write(priv, IPGT, 0x15); - ethoc_ack_irq(dev, INT_MASK_ALL); - ethoc_enable_rx_and_tx(dev); + ethoc_ack_irq(priv, INT_MASK_ALL); + ethoc_enable_rx_and_tx(priv); return 0; } -static int ethoc_init(struct eth_device *dev, bd_t * bd) +static int ethoc_init_common(struct ethoc *priv) { - struct ethoc *priv = (struct ethoc *)dev->priv; - printf("ethoc\n"); + int ret = 0; priv->num_tx = 1; priv->num_rx = PKTBUFSRX; - ethoc_write(dev, TX_BD_NUM, priv->num_tx); - ethoc_init_ring(dev); - ethoc_reset(dev); + ethoc_write(priv, TX_BD_NUM, priv->num_tx); + ethoc_init_ring(priv); + ethoc_reset(priv); + +#ifdef CONFIG_PHYLIB + ret = phy_startup(priv->phydev); + if (ret) { + printf("Could not initialize PHY %s\n", + priv->phydev->dev->name); + return ret; + } +#endif + return ret; +} - return 0; +static void ethoc_stop_common(struct ethoc *priv) +{ + ethoc_disable_rx_and_tx(priv); +#ifdef CONFIG_PHYLIB + phy_shutdown(priv->phydev); +#endif } static int ethoc_update_rx_stats(struct ethoc_bd *bd) @@ -353,37 +392,46 @@ static int ethoc_update_rx_stats(struct ethoc_bd *bd) return ret; } -static int ethoc_rx(struct eth_device *dev, int limit) +static int ethoc_rx_common(struct ethoc *priv, uchar **packetp) { - struct ethoc *priv = (struct ethoc *)dev->priv; - int count; - - for (count = 0; count < limit; ++count) { - u32 entry; - struct ethoc_bd bd; - - entry = priv->num_tx + (priv->cur_rx % priv->num_rx); - ethoc_read_bd(dev, entry, &bd); - if (bd.stat & RX_BD_EMPTY) - break; + struct ethoc_bd bd; + u32 i = priv->cur_rx % priv->num_rx; + u32 entry = priv->num_tx + i; + + ethoc_read_bd(priv, entry, &bd); + if (bd.stat & RX_BD_EMPTY) + return -EAGAIN; + + debug("%s(): RX buffer %d, %x received\n", + __func__, priv->cur_rx, bd.stat); + if (ethoc_update_rx_stats(&bd) == 0) { + int size = bd.stat >> 16; + + size -= 4; /* strip the CRC */ + if (priv->packet) + *packetp = priv->packet + entry * PKTSIZE_ALIGN; + else + *packetp = net_rx_packets[i]; + return size; + } else { + return 0; + } +} - debug("%s(): RX buffer %d, %x received\n", - __func__, priv->cur_rx, bd.stat); - if (ethoc_update_rx_stats(&bd) == 0) { - int size = bd.stat >> 16; - size -= 4; /* strip the CRC */ - net_process_received_packet((void *)bd.addr, size); - } +static int ethoc_is_new_packet_received(struct ethoc *priv) +{ + u32 pending; - /* clear the buffer descriptor so it can be reused */ - flush_dcache_range(bd.addr, bd.addr + PKTSIZE_ALIGN); - bd.stat &= ~RX_BD_STATS; - bd.stat |= RX_BD_EMPTY; - ethoc_write_bd(dev, entry, &bd); - priv->cur_rx++; + pending = ethoc_read(priv, INT_SOURCE); + ethoc_ack_irq(priv, pending); + if (pending & INT_MASK_BUSY) + debug("%s(): packet dropped\n", __func__); + if (pending & INT_MASK_RX) { + debug("%s(): rx irq\n", __func__); + return 1; } - return count; + return 0; } static int ethoc_update_tx_stats(struct ethoc_bd *bd) @@ -403,52 +451,57 @@ static int ethoc_update_tx_stats(struct ethoc_bd *bd) return 0; } -static void ethoc_tx(struct eth_device *dev) +static void ethoc_tx(struct ethoc *priv) { - struct ethoc *priv = (struct ethoc *)dev->priv; u32 entry = priv->dty_tx % priv->num_tx; struct ethoc_bd bd; - ethoc_read_bd(dev, entry, &bd); + ethoc_read_bd(priv, entry, &bd); if ((bd.stat & TX_BD_READY) == 0) (void)ethoc_update_tx_stats(&bd); } -static int ethoc_send(struct eth_device *dev, void *packet, int length) +static int ethoc_send_common(struct ethoc *priv, void *packet, int length) { - struct ethoc *priv = (struct ethoc *)dev->priv; struct ethoc_bd bd; u32 entry; u32 pending; int tmo; entry = priv->cur_tx % priv->num_tx; - ethoc_read_bd(dev, entry, &bd); + ethoc_read_bd(priv, entry, &bd); if (unlikely(length < ETHOC_ZLEN)) bd.stat |= TX_BD_PAD; else bd.stat &= ~TX_BD_PAD; - bd.addr = (u32)packet; - flush_dcache_range(bd.addr, bd.addr + length); + if (priv->packet) { + void *p = priv->packet + entry * PKTSIZE_ALIGN; + + memcpy(p, packet, length); + packet = p; + } else { + bd.addr = virt_to_phys(packet); + } + flush_dcache_range((ulong)packet, (ulong)packet + length); bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK); bd.stat |= TX_BD_LEN(length); - ethoc_write_bd(dev, entry, &bd); + ethoc_write_bd(priv, entry, &bd); /* start transmit */ bd.stat |= TX_BD_READY; - ethoc_write_bd(dev, entry, &bd); + ethoc_write_bd(priv, entry, &bd); /* wait for transfer to succeed */ tmo = get_timer(0) + 5 * CONFIG_SYS_HZ; while (1) { - pending = ethoc_read(dev, INT_SOURCE); - ethoc_ack_irq(dev, pending & ~INT_MASK_RX); + pending = ethoc_read(priv, INT_SOURCE); + ethoc_ack_irq(priv, pending & ~INT_MASK_RX); if (pending & INT_MASK_BUSY) debug("%s(): packet dropped\n", __func__); if (pending & INT_MASK_TX) { - ethoc_tx(dev); + ethoc_tx(priv); break; } if (get_timer(0) >= tmo) { @@ -461,24 +514,290 @@ static int ethoc_send(struct eth_device *dev, void *packet, int length) return 0; } +static int ethoc_free_pkt_common(struct ethoc *priv) +{ + struct ethoc_bd bd; + u32 i = priv->cur_rx % priv->num_rx; + u32 entry = priv->num_tx + i; + void *src; + + ethoc_read_bd(priv, entry, &bd); + + if (priv->packet) + src = priv->packet + entry * PKTSIZE_ALIGN; + else + src = net_rx_packets[i]; + /* clear the buffer descriptor so it can be reused */ + flush_dcache_range((ulong)src, + (ulong)src + PKTSIZE_ALIGN); + bd.stat &= ~RX_BD_STATS; + bd.stat |= RX_BD_EMPTY; + ethoc_write_bd(priv, entry, &bd); + priv->cur_rx++; + + return 0; +} + +#ifdef CONFIG_PHYLIB + +static int ethoc_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) +{ + struct ethoc *priv = bus->priv; + int rc; + + ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(addr, reg)); + ethoc_write(priv, MIICOMMAND, MIICOMMAND_READ); + + rc = wait_for_bit(__func__, ethoc_reg(priv, MIISTATUS), + MIISTATUS_BUSY, false, CONFIG_SYS_HZ, false); + + if (rc == 0) { + u32 data = ethoc_read(priv, MIIRX_DATA); + + /* reset MII command register */ + ethoc_write(priv, MIICOMMAND, 0); + return data; + } + return rc; +} + +static int ethoc_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, + u16 val) +{ + struct ethoc *priv = bus->priv; + int rc; + + ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(addr, reg)); + ethoc_write(priv, MIITX_DATA, val); + ethoc_write(priv, MIICOMMAND, MIICOMMAND_WRITE); + + rc = wait_for_bit(__func__, ethoc_reg(priv, MIISTATUS), + MIISTATUS_BUSY, false, CONFIG_SYS_HZ, false); + + if (rc == 0) { + /* reset MII command register */ + ethoc_write(priv, MIICOMMAND, 0); + } + return rc; +} + +static int ethoc_mdio_init(const char *name, struct ethoc *priv) +{ + struct mii_dev *bus = mdio_alloc(); + int ret; + + if (!bus) { + printf("Failed to allocate MDIO bus\n"); + return -ENOMEM; + } + + bus->read = ethoc_mdio_read; + bus->write = ethoc_mdio_write; + snprintf(bus->name, sizeof(bus->name), "%s", name); + bus->priv = priv; + + ret = mdio_register(bus); + if (ret < 0) + return ret; + + priv->bus = miiphy_get_dev_by_name(name); + return 0; +} + +static int ethoc_phy_init(struct ethoc *priv, void *dev) +{ + struct phy_device *phydev; + int mask = 0xffffffff; + +#ifdef CONFIG_PHY_ADDR + mask = 1 << CONFIG_PHY_ADDR; +#endif + + phydev = phy_find_by_mask(priv->bus, mask, PHY_INTERFACE_MODE_MII); + if (!phydev) + return -ENODEV; + + phy_connect_dev(phydev, dev); + + phydev->supported &= PHY_BASIC_FEATURES; + phydev->advertising = phydev->supported; + + priv->phydev = phydev; + phy_config(phydev); + + return 0; +} + +#else + +static inline int ethoc_mdio_init(const char *name, struct ethoc *priv) +{ + return 0; +} + +static inline int ethoc_phy_init(struct ethoc *priv, void *dev) +{ + return 0; +} + +#endif + +#ifdef CONFIG_DM_ETH + +static int ethoc_write_hwaddr(struct udevice *dev) +{ + struct ethoc_eth_pdata *pdata = dev_get_platdata(dev); + struct ethoc *priv = dev_get_priv(dev); + u8 *mac = pdata->eth_pdata.enetaddr; + + return ethoc_write_hwaddr_common(priv, mac); +} + +static int ethoc_send(struct udevice *dev, void *packet, int length) +{ + return ethoc_send_common(dev_get_priv(dev), packet, length); +} + +static int ethoc_free_pkt(struct udevice *dev, uchar *packet, int length) +{ + return ethoc_free_pkt_common(dev_get_priv(dev)); +} + +static int ethoc_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct ethoc *priv = dev_get_priv(dev); + + if (flags & ETH_RECV_CHECK_DEVICE) + if (!ethoc_is_new_packet_received(priv)) + return -EAGAIN; + + return ethoc_rx_common(priv, packetp); +} + +static int ethoc_start(struct udevice *dev) +{ + return ethoc_init_common(dev_get_priv(dev)); +} + +static void ethoc_stop(struct udevice *dev) +{ + ethoc_stop_common(dev_get_priv(dev)); +} + +static int ethoc_ofdata_to_platdata(struct udevice *dev) +{ + struct ethoc_eth_pdata *pdata = dev_get_platdata(dev); + fdt_addr_t addr; + + pdata->eth_pdata.iobase = dev_get_addr(dev); + addr = dev_get_addr_index(dev, 1); + if (addr != FDT_ADDR_T_NONE) + pdata->packet_base = addr; + return 0; +} + +static int ethoc_probe(struct udevice *dev) +{ + struct ethoc_eth_pdata *pdata = dev_get_platdata(dev); + struct ethoc *priv = dev_get_priv(dev); + + priv->iobase = ioremap(pdata->eth_pdata.iobase, ETHOC_IOSIZE); + if (pdata->packet_base) { + priv->packet_phys = pdata->packet_base; + priv->packet = ioremap(pdata->packet_base, + (1 + PKTBUFSRX) * PKTSIZE_ALIGN); + } + + ethoc_mdio_init(dev->name, priv); + ethoc_phy_init(priv, dev); + + return 0; +} + +static int ethoc_remove(struct udevice *dev) +{ + struct ethoc *priv = dev_get_priv(dev); + +#ifdef CONFIG_PHYLIB + free(priv->phydev); + mdio_unregister(priv->bus); + mdio_free(priv->bus); +#endif + iounmap(priv->iobase); + return 0; +} + +static const struct eth_ops ethoc_ops = { + .start = ethoc_start, + .stop = ethoc_stop, + .send = ethoc_send, + .recv = ethoc_recv, + .free_pkt = ethoc_free_pkt, + .write_hwaddr = ethoc_write_hwaddr, +}; + +static const struct udevice_id ethoc_ids[] = { + { .compatible = "opencores,ethoc" }, + { } +}; + +U_BOOT_DRIVER(ethoc) = { + .name = "ethoc", + .id = UCLASS_ETH, + .of_match = ethoc_ids, + .ofdata_to_platdata = ethoc_ofdata_to_platdata, + .probe = ethoc_probe, + .remove = ethoc_remove, + .ops = ðoc_ops, + .priv_auto_alloc_size = sizeof(struct ethoc), + .platdata_auto_alloc_size = sizeof(struct ethoc_eth_pdata), +}; + +#else + +static int ethoc_init(struct eth_device *dev, bd_t *bd) +{ + struct ethoc *priv = (struct ethoc *)dev->priv; + + return ethoc_init_common(priv); +} + +static int ethoc_write_hwaddr(struct eth_device *dev) +{ + struct ethoc *priv = (struct ethoc *)dev->priv; + u8 *mac = dev->enetaddr; + + return ethoc_write_hwaddr_common(priv, mac); +} + +static int ethoc_send(struct eth_device *dev, void *packet, int length) +{ + return ethoc_send_common(dev->priv, packet, length); +} + static void ethoc_halt(struct eth_device *dev) { - ethoc_disable_rx_and_tx(dev); + ethoc_disable_rx_and_tx(dev->priv); } static int ethoc_recv(struct eth_device *dev) { - u32 pending; + struct ethoc *priv = (struct ethoc *)dev->priv; + int count; - pending = ethoc_read(dev, INT_SOURCE); - ethoc_ack_irq(dev, pending); - if (pending & INT_MASK_BUSY) - debug("%s(): packet dropped\n", __func__); - if (pending & INT_MASK_RX) { - debug("%s(): rx irq\n", __func__); - ethoc_rx(dev, PKTBUFSRX); - } + if (!ethoc_is_new_packet_received(priv)) + return 0; + + for (count = 0; count < PKTBUFSRX; ++count) { + uchar *packetp; + int size = ethoc_rx_common(priv, &packetp); + if (size < 0) + break; + if (size > 0) + net_process_received_packet(packetp, size); + ethoc_free_pkt_common(priv); + } return 0; } @@ -503,9 +822,16 @@ int ethoc_initialize(u8 dev_num, int base_addr) dev->halt = ethoc_halt; dev->send = ethoc_send; dev->recv = ethoc_recv; - dev->write_hwaddr = ethoc_set_mac_address; + dev->write_hwaddr = ethoc_write_hwaddr; sprintf(dev->name, "%s-%hu", "ETHOC", dev_num); + priv->iobase = ioremap(dev->iobase, ETHOC_IOSIZE); eth_register(dev); + + ethoc_mdio_init(dev->name, priv); + ethoc_phy_init(priv, dev); + return 1; } + +#endif diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 360f8e44d10..e871b3e81be 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -233,6 +233,7 @@ static int miiphy_restart_aneg(struct eth_device *dev) return ret; } +#ifndef CONFIG_FEC_FIXED_SPEED static int miiphy_wait_aneg(struct eth_device *dev) { uint32_t start; @@ -260,6 +261,7 @@ static int miiphy_wait_aneg(struct eth_device *dev) return 0; } +#endif /* CONFIG_FEC_FIXED_SPEED */ #endif static int fec_rx_task_enable(struct fec_priv *fec) @@ -502,6 +504,8 @@ static int fec_open(struct eth_device *edev) } speed = fec->phydev->speed; } +#elif CONFIG_FEC_FIXED_SPEED + speed = CONFIG_FEC_FIXED_SPEED; #else miiphy_wait_aneg(edev); speed = miiphy_speed(edev->name, fec->phy_id); diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile index 493cdc6d48e..344fbe20a56 100644 --- a/drivers/net/fm/Makefile +++ b/drivers/net/fm/Makefile @@ -39,3 +39,4 @@ obj-$(CONFIG_PPC_T4080) += t4240.o obj-$(CONFIG_PPC_B4420) += b4860.o obj-$(CONFIG_PPC_B4860) += b4860.o obj-$(CONFIG_LS1043A) += ls1043.o +obj-$(CONFIG_LS1046A) += ls1046.o diff --git a/drivers/net/fm/ls1046.c b/drivers/net/fm/ls1046.c new file mode 100644 index 00000000000..bf555548b7b --- /dev/null +++ b/drivers/net/fm/ls1046.c @@ -0,0 +1,123 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <phy.h> +#include <fm_eth.h> +#include <asm/io.h> +#include <asm/arch/fsl_serdes.h> + +#define FSL_CHASSIS2_RCWSR13_EC1 0xe0000000 /* bits 416..418 */ +#define FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII 0x00000000 +#define FSL_CHASSIS2_RCWSR13_EC1_GPIO 0x20000000 +#define FSL_CHASSIS2_RCWSR13_EC1_FTM 0xa0000000 +#define FSL_CHASSIS2_RCWSR13_EC2 0x1c000000 /* bits 419..421 */ +#define FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII 0x00000000 +#define FSL_CHASSIS2_RCWSR13_EC2_GPIO 0x04000000 +#define FSL_CHASSIS2_RCWSR13_EC2_1588 0x08000000 +#define FSL_CHASSIS2_RCWSR13_EC2_FTM 0x14000000 + +u32 port_to_devdisr[] = { + [FM1_DTSEC1] = FSL_CHASSIS2_DEVDISR2_DTSEC1_1, + [FM1_DTSEC2] = FSL_CHASSIS2_DEVDISR2_DTSEC1_2, + [FM1_DTSEC3] = FSL_CHASSIS2_DEVDISR2_DTSEC1_3, + [FM1_DTSEC4] = FSL_CHASSIS2_DEVDISR2_DTSEC1_4, + [FM1_DTSEC5] = FSL_CHASSIS2_DEVDISR2_DTSEC1_5, + [FM1_DTSEC6] = FSL_CHASSIS2_DEVDISR2_DTSEC1_6, + [FM1_DTSEC9] = FSL_CHASSIS2_DEVDISR2_DTSEC1_9, + [FM1_DTSEC10] = FSL_CHASSIS2_DEVDISR2_DTSEC1_10, + [FM1_10GEC1] = FSL_CHASSIS2_DEVDISR2_10GEC1_1, + [FM1_10GEC2] = FSL_CHASSIS2_DEVDISR2_10GEC1_2, + [FM1_10GEC3] = FSL_CHASSIS2_DEVDISR2_10GEC1_3, + [FM1_10GEC4] = FSL_CHASSIS2_DEVDISR2_10GEC1_4, +}; + +static int is_device_disabled(enum fm_port port) +{ + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 devdisr2 = in_be32(&gur->devdisr2); + + return port_to_devdisr[port] & devdisr2; +} + +void fman_disable_port(enum fm_port port) +{ + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + + setbits_be32(&gur->devdisr2, port_to_devdisr[port]); +} + +phy_interface_t fman_port_enet_if(enum fm_port port) +{ + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 rcwsr13 = in_be32(&gur->rcwsr[13]); + + if (is_device_disabled(port)) + return PHY_INTERFACE_MODE_NONE; + + if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC9))) + return PHY_INTERFACE_MODE_XGMII; + + if ((port == FM1_DTSEC9) && (is_serdes_configured(XFI_FM1_MAC9))) + return PHY_INTERFACE_MODE_NONE; + + if ((port == FM1_10GEC2) && (is_serdes_configured(XFI_FM1_MAC10))) + return PHY_INTERFACE_MODE_XGMII; + + if ((port == FM1_DTSEC10) && (is_serdes_configured(XFI_FM1_MAC10))) + return PHY_INTERFACE_MODE_NONE; + + if (port == FM1_DTSEC3) + if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) == + FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII) + return PHY_INTERFACE_MODE_RGMII; + + if (port == FM1_DTSEC4) + if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC2) == + FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII) + return PHY_INTERFACE_MODE_RGMII; + + /* handle SGMII, only MAC 2/5/6/9/10 available */ + switch (port) { + case FM1_DTSEC2: + case FM1_DTSEC5: + case FM1_DTSEC6: + case FM1_DTSEC9: + case FM1_DTSEC10: + if (is_serdes_configured(SGMII_FM1_DTSEC2 + port - FM1_DTSEC2)) + return PHY_INTERFACE_MODE_SGMII; + break; + default: + break; + } + + /* handle 2.5G SGMII, only MAC 5/9/10 available */ + switch (port) { + case FM1_DTSEC5: + case FM1_DTSEC9: + case FM1_DTSEC10: + if (is_serdes_configured(SGMII_2500_FM1_DTSEC5 + + port - FM1_DTSEC5)) + return PHY_INTERFACE_MODE_SGMII_2500; + break; + default: + break; + } + + /* handle QSGMII, only MAC 1/5/6/10 available */ + switch (port) { + case FM1_DTSEC1: + case FM1_DTSEC5: + case FM1_DTSEC6: + case FM1_DTSEC10: + if (is_serdes_configured(QSGMII_FM1_A)) + return PHY_INTERFACE_MODE_QSGMII; + break; + default: + break; + } + + return PHY_INTERFACE_MODE_NONE; +} diff --git a/drivers/net/fsl_mcdmafec.c b/drivers/net/fsl_mcdmafec.c index 792534b1395..15a3ce03ae3 100644 --- a/drivers/net/fsl_mcdmafec.c +++ b/drivers/net/fsl_mcdmafec.c @@ -556,8 +556,17 @@ int mcdmafec_initialize(bd_t * bis) eth_register(dev); #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - miiphy_register(dev->name, - mcffec_miiphy_read, mcffec_miiphy_write); + int retval; + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; + strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); + mdiodev->read = mcffec_miiphy_read; + mdiodev->write = mcffec_miiphy_write; + + retval = mdio_register(mdiodev); + if (retval < 0) + return retval; #endif if (i > 0) diff --git a/drivers/net/ftmac110.c b/drivers/net/ftmac110.c index 4f17015bc59..8fa767a1fe7 100644 --- a/drivers/net/ftmac110.c +++ b/drivers/net/ftmac110.c @@ -364,32 +364,35 @@ static int ftmac110_recv(struct eth_device *dev) #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) -static int ftmac110_mdio_read( - const char *devname, uint8_t addr, uint8_t reg, uint16_t *value) +static int ftmac110_mdio_read(struct mii_dev *bus, int addr, int devad, + int reg) { + uint16_t value = 0; int ret = 0; struct eth_device *dev; - dev = eth_get_dev_by_name(devname); + dev = eth_get_dev_by_name(bus->name); if (dev == NULL) { - printf("%s: no such device\n", devname); + printf("%s: no such device\n", bus->name); ret = -1; } else { - *value = mdio_read(dev, addr, reg); + value = mdio_read(dev, addr, reg); } - return ret; + if (ret < 0) + return ret; + return value; } -static int ftmac110_mdio_write( - const char *devname, uint8_t addr, uint8_t reg, uint16_t value) +static int ftmac110_mdio_write(struct mii_dev *bus, int addr, int devad, + int reg, u16 value) { int ret = 0; struct eth_device *dev; - dev = eth_get_dev_by_name(devname); + dev = eth_get_dev_by_name(bus->name); if (dev == NULL) { - printf("%s: no such device\n", devname); + printf("%s: no such device\n", bus->name); ret = -1; } else { mdio_write(dev, addr, reg, value); @@ -468,7 +471,17 @@ int ftmac110_initialize(bd_t *bis) eth_register(dev); #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - miiphy_register(dev->name, ftmac110_mdio_read, ftmac110_mdio_write); + int retval; + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; + strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); + mdiodev->read = ftmac110_mdio_read; + mdiodev->write = ftmac110_mdio_write; + + retval = mdio_register(mdiodev); + if (retval < 0) + return retval; #endif card_nr++; diff --git a/drivers/net/keystone_net.c b/drivers/net/keystone_net.c index 6b28df0f969..e41b7d1365d 100644 --- a/drivers/net/keystone_net.c +++ b/drivers/net/keystone_net.c @@ -11,6 +11,7 @@ #include <console.h> #include <dm.h> +#include <dm/lists.h> #include <net.h> #include <phy.h> @@ -765,6 +766,8 @@ static int ks2_eth_start(struct udevice *dev) hw_config_streaming_switch(); if (priv->has_mdio) { + keystone2_mdio_reset(priv->mdio_bus); + phy_startup(priv->phydev); if (priv->phydev->link == 0) { error("phy startup failed\n"); @@ -906,27 +909,38 @@ static int ks2_eth_probe(struct udevice *dev) pll_pa_clk_sel(); - priv->net_rx_buffs.buff_ptr = rx_buffs, - priv->net_rx_buffs.num_buffs = RX_BUFF_NUMS, - priv->net_rx_buffs.buff_len = RX_BUFF_LEN, + priv->net_rx_buffs.buff_ptr = rx_buffs; + priv->net_rx_buffs.num_buffs = RX_BUFF_NUMS; + priv->net_rx_buffs.buff_len = RX_BUFF_LEN; - /* Register MDIO bus */ - mdio_bus = mdio_alloc(); - if (!mdio_bus) { - error("MDIO alloc failed\n"); - return -ENOMEM; - } - priv->mdio_bus = mdio_bus; - mdio_bus->read = keystone2_mdio_read; - mdio_bus->write = keystone2_mdio_write; - mdio_bus->reset = keystone2_mdio_reset; - mdio_bus->priv = priv->mdio_base; - sprintf(mdio_bus->name, "ethernet-mdio"); - - ret = mdio_register(mdio_bus); - if (ret) { - error("MDIO bus register failed\n"); - return ret; + if (priv->slave_port == 1) { + /* + * Register MDIO bus for slave 0 only, other slave have + * to re-use the same + */ + mdio_bus = mdio_alloc(); + if (!mdio_bus) { + error("MDIO alloc failed\n"); + return -ENOMEM; + } + priv->mdio_bus = mdio_bus; + mdio_bus->read = keystone2_mdio_read; + mdio_bus->write = keystone2_mdio_write; + mdio_bus->reset = keystone2_mdio_reset; + mdio_bus->priv = priv->mdio_base; + sprintf(mdio_bus->name, "ethernet-mdio"); + + ret = mdio_register(mdio_bus); + if (ret) { + error("MDIO bus register failed\n"); + return ret; + } + } else { + /* Get the MDIO bus from slave 0 device */ + struct ks2_eth_priv *parent_priv; + + parent_priv = dev_get_priv(dev->parent); + priv->mdio_bus = parent_priv->mdio_bus; } #ifndef CONFIG_SOC_K2G @@ -935,8 +949,11 @@ static int ks2_eth_probe(struct udevice *dev) priv->netcp_pktdma = &netcp_pktdma; - priv->phydev = phy_connect(mdio_bus, priv->phy_addr, dev, priv->phy_if); - phy_config(priv->phydev); + if (priv->has_mdio) { + priv->phydev = phy_connect(priv->mdio_bus, priv->phy_addr, + dev, priv->phy_if); + phy_config(priv->phydev); + } return 0; } @@ -962,39 +979,103 @@ static const struct eth_ops ks2_eth_ops = { .write_hwaddr = ks2_eth_write_hwaddr, }; - -static int ks2_eth_ofdata_to_platdata(struct udevice *dev) +static int ks2_eth_bind_slaves(struct udevice *dev, int gbe, int *gbe_0) { - struct ks2_eth_priv *priv = dev_get_priv(dev); - struct eth_pdata *pdata = dev_get_platdata(dev); const void *fdt = gd->fdt_blob; + struct udevice *sl_dev; int interfaces; - int interface_0; - int netcp_gbe_0; - int phy; + int sec_slave; + int slave; + int ret; + char *slave_name; + + interfaces = fdt_subnode_offset(fdt, gbe, "interfaces"); + fdt_for_each_subnode(fdt, slave, interfaces) { + int slave_no; + + slave_no = fdtdec_get_int(fdt, slave, "slave-port", -ENOENT); + if (slave_no == -ENOENT) + continue; + + if (slave_no == 0) { + /* This is the current eth device */ + *gbe_0 = slave; + } else { + /* Slave devices to be registered */ + slave_name = malloc(20); + snprintf(slave_name, 20, "netcp@slave-%d", slave_no); + ret = device_bind_driver_to_node(dev, "eth_ks2_sl", + slave_name, slave, + &sl_dev); + if (ret) { + error("ks2_net - not able to bind slave interfaces\n"); + return ret; + } + } + } + + sec_slave = fdt_subnode_offset(fdt, gbe, "secondary-slave-ports"); + fdt_for_each_subnode(fdt, slave, sec_slave) { + int slave_no; + + slave_no = fdtdec_get_int(fdt, slave, "slave-port", -ENOENT); + if (slave_no == -ENOENT) + continue; + + /* Slave devices to be registered */ + slave_name = malloc(20); + snprintf(slave_name, 20, "netcp@slave-%d", slave_no); + ret = device_bind_driver_to_node(dev, "eth_ks2_sl", slave_name, + slave, &sl_dev); + if (ret) { + error("ks2_net - not able to bind slave interfaces\n"); + return ret; + } + } + + return 0; +} + +static int ks2_eth_parse_slave_interface(int netcp, int slave, + struct ks2_eth_priv *priv, + struct eth_pdata *pdata) +{ + const void *fdt = gd->fdt_blob; int mdio; - u32 dma_channel[6]; + int phy; + int dma_count; + u32 dma_channel[8]; - interfaces = fdt_subnode_offset(fdt, dev->of_offset, - "netcp-interfaces"); - interface_0 = fdt_subnode_offset(fdt, interfaces, "interface-0"); + priv->slave_port = fdtdec_get_int(fdt, slave, "slave-port", -1); + priv->net_rx_buffs.rx_flow = priv->slave_port * 8; - netcp_gbe_0 = fdtdec_lookup_phandle(fdt, interface_0, "netcp-gbe"); - priv->link_type = fdtdec_get_int(fdt, netcp_gbe_0, - "link-interface", -1); - priv->slave_port = fdtdec_get_int(fdt, netcp_gbe_0, "slave-port", -1); /* U-Boot slave port number starts with 1 instead of 0 */ priv->slave_port += 1; - phy = fdtdec_lookup_phandle(fdt, netcp_gbe_0, "phy-handle"); - priv->phy_addr = fdtdec_get_int(fdt, phy, "reg", -1); + dma_count = fdtdec_get_int_array_count(fdt, netcp, + "ti,navigator-dmas", + dma_channel, 8); - mdio = fdt_parent_offset(fdt, phy); - if (mdio < 0) { - error("mdio dt not found\n"); - return -ENODEV; + if (dma_count > (2 * priv->slave_port)) { + int dma_idx; + + dma_idx = priv->slave_port * 2 - 1; + priv->net_rx_buffs.rx_flow = dma_channel[dma_idx]; + } + + priv->link_type = fdtdec_get_int(fdt, slave, "link-interface", -1); + + phy = fdtdec_lookup_phandle(fdt, slave, "phy-handle"); + if (phy >= 0) { + priv->phy_addr = fdtdec_get_int(fdt, phy, "reg", -1); + + mdio = fdt_parent_offset(fdt, phy); + if (mdio < 0) { + error("mdio dt not found\n"); + return -ENODEV; + } + priv->mdio_base = (void *)fdtdec_get_addr(fdt, mdio, "reg"); } - priv->mdio_base = (void *)fdtdec_get_addr(fdt, mdio, "reg"); if (priv->link_type == LINK_TYPE_MAC_TO_PHY_MODE) { priv->phy_if = PHY_INTERFACE_MODE_SGMII; @@ -1002,11 +1083,51 @@ static int ks2_eth_ofdata_to_platdata(struct udevice *dev) priv->sgmii_link_type = SGMII_LINK_MAC_PHY; priv->has_mdio = true; } - pdata->iobase = dev_get_addr(dev); - fdtdec_get_int_array(fdt, dev->of_offset, "ti,navigator-dmas", - dma_channel, 6); - priv->net_rx_buffs.rx_flow = dma_channel[1]; + return 0; +} + +static int ks2_sl_eth_ofdata_to_platdata(struct udevice *dev) +{ + struct ks2_eth_priv *priv = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + const void *fdt = gd->fdt_blob; + int slave = dev->of_offset; + int interfaces; + int gbe; + int netcp_devices; + int netcp; + + interfaces = fdt_parent_offset(fdt, slave); + gbe = fdt_parent_offset(fdt, interfaces); + netcp_devices = fdt_parent_offset(fdt, gbe); + netcp = fdt_parent_offset(fdt, netcp_devices); + + ks2_eth_parse_slave_interface(netcp, slave, priv, pdata); + + pdata->iobase = fdtdec_get_addr(fdt, netcp, "reg"); + + return 0; +} + +static int ks2_eth_ofdata_to_platdata(struct udevice *dev) +{ + struct ks2_eth_priv *priv = dev_get_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + const void *fdt = gd->fdt_blob; + int gbe_0 = -ENODEV; + int netcp_devices; + int gbe; + + netcp_devices = fdt_subnode_offset(fdt, dev->of_offset, + "netcp-devices"); + gbe = fdt_subnode_offset(fdt, netcp_devices, "gbe"); + + ks2_eth_bind_slaves(dev, gbe, &gbe_0); + + ks2_eth_parse_slave_interface(dev->of_offset, gbe_0, priv, pdata); + + pdata->iobase = dev_get_addr(dev); return 0; } @@ -1016,6 +1137,17 @@ static const struct udevice_id ks2_eth_ids[] = { { } }; +U_BOOT_DRIVER(eth_ks2_slave) = { + .name = "eth_ks2_sl", + .id = UCLASS_ETH, + .ofdata_to_platdata = ks2_sl_eth_ofdata_to_platdata, + .probe = ks2_eth_probe, + .remove = ks2_eth_remove, + .ops = &ks2_eth_ops, + .priv_auto_alloc_size = sizeof(struct ks2_eth_priv), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; U_BOOT_DRIVER(eth_ks2) = { .name = "eth_ks2", diff --git a/drivers/net/lpc32xx_eth.c b/drivers/net/lpc32xx_eth.c index 6cc273c33c8..2dd69f3816e 100644 --- a/drivers/net/lpc32xx_eth.c +++ b/drivers/net/lpc32xx_eth.c @@ -226,9 +226,11 @@ DECLARE_GLOBAL_DATA_PTR; * * Returns 16bit phy register value, or 0xffff on error */ -static int mii_reg_read(const char *devname, u8 phy_adr, u8 reg_ofs, u16 *data) +static int mii_reg_read(struct mii_dev *bus, int phy_adr, int devad, + int reg_ofs) { - struct eth_device *dev = eth_get_dev_by_name(devname); + u16 data = 0; + struct eth_device *dev = eth_get_dev_by_name(bus->name); struct lpc32xx_eth_device *dlpc32xx_eth = to_lpc32xx_eth(dev); struct lpc32xx_eth_registers *regs = dlpc32xx_eth->regs; u32 mind_reg; @@ -270,12 +272,12 @@ static int mii_reg_read(const char *devname, u8 phy_adr, u8 reg_ofs, u16 *data) return -EFAULT; } - *data = (u16) readl(®s->mrdd); + data = (u16) readl(®s->mrdd); debug("%s:(adr %d, off %d) => %04x\n", __func__, phy_adr, - reg_ofs, *data); + reg_ofs, data); - return 0; + return data; } /* @@ -284,9 +286,10 @@ static int mii_reg_read(const char *devname, u8 phy_adr, u8 reg_ofs, u16 *data) * Returns 0 if write succeed, -EINVAL on bad parameters * -ETIME on timeout */ -static int mii_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data) +static int mii_reg_write(struct mii_dev *bus, int phy_adr, int devad, + int reg_ofs, u16 data) { - struct eth_device *dev = eth_get_dev_by_name(devname); + struct eth_device *dev = eth_get_dev_by_name(bus->name); struct lpc32xx_eth_device *dlpc32xx_eth = to_lpc32xx_eth(dev); struct lpc32xx_eth_registers *regs = dlpc32xx_eth->regs; u32 mind_reg; @@ -333,25 +336,6 @@ static int mii_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data) } #endif -#if defined(CONFIG_PHYLIB) -int lpc32xx_eth_phy_read(struct mii_dev *bus, int phy_addr, int dev_addr, - int reg_addr) -{ - u16 data; - int ret; - ret = mii_reg_read(bus->name, phy_addr, reg_addr, &data); - if (ret) - return ret; - return data; -} - -int lpc32xx_eth_phy_write(struct mii_dev *bus, int phy_addr, int dev_addr, - int reg_addr, u16 data) -{ - return mii_reg_write(bus->name, phy_addr, reg_addr, data); -} -#endif - /* * Provide default Ethernet buffers base address if target did not. * Locate buffers in SRAM at 0x00001000 to avoid cache issues and @@ -580,8 +564,8 @@ int lpc32xx_eth_phylib_init(struct eth_device *dev, int phyid) printf("mdio_alloc failed\n"); return -ENOMEM; } - bus->read = lpc32xx_eth_phy_read; - bus->write = lpc32xx_eth_phy_write; + bus->read = mii_reg_read; + bus->write = mii_reg_write; strcpy(bus->name, dev->name); ret = mdio_register(bus); @@ -645,7 +629,17 @@ int lpc32xx_eth_initialize(bd_t *bis) #if defined(CONFIG_PHYLIB) lpc32xx_eth_phylib_init(dev, CONFIG_PHY_ADDR); #elif defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - miiphy_register(dev->name, mii_reg_read, mii_reg_write); + int retval; + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; + strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); + mdiodev->read = mii_reg_read; + mdiodev->write = mii_reg_write; + + retval = mdio_register(mdiodev); + if (retval < 0) + return retval; #endif return 0; diff --git a/drivers/net/macb.c b/drivers/net/macb.c index 0835fdc3060..921537f8a43 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -43,6 +43,8 @@ #include "macb.h" +DECLARE_GLOBAL_DATA_PTR; + #define MACB_RX_BUFFER_SIZE 4096 #define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128) #define MACB_TX_RING_SIZE 16 @@ -108,6 +110,10 @@ struct macb_device { #endif unsigned short phy_addr; struct mii_dev *bus; + +#ifdef CONFIG_DM_ETH + phy_interface_t phy_interface; +#endif }; #ifndef CONFIG_DM_ETH #define to_macb(_nd) container_of(_nd, struct macb_device, netdev) @@ -199,39 +205,41 @@ void __weak arch_get_mdio_control(const char *name) #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) -int macb_miiphy_read(const char *devname, u8 phy_adr, u8 reg, u16 *value) +int macb_miiphy_read(struct mii_dev *bus, int phy_adr, int devad, int reg) { + u16 value = 0; #ifdef CONFIG_DM_ETH - struct udevice *dev = eth_get_dev_by_name(devname); + struct udevice *dev = eth_get_dev_by_name(bus->name); struct macb_device *macb = dev_get_priv(dev); #else - struct eth_device *dev = eth_get_dev_by_name(devname); + struct eth_device *dev = eth_get_dev_by_name(bus->name); struct macb_device *macb = to_macb(dev); #endif if (macb->phy_addr != phy_adr) return -1; - arch_get_mdio_control(devname); - *value = macb_mdio_read(macb, reg); + arch_get_mdio_control(bus->name); + value = macb_mdio_read(macb, reg); - return 0; + return value; } -int macb_miiphy_write(const char *devname, u8 phy_adr, u8 reg, u16 value) +int macb_miiphy_write(struct mii_dev *bus, int phy_adr, int devad, int reg, + u16 value) { #ifdef CONFIG_DM_ETH - struct udevice *dev = eth_get_dev_by_name(devname); + struct udevice *dev = eth_get_dev_by_name(bus->name); struct macb_device *macb = dev_get_priv(dev); #else - struct eth_device *dev = eth_get_dev_by_name(devname); + struct eth_device *dev = eth_get_dev_by_name(bus->name); struct macb_device *macb = to_macb(dev); #endif if (macb->phy_addr != phy_adr) return -1; - arch_get_mdio_control(devname); + arch_get_mdio_control(bus->name); macb_mdio_write(macb, reg, value); return 0; @@ -434,7 +442,7 @@ static void macb_phy_reset(struct macb_device *macb, const char *name) } #ifdef CONFIG_MACB_SEARCH_PHY -static int macb_phy_find(struct macb_device *macb) +static int macb_phy_find(struct macb_device *macb, const char *name) { int i; u16 phy_id; @@ -444,21 +452,27 @@ static int macb_phy_find(struct macb_device *macb) macb->phy_addr = i; phy_id = macb_mdio_read(macb, MII_PHYSID1); if (phy_id != 0xffff) { - printf("%s: PHY present at %d\n", macb->netdev.name, i); + printf("%s: PHY present at %d\n", name, i); return 1; } } /* PHY isn't up to snuff */ - printf("%s: PHY not found\n", macb->netdev.name); + printf("%s: PHY not found\n", name); return 0; } #endif /* CONFIG_MACB_SEARCH_PHY */ - +#ifdef CONFIG_DM_ETH +static int macb_phy_init(struct udevice *dev, const char *name) +#else static int macb_phy_init(struct macb_device *macb, const char *name) +#endif { +#ifdef CONFIG_DM_ETH + struct macb_device *macb = dev_get_priv(dev); +#endif #ifdef CONFIG_PHYLIB struct phy_device *phydev; #endif @@ -470,7 +484,7 @@ static int macb_phy_init(struct macb_device *macb, const char *name) arch_get_mdio_control(name); #ifdef CONFIG_MACB_SEARCH_PHY /* Auto-detect phy_addr */ - if (!macb_phy_find(macb)) + if (!macb_phy_find(macb, name)) return 0; #endif /* CONFIG_MACB_SEARCH_PHY */ @@ -482,9 +496,14 @@ static int macb_phy_init(struct macb_device *macb, const char *name) } #ifdef CONFIG_PHYLIB +#ifdef CONFIG_DM_ETH + phydev = phy_connect(macb->bus, macb->phy_addr, dev, + macb->phy_interface); +#else /* need to consider other phy interface mode */ phydev = phy_connect(macb->bus, macb->phy_addr, &macb->netdev, PHY_INTERFACE_MODE_RGMII); +#endif if (!phydev) { printf("phy_connect failed\n"); return -ENODEV; @@ -585,8 +604,15 @@ static int gmac_init_multi_queues(struct macb_device *macb) return 0; } +#ifdef CONFIG_DM_ETH +static int _macb_init(struct udevice *dev, const char *name) +#else static int _macb_init(struct macb_device *macb, const char *name) +#endif { +#ifdef CONFIG_DM_ETH + struct macb_device *macb = dev_get_priv(dev); +#endif unsigned long paddr; int i; @@ -634,13 +660,35 @@ static int _macb_init(struct macb_device *macb, const char *name) * When the GMAC IP without GE feature, this bit is used * to select interface between RMII and MII. */ +#ifdef CONFIG_DM_ETH + if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) + gem_writel(macb, UR, GEM_BIT(RGMII)); + else + gem_writel(macb, UR, 0); +#else #if defined(CONFIG_RGMII) || defined(CONFIG_RMII) gem_writel(macb, UR, GEM_BIT(RGMII)); #else gem_writel(macb, UR, 0); #endif +#endif } else { /* choose RMII or MII mode. This depends on the board */ +#ifdef CONFIG_DM_ETH +#ifdef CONFIG_AT91FAMILY + if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) { + macb_writel(macb, USRIO, + MACB_BIT(RMII) | MACB_BIT(CLKEN)); + } else { + macb_writel(macb, USRIO, MACB_BIT(CLKEN)); + } +#else + if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) + macb_writel(macb, USRIO, 0); + else + macb_writel(macb, USRIO, MACB_BIT(MII)); +#endif +#else #ifdef CONFIG_RMII #ifdef CONFIG_AT91FAMILY macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN)); @@ -654,9 +702,14 @@ static int _macb_init(struct macb_device *macb, const char *name) macb_writel(macb, USRIO, MACB_BIT(MII)); #endif #endif /* CONFIG_RMII */ +#endif } +#ifdef CONFIG_DM_ETH + if (!macb_phy_init(dev, name)) +#else if (!macb_phy_init(macb, name)) +#endif return -1; /* Enable TX and RX */ @@ -862,7 +915,17 @@ int macb_eth_initialize(int id, void *regs, unsigned int phy_addr) eth_register(netdev); #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) - miiphy_register(netdev->name, macb_miiphy_read, macb_miiphy_write); + int retval; + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; + strncpy(mdiodev->name, netdev->name, MDIO_NAME_LEN); + mdiodev->read = macb_miiphy_read; + mdiodev->write = macb_miiphy_write; + + retval = mdio_register(mdiodev); + if (retval < 0) + return retval; macb->bus = miiphy_get_dev_by_name(netdev->name); #endif return 0; @@ -873,9 +936,7 @@ int macb_eth_initialize(int id, void *regs, unsigned int phy_addr) static int macb_start(struct udevice *dev) { - struct macb_device *macb = dev_get_priv(dev); - - return _macb_init(macb, dev->name); + return _macb_init(dev, dev->name); } static int macb_send(struct udevice *dev, void *packet, int length) @@ -933,11 +994,33 @@ static int macb_eth_probe(struct udevice *dev) struct eth_pdata *pdata = dev_get_platdata(dev); struct macb_device *macb = dev_get_priv(dev); +#ifdef CONFIG_DM_ETH + const char *phy_mode; + + phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); + if (phy_mode) + macb->phy_interface = phy_get_interface_by_name(phy_mode); + if (macb->phy_interface == -1) { + debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); + return -EINVAL; + } +#endif + macb->regs = (void *)pdata->iobase; _macb_eth_initialize(macb); #if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB) - miiphy_register(dev->name, macb_miiphy_read, macb_miiphy_write); + int retval; + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; + strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); + mdiodev->read = macb_miiphy_read; + mdiodev->write = macb_miiphy_write; + + retval = mdio_register(mdiodev); + if (retval < 0) + return retval; macb->bus = miiphy_get_dev_by_name(dev->name); #endif diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c index fd730993710..e1b06b25d7c 100644 --- a/drivers/net/mcffec.c +++ b/drivers/net/mcffec.c @@ -595,8 +595,17 @@ int mcffec_initialize(bd_t * bis) eth_register(dev); #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - miiphy_register(dev->name, - mcffec_miiphy_read, mcffec_miiphy_write); + int retval; + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; + strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); + mdiodev->read = mcffec_miiphy_read; + mdiodev->write = mcffec_miiphy_write; + + retval = mdio_register(mdiodev); + if (retval < 0) + return retval; #endif if (i > 0) fec_info[i - 1].next = &fec_info[i]; diff --git a/drivers/net/mcfmii.c b/drivers/net/mcfmii.c index 17a780c854d..103e3651229 100644 --- a/drivers/net/mcfmii.c +++ b/drivers/net/mcfmii.c @@ -277,8 +277,7 @@ void __mii_init(void) * Otherwise they hang in mii_send() !!! Sorry! */ -int mcffec_miiphy_read(const char *devname, unsigned char addr, unsigned char reg, - unsigned short *value) +int mcffec_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg) { short rdreg; /* register working value */ @@ -287,28 +286,22 @@ int mcffec_miiphy_read(const char *devname, unsigned char addr, unsigned char re #endif rdreg = mii_send(mk_mii_read(addr, reg)); - *value = rdreg; - #ifdef MII_DEBUG - printf("0x%04x\n", *value); + printf("0x%04x\n", rdreg); #endif - return 0; + return rdreg; } -int mcffec_miiphy_write(const char *devname, unsigned char addr, unsigned char reg, - unsigned short value) +int mcffec_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg, + u16 value) { #ifdef MII_DEBUG - printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); + printf("miiphy_write(0x%x) @ 0x%x = 0x%04x\n", reg, addr, value); #endif mii_send(mk_mii_write(addr, reg, value)); -#ifdef MII_DEBUG - printf("0x%04x\n", value); -#endif - return 0; } diff --git a/drivers/net/mpc512x_fec.c b/drivers/net/mpc512x_fec.c index e850672a4ff..b3746fbb9a9 100644 --- a/drivers/net/mpc512x_fec.c +++ b/drivers/net/mpc512x_fec.c @@ -22,8 +22,10 @@ DECLARE_GLOBAL_DATA_PTR; #error "CONFIG_MII has to be defined!" #endif -int fec512x_miiphy_read(const char *devname, u8 phyAddr, u8 regAddr, u16 * retVal); -int fec512x_miiphy_write(const char *devname, u8 phyAddr, u8 regAddr, u16 data); +int fec512x_miiphy_read(struct mii_dev *bus, int phyAddr, int devad, + int regAddr); +int fec512x_miiphy_write(struct mii_dev *bus, int phyAddr, int devad, + int regAddr, u16 data); int mpc512x_fec_init_phy(struct eth_device *dev, bd_t * bis); static uchar rx_buff[FEC_BUFFER_SIZE]; @@ -639,8 +641,17 @@ int mpc512x_fec_initialize (bd_t * bis) eth_register (dev); #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - miiphy_register (dev->name, - fec512x_miiphy_read, fec512x_miiphy_write); + int retval; + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; + strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); + mdiodev->read = fec512x_miiphy_read; + mdiodev->write = fec512x_miiphy_write; + + retval = mdio_register(mdiodev); + if (retval < 0) + return retval; #endif /* Clean up space FEC's MIB and FIFO RAM ...*/ @@ -670,8 +681,10 @@ int mpc512x_fec_initialize (bd_t * bis) /* MII-interface related functions */ /********************************************************************/ -int fec512x_miiphy_read(const char *devname, u8 phyAddr, u8 regAddr, u16 *retVal) +int fec512x_miiphy_read(struct mii_dev *bus, int phyAddr, int devad, + int regAddr) { + u16 retVal = 0; volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; volatile fec512x_t *eth = &im->fec; u32 reg; /* convenient holder for the PHY register */ @@ -711,13 +724,14 @@ int fec512x_miiphy_read(const char *devname, u8 phyAddr, u8 regAddr, u16 *retVal /* * it's now safe to read the PHY's register */ - *retVal = (u16) in_be32(ð->mii_data); + retVal = (u16) in_be32(ð->mii_data); - return 0; + return retVal; } /********************************************************************/ -int fec512x_miiphy_write(const char *devname, u8 phyAddr, u8 regAddr, u16 data) +int fec512x_miiphy_write(struct mii_dev *bus, int phyAddr, int devad, + int regAddr, u16 data) { volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; volatile fec512x_t *eth = &im->fec; diff --git a/drivers/net/mpc5xxx_fec.c b/drivers/net/mpc5xxx_fec.c index e13b4cf32b4..d75e858a382 100644 --- a/drivers/net/mpc5xxx_fec.c +++ b/drivers/net/mpc5xxx_fec.c @@ -35,8 +35,10 @@ typedef struct { uint8 head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */ } NBUF; -int fec5xxx_miiphy_read(const char *devname, uint8 phyAddr, uint8 regAddr, uint16 *retVal); -int fec5xxx_miiphy_write(const char *devname, uint8 phyAddr, uint8 regAddr, uint16 data); +int fec5xxx_miiphy_read(struct mii_dev *bus, int phyAddr, int devad, + int regAddr); +int fec5xxx_miiphy_write(struct mii_dev *bus, int phyAddr, int devad, + int regAddr, u16 data); static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis); @@ -917,8 +919,17 @@ int mpc5xxx_fec_initialize(bd_t * bis) eth_register(dev); #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - miiphy_register (dev->name, - fec5xxx_miiphy_read, fec5xxx_miiphy_write); + int retval; + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; + strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); + mdiodev->read = fec5xxx_miiphy_read; + mdiodev->write = fec5xxx_miiphy_write; + + retval = mdio_register(mdiodev); + if (retval < 0) + return retval; #endif /* @@ -941,8 +952,10 @@ int mpc5xxx_fec_initialize(bd_t * bis) /* MII-interface related functions */ /********************************************************************/ -int fec5xxx_miiphy_read(const char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal) +int fec5xxx_miiphy_read(struct mii_dev *bus, int phyAddr, int devad, + int regAddr) { + uint16 retVal = 0; ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC; uint32 reg; /* convenient holder for the PHY register */ uint32 phy; /* convenient holder for the PHY */ @@ -977,13 +990,14 @@ int fec5xxx_miiphy_read(const char *devname, uint8 phyAddr, uint8 regAddr, uint1 /* * it's now safe to read the PHY's register */ - *retVal = (uint16) eth->mii_data; + retVal = (uint16) eth->mii_data; - return 0; + return retVal; } /********************************************************************/ -int fec5xxx_miiphy_write(const char *devname, uint8 phyAddr, uint8 regAddr, uint16 data) +int fec5xxx_miiphy_write(struct mii_dev *bus, int phyAddr, int devad, + int regAddr, u16 data) { ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC; uint32 reg; /* convenient holder for the PHY register */ diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c index b16be921428..a1c7ea054c1 100644 --- a/drivers/net/mvgbe.c +++ b/drivers/net/mvgbe.c @@ -48,9 +48,11 @@ DECLARE_GLOBAL_DATA_PTR; * * Returns 16bit phy register value, or 0xffff on error */ -static int smi_reg_read(const char *devname, u8 phy_adr, u8 reg_ofs, u16 * data) +static int smi_reg_read(struct mii_dev *bus, int phy_adr, int devad, + int reg_ofs) { - struct eth_device *dev = eth_get_dev_by_name(devname); + u16 data = 0; + struct eth_device *dev = eth_get_dev_by_name(bus->name); struct mvgbe_device *dmvgbe = to_mvgbe(dev); struct mvgbe_registers *regs = dmvgbe->regs; u32 smi_reg; @@ -60,8 +62,8 @@ static int smi_reg_read(const char *devname, u8 phy_adr, u8 reg_ofs, u16 * data) if (phy_adr == MV_PHY_ADR_REQUEST && reg_ofs == MV_PHY_ADR_REQUEST) { /* */ - *data = (u16) (MVGBE_REG_RD(regs->phyadr) & PHYADR_MASK); - return 0; + data = (u16) (MVGBE_REG_RD(regs->phyadr) & PHYADR_MASK); + return data; } /* check parameters */ if (phy_adr > PHYADR_MASK) { @@ -111,12 +113,12 @@ static int smi_reg_read(const char *devname, u8 phy_adr, u8 reg_ofs, u16 * data) for (timeout = 0; timeout < MVGBE_PHY_SMI_TIMEOUT; timeout++) ; - *data = (u16) (MVGBE_REG_RD(MVGBE_SMI_REG) & MVGBE_PHY_SMI_DATA_MASK); + data = (u16) (MVGBE_REG_RD(MVGBE_SMI_REG) & MVGBE_PHY_SMI_DATA_MASK); debug("%s:(adr %d, off %d) value= %04x\n", __func__, phy_adr, reg_ofs, - *data); + data); - return 0; + return data; } /* @@ -125,9 +127,10 @@ static int smi_reg_read(const char *devname, u8 phy_adr, u8 reg_ofs, u16 * data) * Returns 0 if write succeed, -EINVAL on bad parameters * -ETIME on timeout */ -static int smi_reg_write(const char *devname, u8 phy_adr, u8 reg_ofs, u16 data) +static int smi_reg_write(struct mii_dev *bus, int phy_adr, int devad, + int reg_ofs, u16 data) { - struct eth_device *dev = eth_get_dev_by_name(devname); + struct eth_device *dev = eth_get_dev_by_name(bus->name); struct mvgbe_device *dmvgbe = to_mvgbe(dev); struct mvgbe_registers *regs = dmvgbe->regs; u32 smi_reg; @@ -785,7 +788,17 @@ error1: #if defined(CONFIG_PHYLIB) mvgbe_phylib_init(dev, PHY_BASE_ADR + devnum); #elif defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - miiphy_register(dev->name, smi_reg_read, smi_reg_write); + int retval; + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; + strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); + mdiodev->read = smi_reg_read; + mdiodev->write = smi_reg_write; + + retval = mdio_register(mdiodev); + if (retval < 0) + return retval; /* Set phy address of the port */ miiphy_write(dev->name, MV_PHY_ADR_REQUEST, MV_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum); diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c index 58d287bb071..4eeb0f6ede8 100644 --- a/drivers/net/phy/marvell.c +++ b/drivers/net/phy/marvell.c @@ -8,6 +8,7 @@ */ #include <config.h> #include <common.h> +#include <errno.h> #include <phy.h> #define PHY_AUTONEGOTIATE_TIMEOUT 5000 diff --git a/drivers/net/phy/miiphybb.c b/drivers/net/phy/miiphybb.c index 5cda0b84692..af676b9baee 100644 --- a/drivers/net/phy/miiphybb.c +++ b/drivers/net/phy/miiphybb.c @@ -230,24 +230,18 @@ static void miiphy_pre(struct bb_miiphy_bus *bus, char read, * Returns: * 0 on success */ -int bb_miiphy_read(const char *devname, unsigned char addr, - unsigned char reg, unsigned short *value) +int bb_miiphy_read(struct mii_dev *miidev, int addr, int devad, int reg) { short rdreg; /* register working value */ int v; int j; /* counter */ struct bb_miiphy_bus *bus; - bus = bb_miiphy_getbus(devname); + bus = bb_miiphy_getbus(miidev->name); if (bus == NULL) { return -1; } - if (value == NULL) { - puts("NULL value pointer\n"); - return -1; - } - miiphy_pre (bus, 1, addr, reg); /* tri-state our MDIO I/O pin so we can read */ @@ -267,8 +261,7 @@ int bb_miiphy_read(const char *devname, unsigned char addr, bus->set_mdc(bus, 1); bus->delay(bus); } - /* There is no PHY, set value to 0xFFFF and return */ - *value = 0xFFFF; + /* There is no PHY, return */ return -1; } @@ -294,13 +287,11 @@ int bb_miiphy_read(const char *devname, unsigned char addr, bus->set_mdc(bus, 1); bus->delay(bus); - *value = rdreg; - #ifdef DEBUG - printf ("miiphy_read(0x%x) @ 0x%x = 0x%04x\n", reg, addr, *value); + printf("miiphy_read(0x%x) @ 0x%x = 0x%04x\n", reg, addr, rdreg); #endif - return 0; + return rdreg; } @@ -311,13 +302,13 @@ int bb_miiphy_read(const char *devname, unsigned char addr, * Returns: * 0 on success */ -int bb_miiphy_write (const char *devname, unsigned char addr, - unsigned char reg, unsigned short value) +int bb_miiphy_write(struct mii_dev *miidev, int addr, int devad, int reg, + u16 value) { struct bb_miiphy_bus *bus; int j; /* counter */ - bus = bb_miiphy_getbus(devname); + bus = bb_miiphy_getbus(miidev->name); if (bus == NULL) { /* Bus not found! */ return -1; diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 2fa2016cdd7..79c1db2c83a 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -566,7 +566,17 @@ int sh_eth_initialize(bd_t *bd) eth_register(dev); bb_miiphy_buses[0].priv = eth; - miiphy_register(dev->name, bb_miiphy_read, bb_miiphy_write); + int retval; + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; + strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); + mdiodev->read = bb_miiphy_read; + mdiodev->write = bb_miiphy_write; + + retval = mdio_register(mdiodev); + if (retval < 0) + return retval; if (!eth_getenv_enetaddr("ethaddr", dev->enetaddr)) puts("Please set MAC address\n"); diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index c85a178cd89..feae8c09cf1 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -219,20 +219,27 @@ static int smc911x_rx(struct eth_device *dev) #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) /* wrapper for smc911x_eth_phy_read */ -static int smc911x_miiphy_read(const char *devname, u8 phy, u8 reg, u16 *val) +static int smc911x_miiphy_read(struct mii_dev *bus, int phy, int devad, + int reg) { - struct eth_device *dev = eth_get_dev_by_name(devname); - if (dev) - return smc911x_eth_phy_read(dev, phy, reg, val); - return -1; + u16 val = 0; + struct eth_device *dev = eth_get_dev_by_name(bus->name); + if (dev) { + int retval = smc911x_eth_phy_read(dev, phy, reg, &val); + if (retval < 0) + return retval; + return val; + } + return -ENODEV; } /* wrapper for smc911x_eth_phy_write */ -static int smc911x_miiphy_write(const char *devname, u8 phy, u8 reg, u16 val) +static int smc911x_miiphy_write(struct mii_dev *bus, int phy, int devad, + int reg, u16 val) { - struct eth_device *dev = eth_get_dev_by_name(devname); + struct eth_device *dev = eth_get_dev_by_name(bus->name); if (dev) return smc911x_eth_phy_write(dev, phy, reg, val); - return -1; + return -ENODEV; } #endif @@ -276,7 +283,17 @@ int smc911x_initialize(u8 dev_num, int base_addr) eth_register(dev); #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - miiphy_register(dev->name, smc911x_miiphy_read, smc911x_miiphy_write); + int retval; + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; + strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); + mdiodev->read = smc911x_miiphy_read; + mdiodev->write = smc911x_miiphy_write; + + retval = mdio_register(mdiodev); + if (retval < 0) + return retval; #endif return 1; diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c new file mode 100644 index 00000000000..4c149e1bdf2 --- /dev/null +++ b/drivers/net/sun8i_emac.c @@ -0,0 +1,785 @@ +/* + * (C) Copyright 2016 + * Author: Amit Singh Tomar, amittomer25@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Ethernet driver for H3/A64/A83T based SoC's + * + * It is derived from the work done by + * LABBE Corentin & Chen-Yu Tsai for Linux, THANKS! + * +*/ + +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/gpio.h> +#include <common.h> +#include <dm.h> +#include <fdt_support.h> +#include <linux/err.h> +#include <malloc.h> +#include <miiphy.h> +#include <net.h> + +#define MDIO_CMD_MII_BUSY BIT(0) +#define MDIO_CMD_MII_WRITE BIT(1) + +#define MDIO_CMD_MII_PHY_REG_ADDR_MASK 0x000001f0 +#define MDIO_CMD_MII_PHY_REG_ADDR_SHIFT 4 +#define MDIO_CMD_MII_PHY_ADDR_MASK 0x0001f000 +#define MDIO_CMD_MII_PHY_ADDR_SHIFT 12 + +#define CONFIG_TX_DESCR_NUM 32 +#define CONFIG_RX_DESCR_NUM 32 +#define CONFIG_ETH_BUFSIZE 2048 /* Note must be dma aligned */ + +/* + * The datasheet says that each descriptor can transfers up to 4096 bytes + * But later, the register documentation reduces that value to 2048, + * using 2048 cause strange behaviours and even BSP driver use 2047 + */ +#define CONFIG_ETH_RXSIZE 2044 /* Note must fit in ETH_BUFSIZE */ + +#define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM) +#define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM) + +#define H3_EPHY_DEFAULT_VALUE 0x58000 +#define H3_EPHY_DEFAULT_MASK GENMASK(31, 15) +#define H3_EPHY_ADDR_SHIFT 20 +#define REG_PHY_ADDR_MASK GENMASK(4, 0) +#define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */ +#define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */ +#define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */ + +#define SC_RMII_EN BIT(13) +#define SC_EPIT BIT(2) /* 1: RGMII, 0: MII */ +#define SC_ETCS_MASK GENMASK(1, 0) +#define SC_ETCS_EXT_GMII 0x1 +#define SC_ETCS_INT_GMII 0x2 + +#define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ) + +#define AHB_GATE_OFFSET_EPHY 0 + +#if defined(CONFIG_MACH_SUN8I_H3) +#define SUN8I_GPD8_GMAC 2 +#else +#define SUN8I_GPD8_GMAC 4 +#endif + +/* H3/A64 EMAC Register's offset */ +#define EMAC_CTL0 0x00 +#define EMAC_CTL1 0x04 +#define EMAC_INT_STA 0x08 +#define EMAC_INT_EN 0x0c +#define EMAC_TX_CTL0 0x10 +#define EMAC_TX_CTL1 0x14 +#define EMAC_TX_FLOW_CTL 0x1c +#define EMAC_TX_DMA_DESC 0x20 +#define EMAC_RX_CTL0 0x24 +#define EMAC_RX_CTL1 0x28 +#define EMAC_RX_DMA_DESC 0x34 +#define EMAC_MII_CMD 0x48 +#define EMAC_MII_DATA 0x4c +#define EMAC_ADDR0_HIGH 0x50 +#define EMAC_ADDR0_LOW 0x54 +#define EMAC_TX_DMA_STA 0xb0 +#define EMAC_TX_CUR_DESC 0xb4 +#define EMAC_TX_CUR_BUF 0xb8 +#define EMAC_RX_DMA_STA 0xc0 +#define EMAC_RX_CUR_DESC 0xc4 + +DECLARE_GLOBAL_DATA_PTR; + +enum emac_variant { + A83T_EMAC = 1, + H3_EMAC, + A64_EMAC, +}; + +struct emac_dma_desc { + u32 status; + u32 st; + u32 buf_addr; + u32 next; +} __aligned(ARCH_DMA_MINALIGN); + +struct emac_eth_dev { + struct emac_dma_desc rx_chain[CONFIG_TX_DESCR_NUM]; + struct emac_dma_desc tx_chain[CONFIG_RX_DESCR_NUM]; + char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); + char txbuffer[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN); + + u32 interface; + u32 phyaddr; + u32 link; + u32 speed; + u32 duplex; + u32 phy_configured; + u32 tx_currdescnum; + u32 rx_currdescnum; + u32 addr; + u32 tx_slot; + bool use_internal_phy; + + enum emac_variant variant; + void *mac_reg; + phys_addr_t sysctl_reg; + struct phy_device *phydev; + struct mii_dev *bus; +}; + +static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) +{ + struct emac_eth_dev *priv = bus->priv; + ulong start; + u32 miiaddr = 0; + int timeout = CONFIG_MDIO_TIMEOUT; + + miiaddr &= ~MDIO_CMD_MII_WRITE; + miiaddr &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK; + miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) & + MDIO_CMD_MII_PHY_REG_ADDR_MASK; + + miiaddr &= ~MDIO_CMD_MII_PHY_ADDR_MASK; + + miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) & + MDIO_CMD_MII_PHY_ADDR_MASK; + + miiaddr |= MDIO_CMD_MII_BUSY; + + writel(miiaddr, priv->mac_reg + EMAC_MII_CMD); + + start = get_timer(0); + while (get_timer(start) < timeout) { + if (!(readl(priv->mac_reg + EMAC_MII_CMD) & MDIO_CMD_MII_BUSY)) + return readl(priv->mac_reg + EMAC_MII_DATA); + udelay(10); + }; + + return -1; +} + +static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, + u16 val) +{ + struct emac_eth_dev *priv = bus->priv; + ulong start; + u32 miiaddr = 0; + int ret = -1, timeout = CONFIG_MDIO_TIMEOUT; + + miiaddr &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK; + miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) & + MDIO_CMD_MII_PHY_REG_ADDR_MASK; + + miiaddr &= ~MDIO_CMD_MII_PHY_ADDR_MASK; + miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) & + MDIO_CMD_MII_PHY_ADDR_MASK; + + miiaddr |= MDIO_CMD_MII_WRITE; + miiaddr |= MDIO_CMD_MII_BUSY; + + writel(miiaddr, priv->mac_reg + EMAC_MII_CMD); + writel(val, priv->mac_reg + EMAC_MII_DATA); + + start = get_timer(0); + while (get_timer(start) < timeout) { + if (!(readl(priv->mac_reg + EMAC_MII_CMD) & + MDIO_CMD_MII_BUSY)) { + ret = 0; + break; + } + udelay(10); + }; + + return ret; +} + +static int _sun8i_write_hwaddr(struct emac_eth_dev *priv, u8 *mac_id) +{ + u32 macid_lo, macid_hi; + + macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) + + (mac_id[3] << 24); + macid_hi = mac_id[4] + (mac_id[5] << 8); + + writel(macid_hi, priv->mac_reg + EMAC_ADDR0_HIGH); + writel(macid_lo, priv->mac_reg + EMAC_ADDR0_LOW); + + return 0; +} + +static void sun8i_adjust_link(struct emac_eth_dev *priv, + struct phy_device *phydev) +{ + u32 v; + + v = readl(priv->mac_reg + EMAC_CTL0); + + if (phydev->duplex) + v |= BIT(0); + else + v &= ~BIT(0); + + v &= ~0x0C; + + switch (phydev->speed) { + case 1000: + break; + case 100: + v |= BIT(2); + v |= BIT(3); + break; + case 10: + v |= BIT(3); + break; + } + writel(v, priv->mac_reg + EMAC_CTL0); +} + +static int sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 *reg) +{ + if (priv->use_internal_phy) { + /* H3 based SoC's that has an Internal 100MBit PHY + * needs to be configured and powered up before use + */ + *reg &= ~H3_EPHY_DEFAULT_MASK; + *reg |= H3_EPHY_DEFAULT_VALUE; + *reg |= priv->phyaddr << H3_EPHY_ADDR_SHIFT; + *reg &= ~H3_EPHY_SHUTDOWN; + *reg |= H3_EPHY_SELECT; + } else + /* This is to select External Gigabit PHY on + * the boards with H3 SoC. + */ + *reg &= ~H3_EPHY_SELECT; + + return 0; +} + +static int sun8i_emac_set_syscon(struct emac_eth_dev *priv) +{ + int ret; + u32 reg; + + reg = readl(priv->sysctl_reg); + + if (priv->variant == H3_EMAC) { + ret = sun8i_emac_set_syscon_ephy(priv, ®); + if (ret) + return ret; + } + + reg &= ~(SC_ETCS_MASK | SC_EPIT); + if (priv->variant == H3_EMAC || priv->variant == A64_EMAC) + reg &= ~SC_RMII_EN; + + switch (priv->interface) { + case PHY_INTERFACE_MODE_MII: + /* default */ + break; + case PHY_INTERFACE_MODE_RGMII: + reg |= SC_EPIT | SC_ETCS_INT_GMII; + break; + case PHY_INTERFACE_MODE_RMII: + if (priv->variant == H3_EMAC || + priv->variant == A64_EMAC) { + reg |= SC_RMII_EN | SC_ETCS_EXT_GMII; + break; + } + /* RMII not supported on A83T */ + default: + debug("%s: Invalid PHY interface\n", __func__); + return -EINVAL; + } + + writel(reg, priv->sysctl_reg); + + return 0; +} + +static int sun8i_phy_init(struct emac_eth_dev *priv, void *dev) +{ + struct phy_device *phydev; + + phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface); + if (!phydev) + return -ENODEV; + + phy_connect_dev(phydev, dev); + + priv->phydev = phydev; + phy_config(priv->phydev); + + return 0; +} + +static void rx_descs_init(struct emac_eth_dev *priv) +{ + struct emac_dma_desc *desc_table_p = &priv->rx_chain[0]; + char *rxbuffs = &priv->rxbuffer[0]; + struct emac_dma_desc *desc_p; + u32 idx; + + /* flush Rx buffers */ + flush_dcache_range((uintptr_t)rxbuffs, (ulong)rxbuffs + + RX_TOTAL_BUFSIZE); + + for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) { + desc_p = &desc_table_p[idx]; + desc_p->buf_addr = (uintptr_t)&rxbuffs[idx * CONFIG_ETH_BUFSIZE] + ; + desc_p->next = (uintptr_t)&desc_table_p[idx + 1]; + desc_p->st |= CONFIG_ETH_RXSIZE; + desc_p->status = BIT(31); + } + + /* Correcting the last pointer of the chain */ + desc_p->next = (uintptr_t)&desc_table_p[0]; + + flush_dcache_range((uintptr_t)priv->rx_chain, + (uintptr_t)priv->rx_chain + + sizeof(priv->rx_chain)); + + writel((uintptr_t)&desc_table_p[0], (priv->mac_reg + EMAC_RX_DMA_DESC)); + priv->rx_currdescnum = 0; +} + +static void tx_descs_init(struct emac_eth_dev *priv) +{ + struct emac_dma_desc *desc_table_p = &priv->tx_chain[0]; + char *txbuffs = &priv->txbuffer[0]; + struct emac_dma_desc *desc_p; + u32 idx; + + for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) { + desc_p = &desc_table_p[idx]; + desc_p->buf_addr = (uintptr_t)&txbuffs[idx * CONFIG_ETH_BUFSIZE] + ; + desc_p->next = (uintptr_t)&desc_table_p[idx + 1]; + desc_p->status = (1 << 31); + desc_p->st = 0; + } + + /* Correcting the last pointer of the chain */ + desc_p->next = (uintptr_t)&desc_table_p[0]; + + /* Flush all Tx buffer descriptors */ + flush_dcache_range((uintptr_t)priv->tx_chain, + (uintptr_t)priv->tx_chain + + sizeof(priv->tx_chain)); + + writel((uintptr_t)&desc_table_p[0], priv->mac_reg + EMAC_TX_DMA_DESC); + priv->tx_currdescnum = 0; +} + +static int _sun8i_emac_eth_init(struct emac_eth_dev *priv, u8 *enetaddr) +{ + u32 reg, v; + int timeout = 100; + + reg = readl((priv->mac_reg + EMAC_CTL1)); + + if (!(reg & 0x1)) { + /* Soft reset MAC */ + setbits_le32((priv->mac_reg + EMAC_CTL1), 0x1); + do { + reg = readl(priv->mac_reg + EMAC_CTL1); + } while ((reg & 0x01) != 0 && (--timeout)); + if (!timeout) { + printf("%s: Timeout\n", __func__); + return -1; + } + } + + /* Rewrite mac address after reset */ + _sun8i_write_hwaddr(priv, enetaddr); + + v = readl(priv->mac_reg + EMAC_TX_CTL1); + /* TX_MD Transmission starts after a full frame located in TX DMA FIFO*/ + v |= BIT(1); + writel(v, priv->mac_reg + EMAC_TX_CTL1); + + v = readl(priv->mac_reg + EMAC_RX_CTL1); + /* RX_MD RX DMA reads data from RX DMA FIFO to host memory after a + * complete frame has been written to RX DMA FIFO + */ + v |= BIT(1); + writel(v, priv->mac_reg + EMAC_RX_CTL1); + + /* DMA */ + writel(8 << 24, priv->mac_reg + EMAC_CTL1); + + /* Initialize rx/tx descriptors */ + rx_descs_init(priv); + tx_descs_init(priv); + + /* PHY Start Up */ + genphy_parse_link(priv->phydev); + + sun8i_adjust_link(priv, priv->phydev); + + /* Start RX DMA */ + v = readl(priv->mac_reg + EMAC_RX_CTL1); + v |= BIT(30); + writel(v, priv->mac_reg + EMAC_RX_CTL1); + /* Start TX DMA */ + v = readl(priv->mac_reg + EMAC_TX_CTL1); + v |= BIT(30); + writel(v, priv->mac_reg + EMAC_TX_CTL1); + + /* Enable RX/TX */ + setbits_le32(priv->mac_reg + EMAC_RX_CTL0, BIT(31)); + setbits_le32(priv->mac_reg + EMAC_TX_CTL0, BIT(31)); + + return 0; +} + +static int parse_phy_pins(struct udevice *dev) +{ + int offset; + const char *pin_name; + int drive, pull, i; + + offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, + "pinctrl-0"); + if (offset < 0) { + printf("WARNING: emac: cannot find pinctrl-0 node\n"); + return offset; + } + + drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0, + "allwinner,drive", 4); + pull = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0, + "allwinner,pull", 0); + for (i = 0; ; i++) { + int pin; + + if (fdt_get_string_index(gd->fdt_blob, offset, + "allwinner,pins", i, &pin_name)) + break; + if (pin_name[0] != 'P') + continue; + pin = (pin_name[1] - 'A') << 5; + if (pin >= 26 << 5) + continue; + pin += simple_strtol(&pin_name[2], NULL, 10); + + sunxi_gpio_set_cfgpin(pin, SUN8I_GPD8_GMAC); + sunxi_gpio_set_drv(pin, drive); + sunxi_gpio_set_pull(pin, pull); + } + + if (!i) { + printf("WARNING: emac: cannot find allwinner,pins property\n"); + return -2; + } + + return 0; +} + +static int _sun8i_eth_recv(struct emac_eth_dev *priv, uchar **packetp) +{ + u32 status, desc_num = priv->rx_currdescnum; + struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num]; + int length = -EAGAIN; + int good_packet = 1; + uintptr_t desc_start = (uintptr_t)desc_p; + uintptr_t desc_end = desc_start + + roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); + + ulong data_start = (uintptr_t)desc_p->buf_addr; + ulong data_end; + + /* Invalidate entire buffer descriptor */ + invalidate_dcache_range(desc_start, desc_end); + + status = desc_p->status; + + /* Check for DMA own bit */ + if (!(status & BIT(31))) { + length = (desc_p->status >> 16) & 0x3FFF; + + if (length < 0x40) { + good_packet = 0; + debug("RX: Bad Packet (runt)\n"); + } + + data_end = data_start + length; + /* Invalidate received data */ + invalidate_dcache_range(rounddown(data_start, + ARCH_DMA_MINALIGN), + roundup(data_end, + ARCH_DMA_MINALIGN)); + if (good_packet) { + if (length > CONFIG_ETH_RXSIZE) { + printf("Received packet is too big (len=%d)\n", + length); + return -EMSGSIZE; + } + *packetp = (uchar *)(ulong)desc_p->buf_addr; + return length; + } + } + + return length; +} + +static int _sun8i_emac_eth_send(struct emac_eth_dev *priv, void *packet, + int len) +{ + u32 v, desc_num = priv->tx_currdescnum; + struct emac_dma_desc *desc_p = &priv->tx_chain[desc_num]; + uintptr_t desc_start = (uintptr_t)desc_p; + uintptr_t desc_end = desc_start + + roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); + + uintptr_t data_start = (uintptr_t)desc_p->buf_addr; + uintptr_t data_end = data_start + + roundup(len, ARCH_DMA_MINALIGN); + + /* Invalidate entire buffer descriptor */ + invalidate_dcache_range(desc_start, desc_end); + + desc_p->st = len; + /* Mandatory undocumented bit */ + desc_p->st |= BIT(24); + + memcpy((void *)data_start, packet, len); + + /* Flush data to be sent */ + flush_dcache_range(data_start, data_end); + + /* frame end */ + desc_p->st |= BIT(30); + desc_p->st |= BIT(31); + + /*frame begin */ + desc_p->st |= BIT(29); + desc_p->status = BIT(31); + + /*Descriptors st and status field has changed, so FLUSH it */ + flush_dcache_range(desc_start, desc_end); + + /* Move to next Descriptor and wrap around */ + if (++desc_num >= CONFIG_TX_DESCR_NUM) + desc_num = 0; + priv->tx_currdescnum = desc_num; + + /* Start the DMA */ + v = readl(priv->mac_reg + EMAC_TX_CTL1); + v |= BIT(31);/* mandatory */ + v |= BIT(30);/* mandatory */ + writel(v, priv->mac_reg + EMAC_TX_CTL1); + + return 0; +} + +static int sun8i_eth_write_hwaddr(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct emac_eth_dev *priv = dev_get_priv(dev); + + return _sun8i_write_hwaddr(priv, pdata->enetaddr); +} + +static void sun8i_emac_board_setup(struct emac_eth_dev *priv) +{ + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + if (priv->use_internal_phy) { + /* Set clock gating for ephy */ + setbits_le32(&ccm->bus_gate4, BIT(AHB_GATE_OFFSET_EPHY)); + + /* Deassert EPHY */ + setbits_le32(&ccm->ahb_reset2_cfg, BIT(AHB_RESET_OFFSET_EPHY)); + } + + /* Set clock gating for emac */ + setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC)); + + /* De-assert EMAC */ + setbits_le32(&ccm->ahb_reset0_cfg, BIT(AHB_RESET_OFFSET_GMAC)); +} + +static int sun8i_mdio_init(const char *name, struct emac_eth_dev *priv) +{ + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + debug("Failed to allocate MDIO bus\n"); + return -ENOMEM; + } + + bus->read = sun8i_mdio_read; + bus->write = sun8i_mdio_write; + snprintf(bus->name, sizeof(bus->name), name); + bus->priv = (void *)priv; + + return mdio_register(bus); +} + +static int sun8i_emac_eth_start(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + + return _sun8i_emac_eth_init(dev->priv, pdata->enetaddr); +} + +static int sun8i_emac_eth_send(struct udevice *dev, void *packet, int length) +{ + struct emac_eth_dev *priv = dev_get_priv(dev); + + return _sun8i_emac_eth_send(priv, packet, length); +} + +static int sun8i_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct emac_eth_dev *priv = dev_get_priv(dev); + + return _sun8i_eth_recv(priv, packetp); +} + +static int _sun8i_free_pkt(struct emac_eth_dev *priv) +{ + u32 desc_num = priv->rx_currdescnum; + struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num]; + uintptr_t desc_start = (uintptr_t)desc_p; + uintptr_t desc_end = desc_start + + roundup(sizeof(u32), ARCH_DMA_MINALIGN); + + /* Make the current descriptor valid again */ + desc_p->status |= BIT(31); + + /* Flush Status field of descriptor */ + flush_dcache_range(desc_start, desc_end); + + /* Move to next desc and wrap-around condition. */ + if (++desc_num >= CONFIG_RX_DESCR_NUM) + desc_num = 0; + priv->rx_currdescnum = desc_num; + + return 0; +} + +static int sun8i_eth_free_pkt(struct udevice *dev, uchar *packet, + int length) +{ + struct emac_eth_dev *priv = dev_get_priv(dev); + + return _sun8i_free_pkt(priv); +} + +static void sun8i_emac_eth_stop(struct udevice *dev) +{ + struct emac_eth_dev *priv = dev_get_priv(dev); + + /* Stop Rx/Tx transmitter */ + clrbits_le32(priv->mac_reg + EMAC_RX_CTL0, BIT(31)); + clrbits_le32(priv->mac_reg + EMAC_TX_CTL0, BIT(31)); + + /* Stop TX DMA */ + clrbits_le32(priv->mac_reg + EMAC_TX_CTL1, BIT(30)); + + phy_shutdown(priv->phydev); +} + +static int sun8i_emac_eth_probe(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct emac_eth_dev *priv = dev_get_priv(dev); + + priv->mac_reg = (void *)pdata->iobase; + + sun8i_emac_board_setup(priv); + sun8i_emac_set_syscon(priv); + + sun8i_mdio_init(dev->name, priv); + priv->bus = miiphy_get_dev_by_name(dev->name); + + return sun8i_phy_init(priv, dev); +} + +static const struct eth_ops sun8i_emac_eth_ops = { + .start = sun8i_emac_eth_start, + .write_hwaddr = sun8i_eth_write_hwaddr, + .send = sun8i_emac_eth_send, + .recv = sun8i_emac_eth_recv, + .free_pkt = sun8i_eth_free_pkt, + .stop = sun8i_emac_eth_stop, +}; + +static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct emac_eth_dev *priv = dev_get_priv(dev); + const char *phy_mode; + int offset = 0; + + pdata->iobase = dev_get_addr_name(dev, "emac"); + priv->sysctl_reg = dev_get_addr_name(dev, "syscon"); + + pdata->phy_interface = -1; + priv->phyaddr = -1; + priv->use_internal_phy = false; + + offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, + "phy"); + if (offset > 0) + priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", + -1); + + phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); + + if (phy_mode) + pdata->phy_interface = phy_get_interface_by_name(phy_mode); + printf("phy interface%d\n", pdata->phy_interface); + + if (pdata->phy_interface == -1) { + debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); + return -EINVAL; + } + + priv->variant = dev_get_driver_data(dev); + + if (!priv->variant) { + printf("%s: Missing variant '%s'\n", __func__, + (char *)priv->variant); + return -EINVAL; + } + + if (priv->variant == H3_EMAC) { + if (fdt_getprop(gd->fdt_blob, dev->of_offset, + "allwinner,use-internal-phy", NULL)) + priv->use_internal_phy = true; + } + + priv->interface = pdata->phy_interface; + + if (!priv->use_internal_phy) + parse_phy_pins(dev); + + return 0; +} + +static const struct udevice_id sun8i_emac_eth_ids[] = { + {.compatible = "allwinner,sun8i-h3-emac", .data = (uintptr_t)H3_EMAC }, + {.compatible = "allwinner,sun50i-a64-emac", + .data = (uintptr_t)A64_EMAC }, + {.compatible = "allwinner,sun8i-a83t-emac", + .data = (uintptr_t)A83T_EMAC }, + { } +}; + +U_BOOT_DRIVER(eth_sun8i_emac) = { + .name = "eth_sun8i_emac", + .id = UCLASS_ETH, + .of_match = sun8i_emac_eth_ids, + .ofdata_to_platdata = sun8i_emac_eth_ofdata_to_platdata, + .probe = sun8i_emac_eth_probe, + .ops = &sun8i_emac_eth_ops, + .priv_auto_alloc_size = sizeof(struct emac_eth_dev), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; diff --git a/drivers/pch/pch-uclass.c b/drivers/pch/pch-uclass.c index 7216660a24c..af794eb5a12 100644 --- a/drivers/pch/pch-uclass.c +++ b/drivers/pch/pch-uclass.c @@ -8,7 +8,6 @@ #include <common.h> #include <dm.h> #include <pch.h> -#include <dm/root.h> DECLARE_GLOBAL_DATA_PTR; @@ -55,20 +54,8 @@ int pch_get_io_base(struct udevice *dev, u32 *iobasep) return ops->get_io_base(dev, iobasep); } -static int pch_uclass_post_bind(struct udevice *bus) -{ - /* - * Scan the device tree for devices - * - * Before relocation, only bind devices marked for pre-relocation - * use. - */ - return dm_scan_fdt_node(bus, gd->fdt_blob, bus->of_offset, - gd->flags & GD_FLG_RELOC ? false : true); -} - UCLASS_DRIVER(pch) = { .id = UCLASS_PCH, .name = "pch", - .post_bind = pch_uclass_post_bind, + .post_bind = dm_scan_fdt_dev, }; diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 26aa2b0930a..669e37bb5dc 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -31,6 +31,7 @@ config PCI_SANDBOX config PCI_TEGRA bool "Tegra PCI support" depends on TEGRA + depends on (TEGRA186 && POWER_DOMAIN) || (!TEGRA186) help Enable support for the PCIe controller found on some generations of Tegra. Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 32590ce498a..342b78c0c4b 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -13,7 +13,6 @@ #include <pci.h> #include <asm/io.h> #include <dm/lists.h> -#include <dm/root.h> #include <dm/device-internal.h> #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP) #include <asm/fsp/fsp_support.h> @@ -753,27 +752,6 @@ error: return ret; } -static int pci_uclass_post_bind(struct udevice *bus) -{ - /* - * If there is no pci device listed in the device tree, - * don't bother scanning the device tree. - */ - if (bus->of_offset == -1) - return 0; - - /* - * Scan the device tree for devices. This does not probe the PCI bus, - * as this is not permitted while binding. It just finds devices - * mentioned in the device tree. - * - * Before relocation, only bind devices marked for pre-relocation - * use. - */ - return dm_scan_fdt_node(bus, gd->fdt_blob, bus->of_offset, - gd->flags & GD_FLG_RELOC ? false : true); -} - static int decode_regions(struct pci_controller *hose, const void *blob, int parent_node, int node) { @@ -1254,7 +1232,7 @@ UCLASS_DRIVER(pci) = { .id = UCLASS_PCI, .name = "pci", .flags = DM_UC_FLAG_SEQ_ALIAS, - .post_bind = pci_uclass_post_bind, + .post_bind = dm_scan_fdt_dev, .pre_probe = pci_uclass_pre_probe, .post_probe = pci_uclass_post_probe, .child_post_bind = pci_uclass_child_post_bind, diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 4b73a0ff9cb..6b36c187b52 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -458,6 +458,10 @@ void pci_init(void) { hose_head = NULL; + /* allow env to disable pci init/enum */ + if (getenv("pcidisable") != NULL) + return; + /* now call board specific pci_init()... */ pci_init_board(); } diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index 9eb605be742..399055b0781 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -39,14 +39,9 @@ __weak bool board_should_run_oprom(struct udevice *dev) return true; } -static bool should_load_oprom(struct udevice *dev) +__weak bool board_should_load_oprom(struct udevice *dev) { - if (IS_ENABLED(CONFIG_ALWAYS_LOAD_OPROM)) - return 1; - if (board_should_run_oprom(dev)) - return 1; - - return 0; + return true; } __weak uint32_t board_map_oprom_vendev(uint32_t vendev) @@ -278,7 +273,7 @@ int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void), return -ENODEV; } - if (!should_load_oprom(dev)) + if (!board_should_load_oprom(dev)) return -ENXIO; ret = pci_rom_probe(dev, &rom); diff --git a/drivers/pci/pci_sandbox.c b/drivers/pci/pci_sandbox.c index 6de5130c2a8..6a84ee386d7 100644 --- a/drivers/pci/pci_sandbox.c +++ b/drivers/pci/pci_sandbox.c @@ -10,7 +10,6 @@ #include <fdtdec.h> #include <inttypes.h> #include <pci.h> -#include <dm/root.h> DECLARE_GLOBAL_DATA_PTR; @@ -52,12 +51,6 @@ static int sandbox_pci_read_config(struct udevice *bus, pci_dev_t devfn, return ops->read_config(emul, offset, valuep, size); } -static int sandbox_pci_child_post_bind(struct udevice *dev) -{ - /* Attach an emulator if we can */ - return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false); -} - static const struct dm_pci_ops sandbox_pci_ops = { .read_config = sandbox_pci_read_config, .write_config = sandbox_pci_write_config, @@ -73,7 +66,9 @@ U_BOOT_DRIVER(pci_sandbox) = { .id = UCLASS_PCI, .of_match = sandbox_pci_ids, .ops = &sandbox_pci_ops, - .child_post_bind = sandbox_pci_child_post_bind, + + /* Attach an emulator if we can */ + .child_post_bind = dm_scan_fdt_dev, .per_child_platdata_auto_alloc_size = sizeof(struct pci_child_platdata), }; diff --git a/drivers/pci/pci_tegra.c b/drivers/pci/pci_tegra.c index 352cdef56ab..ea8adb98db3 100644 --- a/drivers/pci/pci_tegra.c +++ b/drivers/pci/pci_tegra.c @@ -13,22 +13,35 @@ #define pr_fmt(fmt) "tegra-pcie: " fmt #include <common.h> +#include <clk.h> #include <dm.h> #include <errno.h> #include <fdtdec.h> #include <malloc.h> #include <pci.h> +#include <power-domain.h> +#include <reset.h> #include <asm/io.h> #include <asm/gpio.h> +#include <linux/list.h> + +#ifndef CONFIG_TEGRA186 #include <asm/arch/clock.h> #include <asm/arch/powergate.h> #include <asm/arch-tegra/xusb-padctl.h> - -#include <linux/list.h> - #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> +#endif + +/* + * FIXME: TODO: This driver contains a number of ifdef CONFIG_TEGRA186 that + * should not be present. These are needed because newer Tegra SoCs support + * only the standard clock/reset APIs, whereas older Tegra SoCs support only + * a custom Tegra-specific API. ASAP the older Tegra SoCs' code should be + * fixed to implement the standard APIs, and all drivers converted to solely + * use the new standard APIs, with no ifdefs. + */ DECLARE_GLOBAL_DATA_PTR; @@ -103,6 +116,9 @@ DECLARE_GLOBAL_DATA_PTR; #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222 (0x1 << 20) #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1 (0x1 << 20) #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20) +#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_401 (0x0 << 20) +#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_211 (0x1 << 20) +#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_111 (0x2 << 20) #define AFI_FUSE 0x104 #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2) @@ -110,6 +126,7 @@ DECLARE_GLOBAL_DATA_PTR; #define AFI_PEX0_CTRL 0x110 #define AFI_PEX1_CTRL 0x118 #define AFI_PEX2_CTRL 0x128 +#define AFI_PEX2_CTRL_T186 0x19c #define AFI_PEX_CTRL_RST (1 << 0) #define AFI_PEX_CTRL_CLKREQ_EN (1 << 1) #define AFI_PEX_CTRL_REFCLK_EN (1 << 3) @@ -173,6 +190,7 @@ enum tegra_pci_id { TEGRA30_PCIE, TEGRA124_PCIE, TEGRA210_PCIE, + TEGRA186_PCIE, }; struct tegra_pcie_port { @@ -189,6 +207,7 @@ struct tegra_pcie_soc { unsigned int num_ports; unsigned long pads_pll_ctl; unsigned long tx_ref_sel; + unsigned long afi_pex2_ctrl; u32 pads_refclk_cfg0; u32 pads_refclk_cfg1; bool has_pex_clkreq_en; @@ -209,7 +228,17 @@ struct tegra_pcie { unsigned long xbar; const struct tegra_pcie_soc *soc; + +#ifdef CONFIG_TEGRA186 + struct clk clk_afi; + struct clk clk_pex; + struct reset_ctl reset_afi; + struct reset_ctl reset_pex; + struct reset_ctl reset_pcie_x; + struct power_domain pwrdom; +#else struct tegra_xusb_phy *phy; +#endif }; static void afi_writel(struct tegra_pcie *pcie, unsigned long value, @@ -229,10 +258,12 @@ static void pads_writel(struct tegra_pcie *pcie, unsigned long value, writel(value, pcie->pads.start + offset); } +#ifndef CONFIG_TEGRA186 static unsigned long pads_readl(struct tegra_pcie *pcie, unsigned long offset) { return readl(pcie->pads.start + offset); } +#endif static unsigned long rp_readl(struct tegra_pcie_port *port, unsigned long offset) @@ -400,6 +431,24 @@ static int tegra_pcie_get_xbar_config(const void *fdt, int node, u32 lanes, return 0; } break; + case TEGRA186_PCIE: + switch (lanes) { + case 0x0010004: + debug("x4 x1 configuration\n"); + *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_401; + return 0; + + case 0x0010102: + debug("x2 x1 x1 configuration\n"); + *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_211; + return 0; + + case 0x0010101: + debug("x1 x1 x1 configuration\n"); + *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_111; + return 0; + } + break; default: break; } @@ -471,6 +520,7 @@ static int tegra_pcie_parse_dt(const void *fdt, int node, enum tegra_pci_id id, return err; } +#ifndef CONFIG_TEGRA186 pcie->phy = tegra_xusb_phy_get(TEGRA_XUSB_PADCTL_PCIE); if (pcie->phy) { err = tegra_xusb_phy_prepare(pcie->phy); @@ -479,6 +529,7 @@ static int tegra_pcie_parse_dt(const void *fdt, int node, enum tegra_pci_id id, return err; } } +#endif fdt_for_each_subnode(fdt, subnode, node) { unsigned int index = 0, num_lanes = 0; @@ -523,6 +574,44 @@ static int tegra_pcie_parse_dt(const void *fdt, int node, enum tegra_pci_id id, return 0; } +#ifdef CONFIG_TEGRA186 +static int tegra_pcie_power_on(struct tegra_pcie *pcie) +{ + int ret; + + ret = power_domain_on(&pcie->pwrdom); + if (ret) { + error("power_domain_on() failed: %d\n", ret); + return ret; + } + + ret = clk_enable(&pcie->clk_afi); + if (ret) { + error("clk_enable(afi) failed: %d\n", ret); + return ret; + } + + ret = clk_enable(&pcie->clk_pex); + if (ret) { + error("clk_enable(pex) failed: %d\n", ret); + return ret; + } + + ret = reset_deassert(&pcie->reset_afi); + if (ret) { + error("reset_deassert(afi) failed: %d\n", ret); + return ret; + } + + ret = reset_deassert(&pcie->reset_pex); + if (ret) { + error("reset_deassert(pex) failed: %d\n", ret); + return ret; + } + + return 0; +} +#else static int tegra_pcie_power_on(struct tegra_pcie *pcie) { const struct tegra_pcie_soc *soc = pcie->soc; @@ -639,6 +728,7 @@ static int tegra_pcie_phy_enable(struct tegra_pcie *pcie) return 0; } +#endif static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) { @@ -647,7 +737,11 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) u32 value; int err; +#ifdef CONFIG_TEGRA186 + { +#else if (pcie->phy) { +#endif value = afi_readl(pcie, AFI_PLLE_CONTROL); value &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL; value |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN; @@ -675,6 +769,7 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) afi_writel(pcie, value, AFI_FUSE); +#ifndef CONFIG_TEGRA186 if (pcie->phy) err = tegra_xusb_phy_enable(pcie->phy); else @@ -684,9 +779,18 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) error("failed to power on PHY: %d\n", err); return err; } +#endif /* take the PCIEXCLK logic out of reset */ +#ifdef CONFIG_TEGRA186 + err = reset_deassert(&pcie->reset_pcie_x); + if (err) { + error("reset_deassert(pcie_x) failed: %d\n", err); + return err; + } +#else reset_set_enable(PERIPH_ID_PCIEXCLK, 0); +#endif /* finally enable PCIe */ value = afi_readl(pcie, AFI_CONFIGURATION); @@ -787,7 +891,7 @@ static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port) break; case 2: - ret = AFI_PEX2_CTRL; + ret = port->pcie->soc->afi_pex2_ctrl; break; } @@ -945,6 +1049,7 @@ static const struct tegra_pcie_soc pci_tegra_soc[] = { .num_ports = 3, .pads_pll_ctl = PADS_PLL_CTL_TEGRA30, .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN, + .afi_pex2_ctrl = AFI_PEX2_CTRL, .pads_refclk_cfg0 = 0xfa5cfa5c, .pads_refclk_cfg1 = 0xfa5cfa5c, .has_pex_clkreq_en = true, @@ -972,7 +1077,16 @@ static const struct tegra_pcie_soc pci_tegra_soc[] = { .has_cml_clk = true, .has_gen2 = true, .force_pca_enable = true, - } + }, + [TEGRA186_PCIE] = { + .num_ports = 3, + .afi_pex2_ctrl = AFI_PEX2_CTRL_T186, + .pads_refclk_cfg0 = 0x80b880b8, + .pads_refclk_cfg1 = 0x000480b8, + .has_pex_clkreq_en = true, + .has_pex_bias_ctrl = true, + .has_gen2 = true, + }, }; static int pci_tegra_ofdata_to_platdata(struct udevice *dev) @@ -996,6 +1110,44 @@ static int pci_tegra_probe(struct udevice *dev) struct tegra_pcie *pcie = dev_get_priv(dev); int err; +#ifdef CONFIG_TEGRA186 + err = clk_get_by_name(dev, "afi", &pcie->clk_afi); + if (err) { + debug("clk_get_by_name(afi) failed: %d\n", err); + return err; + } + + err = clk_get_by_name(dev, "pex", &pcie->clk_pex); + if (err) { + debug("clk_get_by_name(pex) failed: %d\n", err); + return err; + } + + err = reset_get_by_name(dev, "afi", &pcie->reset_afi); + if (err) { + debug("reset_get_by_name(afi) failed: %d\n", err); + return err; + } + + err = reset_get_by_name(dev, "pex", &pcie->reset_pex); + if (err) { + debug("reset_get_by_name(pex) failed: %d\n", err); + return err; + } + + err = reset_get_by_name(dev, "pcie_x", &pcie->reset_pcie_x); + if (err) { + debug("reset_get_by_name(pcie_x) failed: %d\n", err); + return err; + } + + err = power_domain_get(dev, &pcie->pwrdom); + if (err) { + debug("power_domain_get() failed: %d\n", err); + return err; + } +#endif + err = tegra_pcie_power_on(pcie); if (err < 0) { error("failed to power on"); @@ -1033,6 +1185,7 @@ static const struct udevice_id pci_tegra_ids[] = { { .compatible = "nvidia,tegra30-pcie", .data = TEGRA30_PCIE }, { .compatible = "nvidia,tegra124-pcie", .data = TEGRA124_PCIE }, { .compatible = "nvidia,tegra210-pcie", .data = TEGRA210_PCIE }, + { .compatible = "nvidia,tegra186-pcie", .data = TEGRA186_PCIE }, { } }; diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index c14bb0aa829..732d59d7110 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -595,7 +595,7 @@ static int imx_pcie_link_up(void) while (!imx6_pcie_link_up()) { udelay(10); count++; - if (count >= 2000) { + if (count >= 4000) { #ifdef CONFIG_PCI_SCAN_SHOW puts("PCI: pcie phy link never came up\n"); #endif diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 1785e3b28cf..44b53b9abdd 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -123,24 +123,31 @@ config QCA953X_PINCTRL both the GPIO definitions and pin control functions for each available multiplex function. -config ROCKCHIP_PINCTRL - bool "Rockchip pin control driver" +config ROCKCHIP_RK3036_PINCTRL + bool "Rockchip rk3036 pin control driver" depends on DM help - Support pin multiplexing control on Rockchip SoCs. The driver is + Support pin multiplexing control on Rockchip rk3036 SoCs. The driver is controlled by a device tree node which contains both the GPIO definitions and pin control functions for each available multiplex function. -config ROCKCHIP_3036_PINCTRL - bool "Rockchip rk3036 pin control driver" +config ROCKCHIP_RK3288_PINCTRL + bool "Rockchip pin control driver" depends on DM help - Support pin multiplexing control on Rockchip rk3036 SoCs. The driver is - controlled by a device tree node which contains both the GPIO + Support pin multiplexing control on Rockchip rk3288 SoCs. The driver + is controlled by a device tree node which contains both the GPIO definitions and pin control functions for each available multiplex function. +config PINCTRL_AT91PIO4 + bool "AT91 PIO4 pinctrl driver" + depends on DM + help + This option is to enable the AT91 pinctrl driver for AT91 PIO4 + controller which is available on SAMA5D2 SoC. + config PINCTRL_SANDBOX bool "Sandbox pinctrl driver" depends on SANDBOX diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 7f946814d33..c92ab8c341c 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -5,6 +5,7 @@ obj-y += pinctrl-uclass.o obj-$(CONFIG_$(SPL_)PINCTRL_GENERIC) += pinctrl-generic.o +obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o obj-y += nxp/ obj-$(CONFIG_ARCH_ATH79) += ath79/ obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c new file mode 100644 index 00000000000..6d4aadc32c0 --- /dev/null +++ b/drivers/pinctrl/pinctrl-at91-pio4.c @@ -0,0 +1,182 @@ +/* + * Atmel PIO4 pinctrl driver + * + * Copyright (C) 2016 Atmel Corporation + * Wenyou.Yang <wenyou.yang@atmel.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm/device.h> +#include <dm/pinctrl.h> +#include <linux/io.h> +#include <linux/err.h> +#include <mach/atmel_pio4.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Warning: + * In order to not introduce confusion between Atmel PIO groups and pinctrl + * framework groups, Atmel PIO groups will be called banks. + */ + +struct atmel_pio4_platdata { + struct atmel_pio4_port *reg_base; +}; + +static const struct pinconf_param conf_params[] = { + { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, + { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, + { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, + { "drive-open-drain", PIN_CONFIG_DRIVE_OPEN_DRAIN, 0 }, + { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 }, + { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, + { "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 }, +}; + +static u32 atmel_pinctrl_get_pinconf(const void *blob, int node) +{ + const struct pinconf_param *params; + u32 param, arg, conf = 0; + u32 i; + + for (i = 0; i < ARRAY_SIZE(conf_params); i++) { + params = &conf_params[i]; + if (!fdt_get_property(blob, node, params->property, NULL)) + continue; + + param = params->param; + arg = params->default_value; + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + conf &= (~ATMEL_PIO_PUEN_MASK); + conf &= (~ATMEL_PIO_PDEN_MASK); + break; + case PIN_CONFIG_BIAS_PULL_UP: + conf |= ATMEL_PIO_PUEN_MASK; + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + conf |= ATMEL_PIO_PDEN_MASK; + break; + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + if (arg == 0) + conf &= (~ATMEL_PIO_OPD_MASK); + else + conf |= ATMEL_PIO_OPD_MASK; + break; + case PIN_CONFIG_INPUT_SCHMITT_ENABLE: + if (arg == 0) + conf |= ATMEL_PIO_SCHMITT_MASK; + else + conf &= (~ATMEL_PIO_SCHMITT_MASK); + break; + case PIN_CONFIG_INPUT_DEBOUNCE: + if (arg == 0) { + conf &= (~ATMEL_PIO_IFEN_MASK); + conf &= (~ATMEL_PIO_IFSCEN_MASK); + } else { + conf |= ATMEL_PIO_IFEN_MASK; + conf |= ATMEL_PIO_IFSCEN_MASK; + } + break; + default: + printf("%s: Unsupported configuration parameter: %u\n", + __func__, param); + break; + } + } + + return conf; +} + +static inline struct atmel_pio4_port *atmel_pio4_bank_base(struct udevice *dev, + u32 bank) +{ + struct atmel_pio4_platdata *plat = dev_get_platdata(dev); + struct atmel_pio4_port *bank_base = + (struct atmel_pio4_port *)((u32)plat->reg_base + + ATMEL_PIO_BANK_OFFSET * bank); + + return bank_base; +} + +#define MAX_PINMUX_ENTRIES 40 + +static int atmel_pinctrl_set_state(struct udevice *dev, struct udevice *config) +{ + struct atmel_pio4_port *bank_base; + const void *blob = gd->fdt_blob; + int node = config->of_offset; + u32 offset, func, bank, line; + u32 cells[MAX_PINMUX_ENTRIES]; + u32 i, conf; + int count; + + conf = atmel_pinctrl_get_pinconf(blob, node); + + count = fdtdec_get_int_array_count(blob, node, "pinmux", + cells, ARRAY_SIZE(cells)); + if (count < 0) { + printf("%s: bad pinmux array %d\n", __func__, count); + return -EINVAL; + } + + if (count > MAX_PINMUX_ENTRIES) { + printf("%s: unsupported pinmux array count %d\n", + __func__, count); + return -EINVAL; + } + + for (i = 0 ; i < count; i++) { + offset = ATMEL_GET_PIN_NO(cells[i]); + func = ATMEL_GET_PIN_FUNC(cells[i]); + + bank = ATMEL_PIO_BANK(offset); + line = ATMEL_PIO_LINE(offset); + + bank_base = atmel_pio4_bank_base(dev, bank); + + writel(BIT(line), &bank_base->mskr); + conf &= (~ATMEL_PIO_CFGR_FUNC_MASK); + conf |= (func & ATMEL_PIO_CFGR_FUNC_MASK); + writel(conf, &bank_base->cfgr); + } + + return 0; +} + +const struct pinctrl_ops atmel_pinctrl_ops = { + .set_state = atmel_pinctrl_set_state, +}; + +static int atmel_pinctrl_probe(struct udevice *dev) +{ + struct atmel_pio4_platdata *plat = dev_get_platdata(dev); + fdt_addr_t addr_base; + + dev = dev_get_parent(dev); + addr_base = dev_get_addr(dev); + if (addr_base == FDT_ADDR_T_NONE) + return -EINVAL; + + plat->reg_base = (struct atmel_pio4_port *)addr_base; + + return 0; +} + +static const struct udevice_id atmel_pinctrl_match[] = { + { .compatible = "atmel,sama5d2-pinctrl" }, + {} +}; + +U_BOOT_DRIVER(atmel_pinctrl) = { + .name = "pinctrl_atmel_pio4", + .id = UCLASS_PINCTRL, + .of_match = atmel_pinctrl_match, + .probe = atmel_pinctrl_probe, + .platdata_auto_alloc_size = sizeof(struct atmel_pio4_platdata), + .ops = &atmel_pinctrl_ops, +}; diff --git a/drivers/pinctrl/pinctrl-uclass.c b/drivers/pinctrl/pinctrl-uclass.c index fd04b264541..7397de28c01 100644 --- a/drivers/pinctrl/pinctrl-uclass.c +++ b/drivers/pinctrl/pinctrl-uclass.c @@ -113,7 +113,7 @@ static int pinctrl_select_state_full(struct udevice *dev, const char *statename) } /** - * pinconfig_post-bind() - post binding for PINCONFIG uclass + * pinconfig_post_bind() - post binding for PINCONFIG uclass * Recursively bind its children as pinconfig devices. * * @dev: pinconfig device @@ -257,7 +257,7 @@ int pinctrl_get_gpio_mux(struct udevice *dev, int banknum, int index) } /** - * pinconfig_post-bind() - post binding for PINCTRL uclass + * pinconfig_post_bind() - post binding for PINCTRL uclass * Recursively bind child nodes as pinconfig devices in case of full pinctrl. * * @dev: pinctrl device diff --git a/drivers/pinctrl/pinctrl_pic32.c b/drivers/pinctrl/pinctrl_pic32.c index 5cf97ecec86..9acac29133c 100644 --- a/drivers/pinctrl/pinctrl_pic32.c +++ b/drivers/pinctrl/pinctrl_pic32.c @@ -10,7 +10,6 @@ #include <errno.h> #include <asm/io.h> #include <dm/pinctrl.h> -#include <dm/root.h> #include <mach/pic32.h> DECLARE_GLOBAL_DATA_PTR; @@ -341,12 +340,6 @@ static int pic32_pinctrl_probe(struct udevice *dev) return 0; } -static int pic32_pinctrl_bind(struct udevice *dev) -{ - /* scan child GPIO banks */ - return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false); -} - static const struct udevice_id pic32_pinctrl_ids[] = { { .compatible = "microchip,pic32mzda-pinctrl" }, { } @@ -358,6 +351,6 @@ U_BOOT_DRIVER(pinctrl_pic32) = { .of_match = pic32_pinctrl_ids, .ops = &pic32_pinctrl_ops, .probe = pic32_pinctrl_probe, - .bind = pic32_pinctrl_bind, + .bind = dm_scan_fdt_dev, .priv_auto_alloc_size = sizeof(struct pic32_pinctrl_priv), }; diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile index 6fa7d00d0d8..64e9587cce4 100644 --- a/drivers/pinctrl/rockchip/Makefile +++ b/drivers/pinctrl/rockchip/Makefile @@ -5,5 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_ROCKCHIP_PINCTRL) += pinctrl_rk3288.o -obj-$(CONFIG_ROCKCHIP_3036_PINCTRL) += pinctrl_rk3036.o +obj-$(CONFIG_ROCKCHIP_RK3036_PINCTRL) += pinctrl_rk3036.o +obj-$(CONFIG_ROCKCHIP_RK3288_PINCTRL) += pinctrl_rk3288.o diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3036.c b/drivers/pinctrl/rockchip/pinctrl_rk3036.c index 1f78bf862db..6aea856aa63 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3036.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3036.c @@ -15,7 +15,6 @@ #include <asm/arch/hardware.h> #include <asm/arch/periph.h> #include <dm/pinctrl.h> -#include <dm/root.h> DECLARE_GLOBAL_DATA_PTR; @@ -253,12 +252,6 @@ static struct pinctrl_ops rk3036_pinctrl_ops = { .get_periph_id = rk3036_pinctrl_get_periph_id, }; -static int rk3036_pinctrl_bind(struct udevice *dev) -{ - /* scan child GPIO banks */ - return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false); -} - static int rk3036_pinctrl_probe(struct udevice *dev) { struct rk3036_pinctrl_priv *priv = dev_get_priv(dev); @@ -279,6 +272,6 @@ U_BOOT_DRIVER(pinctrl_rk3036) = { .of_match = rk3036_pinctrl_ids, .priv_auto_alloc_size = sizeof(struct rk3036_pinctrl_priv), .ops = &rk3036_pinctrl_ops, - .bind = rk3036_pinctrl_bind, + .bind = dm_scan_fdt_dev, .probe = rk3036_pinctrl_probe, }; diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3288.c b/drivers/pinctrl/rockchip/pinctrl_rk3288.c index 1fa1daa939c..03222647cad 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3288.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3288.c @@ -17,7 +17,6 @@ #include <asm/arch/periph.h> #include <asm/arch/pmu_rk3288.h> #include <dm/pinctrl.h> -#include <dm/root.h> DECLARE_GLOBAL_DATA_PTR; @@ -476,6 +475,7 @@ static int rk3288_pinctrl_request(struct udevice *dev, int func, int flags) static int rk3288_pinctrl_get_periph_id(struct udevice *dev, struct udevice *periph) { +#if !CONFIG_IS_ENABLED(OF_PLATDATA) u32 cell[3]; int ret; @@ -506,6 +506,7 @@ static int rk3288_pinctrl_get_periph_id(struct udevice *dev, case 103: return PERIPH_ID_HDMI; } +#endif return -ENOENT; } @@ -587,6 +588,7 @@ static int rk3288_pinctrl_set_pins(struct udevice *dev, int banknum, int index, struct rk3288_pinctrl_priv *priv = dev_get_priv(dev); uint shift, ind = index; uint mask; + uint value; u32 *addr; int ret; @@ -595,7 +597,18 @@ static int rk3288_pinctrl_set_pins(struct udevice *dev, int banknum, int index, &mask); if (ret) return ret; - rk_clrsetreg(addr, mask << shift, muxval << shift); + + /* + * PMU_GPIO0 registers cannot be selectively written so we cannot use + * rk_clrsetreg() here. However, the upper 16 bits are reserved and + * are ignored when written, so we can use the same code as for the + * other GPIO banks providing that we preserve the value of the other + * bits. + */ + value = readl(addr); + value &= ~(mask << shift); + value |= (mask << (shift + 16)) | (muxval << shift); + writel(value, addr); /* Handle pullup/pulldown */ if (flags) { @@ -613,7 +626,12 @@ static int rk3288_pinctrl_set_pins(struct udevice *dev, int banknum, int index, addr = &priv->grf->gpio1_p[banknum - 1][ind]; debug("%s: addr=%p, val=%x, shift=%x\n", __func__, addr, val, shift); - rk_clrsetreg(addr, 3 << shift, val << shift); + + /* As above, rk_clrsetreg() cannot be used here. */ + value = readl(addr); + value &= ~(mask << shift); + value |= (3 << (shift + 16)) | (val << shift); + writel(value, addr); } return 0; @@ -662,12 +680,6 @@ static struct pinctrl_ops rk3288_pinctrl_ops = { .get_periph_id = rk3288_pinctrl_get_periph_id, }; -static int rk3288_pinctrl_bind(struct udevice *dev) -{ - /* scan child GPIO banks */ - return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false); -} - #ifndef CONFIG_SPL_BUILD static int rk3288_pinctrl_parse_tables(struct rk3288_pinctrl_priv *priv, struct rockchip_pin_bank *banks, @@ -719,11 +731,13 @@ static const struct udevice_id rk3288_pinctrl_ids[] = { }; U_BOOT_DRIVER(pinctrl_rk3288) = { - .name = "pinctrl_rk3288", + .name = "rockchip_rk3288_pinctrl", .id = UCLASS_PINCTRL, .of_match = rk3288_pinctrl_ids, .priv_auto_alloc_size = sizeof(struct rk3288_pinctrl_priv), .ops = &rk3288_pinctrl_ops, - .bind = rk3288_pinctrl_bind, +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + .bind = dm_scan_fdt_dev, +#endif .probe = rk3288_pinctrl_probe, }; diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c index 225a05c56d0..3f891f15819 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c @@ -1,11 +1,10 @@ /* - * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ -#include <common.h> -#include <mapmem.h> #include <linux/io.h> #include <linux/err.h> #include <linux/sizes.h> @@ -188,7 +187,7 @@ int uniphier_pinctrl_probe(struct udevice *dev, if (addr == FDT_ADDR_T_NONE) return -EINVAL; - priv->base = map_sysmem(addr, SZ_4K); + priv->base = devm_ioremap(dev, addr, SZ_4K); if (!priv->base) return -ENOMEM; @@ -196,12 +195,3 @@ int uniphier_pinctrl_probe(struct udevice *dev, return 0; } - -int uniphier_pinctrl_remove(struct udevice *dev) -{ - struct uniphier_pinctrl_priv *priv = dev_get_priv(dev); - - unmap_sysmem(priv->base); - - return 0; -} diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c index e95870f2c1e..e42602bc828 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld11.c @@ -101,7 +101,6 @@ U_BOOT_DRIVER(uniphier_ld11_pinctrl) = { .id = UCLASS_PINCTRL, .of_match = of_match_ptr(uniphier_ld11_pinctrl_match), .probe = uniphier_ld11_pinctrl_probe, - .remove = uniphier_pinctrl_remove, .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv), .ops = &uniphier_pinctrl_ops, }; diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c index e9031966d01..d6ae51248a9 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld20.c @@ -115,7 +115,6 @@ U_BOOT_DRIVER(uniphier_ld20_pinctrl) = { .id = UCLASS_PINCTRL, .of_match = of_match_ptr(uniphier_ld20_pinctrl_match), .probe = uniphier_ld20_pinctrl_probe, - .remove = uniphier_pinctrl_remove, .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv), .ops = &uniphier_pinctrl_ops, }; diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c index dbb94993132..955858a6aae 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c @@ -1,5 +1,6 @@ /* - * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -135,7 +136,6 @@ U_BOOT_DRIVER(uniphier_ld4_pinctrl) = { .id = UCLASS_PINCTRL, .of_match = of_match_ptr(uniphier_ld4_pinctrl_match), .probe = uniphier_ld4_pinctrl_probe, - .remove = uniphier_pinctrl_remove, .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv), .ops = &uniphier_pinctrl_ops, }; diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c index 8b40801175d..5f9407ed21b 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c @@ -1,5 +1,6 @@ /* - * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -135,7 +136,6 @@ U_BOOT_DRIVER(uniphier_ld6b_pinctrl) = { .id = UCLASS_PINCTRL, .of_match = of_match_ptr(uniphier_ld6b_pinctrl_match), .probe = uniphier_ld6b_pinctrl_probe, - .remove = uniphier_pinctrl_remove, .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv), .ops = &uniphier_pinctrl_ops, }; diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c index dace726b083..6f349dcd2e2 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c @@ -1,5 +1,6 @@ /* - * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -143,7 +144,6 @@ U_BOOT_DRIVER(uniphier_pro4_pinctrl) = { .id = UCLASS_PINCTRL, .of_match = of_match_ptr(uniphier_pro4_pinctrl_match), .probe = uniphier_pro4_pinctrl_probe, - .remove = uniphier_pinctrl_remove, .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv), .ops = &uniphier_pinctrl_ops, .flags = DM_FLAG_PRE_RELOC, diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c index 50b41cc37c0..268cdea42a2 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c @@ -1,5 +1,6 @@ /* - * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -134,7 +135,6 @@ U_BOOT_DRIVER(uniphier_pro5_pinctrl) = { .id = UCLASS_PINCTRL, .of_match = of_match_ptr(uniphier_pro5_pinctrl_match), .probe = uniphier_pro5_pinctrl_probe, - .remove = uniphier_pinctrl_remove, .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv), .ops = &uniphier_pinctrl_ops, .flags = DM_FLAG_PRE_RELOC, diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c index 9223eebc89d..b5342743177 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c @@ -1,5 +1,6 @@ /* - * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -147,7 +148,6 @@ U_BOOT_DRIVER(uniphier_pxs2_pinctrl) = { .id = UCLASS_PINCTRL, .of_match = of_match_ptr(uniphier_pxs2_pinctrl_match), .probe = uniphier_pxs2_pinctrl_probe, - .remove = uniphier_pinctrl_remove, .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv), .ops = &uniphier_pinctrl_ops, }; diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c index cee0eb1abdd..a85e055dae7 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c @@ -1,5 +1,6 @@ /* - * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -143,7 +144,6 @@ U_BOOT_DRIVER(uniphier_sld8_pinctrl) = { .id = UCLASS_PINCTRL, .of_match = of_match_ptr(uniphier_sld8_pinctrl_match), .probe = uniphier_sld8_pinctrl_probe, - .remove = uniphier_pinctrl_remove, .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv), .ops = &uniphier_pinctrl_ops, }; diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier.h b/drivers/pinctrl/uniphier/pinctrl-uniphier.h index 4bb893218a4..4de5b03c8d7 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier.h +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier.h @@ -1,5 +1,6 @@ /* - * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -119,6 +120,4 @@ extern const struct pinctrl_ops uniphier_pinctrl_ops; int uniphier_pinctrl_probe(struct udevice *dev, struct uniphier_pinctrl_socdata *socdata); -int uniphier_pinctrl_remove(struct udevice *dev); - #endif /* __PINCTRL_UNIPHIER_H__ */ diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index 3c441678059..f2c5629be2d 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -1,5 +1,7 @@ menu "Power" +source "drivers/power/domain/Kconfig" + source "drivers/power/pmic/Kconfig" source "drivers/power/regulator/Kconfig" @@ -13,12 +15,12 @@ choice default SUNXI_NO_PMIC if MACH_SUN8I_H3 || MACH_SUN50I config SUNXI_NO_PMIC - boolean "board without a pmic" + bool "board without a pmic" ---help--- Select this for boards which do not use a PMIC. config AXP152_POWER - boolean "axp152 pmic support" + bool "axp152 pmic support" depends on MACH_SUN5I select CMD_POWEROFF ---help--- @@ -26,7 +28,7 @@ config AXP152_POWER A10s boards. config AXP209_POWER - boolean "axp209 pmic support" + bool "axp209 pmic support" depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I select CMD_POWEROFF ---help--- @@ -34,7 +36,7 @@ config AXP209_POWER A10, A13 and A20 boards. config AXP221_POWER - boolean "axp221 / axp223 pmic support" + bool "axp221 / axp223 pmic support" depends on MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33 select CMD_POWEROFF ---help--- @@ -42,14 +44,14 @@ config AXP221_POWER A23 and A31 boards. config AXP809_POWER - boolean "axp809 pmic support" + bool "axp809 pmic support" depends on MACH_SUN9I select CMD_POWEROFF ---help--- Say y here to enable support for the axp809 pmic found on A80 boards. config AXP818_POWER - boolean "axp818 pmic support" + bool "axp818 pmic support" depends on MACH_SUN8I_A83T select CMD_POWEROFF ---help--- @@ -57,7 +59,7 @@ config AXP818_POWER A83T dev board. config SY8106A_POWER - boolean "SY8106A pmic support" + bool "SY8106A pmic support" depends on MACH_SUN8I_H3 ---help--- Select this to enable support for the SY8106A pmic found on some diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig new file mode 100644 index 00000000000..132e33250e8 --- /dev/null +++ b/drivers/power/domain/Kconfig @@ -0,0 +1,27 @@ +menu "Power Domain Support" + +config POWER_DOMAIN + bool "Enable power domain support using Driver Model" + depends on DM && OF_CONTROL + help + Enable support for the power domain driver class. Many SoCs allow + power to be applied to or removed from portions of the SoC (power + domains). This may be used to save power. This API provides the + means to control such power management hardware. + +config SANDBOX_POWER_DOMAIN + bool "Enable the sandbox power domain test driver" + depends on POWER_DOMAIN && SANDBOX + help + Enable support for a test power domain driver implementation, which + simply accepts requests to power on/off various HW modules without + actually doing anything beyond a little error checking. + +config TEGRA186_POWER_DOMAIN + bool "Enable Tegra186 BPMP-based power domain driver" + depends on TEGRA186_BPMP + help + Enable support for manipulating Tegra's on-SoC power domains via IPC + requests to the BPMP (Boot and Power Management Processor). + +endmenu diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile new file mode 100644 index 00000000000..2c3d92638fb --- /dev/null +++ b/drivers/power/domain/Makefile @@ -0,0 +1,8 @@ +# Copyright (c) 2016, NVIDIA CORPORATION. +# +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_POWER_DOMAIN) += power-domain-uclass.o +obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain.o +obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain-test.o +obj-$(CONFIG_TEGRA186_POWER_DOMAIN) += tegra186-power-domain.o diff --git a/drivers/power/domain/power-domain-uclass.c b/drivers/power/domain/power-domain-uclass.c new file mode 100644 index 00000000000..1bb6262fa1b --- /dev/null +++ b/drivers/power/domain/power-domain-uclass.c @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <dm.h> +#include <fdtdec.h> +#include <power-domain.h> +#include <power-domain-uclass.h> + +DECLARE_GLOBAL_DATA_PTR; + +static inline struct power_domain_ops *power_domain_dev_ops(struct udevice *dev) +{ + return (struct power_domain_ops *)dev->driver->ops; +} + +static int power_domain_of_xlate_default(struct power_domain *power_domain, + struct fdtdec_phandle_args *args) +{ + debug("%s(power_domain=%p)\n", __func__, power_domain); + + if (args->args_count != 1) { + debug("Invalid args_count: %d\n", args->args_count); + return -EINVAL; + } + + power_domain->id = args->args[0]; + + return 0; +} + +int power_domain_get(struct udevice *dev, struct power_domain *power_domain) +{ + struct fdtdec_phandle_args args; + int ret; + struct udevice *dev_power_domain; + struct power_domain_ops *ops; + + debug("%s(dev=%p, power_domain=%p)\n", __func__, dev, power_domain); + + ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, dev->of_offset, + "power-domains", + "#power-domain-cells", 0, 0, + &args); + if (ret) { + debug("%s: fdtdec_parse_phandle_with_args failed: %d\n", + __func__, ret); + return ret; + } + + ret = uclass_get_device_by_of_offset(UCLASS_POWER_DOMAIN, args.node, + &dev_power_domain); + if (ret) { + debug("%s: uclass_get_device_by_of_offset failed: %d\n", + __func__, ret); + return ret; + } + ops = power_domain_dev_ops(dev_power_domain); + + power_domain->dev = dev_power_domain; + if (ops->of_xlate) + ret = ops->of_xlate(power_domain, &args); + else + ret = power_domain_of_xlate_default(power_domain, &args); + if (ret) { + debug("of_xlate() failed: %d\n", ret); + return ret; + } + + ret = ops->request(power_domain); + if (ret) { + debug("ops->request() failed: %d\n", ret); + return ret; + } + + return 0; +} + +int power_domain_free(struct power_domain *power_domain) +{ + struct power_domain_ops *ops = power_domain_dev_ops(power_domain->dev); + + debug("%s(power_domain=%p)\n", __func__, power_domain); + + return ops->free(power_domain); +} + +int power_domain_on(struct power_domain *power_domain) +{ + struct power_domain_ops *ops = power_domain_dev_ops(power_domain->dev); + + debug("%s(power_domain=%p)\n", __func__, power_domain); + + return ops->on(power_domain); +} + +int power_domain_off(struct power_domain *power_domain) +{ + struct power_domain_ops *ops = power_domain_dev_ops(power_domain->dev); + + debug("%s(power_domain=%p)\n", __func__, power_domain); + + return ops->off(power_domain); +} + +UCLASS_DRIVER(power_domain) = { + .id = UCLASS_POWER_DOMAIN, + .name = "power_domain", +}; diff --git a/drivers/power/domain/sandbox-power-domain-test.c b/drivers/power/domain/sandbox-power-domain-test.c new file mode 100644 index 00000000000..92a3a2a5273 --- /dev/null +++ b/drivers/power/domain/sandbox-power-domain-test.c @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <dm.h> +#include <power-domain.h> +#include <asm/io.h> +#include <asm/power-domain.h> + +struct sandbox_power_domain_test { + struct power_domain pd; +}; + +int sandbox_power_domain_test_get(struct udevice *dev) +{ + struct sandbox_power_domain_test *sbrt = dev_get_priv(dev); + + return power_domain_get(dev, &sbrt->pd); +} + +int sandbox_power_domain_test_on(struct udevice *dev) +{ + struct sandbox_power_domain_test *sbrt = dev_get_priv(dev); + + return power_domain_on(&sbrt->pd); +} + +int sandbox_power_domain_test_off(struct udevice *dev) +{ + struct sandbox_power_domain_test *sbrt = dev_get_priv(dev); + + return power_domain_off(&sbrt->pd); +} + +int sandbox_power_domain_test_free(struct udevice *dev) +{ + struct sandbox_power_domain_test *sbrt = dev_get_priv(dev); + + return power_domain_free(&sbrt->pd); +} + +static const struct udevice_id sandbox_power_domain_test_ids[] = { + { .compatible = "sandbox,power-domain-test" }, + { } +}; + +U_BOOT_DRIVER(sandbox_power_domain_test) = { + .name = "sandbox_power_domain_test", + .id = UCLASS_MISC, + .of_match = sandbox_power_domain_test_ids, + .priv_auto_alloc_size = sizeof(struct sandbox_power_domain_test), +}; diff --git a/drivers/power/domain/sandbox-power-domain.c b/drivers/power/domain/sandbox-power-domain.c new file mode 100644 index 00000000000..9071346f984 --- /dev/null +++ b/drivers/power/domain/sandbox-power-domain.c @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <dm.h> +#include <power-domain-uclass.h> +#include <asm/io.h> +#include <asm/power-domain.h> + +#define SANDBOX_POWER_DOMAINS 3 + +struct sandbox_power_domain { + bool on[SANDBOX_POWER_DOMAINS]; +}; + +static int sandbox_power_domain_request(struct power_domain *power_domain) +{ + debug("%s(power_domain=%p)\n", __func__, power_domain); + + if (power_domain->id >= SANDBOX_POWER_DOMAINS) + return -EINVAL; + + return 0; +} + +static int sandbox_power_domain_free(struct power_domain *power_domain) +{ + debug("%s(power_domain=%p)\n", __func__, power_domain); + + return 0; +} + +static int sandbox_power_domain_on(struct power_domain *power_domain) +{ + struct sandbox_power_domain *sbr = dev_get_priv(power_domain->dev); + + debug("%s(power_domain=%p)\n", __func__, power_domain); + + sbr->on[power_domain->id] = true; + + return 0; +} + +static int sandbox_power_domain_off(struct power_domain *power_domain) +{ + struct sandbox_power_domain *sbr = dev_get_priv(power_domain->dev); + + debug("%s(power_domain=%p)\n", __func__, power_domain); + + sbr->on[power_domain->id] = false; + + return 0; +} + +static int sandbox_power_domain_bind(struct udevice *dev) +{ + debug("%s(dev=%p)\n", __func__, dev); + + return 0; +} + +static int sandbox_power_domain_probe(struct udevice *dev) +{ + debug("%s(dev=%p)\n", __func__, dev); + + return 0; +} + +static const struct udevice_id sandbox_power_domain_ids[] = { + { .compatible = "sandbox,power-domain" }, + { } +}; + +struct power_domain_ops sandbox_power_domain_ops = { + .request = sandbox_power_domain_request, + .free = sandbox_power_domain_free, + .on = sandbox_power_domain_on, + .off = sandbox_power_domain_off, +}; + +U_BOOT_DRIVER(sandbox_power_domain) = { + .name = "sandbox_power_domain", + .id = UCLASS_POWER_DOMAIN, + .of_match = sandbox_power_domain_ids, + .bind = sandbox_power_domain_bind, + .probe = sandbox_power_domain_probe, + .priv_auto_alloc_size = sizeof(struct sandbox_power_domain), + .ops = &sandbox_power_domain_ops, +}; + +int sandbox_power_domain_query(struct udevice *dev, unsigned long id) +{ + struct sandbox_power_domain *sbr = dev_get_priv(dev); + + debug("%s(dev=%p, id=%ld)\n", __func__, dev, id); + + if (id >= SANDBOX_POWER_DOMAINS) + return -EINVAL; + + return sbr->on[id]; +} diff --git a/drivers/power/domain/tegra186-power-domain.c b/drivers/power/domain/tegra186-power-domain.c new file mode 100644 index 00000000000..41d84de83e1 --- /dev/null +++ b/drivers/power/domain/tegra186-power-domain.c @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <dm.h> +#include <misc.h> +#include <power-domain-uclass.h> +#include <asm/arch-tegra/bpmp_abi.h> + +#define UPDATE BIT(0) +#define ON BIT(1) + +static int tegra186_power_domain_request(struct power_domain *power_domain) +{ + debug("%s(power_domain=%p) (dev=%p, id=%lu)\n", __func__, + power_domain, power_domain->dev, power_domain->id); + + return 0; +} + +static int tegra186_power_domain_free(struct power_domain *power_domain) +{ + debug("%s(power_domain=%p) (dev=%p, id=%lu)\n", __func__, + power_domain, power_domain->dev, power_domain->id); + + return 0; +} + +static int tegra186_power_domain_common(struct power_domain *power_domain, + bool on) +{ + struct mrq_pg_update_state_request req; + int on_state = on ? ON : 0; + int ret; + + req.partition_id = power_domain->id; + req.logic_state = UPDATE | on_state; + req.sram_state = UPDATE | on_state; + /* + * Drivers manage their own clocks so they don't get out of sync, and + * since some power domains have many clocks, only a subset of which + * are actually needed depending on use-case. + */ + req.clock_state = UPDATE; + + ret = misc_call(power_domain->dev->parent, MRQ_PG_UPDATE_STATE, &req, + sizeof(req), NULL, 0); + if (ret < 0) + return ret; + + return 0; +} + +static int tegra186_power_domain_on(struct power_domain *power_domain) +{ + debug("%s(power_domain=%p) (dev=%p, id=%lu)\n", __func__, + power_domain, power_domain->dev, power_domain->id); + + return tegra186_power_domain_common(power_domain, true); +} + +static int tegra186_power_domain_off(struct power_domain *power_domain) +{ + debug("%s(power_domain=%p) (dev=%p, id=%lu)\n", __func__, + power_domain, power_domain->dev, power_domain->id); + + return tegra186_power_domain_common(power_domain, false); +} + +struct power_domain_ops tegra186_power_domain_ops = { + .request = tegra186_power_domain_request, + .free = tegra186_power_domain_free, + .on = tegra186_power_domain_on, + .off = tegra186_power_domain_off, +}; + +static int tegra186_power_domain_probe(struct udevice *dev) +{ + debug("%s(dev=%p)\n", __func__, dev); + + return 0; +} + +U_BOOT_DRIVER(tegra186_power_domain) = { + .name = "tegra186_power_domain", + .id = UCLASS_POWER_DOMAIN, + .probe = tegra186_power_domain_probe, + .ops = &tegra186_power_domain_ops, +}; diff --git a/drivers/power/pmic/act8846.c b/drivers/power/pmic/act8846.c index ff096b3a9cc..e8164bfd08a 100644 --- a/drivers/power/pmic/act8846.c +++ b/drivers/power/pmic/act8846.c @@ -29,7 +29,7 @@ static int act8846_write(struct udevice *dev, uint reg, const uint8_t *buff, int len) { if (dm_i2c_write(dev, reg, buff, len)) { - debug("write error to device: %p register: %#x!", dev, reg); + debug("write error to device: %p register: %#x!\n", dev, reg); return -EIO; } @@ -39,7 +39,7 @@ static int act8846_write(struct udevice *dev, uint reg, const uint8_t *buff, static int act8846_read(struct udevice *dev, uint reg, uint8_t *buff, int len) { if (dm_i2c_read(dev, reg, buff, len)) { - debug("read error from device: %p register: %#x!", dev, reg); + debug("read error from device: %p register: %#x!\n", dev, reg); return -EIO; } diff --git a/drivers/power/pmic/pm8916.c b/drivers/power/pmic/pm8916.c index d4c7d4adff1..2b65c697ec9 100644 --- a/drivers/power/pmic/pm8916.c +++ b/drivers/power/pmic/pm8916.c @@ -7,7 +7,6 @@ */ #include <common.h> #include <dm.h> -#include <dm/root.h> #include <power/pmic.h> #include <spmi/spmi.h> @@ -79,17 +78,11 @@ static int pm8916_probe(struct udevice *dev) return 0; } - -static int pm8916_bind(struct udevice *dev) -{ - return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false); -} - U_BOOT_DRIVER(pmic_pm8916) = { .name = "pmic_pm8916", .id = UCLASS_PMIC, .of_match = pm8916_ids, - .bind = pm8916_bind, + .bind = dm_scan_fdt_dev, .probe = pm8916_probe, .ops = &pm8916_ops, .priv_auto_alloc_size = sizeof(struct pm8916_priv), diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig index 465ff3fda61..17f22dda2bd 100644 --- a/drivers/power/regulator/Kconfig +++ b/drivers/power/regulator/Kconfig @@ -13,7 +13,7 @@ config DM_REGULATOR - 'drivers/power/pmic/regulator-uclass.c' It's important to call the device_bind() with the proper node offset, when binding the regulator devices. The pmic_bind_childs() can be used - for this purpose if PMIC I/O driver is implemented or dm_scan_fdt_node() + for this purpose if PMIC I/O driver is implemented or dm_scan_fdt_dev() otherwise. Detailed information can be found in the header file. config SPL_DM_REGULATOR diff --git a/drivers/power/regulator/act8846.c b/drivers/power/regulator/act8846.c index 255f8b096e1..d5061651208 100644 --- a/drivers/power/regulator/act8846.c +++ b/drivers/power/regulator/act8846.c @@ -88,7 +88,7 @@ static int reg_get_value(struct udevice *dev) int reg = dev->driver_data; int ret; - ret = pmic_reg_read(dev->parent, reg); + ret = pmic_reg_read(dev->parent, addr_vol[reg]); if (ret < 0) return ret; @@ -120,7 +120,7 @@ static bool reg_get_enable(struct udevice *dev) int reg = dev->driver_data; int ret; - ret = pmic_reg_read(dev->parent, reg); + ret = pmic_reg_read(dev->parent, addr_ctl[reg]); if (ret < 0) return ret; diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index 40cccc2406b..468c92ebced 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -623,20 +623,20 @@ static int uec_miiphy_find_dev_by_name(const char *devname) * Returns: * 0 on success */ -static int uec_miiphy_read(const char *devname, unsigned char addr, - unsigned char reg, unsigned short *value) +static int uec_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg) { + unsigned short value = 0; int devindex = 0; - if (devname == NULL || value == NULL) { + if (bus->name == NULL) { debug("%s: NULL pointer given\n", __FUNCTION__); } else { - devindex = uec_miiphy_find_dev_by_name(devname); + devindex = uec_miiphy_find_dev_by_name(bus->name); if (devindex >= 0) { - *value = uec_read_phy_reg(devlist[devindex], addr, reg); + value = uec_read_phy_reg(devlist[devindex], addr, reg); } } - return 0; + return value; } /* @@ -645,15 +645,15 @@ static int uec_miiphy_read(const char *devname, unsigned char addr, * Returns: * 0 on success */ -static int uec_miiphy_write(const char *devname, unsigned char addr, - unsigned char reg, unsigned short value) +static int uec_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg, + u16 value) { int devindex = 0; - if (devname == NULL) { + if (bus->name == NULL) { debug("%s: NULL pointer given\n", __FUNCTION__); } else { - devindex = uec_miiphy_find_dev_by_name(devname); + devindex = uec_miiphy_find_dev_by_name(bus->name); if (devindex >= 0) { uec_write_phy_reg(devlist[devindex], addr, reg, value); } @@ -1399,7 +1399,17 @@ int uec_initialize(bd_t *bis, uec_info_t *uec_info) } #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - miiphy_register(dev->name, uec_miiphy_read, uec_miiphy_write); + int retval; + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; + strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); + mdiodev->read = uec_miiphy_read; + mdiodev->write = uec_miiphy_write; + + retval = mdio_register(mdiodev); + if (retval < 0) + return retval; #endif return 1; diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 0fe8cc3827f..5b84f2178b7 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -20,4 +20,11 @@ config SANDBOX_RESET simply accepts requests to reset various HW modules without actually doing anything beyond a little error checking. +config TEGRA186_RESET + bool "Enable Tegra186 BPMP-based reset driver" + depends on TEGRA186_BPMP + help + Enable support for manipulating Tegra's on-SoC reset signals via IPC + requests to the BPMP (Boot and Power Management Processor). + endmenu diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 71f3b219613..ff0e0907758 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -5,3 +5,4 @@ obj-$(CONFIG_DM_RESET) += reset-uclass.o obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset.o obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o +obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o diff --git a/drivers/reset/tegra186-reset.c b/drivers/reset/tegra186-reset.c new file mode 100644 index 00000000000..228adda0aa8 --- /dev/null +++ b/drivers/reset/tegra186-reset.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <dm.h> +#include <misc.h> +#include <reset-uclass.h> +#include <asm/arch-tegra/bpmp_abi.h> + +static int tegra186_reset_request(struct reset_ctl *reset_ctl) +{ + debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl, + reset_ctl->dev, reset_ctl->id); + + return 0; +} + +static int tegra186_reset_free(struct reset_ctl *reset_ctl) +{ + debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl, + reset_ctl->dev, reset_ctl->id); + + return 0; +} + +static int tegra186_reset_common(struct reset_ctl *reset_ctl, + enum mrq_reset_commands cmd) +{ + struct mrq_reset_request req; + int ret; + + req.cmd = cmd; + req.reset_id = reset_ctl->id; + + ret = misc_call(reset_ctl->dev->parent, MRQ_RESET, &req, sizeof(req), + NULL, 0); + if (ret < 0) + return ret; + + return 0; +} + +static int tegra186_reset_assert(struct reset_ctl *reset_ctl) +{ + debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl, + reset_ctl->dev, reset_ctl->id); + + return tegra186_reset_common(reset_ctl, CMD_RESET_ASSERT); +} + +static int tegra186_reset_deassert(struct reset_ctl *reset_ctl) +{ + debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl, + reset_ctl->dev, reset_ctl->id); + + return tegra186_reset_common(reset_ctl, CMD_RESET_DEASSERT); +} + +struct reset_ops tegra186_reset_ops = { + .request = tegra186_reset_request, + .free = tegra186_reset_free, + .rst_assert = tegra186_reset_assert, + .rst_deassert = tegra186_reset_deassert, +}; + +static int tegra186_reset_probe(struct udevice *dev) +{ + debug("%s(dev=%p)\n", __func__, dev); + + return 0; +} + +U_BOOT_DRIVER(tegra186_reset) = { + .name = "tegra186_reset", + .id = UCLASS_RESET, + .probe = tegra186_reset_probe, + .ops = &tegra186_reset_ops, +}; diff --git a/drivers/rtc/date.c b/drivers/rtc/date.c index 8c643a0b460..bfa2e1378e2 100644 --- a/drivers/rtc/date.c +++ b/drivers/rtc/date.c @@ -5,10 +5,6 @@ * SPDX-License-Identifier: GPL-2.0+ */ -/* - * Date & Time support for Philips PCF8563 RTC - */ - #include <common.h> #include <command.h> #include <errno.h> @@ -28,53 +24,52 @@ static int month_days[12] = { 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 }; +static int month_offset[] = { + 0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334 +}; + /* * This only works for the Gregorian calendar - i.e. after 1752 (in the UK) */ int rtc_calc_weekday(struct rtc_time *tm) { - int leapsToDate; - int lastYear; + int leaps_to_date; + int last_year; int day; - int MonthOffset[] = { 0,31,59,90,120,151,181,212,243,273,304,334 }; if (tm->tm_year < 1753) - return -EINVAL; - lastYear=tm->tm_year-1; + return -1; + last_year = tm->tm_year - 1; - /* - * Number of leap corrections to apply up to end of last year - */ - leapsToDate = lastYear/4 - lastYear/100 + lastYear/400; + /* Number of leap corrections to apply up to end of last year */ + leaps_to_date = last_year / 4 - last_year / 100 + last_year / 400; /* * This year is a leap year if it is divisible by 4 except when it is * divisible by 100 unless it is divisible by 400 * - * e.g. 1904 was a leap year, 1900 was not, 1996 is, and 2000 will be + * e.g. 1904 was a leap year, 1900 was not, 1996 is, and 2000 is. */ - if((tm->tm_year%4==0) && - ((tm->tm_year%100!=0) || (tm->tm_year%400==0)) && - (tm->tm_mon>2)) { - /* - * We are past Feb. 29 in a leap year - */ - day=1; + if (tm->tm_year % 4 == 0 && + ((tm->tm_year % 100 != 0) || (tm->tm_year % 400 == 0)) && + tm->tm_mon > 2) { + /* We are past Feb. 29 in a leap year */ + day = 1; } else { - day=0; + day = 0; } - day += lastYear*365 + leapsToDate + MonthOffset[tm->tm_mon-1] + tm->tm_mday; - - tm->tm_wday=day%7; + day += last_year * 365 + leaps_to_date + month_offset[tm->tm_mon - 1] + + tm->tm_mday; + tm->tm_wday = day % 7; return 0; } int rtc_to_tm(int tim, struct rtc_time *tm) { - register int i; - register long hms, day; + register int i; + register long hms, day; day = tim / SECDAY; hms = tim % SECDAY; @@ -85,22 +80,19 @@ int rtc_to_tm(int tim, struct rtc_time *tm) tm->tm_sec = (hms % 3600) % 60; /* Number of years in days */ - for (i = STARTOFTIME; day >= days_in_year(i); i++) { + for (i = STARTOFTIME; day >= days_in_year(i); i++) day -= days_in_year(i); - } tm->tm_year = i; /* Number of months in days left */ - if (leapyear(tm->tm_year)) { + if (leapyear(tm->tm_year)) days_in_month(FEBRUARY) = 29; - } - for (i = 1; day >= days_in_month(i); i++) { + for (i = 1; day >= days_in_month(i); i++) day -= days_in_month(i); - } days_in_month(FEBRUARY) = 28; tm->tm_mon = i; - /* Days are what is left over (+1) from all that. */ + /* Days are what is left over (+1) from all that */ tm->tm_mday = day + 1; /* Zero unused fields */ @@ -113,19 +105,20 @@ int rtc_to_tm(int tim, struct rtc_time *tm) return rtc_calc_weekday(tm); } -/* Converts Gregorian date to seconds since 1970-01-01 00:00:00. +/* + * Converts Gregorian date to seconds since 1970-01-01 00:00:00. * Assumes input in normal date format, i.e. 1980-12-31 23:59:59 * => year=1980, mon=12, day=31, hour=23, min=59, sec=59. * * [For the Julian calendar (which was used in Russia before 1917, * Britain & colonies before 1752, anywhere else before 1582, * and is still in use by some communities) leave out the - * -year/100+year/400 terms, and add 10.] + * -year / 100 + year / 400 terms, and add 10.] * * This algorithm was first published by Gauss (I think). * * WARNING: this function will overflow on 2106-02-07 06:28:16 on - * machines were long is 32-bit! (However, as time_t is signed, we + * machines where long is 32-bit! (However, as time_t is signed, we * will already get problems at other places on 2038-01-19 03:14:08) */ unsigned long rtc_mktime(const struct rtc_time *tm) @@ -135,8 +128,8 @@ unsigned long rtc_mktime(const struct rtc_time *tm) int days, hours; mon -= 2; - if (0 >= (int)mon) { /* 1..12 -> 11,12,1..10 */ - mon += 12; /* Puts Feb last since it has leap day */ + if (0 >= (int)mon) { /* 1..12 -> 11, 12, 1..10 */ + mon += 12; /* Puts Feb last since it has leap day */ year -= 1; } diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 0e3890391b2..9ff7234d61e 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -312,6 +312,15 @@ config SYS_NS16550 be used. It can be a constant or a function to get clock, eg, get_serial_clock(). +config ROCKCHIP_SERIAL + bool "Rockchip on-chip UART support" + depends on DM_SERIAL && SPL_OF_PLATDATA + help + Select this to enable a debug UART for Rockchip devices when using + CONFIG_OF_PLATDATA (i.e. a compiled-in device tree replacemenmt). + This uses the ns16550 driver, converting the platdata from of-platdata + to the ns16550 format. + config SANDBOX_SERIAL bool "Sandbox UART support" depends on SANDBOX diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 92cbea59135..6986d659ab0 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -28,6 +28,9 @@ obj-$(CONFIG_S5P) += serial_s5p.o obj-$(CONFIG_MXC_UART) += serial_mxc.o obj-$(CONFIG_PXA_SERIAL) += serial_pxa.o obj-$(CONFIG_MESON_SERIAL) += serial_meson.o +ifdef CONFIG_SPL_BUILD +obj-$(CONFIG_ROCKCHIP_SERIAL) += serial_rockchip.o +endif obj-$(CONFIG_S3C24X0_SERIAL) += serial_s3c24x0.o obj-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o obj-$(CONFIG_SANDBOX_SERIAL) += sandbox.o diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index c6cb3eb500c..88fca15357e 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -347,7 +347,7 @@ int ns16550_serial_probe(struct udevice *dev) return 0; } -#if CONFIG_IS_ENABLED(OF_CONTROL) +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) int ns16550_serial_ofdata_to_platdata(struct udevice *dev) { struct ns16550_platdata *plat = dev->platdata; @@ -416,6 +416,7 @@ const struct dm_serial_ops ns16550_serial_ops = { .setbrg = ns16550_serial_setbrg, }; +#if !CONFIG_IS_ENABLED(OF_PLATDATA) #if CONFIG_IS_ENABLED(OF_CONTROL) /* * Please consider existing compatible strings before adding a new @@ -452,4 +453,5 @@ U_BOOT_DRIVER(ns16550_serial) = { .flags = DM_FLAG_PRE_RELOC, }; #endif +#endif /* !OF_PLATDATA */ #endif /* CONFIG_DM_SERIAL */ diff --git a/drivers/serial/sandbox.c b/drivers/serial/sandbox.c index 58f882b22a6..bcc3465312e 100644 --- a/drivers/serial/sandbox.c +++ b/drivers/serial/sandbox.c @@ -115,7 +115,9 @@ static int sandbox_serial_pending(struct udevice *dev, bool input) return 0; os_usleep(100); +#ifndef CONFIG_SPL_BUILD video_sync_all(); +#endif if (next_index == serial_buf_read) return 1; /* buffer full */ diff --git a/drivers/serial/serial-uclass.c b/drivers/serial/serial-uclass.c index 0ce5c44f331..19f38e162e0 100644 --- a/drivers/serial/serial-uclass.c +++ b/drivers/serial/serial-uclass.c @@ -33,7 +33,13 @@ static void serial_find_console_or_panic(void) struct udevice *dev; int node; - if (CONFIG_IS_ENABLED(OF_CONTROL) && blob) { + if (CONFIG_IS_ENABLED(OF_PLATDATA)) { + uclass_first_device(UCLASS_SERIAL, &dev); + if (dev) { + gd->cur_serial_dev = dev; + return; + } + } else if (CONFIG_IS_ENABLED(OF_CONTROL) && blob) { /* Check for a chosen console */ node = fdtdec_get_chosen_node(blob, "stdout-path"); if (node < 0) { diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c index 1563bb3665b..85457144113 100644 --- a/drivers/serial/serial_mxc.c +++ b/drivers/serial/serial_mxc.c @@ -76,6 +76,7 @@ #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ #define UFCR_RFDIV_SHF 7 /* Reference freq divider shift */ +#define UFCR_DCEDTE (1<<6) /* DTE mode select */ #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ #define USR1_RTSS (1<<14) /* RTS pin status */ @@ -269,8 +270,13 @@ int mxc_serial_setbrg(struct udevice *dev, int baudrate) struct mxc_serial_platdata *plat = dev->platdata; struct mxc_uart *const uart = plat->reg; u32 clk = imx_get_uartclk(); + u32 tmp; + + tmp = 4 << UFCR_RFDIV_SHF; + if (plat->use_dte) + tmp |= UFCR_DCEDTE; + writel(tmp, &uart->fcr); - writel(4 << 7, &uart->fcr); /* divide input clock by 2 */ writel(0xf, &uart->bir); writel(clk / (2 * baudrate), &uart->bmr); diff --git a/drivers/serial/serial_rockchip.c b/drivers/serial/serial_rockchip.c new file mode 100644 index 00000000000..6bac95a414c --- /dev/null +++ b/drivers/serial/serial_rockchip.c @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <debug_uart.h> +#include <dm.h> +#include <dt-structs.h> +#include <ns16550.h> +#include <serial.h> +#include <asm/arch/clock.h> + +struct rockchip_uart_platdata { + struct dtd_rockchip_rk3288_uart dtplat; + struct ns16550_platdata plat; +}; + +struct dtd_rockchip_rk3288_uart *dtplat, s_dtplat; + +static int rockchip_serial_probe(struct udevice *dev) +{ + struct rockchip_uart_platdata *plat = dev_get_platdata(dev); + + /* Create some new platform data for the standard driver */ + plat->plat.base = plat->dtplat.reg[0]; + plat->plat.reg_shift = plat->dtplat.reg_shift; + plat->plat.clock = plat->dtplat.clock_frequency; + dev->platdata = &plat->plat; + + return ns16550_serial_probe(dev); +} + +U_BOOT_DRIVER(rockchip_rk3288_uart) = { + .name = "rockchip_rk3288_uart", + .id = UCLASS_SERIAL, + .priv_auto_alloc_size = sizeof(struct NS16550), + .platdata_auto_alloc_size = sizeof(struct rockchip_uart_platdata), + .probe = rockchip_serial_probe, + .ops = &ns16550_serial_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index 8693c1ed140..ef7cf0f26c8 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -17,6 +17,8 @@ #include <dm/platform_data/serial_sh.h> #include "serial_sh.h" +DECLARE_GLOBAL_DATA_PTR; + #if defined(CONFIG_CPU_SH7760) || \ defined(CONFIG_CPU_SH7780) || \ defined(CONFIG_CPU_SH7785) || \ @@ -201,9 +203,36 @@ static const struct dm_serial_ops sh_serial_ops = { .setbrg = sh_serial_setbrg, }; +#ifdef CONFIG_OF_CONTROL +static const struct udevice_id sh_serial_id[] ={ + {.compatible = "renesas,sci", .data = PORT_SCI}, + {.compatible = "renesas,scif", .data = PORT_SCIF}, + {.compatible = "renesas,scifa", .data = PORT_SCIFA}, + {} +}; + +static int sh_serial_ofdata_to_platdata(struct udevice *dev) +{ + struct sh_serial_platdata *plat = dev_get_platdata(dev); + fdt_addr_t addr; + + addr = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg"); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + plat->base = addr; + plat->clk = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "clock", 1); + plat->type = dev_get_driver_data(dev); + return 0; +} +#endif + U_BOOT_DRIVER(serial_sh) = { .name = "serial_sh", .id = UCLASS_SERIAL, + .of_match = of_match_ptr(sh_serial_id), + .ofdata_to_platdata = of_match_ptr(sh_serial_ofdata_to_platdata), + .platdata_auto_alloc_size = sizeof(struct sh_serial_platdata), .probe = sh_serial_probe, .ops = &sh_serial_ops, .flags = DM_FLAG_PRE_RELOC, @@ -234,6 +263,8 @@ U_BOOT_DRIVER(serial_sh) = { #if defined(CONFIG_SCIF_A) #define SCIF_BASE_PORT PORT_SCIFA +#elif defined(CONFIG_SCI) + #define SCIF_BASE_PORT PORT_SCI #else #define SCIF_BASE_PORT PORT_SCIF #endif diff --git a/drivers/serial/serial_stm32x7.c b/drivers/serial/serial_stm32x7.c index cfbfab7e414..592c0bde368 100644 --- a/drivers/serial/serial_stm32x7.c +++ b/drivers/serial/serial_stm32x7.c @@ -9,6 +9,7 @@ #include <dm.h> #include <asm/io.h> #include <serial.h> +#include <asm/arch/stm32.h> #include <dm/platform_data/serial_stm32x7.h> #include "serial_stm32x7.h" @@ -18,7 +19,20 @@ static int stm32_serial_setbrg(struct udevice *dev, int baudrate) { struct stm32x7_serial_platdata *plat = dev->platdata; struct stm32_usart *const usart = plat->base; - writel(plat->clock/baudrate, &usart->brr); + u32 clock, int_div, frac_div, tmp; + + if (((u32)usart & STM32_BUS_MASK) == APB1_PERIPH_BASE) + clock = clock_get(CLOCK_APB1); + else if (((u32)usart & STM32_BUS_MASK) == APB2_PERIPH_BASE) + clock = clock_get(CLOCK_APB2); + else + return -EINVAL; + + int_div = (25 * clock) / (4 * baudrate); + tmp = ((int_div / 100) << USART_BRR_M_SHIFT) & USART_BRR_M_MASK; + frac_div = int_div - (100 * (tmp >> USART_BRR_M_SHIFT)); + tmp |= (((frac_div * 16) + 50) / 100) & USART_BRR_F_MASK; + writel(tmp, &usart->brr); return 0; } diff --git a/drivers/serial/serial_uniphier.c b/drivers/serial/serial_uniphier.c index 525f0a44175..ab607b7e659 100644 --- a/drivers/serial/serial_uniphier.c +++ b/drivers/serial/serial_uniphier.c @@ -1,5 +1,7 @@ /* - * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2012-2015 Panasonic Corporation + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -9,7 +11,6 @@ #include <linux/sizes.h> #include <asm/errno.h> #include <dm/device.h> -#include <mapmem.h> #include <serial.h> #include <fdtdec.h> @@ -98,7 +99,7 @@ static int uniphier_serial_probe(struct udevice *dev) if (base == FDT_ADDR_T_NONE) return -EINVAL; - port = map_sysmem(base, SZ_64); + port = devm_ioremap(dev, base, SZ_64); if (!port) return -ENOMEM; @@ -115,13 +116,6 @@ static int uniphier_serial_probe(struct udevice *dev) return 0; } -static int uniphier_serial_remove(struct udevice *dev) -{ - unmap_sysmem(uniphier_serial_port(dev)); - - return 0; -} - static const struct udevice_id uniphier_uart_of_match[] = { { .compatible = "socionext,uniphier-uart" }, { /* sentinel */ } @@ -139,7 +133,6 @@ U_BOOT_DRIVER(uniphier_serial) = { .id = UCLASS_SERIAL, .of_match = uniphier_uart_of_match, .probe = uniphier_serial_probe, - .remove = uniphier_serial_remove, .priv_auto_alloc_size = sizeof(struct uniphier_serial_private_data), .ops = &uniphier_serial_ops, }; diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c index 66d54e32ab3..4f6e7e442fa 100644 --- a/drivers/serial/serial_zynq.c +++ b/drivers/serial/serial_zynq.c @@ -5,6 +5,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include <clk.h> #include <common.h> #include <debug_uart.h> #include <dm.h> @@ -108,8 +109,33 @@ static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c) int zynq_serial_setbrg(struct udevice *dev, int baudrate) { struct zynq_uart_priv *priv = dev_get_priv(dev); - unsigned long clock = get_uart_clk(0); + unsigned long clock; +#if defined(CONFIG_CLK) || defined(CONFIG_SPL_CLK) + int ret; + struct clk clk; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret < 0) { + dev_err(dev, "failed to get clock\n"); + return ret; + } + + clock = clk_get_rate(&clk); + if (IS_ERR_VALUE(clock)) { + dev_err(dev, "failed to get rate\n"); + return clock; + } + debug("%s: CLK %ld\n", __func__, clock); + + ret = clk_enable(&clk); + if (ret && ret != -ENOSYS) { + dev_err(dev, "failed to enable clock\n"); + return ret; + } +#else + clock = get_uart_clk(0); +#endif _uart_zynq_serial_setbrg(priv->regs, clock, baudrate); return 0; diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index 4f7fd525322..a5244fff4d9 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -191,6 +191,7 @@ static int cadence_spi_xfer(struct udevice *dev, unsigned int bitlen, struct udevice *bus = dev->parent; struct cadence_spi_platdata *plat = bus->platdata; struct cadence_spi_priv *priv = dev_get_priv(bus); + struct dm_spi_slave_platdata *dm_plat = dev_get_parent_platdata(dev); void *base = priv->regbase; u8 *cmd_buf = priv->cmd_buf; size_t data_bytes; @@ -250,7 +251,7 @@ static int cadence_spi_xfer(struct udevice *dev, unsigned int bitlen, break; case CQSPI_INDIRECT_READ: err = cadence_qspi_apb_indirect_read_setup(plat, - priv->cmd_len, cmd_buf); + priv->cmd_len, dm_plat->mode_rx, cmd_buf); if (!err) { err = cadence_qspi_apb_indirect_read_execute (plat, data_bytes, din); diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 2912e36a53f..a849f7b1997 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -53,7 +53,7 @@ int cadence_qspi_apb_command_write(void *reg_base_addr, unsigned int txlen, const u8 *txbuf); int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat, - unsigned int cmdlen, const u8 *cmdbuf); + unsigned int cmdlen, unsigned int rx_width, const u8 *cmdbuf); int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat, unsigned int rxlen, u8 *rxbuf); int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat, diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index a71531d3093..1d68379c936 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -29,6 +29,7 @@ #include <asm/io.h> #include <asm/errno.h> #include <wait_bit.h> +#include <spi.h> #include "cadence_qspi.h" #define CQSPI_REG_POLL_US (1) /* 1us */ @@ -45,7 +46,6 @@ #define CQSPI_INST_TYPE_QUAD (2) #define CQSPI_STIG_DATA_LEN_MAX (8) -#define CQSPI_INDIRECTTRIGGER_ADDR_MASK (0xFFFFF) #define CQSPI_DUMMY_CLKS_PER_BYTE (8) #define CQSPI_DUMMY_BYTES_MAX (4) @@ -293,8 +293,11 @@ void cadence_qspi_apb_config_baudrate_div(void *reg_base, debug("%s: ref_clk %dHz sclk %dHz Div 0x%x\n", __func__, ref_clk_hz, sclk_hz, div); - div = (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB; - reg |= div; + /* ensure the baud rate doesn't exceed the max value */ + if (div > CQSPI_REG_CONFIG_BAUD_MASK) + div = CQSPI_REG_CONFIG_BAUD_MASK; + + reg |= (div << CQSPI_REG_CONFIG_BAUD_LSB); writel(reg, reg_base + CQSPI_REG_CONFIG); cadence_qspi_apb_controller_enable(reg_base); @@ -549,7 +552,7 @@ int cadence_qspi_apb_command_write(void *reg_base, unsigned int cmdlen, /* Opcode + Address (3/4 bytes) + dummy bytes (0-4 bytes) */ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat, - unsigned int cmdlen, const u8 *cmdbuf) + unsigned int cmdlen, unsigned int rx_width, const u8 *cmdbuf) { unsigned int reg; unsigned int rd_reg; @@ -573,16 +576,15 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat, addr_bytes = cmdlen - 1; /* Setup the indirect trigger address */ - writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK), + writel((u32)plat->ahbbase, plat->regbase + CQSPI_REG_INDIRECTTRIGGER); /* Configure the opcode */ rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB; -#if (CONFIG_SPI_FLASH_QUAD == 1) - /* Instruction and address at DQ0, data at DQ0-3. */ - rd_reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB; -#endif + if (rx_width & SPI_RX_QUAD) + /* Instruction and address at DQ0, data at DQ0-3. */ + rd_reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB; /* Get address */ addr_value = cadence_qspi_apb_cmd2addr(&cmdbuf[1], addr_bytes); @@ -714,7 +716,7 @@ int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat, return -EINVAL; } /* Setup the indirect trigger address */ - writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK), + writel((u32)plat->ahbbase, plat->regbase + CQSPI_REG_INDIRECTTRIGGER); /* Configure the opcode */ diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c index 0bd4f88926f..20aa99a451d 100644 --- a/drivers/spi/davinci_spi.c +++ b/drivers/spi/davinci_spi.c @@ -14,6 +14,7 @@ #include <malloc.h> #include <asm/io.h> #include <asm/arch/hardware.h> +#include <dm.h> /* SPIGCR0 */ #define SPIGCR0_SPIENA_MASK 0x1 @@ -51,6 +52,7 @@ /* SPIDEF */ #define SPIDEF_CSDEF0_MASK BIT(0) +#ifndef CONFIG_DM_SPI #define SPI0_BUS 0 #define SPI0_BASE CONFIG_SYS_SPI_BASE /* @@ -83,6 +85,9 @@ #define SPI2_NUM_CS CONFIG_SYS_SPI2_NUM_CS #define SPI2_BASE CONFIG_SYS_SPI2_BASE #endif +#endif + +DECLARE_GLOBAL_DATA_PTR; /* davinci spi register set */ struct davinci_spi_regs { @@ -114,16 +119,17 @@ struct davinci_spi_regs { /* davinci spi slave */ struct davinci_spi_slave { +#ifndef CONFIG_DM_SPI struct spi_slave slave; +#endif struct davinci_spi_regs *regs; - unsigned int freq; + unsigned int freq; /* current SPI bus frequency */ + unsigned int mode; /* current SPI mode used */ + u8 num_cs; /* total no. of CS available */ + u8 cur_cs; /* CS of current slave */ + bool half_duplex; /* true, if master is half-duplex only */ }; -static inline struct davinci_spi_slave *to_davinci_spi(struct spi_slave *slave) -{ - return container_of(slave, struct davinci_spi_slave, slave); -} - /* * This functions needs to act like a macro to avoid pipeline reloads in the * loops below. Use always_inline. This gains us about 160KiB/s and the bloat @@ -144,15 +150,14 @@ static inline u32 davinci_spi_xfer_data(struct davinci_spi_slave *ds, u32 data) return buf_reg_val; } -static int davinci_spi_read(struct spi_slave *slave, unsigned int len, +static int davinci_spi_read(struct davinci_spi_slave *ds, unsigned int len, u8 *rxp, unsigned long flags) { - struct davinci_spi_slave *ds = to_davinci_spi(slave); unsigned int data1_reg_val; /* enable CS hold, CS[n] and clear the data bits */ data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) | - (slave->cs << SPIDAT1_CSNR_SHIFT)); + (ds->cur_cs << SPIDAT1_CSNR_SHIFT)); /* wait till TXFULL is deasserted */ while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK) @@ -175,15 +180,14 @@ static int davinci_spi_read(struct spi_slave *slave, unsigned int len, return 0; } -static int davinci_spi_write(struct spi_slave *slave, unsigned int len, +static int davinci_spi_write(struct davinci_spi_slave *ds, unsigned int len, const u8 *txp, unsigned long flags) { - struct davinci_spi_slave *ds = to_davinci_spi(slave); unsigned int data1_reg_val; /* enable CS hold and clear the data bits */ data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) | - (slave->cs << SPIDAT1_CSNR_SHIFT)); + (ds->cur_cs << SPIDAT1_CSNR_SHIFT)); /* wait till TXFULL is deasserted */ while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK) @@ -209,16 +213,15 @@ static int davinci_spi_write(struct spi_slave *slave, unsigned int len, return 0; } -#ifndef CONFIG_SPI_HALF_DUPLEX -static int davinci_spi_read_write(struct spi_slave *slave, unsigned int len, - u8 *rxp, const u8 *txp, unsigned long flags) +static int davinci_spi_read_write(struct davinci_spi_slave *ds, unsigned + int len, u8 *rxp, const u8 *txp, + unsigned long flags) { - struct davinci_spi_slave *ds = to_davinci_spi(slave); unsigned int data1_reg_val; /* enable CS hold and clear the data bits */ data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) | - (slave->cs << SPIDAT1_CSNR_SHIFT)); + (ds->cur_cs << SPIDAT1_CSNR_SHIFT)); /* wait till TXFULL is deasserted */ while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK) @@ -237,7 +240,115 @@ static int davinci_spi_read_write(struct spi_slave *slave, unsigned int len, return 0; } -#endif + + +static int __davinci_spi_claim_bus(struct davinci_spi_slave *ds, int cs) +{ + unsigned int mode = 0, scalar; + + /* Enable the SPI hardware */ + writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0); + udelay(1000); + writel(SPIGCR0_SPIENA_MASK, &ds->regs->gcr0); + + /* Set master mode, powered up and not activated */ + writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, &ds->regs->gcr1); + + /* CS, CLK, SIMO and SOMI are functional pins */ + writel(((1 << cs) | SPIPC0_CLKFUN_MASK | + SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0); + + /* setup format */ + scalar = ((CONFIG_SYS_SPI_CLK / ds->freq) - 1) & 0xFF; + + /* + * Use following format: + * character length = 8, + * MSB shifted out first + */ + if (ds->mode & SPI_CPOL) + mode |= SPI_CPOL; + if (!(ds->mode & SPI_CPHA)) + mode |= SPI_CPHA; + writel(8 | (scalar << SPIFMT_PRESCALE_SHIFT) | + (mode << SPIFMT_PHASE_SHIFT), &ds->regs->fmt0); + + /* + * Including a minor delay. No science here. Should be good even with + * no delay + */ + writel((50 << SPI_C2TDELAY_SHIFT) | + (50 << SPI_T2CDELAY_SHIFT), &ds->regs->delay); + + /* default chip select register */ + writel(SPIDEF_CSDEF0_MASK, &ds->regs->def); + + /* no interrupts */ + writel(0, &ds->regs->int0); + writel(0, &ds->regs->lvl); + + /* enable SPI */ + writel((readl(&ds->regs->gcr1) | SPIGCR1_SPIENA_MASK), &ds->regs->gcr1); + + return 0; +} + +static int __davinci_spi_release_bus(struct davinci_spi_slave *ds) +{ + /* Disable the SPI hardware */ + writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0); + + return 0; +} + +static int __davinci_spi_xfer(struct davinci_spi_slave *ds, + unsigned int bitlen, const void *dout, void *din, + unsigned long flags) +{ + unsigned int len; + + if (bitlen == 0) + /* Finish any previously submitted transfers */ + goto out; + + /* + * It's not clear how non-8-bit-aligned transfers are supposed to be + * represented as a stream of bytes...this is a limitation of + * the current SPI interface - here we terminate on receiving such a + * transfer request. + */ + if (bitlen % 8) { + /* Errors always terminate an ongoing transfer */ + flags |= SPI_XFER_END; + goto out; + } + + len = bitlen / 8; + + if (!dout) + return davinci_spi_read(ds, len, din, flags); + if (!din) + return davinci_spi_write(ds, len, dout, flags); + if (!ds->half_duplex) + return davinci_spi_read_write(ds, len, din, dout, flags); + + printf("SPI full duplex not supported\n"); + flags |= SPI_XFER_END; + +out: + if (flags & SPI_XFER_END) { + u8 dummy = 0; + davinci_spi_write(ds, 1, &dummy, flags); + } + return 0; +} + +#ifndef CONFIG_DM_SPI + +static inline struct davinci_spi_slave *to_davinci_spi(struct spi_slave *slave) +{ + return container_of(slave, struct davinci_spi_slave, slave); +} int spi_cs_is_valid(unsigned int bus, unsigned int cs) { @@ -313,6 +424,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, } ds->freq = max_hz; + ds->mode = mode; return &ds->slave; } @@ -324,104 +436,143 @@ void spi_free_slave(struct spi_slave *slave) free(ds); } +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct davinci_spi_slave *ds = to_davinci_spi(slave); + + ds->cur_cs = slave->cs; + + return __davinci_spi_xfer(ds, bitlen, dout, din, flags); +} + int spi_claim_bus(struct spi_slave *slave) { struct davinci_spi_slave *ds = to_davinci_spi(slave); - unsigned int scalar; - /* Enable the SPI hardware */ - writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0); - udelay(1000); - writel(SPIGCR0_SPIENA_MASK, &ds->regs->gcr0); +#ifdef CONFIG_SPI_HALF_DUPLEX + ds->half_duplex = true; +#else + ds->half_duplex = false; +#endif + return __davinci_spi_claim_bus(ds, ds->slave.cs); +} - /* Set master mode, powered up and not activated */ - writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, &ds->regs->gcr1); +void spi_release_bus(struct spi_slave *slave) +{ + struct davinci_spi_slave *ds = to_davinci_spi(slave); - /* CS, CLK, SIMO and SOMI are functional pins */ - writel(((1 << slave->cs) | SPIPC0_CLKFUN_MASK | - SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0); + __davinci_spi_release_bus(ds); +} - /* setup format */ - scalar = ((CONFIG_SYS_SPI_CLK / ds->freq) - 1) & 0xFF; +#else +static int davinci_spi_set_speed(struct udevice *bus, uint max_hz) +{ + struct davinci_spi_slave *ds = dev_get_priv(bus); - /* - * Use following format: - * character length = 8, - * clock signal delayed by half clk cycle, - * clock low in idle state - Mode 0, - * MSB shifted out first - */ - writel(8 | (scalar << SPIFMT_PRESCALE_SHIFT) | - (1 << SPIFMT_PHASE_SHIFT), &ds->regs->fmt0); + debug("%s speed %u\n", __func__, max_hz); + if (max_hz > CONFIG_SYS_SPI_CLK / 2) + return -EINVAL; - /* - * Including a minor delay. No science here. Should be good even with - * no delay - */ - writel((50 << SPI_C2TDELAY_SHIFT) | - (50 << SPI_T2CDELAY_SHIFT), &ds->regs->delay); + ds->freq = max_hz; - /* default chip select register */ - writel(SPIDEF_CSDEF0_MASK, &ds->regs->def); + return 0; +} - /* no interrupts */ - writel(0, &ds->regs->int0); - writel(0, &ds->regs->lvl); +static int davinci_spi_set_mode(struct udevice *bus, uint mode) +{ + struct davinci_spi_slave *ds = dev_get_priv(bus); - /* enable SPI */ - writel((readl(&ds->regs->gcr1) | SPIGCR1_SPIENA_MASK), &ds->regs->gcr1); + debug("%s mode %u\n", __func__, mode); + ds->mode = mode; return 0; } -void spi_release_bus(struct spi_slave *slave) +static int davinci_spi_claim_bus(struct udevice *dev) { - struct davinci_spi_slave *ds = to_davinci_spi(slave); + struct dm_spi_slave_platdata *slave_plat = + dev_get_parent_platdata(dev); + struct udevice *bus = dev->parent; + struct davinci_spi_slave *ds = dev_get_priv(bus); + + if (slave_plat->cs >= ds->num_cs) { + printf("Invalid SPI chipselect\n"); + return -EINVAL; + } + ds->half_duplex = slave_plat->mode & SPI_PREAMBLE; - /* Disable the SPI hardware */ - writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0); + return __davinci_spi_claim_bus(ds, slave_plat->cs); } -int spi_xfer(struct spi_slave *slave, unsigned int bitlen, - const void *dout, void *din, unsigned long flags) +static int davinci_spi_release_bus(struct udevice *dev) { - unsigned int len; + struct davinci_spi_slave *ds = dev_get_priv(dev->parent); - if (bitlen == 0) - /* Finish any previously submitted transfers */ - goto out; + return __davinci_spi_release_bus(ds); +} - /* - * It's not clear how non-8-bit-aligned transfers are supposed to be - * represented as a stream of bytes...this is a limitation of - * the current SPI interface - here we terminate on receiving such a - * transfer request. - */ - if (bitlen % 8) { - /* Errors always terminate an ongoing transfer */ - flags |= SPI_XFER_END; - goto out; +static int davinci_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, + unsigned long flags) +{ + struct dm_spi_slave_platdata *slave = + dev_get_parent_platdata(dev); + struct udevice *bus = dev->parent; + struct davinci_spi_slave *ds = dev_get_priv(bus); + + if (slave->cs >= ds->num_cs) { + printf("Invalid SPI chipselect\n"); + return -EINVAL; } + ds->cur_cs = slave->cs; - len = bitlen / 8; + return __davinci_spi_xfer(ds, bitlen, dout, din, flags); +} - if (!dout) - return davinci_spi_read(slave, len, din, flags); - else if (!din) - return davinci_spi_write(slave, len, dout, flags); -#ifndef CONFIG_SPI_HALF_DUPLEX - else - return davinci_spi_read_write(slave, len, din, dout, flags); -#else - printf("SPI full duplex transaction requested with " - "CONFIG_SPI_HALF_DUPLEX defined.\n"); - flags |= SPI_XFER_END; -#endif +static int davinci_spi_probe(struct udevice *bus) +{ + /* Nothing to do */ + return 0; +} -out: - if (flags & SPI_XFER_END) { - u8 dummy = 0; - davinci_spi_write(slave, 1, &dummy, flags); +static int davinci_ofdata_to_platadata(struct udevice *bus) +{ + struct davinci_spi_slave *ds = dev_get_priv(bus); + const void *blob = gd->fdt_blob; + int node = bus->of_offset; + + ds->regs = dev_map_physmem(bus, sizeof(struct davinci_spi_regs)); + if (!ds->regs) { + printf("%s: could not map device address\n", __func__); + return -EINVAL; } + ds->num_cs = fdtdec_get_int(blob, node, "num-cs", 4); + return 0; } + +static const struct dm_spi_ops davinci_spi_ops = { + .claim_bus = davinci_spi_claim_bus, + .release_bus = davinci_spi_release_bus, + .xfer = davinci_spi_xfer, + .set_speed = davinci_spi_set_speed, + .set_mode = davinci_spi_set_mode, +}; + +static const struct udevice_id davinci_spi_ids[] = { + { .compatible = "ti,keystone-spi" }, + { .compatible = "ti,dm6441-spi" }, + { } +}; + +U_BOOT_DRIVER(davinci_spi) = { + .name = "davinci_spi", + .id = UCLASS_SPI, + .of_match = davinci_spi_ids, + .ops = &davinci_spi_ops, + .ofdata_to_platdata = davinci_ofdata_to_platadata, + .priv_auto_alloc_size = sizeof(struct davinci_spi_slave), + .probe = davinci_spi_probe, +}; +#endif diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 75cbab2676c..2144fca665e 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -386,6 +386,7 @@ static inline void qspi_ahb_read(struct fsl_qspi_priv *priv, u8 *rxbuf, int len) { struct fsl_qspi_regs *regs = priv->regs; u32 mcr_reg; + void *rx_addr = NULL; mcr_reg = qspi_read32(priv->flags, ®s->mcr); @@ -393,8 +394,9 @@ static inline void qspi_ahb_read(struct fsl_qspi_priv *priv, u8 *rxbuf, int len) QSPI_MCR_CLR_RXF_MASK | QSPI_MCR_CLR_TXF_MASK | QSPI_MCR_RESERVED_MASK | QSPI_MCR_END_CFD_LE); + rx_addr = (void *)(uintptr_t)(priv->cur_amba_base + priv->sf_addr); /* Read out the data directly from the AHB buffer. */ - memcpy(rxbuf, (u8 *)(priv->cur_amba_base + priv->sf_addr), len); + memcpy(rxbuf, rx_addr, len); qspi_write32(priv->flags, ®s->mcr, mcr_reg); } diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index 84b6786517c..247abfa72ba 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -12,7 +12,6 @@ #include <spi.h> #include <dm/device-internal.h> #include <dm/uclass-internal.h> -#include <dm/root.h> #include <dm/lists.h> #include <dm/util.h> @@ -109,12 +108,6 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, return dm_spi_xfer(slave->dev, bitlen, dout, din, flags); } -static int spi_post_bind(struct udevice *dev) -{ - /* Scan the bus for devices */ - return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false); -} - static int spi_child_post_bind(struct udevice *dev) { struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev); @@ -278,6 +271,7 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed, int mode, struct udevice **busp, struct spi_slave **devp) { struct udevice *bus, *dev; + struct dm_spi_slave_platdata *plat; bool created = false; int ret; @@ -294,8 +288,6 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed, int mode, * SPI flash chip - we will bind to the correct driver. */ if (ret == -ENODEV && drv_name) { - struct dm_spi_slave_platdata *plat; - debug("%s: Binding new device '%s', busnum=%d, cs=%d, driver=%s\n", __func__, dev_name, busnum, cs, drv_name); ret = device_bind_driver(bus, drv_name, dev_name, &dev); @@ -322,6 +314,11 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed, int mode, slave->dev = dev; } + plat = dev_get_parent_platdata(dev); + if (!speed) { + speed = plat->max_hz; + mode = plat->mode; + } ret = spi_set_speed_mode(bus, speed, mode); if (ret) goto err; @@ -333,7 +330,7 @@ int spi_get_bus_and_cs(int busnum, int cs, int speed, int mode, return 0; err: - debug("%s: Error path, credted=%d, device '%s'\n", __func__, + debug("%s: Error path, created=%d, device '%s'\n", __func__, created, dev->name); if (created) { device_remove(dev); @@ -442,7 +439,7 @@ UCLASS_DRIVER(spi) = { .id = UCLASS_SPI, .name = "spi", .flags = DM_UC_FLAG_SEQ_ALIAS, - .post_bind = spi_post_bind, + .post_bind = dm_scan_fdt_dev, .post_probe = spi_post_probe, .child_pre_probe = spi_child_pre_probe, .per_device_auto_alloc_size = sizeof(struct dm_spi_bus), diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index 9a372ad31da..bb72cb03ec2 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -21,7 +21,8 @@ DECLARE_GLOBAL_DATA_PTR; /* ti qpsi register bit masks */ #define QSPI_TIMEOUT 2000000 -#define QSPI_FCLK 192000000 +#define QSPI_FCLK 192000000 +#define QSPI_DRA7XX_FCLK 76800000 /* clock control */ #define QSPI_CLK_EN BIT(31) #define QSPI_CLK_DIV_MAX 0xffff @@ -101,6 +102,7 @@ struct ti_qspi_priv { #endif struct ti_qspi_regs *base; void *ctrl_mod_mmap; + ulong fclk; unsigned int mode; u32 cmd; u32 dc; @@ -110,12 +112,12 @@ static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz) { uint clk_div; - debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div); - if (!hz) clk_div = 0; else - clk_div = (QSPI_FCLK / hz) - 1; + clk_div = (priv->fclk / hz) - 1; + + debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div); /* disable SCLK */ writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN, @@ -247,13 +249,9 @@ static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen, debug("tx done, status %08x\n", status); } if (rxp) { - priv->cmd |= QSPI_RD_SNGL; debug("rx cmd %08x dc %08x\n", - priv->cmd, priv->dc); - #ifdef CONFIG_DRA7XX - udelay(500); - #endif - writel(priv->cmd, &priv->base->cmd); + ((u32)(priv->cmd | QSPI_RD_SNGL)), priv->dc); + writel(priv->cmd | QSPI_RD_SNGL, &priv->base->cmd); status = readl(&priv->base->status); timeout = QSPI_TIMEOUT; while ((status & QSPI_WC_BUSY) != QSPI_XFER_DONE) { @@ -370,8 +368,10 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, #if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) priv->ctrl_mod_mmap = (void *)CORE_CTRL_IO; priv->slave.memory_map = (void *)MMAP_START_ADDR_DRA; + priv->fclk = QSPI_DRA7XX_FCLK; #else priv->slave.memory_map = (void *)MMAP_START_ADDR_AM43x; + priv->fclk = QSPI_FCLK; #endif ti_spi_set_speed(priv, max_hz); @@ -524,7 +524,10 @@ static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen, static int ti_qspi_probe(struct udevice *bus) { - /* Nothing to do in probe */ + struct ti_qspi_priv *priv = dev_get_priv(bus); + + priv->fclk = dev_get_driver_data(bus); + return 0; } @@ -576,8 +579,8 @@ static const struct dm_spi_ops ti_qspi_ops = { }; static const struct udevice_id ti_qspi_ids[] = { - { .compatible = "ti,dra7xxx-qspi" }, - { .compatible = "ti,am4372-qspi" }, + { .compatible = "ti,dra7xxx-qspi", .data = QSPI_DRA7XX_FCLK}, + { .compatible = "ti,am4372-qspi", .data = QSPI_FCLK}, { } }; diff --git a/drivers/spmi/Kconfig b/drivers/spmi/Kconfig index 8d25b457a6c..ab4878ebae4 100644 --- a/drivers/spmi/Kconfig +++ b/drivers/spmi/Kconfig @@ -9,13 +9,13 @@ config SPMI to connect PMIC devices on various SoCs. config SPMI_MSM - boolean "Support Qualcomm SPMI bus" + bool "Support Qualcomm SPMI bus" depends on SPMI ---help--- Support SPMI bus implementation found on Qualcomm Snapdragon SoCs. config SPMI_SANDBOX - boolean "Support for Sandbox SPMI bus" + bool "Support for Sandbox SPMI bus" depends on SPMI ---help--- Demo SPMI bus implementation. Emulates part of PM8916 as single diff --git a/drivers/spmi/spmi-msm.c b/drivers/spmi/spmi-msm.c index 0cef505e37d..48bc1575964 100644 --- a/drivers/spmi/spmi-msm.c +++ b/drivers/spmi/spmi-msm.c @@ -153,11 +153,12 @@ static int msm_spmi_probe(struct udevice *dev) priv->spmi_core = fdtdec_get_addr_size_auto_parent(gd->fdt_blob, parent->of_offset, dev->of_offset, - "reg", 1, NULL); + "reg", 1, NULL, + false); priv->spmi_obs = fdtdec_get_addr_size_auto_parent(gd->fdt_blob, parent->of_offset, dev->of_offset, "reg", - 2, NULL); + 2, NULL, false); if (priv->arb_chnl == FDT_ADDR_T_NONE || priv->spmi_core == FDT_ADDR_T_NONE || priv->spmi_obs == FDT_ADDR_T_NONE) diff --git a/drivers/spmi/spmi-uclass.c b/drivers/spmi/spmi-uclass.c index 4ddd51b556e..6edece23d82 100644 --- a/drivers/spmi/spmi-uclass.c +++ b/drivers/spmi/spmi-uclass.c @@ -9,7 +9,6 @@ #include <common.h> #include <dm.h> #include <errno.h> -#include <dm/root.h> #include <spmi/spmi.h> #include <linux/ctype.h> @@ -36,13 +35,8 @@ int spmi_reg_write(struct udevice *dev, int usid, int pid, int reg, return ops->write(dev, usid, pid, reg, value); } -static int spmi_post_bind(struct udevice *dev) -{ - return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false); -} - UCLASS_DRIVER(spmi) = { .id = UCLASS_SPMI, .name = "spmi", - .post_bind = spmi_post_bind, + .post_bind = dm_scan_fdt_dev, }; diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig new file mode 100644 index 00000000000..05a37b9a14c --- /dev/null +++ b/drivers/sysreset/Kconfig @@ -0,0 +1,16 @@ +# +# System reset devices +# + +menu "System reset device drivers" + +config SYSRESET + bool "Enable support for system reset drivers" + depends on DM + help + Enable system reset drivers which can be used to reset the CPU or + board. Each driver can provide a reset method which will be called + to effect a reset. The uclass will try all available drivers when + reset_walk() is called. + +endmenu diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile new file mode 100644 index 00000000000..fa75cc52de7 --- /dev/null +++ b/drivers/sysreset/Makefile @@ -0,0 +1,16 @@ +# +# (C) Copyright 2016 Cadence Design Systems Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_SYSRESET) += sysreset-uclass.o + +ifndef CONFIG_SPL_BUILD +obj-$(CONFIG_ROCKCHIP_RK3036) += sysreset_rk3036.o +endif +obj-$(CONFIG_ROCKCHIP_RK3288) += sysreset_rk3288.o +obj-$(CONFIG_ROCKCHIP_RK3399) += sysreset_rk3399.o +obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o +obj-$(CONFIG_ARCH_SNAPDRAGON) += sysreset_snapdragon.o +obj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o diff --git a/drivers/misc/sysreset-uclass.c b/drivers/sysreset/sysreset-uclass.c index 3566d17fb1b..3566d17fb1b 100644 --- a/drivers/misc/sysreset-uclass.c +++ b/drivers/sysreset/sysreset-uclass.c diff --git a/drivers/sysreset/sysreset_rk3036.c b/drivers/sysreset/sysreset_rk3036.c new file mode 100644 index 00000000000..b3d21132399 --- /dev/null +++ b/drivers/sysreset/sysreset_rk3036.c @@ -0,0 +1,45 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <sysreset.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3036.h> +#include <asm/arch/hardware.h> +#include <linux/err.h> + +int rk3036_sysreset_request(struct udevice *dev, enum sysreset_t type) +{ + struct rk3036_cru *cru = rockchip_get_cru(); + + if (IS_ERR(cru)) + return PTR_ERR(cru); + switch (type) { + case SYSRESET_WARM: + writel(0xeca8, &cru->cru_glb_srst_snd_value); + break; + case SYSRESET_COLD: + writel(0xfdb9, &cru->cru_glb_srst_fst_value); + break; + default: + return -EPROTONOSUPPORT; + } + + return -EINPROGRESS; +} + +static struct sysreset_ops rk3036_sysreset = { + .request = rk3036_sysreset_request, +}; + +U_BOOT_DRIVER(sysreset_rk3036) = { + .name = "rk3036_sysreset", + .id = UCLASS_SYSRESET, + .ops = &rk3036_sysreset, +}; diff --git a/drivers/sysreset/sysreset_rk3288.c b/drivers/sysreset/sysreset_rk3288.c new file mode 100644 index 00000000000..0aad1c21601 --- /dev/null +++ b/drivers/sysreset/sysreset_rk3288.c @@ -0,0 +1,47 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <sysreset.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3288.h> +#include <asm/arch/hardware.h> +#include <linux/err.h> + +int rk3288_sysreset_request(struct udevice *dev, enum sysreset_t type) +{ + struct rk3288_cru *cru = rockchip_get_cru(); + + if (IS_ERR(cru)) + return PTR_ERR(cru); + switch (type) { + case SYSRESET_WARM: + rk_clrreg(&cru->cru_mode_con, 0xffff); + writel(0xeca8, &cru->cru_glb_srst_snd_value); + break; + case SYSRESET_COLD: + rk_clrreg(&cru->cru_mode_con, 0xffff); + writel(0xfdb9, &cru->cru_glb_srst_fst_value); + break; + default: + return -EPROTONOSUPPORT; + } + + return -EINPROGRESS; +} + +static struct sysreset_ops rk3288_sysreset = { + .request = rk3288_sysreset_request, +}; + +U_BOOT_DRIVER(sysreset_rk3288) = { + .name = "rk3288_sysreset", + .id = UCLASS_SYSRESET, + .ops = &rk3288_sysreset, +}; diff --git a/drivers/sysreset/sysreset_rk3399.c b/drivers/sysreset/sysreset_rk3399.c new file mode 100644 index 00000000000..9a555464c66 --- /dev/null +++ b/drivers/sysreset/sysreset_rk3399.c @@ -0,0 +1,45 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <sysreset.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3399.h> +#include <asm/arch/hardware.h> +#include <linux/err.h> + +int rk3399_sysreset_request(struct udevice *dev, enum sysreset_t type) +{ + struct rk3399_cru *cru = rockchip_get_cru(); + + if (IS_ERR(cru)) + return PTR_ERR(cru); + switch (type) { + case SYSRESET_WARM: + writel(0xeca8, &cru->glb_srst_snd_value); + break; + case SYSRESET_COLD: + writel(0xfdb9, &cru->glb_srst_fst_value); + break; + default: + return -EPROTONOSUPPORT; + } + + return -EINPROGRESS; +} + +static struct sysreset_ops rk3399_sysreset = { + .request = rk3399_sysreset_request, +}; + +U_BOOT_DRIVER(sysreset_rk3399) = { + .name = "rk3399_sysreset", + .id = UCLASS_SYSRESET, + .ops = &rk3399_sysreset, +}; diff --git a/drivers/misc/sysreset_sandbox.c b/drivers/sysreset/sysreset_sandbox.c index 7ae7f386ee0..7ae7f386ee0 100644 --- a/drivers/misc/sysreset_sandbox.c +++ b/drivers/sysreset/sysreset_sandbox.c diff --git a/drivers/sysreset/sysreset_snapdragon.c b/drivers/sysreset/sysreset_snapdragon.c new file mode 100644 index 00000000000..a6cabfb8b01 --- /dev/null +++ b/drivers/sysreset/sysreset_snapdragon.c @@ -0,0 +1,40 @@ +/* + * Qualcomm APQ8016 reset controller driver + * + * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <sysreset.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +static int msm_sysreset_request(struct udevice *dev, enum sysreset_t type) +{ + phys_addr_t addr = dev_get_addr(dev); + if (!addr) + return -EINVAL; + writel(0, addr); + return -EINPROGRESS; +} + +static struct sysreset_ops msm_sysreset_ops = { + .request = msm_sysreset_request, +}; + +static const struct udevice_id msm_sysreset_ids[] = { + { .compatible = "qcom,pshold" }, + { } +}; + +U_BOOT_DRIVER(msm_reset) = { + .name = "msm_sysreset", + .id = UCLASS_SYSRESET, + .of_match = msm_sysreset_ids, + .ops = &msm_sysreset_ops, +}; diff --git a/drivers/sysreset/sysreset_xtfpga.c b/drivers/sysreset/sysreset_xtfpga.c new file mode 100644 index 00000000000..54fd5a0163b --- /dev/null +++ b/drivers/sysreset/sysreset_xtfpga.c @@ -0,0 +1,37 @@ +/* + * Cadence Tensilica xtfpga system reset driver. + * + * (C) Copyright 2016 Cadence Design Systems Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <sysreset.h> +#include <asm/io.h> + +static int xtfpga_reset_request(struct udevice *dev, enum sysreset_t type) +{ + switch (type) { + case SYSRESET_COLD: + writel(CONFIG_SYS_FPGAREG_RESET_CODE, + CONFIG_SYS_FPGAREG_RESET); + break; + default: + return -EPROTONOSUPPORT; + } + + return -EINPROGRESS; +} + +static struct sysreset_ops xtfpga_sysreset_ops = { + .request = xtfpga_reset_request, +}; + +U_BOOT_DRIVER(xtfpga_sysreset) = { + .name = "xtfpga_sysreset", + .id = UCLASS_SYSRESET, + .ops = &xtfpga_sysreset_ops, +}; diff --git a/drivers/tpm/Kconfig b/drivers/tpm/Kconfig index 9a7b7f535fb..7ab34ce8635 100644 --- a/drivers/tpm/Kconfig +++ b/drivers/tpm/Kconfig @@ -15,7 +15,7 @@ config TPM_TIS_SANDBOX config TPM_ATMEL_TWI bool "Enable Atmel TWI TPM device driver" - depends on TPM && DM_I2C + depends on TPM help This driver supports an Atmel TPM device connected on the I2C bus. The usual tpm operations and the 'tpm' command can be used to talk diff --git a/drivers/tpm/tpm_atmel_twi.c b/drivers/tpm/tpm_atmel_twi.c index 2aa9381b11a..eba654b15dc 100644 --- a/drivers/tpm/tpm_atmel_twi.c +++ b/drivers/tpm/tpm_atmel_twi.c @@ -81,14 +81,23 @@ static int tpm_atmel_twi_xfer(struct udevice *dev, print_buffer(0, (void *)sendbuf, 1, send_size, 0); #endif +#ifndef CONFIG_DM_I2C res = i2c_write(0x29, 0, 0, (uchar *)sendbuf, send_size); +#else + res = dm_i2c_write(dev, 0, sendbuf, send_size); +#endif if (res) { printf("i2c_write returned %d\n", res); return -1; } start = get_timer(0); - while ((res = i2c_read(0x29, 0, 0, recvbuf, 10))) { +#ifndef CONFIG_DM_I2C + while ((res = i2c_read(0x29, 0, 0, recvbuf, 10))) +#else + while ((res = dm_i2c_read(dev, 0, recvbuf, 10))) +#endif + { /* TODO Use TIS_TIMEOUT from tpm_tis_infineon.h */ if (get_timer(start) > ATMEL_TPM_TIMEOUT_MS) { puts("tpm timed out\n"); @@ -99,7 +108,11 @@ static int tpm_atmel_twi_xfer(struct udevice *dev, if (!res) { *recv_len = get_unaligned_be32(recvbuf + 2); if (*recv_len > 10) +#ifndef CONFIG_DM_I2C res = i2c_read(0x29, 0, 0, recvbuf, *recv_len); +#else + res = dm_i2c_read(dev, 0, recvbuf, *recv_len); +#endif } if (res) { printf("i2c_read returned %d (rlen=%d)\n", res, *recv_len); diff --git a/drivers/usb/emul/usb-emul-uclass.c b/drivers/usb/emul/usb-emul-uclass.c index ee7ea5ad91c..6e03c1e0d9e 100644 --- a/drivers/usb/emul/usb-emul-uclass.c +++ b/drivers/usb/emul/usb-emul-uclass.c @@ -8,7 +8,6 @@ #include <common.h> #include <dm.h> #include <usb.h> -#include <dm/root.h> #include <dm/device-internal.h> DECLARE_GLOBAL_DATA_PTR; @@ -265,12 +264,6 @@ int usb_emul_setup_device(struct udevice *dev, int maxpacketsize, return 0; } -int usb_emul_post_bind(struct udevice *dev) -{ - /* Scan the bus for devices */ - return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false); -} - void usb_emul_reset(struct udevice *dev) { struct usb_dev_platdata *plat = dev_get_parent_platdata(dev); @@ -282,7 +275,7 @@ void usb_emul_reset(struct udevice *dev) UCLASS_DRIVER(usb_emul) = { .id = UCLASS_USB_EMUL, .name = "usb_emul", - .post_bind = usb_emul_post_bind, + .post_bind = dm_scan_fdt_dev, .per_child_auto_alloc_size = sizeof(struct usb_device), .per_child_platdata_auto_alloc_size = sizeof(struct usb_dev_platdata), }; diff --git a/drivers/usb/eth/asix88179.c b/drivers/usb/eth/asix88179.c index 5e1ea8693b0..7548269f958 100644 --- a/drivers/usb/eth/asix88179.c +++ b/drivers/usb/eth/asix88179.c @@ -7,6 +7,7 @@ */ #include <common.h> +#include <dm.h> #include <usb.h> #include <net.h> #include <linux/mii.h> @@ -185,6 +186,7 @@ #define FLAG_TYPE_SITECOM (1U << 3) #define FLAG_TYPE_SAMSUNG (1U << 4) #define FLAG_TYPE_LENOVO (1U << 5) +#define FLAG_TYPE_GX3 (1U << 6) /* local vars */ static const struct { @@ -196,10 +198,18 @@ static const struct { {7, 0xcc, 0x4c, 0x04, 8}, }; +#ifndef CONFIG_DM_ETH static int curr_eth_dev; /* index for name of next device detected */ +#endif /* driver private */ struct asix_private { +#ifdef CONFIG_DM_ETH + struct ueth_data ueth; + unsigned pkt_cnt; + uint8_t *pkt_data; + uint32_t *pkt_hdr; +#endif int flags; int rx_urb_size; int maxpacketsize; @@ -258,36 +268,32 @@ static int asix_read_cmd(struct ueth_data *dev, u8 cmd, u16 value, u16 index, return len == size ? 0 : ECOMM; } -static int asix_read_mac(struct eth_device *eth) +static int asix_read_mac(struct ueth_data *dev, uint8_t *enetaddr) { - struct ueth_data *dev = (struct ueth_data *)eth->priv; - u8 buf[ETH_ALEN]; - - asix_read_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, 6, 6, buf); - debug("asix_read_mac() returning %02x:%02x:%02x:%02x:%02x:%02x\n", - buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]); + int ret; - memcpy(eth->enetaddr, buf, ETH_ALEN); + ret = asix_read_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, 6, 6, enetaddr); + if (ret < 0) + debug("Failed to read MAC address: %02x\n", ret); - return 0; + return ret; } -static int asix_write_mac(struct eth_device *eth) +static int asix_write_mac(struct ueth_data *dev, uint8_t *enetaddr) { - struct ueth_data *dev = (struct ueth_data *)eth->priv; int ret; ret = asix_write_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, ETH_ALEN, - ETH_ALEN, eth->enetaddr); + ETH_ALEN, enetaddr); if (ret < 0) debug("Failed to set MAC address: %02x\n", ret); return ret; } -static int asix_basic_reset(struct ueth_data *dev) +static int asix_basic_reset(struct ueth_data *dev, + struct asix_private *dev_priv) { - struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv; u8 buf[5]; u16 *tmp16; u8 *tmp; @@ -386,13 +392,9 @@ static int asix_wait_link(struct ueth_data *dev) } } -/* - * Asix callbacks - */ -static int asix_init(struct eth_device *eth, bd_t *bd) +static int asix_init_common(struct ueth_data *dev, + struct asix_private *dev_priv) { - struct ueth_data *dev = (struct ueth_data *)eth->priv; - struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv; u8 buf[2], tmp[5], link_sts; u16 *tmp16, mode; @@ -410,7 +412,7 @@ static int asix_init(struct eth_device *eth, bd_t *bd) if (asix_wait_link(dev) != 0) { /*reset device and try again*/ printf("Reset Ethernet Device\n"); - asix_basic_reset(dev); + asix_basic_reset(dev, dev_priv); if (asix_wait_link(dev) != 0) goto out_err; } @@ -462,11 +464,10 @@ out_err: return -1; } -static int asix_send(struct eth_device *eth, void *packet, int length) +static int asix_send_common(struct ueth_data *dev, + struct asix_private *dev_priv, + void *packet, int length) { - struct ueth_data *dev = (struct ueth_data *)eth->priv; - struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv; - int err; u32 packet_len, tx_hdr2; int actual_len, framesize; @@ -503,6 +504,33 @@ static int asix_send(struct eth_device *eth, void *packet, int length) return err; } +#ifndef CONFIG_DM_ETH +/* + * Asix callbacks + */ +static int asix_init(struct eth_device *eth, bd_t *bd) +{ + struct ueth_data *dev = (struct ueth_data *)eth->priv; + struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv; + + return asix_init_common(dev, dev_priv); +} + +static int asix_write_hwaddr(struct eth_device *eth) +{ + struct ueth_data *dev = (struct ueth_data *)eth->priv; + + return asix_write_mac(dev, eth->enetaddr); +} + +static int asix_send(struct eth_device *eth, void *packet, int length) +{ + struct ueth_data *dev = (struct ueth_data *)eth->priv; + struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv; + + return asix_send_common(dev, dev_priv, packet, length); +} + static int asix_recv(struct eth_device *eth) { struct ueth_data *dev = (struct ueth_data *)eth->priv; @@ -542,7 +570,7 @@ static int asix_recv(struct eth_device *eth) rx_hdr = *(u32 *)(recv_buf + actual_len - 4); - le32_to_cpus(&pkt_hdr); + le32_to_cpus(&rx_hdr); pkt_cnt = (u16)rx_hdr; hdr_off = (u16)(rx_hdr >> 16); @@ -596,6 +624,7 @@ static const struct asix_dongle asix_dongles[] = { { 0x0df6, 0x0072, FLAG_TYPE_SITECOM }, { 0x04e8, 0xa100, FLAG_TYPE_SAMSUNG }, { 0x17ef, 0x304b, FLAG_TYPE_LENOVO }, + { 0x04b4, 0x3610, FLAG_TYPE_GX3 }, { 0x0000, 0x0000, FLAG_NONE } /* END - Do not remove */ }; @@ -691,6 +720,8 @@ int ax88179_eth_probe(struct usb_device *dev, unsigned int ifnum, int ax88179_eth_get_info(struct usb_device *dev, struct ueth_data *ss, struct eth_device *eth) { + struct asix_private *dev_priv = (struct asix_private *)ss->dev_priv; + if (!eth) { debug("%s: missing parameter.\n", __func__); return 0; @@ -700,16 +731,190 @@ int ax88179_eth_get_info(struct usb_device *dev, struct ueth_data *ss, eth->send = asix_send; eth->recv = asix_recv; eth->halt = asix_halt; - eth->write_hwaddr = asix_write_mac; + eth->write_hwaddr = asix_write_hwaddr; eth->priv = ss; - if (asix_basic_reset(ss)) + if (asix_basic_reset(ss, dev_priv)) return 0; /* Get the MAC address */ - if (asix_read_mac(eth)) + if (asix_read_mac(ss, eth->enetaddr)) return 0; debug("MAC %pM\n", eth->enetaddr); return 1; } + +#else /* !CONFIG_DM_ETH */ + +static int ax88179_eth_start(struct udevice *dev) +{ + struct asix_private *priv = dev_get_priv(dev); + + return asix_init_common(&priv->ueth, priv); +} + +void ax88179_eth_stop(struct udevice *dev) +{ + struct asix_private *priv = dev_get_priv(dev); + struct ueth_data *ueth = &priv->ueth; + + debug("** %s()\n", __func__); + + usb_ether_advance_rxbuf(ueth, -1); + priv->pkt_cnt = 0; + priv->pkt_data = NULL; + priv->pkt_hdr = NULL; +} + +int ax88179_eth_send(struct udevice *dev, void *packet, int length) +{ + struct asix_private *priv = dev_get_priv(dev); + + return asix_send_common(&priv->ueth, priv, packet, length); +} + +int ax88179_eth_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct asix_private *priv = dev_get_priv(dev); + struct ueth_data *ueth = &priv->ueth; + int ret, len; + u16 pkt_len; + + /* No packet left, get a new one */ + if (priv->pkt_cnt == 0) { + uint8_t *ptr; + u16 pkt_cnt; + u16 hdr_off; + u32 rx_hdr; + + len = usb_ether_get_rx_bytes(ueth, &ptr); + debug("%s: first try, len=%d\n", __func__, len); + if (!len) { + if (!(flags & ETH_RECV_CHECK_DEVICE)) + return -EAGAIN; + + ret = usb_ether_receive(ueth, priv->rx_urb_size); + if (ret < 0) + return ret; + + len = usb_ether_get_rx_bytes(ueth, &ptr); + debug("%s: second try, len=%d\n", __func__, len); + } + + if (len < 4) { + usb_ether_advance_rxbuf(ueth, -1); + return -EMSGSIZE; + } + + rx_hdr = *(u32 *)(ptr + len - 4); + le32_to_cpus(&rx_hdr); + + pkt_cnt = (u16)rx_hdr; + if (pkt_cnt == 0) { + usb_ether_advance_rxbuf(ueth, -1); + return 0; + } + + hdr_off = (u16)(rx_hdr >> 16); + if (hdr_off > len - 4) { + usb_ether_advance_rxbuf(ueth, -1); + return -EIO; + } + + priv->pkt_cnt = pkt_cnt; + priv->pkt_data = ptr; + priv->pkt_hdr = (u32 *)(ptr + hdr_off); + debug("%s: %d packets received, pkt header at %d\n", + __func__, (int)priv->pkt_cnt, (int)hdr_off); + } + + le32_to_cpus(priv->pkt_hdr); + pkt_len = (*priv->pkt_hdr >> 16) & 0x1fff; + + *packetp = priv->pkt_data + 2; + + priv->pkt_data += (pkt_len + 7) & 0xFFF8; + priv->pkt_cnt--; + priv->pkt_hdr++; + + debug("%s: return packet of %d bytes (%d packets left)\n", + __func__, (int)pkt_len, priv->pkt_cnt); + return pkt_len; +} + +static int ax88179_free_pkt(struct udevice *dev, uchar *packet, int packet_len) +{ + struct asix_private *priv = dev_get_priv(dev); + struct ueth_data *ueth = &priv->ueth; + + if (priv->pkt_cnt == 0) + usb_ether_advance_rxbuf(ueth, -1); + + return 0; +} + +int ax88179_write_hwaddr(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct asix_private *priv = dev_get_priv(dev); + struct ueth_data *ueth = &priv->ueth; + + return asix_write_mac(ueth, pdata->enetaddr); +} + +static int ax88179_eth_probe(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct asix_private *priv = dev_get_priv(dev); + struct usb_device *usb_dev; + int ret; + + priv->flags = dev->driver_data; + ret = usb_ether_register(dev, &priv->ueth, AX_RX_URB_SIZE); + if (ret) + return ret; + + usb_dev = priv->ueth.pusb_dev; + priv->maxpacketsize = usb_dev->epmaxpacketout[AX_ENDPOINT_OUT]; + + /* Get the MAC address */ + ret = asix_read_mac(&priv->ueth, pdata->enetaddr); + if (ret) + return ret; + debug("MAC %pM\n", pdata->enetaddr); + + return 0; +} + +static const struct eth_ops ax88179_eth_ops = { + .start = ax88179_eth_start, + .send = ax88179_eth_send, + .recv = ax88179_eth_recv, + .free_pkt = ax88179_free_pkt, + .stop = ax88179_eth_stop, + .write_hwaddr = ax88179_write_hwaddr, +}; + +U_BOOT_DRIVER(ax88179_eth) = { + .name = "ax88179_eth", + .id = UCLASS_ETH, + .probe = ax88179_eth_probe, + .ops = &ax88179_eth_ops, + .priv_auto_alloc_size = sizeof(struct asix_private), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +}; + +static const struct usb_device_id ax88179_eth_id_table[] = { + { USB_DEVICE(0x0b95, 0x1790), .driver_info = FLAG_TYPE_AX88179 }, + { USB_DEVICE(0x0b95, 0x178a), .driver_info = FLAG_TYPE_AX88178a }, + { USB_DEVICE(0x2001, 0x4a00), .driver_info = FLAG_TYPE_DLINK_DUB1312 }, + { USB_DEVICE(0x0df6, 0x0072), .driver_info = FLAG_TYPE_SITECOM }, + { USB_DEVICE(0x04e8, 0xa100), .driver_info = FLAG_TYPE_SAMSUNG }, + { USB_DEVICE(0x17ef, 0x304b), .driver_info = FLAG_TYPE_LENOVO }, + { USB_DEVICE(0x04b4, 0x3610), .driver_info = FLAG_TYPE_GX3 }, + { } /* Terminating entry */ +}; + +U_BOOT_USB_DEVICE(ax88179_eth, ax88179_eth_id_table); +#endif /* !CONFIG_DM_ETH */ diff --git a/drivers/usb/eth/r8152.c b/drivers/usb/eth/r8152.c index 325b70c2dd6..070aadfa206 100644 --- a/drivers/usb/eth/r8152.c +++ b/drivers/usb/eth/r8152.c @@ -3,9 +3,10 @@ * * SPDX-License-Identifier: GPL-2.0 * - */ + */ #include <common.h> +#include <dm.h> #include <errno.h> #include <malloc.h> #include <usb.h> @@ -15,6 +16,7 @@ #include "usb_ether.h" #include "r8152.h" +#ifndef CONFIG_DM_ETH /* local vars */ static int curr_eth_dev; /* index for name of next device detected */ @@ -23,12 +25,6 @@ struct r8152_dongle { unsigned short product; }; -struct r8152_version { - unsigned short tcr; - unsigned short version; - bool gmii; -}; - static const struct r8152_dongle const r8152_dongles[] = { /* Realtek */ { 0x0bda, 0x8050 }, @@ -54,6 +50,13 @@ static const struct r8152_dongle const r8152_dongles[] = { /* Nvidia */ { 0x0955, 0x09ff }, }; +#endif + +struct r8152_version { + unsigned short tcr; + unsigned short version; + bool gmii; +}; static const struct r8152_version const r8152_versions[] = { { 0x4c00, RTL_VER_01, 0 }, @@ -1176,11 +1179,8 @@ static int rtl_ops_init(struct r8152 *tp) return ret; } -static int r8152_init(struct eth_device *eth, bd_t *bd) +static int r8152_init_common(struct r8152 *tp) { - struct ueth_data *dev = (struct ueth_data *)eth->priv; - struct r8152 *tp = (struct r8152 *)dev->dev_priv; - u8 speed; int timeout = 0; int link_detected; @@ -1210,14 +1210,11 @@ static int r8152_init(struct eth_device *eth, bd_t *bd) return 0; } -static int r8152_send(struct eth_device *eth, void *packet, int length) +static int r8152_send_common(struct ueth_data *ueth, void *packet, int length) { - struct ueth_data *dev = (struct ueth_data *)eth->priv; - + struct usb_device *udev = ueth->pusb_dev; u32 opts1, opts2 = 0; - int err; - int actual_len; unsigned char msg[PKTSIZE + sizeof(struct tx_desc)]; struct tx_desc *tx_desc = (struct tx_desc *)msg; @@ -1231,18 +1228,31 @@ static int r8152_send(struct eth_device *eth, void *packet, int length) memcpy(msg + sizeof(struct tx_desc), (void *)packet, length); - err = usb_bulk_msg(dev->pusb_dev, - usb_sndbulkpipe(dev->pusb_dev, dev->ep_out), - (void *)msg, - length + sizeof(struct tx_desc), - &actual_len, - USB_BULK_SEND_TIMEOUT); + err = usb_bulk_msg(udev, usb_sndbulkpipe(udev, ueth->ep_out), + (void *)msg, length + sizeof(struct tx_desc), + &actual_len, USB_BULK_SEND_TIMEOUT); debug("Tx: len = %zu, actual = %u, err = %d\n", length + sizeof(struct tx_desc), actual_len, err); return err; } +#ifndef CONFIG_DM_ETH +static int r8152_init(struct eth_device *eth, bd_t *bd) +{ + struct ueth_data *dev = (struct ueth_data *)eth->priv; + struct r8152 *tp = (struct r8152 *)dev->dev_priv; + + return r8152_init_common(tp); +} + +static int r8152_send(struct eth_device *eth, void *packet, int length) +{ + struct ueth_data *dev = (struct ueth_data *)eth->priv; + + return r8152_send_common(dev, packet, length); +} + static int r8152_recv(struct eth_device *eth) { struct ueth_data *dev = (struct ueth_data *)eth->priv; @@ -1454,3 +1464,186 @@ int r8152_eth_get_info(struct usb_device *dev, struct ueth_data *ss, debug("MAC %pM\n", eth->enetaddr); return 1; } +#endif /* !CONFIG_DM_ETH */ + +#ifdef CONFIG_DM_ETH +static int r8152_eth_start(struct udevice *dev) +{ + struct r8152 *tp = dev_get_priv(dev); + + debug("** %s (%d)\n", __func__, __LINE__); + + return r8152_init_common(tp); +} + +void r8152_eth_stop(struct udevice *dev) +{ + struct r8152 *tp = dev_get_priv(dev); + + debug("** %s (%d)\n", __func__, __LINE__); + + tp->rtl_ops.disable(tp); +} + +int r8152_eth_send(struct udevice *dev, void *packet, int length) +{ + struct r8152 *tp = dev_get_priv(dev); + + return r8152_send_common(&tp->ueth, packet, length); +} + +int r8152_eth_recv(struct udevice *dev, int flags, uchar **packetp) +{ + struct r8152 *tp = dev_get_priv(dev); + struct ueth_data *ueth = &tp->ueth; + uint8_t *ptr; + int ret, len; + struct rx_desc *rx_desc; + u16 packet_len; + + len = usb_ether_get_rx_bytes(ueth, &ptr); + debug("%s: first try, len=%d\n", __func__, len); + if (!len) { + if (!(flags & ETH_RECV_CHECK_DEVICE)) + return -EAGAIN; + ret = usb_ether_receive(ueth, RTL8152_AGG_BUF_SZ); + if (ret) + return ret; + + len = usb_ether_get_rx_bytes(ueth, &ptr); + debug("%s: second try, len=%d\n", __func__, len); + } + + rx_desc = (struct rx_desc *)ptr; + packet_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; + packet_len -= CRC_SIZE; + + if (packet_len > len - (sizeof(struct rx_desc) + CRC_SIZE)) { + debug("Rx: too large packet: %d\n", packet_len); + goto err; + } + + *packetp = ptr + sizeof(struct rx_desc); + return packet_len; + +err: + usb_ether_advance_rxbuf(ueth, -1); + return -ENOSPC; +} + +static int r8152_free_pkt(struct udevice *dev, uchar *packet, int packet_len) +{ + struct r8152 *tp = dev_get_priv(dev); + + packet_len += sizeof(struct rx_desc) + CRC_SIZE; + packet_len = ALIGN(packet_len, 8); + usb_ether_advance_rxbuf(&tp->ueth, packet_len); + + return 0; +} + +static int r8152_write_hwaddr(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct r8152 *tp = dev_get_priv(dev); + + unsigned char enetaddr[8] = { 0 }; + + debug("** %s (%d)\n", __func__, __LINE__); + memcpy(enetaddr, pdata->enetaddr, ETH_ALEN); + + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); + pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, enetaddr); + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); + + debug("MAC %pM\n", pdata->enetaddr); + return 0; +} + +int r8152_read_rom_hwaddr(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct r8152 *tp = dev_get_priv(dev); + + debug("** %s (%d)\n", __func__, __LINE__); + r8152_read_mac(tp, pdata->enetaddr); + return 0; +} + +static int r8152_eth_probe(struct udevice *dev) +{ + struct usb_device *udev = dev_get_parent_priv(dev); + struct eth_pdata *pdata = dev_get_platdata(dev); + struct r8152 *tp = dev_get_priv(dev); + struct ueth_data *ueth = &tp->ueth; + int ret; + + tp->udev = udev; + r8152_read_mac(tp, pdata->enetaddr); + + r8152b_get_version(tp); + + ret = rtl_ops_init(tp); + if (ret) + return ret; + + tp->rtl_ops.init(tp); + tp->rtl_ops.up(tp); + + rtl8152_set_speed(tp, AUTONEG_ENABLE, + tp->supports_gmii ? SPEED_1000 : SPEED_100, + DUPLEX_FULL); + + return usb_ether_register(dev, ueth, RTL8152_AGG_BUF_SZ); +} + +static const struct eth_ops r8152_eth_ops = { + .start = r8152_eth_start, + .send = r8152_eth_send, + .recv = r8152_eth_recv, + .free_pkt = r8152_free_pkt, + .stop = r8152_eth_stop, + .write_hwaddr = r8152_write_hwaddr, + .read_rom_hwaddr = r8152_read_rom_hwaddr, +}; + +U_BOOT_DRIVER(r8152_eth) = { + .name = "r8152_eth", + .id = UCLASS_ETH, + .probe = r8152_eth_probe, + .ops = &r8152_eth_ops, + .priv_auto_alloc_size = sizeof(struct r8152), + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +}; + +static const struct usb_device_id r8152_eth_id_table[] = { + /* Realtek */ + { USB_DEVICE(0x0bda, 0x8050) }, + { USB_DEVICE(0x0bda, 0x8152) }, + { USB_DEVICE(0x0bda, 0x8153) }, + + /* Samsung */ + { USB_DEVICE(0x04e8, 0xa101) }, + + /* Lenovo */ + { USB_DEVICE(0x17ef, 0x304f) }, + { USB_DEVICE(0x17ef, 0x3052) }, + { USB_DEVICE(0x17ef, 0x3054) }, + { USB_DEVICE(0x17ef, 0x3057) }, + { USB_DEVICE(0x17ef, 0x7205) }, + { USB_DEVICE(0x17ef, 0x720a) }, + { USB_DEVICE(0x17ef, 0x720b) }, + { USB_DEVICE(0x17ef, 0x720c) }, + + /* TP-LINK */ + { USB_DEVICE(0x2357, 0x0601) }, + + /* Nvidia */ + { USB_DEVICE(0x0955, 0x09ff) }, + + { } /* Terminating entry */ +}; + +U_BOOT_USB_DEVICE(r8152_eth, r8152_eth_id_table); +#endif /* CONFIG_DM_ETH */ + diff --git a/drivers/usb/eth/r8152.h b/drivers/usb/eth/r8152.h index cd44da239d1..784ad997ac3 100644 --- a/drivers/usb/eth/r8152.h +++ b/drivers/usb/eth/r8152.h @@ -594,6 +594,10 @@ struct r8152 { u16 ocp_base; u8 version; + +#ifdef CONFIG_DM_ETH + struct ueth_data ueth; +#endif }; int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, diff --git a/drivers/usb/eth/r8152_fw.c b/drivers/usb/eth/r8152_fw.c index f820b16afca..b6c82283a87 100644 --- a/drivers/usb/eth/r8152_fw.c +++ b/drivers/usb/eth/r8152_fw.c @@ -5,7 +5,9 @@ * */ #include <common.h> +#include <dm.h> #include <errno.h> +#include "usb_ether.h" #include "r8152.h" static u8 r8152b_pla_patch_a[] = { diff --git a/drivers/usb/eth/smsc95xx.c b/drivers/usb/eth/smsc95xx.c index 08eaed5c2e0..7d9abfda3be 100644 --- a/drivers/usb/eth/smsc95xx.c +++ b/drivers/usb/eth/smsc95xx.c @@ -391,8 +391,8 @@ static int smsc95xx_write_hwaddr_common(struct usb_device *udev, struct smsc95xx_private *priv, unsigned char *enetaddr) { - u32 addr_lo = __get_unaligned_le32(&enetaddr[0]); - u32 addr_hi = __get_unaligned_le16(&enetaddr[4]); + u32 addr_lo = get_unaligned_le32(&enetaddr[0]); + u32 addr_hi = get_unaligned_le16(&enetaddr[4]); int ret; /* set hardware address */ diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index ae624766c10..40839d89e97 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -43,6 +43,11 @@ config USB_GADGET_ATMEL_USBA USBA is the integrated high-speed USB Device controller on the AT32AP700x, some AT91SAM9 and AT91CAP9 processors from Atmel. +config USB_GADGET_BCM_UDC_OTG_PHY + bool "Broadcom UDC OTG PHY" + help + Enable the Broadcom UDC OTG physical device interface. + config USB_GADGET_DWC2_OTG bool "DesignWare USB2.0 HS OTG controller (gadget mode)" select USB_GADGET_DUALSPEED diff --git a/drivers/usb/gadget/dwc2_udc_otg.c b/drivers/usb/gadget/dwc2_udc_otg.c index a23278d957a..029927f8ac1 100644 --- a/drivers/usb/gadget/dwc2_udc_otg.c +++ b/drivers/usb/gadget/dwc2_udc_otg.c @@ -403,6 +403,7 @@ static void reconfig_usbd(struct dwc2_udc *dev) int i; unsigned int uTemp = writel(CORE_SOFT_RESET, ®->grstctl); uint32_t dflt_gusbcfg; + uint32_t rx_fifo_sz, tx_fifo_sz, np_tx_fifo_sz; debug("Reseting OTG controller\n"); @@ -467,18 +468,27 @@ static void reconfig_usbd(struct dwc2_udc *dev) /* 10. Unmask device IN EP common interrupts*/ writel(DIEPMSK_INIT, ®->diepmsk); + rx_fifo_sz = RX_FIFO_SIZE; + np_tx_fifo_sz = NPTX_FIFO_SIZE; + tx_fifo_sz = PTX_FIFO_SIZE; + + if (dev->pdata->rx_fifo_sz) + rx_fifo_sz = dev->pdata->rx_fifo_sz; + if (dev->pdata->np_tx_fifo_sz) + np_tx_fifo_sz = dev->pdata->np_tx_fifo_sz; + if (dev->pdata->tx_fifo_sz) + tx_fifo_sz = dev->pdata->tx_fifo_sz; + /* 11. Set Rx FIFO Size (in 32-bit words) */ - writel(RX_FIFO_SIZE >> 2, ®->grxfsiz); + writel(rx_fifo_sz, ®->grxfsiz); /* 12. Set Non Periodic Tx FIFO Size */ - writel((NPTX_FIFO_SIZE >> 2) << 16 | ((RX_FIFO_SIZE >> 2)) << 0, + writel((np_tx_fifo_sz << 16) | rx_fifo_sz, ®->gnptxfsiz); for (i = 1; i < DWC2_MAX_HW_ENDPOINTS; i++) - writel((PTX_FIFO_SIZE >> 2) << 16 | - ((RX_FIFO_SIZE + NPTX_FIFO_SIZE + - PTX_FIFO_SIZE*(i-1)) >> 2) << 0, - ®->dieptxf[i-1]); + writel((rx_fifo_sz + np_tx_fifo_sz + tx_fifo_sz*(i-1)) | + tx_fifo_sz << 16, ®->dieptxf[i-1]); /* Flush the RX FIFO */ writel(RX_FIFO_FLUSH, ®->grstctl); diff --git a/drivers/usb/gadget/dwc2_udc_otg_regs.h b/drivers/usb/gadget/dwc2_udc_otg_regs.h index 78ec90ea9f4..c94396afc02 100644 --- a/drivers/usb/gadget/dwc2_udc_otg_regs.h +++ b/drivers/usb/gadget/dwc2_udc_otg_regs.h @@ -130,9 +130,9 @@ struct dwc2_usbotg_reg { #define HIGH_SPEED_CONTROL_PKT_SIZE 64 #define HIGH_SPEED_BULK_PKT_SIZE 512 -#define RX_FIFO_SIZE (1024*4) -#define NPTX_FIFO_SIZE (1024*4) -#define PTX_FIFO_SIZE (1536*1) +#define RX_FIFO_SIZE (1024) +#define NPTX_FIFO_SIZE (1024) +#define PTX_FIFO_SIZE (384) #define DEPCTL_TXFNUM_0 (0x0<<22) #define DEPCTL_TXFNUM_1 (0x1<<22) diff --git a/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c index 12f5c85c310..0d6d2fba8a0 100644 --- a/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c +++ b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c @@ -110,6 +110,9 @@ static int setdma_rx(struct dwc2_ep *ep, struct dwc2_request *req) ctrl = readl(®->out_endp[ep_num].doepctl); + invalidate_dcache_range((unsigned long) ep->dma_buf, + (unsigned long) ep->dma_buf + ep->len); + writel((unsigned int) ep->dma_buf, ®->out_endp[ep_num].doepdma); writel(DOEPT_SIZ_PKT_CNT(pktcnt) | DOEPT_SIZ_XFER_SIZE(length), ®->out_endp[ep_num].doeptsiz); diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 89580cc31f7..e0699d41ac1 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -3,8 +3,12 @@ # comment "USB Host Controller Drivers" +config USB_HOST + bool + config USB_XHCI_HCD bool "xHCI HCD (USB 3.0) support" + select USB_HOST ---help--- The eXtensible Host Controller Interface (xHCI) is standard for USB 3.0 "SuperSpeed" host controller hardware. @@ -24,18 +28,11 @@ config USB_XHCI_DWC3 Say Y or if your system has a Dual Role SuperSpeed USB controller based on the DesignWare USB3 IP Core. -endif - -config USB_OHCI_GENERIC - bool "Support for generic OHCI USB controller" - depends on OF_CONTROL - depends on DM_USB - default n - ---help--- - Enables support for generic OHCI controller. +endif # USB_XHCI_HCD config USB_EHCI_HCD bool "EHCI HCD (USB 2.0) support" + select USB_HOST ---help--- The Enhanced Host Controller Interface (EHCI) is standard for USB 2.0 "high speed" (480 Mbit/sec, 60 Mbyte/sec) host controller hardware. @@ -60,6 +57,13 @@ config USB_EHCI if USB_EHCI_HCD +config USB_EHCI_ATMEL + bool "Support for Atmel on-chip EHCI USB controller" + depends on ARCH_AT91 + default y + ---help--- + Enables support for the on-chip EHCI controller on Atmel chips. + config USB_EHCI_MARVELL bool "Support for MVEBU (AXP / A38x) on-chip EHCI USB controller" depends on ARCH_MVEBU @@ -74,6 +78,22 @@ config USB_EHCI_MX6 ---help--- Enables support for the on-chip EHCI controller on i.MX6 SoCs. +config USB_EHCI_MX7 + bool "Support for i.MX7 on-chip EHCI USB controller" + depends on ARCH_MX7 + default y + ---help--- + Enables support for the on-chip EHCI controller on i.MX7 SoCs. + +if USB_EHCI_MX7 + +config MXC_USB_OTG_HACTIVE + bool "USB Power pin high active" + ---help--- + Set the USB Power pin polarity to be high active (PWR_POL) + +endif + config USB_EHCI_MSM bool "Support for Qualcomm on-chip EHCI USB controller" depends on DM_USB @@ -85,6 +105,13 @@ config USB_EHCI_MSM This driver supports combination of Chipidea USB controller and Synapsys USB PHY in host mode only. +config USB_EHCI_ZYNQ + bool "Support for Xilinx Zynq on-chip EHCI USB controller" + depends on ARCH_ZYNQ + default y + ---help--- + Enable support for Zynq on-chip EHCI USB controller + config USB_EHCI_GENERIC bool "Support for generic EHCI USB controller" depends on OF_CONTROL @@ -93,4 +120,46 @@ config USB_EHCI_GENERIC ---help--- Enables support for generic EHCI controller. -endif +endif # USB_EHCI_HCD + +config USB_OHCI_HCD + bool "OHCI HCD (USB 1.1) support" + ---help--- + The Open Host Controller Interface (OHCI) is a standard for accessing + USB 1.1 host controller hardware. It does more in hardware than Intel's + UHCI specification. If your USB host controller follows the OHCI spec, + say Y. On most non-x86 systems, and on x86 hardware that's not using a + USB controller from Intel or VIA, this is appropriate. If your host + controller doesn't use PCI, this is probably appropriate. For a PCI + based system where you're not sure, the "lspci -v" entry will list the + right "prog-if" for your USB controller(s): EHCI, OHCI, or UHCI. + +if USB_OHCI_HCD + +config USB_OHCI_GENERIC + bool "Support for generic OHCI USB controller" + depends on OF_CONTROL + depends on DM_USB + select USB_HOST + ---help--- + Enables support for generic OHCI controller. + +endif # USB_OHCI_HCD + +config USB_UHCI_HCD + bool "UHCI HCD (most Intel and VIA) support" + select USB_HOST + ---help--- + The Universal Host Controller Interface is a standard by Intel for + accessing the USB hardware in the PC (which is also called the USB + host controller). If your USB host controller conforms to this + standard, you may want to say Y, but see below. All recent boards + with Intel PCI chipsets (like intel 430TX, 440FX, 440LX, 440BX, + i810, i820) conform to this standard. Also all VIA PCI chipsets + (like VIA VP2, VP3, MVP3, Apollo Pro, Apollo Pro II or Apollo Pro + 133) and LEON/GRLIB SoCs with the GRUSBHC controller. + If unsure, say Y. + +if USB_UHCI_HCD + +endif # USB_UHCI_HCD diff --git a/drivers/usb/host/ehci-atmel.c b/drivers/usb/host/ehci-atmel.c index 1d7d28048bc..d65bbe986c9 100644 --- a/drivers/usb/host/ehci-atmel.c +++ b/drivers/usb/host/ehci-atmel.c @@ -7,12 +7,18 @@ */ #include <common.h> +#include <clk.h> +#include <dm.h> #include <usb.h> #include <asm/io.h> #include <asm/arch/clk.h> #include "ehci.h" +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_DM_USB + int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, struct ehci_hcor **hcor) { @@ -41,3 +47,113 @@ int ehci_hcd_stop(int index) return 0; } + +#else + +struct ehci_atmel_priv { + struct ehci_ctrl ehci; +}; + +static int ehci_atmel_enable_clk(struct udevice *dev) +{ + struct udevice *dev_clk; + struct clk clk; + int periph; + int ret; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret) + return ret; + + ret = clk_enable(&clk); + if (ret) + return ret; + + ret = clk_get_by_index(dev, 1, &clk); + if (ret) + return -EINVAL; + + periph = fdtdec_get_uint(gd->fdt_blob, clk.dev->of_offset, "reg", -1); + if (periph < 0) + return -EINVAL; + + dev_clk = dev_get_parent(clk.dev); + if (!dev_clk) + return -ENODEV; + + ret = clk_request(dev_clk, &clk); + if (ret) + return ret; + + clk.id = periph; + ret = clk_enable(&clk); + if (ret) + return ret; + + clk_free(&clk); + + return 0; +} + +static int ehci_atmel_probe(struct udevice *dev) +{ + struct ehci_hccr *hccr; + struct ehci_hcor *hcor; + fdt_addr_t hcd_base; + int ret; + + ret = ehci_atmel_enable_clk(dev); + if (ret) { + debug("Failed to enable USB Host clock\n"); + return ret; + } + + /* + * Get the base address for EHCI controller from the device node + */ + hcd_base = dev_get_addr(dev); + if (hcd_base == FDT_ADDR_T_NONE) { + debug("Can't get the EHCI register base address\n"); + return -ENXIO; + } + + hccr = (struct ehci_hccr *)hcd_base; + hcor = (struct ehci_hcor *) + ((u32)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); + + debug("echi-atmel: init hccr %x and hcor %x hc_length %d\n", + (u32)hccr, (u32)hcor, + (u32)HC_LENGTH(ehci_readl(&hccr->cr_capbase))); + + return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST); +} + +static int ehci_atmel_remove(struct udevice *dev) +{ + int ret; + + ret = ehci_deregister(dev); + if (ret) + return ret; + + return 0; +} + +static const struct udevice_id ehci_usb_ids[] = { + { .compatible = "atmel,at91sam9g45-ehci", }, + { } +}; + +U_BOOT_DRIVER(ehci_atmel) = { + .name = "ehci_atmel", + .id = UCLASS_USB, + .of_match = ehci_usb_ids, + .probe = ehci_atmel_probe, + .remove = ehci_atmel_remove, + .ops = &ehci_usb_ops, + .platdata_auto_alloc_size = sizeof(struct usb_platdata), + .priv_auto_alloc_size = sizeof(struct ehci_atmel_priv), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; + +#endif diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index fa916ed77f9..f5e3ae796e1 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2009, 2011 Freescale Semiconductor, Inc. + * (C) Copyright 2009, 2011, 2016 Freescale Semiconductor, Inc. * * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB * @@ -16,14 +16,32 @@ #include <hwconfig.h> #include <fsl_usb.h> #include <fdt_support.h> +#include <dm.h> #include "ehci.h" +DECLARE_GLOBAL_DATA_PTR; + #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #endif +#ifdef CONFIG_DM_USB +struct ehci_fsl_priv { + struct ehci_ctrl ehci; + fdt_addr_t hcd_base; + char *phy_type; +}; +#endif + static void set_txfifothresh(struct usb_ehci *, u32); +#ifdef CONFIG_DM_USB +static int ehci_fsl_init(struct ehci_fsl_priv *priv, struct usb_ehci *ehci, + struct ehci_hccr *hccr, struct ehci_hcor *hcor); +#else +static int ehci_fsl_init(int index, struct usb_ehci *ehci, + struct ehci_hccr *hccr, struct ehci_hcor *hcor); +#endif /* Check USB PHY clock valid */ static int usb_phy_clk_valid(struct usb_ehci *ehci) @@ -37,6 +55,99 @@ static int usb_phy_clk_valid(struct usb_ehci *ehci) } } +#ifdef CONFIG_DM_USB +static int ehci_fsl_ofdata_to_platdata(struct udevice *dev) +{ + struct ehci_fsl_priv *priv = dev_get_priv(dev); + const void *prop; + + prop = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy_type", + NULL); + if (prop) { + priv->phy_type = (char *)prop; + debug("phy_type %s\n", priv->phy_type); + } + + return 0; +} + +static int ehci_fsl_init_after_reset(struct ehci_ctrl *ctrl) +{ + struct usb_ehci *ehci = NULL; + struct ehci_fsl_priv *priv = container_of(ctrl, struct ehci_fsl_priv, + ehci); + + ehci = (struct usb_ehci *)priv->hcd_base; + if (ehci_fsl_init(priv, ehci, priv->ehci.hccr, priv->ehci.hcor) < 0) + return -ENXIO; + + return 0; +} + +static const struct ehci_ops fsl_ehci_ops = { + .init_after_reset = ehci_fsl_init_after_reset, +}; + +static int ehci_fsl_probe(struct udevice *dev) +{ + struct ehci_fsl_priv *priv = dev_get_priv(dev); + struct usb_ehci *ehci = NULL; + struct ehci_hccr *hccr; + struct ehci_hcor *hcor; + + /* + * Get the base address for EHCI controller from the device node + */ + priv->hcd_base = dev_get_addr(dev); + if (priv->hcd_base == FDT_ADDR_T_NONE) { + debug("Can't get the EHCI register base address\n"); + return -ENXIO; + } + ehci = (struct usb_ehci *)priv->hcd_base; + hccr = (struct ehci_hccr *)(&ehci->caplength); + hcor = (struct ehci_hcor *) + ((u32)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); + + if (ehci_fsl_init(priv, ehci, hccr, hcor) < 0) + return -ENXIO; + + debug("ehci-fsl: init hccr %x and hcor %x hc_length %d\n", + (u32)hccr, (u32)hcor, + (u32)HC_LENGTH(ehci_readl(&hccr->cr_capbase))); + + return ehci_register(dev, hccr, hcor, &fsl_ehci_ops, 0, USB_INIT_HOST); +} + +static int ehci_fsl_remove(struct udevice *dev) +{ + int ret; + + ret = ehci_deregister(dev); + if (ret) + return ret; + + return 0; +} + +static const struct udevice_id ehci_usb_ids[] = { + { .compatible = "fsl-usb2-mph", }, + { .compatible = "fsl-usb2-dr", }, + { } +}; + +U_BOOT_DRIVER(ehci_fsl) = { + .name = "ehci_fsl", + .id = UCLASS_USB, + .of_match = ehci_usb_ids, + .ofdata_to_platdata = ehci_fsl_ofdata_to_platdata, + .probe = ehci_fsl_probe, + .remove = ehci_fsl_remove, + .ops = &ehci_usb_ops, + .platdata_auto_alloc_size = sizeof(struct usb_platdata), + .priv_auto_alloc_size = sizeof(struct ehci_fsl_priv), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; +#else /* * Create the appropriate control structures to manage * a new EHCI host controller. @@ -47,9 +158,49 @@ int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, struct ehci_hcor **hcor) { struct usb_ehci *ehci = NULL; + + switch (index) { + case 0: + ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR; + break; + case 1: + ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB2_ADDR; + break; + default: + printf("ERROR: wrong controller index!!\n"); + return -EINVAL; + }; + + *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); + *hcor = (struct ehci_hcor *)((uint32_t) *hccr + + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); + + return ehci_fsl_init(index, ehci, *hccr, *hcor); +} + +/* + * Destroy the appropriate control structures corresponding + * the the EHCI host controller. + */ +int ehci_hcd_stop(int index) +{ + return 0; +} +#endif + +#ifdef CONFIG_DM_USB +static int ehci_fsl_init(struct ehci_fsl_priv *priv, struct usb_ehci *ehci, + struct ehci_hccr *hccr, struct ehci_hcor *hcor) +#else +static int ehci_fsl_init(int index, struct usb_ehci *ehci, + struct ehci_hccr *hccr, struct ehci_hcor *hcor) +#endif +{ const char *phy_type = NULL; +#ifndef CONFIG_DM_USB size_t len; char current_usb_controller[5]; +#endif #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY char usb_phy[5]; @@ -64,25 +215,6 @@ int ehci_hcd_init(int index, enum usb_init_type init, */ mdelay(5); } - memset(current_usb_controller, '\0', 5); - snprintf(current_usb_controller, sizeof(current_usb_controller), - "usb%d", index+1); - - switch (index) { - case 0: - ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR; - break; - case 1: - ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB2_ADDR; - break; - default: - printf("ERROR: wrong controller index!!\n"); - return -EINVAL; - }; - - *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); - *hcor = (struct ehci_hcor *)((uint32_t) *hccr + - HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); /* Set to Host mode */ setbits_le32(&ehci->usbmode, CM_HOST); @@ -91,9 +223,18 @@ int ehci_hcd_init(int index, enum usb_init_type init, out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB); /* Init phy */ +#ifdef CONFIG_DM_USB + if (priv->phy_type) + phy_type = priv->phy_type; +#else + memset(current_usb_controller, '\0', 5); + snprintf(current_usb_controller, sizeof(current_usb_controller), + "usb%d", index+1); + if (hwconfig_sub(current_usb_controller, "phy_type")) phy_type = hwconfig_subarg(current_usb_controller, "phy_type", &len); +#endif else phy_type = getenv("usb_phy_type"); @@ -116,7 +257,7 @@ int ehci_hcd_init(int index, enum usb_init_type init, UTMI_PHY_EN); udelay(1000); /* delay required for PHY Clk to appear */ #endif - out_le32(&(*hcor)->or_portsc[0], PORT_PTS_UTMI); + out_le32(&(hcor)->or_portsc[0], PORT_PTS_UTMI); clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK, USB_EN); } else { @@ -127,7 +268,7 @@ int ehci_hcd_init(int index, enum usb_init_type init, udelay(1000); /* delay required for PHY Clk to appear */ if (!usb_phy_clk_valid(ehci)) return -EINVAL; - out_le32(&(*hcor)->or_portsc[0], PORT_PTS_ULPI); + out_le32(&(hcor)->or_portsc[0], PORT_PTS_ULPI); } out_be32(&ehci->prictrl, 0x0000000c); @@ -153,15 +294,6 @@ int ehci_hcd_init(int index, enum usb_init_type init, } /* - * Destroy the appropriate control structures corresponding - * the the EHCI host controller. - */ -int ehci_hcd_stop(int index) -{ - return 0; -} - -/* * Setting the value of TXFIFO_THRESH field in TXFILLTUNING register * to counter DDR latencies in writing data into Tx buffer. * This prevents Tx buffer from getting underrun diff --git a/drivers/usb/host/ehci-mx6.c b/drivers/usb/host/ehci-mx6.c index 069f116ed2d..602fec53948 100644 --- a/drivers/usb/host/ehci-mx6.c +++ b/drivers/usb/host/ehci-mx6.c @@ -15,6 +15,7 @@ #include <asm/arch/imx-regs.h> #include <asm/arch/clock.h> #include <asm/imx-common/iomux-v3.h> +#include <dm.h> #include "ehci.h" @@ -49,7 +50,7 @@ #define USBNC_OFFSET 0x200 #define USBNC_PHYSTATUS_ID_DIG (1 << 4) /* otg_id status */ #define USBNC_PHYCFG2_ACAENB (1 << 4) /* otg_id detection enable */ -#define UCTRL_PM (1 << 9) /* OTG Power Mask */ +#define UCTRL_PWR_POL (1 << 9) /* OTG Polarity of Power Pin */ #define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */ #define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */ @@ -207,12 +208,20 @@ static void usb_power_config(int index) struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR + (0x10000 * index) + USBNC_OFFSET); void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2); + void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1); /* * Clear the ACAENB to enable usb_otg_id detection, * otherwise it is the ACA detection enabled. */ clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB); + + /* Set power polarity to high active */ +#ifdef CONFIG_MXC_USB_OTG_HACTIVE + setbits_le32(ctrl, UCTRL_PWR_POL); +#else + clrbits_le32(ctrl, UCTRL_PWR_POL); +#endif } int usb_phy_mode(int port) @@ -250,11 +259,7 @@ static void usb_oc_config(int index) setbits_le32(ctrl, UCTRL_OVER_CUR_POL); #endif -#if defined(CONFIG_MX6) setbits_le32(ctrl, UCTRL_OVER_CUR_DIS); -#elif defined(CONFIG_MX7) - setbits_le32(ctrl, UCTRL_OVER_CUR_DIS | UCTRL_PM); -#endif } /** @@ -303,6 +308,30 @@ int __weak board_ehci_power(int port, int on) return 0; } +int ehci_mx6_common_init(struct usb_ehci *ehci, int index) +{ + int ret; + + enable_usboh3_clk(1); + mdelay(1); + + /* Do board specific initialization */ + ret = board_ehci_hcd_init(index); + if (ret) + return ret; + + usb_power_config(index); + usb_oc_config(index); + +#if defined(CONFIG_MX6) + usb_internal_phy_clock_gate(index, 1); + usb_phy_enable(index, ehci); +#endif + + return 0; +} + +#ifndef CONFIG_DM_USB int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, struct ehci_hcor **hcor) { @@ -318,26 +347,18 @@ int ehci_hcd_init(int index, enum usb_init_type init, if (index > 3) return -EINVAL; - enable_usboh3_clk(1); - mdelay(1); - /* Do board specific initialization */ - ret = board_ehci_hcd_init(index); + ret = ehci_mx6_common_init(ehci, index); if (ret) return ret; - usb_power_config(index); - usb_oc_config(index); - -#if defined(CONFIG_MX6) - usb_internal_phy_clock_gate(index, 1); - usb_phy_enable(index, ehci); -#endif type = board_usb_phy_mode(index); - *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); - *hcor = (struct ehci_hcor *)((uint32_t)*hccr + - HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); + if (hccr && hcor) { + *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); + *hcor = (struct ehci_hcor *)((uint32_t)*hccr + + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); + } if ((type == init) || (type == USB_INIT_DEVICE)) board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1); @@ -359,3 +380,102 @@ int ehci_hcd_stop(int index) { return 0; } +#else +struct ehci_mx6_priv_data { + struct ehci_ctrl ctrl; + struct usb_ehci *ehci; + enum usb_init_type init_type; + int portnr; +}; + +static int mx6_init_after_reset(struct ehci_ctrl *dev) +{ + struct ehci_mx6_priv_data *priv = dev->priv; + enum usb_init_type type = priv->init_type; + struct usb_ehci *ehci = priv->ehci; + int ret; + + ret = ehci_mx6_common_init(priv->ehci, priv->portnr); + if (ret) + return ret; + + board_ehci_power(priv->portnr, (type == USB_INIT_DEVICE) ? 0 : 1); + + if (type == USB_INIT_DEVICE) + return 0; + + setbits_le32(&ehci->usbmode, CM_HOST); + writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); + setbits_le32(&ehci->portsc, USB_EN); + + mdelay(10); + + return 0; +} + +static const struct ehci_ops mx6_ehci_ops = { + .init_after_reset = mx6_init_after_reset +}; + +static int ehci_usb_probe(struct udevice *dev) +{ + struct usb_platdata *plat = dev_get_platdata(dev); + struct usb_ehci *ehci = (struct usb_ehci *)dev_get_addr(dev); + struct ehci_mx6_priv_data *priv = dev_get_priv(dev); + struct ehci_hccr *hccr; + struct ehci_hcor *hcor; + int ret; + + priv->ehci = ehci; + priv->portnr = dev->seq; + priv->init_type = plat->init_type; + + ret = ehci_mx6_common_init(ehci, priv->portnr); + if (ret) + return ret; + + board_ehci_power(priv->portnr, (priv->init_type == USB_INIT_DEVICE) ? 0 : 1); + + if (priv->init_type == USB_INIT_HOST) { + setbits_le32(&ehci->usbmode, CM_HOST); + writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); + setbits_le32(&ehci->portsc, USB_EN); + } + + mdelay(10); + + hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); + hcor = (struct ehci_hcor *)((uint32_t)hccr + + HC_LENGTH(ehci_readl(&(hccr)->cr_capbase))); + + return ehci_register(dev, hccr, hcor, &mx6_ehci_ops, 0, priv->init_type); +} + +static int ehci_usb_remove(struct udevice *dev) +{ + int ret; + + ret = ehci_deregister(dev); + if (ret) + return ret; + + return 0; +} + +static const struct udevice_id mx6_usb_ids[] = { + { .compatible = "fsl,imx27-usb" }, + { } +}; + +U_BOOT_DRIVER(usb_mx6) = { + .name = "ehci_mx6", + .id = UCLASS_USB, + .of_match = mx6_usb_ids, + .probe = ehci_usb_probe, + .remove = ehci_usb_remove, + .ops = &ehci_usb_ops, + .platdata_auto_alloc_size = sizeof(struct usb_platdata), + .priv_auto_alloc_size = sizeof(struct ehci_mx6_priv_data), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; +#endif diff --git a/drivers/usb/host/ehci-zynq.c b/drivers/usb/host/ehci-zynq.c index 37a7935b436..76642cdad7d 100644 --- a/drivers/usb/host/ehci-zynq.c +++ b/drivers/usb/host/ehci-zynq.c @@ -7,55 +7,48 @@ */ #include <common.h> +#include <dm.h> +#include <usb.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> #include <asm/io.h> -#include <usb.h> #include <usb/ehci-ci.h> #include <usb/ulpi.h> #include "ehci.h" -#define ZYNQ_USB_USBCMD_RST 0x0000002 -#define ZYNQ_USB_USBCMD_STOP 0x0000000 -#define ZYNQ_USB_NUM_MIO 12 +struct zynq_ehci_priv { + struct ehci_ctrl ehcictrl; + struct usb_ehci *ehci; +}; -/* - * Create the appropriate control structures to manage - * a new EHCI host controller. - */ -int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, - struct ehci_hcor **hcor) +static int ehci_zynq_ofdata_to_platdata(struct udevice *dev) { - struct usb_ehci *ehci; + struct zynq_ehci_priv *priv = dev_get_priv(dev); + + priv->ehci = (struct usb_ehci *)dev_get_addr_ptr(dev); + if (!priv->ehci) + return -EINVAL; + + return 0; +} + +static int ehci_zynq_probe(struct udevice *dev) +{ + struct usb_platdata *plat = dev_get_platdata(dev); + struct zynq_ehci_priv *priv = dev_get_priv(dev); + struct ehci_hccr *hccr; + struct ehci_hcor *hcor; struct ulpi_viewport ulpi_vp; - int ret, mio_usb; /* Used for writing the ULPI data address */ struct ulpi_regs *ulpi = (struct ulpi_regs *)0; + int ret; - if (!index) { - mio_usb = zynq_slcr_get_mio_pin_status("usb0"); - if (mio_usb != ZYNQ_USB_NUM_MIO) { - printf("usb0 wrong num MIO: %d, Index %d\n", mio_usb, - index); - return -1; - } - ehci = (struct usb_ehci *)ZYNQ_USB_BASEADDR0; - } else { - mio_usb = zynq_slcr_get_mio_pin_status("usb1"); - if (mio_usb != ZYNQ_USB_NUM_MIO) { - printf("usb1 wrong num MIO: %d, Index %d\n", mio_usb, - index); - return -1; - } - ehci = (struct usb_ehci *)ZYNQ_USB_BASEADDR1; - } - - *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); - *hcor = (struct ehci_hcor *)((uint32_t) *hccr + - HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); + hccr = (struct ehci_hccr *)((uint32_t)&priv->ehci->caplength); + hcor = (struct ehci_hcor *)((uint32_t) hccr + + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); - ulpi_vp.viewport_addr = (u32)&ehci->ulpi_viewpoint; + ulpi_vp.viewport_addr = (u32)&priv->ehci->ulpi_viewpoint; ulpi_vp.port_num = 0; ret = ulpi_init(&ulpi_vp); @@ -77,28 +70,34 @@ int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, ulpi_write(&ulpi_vp, &ulpi->otg_ctrl_set, ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); - return 0; + return ehci_register(dev, hccr, hcor, NULL, 0, plat->init_type); } -/* - * Destroy the appropriate control structures corresponding - * the the EHCI host controller. - */ -int ehci_hcd_stop(int index) +static int ehci_zynq_remove(struct udevice *dev) { - struct usb_ehci *ehci; - - if (!index) - ehci = (struct usb_ehci *)ZYNQ_USB_BASEADDR0; - else - ehci = (struct usb_ehci *)ZYNQ_USB_BASEADDR1; + int ret; - /* Stop controller */ - writel(ZYNQ_USB_USBCMD_STOP, &ehci->usbcmd); - udelay(1000); - - /* Initiate controller reset */ - writel(ZYNQ_USB_USBCMD_RST, &ehci->usbcmd); + ret = ehci_deregister(dev); + if (ret) + return ret; return 0; } + +static const struct udevice_id ehci_zynq_ids[] = { + { .compatible = "xlnx,zynq-usb-2.20a" }, + { } +}; + +U_BOOT_DRIVER(ehci_zynq) = { + .name = "ehci_zynq", + .id = UCLASS_USB, + .of_match = ehci_zynq_ids, + .ofdata_to_platdata = ehci_zynq_ofdata_to_platdata, + .probe = ehci_zynq_probe, + .remove = ehci_zynq_remove, + .ops = &ehci_usb_ops, + .platdata_auto_alloc_size = sizeof(struct usb_platdata), + .priv_auto_alloc_size = sizeof(struct zynq_ehci_priv), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; diff --git a/drivers/usb/host/usb-uclass.c b/drivers/usb/host/usb-uclass.c index 69c9a504ebb..be114fc0771 100644 --- a/drivers/usb/host/usb-uclass.c +++ b/drivers/usb/host/usb-uclass.c @@ -14,7 +14,6 @@ #include <usb.h> #include <dm/device-internal.h> #include <dm/lists.h> -#include <dm/root.h> #include <dm/uclass-internal.h> DECLARE_GLOBAL_DATA_PTR; @@ -349,12 +348,6 @@ struct usb_device *usb_get_dev_index(struct udevice *bus, int index) } #endif -int usb_post_bind(struct udevice *dev) -{ - /* Scan the bus for devices */ - return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false); -} - int usb_setup_ehci_gadget(struct ehci_ctrl **ctlrp) { struct usb_platdata *plat; @@ -768,7 +761,7 @@ UCLASS_DRIVER(usb) = { .id = UCLASS_USB, .name = "usb", .flags = DM_UC_FLAG_SEQ_ALIAS, - .post_bind = usb_post_bind, + .post_bind = dm_scan_fdt_dev, .priv_auto_alloc_size = sizeof(struct usb_uclass_priv), .per_child_auto_alloc_size = sizeof(struct usb_device), .per_device_auto_alloc_size = sizeof(struct usb_bus_priv), diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c index c12a1894857..bdcd4f1c991 100644 --- a/drivers/usb/host/xhci-fsl.c +++ b/drivers/usb/host/xhci-fsl.c @@ -1,5 +1,5 @@ /* - * Copyright 2015 Freescale Semiconductor, Inc. + * Copyright 2015,2016 Freescale Semiconductor, Inc. * * FSL USB HOST xHCI Controller * @@ -17,12 +17,21 @@ #include "xhci.h" #include <fsl_errata.h> #include <fsl_usb.h> +#include <dm.h> /* Declare global data pointer */ DECLARE_GLOBAL_DATA_PTR; +#ifndef CONFIG_DM_USB static struct fsl_xhci fsl_xhci; unsigned long ctr_addr[] = FSL_USB_XHCI_ADDR; +#else +struct xhci_fsl_priv { + struct xhci_ctrl xhci; + fdt_addr_t hcd_base; + struct fsl_xhci ctx; +}; +#endif __weak int __board_usb_init(int index, enum usb_init_type init) { @@ -77,6 +86,77 @@ static int fsl_xhci_core_exit(struct fsl_xhci *fsl_xhci) return 0; } +#ifdef CONFIG_DM_USB +static int xhci_fsl_probe(struct udevice *dev) +{ + struct xhci_fsl_priv *priv = dev_get_priv(dev); + struct xhci_hccr *hccr; + struct xhci_hcor *hcor; + + int ret = 0; + + /* + * Get the base address for XHCI controller from the device node + */ + priv->hcd_base = dev_get_addr(dev); + if (priv->hcd_base == FDT_ADDR_T_NONE) { + debug("Can't get the XHCI register base address\n"); + return -ENXIO; + } + priv->ctx.hcd = (struct xhci_hccr *)priv->hcd_base; + priv->ctx.dwc3_reg = (struct dwc3 *)((char *)(priv->hcd_base) + + DWC3_REG_OFFSET); + + fsl_apply_xhci_errata(); + + ret = fsl_xhci_core_init(&priv->ctx); + if (ret < 0) { + puts("Failed to initialize xhci\n"); + return ret; + } + + hccr = (struct xhci_hccr *)(priv->ctx.hcd); + hcor = (struct xhci_hcor *)((uintptr_t) hccr + + HC_LENGTH(xhci_readl(&hccr->cr_capbase))); + + debug("xhci-fsl: init hccr %lx and hcor %lx hc_length %lx\n", + (uintptr_t)hccr, (uintptr_t)hcor, + (uintptr_t)HC_LENGTH(xhci_readl(&hccr->cr_capbase))); + + return xhci_register(dev, hccr, hcor); +} + +static int xhci_fsl_remove(struct udevice *dev) +{ + struct xhci_fsl_priv *priv = dev_get_priv(dev); + int ret; + + fsl_xhci_core_exit(&priv->ctx); + + ret = xhci_deregister(dev); + if (ret) + return ret; + + return 0; +} + +static const struct udevice_id xhci_usb_ids[] = { + { .compatible = "fsl,layerscape-dwc3", }, + { } +}; + +U_BOOT_DRIVER(xhci_fsl) = { + .name = "xhci_fsl", + .id = UCLASS_USB, + .of_match = xhci_usb_ids, + .probe = xhci_fsl_probe, + .remove = xhci_fsl_remove, + .ops = &xhci_usb_ops, + .platdata_auto_alloc_size = sizeof(struct usb_platdata), + .priv_auto_alloc_size = sizeof(struct xhci_fsl_priv), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; +#else int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor) { struct fsl_xhci *ctx = &fsl_xhci; @@ -116,3 +196,4 @@ void xhci_hcd_stop(int index) fsl_xhci_core_exit(ctx); } +#endif diff --git a/drivers/usb/musb-new/musb_dsps.c b/drivers/usb/musb-new/musb_dsps.c index bb7c9522927..a71db76d7c7 100644 --- a/drivers/usb/musb-new/musb_dsps.c +++ b/drivers/usb/musb-new/musb_dsps.c @@ -627,7 +627,7 @@ static int __devinit dsps_probe(struct platform_device *pdev) /* get memory resource */ iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!iomem) { - dev_err(&pdev->dev, "failed to get usbss mem resourse\n"); + dev_err(&pdev->dev, "failed to get usbss mem resource\n"); ret = -ENODEV; goto err1; } diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile index 93d147e26f1..4e548c24ec8 100644 --- a/drivers/usb/phy/Makefile +++ b/drivers/usb/phy/Makefile @@ -7,3 +7,4 @@ obj-$(CONFIG_TWL4030_USB) += twl4030.o obj-$(CONFIG_OMAP_USB_PHY) += omap_usb_phy.o +obj-$(CONFIG_ROCKCHIP_USB2_PHY) += rockchip_usb2_phy.o diff --git a/drivers/usb/phy/rockchip_usb2_phy.c b/drivers/usb/phy/rockchip_usb2_phy.c new file mode 100644 index 00000000000..1958478d628 --- /dev/null +++ b/drivers/usb/phy/rockchip_usb2_phy.c @@ -0,0 +1,107 @@ +/* + * Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <libfdt.h> + +#include "../gadget/dwc2_udc_otg_priv.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define BIT_WRITEABLE_SHIFT 16 + +struct usb2phy_reg { + unsigned int offset; + unsigned int bitend; + unsigned int bitstart; + unsigned int disable; + unsigned int enable; +}; + +/** + * struct rockchip_usb2_phy_cfg: usb-phy port configuration + * @port_reset: usb otg per-port reset register + * @soft_con: software control usb otg register + * @suspend: phy suspend register + */ +struct rockchip_usb2_phy_cfg { + struct usb2phy_reg port_reset; + struct usb2phy_reg soft_con; + struct usb2phy_reg suspend; +}; + +struct rockchip_usb2_phy_dt_id { + char compatible[128]; + const void *data; +}; + +static const struct rockchip_usb2_phy_cfg rk3288_pdata = { + .port_reset = {0x00, 12, 12, 0, 1}, + .soft_con = {0x08, 2, 2, 0, 1}, + .suspend = {0x0c, 5, 0, 0x01, 0x2A}, +}; + +static struct rockchip_usb2_phy_dt_id rockchip_usb2_phy_dt_ids[] = { + { .compatible = "rockchip,rk3288-usb-phy", .data = &rk3288_pdata }, + {} +}; + +static void property_enable(struct dwc2_plat_otg_data *pdata, + const struct usb2phy_reg *reg, bool en) +{ + unsigned int val, mask, tmp; + + tmp = en ? reg->enable : reg->disable; + mask = GENMASK(reg->bitend, reg->bitstart); + val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); + + writel(val, pdata->regs_phy + reg->offset); +} + + +void otg_phy_init(struct dwc2_udc *dev) +{ + struct dwc2_plat_otg_data *pdata = dev->pdata; + struct rockchip_usb2_phy_cfg *phy_cfg = NULL; + struct rockchip_usb2_phy_dt_id *of_id; + int i; + + for (i = 0; i < ARRAY_SIZE(rockchip_usb2_phy_dt_ids); i++) { + of_id = &rockchip_usb2_phy_dt_ids[i]; + if (fdt_node_check_compatible(gd->fdt_blob, pdata->phy_of_node, + of_id->compatible) == 0) { + phy_cfg = (struct rockchip_usb2_phy_cfg *)of_id->data; + break; + } + } + if (!phy_cfg) { + debug("Can't find device platform data\n"); + + hang(); + return; + } + pdata->priv = phy_cfg; + /* disable software control */ + property_enable(pdata, &phy_cfg->soft_con, false); + + /* reset otg port */ + property_enable(pdata, &phy_cfg->port_reset, true); + mdelay(1); + property_enable(pdata, &phy_cfg->port_reset, false); + udelay(1); +} + +void otg_phy_off(struct dwc2_udc *dev) +{ + struct dwc2_plat_otg_data *pdata = dev->pdata; + struct rockchip_usb2_phy_cfg *phy_cfg = pdata->priv; + + /* enable software control */ + property_enable(pdata, &phy_cfg->soft_con, true); + /* enter suspend */ + property_enable(pdata, &phy_cfg->suspend, true); +} diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index ef4984becb4..30b53dbb80e 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -1929,10 +1929,10 @@ static void plot_logo_or_black(void *screen, int x, int y, int black) static void *video_logo(void) { char info[128]; - int space, len; __maybe_unused int y_off = 0; __maybe_unused ulong addr; __maybe_unused char *s; + __maybe_unused int len, space; splash_get_pos(&video_logo_xpos, &video_logo_ypos); @@ -1978,6 +1978,7 @@ static void *video_logo(void) sprintf(info, " %s", version_string); +#ifndef CONFIG_HIDE_LOGO_VERSION space = (VIDEO_LINE_LEN / 2 - VIDEO_INFO_X) / VIDEO_FONT_WIDTH; len = strlen(info); @@ -2027,6 +2028,7 @@ static void *video_logo(void) } } #endif +#endif return (video_fb_address + video_logo_height * VIDEO_LINE_LEN); } diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c index cc26f1956d3..c6d88d9225d 100644 --- a/drivers/video/rockchip/rk_vop.c +++ b/drivers/video/rockchip/rk_vop.c @@ -238,7 +238,7 @@ int rk_display_init(struct udevice *dev, ulong fbbase, return ret; } - ret = uclass_get_device(UCLASS_CLK, 0, &dev_clk); + ret = rockchip_get_clk(&dev_clk); if (!ret) { clk.id = DCLK_VOP0 + remote_vop_id; ret = clk_request(dev_clk, &clk); diff --git a/drivers/video/tegra.c b/drivers/video/tegra.c index 217f05f9e2e..92214d61b27 100644 --- a/drivers/video/tegra.c +++ b/drivers/video/tegra.c @@ -251,7 +251,7 @@ static int setup_window(struct disp_ctl_win *win, /** * Register a new display based on device tree configuration. * - * The frame buffer can be positioned by U-Boot or overriden by the fdt. + * The frame buffer can be positioned by U-Boot or overridden by the fdt. * You should pass in the U-Boot address here, and check the contents of * struct tegra_lcd_priv to see what was actually chosen. * diff --git a/drivers/watchdog/imx_watchdog.c b/drivers/watchdog/imx_watchdog.c index f9f817596ff..2938d9f1fe9 100644 --- a/drivers/watchdog/imx_watchdog.c +++ b/drivers/watchdog/imx_watchdog.c @@ -39,7 +39,7 @@ void hw_watchdog_init(void) } #endif -void reset_cpu(ulong addr) +void __attribute__((weak)) reset_cpu(ulong addr) { struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; 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