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-rw-r--r--drivers/clk/uniphier/Kconfig5
-rw-r--r--drivers/clk/uniphier/clk-uniphier-core.c4
-rw-r--r--drivers/clk/uniphier/clk-uniphier-mio.c2
-rw-r--r--drivers/pinctrl/uniphier/Kconfig6
-rw-r--r--drivers/pinctrl/uniphier/Makefile1
-rw-r--r--drivers/pinctrl/uniphier/pinctrl-uniphier-sld3.c129
-rw-r--r--drivers/ram/Kconfig2
-rw-r--r--drivers/reset/reset-uniphier.c71
-rw-r--r--drivers/timer/Kconfig8
-rw-r--r--drivers/timer/Makefile1
-rw-r--r--drivers/timer/atmel_pit_timer.c90
-rw-r--r--drivers/usb/gadget/f_fastboot.c4
-rw-r--r--drivers/usb/host/Kconfig6
13 files changed, 127 insertions, 202 deletions
diff --git a/drivers/clk/uniphier/Kconfig b/drivers/clk/uniphier/Kconfig
index da3e3553895..3666d8414ce 100644
--- a/drivers/clk/uniphier/Kconfig
+++ b/drivers/clk/uniphier/Kconfig
@@ -1,9 +1,8 @@
config CLK_UNIPHIER
- bool "Clock driver for UniPhier SoCs"
+ def_bool y
depends on ARCH_UNIPHIER
select CLK
- select SPL_CLK
- default y
+ select SPL_CLK if SPL
help
Support for clock controllers on UniPhier SoCs.
Say Y if you want to control clocks provided by System Control
diff --git a/drivers/clk/uniphier/clk-uniphier-core.c b/drivers/clk/uniphier/clk-uniphier-core.c
index 0fb48541b9b..eed21b9a687 100644
--- a/drivers/clk/uniphier/clk-uniphier-core.c
+++ b/drivers/clk/uniphier/clk-uniphier-core.c
@@ -147,10 +147,6 @@ static int uniphier_clk_probe(struct udevice *dev)
static const struct udevice_id uniphier_clk_match[] = {
{
- .compatible = "socionext,uniphier-sld3-mio-clock",
- .data = (ulong)&uniphier_mio_clk_data,
- },
- {
.compatible = "socionext,uniphier-ld4-mio-clock",
.data = (ulong)&uniphier_mio_clk_data,
},
diff --git a/drivers/clk/uniphier/clk-uniphier-mio.c b/drivers/clk/uniphier/clk-uniphier-mio.c
index 18e68567092..9c13dcd5551 100644
--- a/drivers/clk/uniphier/clk-uniphier-mio.c
+++ b/drivers/clk/uniphier/clk-uniphier-mio.c
@@ -64,11 +64,9 @@ static const struct uniphier_clk_gate_data uniphier_mio_clk_gate[] = {
UNIPHIER_MIO_CLK_USB2(8, 0),
UNIPHIER_MIO_CLK_USB2(9, 1),
UNIPHIER_MIO_CLK_USB2(10, 2),
- UNIPHIER_MIO_CLK_USB2(11, 3), /* for PH1-sLD3 only */
UNIPHIER_MIO_CLK_USB2_PHY(12, 0),
UNIPHIER_MIO_CLK_USB2_PHY(13, 1),
UNIPHIER_MIO_CLK_USB2_PHY(14, 2),
- UNIPHIER_MIO_CLK_USB2_PHY(15, 3), /* for PH1-sLD3 only */
UNIPHIER_CLK_END
};
diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig
index a6e51caba5f..b6abcd12ff3 100644
--- a/drivers/pinctrl/uniphier/Kconfig
+++ b/drivers/pinctrl/uniphier/Kconfig
@@ -3,12 +3,6 @@ if ARCH_UNIPHIER
config PINCTRL_UNIPHIER
bool
-config PINCTRL_UNIPHIER_SLD3
- bool "UniPhier sLD3 SoC pinctrl driver"
- depends on ARCH_UNIPHIER_SLD3
- default y
- select PINCTRL_UNIPHIER
-
config PINCTRL_UNIPHIER_LD4
bool "UniPhier LD4 SoC pinctrl driver"
depends on ARCH_UNIPHIER_LD4
diff --git a/drivers/pinctrl/uniphier/Makefile b/drivers/pinctrl/uniphier/Makefile
index b805765ed1c..215104b61b4 100644
--- a/drivers/pinctrl/uniphier/Makefile
+++ b/drivers/pinctrl/uniphier/Makefile
@@ -4,7 +4,6 @@
obj-y += pinctrl-uniphier-core.o
-obj-$(CONFIG_PINCTRL_UNIPHIER_SLD3) += pinctrl-uniphier-sld3.o
obj-$(CONFIG_PINCTRL_UNIPHIER_LD4) += pinctrl-uniphier-ld4.o
obj-$(CONFIG_PINCTRL_UNIPHIER_PRO4) += pinctrl-uniphier-pro4.o
obj-$(CONFIG_PINCTRL_UNIPHIER_SLD8) += pinctrl-uniphier-sld8.o
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld3.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld3.c
deleted file mode 100644
index e9cc9d205d8..00000000000
--- a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld3.c
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- * Copyright (C) 2016 Socionext Inc.
- * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <dm.h>
-#include <dm/pinctrl.h>
-
-#include "pinctrl-uniphier.h"
-
-static const unsigned emmc_pins[] = {55, 56, 60};
-static const int emmc_muxvals[] = {1, 1, 1};
-static const unsigned emmc_dat8_pins[] = {57};
-static const int emmc_dat8_muxvals[] = {1};
-static const unsigned ether_mii_pins[] = {35, 107, 108, 109, 110, 111, 112,
- 113};
-static const int ether_mii_muxvals[] = {1, 2, 2, 2, 2, 2, 2, 2};
-static const unsigned ether_rmii_pins[] = {35};
-static const int ether_rmii_muxvals[] = {1};
-static const unsigned i2c0_pins[] = {36};
-static const int i2c0_muxvals[] = {0};
-static const unsigned nand_pins[] = {38, 39, 40, 58, 59};
-static const int nand_muxvals[] = {1, 1, 1, 1, 1};
-static const unsigned nand_cs1_pins[] = {41};
-static const int nand_cs1_muxvals[] = {1};
-static const unsigned sd_pins[] = {42, 43, 44, 45};
-static const int sd_muxvals[] = {1, 1, 1, 1};
-static const unsigned system_bus_pins[] = {46, 50, 51, 53, 54, 73, 74, 75, 76,
- 77, 78, 79, 80, 88, 89, 91, 92, 99};
-static const int system_bus_muxvals[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1};
-static const unsigned system_bus_cs0_pins[] = {93};
-static const int system_bus_cs0_muxvals[] = {1};
-static const unsigned system_bus_cs1_pins[] = {94};
-static const int system_bus_cs1_muxvals[] = {1};
-static const unsigned system_bus_cs2_pins[] = {95};
-static const int system_bus_cs2_muxvals[] = {1};
-static const unsigned system_bus_cs3_pins[] = {96};
-static const int system_bus_cs3_muxvals[] = {1};
-static const unsigned system_bus_cs4_pins[] = {81};
-static const int system_bus_cs4_muxvals[] = {1};
-static const unsigned system_bus_cs5_pins[] = {82};
-static const int system_bus_cs5_muxvals[] = {1};
-static const unsigned uart0_pins[] = {63, 64};
-static const int uart0_muxvals[] = {0, 1};
-static const unsigned uart1_pins[] = {65, 66};
-static const int uart1_muxvals[] = {0, 1};
-static const unsigned uart2_pins[] = {96, 102};
-static const int uart2_muxvals[] = {2, 2};
-static const unsigned usb0_pins[] = {13, 14};
-static const int usb0_muxvals[] = {0, 1};
-static const unsigned usb1_pins[] = {15, 16};
-static const int usb1_muxvals[] = {0, 1};
-static const unsigned usb2_pins[] = {17, 18};
-static const int usb2_muxvals[] = {0, 1};
-static const unsigned usb3_pins[] = {19, 20};
-static const int usb3_muxvals[] = {0, 1};
-
-static const struct uniphier_pinctrl_group uniphier_sld3_groups[] = {
- UNIPHIER_PINCTRL_GROUP_SPL(emmc),
- UNIPHIER_PINCTRL_GROUP_SPL(emmc_dat8),
- UNIPHIER_PINCTRL_GROUP(ether_mii),
- UNIPHIER_PINCTRL_GROUP(ether_rmii),
- UNIPHIER_PINCTRL_GROUP(i2c0),
- UNIPHIER_PINCTRL_GROUP(nand),
- UNIPHIER_PINCTRL_GROUP(nand_cs1),
- UNIPHIER_PINCTRL_GROUP(sd),
- UNIPHIER_PINCTRL_GROUP(system_bus),
- UNIPHIER_PINCTRL_GROUP(system_bus_cs0),
- UNIPHIER_PINCTRL_GROUP(system_bus_cs1),
- UNIPHIER_PINCTRL_GROUP(system_bus_cs2),
- UNIPHIER_PINCTRL_GROUP(system_bus_cs3),
- UNIPHIER_PINCTRL_GROUP(system_bus_cs4),
- UNIPHIER_PINCTRL_GROUP(system_bus_cs5),
- UNIPHIER_PINCTRL_GROUP_SPL(uart0),
- UNIPHIER_PINCTRL_GROUP_SPL(uart1),
- UNIPHIER_PINCTRL_GROUP_SPL(uart2),
- UNIPHIER_PINCTRL_GROUP(usb0),
- UNIPHIER_PINCTRL_GROUP(usb1),
- UNIPHIER_PINCTRL_GROUP(usb2),
- UNIPHIER_PINCTRL_GROUP(usb3)
-};
-
-static const char * const uniphier_sld3_functions[] = {
- UNIPHIER_PINMUX_FUNCTION_SPL(emmc),
- UNIPHIER_PINMUX_FUNCTION(ether_mii),
- UNIPHIER_PINMUX_FUNCTION(ether_rmii),
- UNIPHIER_PINMUX_FUNCTION(i2c0),
- UNIPHIER_PINMUX_FUNCTION(nand),
- UNIPHIER_PINMUX_FUNCTION(sd),
- UNIPHIER_PINMUX_FUNCTION(system_bus),
- UNIPHIER_PINMUX_FUNCTION_SPL(uart0),
- UNIPHIER_PINMUX_FUNCTION_SPL(uart1),
- UNIPHIER_PINMUX_FUNCTION_SPL(uart2),
- UNIPHIER_PINMUX_FUNCTION(usb0),
- UNIPHIER_PINMUX_FUNCTION(usb1),
- UNIPHIER_PINMUX_FUNCTION(usb2),
- UNIPHIER_PINMUX_FUNCTION(usb3),
-};
-
-static struct uniphier_pinctrl_socdata uniphier_sld3_pinctrl_socdata = {
- .groups = uniphier_sld3_groups,
- .groups_count = ARRAY_SIZE(uniphier_sld3_groups),
- .functions = uniphier_sld3_functions,
- .functions_count = ARRAY_SIZE(uniphier_sld3_functions),
- .caps = UNIPHIER_PINCTRL_CAPS_MUX_4BIT,
-};
-
-static int uniphier_sld3_pinctrl_probe(struct udevice *dev)
-{
- return uniphier_pinctrl_probe(dev, &uniphier_sld3_pinctrl_socdata);
-}
-
-static const struct udevice_id uniphier_sld3_pinctrl_match[] = {
- { .compatible = "socionext,uniphier-sld3-pinctrl" },
- { /* sentinel */ }
-};
-
-U_BOOT_DRIVER(uniphier_sld3_pinctrl) = {
- .name = "uniphier-sld3-pinctrl",
- .id = UCLASS_PINCTRL,
- .of_match = of_match_ptr(uniphier_sld3_pinctrl_match),
- .probe = uniphier_sld3_pinctrl_probe,
- .priv_auto_alloc_size = sizeof(struct uniphier_pinctrl_priv),
- .ops = &uniphier_pinctrl_ops,
-};
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index 836be25507b..47969f3f281 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -18,7 +18,7 @@ config SPL_RAM
setting up RAM (e.g. SDRAM / DDR) within SPL.
config TPL_RAM
- bool "Enable RAM support in SPL"
+ bool "Enable RAM support in TPL"
depends on RAM && TPL_DM
help
The RAM subsystem adds a small amount of overhead to the image.
diff --git a/drivers/reset/reset-uniphier.c b/drivers/reset/reset-uniphier.c
index 17e971a427f..ebb2cae5eb3 100644
--- a/drivers/reset/reset-uniphier.c
+++ b/drivers/reset/reset-uniphier.c
@@ -41,46 +41,20 @@ struct uniphier_reset_data {
}
/* System reset data */
-#define UNIPHIER_SLD3_SYS_RESET_STDMAC(id) \
- UNIPHIER_RESETX((id), 0x2000, 10)
-
-#define UNIPHIER_LD11_SYS_RESET_STDMAC(id) \
- UNIPHIER_RESETX((id), 0x200c, 8)
-
-#define UNIPHIER_PRO4_SYS_RESET_GIO(id) \
- UNIPHIER_RESETX((id), 0x2000, 6)
-
-#define UNIPHIER_LD20_SYS_RESET_GIO(id) \
- UNIPHIER_RESETX((id), 0x200c, 5)
-
-#define UNIPHIER_PRO4_SYS_RESET_USB3(id, ch) \
- UNIPHIER_RESETX((id), 0x2000 + 0x4 * (ch), 17)
-
-static const struct uniphier_reset_data uniphier_sld3_sys_reset_data[] = {
- UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* Ether, HSC, MIO */
- UNIPHIER_RESET_END,
-};
-
static const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = {
- UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC, MIO, RLE */
- UNIPHIER_PRO4_SYS_RESET_GIO(12), /* Ether, SATA, USB3 */
- UNIPHIER_PRO4_SYS_RESET_USB3(14, 0),
- UNIPHIER_PRO4_SYS_RESET_USB3(15, 1),
- UNIPHIER_RESET_END,
-};
-
-static const struct uniphier_reset_data uniphier_pro5_sys_reset_data[] = {
- UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC */
- UNIPHIER_PRO4_SYS_RESET_GIO(12), /* PCIe, USB3 */
- UNIPHIER_PRO4_SYS_RESET_USB3(14, 0),
- UNIPHIER_PRO4_SYS_RESET_USB3(15, 1),
+ UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
+ UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC */
+ UNIPHIER_RESETX(12, 0x2000, 6), /* GIO */
+ UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */
+ UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */
UNIPHIER_RESET_END,
};
static const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = {
- UNIPHIER_SLD3_SYS_RESET_STDMAC(8), /* HSC, RLE */
- UNIPHIER_PRO4_SYS_RESET_USB3(14, 0),
- UNIPHIER_PRO4_SYS_RESET_USB3(15, 1),
+ UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
+ UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC */
+ UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */
+ UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */
UNIPHIER_RESETX(16, 0x2014, 4), /* USB30-PHY0 */
UNIPHIER_RESETX(17, 0x2014, 0), /* USB30-PHY1 */
UNIPHIER_RESETX(18, 0x2014, 2), /* USB30-PHY2 */
@@ -91,14 +65,11 @@ static const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = {
UNIPHIER_RESET_END,
};
-static const struct uniphier_reset_data uniphier_ld11_sys_reset_data[] = {
- UNIPHIER_LD11_SYS_RESET_STDMAC(8), /* HSC, MIO */
- UNIPHIER_RESET_END,
-};
-
static const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = {
- UNIPHIER_LD11_SYS_RESET_STDMAC(8), /* HSC */
- UNIPHIER_LD20_SYS_RESET_GIO(12), /* PCIe, USB3 */
+ UNIPHIER_RESETX(2, 0x200c, 0), /* NAND */
+ UNIPHIER_RESETX(4, 0x200c, 2), /* eMMC */
+ UNIPHIER_RESETX(8, 0x200c, 8), /* STDMAC */
+ UNIPHIER_RESETX(12, 0x200c, 5), /* GIO */
UNIPHIER_RESETX(16, 0x200c, 12), /* USB30-PHY0 */
UNIPHIER_RESETX(17, 0x200c, 13), /* USB30-PHY1 */
UNIPHIER_RESETX(18, 0x200c, 14), /* USB30-PHY2 */
@@ -270,12 +241,8 @@ static int uniphier_reset_probe(struct udevice *dev)
static const struct udevice_id uniphier_reset_match[] = {
/* System reset */
{
- .compatible = "socionext,uniphier-sld3-reset",
- .data = (ulong)uniphier_sld3_sys_reset_data,
- },
- {
.compatible = "socionext,uniphier-ld4-reset",
- .data = (ulong)uniphier_sld3_sys_reset_data,
+ .data = (ulong)uniphier_pro4_sys_reset_data,
},
{
.compatible = "socionext,uniphier-pro4-reset",
@@ -283,11 +250,11 @@ static const struct udevice_id uniphier_reset_match[] = {
},
{
.compatible = "socionext,uniphier-sld8-reset",
- .data = (ulong)uniphier_sld3_sys_reset_data,
+ .data = (ulong)uniphier_pro4_sys_reset_data,
},
{
.compatible = "socionext,uniphier-pro5-reset",
- .data = (ulong)uniphier_pro5_sys_reset_data,
+ .data = (ulong)uniphier_pro4_sys_reset_data,
},
{
.compatible = "socionext,uniphier-pxs2-reset",
@@ -295,7 +262,7 @@ static const struct udevice_id uniphier_reset_match[] = {
},
{
.compatible = "socionext,uniphier-ld11-reset",
- .data = (ulong)uniphier_ld11_sys_reset_data,
+ .data = (ulong)uniphier_ld20_sys_reset_data,
},
{
.compatible = "socionext,uniphier-ld20-reset",
@@ -303,10 +270,6 @@ static const struct udevice_id uniphier_reset_match[] = {
},
/* Media I/O reset */
{
- .compatible = "socionext,uniphier-sld3-mio-clock",
- .data = (ulong)uniphier_mio_reset_data,
- },
- {
.compatible = "socionext,uniphier-ld4-mio-reset",
.data = (ulong)uniphier_mio_reset_data,
},
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 13f122350b2..6305bbf01cd 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -44,6 +44,14 @@ config ALTERA_TIMER
Select this to enable a timer for Altera devices. Please find
details on the "Embedded Peripherals IP User Guide" of Altera.
+config ATMEL_PIT_TIMER
+ bool "Atmel periodic interval timer support"
+ depends on TIMER
+ help
+ Select this to enable a periodic interval timer for Atmel devices,
+ it is designed to offer maximum accuracy and efficient management,
+ even for systems with long response time.
+
config SANDBOX_TIMER
bool "Sandbox timer support"
depends on SANDBOX && TIMER
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index fa7ce7c8358..69e8961a7ba 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -15,3 +15,4 @@ obj-$(CONFIG_ARC_TIMER) += arc_timer.o
obj-$(CONFIG_AG101P_TIMER) += ag101p_timer.o
obj-$(CONFIG_AE3XX_TIMER) += ae3xx_timer.o
obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o
+obj-$(CONFIG_ATMEL_PIT_TIMER) += atmel_pit_timer.o
diff --git a/drivers/timer/atmel_pit_timer.c b/drivers/timer/atmel_pit_timer.c
new file mode 100644
index 00000000000..999717b91ff
--- /dev/null
+++ b/drivers/timer/atmel_pit_timer.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (C) 2017 Microchip Corporation
+ * Wenyou.Yang <wenyou.yang@microchip.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <timer.h>
+#include <asm/io.h>
+
+#define AT91_PIT_VALUE 0xfffff
+#define AT91_PIT_PITEN BIT(24) /* Timer Enabled */
+
+struct atmel_pit_regs {
+ u32 mode;
+ u32 status;
+ u32 value;
+ u32 value_image;
+};
+
+struct atmel_pit_platdata {
+ struct atmel_pit_regs *regs;
+};
+
+static int atmel_pit_get_count(struct udevice *dev, u64 *count)
+{
+ struct atmel_pit_platdata *plat = dev_get_platdata(dev);
+ struct atmel_pit_regs *const regs = plat->regs;
+ u32 val = readl(&regs->value_image);
+
+ *count = timer_conv_64(val);
+
+ return 0;
+}
+
+static int atmel_pit_probe(struct udevice *dev)
+{
+ struct atmel_pit_platdata *plat = dev_get_platdata(dev);
+ struct atmel_pit_regs *const regs = plat->regs;
+ struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct clk clk;
+ ulong clk_rate;
+ int ret;
+
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret)
+ return -EINVAL;
+
+ clk_rate = clk_get_rate(&clk);
+ if (!clk_rate)
+ return -EINVAL;
+
+ uc_priv->clock_rate = clk_rate / 16;
+
+ writel(AT91_PIT_VALUE | AT91_PIT_PITEN, &regs->mode);
+
+ return 0;
+}
+
+static int atmel_pit_ofdata_to_platdata(struct udevice *dev)
+{
+ struct atmel_pit_platdata *plat = dev_get_platdata(dev);
+
+ plat->regs = (struct atmel_pit_regs *)devfdt_get_addr_ptr(dev);
+
+ return 0;
+}
+
+static const struct timer_ops atmel_pit_ops = {
+ .get_count = atmel_pit_get_count,
+};
+
+static const struct udevice_id atmel_pit_ids[] = {
+ { .compatible = "atmel,at91sam9260-pit" },
+ { }
+};
+
+U_BOOT_DRIVER(atmel_pit) = {
+ .name = "atmel_pit",
+ .id = UCLASS_TIMER,
+ .of_match = atmel_pit_ids,
+ .ofdata_to_platdata = atmel_pit_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct atmel_pit_platdata),
+ .probe = atmel_pit_probe,
+ .ops = &atmel_pit_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c
index d05b74b2d2a..f3382a965be 100644
--- a/drivers/usb/gadget/f_fastboot.c
+++ b/drivers/usb/gadget/f_fastboot.c
@@ -561,7 +561,7 @@ static void do_bootm_on_complete(struct usb_ep *ep, struct usb_request *req)
puts("Booting kernel..\n");
- sprintf(boot_addr_start, "0x%lx", load_addr);
+ sprintf(boot_addr_start, "0x%lx", (long)CONFIG_FASTBOOT_BUF_ADDR);
do_bootm(NULL, 0, 2, bootm_args);
/* This only happens if image is somehow faulty so we start over */
@@ -718,7 +718,7 @@ static void rx_handler_command(struct usb_ep *ep, struct usb_request *req)
}
if (!func_cb) {
- error("unknown command: %s", cmdbuf);
+ error("unknown command: %.*s", req->actual, cmdbuf);
fastboot_tx_write_str("FAILunknown command");
} else {
if (req->actual < req->length) {
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 67ad72b4a2c..eb035a476be 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -142,6 +142,12 @@ config USB_EHCI_MSM
This driver supports combination of Chipidea USB controller
and Synapsys USB PHY in host mode only.
+config USB_EHCI_PCI
+ bool "Support for PCI-based EHCI USB controller"
+ default y if X86
+ help
+ Enables support for the PCI-based EHCI controller.
+
config USB_EHCI_RCAR_GEN3
bool "Support for Renesas RCar M3/H3 EHCI USB controller"
depends on RCAR_GEN3
generated by cgit v1.2.3 (git 2.0.4) at 2024-09-06 02:15:15 +0000