diff options
Diffstat (limited to 'drivers')
31 files changed, 839 insertions, 184 deletions
diff --git a/drivers/clk/renesas/clk-rcar-gen2.c b/drivers/clk/renesas/clk-rcar-gen2.c index 13111b341a..bfd7620dae 100644 --- a/drivers/clk/renesas/clk-rcar-gen2.c +++ b/drivers/clk/renesas/clk-rcar-gen2.c @@ -291,7 +291,8 @@ int gen2_clk_probe(struct udevice *dev) if (ret < 0) return ret; - rst_base = fdtdec_get_addr(gd->fdt_blob, ret, "reg"); + rst_base = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob, ret, "reg", + 0, NULL, false); if (rst_base == FDT_ADDR_T_NONE) return -EINVAL; diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 865b80cc0f..1f62376595 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -994,6 +994,13 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) case DCLK_VOP1: ret = rk3399_vop_set_clk(priv->cru, clk->id, rate); break; + case ACLK_VOP1: + case HCLK_VOP1: + /** + * assigned-clocks handling won't require for vopl, so + * return 0 to satisfy clk_set_defaults during device probe. + */ + return 0; case SCLK_DDRCLK: ret = rk3399_ddr_set_clk(priv->cru, rate); break; diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index 2a2aa2f4f1..c37642569d 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -51,7 +51,7 @@ static int ipi_req(const u32 *req, size_t req_len, u32 *res, size_t res_maxlen) static int send_req(const u32 *req, size_t req_len, u32 *res, size_t res_maxlen) { - if (IS_ENABLED(CONFIG_SPL_BUILD)) + if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) return ipi_req(req, req_len, res, res_maxlen); return xilinx_pm_request(req[0], 0, 0, 0, 0, res); diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index f751a8b9ea..2081520f42 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -423,6 +423,14 @@ config MPC8XXX_GPIO value setting, the open-drain feature, which can configure individual GPIOs to work as open-drain outputs, is supported. +config MPC83XX_SPISEL_BOOT + bool "Freescale MPC83XX SPISEL_BOOT driver" + depends on DM_GPIO && ARCH_MPC830X + help + GPIO driver to set/clear dedicated SPISEL_BOOT output on MPC83XX. + + This pin is typically used as spi chip select to a spi nor flash. + config MT7621_GPIO bool "MediaTek MT7621 GPIO driver" depends on DM_GPIO && SOC_MT7628 diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 9dd5a58389..7638259007 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -40,6 +40,7 @@ obj-$(CONFIG_DM644X_GPIO) += da8xx_gpio.o obj-$(CONFIG_ALTERA_PIO) += altera_pio.o obj-$(CONFIG_MPC83XX_GPIO) += mpc83xx_gpio.o obj-$(CONFIG_MPC8XXX_GPIO) += mpc8xxx_gpio.o +obj-$(CONFIG_MPC83XX_SPISEL_BOOT) += mpc83xx_spisel_boot.o obj-$(CONFIG_SH_GPIO_PFC) += sh_pfc.o obj-$(CONFIG_OMAP_GPIO) += omap_gpio.o obj-$(CONFIG_DB8500_GPIO) += db8500_gpio.o diff --git a/drivers/gpio/mpc83xx_spisel_boot.c b/drivers/gpio/mpc83xx_spisel_boot.c new file mode 100644 index 0000000000..c7b08404d9 --- /dev/null +++ b/drivers/gpio/mpc83xx_spisel_boot.c @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 DEIF A/S + * + * GPIO driver to set/clear SPISEL_BOOT pin on mpc83xx. + */ + +#include <common.h> +#include <dm.h> +#include <mapmem.h> +#include <asm/gpio.h> + +struct mpc83xx_spisel_boot { + u32 __iomem *spi_cs; + ulong addr; + uint gpio_count; + ulong type; +}; + +static u32 gpio_mask(uint gpio) +{ + return (1U << (31 - (gpio))); +} + +static int mpc83xx_spisel_boot_direction_input(struct udevice *dev, uint gpio) +{ + return -EINVAL; +} + +static int mpc83xx_spisel_boot_set_value(struct udevice *dev, uint gpio, int value) +{ + struct mpc83xx_spisel_boot *data = dev_get_priv(dev); + + debug("%s: gpio=%d, value=%u, gpio_mask=0x%08x\n", __func__, + gpio, value, gpio_mask(gpio)); + + if (value) + setbits_be32(data->spi_cs, gpio_mask(gpio)); + else + clrbits_be32(data->spi_cs, gpio_mask(gpio)); + + return 0; +} + +static int mpc83xx_spisel_boot_direction_output(struct udevice *dev, uint gpio, int value) +{ + return 0; +} + +static int mpc83xx_spisel_boot_get_value(struct udevice *dev, uint gpio) +{ + struct mpc83xx_spisel_boot *data = dev_get_priv(dev); + + return !!(in_be32(data->spi_cs) & gpio_mask(gpio)); +} + +static int mpc83xx_spisel_boot_get_function(struct udevice *dev, uint gpio) +{ + return GPIOF_OUTPUT; +} + +#if CONFIG_IS_ENABLED(OF_CONTROL) +static int mpc83xx_spisel_boot_ofdata_to_platdata(struct udevice *dev) +{ + struct mpc8xxx_gpio_plat *plat = dev_get_platdata(dev); + fdt_addr_t addr; + u32 reg[2]; + + dev_read_u32_array(dev, "reg", reg, 2); + addr = dev_translate_address(dev, reg); + + plat->addr = addr; + plat->size = reg[1]; + plat->ngpios = dev_read_u32_default(dev, "ngpios", 1); + + return 0; +} +#endif + +static int mpc83xx_spisel_boot_platdata_to_priv(struct udevice *dev) +{ + struct mpc83xx_spisel_boot *priv = dev_get_priv(dev); + struct mpc8xxx_gpio_plat *plat = dev_get_platdata(dev); + unsigned long size = plat->size; + ulong driver_data = dev_get_driver_data(dev); + + if (size == 0) + size = 0x04; + + priv->addr = plat->addr; + priv->spi_cs = map_sysmem(plat->addr, size); + + if (!priv->spi_cs) + return -ENOMEM; + + priv->gpio_count = plat->ngpios; + + priv->type = driver_data; + + return 0; +} + +static int mpc83xx_spisel_boot_probe(struct udevice *dev) +{ + struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); + struct mpc83xx_spisel_boot *data = dev_get_priv(dev); + char name[32], *str; + + mpc83xx_spisel_boot_platdata_to_priv(dev); + + snprintf(name, sizeof(name), "MPC@%lx_", data->addr); + str = strdup(name); + + if (!str) + return -ENOMEM; + + uc_priv->bank_name = str; + uc_priv->gpio_count = data->gpio_count; + + return 0; +} + +static const struct dm_gpio_ops mpc83xx_spisel_boot_ops = { + .direction_input = mpc83xx_spisel_boot_direction_input, + .direction_output = mpc83xx_spisel_boot_direction_output, + .get_value = mpc83xx_spisel_boot_get_value, + .set_value = mpc83xx_spisel_boot_set_value, + .get_function = mpc83xx_spisel_boot_get_function, +}; + +static const struct udevice_id mpc83xx_spisel_boot_ids[] = { + { .compatible = "fsl,mpc8309-spisel-boot" }, + { .compatible = "fsl,mpc83xx-spisel-boot" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(spisel_boot_mpc83xx) = { + .name = "spisel_boot_mpc83xx", + .id = UCLASS_GPIO, + .ops = &mpc83xx_spisel_boot_ops, +#if CONFIG_IS_ENABLED(OF_CONTROL) + .ofdata_to_platdata = mpc83xx_spisel_boot_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct mpc8xxx_gpio_plat), + .of_match = mpc83xx_spisel_boot_ids, +#endif + .probe = mpc83xx_spisel_boot_probe, + .priv_auto_alloc_size = sizeof(struct mpc83xx_spisel_boot), +}; diff --git a/drivers/gpio/mpc8xxx_gpio.c b/drivers/gpio/mpc8xxx_gpio.c index c273c2c8a4..4b385b8b39 100644 --- a/drivers/gpio/mpc8xxx_gpio.c +++ b/drivers/gpio/mpc8xxx_gpio.c @@ -57,27 +57,6 @@ static inline u32 mpc8xxx_gpio_get_dir(struct ccsr_gpio *base, u32 mask) return in_be32(&base->gpdir) & mask; } -static inline void mpc8xxx_gpio_set_in(struct ccsr_gpio *base, u32 gpios) -{ - clrbits_be32(&base->gpdat, gpios); - /* GPDIR register 0 -> input */ - clrbits_be32(&base->gpdir, gpios); -} - -static inline void mpc8xxx_gpio_set_low(struct ccsr_gpio *base, u32 gpios) -{ - clrbits_be32(&base->gpdat, gpios); - /* GPDIR register 1 -> output */ - setbits_be32(&base->gpdir, gpios); -} - -static inline void mpc8xxx_gpio_set_high(struct ccsr_gpio *base, u32 gpios) -{ - setbits_be32(&base->gpdat, gpios); - /* GPDIR register 1 -> output */ - setbits_be32(&base->gpdir, gpios); -} - static inline int mpc8xxx_gpio_open_drain_val(struct ccsr_gpio *base, u32 mask) { return in_be32(&base->gpodr) & mask; @@ -100,22 +79,32 @@ static inline void mpc8xxx_gpio_open_drain_off(struct ccsr_gpio *base, static int mpc8xxx_gpio_direction_input(struct udevice *dev, uint gpio) { struct mpc8xxx_gpio_data *data = dev_get_priv(dev); + u32 mask = gpio_mask(gpio); + + /* GPDIR register 0 -> input */ + clrbits_be32(&data->base->gpdir, mask); - mpc8xxx_gpio_set_in(data->base, gpio_mask(gpio)); return 0; } static int mpc8xxx_gpio_set_value(struct udevice *dev, uint gpio, int value) { struct mpc8xxx_gpio_data *data = dev_get_priv(dev); + struct ccsr_gpio *base = data->base; + u32 mask = gpio_mask(gpio); + u32 gpdir; if (value) { - data->dat_shadow |= gpio_mask(gpio); - mpc8xxx_gpio_set_high(data->base, gpio_mask(gpio)); + data->dat_shadow |= mask; } else { - data->dat_shadow &= ~gpio_mask(gpio); - mpc8xxx_gpio_set_low(data->base, gpio_mask(gpio)); + data->dat_shadow &= ~mask; } + + gpdir = in_be32(&base->gpdir); + gpdir |= gpio_mask(gpio); + out_be32(&base->gpdat, gpdir & data->dat_shadow); + out_be32(&base->gpdir, gpdir); + return 0; } diff --git a/drivers/mmc/tegra_mmc.c b/drivers/mmc/tegra_mmc.c index f022e93552..2b041562a6 100644 --- a/drivers/mmc/tegra_mmc.c +++ b/drivers/mmc/tegra_mmc.c @@ -3,7 +3,7 @@ * (C) Copyright 2009 SAMSUNG Electronics * Minkyu Kang <mk7.kang@samsung.com> * Jaehoon Chung <jh80.chung@samsung.com> - * Portions Copyright 2011-2016 NVIDIA Corporation + * Portions Copyright 2011-2019 NVIDIA Corporation */ #include <bouncebuf.h> @@ -15,6 +15,9 @@ #include <asm/io.h> #include <asm/arch-tegra/tegra_mmc.h> #include <linux/err.h> +#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA210) +#include <asm/arch/clock.h> +#endif struct tegra_mmc_plat { struct mmc_config cfg; @@ -30,6 +33,7 @@ struct tegra_mmc_priv { struct gpio_desc wp_gpio; /* Write Protect GPIO */ unsigned int version; /* SDHCI spec. version */ unsigned int clock; /* Current clock (MHz) */ + int mmc_id; /* peripheral id */ }; static void tegra_mmc_set_power(struct tegra_mmc_priv *priv, @@ -372,6 +376,25 @@ static void tegra_mmc_change_clock(struct tegra_mmc_priv *priv, uint clock) rate = clk_set_rate(&priv->clk, clock); div = (rate + clock - 1) / clock; + +#if defined(CONFIG_TEGRA210) + if (priv->mmc_id == PERIPH_ID_SDMMC1 && clock <= 400000) { + /* clock_adjust_periph_pll_div() chooses a 'bad' clock + * on SDMMC1 T210, so skip it here and force a clock + * that's been spec'd in the table in the TRM for + * card-detect (400KHz). + */ + uint effective_rate = clock_adjust_periph_pll_div(priv->mmc_id, + CLOCK_ID_PERIPH, 24727273, NULL); + div = 62; + + debug("%s: WAR: Using SDMMC1 clock of %u, div %d to achieve %dHz card clock ...\n", + __func__, effective_rate, div, clock); + } else { + clock_adjust_periph_pll_div(priv->mmc_id, CLOCK_ID_PERIPH, + clock, &div); + } +#endif debug("div = %d\n", div); writew(0, &priv->reg->clkcon); @@ -446,16 +469,19 @@ static int tegra_mmc_set_ios(struct udevice *dev) static void tegra_mmc_pad_init(struct tegra_mmc_priv *priv) { -#if defined(CONFIG_TEGRA30) +#if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA210) u32 val; + u16 clk_con; + int timeout; + int id = priv->mmc_id; - debug("%s: sdmmc address = %08x\n", __func__, (unsigned int)priv->reg); + debug("%s: sdmmc address = %p, id = %d\n", __func__, + priv->reg, id); /* Set the pad drive strength for SDMMC1 or 3 only */ - if (priv->reg != (void *)0x78000000 && - priv->reg != (void *)0x78000400) { + if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) { debug("%s: settings are only valid for SDMMC1/SDMMC3!\n", - __func__); + __func__); return; } @@ -464,11 +490,65 @@ static void tegra_mmc_pad_init(struct tegra_mmc_priv *priv) val |= MEMCOMP_PADCTRL_VREF; writel(val, &priv->reg->sdmemcmppadctl); + /* Disable SD Clock Enable before running auto-cal as per TRM */ + clk_con = readw(&priv->reg->clkcon); + debug("%s: CLOCK_CONTROL = 0x%04X\n", __func__, clk_con); + clk_con &= ~TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE; + writew(clk_con, &priv->reg->clkcon); + val = readl(&priv->reg->autocalcfg); val &= 0xFFFF0000; - val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED; + val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET; writel(val, &priv->reg->autocalcfg); -#endif + val |= AUTO_CAL_START | AUTO_CAL_ENABLE; + writel(val, &priv->reg->autocalcfg); + debug("%s: AUTO_CAL_CFG = 0x%08X\n", __func__, val); + udelay(1); + timeout = 100; /* 10 mSec max (100*100uS) */ + do { + val = readl(&priv->reg->autocalsts); + udelay(100); + } while ((val & AUTO_CAL_ACTIVE) && --timeout); + val = readl(&priv->reg->autocalsts); + debug("%s: Final AUTO_CAL_STATUS = 0x%08X, timeout = %d\n", + __func__, val, timeout); + + /* Re-enable SD Clock Enable when auto-cal is done */ + clk_con |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE; + writew(clk_con, &priv->reg->clkcon); + clk_con = readw(&priv->reg->clkcon); + debug("%s: final CLOCK_CONTROL = 0x%04X\n", __func__, clk_con); + + if (timeout == 0) { + printf("%s: Warning: Autocal timed out!\n", __func__); + /* TBD: Set CFG2TMC_SDMMC1_PAD_CAL_DRV* regs here */ + } + +#if defined(CONFIG_TEGRA210) + u32 tap_value, trim_value; + + /* Set tap/trim values for SDMMC1/3 @ <48MHz here */ + val = readl(&priv->reg->venspictl); /* aka VENDOR_SYS_SW_CNTL */ + val &= IO_TRIM_BYPASS_MASK; + if (id == PERIPH_ID_SDMMC1) { + tap_value = 4; /* default */ + if (val) + tap_value = 3; + trim_value = 2; + } else { /* SDMMC3 */ + tap_value = 3; + trim_value = 3; + } + + val = readl(&priv->reg->venclkctl); + val &= ~TRIM_VAL_MASK; + val |= (trim_value << TRIM_VAL_SHIFT); + val &= ~TAP_VAL_MASK; + val |= (tap_value << TAP_VAL_SHIFT); + writel(val, &priv->reg->venclkctl); + debug("%s: VENDOR_CLOCK_CNTRL = 0x%08X\n", __func__, val); +#endif /* T210 */ +#endif /* T30/T210 */ } static void tegra_mmc_reset(struct tegra_mmc_priv *priv, struct mmc *mmc) @@ -514,6 +594,13 @@ static int tegra_mmc_init(struct udevice *dev) unsigned int mask; debug(" tegra_mmc_init called\n"); +#if defined(CONFIG_TEGRA210) + priv->mmc_id = clock_decode_periph_id(dev); + if (priv->mmc_id == PERIPH_ID_NONE) { + printf("%s: Missing/invalid peripheral ID\n", __func__); + return -EINVAL; + } +#endif tegra_mmc_reset(priv, mmc); #if defined(CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK) diff --git a/drivers/mtd/nand/raw/zynq_nand.c b/drivers/mtd/nand/raw/zynq_nand.c index 28db4153f5..0aea83dac0 100644 --- a/drivers/mtd/nand/raw/zynq_nand.c +++ b/drivers/mtd/nand/raw/zynq_nand.c @@ -1081,18 +1081,23 @@ static int zynq_nand_probe(struct udevice *dev) u8 set_feature[4] = {ONDIE_ECC_FEATURE_ENABLE, 0x00, 0x00, 0x00}; unsigned long ecc_cfg; int ondie_ecc_enabled = 0; - int err = -1; int is_16bit_bw; smc->reg = (struct zynq_nand_smc_regs *)dev_read_addr(dev); of_nand = dev_read_subnode(dev, "flash@e1000000"); if (!ofnode_valid(of_nand)) { printf("Failed to find nand node in dt\n"); - goto fail; + return -ENODEV; } + + if (!ofnode_is_available(of_nand)) { + debug("Nand node in dt disabled\n"); + return dm_scan_fdt_dev(dev); + } + if (ofnode_read_resource(of_nand, 0, &res)) { printf("Failed to get nand resource\n"); - goto fail; + return -ENODEV; } xnand->nand_base = (void __iomem *)res.start; @@ -1119,7 +1124,7 @@ static int zynq_nand_probe(struct udevice *dev) if (is_16bit_bw == NAND_BW_UNKNOWN) { printf("%s: Unable detect NAND based on MIO settings\n", __func__); - goto fail; + return -EINVAL; } if (is_16bit_bw == NAND_BW_16BIT) @@ -1130,13 +1135,13 @@ static int zynq_nand_probe(struct udevice *dev) /* Initialize the NAND flash interface on NAND controller */ if (zynq_nand_init_nand_flash(mtd, nand_chip->options) < 0) { printf("%s: nand flash init failed\n", __func__); - goto fail; + return -EINVAL; } /* first scan to find the device and get the page size */ if (nand_scan_ident(mtd, 1, NULL)) { printf("%s: nand_scan_ident failed\n", __func__); - goto fail; + return -EINVAL; } /* Send the command for reading device ID */ nand_chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); @@ -1261,14 +1266,12 @@ static int zynq_nand_probe(struct udevice *dev) /* Second phase scan */ if (nand_scan_tail(mtd)) { printf("%s: nand_scan_tail failed\n", __func__); - goto fail; + return -EINVAL; } if (nand_register(0, mtd)) - goto fail; + return -EINVAL; + return 0; -fail: - free(xnand); - return err; } static const struct udevice_id zynq_nand_dt_ids[] = { diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 973b6f86c9..abdf560e02 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -147,6 +147,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("mx25l6405d", 0xc22017, 0, 64 * 1024, 128, SECT_4K) }, { INFO("mx25u2033e", 0xc22532, 0, 64 * 1024, 4, SECT_4K) }, { INFO("mx25u1635e", 0xc22535, 0, 64 * 1024, 32, SECT_4K) }, + { INFO("mx25u3235f", 0xc22536, 0, 4 * 1024, 1024, SECT_4K) }, { INFO("mx25u6435f", 0xc22537, 0, 64 * 1024, 128, SECT_4K) }, { INFO("mx25l12805d", 0xc22018, 0, 64 * 1024, 256, 0) }, { INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) }, diff --git a/drivers/net/fm/ls1043.c b/drivers/net/fm/ls1043.c index cd510f2955..ba4da69423 100644 --- a/drivers/net/fm/ls1043.c +++ b/drivers/net/fm/ls1043.c @@ -65,12 +65,12 @@ phy_interface_t fman_port_enet_if(enum fm_port port) if (port == FM1_DTSEC3) if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) == FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII) { - return PHY_INTERFACE_MODE_RGMII_TXID; + return PHY_INTERFACE_MODE_RGMII_ID; } if (port == FM1_DTSEC4) if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC2) == FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII) { - return PHY_INTERFACE_MODE_RGMII_TXID; + return PHY_INTERFACE_MODE_RGMII_ID; } /* handle SGMII */ diff --git a/drivers/net/fm/ls1046.c b/drivers/net/fm/ls1046.c index 3617ad93e4..49b540bd30 100644 --- a/drivers/net/fm/ls1046.c +++ b/drivers/net/fm/ls1046.c @@ -71,12 +71,12 @@ phy_interface_t fman_port_enet_if(enum fm_port port) if (port == FM1_DTSEC3) if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) == FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII) - return PHY_INTERFACE_MODE_RGMII_TXID; + return PHY_INTERFACE_MODE_RGMII_ID; if (port == FM1_DTSEC4) if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC2) == FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII) - return PHY_INTERFACE_MODE_RGMII_TXID; + return PHY_INTERFACE_MODE_RGMII_ID; /* handle SGMII, only MAC 2/5/6/9/10 available */ switch (port) { diff --git a/drivers/net/fm/memac.c b/drivers/net/fm/memac.c index 2c499513f9..bed8f14aee 100644 --- a/drivers/net/fm/memac.c +++ b/drivers/net/fm/memac.c @@ -83,6 +83,8 @@ static void memac_set_interface_mode(struct fsl_enet_mac *mac, if_mode |= IF_MODE_GMII; break; case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: + case PHY_INTERFACE_MODE_RGMII_RXID: case PHY_INTERFACE_MODE_RGMII_TXID: if_mode |= (IF_MODE_GMII | IF_MODE_RG); break; @@ -107,6 +109,8 @@ static void memac_set_interface_mode(struct fsl_enet_mac *mac, if_mode |= IF_MODE_EN_AUTO; if (type == PHY_INTERFACE_MODE_RGMII || + type == PHY_INTERFACE_MODE_RGMII_ID || + type == PHY_INTERFACE_MODE_RGMII_RXID || type == PHY_INTERFACE_MODE_RGMII_TXID) { if_mode &= ~IF_MODE_EN_AUTO; if_mode &= ~IF_MODE_SETSP_MASK; diff --git a/drivers/net/macb.c b/drivers/net/macb.c index 631b53b093..bd588cab06 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -807,7 +807,7 @@ static int _macb_init(struct macb_device *macb, const char *name) macb->next_rx_tail = 0; #ifdef CONFIG_MACB_ZYNQ - macb_writel(macb, DMACFG, MACB_ZYNQ_GEM_DMACR_INIT); + gem_writel(macb, DMACFG, MACB_ZYNQ_GEM_DMACR_INIT); #endif macb_writel(macb, RBQP, macb->rx_ring_dma); diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 183e8e3083..f8e5d05722 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -859,6 +859,10 @@ static int sh_ether_probe(struct udevice *udev) goto err_mdio_register; #endif + ret = sh_eth_init_common(eth, pdata->enetaddr); + if (ret) + goto err_phy_config; + ret = sh_eth_phy_config(udev); if (ret) { printf(SHETHER_NAME ": phy config timeout\n"); diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 5f2f87d352..a158824fc9 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -197,6 +197,7 @@ struct zynq_gem_priv { int phyaddr; int init; struct zynq_gem_regs *iobase; + struct zynq_gem_regs *mdiobase; phy_interface_t interface; struct phy_device *phydev; ofnode phy_of_node; @@ -211,7 +212,7 @@ static int phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum, u32 op, u16 *data) { u32 mgtcr; - struct zynq_gem_regs *regs = priv->iobase; + struct zynq_gem_regs *regs = priv->mdiobase; int err; err = wait_for_bit_le32(®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK, @@ -297,7 +298,7 @@ static int zynq_phy_init(struct udevice *dev) { int ret; struct zynq_gem_priv *priv = dev_get_priv(dev); - struct zynq_gem_regs *regs = priv->iobase; + struct zynq_gem_regs *regs_mdio = priv->mdiobase; const u32 supported = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half | @@ -306,7 +307,7 @@ static int zynq_phy_init(struct udevice *dev) SUPPORTED_1000baseT_Full; /* Enable only MDIO bus */ - writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s->nwctrl); + writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s_mdio->nwctrl); priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface); @@ -335,6 +336,7 @@ static int zynq_gem_init(struct udevice *dev) unsigned long clk_rate = 0; struct zynq_gem_priv *priv = dev_get_priv(dev); struct zynq_gem_regs *regs = priv->iobase; + struct zynq_gem_regs *regs_mdio = priv->mdiobase; struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC]; struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2]; @@ -402,7 +404,7 @@ static int zynq_gem_init(struct udevice *dev) writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr); /* Setup for Network Control register, MDIO, Rx and Tx enable */ - setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK); + setbits_le32(®s_mdio->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK); /* Disable the second priority queue */ dummy_tx_bd->addr = 0; @@ -578,6 +580,7 @@ static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length) struct zynq_gem_priv *priv = dev_get_priv(dev); struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current]; struct emac_bd *first_bd; + dma_addr_t addr; if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) { priv->rx_first_buf = priv->rxbd_current; @@ -592,6 +595,17 @@ static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length) first_bd->status = 0xF0000000; } + /* Flush the cache for the packet as well */ +#if defined(CONFIG_PHYS_64BIT) + addr = (dma_addr_t)((current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK) + | ((dma_addr_t)current_bd->addr_hi << 32)); +#else + addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK; +#endif + flush_dcache_range(addr, addr + roundup(PKTSIZE_ALIGN, + ARCH_DMA_MINALIGN)); + barrier(); + if ((++priv->rxbd_current) >= RX_BUF) priv->rxbd_current = 0; @@ -731,6 +745,7 @@ static int zynq_gem_ofdata_to_platdata(struct udevice *dev) pdata->iobase = (phys_addr_t)dev_read_addr(dev); priv->iobase = (struct zynq_gem_regs *)pdata->iobase; + priv->mdiobase = priv->iobase; /* Hardcode for now */ priv->phyaddr = -1; @@ -756,8 +771,9 @@ static int zynq_gem_ofdata_to_platdata(struct udevice *dev) priv->int_pcs = dev_read_bool(dev, "is-internal-pcspma"); - printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase, - priv->phyaddr, phy_string_for_interface(priv->interface)); + printf("\nZYNQ GEM: %lx, mdio bus %lx, phyaddr %d, interface %s\n", + (ulong)priv->iobase, (ulong)priv->mdiobase, priv->phyaddr, + phy_string_for_interface(priv->interface)); return 0; } diff --git a/drivers/pci/pcie_ecam_generic.c b/drivers/pci/pcie_ecam_generic.c index c875f3a5b7..890b6a8fb6 100644 --- a/drivers/pci/pcie_ecam_generic.c +++ b/drivers/pci/pcie_ecam_generic.c @@ -19,6 +19,8 @@ */ struct generic_ecam_pcie { void *cfg_base; + pci_size_t size; + int first_busno; }; /** @@ -43,7 +45,7 @@ static int pci_generic_ecam_conf_address(const struct udevice *bus, void *addr; addr = pcie->cfg_base; - addr += PCI_BUS(bdf) << 20; + addr += (PCI_BUS(bdf) - pcie->first_busno) << 20; addr += PCI_DEV(bdf) << 15; addr += PCI_FUNC(bdf) << 12; addr += offset; @@ -52,6 +54,16 @@ static int pci_generic_ecam_conf_address(const struct udevice *bus, return 0; } +static bool pci_generic_ecam_addr_valid(const struct udevice *bus, + pci_dev_t bdf) +{ + struct generic_ecam_pcie *pcie = dev_get_priv(bus); + int num_buses = DIV_ROUND_UP(pcie->size, 1 << 16); + + return (PCI_BUS(bdf) >= pcie->first_busno && + PCI_BUS(bdf) < pcie->first_busno + num_buses); +} + /** * pci_generic_ecam_read_config() - Read from configuration space * @bus: Pointer to the PCI bus @@ -68,6 +80,11 @@ static int pci_generic_ecam_read_config(const struct udevice *bus, pci_dev_t bdf, uint offset, ulong *valuep, enum pci_size_t size) { + if (!pci_generic_ecam_addr_valid(bus, bdf)) { + *valuep = pci_get_ff(size); + return 0; + } + return pci_generic_mmap_read_config(bus, pci_generic_ecam_conf_address, bdf, offset, valuep, size); } @@ -88,6 +105,9 @@ static int pci_generic_ecam_write_config(struct udevice *bus, pci_dev_t bdf, uint offset, ulong value, enum pci_size_t size) { + if (!pci_generic_ecam_addr_valid(bus, bdf)) + return 0; + return pci_generic_mmap_write_config(bus, pci_generic_ecam_conf_address, bdf, offset, value, size); } @@ -116,9 +136,17 @@ static int pci_generic_ecam_ofdata_to_platdata(struct udevice *dev) return err; } - pcie->cfg_base = map_physmem(reg_res.start, - fdt_resource_size(®_res), - MAP_NOCACHE); + pcie->size = fdt_resource_size(®_res); + pcie->cfg_base = map_physmem(reg_res.start, pcie->size, MAP_NOCACHE); + + return 0; +} + +static int pci_generic_ecam_probe(struct udevice *dev) +{ + struct generic_ecam_pcie *pcie = dev_get_priv(dev); + + pcie->first_busno = dev->seq; return 0; } @@ -138,6 +166,7 @@ U_BOOT_DRIVER(pci_generic_ecam) = { .id = UCLASS_PCI, .of_match = pci_generic_ecam_ids, .ops = &pci_generic_ecam_ops, + .probe = pci_generic_ecam_probe, .ofdata_to_platdata = pci_generic_ecam_ofdata_to_platdata, .priv_auto_alloc_size = sizeof(struct generic_ecam_pcie), }; diff --git a/drivers/power/power_i2c.c b/drivers/power/power_i2c.c index bcddff2d7a..b30f223a5c 100644 --- a/drivers/power/power_i2c.c +++ b/drivers/power/power_i2c.c @@ -7,6 +7,7 @@ * Stefano Babic, DENX Software Engineering, sbabic@denx.de * * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * (C) Copyright 2019 NXP */ #include <common.h> @@ -21,8 +22,20 @@ int pmic_reg_write(struct pmic *p, u32 reg, u32 val) if (check_reg(p, reg)) return -EINVAL; +#if defined(CONFIG_DM_I2C) + struct udevice *dev; + int ret; + ret = i2c_get_chip_for_busnum(p->bus, pmic_i2c_addr, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + p->bus); + return -ENXIO; + } +#else /* Non DM I2C support - will be removed */ I2C_SET_BUS(p->bus); +#endif switch (pmic_i2c_tx_num) { case 3: @@ -53,7 +66,11 @@ int pmic_reg_write(struct pmic *p, u32 reg, u32 val) return -EINVAL; } +#if defined(CONFIG_DM_I2C) + return dm_i2c_write(dev, reg, buf, pmic_i2c_tx_num); +#else return i2c_write(pmic_i2c_addr, reg, 1, buf, pmic_i2c_tx_num); +#endif } int pmic_reg_read(struct pmic *p, u32 reg, u32 *val) @@ -65,9 +82,21 @@ int pmic_reg_read(struct pmic *p, u32 reg, u32 *val) if (check_reg(p, reg)) return -EINVAL; - I2C_SET_BUS(p->bus); +#if defined(CONFIG_DM_I2C) + struct udevice *dev; + ret = i2c_get_chip_for_busnum(p->bus, pmic_i2c_addr, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + p->bus); + return -ENXIO; + } + ret = dm_i2c_read(dev, reg, buf, pmic_i2c_tx_num); +#else /* Non DM I2C support - will be removed */ + I2C_SET_BUS(p->bus); ret = i2c_read(pmic_i2c_addr, reg, 1, buf, pmic_i2c_tx_num); +#endif if (ret) return ret; @@ -100,12 +129,25 @@ int pmic_reg_read(struct pmic *p, u32 reg, u32 *val) int pmic_probe(struct pmic *p) { - i2c_set_bus_num(p->bus); debug("Bus: %d PMIC:%s probed!\n", p->bus, p->name); +#if defined(CONFIG_DM_I2C) + struct udevice *dev; + int ret; + + ret = i2c_get_chip_for_busnum(p->bus, pmic_i2c_addr, + 1, &dev); + if (ret) { + printf("%s: Cannot find udev for a bus %d\n", __func__, + p->bus); + return -ENXIO; + } +#else /* Non DM I2C support - will be removed */ + i2c_set_bus_num(p->bus); if (i2c_probe(pmic_i2c_addr)) { printf("Can't find PMIC:%s\n", p->name); return -ENODEV; } +#endif return 0; } diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index c1b303ffcb..a2f1b35629 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -479,39 +479,38 @@ static int ns16550_serial_getinfo(struct udevice *dev, return 0; } -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) -static int ns1655_serial_set_base_addr(struct udevice *dev) +static int ns16550_serial_assign_base(struct ns16550_platdata *plat, ulong base) { - fdt_addr_t addr; - struct ns16550_platdata *plat; - - plat = dev_get_platdata(dev); - - addr = dev_read_addr_pci(dev); - if (addr == FDT_ADDR_T_NONE) + if (base == FDT_ADDR_T_NONE) return -EINVAL; #ifdef CONFIG_SYS_NS16550_PORT_MAPPED - plat->base = addr; + plat->base = base; #else - plat->base = (unsigned long)map_physmem(addr, 0, MAP_NOCACHE); + plat->base = (unsigned long)map_physmem(base, 0, MAP_NOCACHE); #endif return 0; } -#endif int ns16550_serial_probe(struct udevice *dev) { + struct ns16550_platdata *plat = dev->platdata; struct NS16550 *const com_port = dev_get_priv(dev); struct reset_ctl_bulk reset_bulk; + fdt_addr_t addr; int ret; -#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) - ret = ns1655_serial_set_base_addr(dev); - if (ret) - return ret; -#endif + /* + * If we are on PCI bus, either directly attached to a PCI root port, + * or via a PCI bridge, assign platdata->base before probing hardware. + */ + if (device_is_on_pci_bus(dev)) { + addr = devfdt_get_addr_pci(dev); + ret = ns16550_serial_assign_base(plat, addr); + if (ret) + return ret; + } ret = reset_get_bulk(dev, &reset_bulk); if (!ret) @@ -535,9 +534,15 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev) { struct ns16550_platdata *plat = dev->platdata; const u32 port_type = dev_get_driver_data(dev); + fdt_addr_t addr; struct clk clk; int err; + addr = dev_read_addr(dev); + err = ns16550_serial_assign_base(plat, addr); + if (err && !device_is_on_pci_bus(dev)) + return err; + plat->reg_offset = dev_read_u32_default(dev, "reg-offset", 0); plat->reg_shift = dev_read_u32_default(dev, "reg-shift", 0); plat->reg_width = dev_read_u32_default(dev, "reg-io-width", 1); diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c index e4e4c39285..0dd6cec82a 100644 --- a/drivers/serial/serial_zynq.c +++ b/drivers/serial/serial_zynq.c @@ -17,8 +17,6 @@ #include <serial.h> #include <linux/err.h> -DECLARE_GLOBAL_DATA_PTR; - #define ZYNQ_UART_SR_TXACTIVE BIT(11) /* TX active */ #define ZYNQ_UART_SR_TXFULL BIT(4) /* TX FIFO full */ #define ZYNQ_UART_SR_RXEMPTY BIT(1) /* RX FIFO empty */ @@ -45,7 +43,7 @@ struct zynq_uart_platdata { struct uart_zynq *regs; }; -/* Set up the baud rate in gd struct */ +/* Set up the baud rate */ static void _uart_zynq_serial_setbrg(struct uart_zynq *regs, unsigned long clock, unsigned long baud) { @@ -140,9 +138,12 @@ static int zynq_serial_setbrg(struct udevice *dev, int baudrate) static int zynq_serial_probe(struct udevice *dev) { struct zynq_uart_platdata *platdata = dev_get_platdata(dev); + struct uart_zynq *regs = platdata->regs; + u32 val; - /* No need to reinitialize the UART after relocation */ - if (gd->flags & GD_FLG_RELOC) + /* No need to reinitialize the UART if TX already enabled */ + val = readl(®s->control); + if (val & ZYNQ_UART_CR_TX_EN) return 0; _uart_zynq_serial_init(platdata->regs); diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c index a09bf884e8..a6c3939db5 100644 --- a/drivers/spi/atmel-quadspi.c +++ b/drivers/spi/atmel-quadspi.c @@ -146,7 +146,9 @@ struct atmel_qspi_caps { struct atmel_qspi { void __iomem *regs; void __iomem *mem; + resource_size_t mmap_size; const struct atmel_qspi_caps *caps; + struct udevice *dev; ulong bus_clk_rate; u32 mr; }; @@ -168,6 +170,81 @@ static const struct atmel_qspi_mode atmel_qspi_modes[] = { { 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD }, }; +#ifdef VERBOSE_DEBUG +static const char *atmel_qspi_reg_name(u32 offset, char *tmp, size_t sz) +{ + switch (offset) { + case QSPI_CR: + return "CR"; + case QSPI_MR: + return "MR"; + case QSPI_RD: + return "MR"; + case QSPI_TD: + return "TD"; + case QSPI_SR: + return "SR"; + case QSPI_IER: + return "IER"; + case QSPI_IDR: + return "IDR"; + case QSPI_IMR: + return "IMR"; + case QSPI_SCR: + return "SCR"; + case QSPI_IAR: + return "IAR"; + case QSPI_ICR: + return "ICR/WICR"; + case QSPI_IFR: + return "IFR"; + case QSPI_RICR: + return "RICR"; + case QSPI_SMR: + return "SMR"; + case QSPI_SKR: + return "SKR"; + case QSPI_WPMR: + return "WPMR"; + case QSPI_WPSR: + return "WPSR"; + case QSPI_VERSION: + return "VERSION"; + default: + snprintf(tmp, sz, "0x%02x", offset); + break; + } + + return tmp; +} +#endif /* VERBOSE_DEBUG */ + +static u32 atmel_qspi_read(struct atmel_qspi *aq, u32 offset) +{ + u32 value = readl(aq->regs + offset); + +#ifdef VERBOSE_DEBUG + char tmp[16]; + + dev_vdbg(aq->dev, "read 0x%08x from %s\n", value, + atmel_qspi_reg_name(offset, tmp, sizeof(tmp))); +#endif /* VERBOSE_DEBUG */ + + return value; +} + +static void atmel_qspi_write(u32 value, struct atmel_qspi *aq, u32 offset) +{ +#ifdef VERBOSE_DEBUG + char tmp[16]; + + dev_vdbg(aq->dev, "write 0x%08x into %s\n", value, + atmel_qspi_reg_name(offset, tmp, sizeof(tmp))); +#endif /* VERBOSE_DEBUG */ + + writel(value, aq->regs + offset); +} + static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op, const struct atmel_qspi_mode *mode) { @@ -288,32 +365,32 @@ static int atmel_qspi_set_cfg(struct atmel_qspi *aq, * Serial Memory Mode (SMM). */ if (aq->mr != QSPI_MR_SMM) { - writel(QSPI_MR_SMM, aq->regs + QSPI_MR); + atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR); aq->mr = QSPI_MR_SMM; } /* Clear pending interrupts */ - (void)readl(aq->regs + QSPI_SR); + (void)atmel_qspi_read(aq, QSPI_SR); if (aq->caps->has_ricr) { if (!op->addr.nbytes && op->data.dir == SPI_MEM_DATA_IN) ifr |= QSPI_IFR_APBTFRTYP_READ; /* Set QSPI Instruction Frame registers */ - writel(iar, aq->regs + QSPI_IAR); + atmel_qspi_write(iar, aq, QSPI_IAR); if (op->data.dir == SPI_MEM_DATA_IN) - writel(icr, aq->regs + QSPI_RICR); + atmel_qspi_write(icr, aq, QSPI_RICR); else - writel(icr, aq->regs + QSPI_WICR); - writel(ifr, aq->regs + QSPI_IFR); + atmel_qspi_write(icr, aq, QSPI_WICR); + atmel_qspi_write(ifr, aq, QSPI_IFR); } else { if (op->data.dir == SPI_MEM_DATA_OUT) ifr |= QSPI_IFR_SAMA5D2_WRITE_TRSFR; /* Set QSPI Instruction Frame registers */ - writel(iar, aq->regs + QSPI_IAR); - writel(icr, aq->regs + QSPI_ICR); - writel(ifr, aq->regs + QSPI_IFR); + atmel_qspi_write(iar, aq, QSPI_IAR); + atmel_qspi_write(icr, aq, QSPI_ICR); + atmel_qspi_write(ifr, aq, QSPI_IFR); } return 0; @@ -326,6 +403,14 @@ static int atmel_qspi_exec_op(struct spi_slave *slave, u32 sr, imr, offset; int err; + /* + * Check if the address exceeds the MMIO window size. An improvement + * would be to add support for regular SPI mode and fall back to it + * when the flash memories overrun the controller's memory space. + */ + if (op->addr.val + op->data.nbytes > aq->mmap_size) + return -ENOTSUPP; + err = atmel_qspi_set_cfg(aq, op, &offset); if (err) return err; @@ -333,7 +418,7 @@ static int atmel_qspi_exec_op(struct spi_slave *slave, /* Skip to the final steps if there is no data */ if (op->data.nbytes) { /* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */ - (void)readl(aq->regs + QSPI_IFR); + (void)atmel_qspi_read(aq, QSPI_IFR); /* Send/Receive data */ if (op->data.dir == SPI_MEM_DATA_IN) @@ -344,7 +429,7 @@ static int atmel_qspi_exec_op(struct spi_slave *slave, op->data.nbytes); /* Release the chip-select */ - writel(QSPI_CR_LASTXFER, aq->regs + QSPI_CR); + atmel_qspi_write(QSPI_CR_LASTXFER, aq, QSPI_CR); } /* Poll INSTruction End and Chip Select Rise flags. */ @@ -366,12 +451,12 @@ static int atmel_qspi_set_speed(struct udevice *bus, uint hz) new_value = QSPI_SCR_SCBR(scbr); mask = QSPI_SCR_SCBR_MASK; - scr = readl(aq->regs + QSPI_SCR); + scr = atmel_qspi_read(aq, QSPI_SCR); if ((scr & mask) == new_value) return 0; scr = (scr & ~mask) | new_value; - writel(scr, aq->regs + QSPI_SCR); + atmel_qspi_write(scr, aq, QSPI_SCR); return 0; } @@ -388,12 +473,12 @@ static int atmel_qspi_set_mode(struct udevice *bus, uint mode) mask = QSPI_SCR_CPOL | QSPI_SCR_CPHA; - scr = readl(aq->regs + QSPI_SCR); + scr = atmel_qspi_read(aq, QSPI_SCR); if ((scr & mask) == new_value) return 0; scr = (scr & ~mask) | new_value; - writel(scr, aq->regs + QSPI_SCR); + atmel_qspi_write(scr, aq, QSPI_SCR); return 0; } @@ -446,14 +531,14 @@ free_pclk: static void atmel_qspi_init(struct atmel_qspi *aq) { /* Reset the QSPI controller */ - writel(QSPI_CR_SWRST, aq->regs + QSPI_CR); + atmel_qspi_write(QSPI_CR_SWRST, aq, QSPI_CR); /* Set the QSPI controller by default in Serial Memory Mode */ - writel(QSPI_MR_SMM, aq->regs + QSPI_MR); + atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR); aq->mr = QSPI_MR_SMM; /* Enable the QSPI controller */ - writel(QSPI_CR_QSPIEN, aq->regs + QSPI_CR); + atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR); } static int atmel_qspi_probe(struct udevice *dev) @@ -490,10 +575,14 @@ static int atmel_qspi_probe(struct udevice *dev) if (IS_ERR(aq->mem)) return PTR_ERR(aq->mem); + aq->mmap_size = resource_size(&res); + ret = atmel_qspi_enable_clk(dev); if (ret) return ret; + aq->dev = dev; + atmel_qspi_init(aq); return 0; diff --git a/drivers/spi/mpc8xxx_spi.c b/drivers/spi/mpc8xxx_spi.c index 1c7bf10f91..1bde31ad34 100644 --- a/drivers/spi/mpc8xxx_spi.c +++ b/drivers/spi/mpc8xxx_spi.c @@ -5,6 +5,7 @@ */ #include <common.h> +#include <clk.h> #include <dm.h> #include <errno.h> #include <malloc.h> @@ -27,6 +28,8 @@ enum { SPI_MODE_EN = BIT(31 - 7), /* Enable interface */ SPI_MODE_LEN_MASK = 0xf00000, + SPI_MODE_LEN_SHIFT = 20, + SPI_MODE_PM_SHIFT = 16, SPI_MODE_PM_MASK = 0xf0000, SPI_COM_LST = BIT(31 - 9), @@ -35,46 +38,38 @@ enum { struct mpc8xxx_priv { spi8xxx_t *spi; struct gpio_desc gpios[16]; - int max_cs; + int cs_count; + ulong clk_rate; }; -static inline u32 to_prescale_mod(u32 val) -{ - return (min(val, (u32)15) << 16); -} - -static void set_char_len(spi8xxx_t *spi, u32 val) -{ - clrsetbits_be32(&spi->mode, SPI_MODE_LEN_MASK, (val << 20)); -} - #define SPI_TIMEOUT 1000 -static int __spi_set_speed(spi8xxx_t *spi, uint speed) -{ - /* TODO(mario.six@gdsys.cc): This only ever sets one fixed speed */ - - /* Use SYSCLK / 8 (16.67MHz typ.) */ - clrsetbits_be32(&spi->mode, SPI_MODE_PM_MASK, to_prescale_mod(1)); - - return 0; -} - static int mpc8xxx_spi_ofdata_to_platdata(struct udevice *dev) { struct mpc8xxx_priv *priv = dev_get_priv(dev); + struct clk clk; int ret; priv->spi = (spi8xxx_t *)dev_read_addr(dev); - /* TODO(mario.six@gdsys.cc): Read clock and save the value */ - ret = gpio_request_list_by_name(dev, "gpios", priv->gpios, ARRAY_SIZE(priv->gpios), GPIOD_IS_OUT | GPIOD_ACTIVE_LOW); if (ret < 0) return -EINVAL; - priv->max_cs = ret; + priv->cs_count = ret; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret) { + dev_err(dev, "%s: clock not defined\n", __func__); + return ret; + } + + priv->clk_rate = clk_get_rate(&clk); + if (!priv->clk_rate) { + dev_err(dev, "%s: failed to get clock rate\n", __func__); + return -EINVAL; + } return 0; } @@ -82,14 +77,18 @@ static int mpc8xxx_spi_ofdata_to_platdata(struct udevice *dev) static int mpc8xxx_spi_probe(struct udevice *dev) { struct mpc8xxx_priv *priv = dev_get_priv(dev); + spi8xxx_t *spi = priv->spi; /* * SPI pins on the MPC83xx are not muxed, so all we do is initialize * some registers */ - out_be32(&priv->spi->mode, SPI_MODE_REV | SPI_MODE_MS | SPI_MODE_EN); + out_be32(&priv->spi->mode, SPI_MODE_REV | SPI_MODE_MS); + + /* set len to 8 bits */ + setbits_be32(&spi->mode, (8 - 1) << SPI_MODE_LEN_SHIFT); - __spi_set_speed(priv->spi, 16666667); + setbits_be32(&spi->mode, SPI_MODE_EN); /* Clear all SPI events */ setbits_be32(&priv->spi->event, 0xffffffff); @@ -126,45 +125,35 @@ static int mpc8xxx_spi_xfer(struct udevice *dev, uint bitlen, struct mpc8xxx_priv *priv = dev_get_priv(bus); spi8xxx_t *spi = priv->spi; struct dm_spi_slave_platdata *platdata = dev_get_parent_platdata(dev); - u32 tmpdin = 0; - int num_blks = DIV_ROUND_UP(bitlen, 32); + u32 tmpdin = 0, tmpdout = 0, n; + const u8 *cout = dout; + u8 *cin = din; debug("%s: slave %s:%u dout %08X din %08X bitlen %u\n", __func__, - bus->name, platdata->cs, *(uint *)dout, *(uint *)din, bitlen); + bus->name, platdata->cs, (uint)dout, (uint)din, bitlen); + if (platdata->cs >= priv->cs_count) { + dev_err(dev, "chip select index %d too large (cs_count=%d)\n", + platdata->cs, priv->cs_count); + return -EINVAL; + } + if (bitlen % 8) { + printf("*** spi_xfer: bitlen must be multiple of 8\n"); + return -ENOTSUPP; + } if (flags & SPI_XFER_BEGIN) mpc8xxx_spi_cs_activate(dev); /* Clear all SPI events */ setbits_be32(&spi->event, 0xffffffff); + n = bitlen / 8; - /* Handle data in 32-bit chunks */ - while (num_blks--) { - u32 tmpdout = 0; - uchar xfer_bitlen = (bitlen >= 32 ? 32 : bitlen); + /* Handle data in 8-bit chunks */ + while (n--) { ulong start; - clrbits_be32(&spi->mode, SPI_MODE_EN); - - /* Set up length for this transfer */ - - if (bitlen <= 4) /* 4 bits or less */ - set_char_len(spi, 3); - else if (bitlen <= 16) /* at most 16 bits */ - set_char_len(spi, bitlen - 1); - else /* more than 16 bits -> full 32 bit transfer */ - set_char_len(spi, 0); - - setbits_be32(&spi->mode, SPI_MODE_EN); - - /* Shift data so it's msb-justified */ - tmpdout = *(u32 *)dout >> (32 - xfer_bitlen); - - if (bitlen > 32) { - /* Set up the next iteration if sending > 32 bits */ - bitlen -= 32; - dout += 4; - } + if (cout) + tmpdout = *cout++; /* Write the data out */ out_be32(&spi->tx, tmpdout); @@ -188,11 +177,8 @@ static int mpc8xxx_spi_xfer(struct udevice *dev, uint bitlen, tmpdin = in_be32(&spi->rx); setbits_be32(&spi->event, SPI_EV_NE); - *(u32 *)din = (tmpdin << (32 - xfer_bitlen)); - if (xfer_bitlen == 32) { - /* Advance output buffer by 32 bits */ - din += 4; - } + if (cin) + *cin++ = tmpdin; /* * Only bail when we've had both NE and NF events. @@ -224,8 +210,43 @@ static int mpc8xxx_spi_xfer(struct udevice *dev, uint bitlen, static int mpc8xxx_spi_set_speed(struct udevice *dev, uint speed) { struct mpc8xxx_priv *priv = dev_get_priv(dev); + spi8xxx_t *spi = priv->spi; + u32 bits, mask, div16, pm; + u32 mode; + ulong clk; + + clk = priv->clk_rate; + if (clk / 64 > speed) { + div16 = SPI_MODE_DIV16; + clk /= 16; + } else { + div16 = 0; + } + pm = (clk - 1)/(4*speed) + 1; + if (pm > 16) { + dev_err(dev, "requested speed %u too small\n", speed); + return -EINVAL; + } + pm--; + + bits = div16 | (pm << SPI_MODE_PM_SHIFT); + mask = SPI_MODE_DIV16 | SPI_MODE_PM_MASK; + mode = in_be32(&spi->mode); + if ((mode & mask) != bits) { + /* Must clear mode[EN] while changing speed. */ + mode &= ~(mask | SPI_MODE_EN); + out_be32(&spi->mode, mode); + mode |= bits; + out_be32(&spi->mode, mode); + mode |= SPI_MODE_EN; + out_be32(&spi->mode, mode); + } - return __spi_set_speed(priv->spi, speed); + debug("requested speed %u, set speed to %lu/(%s4*%u) == %lu\n", + speed, priv->clk_rate, div16 ? "16*" : "", pm + 1, + clk/(4*(pm + 1))); + + return 0; } static int mpc8xxx_spi_set_mode(struct udevice *dev, uint mode) diff --git a/drivers/spi/tegra210_qspi.c b/drivers/spi/tegra210_qspi.c index d82ecaa61f..6e540e97df 100644 --- a/drivers/spi/tegra210_qspi.c +++ b/drivers/spi/tegra210_qspi.c @@ -2,7 +2,8 @@ /* * NVIDIA Tegra210 QSPI controller driver * - * (C) Copyright 2015 NVIDIA Corporation <www.nvidia.com> + * (C) Copyright 2015-2020 NVIDIA Corporation <www.nvidia.com> + * */ #include <common.h> @@ -41,10 +42,10 @@ DECLARE_GLOBAL_DATA_PTR; #define QSPI_CMD1_BITLEN_SHIFT 0 /* COMMAND2 */ -#define QSPI_CMD2_TX_CLK_TAP_DELAY BIT(6) -#define QSPI_CMD2_TX_CLK_TAP_DELAY_MASK GENMASK(11,6) -#define QSPI_CMD2_RX_CLK_TAP_DELAY BIT(0) -#define QSPI_CMD2_RX_CLK_TAP_DELAY_MASK GENMASK(5,0) +#define QSPI_CMD2_TX_CLK_TAP_DELAY_SHIFT 10 +#define QSPI_CMD2_TX_CLK_TAP_DELAY_MASK GENMASK(14,10) +#define QSPI_CMD2_RX_CLK_TAP_DELAY_SHIFT 0 +#define QSPI_CMD2_RX_CLK_TAP_DELAY_MASK GENMASK(7,0) /* TRANSFER STATUS */ #define QSPI_XFER_STS_RDY BIT(30) @@ -96,10 +97,8 @@ struct tegra210_qspi_priv { static int tegra210_qspi_ofdata_to_platdata(struct udevice *bus) { struct tegra_spi_platdata *plat = bus->platdata; - const void *blob = gd->fdt_blob; - int node = dev_of_offset(bus); - plat->base = devfdt_get_addr(bus); + plat->base = dev_read_addr(bus); plat->periph_id = clock_decode_periph_id(bus); if (plat->periph_id == PERIPH_ID_NONE) { @@ -109,10 +108,11 @@ static int tegra210_qspi_ofdata_to_platdata(struct udevice *bus) } /* Use 500KHz as a suitable default */ - plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", - 500000); - plat->deactivate_delay_us = fdtdec_get_int(blob, node, - "spi-deactivate-delay", 0); + plat->frequency = dev_read_u32_default(bus, "spi-max-frequency", + 500000); + plat->deactivate_delay_us = dev_read_u32_default(bus, + "spi-deactivate-delay", + 0); debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n", __func__, plat->base, plat->periph_id, plat->frequency, plat->deactivate_delay_us); @@ -126,25 +126,32 @@ static int tegra210_qspi_probe(struct udevice *bus) struct tegra210_qspi_priv *priv = dev_get_priv(bus); priv->regs = (struct qspi_regs *)plat->base; + struct qspi_regs *regs = priv->regs; priv->last_transaction_us = timer_get_us(); priv->freq = plat->frequency; priv->periph_id = plat->periph_id; + debug("%s: Freq = %u, id = %d\n", __func__, priv->freq, + priv->periph_id); /* Change SPI clock to correct frequency, PLLP_OUT0 source */ clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq); + /* Set tap delays here, clock change above resets QSPI controller */ + u32 reg = (0x09 << QSPI_CMD2_TX_CLK_TAP_DELAY_SHIFT) | + (0x0C << QSPI_CMD2_RX_CLK_TAP_DELAY_SHIFT); + writel(reg, ®s->command2); + debug("%s: COMMAND2 = %08x\n", __func__, readl(®s->command2)); + return 0; } -static int tegra210_qspi_claim_bus(struct udevice *bus) +static int tegra210_qspi_claim_bus(struct udevice *dev) { + struct udevice *bus = dev->parent; struct tegra210_qspi_priv *priv = dev_get_priv(bus); struct qspi_regs *regs = priv->regs; - /* Change SPI clock to correct frequency, PLLP_OUT0 source */ - clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq); - debug("%s: FIFO STATUS = %08x\n", __func__, readl(®s->fifo_status)); /* Set master mode and sw controlled CS */ diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index bea4a92b61..928a89133c 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -108,6 +108,7 @@ config USB_KEYBOARD_FN_KEYS choice prompt "USB keyboard polling" + default SYS_USB_EVENT_POLL_VIA_INT_QUEUE if ARCH_SUNXI default SYS_USB_EVENT_POLL ---help--- Enable a polling mechanism for USB keyboard. diff --git a/drivers/video/rockchip/Kconfig b/drivers/video/rockchip/Kconfig index 10182d0b66..cfd774ead6 100644 --- a/drivers/video/rockchip/Kconfig +++ b/drivers/video/rockchip/Kconfig @@ -22,6 +22,7 @@ menuconfig VIDEO_ROCKCHIP config VIDEO_ROCKCHIP_MAX_XRES int "Maximum horizontal resolution (for memory allocation purposes)" depends on VIDEO_ROCKCHIP + default 3480 if ROCKCHIP_RK3399 && DISPLAY_ROCKCHIP_HDMI default 1920 help The maximum horizontal resolution to support for the framebuffer. @@ -31,6 +32,7 @@ config VIDEO_ROCKCHIP_MAX_XRES config VIDEO_ROCKCHIP_MAX_YRES int "Maximum vertical resolution (for memory allocation purposes)" depends on VIDEO_ROCKCHIP + default 2160 if ROCKCHIP_RK3399 && DISPLAY_ROCKCHIP_HDMI default 1080 help The maximum vertical resolution to support for the framebuffer. diff --git a/drivers/video/rockchip/rk3399_vop.c b/drivers/video/rockchip/rk3399_vop.c index 81c122d7a9..1d5b3931a6 100644 --- a/drivers/video/rockchip/rk3399_vop.c +++ b/drivers/video/rockchip/rk3399_vop.c @@ -45,8 +45,6 @@ static void rk3399_set_pin_polarity(struct udevice *dev, V_RK3399_DSP_MIPI_POL(polarity)); break; - case VOP_MODE_LVDS: - /* The RK3399 has neither parallel RGB nor LVDS output. */ default: debug("%s: unsupported output mode %x\n", __func__, mode); } diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c index e91d4dfa7f..e1bd656bee 100644 --- a/drivers/video/rockchip/rk_vop.c +++ b/drivers/video/rockchip/rk_vop.c @@ -118,10 +118,12 @@ static void rkvop_enable_output(struct udevice *dev, enum vop_modes mode) V_EDP_OUT_EN(1)); break; +#if defined(CONFIG_ROCKCHIP_RK3288) case VOP_MODE_LVDS: clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN, V_RGB_OUT_EN(1)); break; +#endif case VOP_MODE_MIPI: clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN, @@ -313,7 +315,9 @@ static int rk_display_init(struct udevice *dev, ulong fbbase, ofnode ep_node) /* Set bitwidth for vop display according to vop mode */ switch (vop_id) { case VOP_MODE_EDP: +#if defined(CONFIG_ROCKCHIP_RK3288) case VOP_MODE_LVDS: +#endif l2bpp = VIDEO_BPP16; break; case VOP_MODE_HDMI: diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index cb4da2e3cf..6cafd243e0 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -185,6 +185,15 @@ config XILINX_TB_WATCHDOG Select this to enable Xilinx Axi watchdog timer, which can be found on some Xilinx Microblaze Platforms. +config WDT_XILINX + bool "Xilinx window watchdog timer support" + depends on WDT && ARCH_VERSAL + select REGMAP + imply WATCHDOG + help + Select this to enable Xilinx window watchdog timer, which can be found on + Xilinx Versal Platforms. + config WDT_TANGIER bool "Intel Tangier watchdog timer support" depends on WDT && INTEL_MID diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 87f92a43b1..519bbd3a40 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -30,3 +30,4 @@ obj-$(CONFIG_WDT_OMAP3) += omap_wdt.o obj-$(CONFIG_WDT_SP805) += sp805_wdt.o obj-$(CONFIG_WDT_STM32MP) += stm32mp_wdt.o obj-$(CONFIG_WDT_TANGIER) += tangier_wdt.o +obj-$(CONFIG_WDT_XILINX) += xilinx_wwdt.o diff --git a/drivers/watchdog/cdns_wdt.c b/drivers/watchdog/cdns_wdt.c index 775f06a6e1..5bf02605a8 100644 --- a/drivers/watchdog/cdns_wdt.c +++ b/drivers/watchdog/cdns_wdt.c @@ -15,8 +15,6 @@ #include <linux/err.h> #include <linux/io.h> -DECLARE_GLOBAL_DATA_PTR; - struct cdns_regs { u32 zmr; /* WD Zero mode register, offset - 0x0 */ u32 ccr; /* Counter Control Register offset - 0x4 */ diff --git a/drivers/watchdog/xilinx_wwdt.c b/drivers/watchdog/xilinx_wwdt.c new file mode 100644 index 0000000000..d8a585a483 --- /dev/null +++ b/drivers/watchdog/xilinx_wwdt.c @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx window watchdog timer driver. + * + * Author(s): Michal Simek <michal.simek@xilinx.com> + * Ashok Reddy Soma <ashokred@xilinx.com> + * + * Copyright (c) 2020, Xilinx Inc. + */ + +#include <clk.h> +#include <common.h> +#include <dm.h> +#include <regmap.h> +#include <wdt.h> +#include <linux/compat.h> +#include <linux/io.h> + +/* Refresh Register Masks */ +#define XWT_WWREF_GWRR_MASK BIT(0) /* Refresh and start new period */ + +/* Generic Control/Status Register Masks */ +#define XWT_WWCSR_GWEN_MASK BIT(0) /* Enable Bit */ + +/* Register offsets for the Wdt device */ +#define XWT_WWREF_OFFSET 0x1000 /* Refresh Register */ +#define XWT_WWCSR_OFFSET 0x2000 /* Control/Status Register */ +#define XWT_WWOFF_OFFSET 0x2008 /* Offset Register */ +#define XWT_WWCMP0_OFFSET 0x2010 /* Compare Value Register0 */ +#define XWT_WWCMP1_OFFSET 0x2014 /* Compare Value Register1 */ +#define XWT_WWWRST_OFFSET 0x2FD0 /* Warm Reset Register */ + +struct xlnx_wwdt_priv { + bool enable_once; + struct regmap *regs; + struct clk clk; +}; + +struct xlnx_wwdt_platdata { + bool enable_once; +}; + +static int xlnx_wwdt_reset(struct udevice *dev) +{ + struct xlnx_wwdt_priv *wdt = dev_get_priv(dev); + + regmap_write(wdt->regs, XWT_WWREF_OFFSET, XWT_WWREF_GWRR_MASK); + + return 0; +} + +static int xlnx_wwdt_stop(struct udevice *dev) +{ + u32 csr; + struct xlnx_wwdt_priv *wdt = dev_get_priv(dev); + + if (wdt->enable_once) { + dev_warn(dev, "Can't stop Xilinx watchdog.\n"); + return -EBUSY; + } + + /* Disable the generic watchdog timer */ + regmap_read(wdt->regs, XWT_WWCSR_OFFSET, &csr); + csr &= ~(XWT_WWCSR_GWEN_MASK); + regmap_write(wdt->regs, XWT_WWCSR_OFFSET, csr); + + clk_disable(&wdt->clk); + + dev_dbg(dev, "Watchdog disabled!\n"); + + return 0; +} + +static int xlnx_wwdt_start(struct udevice *dev, u64 timeout, ulong flags) +{ + int ret; + u32 csr; + u64 count; + unsigned long clock_f; + struct xlnx_wwdt_priv *wdt = dev_get_priv(dev); + + clock_f = clk_get_rate(&wdt->clk); + if (IS_ERR_VALUE(clock_f)) { + dev_err(dev, "failed to get rate\n"); + return clock_f; + } + + dev_dbg(dev, "%s: CLK %ld\n", __func__, clock_f); + + /* Calculate timeout count */ + count = timeout * clock_f; + + /* clk_enable will return -ENOSYS when it is not implemented */ + ret = clk_enable(&wdt->clk); + if (ret && ret != -ENOSYS) { + dev_err(dev, "failed to enable clock\n"); + return ret; + } + + /* + * Timeout count is half as there are two windows + * first window overflow is ignored (interrupt), + * reset is only generated at second window overflow + */ + count = count >> 1; + + /* Disable the generic watchdog timer */ + regmap_read(wdt->regs, XWT_WWCSR_OFFSET, &csr); + csr &= ~(XWT_WWCSR_GWEN_MASK); + regmap_write(wdt->regs, XWT_WWCSR_OFFSET, csr); + + /* Set compare and offset registers for generic watchdog timeout */ + regmap_write(wdt->regs, XWT_WWCMP0_OFFSET, (u32)count); + regmap_write(wdt->regs, XWT_WWCMP1_OFFSET, 0); + regmap_write(wdt->regs, XWT_WWOFF_OFFSET, (u32)count); + + /* Enable the generic watchdog timer */ + regmap_read(wdt->regs, XWT_WWCSR_OFFSET, &csr); + csr |= (XWT_WWCSR_GWEN_MASK); + regmap_write(wdt->regs, XWT_WWCSR_OFFSET, csr); + + return 0; +} + +static int xlnx_wwdt_probe(struct udevice *dev) +{ + int ret; + struct xlnx_wwdt_platdata *platdata = dev_get_platdata(dev); + struct xlnx_wwdt_priv *wdt = dev_get_priv(dev); + + dev_dbg(dev, "%s: Probing wdt%u\n", __func__, dev->seq); + + ret = regmap_init_mem(dev_ofnode(dev), &wdt->regs); + if (ret) { + dev_dbg(dev, "failed to get regbase of wwdt\n"); + return ret; + } + + wdt->enable_once = platdata->enable_once; + + ret = clk_get_by_index(dev, 0, &wdt->clk); + if (ret < 0) + dev_err(dev, "failed to get clock\n"); + + return ret; +} + +static int xlnx_wwdt_ofdata_to_platdata(struct udevice *dev) +{ + struct xlnx_wwdt_platdata *platdata = dev_get_platdata(dev); + + platdata->enable_once = dev_read_u32_default(dev, + "xlnx,wdt-enable-once", 0); + dev_dbg(dev, "wdt-enable-once %d\n", platdata->enable_once); + + return 0; +} + +static const struct wdt_ops xlnx_wwdt_ops = { + .start = xlnx_wwdt_start, + .reset = xlnx_wwdt_reset, + .stop = xlnx_wwdt_stop, +}; + +static const struct udevice_id xlnx_wwdt_ids[] = { + { .compatible = "xlnx,versal-wwdt-1.0", }, + {}, +}; + +U_BOOT_DRIVER(xlnx_wwdt) = { + .name = "xlnx_wwdt", + .id = UCLASS_WDT, + .of_match = xlnx_wwdt_ids, + .probe = xlnx_wwdt_probe, + .priv_auto_alloc_size = sizeof(struct xlnx_wwdt_priv), + .platdata_auto_alloc_size = sizeof(struct xlnx_wwdt_platdata), + .ofdata_to_platdata = xlnx_wwdt_ofdata_to_platdata, + .ops = &xlnx_wwdt_ops, +}; |