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path: root/drivers/spi/mt7621_spi.c
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Diffstat (limited to 'drivers/spi/mt7621_spi.c')
-rw-r--r--drivers/spi/mt7621_spi.c247
1 files changed, 121 insertions, 126 deletions
diff --git a/drivers/spi/mt7621_spi.c b/drivers/spi/mt7621_spi.c
index 107e58f657..90e85c6b44 100644
--- a/drivers/spi/mt7621_spi.c
+++ b/drivers/spi/mt7621_spi.c
@@ -9,18 +9,22 @@
*/
#include <common.h>
+#include <clk.h>
#include <dm.h>
#include <spi.h>
#include <wait_bit.h>
#include <linux/io.h>
-#define SPI_MSG_SIZE_MAX 32 /* SPI message chunk size */
-/* Enough for SPI NAND page read / write with page size 2048 bytes */
-#define SPI_MSG_SIZE_OVERALL (2048 + 16)
+#define MT7621_RX_FIFO_LEN 32
+#define MT7621_TX_FIFO_LEN 36
#define MT7621_SPI_TRANS 0x00
#define MT7621_SPI_TRANS_START BIT(8)
#define MT7621_SPI_TRANS_BUSY BIT(16)
+#define TRANS_ADDR_SZ GENMASK(20, 19)
+#define TRANS_ADDR_SZ_SHIFT 19
+#define TRANS_MOSI_BCNT GENMASK(3, 0)
+#define TRANS_MOSI_BCNT_SHIFT 0
#define MT7621_SPI_OPCODE 0x04
#define MT7621_SPI_DATA0 0x08
@@ -38,27 +42,34 @@
#define MASTER_RS_CLK_SEL_SHIFT 16
#define MASTER_RS_SLAVE_SEL GENMASK(31, 29)
+#define MOREBUF_CMD_CNT GENMASK(29, 24)
+#define MOREBUF_CMD_CNT_SHIFT 24
+#define MOREBUF_MISO_CNT GENMASK(20, 12)
+#define MOREBUF_MISO_CNT_SHIFT 12
+#define MOREBUF_MOSI_CNT GENMASK(8, 0)
+#define MOREBUF_MOSI_CNT_SHIFT 0
+
struct mt7621_spi {
void __iomem *base;
unsigned int sys_freq;
- u32 data[(SPI_MSG_SIZE_OVERALL / 4) + 1];
- int tx_len;
};
-static void mt7621_spi_reset(struct mt7621_spi *rs, int duplex)
-{
- setbits_le32(rs->base + MT7621_SPI_MASTER,
- MASTER_RS_SLAVE_SEL | MASTER_MORE_BUFMODE);
-}
-
static void mt7621_spi_set_cs(struct mt7621_spi *rs, int cs, int enable)
{
- u32 val = 0;
-
debug("%s: cs#%d -> %s\n", __func__, cs, enable ? "enable" : "disable");
- if (enable)
- val = BIT(cs);
- iowrite32(val, rs->base + MT7621_SPI_POLAR);
+
+ if (enable) {
+ setbits_le32(rs->base + MT7621_SPI_MASTER,
+ MASTER_RS_SLAVE_SEL | MASTER_MORE_BUFMODE);
+ iowrite32(BIT(cs), rs->base + MT7621_SPI_POLAR);
+ } else {
+ iowrite32(0, rs->base + MT7621_SPI_POLAR);
+ iowrite32((2 << TRANS_ADDR_SZ_SHIFT) |
+ (1 << TRANS_MOSI_BCNT_SHIFT),
+ rs->base + MT7621_SPI_TRANS);
+ clrbits_le32(rs->base + MT7621_SPI_MASTER,
+ MASTER_RS_SLAVE_SEL | MASTER_MORE_BUFMODE);
+ }
}
static int mt7621_spi_set_mode(struct udevice *bus, uint mode)
@@ -128,20 +139,89 @@ static inline int mt7621_spi_wait_till_ready(struct mt7621_spi *rs)
return ret;
}
+static int mt7621_spi_read(struct mt7621_spi *rs, u8 *buf, size_t len)
+{
+ size_t rx_len;
+ int i, ret;
+ u32 val = 0;
+
+ while (len) {
+ rx_len = min_t(size_t, len, MT7621_RX_FIFO_LEN);
+
+ iowrite32((rx_len * 8) << MOREBUF_MISO_CNT_SHIFT,
+ rs->base + MT7621_SPI_MOREBUF);
+ iowrite32(MT7621_SPI_TRANS_START, rs->base + MT7621_SPI_TRANS);
+
+ ret = mt7621_spi_wait_till_ready(rs);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < rx_len; i++) {
+ if ((i % 4) == 0)
+ val = ioread32(rs->base + MT7621_SPI_DATA0 + i);
+ *buf++ = val & 0xff;
+ val >>= 8;
+ }
+
+ len -= rx_len;
+ }
+
+ return ret;
+}
+
+static int mt7621_spi_write(struct mt7621_spi *rs, const u8 *buf, size_t len)
+{
+ size_t tx_len, opcode_len, dido_len;
+ int i, ret;
+ u32 val;
+
+ while (len) {
+ tx_len = min_t(size_t, len, MT7621_TX_FIFO_LEN);
+
+ opcode_len = min_t(size_t, tx_len, 4);
+ dido_len = tx_len - opcode_len;
+
+ val = 0;
+ for (i = 0; i < opcode_len; i++) {
+ val <<= 8;
+ val |= *buf++;
+ }
+
+ iowrite32(val, rs->base + MT7621_SPI_OPCODE);
+
+ val = 0;
+ for (i = 0; i < dido_len; i++) {
+ val |= (*buf++) << ((i % 4) * 8);
+
+ if ((i % 4 == 3) || (i == dido_len - 1)) {
+ iowrite32(val, rs->base + MT7621_SPI_DATA0 +
+ (i & ~3));
+ val = 0;
+ }
+ }
+
+ iowrite32(((opcode_len * 8) << MOREBUF_CMD_CNT_SHIFT) |
+ ((dido_len * 8) << MOREBUF_MOSI_CNT_SHIFT),
+ rs->base + MT7621_SPI_MOREBUF);
+ iowrite32(MT7621_SPI_TRANS_START, rs->base + MT7621_SPI_TRANS);
+
+ ret = mt7621_spi_wait_till_ready(rs);
+ if (ret)
+ return ret;
+
+ len -= tx_len;
+ }
+
+ return 0;
+}
+
static int mt7621_spi_xfer(struct udevice *dev, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)
{
struct udevice *bus = dev->parent;
struct mt7621_spi *rs = dev_get_priv(bus);
- const u8 *tx_buf = dout;
- u8 *ptr = (u8 *)dout;
- u8 *rx_buf = din;
int total_size = bitlen >> 3;
- int chunk_size;
- int rx_len = 0;
- u32 data[(SPI_MSG_SIZE_MAX / 4) + 1] = { 0 };
- u32 val;
- int i;
+ int ret = 0;
debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din,
total_size, flags);
@@ -155,13 +235,6 @@ static int mt7621_spi_xfer(struct udevice *dev, unsigned int bitlen,
return -EIO;
}
- if (dout) {
- debug("TX-DATA: ");
- for (i = 0; i < total_size; i++)
- debug("%02x ", *ptr++);
- debug("\n");
- }
-
mt7621_spi_wait_till_ready(rs);
/*
@@ -171,119 +244,41 @@ static int mt7621_spi_xfer(struct udevice *dev, unsigned int bitlen,
if (flags & SPI_XFER_BEGIN)
mt7621_spi_set_cs(rs, spi_chip_select(dev), 1);
- while (total_size > 0) {
- /* Don't exceed the max xfer size */
- chunk_size = min_t(int, total_size, SPI_MSG_SIZE_MAX);
-
- /*
- * We might have some TX data buffered from the last xfer
- * message. Make sure, that this does not exceed the max
- * xfer size
- */
- if (rs->tx_len > 4)
- chunk_size -= rs->tx_len;
- if (din)
- rx_len = chunk_size;
-
- if (tx_buf) {
- /* Check if this message does not exceed the buffer */
- if ((chunk_size + rs->tx_len) > SPI_MSG_SIZE_OVERALL) {
- printf("TX message size too big (%d)\n",
- chunk_size + rs->tx_len);
- return -EMSGSIZE;
- }
-
- /*
- * Write all TX data into internal buffer to collect
- * all TX messages into one buffer (might be split into
- * multiple calls to this function)
- */
- for (i = 0; i < chunk_size; i++, rs->tx_len++) {
- rs->data[rs->tx_len / 4] |=
- tx_buf[i] << (8 * (rs->tx_len & 3));
- }
- }
-
- if (flags & SPI_XFER_END) {
- /* Write TX data into controller */
- if (rs->tx_len) {
- rs->data[0] = swab32(rs->data[0]);
- if (rs->tx_len < 4)
- rs->data[0] >>= (4 - rs->tx_len) * 8;
-
- for (i = 0; i < rs->tx_len; i += 4) {
- iowrite32(rs->data[i / 4], rs->base +
- MT7621_SPI_OPCODE + i);
- }
- }
+ if (din)
+ ret = mt7621_spi_read(rs, din, total_size);
+ else if (dout)
+ ret = mt7621_spi_write(rs, dout, total_size);
- /* Write length into controller */
- val = (min_t(int, rs->tx_len, 4) * 8) << 24;
- if (rs->tx_len > 4)
- val |= (rs->tx_len - 4) * 8;
- val |= (rx_len * 8) << 12;
- iowrite32(val, rs->base + MT7621_SPI_MOREBUF);
-
- /* Start the xfer */
- setbits_le32(rs->base + MT7621_SPI_TRANS,
- MT7621_SPI_TRANS_START);
-
- /* Wait until xfer is finished on bus */
- mt7621_spi_wait_till_ready(rs);
-
- /* Reset TX length and TX buffer for next xfer */
- rs->tx_len = 0;
- memset(rs->data, 0, sizeof(rs->data));
- }
-
- for (i = 0; i < rx_len; i += 4)
- data[i / 4] = ioread32(rs->base + MT7621_SPI_DATA0 + i);
-
- if (rx_len) {
- debug("RX-DATA: ");
- for (i = 0; i < rx_len; i++) {
- rx_buf[i] = data[i / 4] >> (8 * (i & 3));
- debug("%02x ", rx_buf[i]);
- }
- debug("\n");
- }
-
- if (tx_buf)
- tx_buf += chunk_size;
- if (rx_buf)
- rx_buf += chunk_size;
- total_size -= chunk_size;
- }
-
- /* Wait until xfer is finished on bus and de-assert CS */
- mt7621_spi_wait_till_ready(rs);
if (flags & SPI_XFER_END)
mt7621_spi_set_cs(rs, spi_chip_select(dev), 0);
- return 0;
+ return ret;
}
static int mt7621_spi_probe(struct udevice *dev)
{
struct mt7621_spi *rs = dev_get_priv(dev);
+ struct clk clk;
+ int ret;
rs->base = dev_remap_addr(dev);
if (!rs->base)
return -EINVAL;
- /*
- * Read input clock via DT for now. At some point this should be
- * replaced by implementing a clock driver for this SoC and getting
- * the SPI frequency via this clock driver.
- */
- rs->sys_freq = dev_read_u32_default(dev, "clock-frequency", 0);
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret < 0) {
+ printf("Please provide a clock!\n");
+ return ret;
+ }
+
+ clk_enable(&clk);
+
+ rs->sys_freq = clk_get_rate(&clk);
if (!rs->sys_freq) {
- printf("Please provide clock-frequency!\n");
+ printf("Please provide a valid clock!\n");
return -EINVAL;
}
- mt7621_spi_reset(rs, 0);
-
return 0;
}