diff options
Diffstat (limited to 'drivers/serial')
| -rw-r--r-- | drivers/serial/Makefile | 1 | ||||
| -rw-r--r-- | drivers/serial/s3c64xx.c | 172 | ||||
| -rw-r--r-- | drivers/serial/serial_sh.c | 49 |
3 files changed, 209 insertions, 13 deletions
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 2384735a2c..f30014d32e 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -30,6 +30,7 @@ COBJS-$(CONFIG_MCFUART) += mcfuart.o COBJS-$(CONFIG_NS9750_UART) += ns9750_serial.o COBJS-y += ns16550.o COBJS-$(CONFIG_DRIVER_S3C4510_UART) += s3c4510b_uart.o +COBJS-$(CONFIG_S3C64XX) += s3c64xx.o COBJS-y += serial.o COBJS-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o COBJS-y += serial_pl010.o diff --git a/drivers/serial/s3c64xx.c b/drivers/serial/s3c64xx.c new file mode 100644 index 0000000000..9d8fcb9b49 --- /dev/null +++ b/drivers/serial/s3c64xx.c @@ -0,0 +1,172 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> + * + * (C) Copyright 2008 + * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include <common.h> + +#include <s3c6400.h> + +#ifdef CONFIG_SERIAL1 +#define UART_NR S3C64XX_UART0 + +#elif defined(CONFIG_SERIAL2) +#define UART_NR S3C64XX_UART1 + +#elif defined(CONFIG_SERIAL3) +#define UART_NR S3C64XX_UART2 + +#else +#error "Bad: you didn't configure serial ..." +#endif + +#define barrier() asm volatile("" ::: "memory") + +/* + * The coefficient, used to calculate the baudrate on S3C6400 UARTs is + * calculated as + * C = UBRDIV * 16 + number_of_set_bits_in_UDIVSLOT + * however, section 31.6.11 of the datasheet doesn't recomment using 1 for 1, + * 3 for 2, ... (2^n - 1) for n, instead, they suggest using these constants: + */ +static const int udivslot[] = { + 0, + 0x0080, + 0x0808, + 0x0888, + 0x2222, + 0x4924, + 0x4a52, + 0x54aa, + 0x5555, + 0xd555, + 0xd5d5, + 0xddd5, + 0xdddd, + 0xdfdd, + 0xdfdf, + 0xffdf, +}; + +void serial_setbrg(void) +{ + DECLARE_GLOBAL_DATA_PTR; + s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR); + u32 pclk = get_PCLK(); + u32 baudrate = gd->baudrate; + int i; + + i = (pclk / baudrate) % 16; + + uart->UBRDIV = pclk / baudrate / 16 - 1; + uart->UDIVSLOT = udivslot[i]; + + for (i = 0; i < 100; i++) + barrier(); +} + +/* + * Initialise the serial port with the given baudrate. The settings + * are always 8 data bits, no parity, 1 stop bit, no start bits. + */ +int serial_init(void) +{ + s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR); + + /* reset and enable FIFOs, set triggers to the maximum */ + uart->UFCON = 0xff; + uart->UMCON = 0; + /* 8N1 */ + uart->ULCON = 3; + /* No interrupts, no DMA, pure polling */ + uart->UCON = 5; + + serial_setbrg(); + + return 0; +} + +/* + * Read a single byte from the serial port. Returns 1 on success, 0 + * otherwise. When the function is succesfull, the character read is + * written into its argument c. + */ +int serial_getc(void) +{ + s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR); + + /* wait for character to arrive */ + while (!(uart->UTRSTAT & 0x1)); + + return uart->URXH & 0xff; +} + +#ifdef CONFIG_MODEM_SUPPORT +static int be_quiet; +void disable_putc(void) +{ + be_quiet = 1; +} + +void enable_putc(void) +{ + be_quiet = 0; +} +#endif + + +/* + * Output a single byte to the serial port. + */ +void serial_putc(const char c) +{ + s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR); + +#ifdef CONFIG_MODEM_SUPPORT + if (be_quiet) + return; +#endif + + /* wait for room in the tx FIFO */ + while (!(uart->UTRSTAT & 0x2)); + + uart->UTXH = c; + + /* If \n, also do \r */ + if (c == '\n') + serial_putc('\r'); +} + +/* + * Test whether a character is in the RX buffer + */ +int serial_tstc(void) +{ + s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR); + + return uart->UTRSTAT & 0x1; +} + +void serial_puts(const char *s) +{ + while (*s) + serial_putc(*s++); +} diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index 2b9eeed47e..61c2b82c0a 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -20,14 +20,20 @@ #include <common.h> #include <asm/processor.h> -#if defined (CONFIG_CONS_SCIF0) -#define SCIF_BASE SCIF0_BASE -#elif defined (CONFIG_CONS_SCIF1) -#define SCIF_BASE SCIF1_BASE -#elif defined (CONFIG_CONS_SCIF2) -#define SCIF_BASE SCIF2_BASE +#if defined(CONFIG_CONS_SCIF0) +# define SCIF_BASE SCIF0_BASE +#elif defined(CONFIG_CONS_SCIF1) +# define SCIF_BASE SCIF1_BASE +#elif defined(CONFIG_CONS_SCIF2) +# define SCIF_BASE SCIF2_BASE +#elif defined(CONFIG_CONS_SCIF3) +# define SCIF_BASE SCIF3_BASE +#elif defined(CONFIG_CONS_SCIF4) +# define SCIF_BASE SCIF4_BASE +#elif defined(CONFIG_CONS_SCIF5) +# define SCIF_BASE SCIF5_BASE #else -#error "Default SCIF doesn't set....." +# error "Default SCIF doesn't set....." #endif /* Base register */ @@ -36,7 +42,8 @@ #define SCSCR (vu_short *)(SCIF_BASE + 0x8) #define SCFCR (vu_short *)(SCIF_BASE + 0x18) #define SCFDR (vu_short *)(SCIF_BASE + 0x1C) -#ifdef CONFIG_CPU_SH7720 /* SH7720 specific */ +#if defined(CONFIG_CPU_SH7720) || \ + (defined(CONFIG_CPU_SH7723) && defined(CONFIG_SCIF_A)) # define SCFSR (vu_short *)(SCIF_BASE + 0x14) /* SCSSR */ # define SCFTDR (vu_char *)(SCIF_BASE + 0x20) # define SCFRDR (vu_char *)(SCIF_BASE + 0x24) @@ -55,7 +62,7 @@ # define LSR_ORER 1 # define FIFOLEVEL_MASK 0xFF #elif defined(CONFIG_CPU_SH7763) -# if defined (CONFIG_CONS_SCIF2) +# if defined(CONFIG_CONS_SCIF2) # define SCSPTR (vu_short *)(SCIF_BASE + 0x20) # define SCLSR (vu_short *)(SCIF_BASE + 0x24) # define LSR_ORER 1 @@ -68,9 +75,20 @@ # define LSR_ORER 1 # define FIFOLEVEL_MASK 0xFF # endif +#elif defined(CONFIG_CPU_SH7723) +# if defined(CONIFG_SCIF_A) +# define SCLSR SCFSR +# define LSR_ORER 0x0200 +# define FIFOLEVEL_MASK 0x3F +#else +# define SCLSR (vu_short *)(SCIF_BASE + 0x24) +# define LSR_ORER 1 +# define FIFOLEVEL_MASK 0x1F +#endif #elif defined(CONFIG_CPU_SH7750) || \ defined(CONFIG_CPU_SH7751) || \ - defined(CONFIG_CPU_SH7722) + defined(CONFIG_CPU_SH7722) || \ + defined(CONFIG_CPU_SH7203) # define SCSPTR (vu_short *)(SCIF_BASE + 0x20) # define SCLSR (vu_short *)(SCIF_BASE + 0x24) # define LSR_ORER 1 @@ -89,6 +107,9 @@ /* SCBRR register value setting */ #if defined(CONFIG_CPU_SH7720) # define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) +#elif defined(CONFIG_CPU_SH7723) && defined(CONFIG_SCIF_A) +/* SH7723 SCIFA use bus clock. So clock *2 */ +# define SCBRR_VALUE(bps, clk) (((clk*2*2)+16*bps)/(32*bps)-1) #else /* Generic SuperH */ # define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) #endif @@ -167,7 +188,7 @@ void serial_puts(const char *s) int serial_tstc(void) { - return serial_rx_fifo_level()? 1 : 0; + return serial_rx_fifo_level() ? 1 : 0; } #define FSR_ERR_CLEAR 0x0063 @@ -191,14 +212,16 @@ int serial_getc_check(void) handle_error(); if (*SCLSR & LSR_ORER) handle_error(); - return (status & (FSR_DR | FSR_RDF)); + return status & (FSR_DR | FSR_RDF); } int serial_getc(void) { unsigned short status; char ch; - while (!serial_getc_check()) ; + + while (!serial_getc_check()) + ; ch = *SCFRDR; status = *SCFSR; |