summaryrefslogtreecommitdiff
path: root/drivers/pci
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/pci-uclass.c4
-rw-r--r--drivers/pci/pci_auto.c1
-rw-r--r--drivers/pci/pcie_imx.c6
3 files changed, 6 insertions, 5 deletions
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index ea70853da2..0756bbe8f1 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -238,7 +238,7 @@ int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
{
struct udevice *bus;
- for (bus = dev; device_get_uclass_id(bus->parent) == UCLASS_PCI;)
+ for (bus = dev; device_is_on_pci_bus(bus);)
bus = bus->parent;
return pci_bus_write_config(bus, pci_get_bdf(dev), offset, value, size);
}
@@ -303,7 +303,7 @@ int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep,
{
struct udevice *bus;
- for (bus = dev; device_get_uclass_id(bus->parent) == UCLASS_PCI;)
+ for (bus = dev; device_is_on_pci_bus(bus);)
bus = bus->parent;
return pci_bus_read_config(bus, pci_get_bdf(dev), offset, valuep,
size);
diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c
index 41d5447f12..79f27c744b 100644
--- a/drivers/pci/pci_auto.c
+++ b/drivers/pci/pci_auto.c
@@ -185,6 +185,7 @@ void pciauto_setup_device(struct pci_controller *hose,
#ifndef CONFIG_PCI_ENUM_ONLY
/* Configure the expansion ROM address */
pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
+ header_type &= 0x7f;
if (header_type != PCI_HEADER_TYPE_CARDBUS) {
rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c
index ca485ba90c..1568f20c1a 100644
--- a/drivers/pci/pcie_imx.c
+++ b/drivers/pci/pcie_imx.c
@@ -495,7 +495,7 @@ __weak int imx6_pcie_toggle_reset(void)
*
* The PCIe #PERST reset line _MUST_ be connected, otherwise your
* design does not conform to the specification. You must wait at
- * least 20 mS after de-asserting the #PERST so the EP device can
+ * least 20 ms after de-asserting the #PERST so the EP device can
* do self-initialisation.
*
* In case your #PERST pin is connected to a plain GPIO pin of the
@@ -506,7 +506,7 @@ __weak int imx6_pcie_toggle_reset(void)
* In case your #PERST toggling logic is more complex, for example
* connected via CPLD or somesuch, you can override this function
* in your board file and implement reset logic as needed. You must
- * not forget to wait at least 20 mS after de-asserting #PERST in
+ * not forget to wait at least 20 ms after de-asserting #PERST in
* this case either though.
*
* In case your #PERST line of the PCIe EP device is not connected
@@ -538,7 +538,7 @@ static int imx6_pcie_deassert_core_reset(void)
/*
* Wait for the clock to settle a bit, when the clock are sourced
- * from the CPU, we need about 30mS to settle.
+ * from the CPU, we need about 30 ms to settle.
*/
mdelay(50);