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path: root/drivers/net/sh_eth.h
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Diffstat (limited to 'drivers/net/sh_eth.h')
-rw-r--r--drivers/net/sh_eth.h34
1 files changed, 29 insertions, 5 deletions
diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index 9ad800e4273..8aa71098cb3 100644
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -31,6 +31,11 @@
#define ADDR_TO_P2(addr) (addr)
#endif /* defined(CONFIG_SH) */
+/* base padding size is 16 */
+#ifndef CONFIG_SH_ETHER_ALIGNE_SIZE
+#define CONFIG_SH_ETHER_ALIGNE_SIZE 16
+#endif
+
/* Number of supported ports */
#define MAX_PORT_NUM 2
@@ -45,15 +50,16 @@
/* The size of the tx descriptor is determined by how much padding is used.
4, 20, or 52 bytes of padding can be used */
-#define TX_DESC_PADDING 4
-#define TX_DESC_SIZE (12 + TX_DESC_PADDING)
+#define TX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
+/* same as CONFIG_SH_ETHER_ALIGNE_SIZE */
+#define TX_DESC_SIZE (12 + TX_DESC_PADDING)
/* Tx descriptor. We always use 3 bytes of padding */
struct tx_desc_s {
volatile u32 td0;
u32 td1;
u32 td2; /* Buffer start */
- u32 padding;
+ u8 padding[TX_DESC_PADDING]; /* aligned cache line size */
};
/* There is no limitation in the number of rx descriptors */
@@ -61,15 +67,18 @@ struct tx_desc_s {
/* The size of the rx descriptor is determined by how much padding is used.
4, 20, or 52 bytes of padding can be used */
-#define RX_DESC_PADDING 4
+#define RX_DESC_PADDING (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
+/* same as CONFIG_SH_ETHER_ALIGNE_SIZE */
#define RX_DESC_SIZE (12 + RX_DESC_PADDING)
+/* aligned cache line size */
+#define RX_BUF_ALIGNE_SIZE (CONFIG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32)
/* Rx descriptor. We always use 4 bytes of padding */
struct rx_desc_s {
volatile u32 rd0;
volatile u32 rd1;
u32 rd2; /* Buffer start */
- u32 padding;
+ u8 padding[TX_DESC_PADDING]; /* aligned cache line size */
};
struct sh_eth_info {
@@ -157,6 +166,7 @@ enum {
TLFRCR,
CERCR,
CEECR,
+ RMIIMR, /* R8A7790 */
MAFCR,
RTRATE,
CSMR,
@@ -263,6 +273,7 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
[RMCR] = 0x0058,
[TFUCR] = 0x0064,
[RFOCR] = 0x0068,
+ [RMIIMR] = 0x006C,
[FCFTR] = 0x0070,
[RPADIR] = 0x0078,
[TRIMD] = 0x007c,
@@ -290,6 +301,9 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
#elif defined(CONFIG_R8A7740)
#define SH_ETH_TYPE_GETHER
#define BASE_IO_ADDR 0xE9A00000
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
+#define SH_ETH_TYPE_ETHER
+#define BASE_IO_ADDR 0xEE700200
#endif
/*
@@ -320,6 +334,14 @@ enum DMAC_M_BIT {
#endif
};
+#if CONFIG_SH_ETHER_ALIGNE_SIZE == 64
+# define EMDR_DESC EDMR_DL1
+#elif CONFIG_SH_ETHER_ALIGNE_SIZE == 32
+# define EMDR_DESC EDMR_DL0
+#elif CONFIG_SH_ETHER_ALIGNE_SIZE == 16 /* Default */
+# define EMDR_DESC 0
+#endif
+
/* RFLR */
#define RFLR_RFL_MIN 0x05EE /* Recv Frame length 1518 byte */
@@ -485,6 +507,8 @@ enum FELIC_MODE_BIT {
ECMR_PRM = 0x00000001,
#ifdef CONFIG_CPU_SH7724
ECMR_RTM = 0x00000010,
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
+ ECMR_RTM = 0x00000004,
#endif
};