5 files changed, 9 insertions, 9 deletions
diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c
index 82c787bf38..54b142f47d 100644
--- a/drivers/net/fm/eth.c
+++ b/drivers/net/fm/eth.c
@@ -46,7 +46,7 @@ static int num_controllers;
 			TBICR_FULL_DUPLEX | TBICR_SPEED1_SET)
 
 /* Configure the TBI for SGMII operation */
-void dtsec_configure_serdes(struct fm_eth *priv)
+static void dtsec_configure_serdes(struct fm_eth *priv)
 {
 #ifdef CONFIG_SYS_FMAN_V3
 	u32 value;
diff --git a/drivers/net/fm/p1023.c b/drivers/net/fm/p1023.c
index 9765da5b23..387d2a382d 100644
--- a/drivers/net/fm/p1023.c
+++ b/drivers/net/fm/p1023.c
@@ -23,7 +23,7 @@
 #include <asm/immap_85xx.h>
 #include <asm/fsl_serdes.h>
 
-u32 port_to_devdisr[] = {
+static u32 port_to_devdisr[] = {
 	[FM1_DTSEC1] = MPC85xx_DEVDISR_TSEC1,
 	[FM1_DTSEC2] = MPC85xx_DEVDISR_TSEC2,
 };
diff --git a/drivers/net/fm/p4080.c b/drivers/net/fm/p4080.c
index 9dc6049c36..b04fd0f656 100644
--- a/drivers/net/fm/p4080.c
+++ b/drivers/net/fm/p4080.c
@@ -23,7 +23,7 @@
 #include <asm/immap_85xx.h>
 #include <asm/fsl_serdes.h>
 
-u32 port_to_devdisr[] = {
+static u32 port_to_devdisr[] = {
 	[FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
 	[FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
 	[FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
diff --git a/drivers/net/fm/p5020.c b/drivers/net/fm/p5020.c
index a7a6e43fe2..5391044833 100644
--- a/drivers/net/fm/p5020.c
+++ b/drivers/net/fm/p5020.c
@@ -23,7 +23,7 @@
 #include <asm/immap_85xx.h>
 #include <asm/fsl_serdes.h>
 
-u32 port_to_devdisr[] = {
+static u32 port_to_devdisr[] = {
 	[FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
 	[FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
 	[FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
diff --git a/drivers/net/fm/tgec_phy.c b/drivers/net/fm/tgec_phy.c
index 2d349ad037..2be69d7162 100644
--- a/drivers/net/fm/tgec_phy.c
+++ b/drivers/net/fm/tgec_phy.c
@@ -30,8 +30,8 @@
  * until the write is done before it returns.  All PHY configuration has to be
  * done through the TSEC1 MIIM regs
  */
-int tgec_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
-			int regnum, u16 value)
+static int tgec_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
+			   int regnum, u16 value)
 {
 	u32 mdio_ctl;
 	u32 stat_val;
@@ -72,8 +72,8 @@ int tgec_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
  * Clears miimcom first.  All PHY configuration has to be done through the
  * TSEC1 MIIM regs
  */
-int tgec_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
-			int regnum)
+static int tgec_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
+			  int regnum)
 {
 	u32 mdio_ctl;
 	u32 stat_val;
@@ -114,7 +114,7 @@ int tgec_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
 	return in_be32(&regs->mdio_data) & 0xffff;
 }
 
-int tgec_mdio_reset(struct mii_dev *bus)
+static int tgec_mdio_reset(struct mii_dev *bus)
 {
 	return 0;
 }