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path: root/drivers/net/fec_mxc.h
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Diffstat (limited to 'drivers/net/fec_mxc.h')
-rw-r--r--drivers/net/fec_mxc.h32
1 files changed, 30 insertions, 2 deletions
diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h
index 6cb1bfc055..5d0d69d5e9 100644
--- a/drivers/net/fec_mxc.h
+++ b/drivers/net/fec_mxc.h
@@ -145,9 +145,17 @@ struct ethernet_regs {
uint32_t r_fdxfc; /* MBAR_ETH + 0x2DC */
uint32_t ieee_r_octets_ok; /* MBAR_ETH + 0x2E0 */
- uint32_t res14[6]; /* MBAR_ETH + 0x2E4-2FC */
-
+ uint32_t res14[7]; /* MBAR_ETH + 0x2E4-2FC */
+
+#ifdef CONFIG_MX25
+ uint16_t miigsk_cfgr; /* MBAR_ETH + 0x300 */
+ uint16_t res15[3]; /* MBAR_ETH + 0x302-306 */
+ uint16_t miigsk_enr; /* MBAR_ETH + 0x308 */
+ uint16_t res16[3]; /* MBAR_ETH + 0x30a-30e */
+ uint32_t res17[60]; /* MBAR_ETH + 0x300-3FF */
+#else
uint32_t res15[64]; /* MBAR_ETH + 0x300-3FF */
+#endif
};
#define FEC_IEVENT_HBERR 0x80000000
@@ -196,6 +204,26 @@ struct ethernet_regs {
#define FEC_ECNTRL_RESET 0x00000001 /* reset the FEC */
#define FEC_ECNTRL_ETHER_EN 0x00000002 /* enable the FEC */
+#ifdef CONFIG_MX25
+/* defines for MIIGSK */
+/* RMII frequency control: 0=50MHz, 1=5MHz */
+#define MIIGSK_CFGR_FRCONT (1 << 6)
+/* loopback mode */
+#define MIIGSK_CFGR_LBMODE (1 << 4)
+/* echo mode */
+#define MIIGSK_CFGR_EMODE (1 << 3)
+/* MII gasket mode field */
+#define MIIGSK_CFGR_IF_MODE_MASK (3 << 0)
+/* MMI/7-Wire mode */
+#define MIIGSK_CFGR_IF_MODE_MII (0 << 0)
+/* RMII mode */
+#define MIIGSK_CFGR_IF_MODE_RMII (1 << 0)
+/* reflects MIIGSK Enable bit (RO) */
+#define MIIGSK_ENR_READY (1 << 2)
+/* enable MIGSK (set by default) */
+#define MIIGSK_ENR_EN (1 << 1)
+#endif
+
/**
* @brief Descriptor buffer alignment
*