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-rw-r--r--drivers/mtd/Makefile4
-rw-r--r--drivers/mtd/mtd_uboot.c99
-rw-r--r--drivers/mtd/nand/Makefile1
-rw-r--r--drivers/mtd/nand/omap_gpmc.c236
-rw-r--r--drivers/mtd/nand/sunxi_nand_spl.c273
-rw-r--r--drivers/mtd/spi/Kconfig9
-rw-r--r--drivers/mtd/spi/Makefile2
-rw-r--r--drivers/mtd/spi/sf_dataflash.c711
-rw-r--r--drivers/mtd/spi/sf_internal.h5
-rw-r--r--drivers/mtd/spi/sf_mtd.c104
-rw-r--r--drivers/mtd/spi/sf_probe.c11
11 files changed, 1060 insertions, 395 deletions
diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile
index 5467a951bb..a623f4c9fa 100644
--- a/drivers/mtd/Makefile
+++ b/drivers/mtd/Makefile
@@ -5,8 +5,8 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq (,$(findstring y,$(CONFIG_MTD_DEVICE)$(CONFIG_CMD_NAND)$(CONFIG_CMD_ONENAND)))
-obj-y += mtdcore.o
+ifneq (,$(findstring y,$(CONFIG_MTD_DEVICE)$(CONFIG_CMD_NAND)$(CONFIG_CMD_ONENAND)$(CONFIG_CMD_SF)))
+obj-y += mtdcore.o mtd_uboot.o
endif
obj-$(CONFIG_MTD_PARTITIONS) += mtdpart.o
obj-$(CONFIG_MTD_CONCAT) += mtdconcat.o
diff --git a/drivers/mtd/mtd_uboot.c b/drivers/mtd/mtd_uboot.c
new file mode 100644
index 0000000000..7197007d41
--- /dev/null
+++ b/drivers/mtd/mtd_uboot.c
@@ -0,0 +1,99 @@
+/*
+ * (C) Copyright 2014
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <linux/mtd/mtd.h>
+#include <jffs2/jffs2.h>
+
+static int get_part(const char *partname, int *idx, loff_t *off, loff_t *size,
+ loff_t *maxsize, int devtype)
+{
+#ifdef CONFIG_CMD_MTDPARTS
+ struct mtd_device *dev;
+ struct part_info *part;
+ u8 pnum;
+ int ret;
+
+ ret = mtdparts_init();
+ if (ret)
+ return ret;
+
+ ret = find_dev_and_part(partname, &dev, &pnum, &part);
+ if (ret)
+ return ret;
+
+ if (dev->id->type != devtype) {
+ printf("not same typ %d != %d\n", dev->id->type, devtype);
+ return -1;
+ }
+
+ *off = part->offset;
+ *size = part->size;
+ *maxsize = part->size;
+ *idx = dev->id->num;
+
+ return 0;
+#else
+ puts("offset is not a number\n");
+ return -1;
+#endif
+}
+
+int mtd_arg_off(const char *arg, int *idx, loff_t *off, loff_t *size,
+ loff_t *maxsize, int devtype, int chipsize)
+{
+ if (!str2off(arg, off))
+ return get_part(arg, idx, off, size, maxsize, devtype);
+
+ if (*off >= chipsize) {
+ puts("Offset exceeds device limit\n");
+ return -1;
+ }
+
+ *maxsize = chipsize - *off;
+ *size = *maxsize;
+ return 0;
+}
+
+int mtd_arg_off_size(int argc, char *const argv[], int *idx, loff_t *off,
+ loff_t *size, loff_t *maxsize, int devtype, int chipsize)
+{
+ int ret;
+
+ if (argc == 0) {
+ *off = 0;
+ *size = chipsize;
+ *maxsize = *size;
+ goto print;
+ }
+
+ ret = mtd_arg_off(argv[0], idx, off, size, maxsize, devtype,
+ chipsize);
+ if (ret)
+ return ret;
+
+ if (argc == 1)
+ goto print;
+
+ if (!str2off(argv[1], size)) {
+ printf("'%s' is not a number\n", argv[1]);
+ return -1;
+ }
+
+ if (*size > *maxsize) {
+ puts("Size exceeds partition or device limit\n");
+ return -1;
+ }
+
+print:
+ printf("device %d ", *idx);
+ if (*size == chipsize)
+ puts("whole chip\n");
+ else
+ printf("offset 0x%llx, size 0x%llx\n",
+ (unsigned long long)*off, (unsigned long long)*size);
+ return 0;
+}
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index a0cf4d5fe4..347ea62e0b 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -73,6 +73,5 @@ obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_spl.o
obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_spl.o
obj-$(CONFIG_NAND_MXC) += mxc_nand_spl.o
obj-$(CONFIG_NAND_MXS) += mxs_nand_spl.o mxs_nand.o
-obj-$(CONFIG_NAND_SUNXI) += sunxi_nand_spl.o
endif # drivers
diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c
index 610f9698e1..4372988ed2 100644
--- a/drivers/mtd/nand/omap_gpmc.c
+++ b/drivers/mtd/nand/omap_gpmc.c
@@ -340,6 +340,125 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
return 0;
}
+#ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH
+
+#define PREFETCH_CONFIG1_CS_SHIFT 24
+#define PREFETCH_FIFOTHRESHOLD_MAX 0x40
+#define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8)
+#define PREFETCH_STATUS_COUNT(val) (val & 0x00003fff)
+#define PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F)
+#define ENABLE_PREFETCH (1 << 7)
+
+/**
+ * omap_prefetch_enable - configures and starts prefetch transfer
+ * @fifo_th: fifo threshold to be used for read/ write
+ * @count: number of bytes to be transferred
+ * @is_write: prefetch read(0) or write post(1) mode
+ * @cs: chip select to use
+ */
+static int omap_prefetch_enable(int fifo_th, unsigned int count, int is_write, int cs)
+{
+ uint32_t val;
+
+ if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX)
+ return -EINVAL;
+
+ if (readl(&gpmc_cfg->prefetch_control))
+ return -EBUSY;
+
+ /* Set the amount of bytes to be prefetched */
+ writel(count, &gpmc_cfg->prefetch_config2);
+
+ val = (cs << PREFETCH_CONFIG1_CS_SHIFT) | (is_write & 1) |
+ PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH;
+ writel(val, &gpmc_cfg->prefetch_config1);
+
+ /* Start the prefetch engine */
+ writel(1, &gpmc_cfg->prefetch_control);
+
+ return 0;
+}
+
+/**
+ * omap_prefetch_reset - disables and stops the prefetch engine
+ */
+static void omap_prefetch_reset(void)
+{
+ writel(0, &gpmc_cfg->prefetch_control);
+ writel(0, &gpmc_cfg->prefetch_config1);
+}
+
+static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int len)
+{
+ int ret;
+ uint32_t cnt;
+ struct omap_nand_info *info = chip->priv;
+
+ ret = omap_prefetch_enable(PREFETCH_FIFOTHRESHOLD_MAX, len, 0, info->cs);
+ if (ret < 0)
+ return ret;
+
+ do {
+ int i;
+
+ cnt = readl(&gpmc_cfg->prefetch_status);
+ cnt = PREFETCH_STATUS_FIFO_CNT(cnt);
+
+ for (i = 0; i < cnt / 4; i++) {
+ *buf++ = readl(CONFIG_SYS_NAND_BASE);
+ len -= 4;
+ }
+ } while (len);
+
+ omap_prefetch_reset();
+
+ return 0;
+}
+
+static inline void omap_nand_read(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+ struct nand_chip *chip = mtd->priv;
+
+ if (chip->options & NAND_BUSWIDTH_16)
+ nand_read_buf16(mtd, buf, len);
+ else
+ nand_read_buf(mtd, buf, len);
+}
+
+static void omap_nand_read_prefetch(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+ int ret;
+ uint32_t head, tail;
+ struct nand_chip *chip = mtd->priv;
+
+ /*
+ * If the destination buffer is unaligned, start with reading
+ * the overlap byte-wise.
+ */
+ head = ((uint32_t) buf) % 4;
+ if (head) {
+ omap_nand_read(mtd, buf, head);
+ buf += head;
+ len -= head;
+ }
+
+ /*
+ * Only transfer multiples of 4 bytes in a pre-fetched fashion.
+ * If there's a residue, care for it byte-wise afterwards.
+ */
+ tail = len % 4;
+
+ ret = __read_prefetch_aligned(chip, (uint32_t *)buf, len - tail);
+ if (ret < 0) {
+ /* fallback in case the prefetch engine is busy */
+ omap_nand_read(mtd, buf, len);
+ } else if (tail) {
+ buf += len - tail;
+ omap_nand_read(mtd, buf, tail);
+ }
+}
+#endif /* CONFIG_NAND_OMAP_GPMC_PREFETCH */
+
#ifdef CONFIG_NAND_OMAP_ELM
/*
* omap_reverse_list - re-orders list elements in reverse order [internal]
@@ -452,115 +571,6 @@ static int omap_correct_data_bch(struct mtd_info *mtd, uint8_t *dat,
return (err) ? err : error_count;
}
-#ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH
-
-#define PREFETCH_CONFIG1_CS_SHIFT 24
-#define PREFETCH_FIFOTHRESHOLD_MAX 0x40
-#define PREFETCH_FIFOTHRESHOLD(val) ((val) << 8)
-#define PREFETCH_STATUS_COUNT(val) (val & 0x00003fff)
-#define PREFETCH_STATUS_FIFO_CNT(val) ((val >> 24) & 0x7F)
-#define ENABLE_PREFETCH (1 << 7)
-
-/**
- * omap_prefetch_enable - configures and starts prefetch transfer
- * @fifo_th: fifo threshold to be used for read/ write
- * @count: number of bytes to be transferred
- * @is_write: prefetch read(0) or write post(1) mode
- * @cs: chip select to use
- */
-static int omap_prefetch_enable(int fifo_th, unsigned int count, int is_write, int cs)
-{
- uint32_t val;
-
- if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX)
- return -EINVAL;
-
- if (readl(&gpmc_cfg->prefetch_control))
- return -EBUSY;
-
- /* Set the amount of bytes to be prefetched */
- writel(count, &gpmc_cfg->prefetch_config2);
-
- val = (cs << PREFETCH_CONFIG1_CS_SHIFT) | (is_write & 1) |
- PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH;
- writel(val, &gpmc_cfg->prefetch_config1);
-
- /* Start the prefetch engine */
- writel(1, &gpmc_cfg->prefetch_control);
-
- return 0;
-}
-
-/**
- * omap_prefetch_reset - disables and stops the prefetch engine
- */
-static void omap_prefetch_reset(void)
-{
- writel(0, &gpmc_cfg->prefetch_control);
- writel(0, &gpmc_cfg->prefetch_config1);
-}
-
-static int __read_prefetch_aligned(struct nand_chip *chip, uint32_t *buf, int len)
-{
- int ret;
- uint32_t cnt;
- struct omap_nand_info *info = chip->priv;
-
- ret = omap_prefetch_enable(PREFETCH_FIFOTHRESHOLD_MAX, len, 0, info->cs);
- if (ret < 0)
- return ret;
-
- do {
- int i;
-
- cnt = readl(&gpmc_cfg->prefetch_status);
- cnt = PREFETCH_STATUS_FIFO_CNT(cnt);
-
- for (i = 0; i < cnt / 4; i++) {
- *buf++ = readl(CONFIG_SYS_NAND_BASE);
- len -= 4;
- }
- } while (len);
-
- omap_prefetch_reset();
-
- return 0;
-}
-
-static void omap_nand_read_prefetch8(struct mtd_info *mtd, uint8_t *buf, int len)
-{
- int ret;
- uint32_t head, tail;
- struct nand_chip *chip = mtd->priv;
-
- /*
- * If the destination buffer is unaligned, start with reading
- * the overlap byte-wise.
- */
- head = ((uint32_t) buf) % 4;
- if (head) {
- nand_read_buf(mtd, buf, head);
- buf += head;
- len -= head;
- }
-
- /*
- * Only transfer multiples of 4 bytes in a pre-fetched fashion.
- * If there's a residue, care for it byte-wise afterwards.
- */
- tail = len % 4;
-
- ret = __read_prefetch_aligned(chip, (uint32_t *) buf, len - tail);
- if (ret < 0) {
- /* fallback in case the prefetch engine is busy */
- nand_read_buf(mtd, buf, len);
- } else if (tail) {
- buf += len - tail;
- nand_read_buf(mtd, buf, tail);
- }
-}
-#endif /* CONFIG_NAND_OMAP_GPMC_PREFETCH */
-
/**
* omap_read_page_bch - hardware ecc based page read function
* @mtd: mtd info structure
@@ -1011,13 +1021,11 @@ int board_nand_init(struct nand_chip *nand)
if (err)
return err;
- /* TODO: Implement for 16-bit bus width */
- if (nand->options & NAND_BUSWIDTH_16)
- nand->read_buf = nand_read_buf16;
#ifdef CONFIG_NAND_OMAP_GPMC_PREFETCH
- else
- nand->read_buf = omap_nand_read_prefetch8;
+ nand->read_buf = omap_nand_read_prefetch;
#else
+ if (nand->options & NAND_BUSWIDTH_16)
+ nand->read_buf = nand_read_buf16;
else
nand->read_buf = nand_read_buf;
#endif
diff --git a/drivers/mtd/nand/sunxi_nand_spl.c b/drivers/mtd/nand/sunxi_nand_spl.c
deleted file mode 100644
index 75982f54cc..0000000000
--- a/drivers/mtd/nand/sunxi_nand_spl.c
+++ /dev/null
@@ -1,273 +0,0 @@
-/*
- * Copyright (c) 2014, Antmicro Ltd <www.antmicro.com>
- * Copyright (c) 2015, Turtle Solutions <www.turtle-solutions.eu>
- * Copyright (c) 2015, Roy Spliet <rspliet@ultimaker.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * \todo Detect chip parameters (page size, ECC mode, randomisation...)
- */
-
-#include <common.h>
-#include <config.h>
-#include <asm/io.h>
-#include <nand.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/dma.h>
-#include <asm/arch/nand.h>
-
-void
-nand_init(void)
-{
- struct sunxi_ccm_reg * const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
- struct sunxi_nand * const nand = (struct sunxi_nand *)SUNXI_NFC_BASE;
- u32 val;
-
- board_nand_init();
-
- /* "un-gate" NAND clock and clock source
- * This assumes that the clock was already correctly configured by
- * BootROM */
- setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_NAND0));
-#ifdef CONFIG_MACH_SUN9I
- setbits_le32(&ccm->ahb_gate1, (1 << AHB_GATE_OFFSET_DMA));
-#else
- setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_DMA));
-#endif
- setbits_le32(&ccm->nand0_clk_cfg, 0x80000000);
-
- val = readl(&nand->ctl);
- val |= SUNXI_NAND_CTL_RST;
- writel(val, &nand->ctl);
-
- /* Wait until reset pin is deasserted */
- do {
- val = readl(&nand->ctl);
- if (!(val & SUNXI_NAND_CTL_RST))
- break;
- } while (1);
-
- /** \todo Chip select, currently kind of static */
- val = readl(&nand->ctl);
- val &= 0xf0fff0f2;
- val |= SUNXI_NAND_CTL_EN;
- val |= SUNXI_NAND_CTL_PAGE_SIZE(CONFIG_NAND_SUNXI_PAGE_SIZE);
- writel(val, &nand->ctl);
-
- writel(0x100, &nand->timing_ctl);
- writel(0x7ff, &nand->timing_cfg);
-
- /* reset CMD */
- val = SUNXI_NAND_CMD_SEND_CMD1 | SUNXI_NAND_CMD_WAIT_FLAG |
- NAND_CMD_RESET;
- writel(val, &nand->cmd);
- do {
- val = readl(&nand->st);
- if (val & (1<<1))
- break;
- udelay(1000);
- } while (1);
-
- printf("Nand initialised\n");
-}
-
-int
-nand_wait_timeout(u32 *reg, u32 mask, u32 val)
-{
- unsigned long tmo = timer_get_us() + 1000000; /* 1s */
-
- while ((readl(reg) & mask) != val) {
- if (timer_get_us() > tmo)
- return -ETIMEDOUT;
- }
-
- return 0;
-}
-
-/* random seed */
-static const uint16_t random_seed[128] = {
- 0x2b75, 0x0bd0, 0x5ca3, 0x62d1, 0x1c93, 0x07e9, 0x2162, 0x3a72,
- 0x0d67, 0x67f9, 0x1be7, 0x077d, 0x032f, 0x0dac, 0x2716, 0x2436,
- 0x7922, 0x1510, 0x3860, 0x5287, 0x480f, 0x4252, 0x1789, 0x5a2d,
- 0x2a49, 0x5e10, 0x437f, 0x4b4e, 0x2f45, 0x216e, 0x5cb7, 0x7130,
- 0x2a3f, 0x60e4, 0x4dc9, 0x0ef0, 0x0f52, 0x1bb9, 0x6211, 0x7a56,
- 0x226d, 0x4ea7, 0x6f36, 0x3692, 0x38bf, 0x0c62, 0x05eb, 0x4c55,
- 0x60f4, 0x728c, 0x3b6f, 0x2037, 0x7f69, 0x0936, 0x651a, 0x4ceb,
- 0x6218, 0x79f3, 0x383f, 0x18d9, 0x4f05, 0x5c82, 0x2912, 0x6f17,
- 0x6856, 0x5938, 0x1007, 0x61ab, 0x3e7f, 0x57c2, 0x542f, 0x4f62,
- 0x7454, 0x2eac, 0x7739, 0x42d4, 0x2f90, 0x435a, 0x2e52, 0x2064,
- 0x637c, 0x66ad, 0x2c90, 0x0bad, 0x759c, 0x0029, 0x0986, 0x7126,
- 0x1ca7, 0x1605, 0x386a, 0x27f5, 0x1380, 0x6d75, 0x24c3, 0x0f8e,
- 0x2b7a, 0x1418, 0x1fd1, 0x7dc1, 0x2d8e, 0x43af, 0x2267, 0x7da3,
- 0x4e3d, 0x1338, 0x50db, 0x454d, 0x764d, 0x40a3, 0x42e6, 0x262b,
- 0x2d2e, 0x1aea, 0x2e17, 0x173d, 0x3a6e, 0x71bf, 0x25f9, 0x0a5d,
- 0x7c57, 0x0fbe, 0x46ce, 0x4939, 0x6b17, 0x37bb, 0x3e91, 0x76db,
-};
-
-uint32_t ecc_errors = 0;
-
-static void
-nand_config_ecc(struct sunxi_nand *nand, uint32_t page, int syndrome)
-{
- static u8 strength[] = {16, 24, 28, 32, 40, 48, 56, 60, 64};
- int i;
- uint32_t ecc_mode;
- u32 ecc;
- u16 seed = 0;
-
- for (i = 0; i < ARRAY_SIZE(strength); i++) {
- if (CONFIG_NAND_SUNXI_ECC_STRENGTH == strength[i]) {
- ecc_mode = i;
- break;
- }
- }
-
- if (i == ARRAY_SIZE(strength)) {
- printf("ECC strength unsupported\n");
- return;
- }
-
- ecc = SUNXI_NAND_ECC_CTL_ECC_EN |
- SUNXI_NAND_ECC_CTL_PIPELINE |
- SUNXI_NAND_ECC_CTL_RND_EN |
- SUNXI_NAND_ECC_CTL_MODE(ecc_mode);
-
- if (CONFIG_NAND_SUNXI_ECC_STEP == 512)
- ecc |= SUNXI_NAND_ECC_CTL_BS_512B;
-
- if (syndrome)
- seed = 0x4A80;
- else
- seed = random_seed[page % ARRAY_SIZE(random_seed)];
-
- ecc |= SUNXI_NAND_ECC_CTL_RND_SEED(seed);
-
- writel(ecc, &nand->ecc_ctl);
-}
-
-/* read CONFIG_NAND_SUNXI_ECC_STEP bytes from real_addr to temp_buf */
-void
-nand_read_block(struct sunxi_nand *nand, phys_addr_t src, dma_addr_t dst,
- int syndrome)
-{
- struct sunxi_dma * const dma = (struct sunxi_dma *)SUNXI_DMA_BASE;
- struct sunxi_dma_cfg * const dma_cfg = &dma->ddma[0];
-
- uint32_t shift;
- uint32_t page;
- uint32_t addr;
- uint32_t oob_offset;
- uint32_t ecc_bytes;
- u32 val;
- u32 cmd;
-
- page = src / CONFIG_NAND_SUNXI_PAGE_SIZE;
- if (page > 0xFFFF) {
- /* TODO: currently this is not supported */
- printf("Reading from address >= %08X is not allowed.\n",
- 0xFFFF * CONFIG_NAND_SUNXI_PAGE_SIZE);
- return;
- }
-
- shift = src % CONFIG_NAND_SUNXI_PAGE_SIZE;
- writel(0, &nand->ecc_st);
-
- /* ECC_CTL, randomization */
- ecc_bytes = CONFIG_NAND_SUNXI_ECC_STRENGTH *
- fls(CONFIG_NAND_SUNXI_ECC_STEP * 8);
- ecc_bytes = DIV_ROUND_UP(ecc_bytes, 8);
- ecc_bytes += (ecc_bytes & 1); /* Align to 2-bytes */
- ecc_bytes += 4;
-
- nand_config_ecc(nand, page, syndrome);
- if (syndrome) {
- /* shift every 1kB in syndrome */
- shift += (shift / CONFIG_NAND_SUNXI_ECC_STEP) * ecc_bytes;
- oob_offset = CONFIG_NAND_SUNXI_ECC_STEP + shift;
- } else {
- oob_offset = CONFIG_NAND_SUNXI_PAGE_SIZE +
- (shift / CONFIG_NAND_SUNXI_ECC_STEP) * ecc_bytes;
- }
-
- addr = (page << 16) | shift;
-
- /* DMA */
- val = readl(&nand->ctl);
- writel(val | SUNXI_NAND_CTL_RAM_METHOD_DMA, &nand->ctl);
-
- writel(oob_offset, &nand->spare_area);
-
- /* DMAC
- * \todo Separate this into a tidy driver */
- writel(0x0, &dma->irq_en); /* clear dma interrupts */
- writel((uint32_t) &nand->io_data , &dma_cfg->src_addr);
- writel(dst , &dma_cfg->dst_addr);
- writel(0x00007F0F , &dma_cfg->ddma_para);
- writel(CONFIG_NAND_SUNXI_ECC_STEP, &dma_cfg->bc);
-
- val = SUNXI_DMA_CTL_SRC_DRQ(DDMA_SRC_DRQ_NAND) |
- SUNXI_DMA_CTL_MODE_IO |
- SUNXI_DMA_CTL_SRC_DATA_WIDTH_32 |
- SUNXI_DMA_CTL_DST_DRQ(DDMA_DST_DRQ_SDRAM) |
- SUNXI_DMA_CTL_DST_DATA_WIDTH_32 |
- SUNXI_DMA_CTL_TRIGGER;
- writel(val, &dma_cfg->ctl);
-
- writel(0x00E00530, &nand->rcmd_set);
- nand_wait_timeout(&nand->st, SUNXI_NAND_ST_FIFO_FULL, 0);
-
- writel(1 , &nand->block_num);
- writel(addr, &nand->addr_low);
- writel(0 , &nand->addr_high);
-
- /* CMD (PAGE READ) */
- cmd = 0x85E80000;
- cmd |= SUNXI_NAND_CMD_ADDR_CYCLES(CONFIG_NAND_SUNXI_ADDR_CYCLES);
- cmd |= (syndrome ? SUNXI_NAND_CMD_ORDER_SEQ :
- SUNXI_NAND_CMD_ORDER_INTERLEAVE);
- writel(cmd, &nand->cmd);
-
- if(nand_wait_timeout(&nand->st, SUNXI_NAND_ST_DMA_INT,
- SUNXI_NAND_ST_DMA_INT)) {
- printf("NAND timeout reading data\n");
- return;
- }
-
- if(nand_wait_timeout(&dma_cfg->ctl, SUNXI_DMA_CTL_TRIGGER, 0)) {
- printf("NAND timeout reading data\n");
- return;
- }
-
- if (readl(&nand->ecc_st))
- ecc_errors++;
-}
-
-int
-nand_spl_load_image(uint32_t offs, unsigned int size, void *dest)
-{
- struct sunxi_nand * const nand = (struct sunxi_nand *)SUNXI_NFC_BASE;
- dma_addr_t dst_block;
- dma_addr_t dst_end;
- phys_addr_t addr = offs;
-
- dst_end = ((dma_addr_t) dest) + size;
-
- memset((void *)dest, 0x0, size);
- ecc_errors = 0;
- for (dst_block = (dma_addr_t) dest; dst_block < dst_end;
- dst_block += CONFIG_NAND_SUNXI_ECC_STEP,
- addr += CONFIG_NAND_SUNXI_ECC_STEP) {
- /* syndrome read first 4MiB to match Allwinner BootROM */
- nand_read_block(nand, addr, dst_block, addr < 0x400000);
- }
-
- if (ecc_errors)
- printf("Error: %d ECC failures detected\n", ecc_errors);
- return ecc_errors == 0;
-}
-
-void
-nand_deselect(void)
-{}
diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig
index ac6d09f928..40a7981bd5 100644
--- a/drivers/mtd/spi/Kconfig
+++ b/drivers/mtd/spi/Kconfig
@@ -1,3 +1,12 @@
+config SPI_FLASH
+ bool "Enable SPI Flash support"
+ help
+ Enable the legacy SPI flash support. This will include basic
+ standard support for things like probing, read / write, and
+ erasing through the MTD layer.
+
+ If unsure, say N
+
config DM_SPI_FLASH
bool "Enable Driver Model for SPI flash"
depends on DM && DM_SPI
diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index c61b784e17..ed46648aa3 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -15,7 +15,9 @@ endif
#ifndef CONFIG_DM_SPI
obj-$(CONFIG_SPI_FLASH) += sf_probe.o
#endif
+obj-$(CONFIG_SF_DATAFLASH) += sf_dataflash.o
obj-$(CONFIG_CMD_SF) += sf.o
obj-$(CONFIG_SPI_FLASH) += sf_ops.o sf_params.o
+obj-$(CONFIG_SPI_FLASH_MTD) += sf_mtd.o
obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o
obj-$(CONFIG_SPI_M95XXX) += eeprom_m95xxx.o
diff --git a/drivers/mtd/spi/sf_dataflash.c b/drivers/mtd/spi/sf_dataflash.c
new file mode 100644
index 0000000000..d287db8b4c
--- /dev/null
+++ b/drivers/mtd/spi/sf_dataflash.c
@@ -0,0 +1,711 @@
+/*
+ *
+ * Atmel DataFlash probing
+ *
+ * Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc.
+ * Haikun Wang (haikun.wang@freescale.com)
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+*/
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <spi.h>
+#include <spi_flash.h>
+#include <div64.h>
+#include <linux/err.h>
+#include <linux/math64.h>
+
+#include "sf_internal.h"
+
+/*
+ * DataFlash is a kind of SPI flash. Most AT45 chips have two buffers in
+ * each chip, which may be used for double buffered I/O; but this driver
+ * doesn't (yet) use these for any kind of i/o overlap or prefetching.
+ *
+ * Sometimes DataFlash is packaged in MMC-format cards, although the
+ * MMC stack can't (yet?) distinguish between MMC and DataFlash
+ * protocols during enumeration.
+ */
+
+/* reads can bypass the buffers */
+#define OP_READ_CONTINUOUS 0xE8
+#define OP_READ_PAGE 0xD2
+
+/* group B requests can run even while status reports "busy" */
+#define OP_READ_STATUS 0xD7 /* group B */
+
+/* move data between host and buffer */
+#define OP_READ_BUFFER1 0xD4 /* group B */
+#define OP_READ_BUFFER2 0xD6 /* group B */
+#define OP_WRITE_BUFFER1 0x84 /* group B */
+#define OP_WRITE_BUFFER2 0x87 /* group B */
+
+/* erasing flash */
+#define OP_ERASE_PAGE 0x81
+#define OP_ERASE_BLOCK 0x50
+
+/* move data between buffer and flash */
+#define OP_TRANSFER_BUF1 0x53
+#define OP_TRANSFER_BUF2 0x55
+#define OP_MREAD_BUFFER1 0xD4
+#define OP_MREAD_BUFFER2 0xD6
+#define OP_MWERASE_BUFFER1 0x83
+#define OP_MWERASE_BUFFER2 0x86
+#define OP_MWRITE_BUFFER1 0x88 /* sector must be pre-erased */
+#define OP_MWRITE_BUFFER2 0x89 /* sector must be pre-erased */
+
+/* write to buffer, then write-erase to flash */
+#define OP_PROGRAM_VIA_BUF1 0x82
+#define OP_PROGRAM_VIA_BUF2 0x85
+
+/* compare buffer to flash */
+#define OP_COMPARE_BUF1 0x60
+#define OP_COMPARE_BUF2 0x61
+
+/* read flash to buffer, then write-erase to flash */
+#define OP_REWRITE_VIA_BUF1 0x58
+#define OP_REWRITE_VIA_BUF2 0x59
+
+/*
+ * newer chips report JEDEC manufacturer and device IDs; chip
+ * serial number and OTP bits; and per-sector writeprotect.
+ */
+#define OP_READ_ID 0x9F
+#define OP_READ_SECURITY 0x77
+#define OP_WRITE_SECURITY_REVC 0x9A
+#define OP_WRITE_SECURITY 0x9B /* revision D */
+
+
+struct dataflash {
+ uint8_t command[16];
+ unsigned short page_offset; /* offset in flash address */
+};
+
+/*
+ * Return the status of the DataFlash device.
+ */
+static inline int dataflash_status(struct spi_slave *spi)
+{
+ int ret;
+ u8 status;
+ /*
+ * NOTE: at45db321c over 25 MHz wants to write
+ * a dummy byte after the opcode...
+ */
+ ret = spi_flash_cmd(spi, OP_READ_STATUS, &status, 1);
+ return ret ? -EIO : status;
+}
+
+/*
+ * Poll the DataFlash device until it is READY.
+ * This usually takes 5-20 msec or so; more for sector erase.
+ * ready: return > 0
+ */
+static int dataflash_waitready(struct spi_slave *spi)
+{
+ int status;
+ int timeout = 2 * CONFIG_SYS_HZ;
+ int timebase;
+
+ timebase = get_timer(0);
+ do {
+ status = dataflash_status(spi);
+ if (status < 0)
+ status = 0;
+
+ if (status & (1 << 7)) /* RDY/nBSY */
+ return status;
+
+ mdelay(3);
+ } while (get_timer(timebase) < timeout);
+
+ return -ETIME;
+}
+
+/*
+ * Erase pages of flash.
+ */
+static int spi_dataflash_erase(struct udevice *dev, u32 offset, size_t len)
+{
+ struct dataflash *dataflash;
+ struct spi_flash *spi_flash;
+ struct spi_slave *spi;
+ unsigned blocksize;
+ uint8_t *command;
+ uint32_t rem;
+ int status;
+
+ dataflash = dev_get_priv(dev);
+ spi_flash = dev_get_uclass_priv(dev);
+ spi = spi_flash->spi;
+
+ blocksize = spi_flash->page_size << 3;
+
+ memset(dataflash->command, 0 , sizeof(dataflash->command));
+ command = dataflash->command;
+
+ debug("%s: erase addr=0x%x len 0x%x\n", dev->name, offset, len);
+
+ div_u64_rem(len, spi_flash->page_size, &rem);
+ if (rem)
+ return -EINVAL;
+ div_u64_rem(offset, spi_flash->page_size, &rem);
+ if (rem)
+ return -EINVAL;
+
+ status = spi_claim_bus(spi);
+ if (status) {
+ debug("SPI DATAFLASH: unable to claim SPI bus\n");
+ return status;
+ }
+
+ while (len > 0) {
+ unsigned int pageaddr;
+ int do_block;
+ /*
+ * Calculate flash page address; use block erase (for speed) if
+ * we're at a block boundary and need to erase the whole block.
+ */
+ pageaddr = div_u64(offset, spi_flash->page_size);
+ do_block = (pageaddr & 0x7) == 0 && len >= blocksize;
+ pageaddr = pageaddr << dataflash->page_offset;
+
+ command[0] = do_block ? OP_ERASE_BLOCK : OP_ERASE_PAGE;
+ command[1] = (uint8_t)(pageaddr >> 16);
+ command[2] = (uint8_t)(pageaddr >> 8);
+ command[3] = 0;
+
+ debug("%s ERASE %s: (%x) %x %x %x [%d]\n",
+ dev->name, do_block ? "block" : "page",
+ command[0], command[1], command[2], command[3],
+ pageaddr);
+
+ status = spi_flash_cmd_write(spi, command, 4, NULL, 0);
+ if (status < 0) {
+ debug("%s: erase send command error!\n", dev->name);
+ return -EIO;
+ }
+
+ status = dataflash_waitready(spi);
+ if (status < 0) {
+ debug("%s: erase waitready error!\n", dev->name);
+ return status;
+ }
+
+ if (do_block) {
+ offset += blocksize;
+ len -= blocksize;
+ } else {
+ offset += spi_flash->page_size;
+ len -= spi_flash->page_size;
+ }
+ }
+
+ spi_release_bus(spi);
+
+ return 0;
+}
+
+/*
+ * Read from the DataFlash device.
+ * offset : Start offset in flash device
+ * len : Amount to read
+ * buf : Buffer containing the data
+ */
+static int spi_dataflash_read(struct udevice *dev, u32 offset, size_t len,
+ void *buf)
+{
+ struct dataflash *dataflash;
+ struct spi_flash *spi_flash;
+ struct spi_slave *spi;
+ unsigned int addr;
+ uint8_t *command;
+ int status;
+
+ dataflash = dev_get_priv(dev);
+ spi_flash = dev_get_uclass_priv(dev);
+ spi = spi_flash->spi;
+
+ memset(dataflash->command, 0 , sizeof(dataflash->command));
+ command = dataflash->command;
+
+ debug("%s: erase addr=0x%x len 0x%x\n", dev->name, offset, len);
+ debug("READ: (%x) %x %x %x\n",
+ command[0], command[1], command[2], command[3]);
+
+ /* Calculate flash page/byte address */
+ addr = (((unsigned)offset / spi_flash->page_size)
+ << dataflash->page_offset)
+ + ((unsigned)offset % spi_flash->page_size);
+
+ status = spi_claim_bus(spi);
+ if (status) {
+ debug("SPI DATAFLASH: unable to claim SPI bus\n");
+ return status;
+ }
+
+ /*
+ * Continuous read, max clock = f(car) which may be less than
+ * the peak rate available. Some chips support commands with
+ * fewer "don't care" bytes. Both buffers stay unchanged.
+ */
+ command[0] = OP_READ_CONTINUOUS;
+ command[1] = (uint8_t)(addr >> 16);
+ command[2] = (uint8_t)(addr >> 8);
+ command[3] = (uint8_t)(addr >> 0);
+
+ /* plus 4 "don't care" bytes, command len: 4 + 4 "don't care" bytes */
+ status = spi_flash_cmd_read(spi, command, 8, buf, len);
+
+ spi_release_bus(spi);
+
+ return status;
+}
+
+/*
+ * Write to the DataFlash device.
+ * offset : Start offset in flash device
+ * len : Amount to write
+ * buf : Buffer containing the data
+ */
+int spi_dataflash_write(struct udevice *dev, u32 offset, size_t len,
+ const void *buf)
+{
+ struct dataflash *dataflash;
+ struct spi_flash *spi_flash;
+ struct spi_slave *spi;
+ uint8_t *command;
+ unsigned int pageaddr, addr, to, writelen;
+ size_t remaining = len;
+ u_char *writebuf = (u_char *)buf;
+ int status = -EINVAL;
+
+ dataflash = dev_get_priv(dev);
+ spi_flash = dev_get_uclass_priv(dev);
+ spi = spi_flash->spi;
+
+ memset(dataflash->command, 0 , sizeof(dataflash->command));
+ command = dataflash->command;
+
+ debug("%s: write 0x%x..0x%x\n", dev->name, offset, (offset + len));
+
+ pageaddr = ((unsigned)offset / spi_flash->page_size);
+ to = ((unsigned)offset % spi_flash->page_size);
+ if (to + len > spi_flash->page_size)
+ writelen = spi_flash->page_size - to;
+ else
+ writelen = len;
+
+ status = spi_claim_bus(spi);
+ if (status) {
+ debug("SPI DATAFLASH: unable to claim SPI bus\n");
+ return status;
+ }
+
+ while (remaining > 0) {
+ debug("write @ %d:%d len=%d\n", pageaddr, to, writelen);
+
+ /*
+ * REVISIT:
+ * (a) each page in a sector must be rewritten at least
+ * once every 10K sibling erase/program operations.
+ * (b) for pages that are already erased, we could
+ * use WRITE+MWRITE not PROGRAM for ~30% speedup.
+ * (c) WRITE to buffer could be done while waiting for
+ * a previous MWRITE/MWERASE to complete ...
+ * (d) error handling here seems to be mostly missing.
+ *
+ * Two persistent bits per page, plus a per-sector counter,
+ * could support (a) and (b) ... we might consider using
+ * the second half of sector zero, which is just one block,
+ * to track that state. (On AT91, that sector should also
+ * support boot-from-DataFlash.)
+ */
+
+ addr = pageaddr << dataflash->page_offset;
+
+ /* (1) Maybe transfer partial page to Buffer1 */
+ if (writelen != spi_flash->page_size) {
+ command[0] = OP_TRANSFER_BUF1;
+ command[1] = (addr & 0x00FF0000) >> 16;
+ command[2] = (addr & 0x0000FF00) >> 8;
+ command[3] = 0;
+
+ debug("TRANSFER: (%x) %x %x %x\n",
+ command[0], command[1], command[2], command[3]);
+
+ status = spi_flash_cmd_write(spi, command, 4, NULL, 0);
+ if (status < 0) {
+ debug("%s: write(<pagesize) command error!\n",
+ dev->name);
+ return -EIO;
+ }
+
+ status = dataflash_waitready(spi);
+ if (status < 0) {
+ debug("%s: write(<pagesize) waitready error!\n",
+ dev->name);
+ return status;
+ }
+ }
+
+ /* (2) Program full page via Buffer1 */
+ addr += to;
+ command[0] = OP_PROGRAM_VIA_BUF1;
+ command[1] = (addr & 0x00FF0000) >> 16;
+ command[2] = (addr & 0x0000FF00) >> 8;
+ command[3] = (addr & 0x000000FF);
+
+ debug("PROGRAM: (%x) %x %x %x\n",
+ command[0], command[1], command[2], command[3]);
+
+ status = spi_flash_cmd_write(spi, command,
+ 4, writebuf, writelen);
+ if (status < 0) {
+ debug("%s: write send command error!\n", dev->name);
+ return -EIO;
+ }
+
+ status = dataflash_waitready(spi);
+ if (status < 0) {
+ debug("%s: write waitready error!\n", dev->name);
+ return status;
+ }
+
+#ifdef CONFIG_SPI_DATAFLASH_WRITE_VERIFY
+ /* (3) Compare to Buffer1 */
+ addr = pageaddr << dataflash->page_offset;
+ command[0] = OP_COMPARE_BUF1;
+ command[1] = (addr & 0x00FF0000) >> 16;
+ command[2] = (addr & 0x0000FF00) >> 8;
+ command[3] = 0;
+
+ debug("COMPARE: (%x) %x %x %x\n",
+ command[0], command[1], command[2], command[3]);
+
+ status = spi_flash_cmd_write(spi, command,
+ 4, writebuf, writelen);
+ if (status < 0) {
+ debug("%s: write(compare) send command error!\n",
+ dev->name);
+ return -EIO;
+ }
+
+ status = dataflash_waitready(spi);
+
+ /* Check result of the compare operation */
+ if (status & (1 << 6)) {
+ printf("SPI DataFlash: write compare page %u, err %d\n",
+ pageaddr, status);
+ remaining = 0;
+ status = -EIO;
+ break;
+ } else {
+ status = 0;
+ }
+
+#endif /* CONFIG_SPI_DATAFLASH_WRITE_VERIFY */
+ remaining = remaining - writelen;
+ pageaddr++;
+ to = 0;
+ writebuf += writelen;
+
+ if (remaining > spi_flash->page_size)
+ writelen = spi_flash->page_size;
+ else
+ writelen = remaining;
+ }
+
+ spi_release_bus(spi);
+
+ return 0;
+}
+
+static int add_dataflash(struct udevice *dev, char *name, int nr_pages,
+ int pagesize, int pageoffset, char revision)
+{
+ struct spi_flash *spi_flash;
+ struct dataflash *dataflash;
+
+ dataflash = dev_get_priv(dev);
+ spi_flash = dev_get_uclass_priv(dev);
+
+ dataflash->page_offset = pageoffset;
+
+ spi_flash->name = name;
+ spi_flash->page_size = pagesize;
+ spi_flash->size = nr_pages * pagesize;
+ spi_flash->erase_size = pagesize;
+
+#ifndef CONFIG_SPL_BUILD
+ printf("SPI DataFlash: Detected %s with page size ", spi_flash->name);
+ print_size(spi_flash->page_size, ", erase size ");
+ print_size(spi_flash->erase_size, ", total ");
+ print_size(spi_flash->size, "");
+ printf(", revision %c", revision);
+ puts("\n");
+#endif
+
+ return 0;
+}
+
+struct flash_info {
+ char *name;
+
+ /*
+ * JEDEC id has a high byte of zero plus three data bytes:
+ * the manufacturer id, then a two byte device id.
+ */
+ uint32_t jedec_id;
+
+ /* The size listed here is what works with OP_ERASE_PAGE. */
+ unsigned nr_pages;
+ uint16_t pagesize;
+ uint16_t pageoffset;
+
+ uint16_t flags;
+#define SUP_POW2PS 0x0002 /* supports 2^N byte pages */
+#define IS_POW2PS 0x0001 /* uses 2^N byte pages */
+};
+
+static struct flash_info dataflash_data[] = {
+ /*
+ * NOTE: chips with SUP_POW2PS (rev D and up) need two entries,
+ * one with IS_POW2PS and the other without. The entry with the
+ * non-2^N byte page size can't name exact chip revisions without
+ * losing backwards compatibility for cmdlinepart.
+ *
+ * Those two entries have different name spelling format in order to
+ * show their difference obviously.
+ * The upper case refer to the chip isn't in normal 2^N bytes page-size
+ * mode.
+ * The lower case refer to the chip is in normal 2^N bytes page-size
+ * mode.
+ *
+ * These newer chips also support 128-byte security registers (with
+ * 64 bytes one-time-programmable) and software write-protection.
+ */
+ { "AT45DB011B", 0x1f2200, 512, 264, 9, SUP_POW2PS},
+ { "at45db011d", 0x1f2200, 512, 256, 8, SUP_POW2PS | IS_POW2PS},
+
+ { "AT45DB021B", 0x1f2300, 1024, 264, 9, SUP_POW2PS},
+ { "at45db021d", 0x1f2300, 1024, 256, 8, SUP_POW2PS | IS_POW2PS},
+
+ { "AT45DB041x", 0x1f2400, 2048, 264, 9, SUP_POW2PS},
+ { "at45db041d", 0x1f2400, 2048, 256, 8, SUP_POW2PS | IS_POW2PS},
+
+ { "AT45DB081B", 0x1f2500, 4096, 264, 9, SUP_POW2PS},
+ { "at45db081d", 0x1f2500, 4096, 256, 8, SUP_POW2PS | IS_POW2PS},
+
+ { "AT45DB161x", 0x1f2600, 4096, 528, 10, SUP_POW2PS},
+ { "at45db161d", 0x1f2600, 4096, 512, 9, SUP_POW2PS | IS_POW2PS},
+
+ { "AT45DB321x", 0x1f2700, 8192, 528, 10, 0}, /* rev C */
+
+ { "AT45DB321x", 0x1f2701, 8192, 528, 10, SUP_POW2PS},
+ { "at45db321d", 0x1f2701, 8192, 512, 9, SUP_POW2PS | IS_POW2PS},
+
+ { "AT45DB642x", 0x1f2800, 8192, 1056, 11, SUP_POW2PS},
+ { "at45db642d", 0x1f2800, 8192, 1024, 10, SUP_POW2PS | IS_POW2PS},
+};
+
+static struct flash_info *jedec_probe(struct spi_slave *spi, u8 *id)
+{
+ int tmp;
+ uint32_t jedec;
+ struct flash_info *info;
+ int status;
+
+ /*
+ * JEDEC also defines an optional "extended device information"
+ * string for after vendor-specific data, after the three bytes
+ * we use here. Supporting some chips might require using it.
+ *
+ * If the vendor ID isn't Atmel's (0x1f), assume this call failed.
+ * That's not an error; only rev C and newer chips handle it, and
+ * only Atmel sells these chips.
+ */
+ if (id[0] != 0x1f)
+ return NULL;
+
+ jedec = id[0];
+ jedec = jedec << 8;
+ jedec |= id[1];
+ jedec = jedec << 8;
+ jedec |= id[2];
+
+ for (tmp = 0, info = dataflash_data;
+ tmp < ARRAY_SIZE(dataflash_data);
+ tmp++, info++) {
+ if (info->jedec_id == jedec) {
+ if (info->flags & SUP_POW2PS) {
+ status = dataflash_status(spi);
+ if (status < 0) {
+ debug("SPI DataFlash: status error %d\n",
+ status);
+ return NULL;
+ }
+ if (status & 0x1) {
+ if (info->flags & IS_POW2PS)
+ return info;
+ } else {
+ if (!(info->flags & IS_POW2PS))
+ return info;
+ }
+ } else {
+ return info;
+ }
+ }
+ }
+
+ /*
+ * Treat other chips as errors ... we won't know the right page
+ * size (it might be binary) even when we can tell which density
+ * class is involved (legacy chip id scheme).
+ */
+ printf("SPI DataFlash: Unsupported flash IDs: ");
+ printf("manuf %02x, jedec %04x, ext_jedec %04x\n",
+ id[0], jedec, id[3] << 8 | id[4]);
+ return NULL;
+}
+
+/*
+ * Detect and initialize DataFlash device, using JEDEC IDs on newer chips
+ * or else the ID code embedded in the status bits:
+ *
+ * Device Density ID code #Pages PageSize Offset
+ * AT45DB011B 1Mbit (128K) xx0011xx (0x0c) 512 264 9
+ * AT45DB021B 2Mbit (256K) xx0101xx (0x14) 1024 264 9
+ * AT45DB041B 4Mbit (512K) xx0111xx (0x1c) 2048 264 9
+ * AT45DB081B 8Mbit (1M) xx1001xx (0x24) 4096 264 9
+ * AT45DB0161B 16Mbit (2M) xx1011xx (0x2c) 4096 528 10
+ * AT45DB0321B 32Mbit (4M) xx1101xx (0x34) 8192 528 10
+ * AT45DB0642 64Mbit (8M) xx111xxx (0x3c) 8192 1056 11
+ * AT45DB1282 128Mbit (16M) xx0100xx (0x10) 16384 1056 11
+ */
+static int spi_dataflash_probe(struct udevice *dev)
+{
+ struct spi_slave *spi = dev_get_parentdata(dev);
+ struct spi_flash *spi_flash;
+ struct flash_info *info;
+ u8 idcode[5];
+ int ret, status = 0;
+
+ spi_flash = dev_get_uclass_priv(dev);
+ spi_flash->dev = dev;
+
+ ret = spi_claim_bus(spi);
+ if (ret)
+ return ret;
+
+ ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode));
+ if (ret) {
+ printf("SPI DataFlash: Failed to get idcodes\n");
+ goto err_read_cmd;
+ }
+
+ /*
+ * Try to detect dataflash by JEDEC ID.
+ * If it succeeds we know we have either a C or D part.
+ * D will support power of 2 pagesize option.
+ * Both support the security register, though with different
+ * write procedures.
+ */
+ info = jedec_probe(spi, idcode);
+ if (info != NULL)
+ add_dataflash(dev, info->name, info->nr_pages,
+ info->pagesize, info->pageoffset,
+ (info->flags & SUP_POW2PS) ? 'd' : 'c');
+ else {
+ /*
+ * Older chips support only legacy commands, identifing
+ * capacity using bits in the status byte.
+ */
+ status = dataflash_status(spi);
+ if (status <= 0 || status == 0xff) {
+ printf("SPI DataFlash: read status error %d\n", status);
+ if (status == 0 || status == 0xff)
+ status = -ENODEV;
+ goto err_read_cmd;
+ }
+ /*
+ * if there's a device there, assume it's dataflash.
+ * board setup should have set spi->max_speed_max to
+ * match f(car) for continuous reads, mode 0 or 3.
+ */
+ switch (status & 0x3c) {
+ case 0x0c: /* 0 0 1 1 x x */
+ status = add_dataflash(dev, "AT45DB011B",
+ 512, 264, 9, 0);
+ break;
+ case 0x14: /* 0 1 0 1 x x */
+ status = add_dataflash(dev, "AT45DB021B",
+ 1024, 264, 9, 0);
+ break;
+ case 0x1c: /* 0 1 1 1 x x */
+ status = add_dataflash(dev, "AT45DB041x",
+ 2048, 264, 9, 0);
+ break;
+ case 0x24: /* 1 0 0 1 x x */
+ status = add_dataflash(dev, "AT45DB081B",
+ 4096, 264, 9, 0);
+ break;
+ case 0x2c: /* 1 0 1 1 x x */
+ status = add_dataflash(dev, "AT45DB161x",
+ 4096, 528, 10, 0);
+ break;
+ case 0x34: /* 1 1 0 1 x x */
+ status = add_dataflash(dev, "AT45DB321x",
+ 8192, 528, 10, 0);
+ break;
+ case 0x38: /* 1 1 1 x x x */
+ case 0x3c:
+ status = add_dataflash(dev, "AT45DB642x",
+ 8192, 1056, 11, 0);
+ break;
+ /* obsolete AT45DB1282 not (yet?) supported */
+ default:
+ dev_info(&spi->dev, "unsupported device (%x)\n",
+ status & 0x3c);
+ status = -ENODEV;
+ goto err_read_cmd;
+ }
+ }
+
+ /* Assign spi data */
+ spi_flash->spi = spi;
+ spi_flash->memory_map = spi->memory_map;
+ spi_flash->dual_flash = spi->option;
+
+ spi_release_bus(spi);
+
+ return 0;
+
+err_read_cmd:
+ spi_release_bus(spi);
+
+ return status;
+}
+
+static const struct dm_spi_flash_ops spi_dataflash_ops = {
+ .read = spi_dataflash_read,
+ .write = spi_dataflash_write,
+ .erase = spi_dataflash_erase,
+};
+
+static const struct udevice_id spi_dataflash_ids[] = {
+ { .compatible = "atmel,at45", },
+ { .compatible = "atmel,dataflash", },
+ { }
+};
+
+U_BOOT_DRIVER(spi_dataflash) = {
+ .name = "spi_dataflash",
+ .id = UCLASS_SPI_FLASH,
+ .of_match = spi_dataflash_ids,
+ .probe = spi_dataflash_probe,
+ .priv_auto_alloc_size = sizeof(struct dataflash),
+ .ops = &spi_dataflash_ops,
+};
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 4158e13322..81eea8ce9d 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -218,4 +218,9 @@ int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
size_t len, void *data);
+#ifdef CONFIG_SPI_FLASH_MTD
+int spi_flash_mtd_register(struct spi_flash *flash);
+void spi_flash_mtd_unregister(void);
+#endif
+
#endif /* _SF_INTERNAL_H_ */
diff --git a/drivers/mtd/spi/sf_mtd.c b/drivers/mtd/spi/sf_mtd.c
new file mode 100644
index 0000000000..0b9cb62261
--- /dev/null
+++ b/drivers/mtd/spi/sf_mtd.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (C) 2012-2014 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/errno.h>
+#include <linux/mtd/mtd.h>
+#include <spi_flash.h>
+
+static struct mtd_info sf_mtd_info;
+static char sf_mtd_name[8];
+
+static int spi_flash_mtd_erase(struct mtd_info *mtd, struct erase_info *instr)
+{
+ struct spi_flash *flash = mtd->priv;
+ int err;
+
+ instr->state = MTD_ERASING;
+
+ err = spi_flash_erase(flash, instr->addr, instr->len);
+ if (err) {
+ instr->state = MTD_ERASE_FAILED;
+ instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
+ return -EIO;
+ }
+
+ instr->state = MTD_ERASE_DONE;
+ mtd_erase_callback(instr);
+
+ return 0;
+}
+
+static int spi_flash_mtd_read(struct mtd_info *mtd, loff_t from, size_t len,
+ size_t *retlen, u_char *buf)
+{
+ struct spi_flash *flash = mtd->priv;
+ int err;
+
+ err = spi_flash_read(flash, from, len, buf);
+ if (!err)
+ *retlen = len;
+
+ return err;
+}
+
+static int spi_flash_mtd_write(struct mtd_info *mtd, loff_t to, size_t len,
+ size_t *retlen, const u_char *buf)
+{
+ struct spi_flash *flash = mtd->priv;
+ int err;
+
+ err = spi_flash_write(flash, to, len, buf);
+ if (!err)
+ *retlen = len;
+
+ return err;
+}
+
+static void spi_flash_mtd_sync(struct mtd_info *mtd)
+{
+}
+
+static int spi_flash_mtd_number(void)
+{
+#ifdef CONFIG_SYS_MAX_FLASH_BANKS
+ return CONFIG_SYS_MAX_FLASH_BANKS;
+#else
+ return 0;
+#endif
+}
+
+int spi_flash_mtd_register(struct spi_flash *flash)
+{
+ memset(&sf_mtd_info, 0, sizeof(sf_mtd_info));
+ sprintf(sf_mtd_name, "nor%d", spi_flash_mtd_number());
+
+ sf_mtd_info.name = sf_mtd_name;
+ sf_mtd_info.type = MTD_NORFLASH;
+ sf_mtd_info.flags = MTD_CAP_NORFLASH;
+ sf_mtd_info.writesize = 1;
+ sf_mtd_info.writebufsize = flash->page_size;
+
+ sf_mtd_info._erase = spi_flash_mtd_erase;
+ sf_mtd_info._read = spi_flash_mtd_read;
+ sf_mtd_info._write = spi_flash_mtd_write;
+ sf_mtd_info._sync = spi_flash_mtd_sync;
+
+ sf_mtd_info.size = flash->size;
+ sf_mtd_info.priv = flash;
+
+ /* Only uniform flash devices for now */
+ sf_mtd_info.numeraseregions = 0;
+ sf_mtd_info.erasesize = flash->sector_size;
+
+ return add_mtd_device(&sf_mtd_info);
+}
+
+void spi_flash_mtd_unregister(void)
+{
+ del_mtd_device(&sf_mtd_info);
+}
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 201471c392..e0283dc82c 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -372,11 +372,9 @@ int spi_flash_probe_slave(struct spi_slave *spi, struct spi_flash *flash)
puts(" Full access #define CONFIG_SPI_FLASH_BAR\n");
}
#endif
-
- /* Release spi bus */
- spi_release_bus(spi);
-
- return 0;
+#ifdef CONFIG_SPI_FLASH_MTD
+ ret = spi_flash_mtd_register(flash);
+#endif
err_read_id:
spi_release_bus(spi);
@@ -430,6 +428,9 @@ struct spi_flash *spi_flash_probe_fdt(const void *blob, int slave_node,
void spi_flash_free(struct spi_flash *flash)
{
+#ifdef CONFIG_SPI_FLASH_MTD
+ spi_flash_mtd_unregister();
+#endif
spi_free_slave(flash->spi);
free(flash);
}
generated by cgit v1.2.3 (git 2.0.4) at 2024-07-07 18:14:27 +0000