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-rw-r--r--drivers/mtd/cfi_flash.c32
-rw-r--r--drivers/mtd/nand/raw/fsl_ifc_nand.c4
-rw-r--r--drivers/mtd/nand/raw/fsl_ifc_spl.c8
-rw-r--r--drivers/mtd/nand/raw/lpc32xx_nand_mlc.c6
-rw-r--r--drivers/mtd/onenand/onenand_spl.c6
-rw-r--r--drivers/mtd/onenand/onenand_uboot.c2
-rw-r--r--drivers/mtd/spi/fsl_espi_spl.c12
-rw-r--r--drivers/mtd/stm32_flash.c2
8 files changed, 36 insertions, 36 deletions
diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
index d34d8ee976..c1cdd2cbc3 100644
--- a/drivers/mtd/cfi_flash.c
+++ b/drivers/mtd/cfi_flash.c
@@ -53,7 +53,7 @@
* AMD/Spansion Application Note: Migration from Single-byte to Three-byte
* Device IDs, Publication Number 25538 Revision A, November 8, 2001
*
- * Define CONFIG_SYS_WRITE_SWAPPED_DATA, if you have to swap the Bytes between
+ * Define CFG_SYS_WRITE_SWAPPED_DATA, if you have to swap the Bytes between
* reading and writing ... (yes there is such a Hardware).
*/
@@ -119,14 +119,14 @@ phys_addr_t cfi_flash_bank_addr(int i)
#else
__weak phys_addr_t cfi_flash_bank_addr(int i)
{
- return ((phys_addr_t [])CONFIG_SYS_FLASH_BANKS_LIST)[i];
+ return ((phys_addr_t [])CFG_SYS_FLASH_BANKS_LIST)[i];
}
#endif
__weak unsigned long cfi_flash_bank_size(int i)
{
-#ifdef CONFIG_SYS_FLASH_BANKS_SIZES
- return ((unsigned long [])CONFIG_SYS_FLASH_BANKS_SIZES)[i];
+#ifdef CFG_SYS_FLASH_BANKS_SIZES
+ return ((unsigned long [])CFG_SYS_FLASH_BANKS_SIZES)[i];
#else
return 0;
#endif
@@ -178,7 +178,7 @@ __maybe_weak u64 flash_read64(void *addr)
*/
#if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || \
(defined(CONFIG_SYS_MONITOR_BASE) && \
- (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE))
+ (CONFIG_SYS_MONITOR_BASE >= CFG_SYS_FLASH_BASE))
static flash_info_t *flash_get_info(ulong base)
{
int i;
@@ -227,7 +227,7 @@ static void flash_make_cmd(flash_info_t *info, u32 cmd, void *cmdbuf)
int i;
int cword_offset;
int cp_offset;
-#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
+#if defined(__LITTLE_ENDIAN) || defined(CFG_SYS_WRITE_SWAPPED_DATA)
u32 cmd_le = cpu_to_le32(cmd);
#endif
uchar val;
@@ -235,7 +235,7 @@ static void flash_make_cmd(flash_info_t *info, u32 cmd, void *cmdbuf)
for (i = info->portwidth; i > 0; i--) {
cword_offset = (info->portwidth - i) % info->chipwidth;
-#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
+#if defined(__LITTLE_ENDIAN) || defined(CFG_SYS_WRITE_SWAPPED_DATA)
cp_offset = info->portwidth - i;
val = *((uchar *)&cmd_le + cword_offset);
#else
@@ -292,7 +292,7 @@ static inline uchar flash_read_uchar(flash_info_t *info, uint offset)
uchar retval;
cp = flash_map(info, 0, offset);
-#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
+#if defined(__LITTLE_ENDIAN) || defined(CFG_SYS_WRITE_SWAPPED_DATA)
retval = flash_read8(cp);
#else
retval = flash_read8(cp + info->portwidth - 1);
@@ -335,7 +335,7 @@ static ulong flash_read_long (flash_info_t *info, flash_sect_t sect,
for (x = 0; x < 4 * info->portwidth; x++)
debug("addr[%x] = 0x%x\n", x, flash_read8(addr + x));
#endif
-#if defined(__LITTLE_ENDIAN) || defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
+#if defined(__LITTLE_ENDIAN) || defined(CFG_SYS_WRITE_SWAPPED_DATA)
retval = ((flash_read8(addr) << 16) |
(flash_read8(addr + info->portwidth) << 24) |
(flash_read8(addr + 2 * info->portwidth)) |
@@ -580,7 +580,7 @@ static int flash_status_check(flash_info_t *info, flash_sect_t sector,
#endif
/* Wait for command completion */
-#ifdef CONFIG_SYS_LOW_RES_TIMER
+#ifdef CFG_SYS_LOW_RES_TIMER
reset_timer();
#endif
start = get_timer(0);
@@ -673,7 +673,7 @@ static int flash_status_poll(flash_info_t *info, void *src, void *dst,
#endif
/* Wait for command completion */
-#ifdef CONFIG_SYS_LOW_RES_TIMER
+#ifdef CFG_SYS_LOW_RES_TIMER
reset_timer();
#endif
start = get_timer(0);
@@ -713,7 +713,7 @@ static int flash_status_poll(flash_info_t *info, void *src, void *dst,
*/
static void flash_add_byte(flash_info_t *info, cfiword_t *cword, uchar c)
{
-#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
+#if defined(__LITTLE_ENDIAN) && !defined(CFG_SYS_WRITE_SWAPPED_DATA)
unsigned short w;
unsigned int l;
unsigned long long ll;
@@ -724,7 +724,7 @@ static void flash_add_byte(flash_info_t *info, cfiword_t *cword, uchar c)
cword->w8 = c;
break;
case FLASH_CFI_16BIT:
-#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
+#if defined(__LITTLE_ENDIAN) && !defined(CFG_SYS_WRITE_SWAPPED_DATA)
w = c;
w <<= 8;
cword->w16 = (cword->w16 >> 8) | w;
@@ -733,7 +733,7 @@ static void flash_add_byte(flash_info_t *info, cfiword_t *cword, uchar c)
#endif
break;
case FLASH_CFI_32BIT:
-#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
+#if defined(__LITTLE_ENDIAN) && !defined(CFG_SYS_WRITE_SWAPPED_DATA)
l = c;
l <<= 24;
cword->w32 = (cword->w32 >> 8) | l;
@@ -742,7 +742,7 @@ static void flash_add_byte(flash_info_t *info, cfiword_t *cword, uchar c)
#endif
break;
case FLASH_CFI_64BIT:
-#if defined(__LITTLE_ENDIAN) && !defined(CONFIG_SYS_WRITE_SWAPPED_DATA)
+#if defined(__LITTLE_ENDIAN) && !defined(CFG_SYS_WRITE_SWAPPED_DATA)
ll = c;
ll <<= 56;
cword->w64 = (cword->w64 >> 8) | ll;
@@ -2359,7 +2359,7 @@ static void flash_protect_default(void)
/* Monitor protection ON by default */
#if defined(CONFIG_SYS_MONITOR_BASE) && \
- (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) && \
+ (CONFIG_SYS_MONITOR_BASE >= CFG_SYS_FLASH_BASE) && \
(!defined(CONFIG_MONITOR_IS_IN_RAM))
flash_protect(FLAG_PROTECT_SET,
CONFIG_SYS_MONITOR_BASE,
diff --git a/drivers/mtd/nand/raw/fsl_ifc_nand.c b/drivers/mtd/nand/raw/fsl_ifc_nand.c
index 59de325640..18abd75441 100644
--- a/drivers/mtd/nand/raw/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/raw/fsl_ifc_nand.c
@@ -780,10 +780,10 @@ static void fsl_ifc_ctrl_init(void)
ver = ifc_in32(&ifc_ctrl->regs.gregs->ifc_rev);
if (ver >= FSL_IFC_V2_0_0)
ifc_ctrl->regs.rregs =
- (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET;
+ (void *)CFG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET;
else
ifc_ctrl->regs.rregs =
- (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET;
+ (void *)CFG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET;
/* clear event registers */
ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.nand_evter_stat, ~0U);
diff --git a/drivers/mtd/nand/raw/fsl_ifc_spl.c b/drivers/mtd/nand/raw/fsl_ifc_spl.c
index 7d4b77dd11..3b464ce10c 100644
--- a/drivers/mtd/nand/raw/fsl_ifc_spl.c
+++ b/drivers/mtd/nand/raw/fsl_ifc_spl.c
@@ -54,14 +54,14 @@ static inline int check_read_ecc(uchar *buf, u32 *eccstat,
static inline struct fsl_ifc_runtime *runtime_regs_address(void)
{
- struct fsl_ifc regs = {(void *)CONFIG_SYS_IFC_ADDR, NULL};
+ struct fsl_ifc regs = {(void *)CFG_SYS_IFC_ADDR, NULL};
int ver = 0;
ver = ifc_in32(&regs.gregs->ifc_rev);
if (ver >= FSL_IFC_V2_0_0)
- regs.rregs = (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET;
+ regs.rregs = (void *)CFG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET;
else
- regs.rregs = (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET;
+ regs.rregs = (void *)CFG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET;
return regs.rregs;
}
@@ -108,7 +108,7 @@ static inline int bad_block(uchar *marker, int port_size)
int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
{
- struct fsl_ifc_fcm *gregs = (void *)CONFIG_SYS_IFC_ADDR;
+ struct fsl_ifc_fcm *gregs = (void *)CFG_SYS_IFC_ADDR;
struct fsl_ifc_runtime *ifc = NULL;
uchar *buf = (uchar *)CFG_SYS_NAND_BASE;
int page_size;
diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c
index 5bc5301d63..a884c65d18 100644
--- a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c
+++ b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c
@@ -84,8 +84,8 @@ struct lpc32xx_nand_mlc_registers {
static struct lpc32xx_nand_mlc_registers __iomem *lpc32xx_nand_mlc_registers
= (struct lpc32xx_nand_mlc_registers __iomem *)MLC_NAND_BASE;
-#if !defined(CONFIG_SYS_MAX_NAND_CHIPS)
-#define CONFIG_SYS_MAX_NAND_CHIPS 1
+#if !defined(CFG_SYS_MAX_NAND_CHIPS)
+#define CFG_SYS_MAX_NAND_CHIPS 1
#endif
#define clkdiv(v, w, o) (((1+(clk/v)) & w) << o)
@@ -586,7 +586,7 @@ void board_nand_init(void)
lpc32xx_nand_init();
/* identify chip */
- ret = nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_CHIPS, NULL);
+ ret = nand_scan_ident(mtd, CFG_SYS_MAX_NAND_CHIPS, NULL);
if (ret) {
pr_err("nand_scan_ident returned %i", ret);
return;
diff --git a/drivers/mtd/onenand/onenand_spl.c b/drivers/mtd/onenand/onenand_spl.c
index ab6f1a8be3..2699958a5d 100644
--- a/drivers/mtd/onenand/onenand_spl.c
+++ b/drivers/mtd/onenand/onenand_spl.c
@@ -49,12 +49,12 @@ static inline int onenand_bufferram_address(int block)
static inline uint16_t onenand_readw(uint32_t addr)
{
- return readw(CONFIG_SYS_ONENAND_BASE + addr);
+ return readw(CFG_SYS_ONENAND_BASE + addr);
}
static inline void onenand_writew(uint16_t value, uint32_t addr)
{
- writew(value, CONFIG_SYS_ONENAND_BASE + addr);
+ writew(value, CFG_SYS_ONENAND_BASE + addr);
}
static enum onenand_spl_pagesize onenand_spl_get_geometry(void)
@@ -82,7 +82,7 @@ static enum onenand_spl_pagesize onenand_spl_get_geometry(void)
static int onenand_spl_read_page(uint32_t block, uint32_t page, uint32_t *buf,
enum onenand_spl_pagesize pagesize)
{
- const uint32_t addr = CONFIG_SYS_ONENAND_BASE + ONENAND_DATARAM;
+ const uint32_t addr = CFG_SYS_ONENAND_BASE + ONENAND_DATARAM;
uint32_t offset;
onenand_writew(onenand_block_address(block),
diff --git a/drivers/mtd/onenand/onenand_uboot.c b/drivers/mtd/onenand/onenand_uboot.c
index 3a8c7b867e..04791df69b 100644
--- a/drivers/mtd/onenand/onenand_uboot.c
+++ b/drivers/mtd/onenand/onenand_uboot.c
@@ -35,7 +35,7 @@ void onenand_init(void)
/* It's used for some board init required */
err = onenand_board_init(&onenand_mtd);
#else
- onenand_chip.base = (void *) CONFIG_SYS_ONENAND_BASE;
+ onenand_chip.base = (void *) CFG_SYS_ONENAND_BASE;
#endif
if (!err && !(onenand_scan(&onenand_mtd, 1))) {
diff --git a/drivers/mtd/spi/fsl_espi_spl.c b/drivers/mtd/spi/fsl_espi_spl.c
index 5c41d7558c..dfc35d6eab 100644
--- a/drivers/mtd/spi/fsl_espi_spl.c
+++ b/drivers/mtd/spi/fsl_espi_spl.c
@@ -49,8 +49,8 @@ void fsl_spi_boot(void)
}
#ifdef CONFIG_FSL_CORENET
- offset = CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS;
- code_len = CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE;
+ offset = CFG_SYS_SPI_FLASH_U_BOOT_OFFS;
+ code_len = CFG_SYS_SPI_FLASH_U_BOOT_SIZE;
#else
/*
* Load U-Boot image from SPI flash into RAM
@@ -66,7 +66,7 @@ void fsl_spi_boot(void)
flash->page_size, (void *)buf);
offset = *(u32 *)(buf + ESPI_BOOT_IMAGE_ADDR);
/* Skip spl code */
- offset += CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS;
+ offset += CFG_SYS_SPI_FLASH_U_BOOT_OFFS;
/* Get the code size from offset 0x48 */
code_len = *(u32 *)(buf + ESPI_BOOT_IMAGE_SIZE);
/* Skip spl code */
@@ -76,7 +76,7 @@ void fsl_spi_boot(void)
printf("Loading second stage boot loader ");
while (copy_len <= code_len) {
spi_flash_read(flash, offset + copy_len, 0x2000,
- (void *)(CONFIG_SYS_SPI_FLASH_U_BOOT_DST
+ (void *)(CFG_SYS_SPI_FLASH_U_BOOT_DST
+ copy_len));
copy_len = copy_len + 0x2000;
putc('.');
@@ -85,7 +85,7 @@ void fsl_spi_boot(void)
/*
* Jump to U-Boot image
*/
- flush_cache(CONFIG_SYS_SPI_FLASH_U_BOOT_DST, code_len);
- uboot = (void *)CONFIG_SYS_SPI_FLASH_U_BOOT_START;
+ flush_cache(CFG_SYS_SPI_FLASH_U_BOOT_DST, code_len);
+ uboot = (void *)CFG_SYS_SPI_FLASH_U_BOOT_START;
(*uboot)();
}
diff --git a/drivers/mtd/stm32_flash.c b/drivers/mtd/stm32_flash.c
index 95afa2d6bc..4523344ba6 100644
--- a/drivers/mtd/stm32_flash.c
+++ b/drivers/mtd/stm32_flash.c
@@ -39,7 +39,7 @@ unsigned long flash_init(void)
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
flash_info[i].flash_id = FLASH_STM32;
flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- flash_info[i].start[0] = CONFIG_SYS_FLASH_BASE + (i << 20);
+ flash_info[i].start[0] = CFG_SYS_FLASH_BASE + (i << 20);
flash_info[i].size = sect_sz_kb[0];
for (j = 1; j < CONFIG_SYS_MAX_FLASH_SECT; j++) {
flash_info[i].start[j] = flash_info[i].start[j - 1]
generated by cgit v1.2.3 (git 2.0.4) at 2024-07-05 11:45:40 +0000