3 files changed, 44 insertions, 6 deletions

diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c
index 71f5027889f..d3b71a50adc 100644
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -2601,6 +2601,7 @@ static const struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
 						  int *maf_id, int *dev_id,
 						  const struct nand_flash_dev *type)
 {
+	const char *name;
 	int i, maf_idx;
 	u8 id_data[8];
 	int ret;
@@ -2848,14 +2849,14 @@ ident_done:
 		chip->cmdfunc = nand_command_lp;
 
 	/* TODO onfi flash name */
-	MTDDEBUG (MTD_DEBUG_LEVEL0, "NAND device: Manufacturer ID:"
-		" 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, *dev_id,
-		nand_manuf_ids[maf_idx].name,
+	name = type->name;
 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
-		chip->onfi_version ? chip->onfi_params.model : type->name);
-#else
-		type->name);
+	if (chip->onfi_version)
+		name = chip->onfi_params.model;
 #endif
+	MTDDEBUG(MTD_DEBUG_LEVEL0, "NAND device: Manufacturer ID:"
+		 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, *dev_id,
+		 nand_manuf_ids[maf_idx].name, name);
 
 	return type;
 }
diff --git a/drivers/mtd/nand/nand_ecc.c b/drivers/mtd/nand/nand_ecc.c
index 81f0e0812b1..097cf625b8e 100644
--- a/drivers/mtd/nand/nand_ecc.c
+++ b/drivers/mtd/nand/nand_ecc.c
@@ -39,6 +39,7 @@
 
 #include <asm/errno.h>
 #include <linux/mtd/mtd.h>
+#include <linux/mtd/nand_ecc.h>
 
 /* The PPC4xx NDFC uses Smart Media (SMC) bytes order */
 #ifdef CONFIG_NAND_NDFC
diff --git a/drivers/mtd/nand/tegra_nand.c b/drivers/mtd/nand/tegra_nand.c
index 5408c51ffb5..4d94cc6f562 100644
--- a/drivers/mtd/nand/tegra_nand.c
+++ b/drivers/mtd/nand/tegra_nand.c
@@ -219,6 +219,34 @@ static uint8_t read_byte(struct mtd_info *mtd)
 }
 
 /**
+ * Read len bytes from the chip into a buffer
+ *
+ * @param mtd	MTD device structure
+ * @param buf	buffer to store data to
+ * @param len	number of bytes to read
+ *
+ * Read function for 8bit bus-width
+ */
+static void read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+	int i, s;
+	unsigned int reg;
+	struct nand_chip *chip = mtd->priv;
+	struct nand_drv *info = (struct nand_drv *)chip->priv;
+
+	for (i = 0; i < len; i += 4) {
+		s = (len - i) > 4 ? 4 : len - i;
+		writel(CMD_PIO | CMD_RX | CMD_A_VALID | CMD_CE0 |
+			((s - 1) << CMD_TRANS_SIZE_SHIFT) | CMD_GO,
+			&info->reg->command);
+		if (!nand_waitfor_cmd_completion(info->reg))
+			puts("Command timeout during read_buf\n");
+		reg = readl(&info->reg->resp);
+		memcpy(buf + i, &reg, s);
+	}
+}
+
+/**
  * Check NAND status to see if it is ready or not
  *
  * @param mtd	MTD device structure
@@ -317,6 +345,7 @@ static void nand_command(struct mtd_info *mtd, unsigned int command,
 	switch (command) {
 	case NAND_CMD_READID:
 		writel(NAND_CMD_READID, &info->reg->cmd_reg1);
+		writel(column & 0xFF, &info->reg->addr_reg1);
 		writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_PIO
 			| CMD_RX |
 			((4 - 1) << CMD_TRANS_SIZE_SHIFT)
@@ -324,6 +353,12 @@ static void nand_command(struct mtd_info *mtd, unsigned int command,
 			&info->reg->command);
 		info->pio_byte_index = 0;
 		break;
+	case NAND_CMD_PARAM:
+		writel(NAND_CMD_PARAM, &info->reg->cmd_reg1);
+		writel(column & 0xFF, &info->reg->addr_reg1);
+		writel(CMD_GO | CMD_CLE | CMD_ALE | CMD_CE0,
+			&info->reg->command);
+		break;
 	case NAND_CMD_READ0:
 		writel(NAND_CMD_READ0, &info->reg->cmd_reg1);
 		writel(NAND_CMD_READSTART, &info->reg->cmd_reg2);
@@ -976,6 +1011,7 @@ int tegra_nand_init(struct nand_chip *nand, int devnum)
 	nand->options = LP_OPTIONS;
 	nand->cmdfunc = nand_command;
 	nand->read_byte = read_byte;
+	nand->read_buf = read_buf;
 	nand->ecc.read_page = nand_read_page_hwecc;
 	nand->ecc.write_page = nand_write_page_hwecc;
 	nand->ecc.read_page_raw = nand_read_page_raw;