diff options
Diffstat (limited to 'doc')
35 files changed, 296 insertions, 116 deletions
diff --git a/doc/README.POST b/doc/README.POST index 1d1c25bdf9..1366f95c66 100644 --- a/doc/README.POST +++ b/doc/README.POST @@ -242,11 +242,11 @@ storage server and etc. All POST-related code will be #ifdef'ed with the CONFIG_POST macro. This macro will be defined in the config_<board>.h file for those -boards that need POST. The CONFIG_POST macro will contain the list of +boards that need POST. The CFG_POST macro will contain the list of POST tests for the board. The macro will have the format of array composed of post_test structures: -#define CONFIG_POST \ +#define CFG_POST \ { "On-board peripherals test", "board", \ " This test performs full check-up of the " \ @@ -257,7 +257,7 @@ composed of post_test structures: A new file, post.h, will be created in the include/ directory. This file will contain common POST declarations and will define a set of -macros that will be reused for defining CONFIG_POST. As an example, +macros that will be reused for defining CFG_POST. As an example, the following macro may be defined: #define POST_CACHE \ @@ -649,15 +649,15 @@ not need any modifications for porting them to another board/CPU. For verifying the I2C bus, a full I2C bus scanning will be performed using the i2c_probe() routine. If a board defines -CONFIG_SYS_POST_I2C_ADDRS the I2C test will pass if all devices -listed in CONFIG_SYS_POST_I2C_ADDRS are found, and no additional -devices are detected. If CONFIG_SYS_POST_I2C_ADDRS is not defined +CFG_SYS_POST_I2C_ADDRS the I2C test will pass if all devices +listed in CFG_SYS_POST_I2C_ADDRS are found, and no additional +devices are detected. If CFG_SYS_POST_I2C_ADDRS is not defined the test will pass if any I2C device is found. -The CONFIG_SYS_POST_I2C_IGNORES define can be used to list I2C +The CFG_SYS_POST_I2C_IGNORES define can be used to list I2C devices which may or may not be present when using -CONFIG_SYS_POST_I2C_ADDRS. The I2C POST test will pass regardless -if the devices in CONFIG_SYS_POST_I2C_IGNORES are found or not. +CFG_SYS_POST_I2C_ADDRS. The I2C POST test will pass regardless +if the devices in CFG_SYS_POST_I2C_IGNORES are found or not. This is useful in cases when I2C devices are optional (eg on a daughtercard that may or may not be present) or not critical to board operation. diff --git a/doc/README.arm-relocation b/doc/README.arm-relocation index 6bb4e17847..69882a76a3 100644 --- a/doc/README.arm-relocation +++ b/doc/README.arm-relocation @@ -53,8 +53,8 @@ c) end executes this code d) this initialize CPU, RAM, ... and copy itself to RAM (this bin must fit in one page, so board_init_f() don;t fit in it ... ) -e) there it copy u-boot to CONFIG_SYS_NAND_U_BOOT_DST and - starts this image @ CONFIG_SYS_NAND_U_BOOT_START +e) there it copy u-boot to CFG_SYS_NAND_U_BOOT_DST and + starts this image @ CFG_SYS_NAND_U_BOOT_START f) u-boot code steps through board_init_f() and calculates the relocation address and copy itself to it @@ -86,8 +86,8 @@ Relocation with SPL (example for the tx25 booting from NAND Flash): - The First page contains u-boot code from drivers/mtd/nand/raw/mxc_nand_spl.c which inits the dram, cpu registers, reloacte itself to CONFIG_SPL_TEXT_BASE and loads - the "real" u-boot to CONFIG_SYS_NAND_U_BOOT_DST and starts execution - @CONFIG_SYS_NAND_U_BOOT_START + the "real" u-boot to CFG_SYS_NAND_U_BOOT_DST and starts execution + @CFG_SYS_NAND_U_BOOT_START - This u-boot does no RAM init, nor CPU register setup. Just look where it has to copy and relocate itself to this address. If diff --git a/doc/README.atmel_mci b/doc/README.atmel_mci index 00e64ba0c7..0b6d2c53db 100644 --- a/doc/README.atmel_mci +++ b/doc/README.atmel_mci @@ -60,7 +60,7 @@ int board_mmc_init(struct bd_info *bd) /* this is a weak define that we are overriding */ int board_mmc_getcd(struct mmc *mmc) { - return !at91_get_gpio_value(CONFIG_SYS_MMC_CD_PIN); + return !at91_get_gpio_value(CFG_SYS_MMC_CD_PIN); } #endif @@ -70,5 +70,5 @@ and the board definition files needs: /* SD/MMC card */ #define CONFIG_GENERIC_ATMEL_MCI 1 #define CONFIG_ATMEL_MCI_PORTB 1 /* Atmel XE-EK uses port B */ -#define CONFIG_SYS_MMC_CD_PIN AT91_PIN_PC9 +#define CFG_SYS_MMC_CD_PIN AT91_PIN_PC9 #define CONFIG_CMD_MMC 1 diff --git a/doc/README.cfi b/doc/README.cfi index ad52850818..3818574702 100644 --- a/doc/README.cfi +++ b/doc/README.cfi @@ -35,12 +35,12 @@ In addition, the t3corp board defines the routine thusly: void flash_cmd_reset(flash_info_t *info) { /* - * FLASH at address CONFIG_SYS_FLASH_BASE is a Spansion chip and + * FLASH at address CFG_SYS_FLASH_BASE is a Spansion chip and * needs the Spansion type reset commands. The other flash chip * is located behind a FPGA (Xilinx DS617) and needs the Intel type * reset command. */ - if (info->start[0] == CONFIG_SYS_FLASH_BASE) + if (info->start[0] == CFG_SYS_FLASH_BASE) flash_write_cmd(info, 0, 0, AMD_CMD_RESET); else flash_write_cmd(info, 0, 0, FLASH_CMD_RESET); diff --git a/doc/README.davinci b/doc/README.davinci index 607531af2a..326efa0a2d 100644 --- a/doc/README.davinci +++ b/doc/README.davinci @@ -75,7 +75,7 @@ http://www.ti.com/tool/TMDXLCDK138 Davinci special defines ======================= -CONFIG_SYS_DV_NOR_BOOT_CFG: AM18xx based boards, booting in NOR Boot mode +CFG_SYS_DV_NOR_BOOT_CFG: AM18xx based boards, booting in NOR Boot mode need a "NOR Boot Configuration Word" stored in the NOR Flash. This define adds this. More Info about this, see: diff --git a/doc/README.fec_mxc b/doc/README.fec_mxc index d17dfb676f..2ccd4288d2 100644 --- a/doc/README.fec_mxc +++ b/doc/README.fec_mxc @@ -18,16 +18,10 @@ CONFIG_PHYLIB CONFIG_FEC_MXC_NO_ANEG Relevant only if PHYLIB not used. Skips auto-negotiation restart. -CONFIG_FEC_MXC_PHYADDR +CFG_FEC_MXC_PHYADDR Optional, selects the exact phy address that should be connected and function fecmxc_initialize will try to initialize it. -CONFIG_FEC_FIXED_SPEED - Optional, selects a fixed speed on the MAC interface without asking some - phy. This is usefull if there is a direct MAC <-> MAC connection, for - example if the CPU is connected directly via the RGMII interface to a - ethernet-switch. - Reading the ethaddr from the SoC eFuses: if CONFIG_FEC_MXC is defined and the U-Boot environment does not contain the ethaddr variable, then its value gets read from the corresponding eFuses in diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr index cec5d94df4..f44bb2aa25 100644 --- a/doc/README.fsl-ddr +++ b/doc/README.fsl-ddr @@ -56,8 +56,8 @@ Table of 2-way interleaving modes supported in cpu/8xxx/ddr/ The ways to configure the ddr interleaving mode ============================================== 1. In board header file(e.g.MPC8572DS.h), add default interleaving setting - under "CONFIG_EXTRA_ENV_SETTINGS", like: - #define CONFIG_EXTRA_ENV_SETTINGS \ + under "CFG_EXTRA_ENV_SETTINGS", like: + #define CFG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:ctlr_intlv=bank" \ ...... @@ -137,7 +137,7 @@ Memory testing options for mpc85xx 2. Memory test can be done with Power-On-Self-Test function, activated at compile time. - In order to enable the POST memory test, CONFIG_POST needs to be + In order to enable the POST memory test, CFG_POST needs to be defined in board configuraiton header file. By default, POST memory test performs a fast test. A slow test can be enabled by changing the flag at compiling time. To test memory bigger than 2GB, 36BIT support is needed. diff --git a/doc/README.fsl-dpaa b/doc/README.fsl-dpaa deleted file mode 100644 index 3ef5eeb32e..0000000000 --- a/doc/README.fsl-dpaa +++ /dev/null @@ -1,10 +0,0 @@ -This file documents Freescale DPAA-specific options. - -FMan (Frame Manager) - - CONFIG_FSL_FM_10GEC_REGULAR_NOTATION - on SoCs T4240, T2080, LS1043A, etc, the notation between 10GEC and MAC as below: - 10GEC1->MAC9, 10GEC2->MAC10, 10GEC3->MAC1, 10GEC4->MAC2 - on SoCs T1024, etc, the notation between 10GEC and MAC as below: - 10GEC1->MAC1, 10GEC2->MAC2 - so we introduce CONFIG_FSL_FM_10GEC_REGULAR_NOTATION to identify the new SoCs on - which 10GEC enumeration is consistent with MAC enumeration. diff --git a/doc/README.fsl_iim b/doc/README.fsl_iim index e087f5e0e4..78d3cb8b3e 100644 --- a/doc/README.fsl_iim +++ b/doc/README.fsl_iim @@ -45,4 +45,4 @@ Fuse operations: Configuration: CONFIG_FSL_IIM - Define this to enable the fsl_iim driver. + Enable this to enable the fsl_iim driver. diff --git a/doc/README.generic_usb_ohci b/doc/README.generic_usb_ohci index 82fea6201d..767614cbc6 100644 --- a/doc/README.generic_usb_ohci +++ b/doc/README.generic_usb_ohci @@ -11,7 +11,7 @@ Configuration options CONFIG_USB_OHCI_NEW: enable the new OHCI driver - CONFIG_SYS_USB_OHCI_REGS_BASE: defines the base address of the OHCI + CFG_SYS_USB_OHCI_REGS_BASE: defines the base address of the OHCI registers CONFIG_SYS_USB_OHCI_SLOT_NAME: slot name diff --git a/doc/README.hwconfig b/doc/README.hwconfig index b6ddb438cf..5408a22bb6 100644 --- a/doc/README.hwconfig +++ b/doc/README.hwconfig @@ -1,6 +1,3 @@ -To enable this feature just define CONFIG_HWCONFIG in your board -config file. - This implements a simple hwconfig infrastructure: an interface for software knobs to control hardware. diff --git a/doc/README.kwbimage b/doc/README.kwbimage index 762b2e3acb..a1d247c32d 100644 --- a/doc/README.kwbimage +++ b/doc/README.kwbimage @@ -42,7 +42,7 @@ Board specific configuration file specifications: kwbimage.cfg. The name can be set as part of the full path to the file using CONFIG_SYS_KWD_CONFIG (probably in include/configs/<yourboard>.h). The path should look like: - $(CONFIG_BOARDDIR)/<yourkwbimagename>.cfg + $(CFG_BOARDDIR)/<yourkwbimagename>.cfg 2. This file can have empty lines and lines starting with "#" as first character to put comments 3. This file can have configuration command lines as mentioned below, diff --git a/doc/README.link-local b/doc/README.link-local index 148b4987f2..ec2ef940e4 100644 --- a/doc/README.link-local +++ b/doc/README.link-local @@ -51,7 +51,7 @@ by env variables. It depends on CONFIG_CMD_LINK_LOCAL, CONFIG_CMD_DHCP, and CONFIG_BOOTP_MAY_FAIL. If both fail or are disabled, static settings are used. -#define CONFIG_EXTRA_ENV_SETTINGS \ +#define CFG_EXTRA_ENV_SETTINGS \ "ipconfigcmd=if test \\\"$dhcpenabled\\\" -ne 0;" \ "then " \ "dhcpfail=0;dhcp || dhcpfail=1;" \ diff --git a/doc/README.mpc85xx b/doc/README.mpc85xx index 3c6ebbdb0e..bafffe6dc5 100644 --- a/doc/README.mpc85xx +++ b/doc/README.mpc85xx @@ -59,13 +59,13 @@ A) defined(CONFIG_SYS_RAMBOOT) i.e. SD, SPI, NAND RAMBOOT & NAND_SPL boot 3) TLB entry for the stack during AS1 Location : Lable "create_init_ram_area" TLB Entry : 14 - EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR + EPN -->RPN : CFG_SYS_INIT_RAM_ADDR --> CFG_SYS_INIT_RAM_ADDR Properties : 16K, AS1, IPROT 4) TLB entry for CCSRBAR during AS1 execution Location : cpu_init_early_f TLB Entry : 13 - EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR + EPN -->RPN : CFG_SYS_CCSRBAR --> CFG_SYS_CCSRBAR Properties : 1M, AS1, I, G 5) Invalidate unproctected TLB Entries @@ -84,7 +84,7 @@ A) defined(CONFIG_SYS_RAMBOOT) i.e. SD, SPI, NAND RAMBOOT & NAND_SPL boot 8) Update Flash's TLB entry Location : Board_init_r TLB entry : Search from TLB entries - EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS + EPN -->RPN : CFG_SYS_FLASH_BASE --> CFG_SYS_FLASH_BASE_PHYS Properties : Board specific size, AS0, I, G, IPROT @@ -94,7 +94,7 @@ B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot Location : Label "_start" TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB #if defined(CONFIG_NXP_ESBC) - EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW + EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CFG_SYS_PBI_FLASH_WINDOW Properties : 1M, AS1, I, G, IPROT #else EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000 @@ -105,7 +105,7 @@ B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot Location : Label "create_init_ram_area" TLB Entry : 15 #if defined(CONFIG_NXP_ESBC) - EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW + EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CFG_SYS_PBI_FLASH_WINDOW Properties : 1M, AS1, I, G, IPROT #else EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000 @@ -115,13 +115,13 @@ B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot 3) TLB entry for the stack during AS1 Location : Lable "create_init_ram_area" TLB Entry : 14 - EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR + EPN -->RPN : CFG_SYS_INIT_RAM_ADDR --> CFG_SYS_INIT_RAM_ADDR Properties : 16K, AS1, IPROT 4) TLB entry for CCSRBAR during AS1 execution Location : cpu_init_early_f TLB Entry : 13 - EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR + EPN -->RPN : CFG_SYS_CCSRBAR --> CFG_SYS_CCSRBAR Properties : 1M, AS1, I, G 5) TLB entry for Errata workaround CONFIG_SYS_FSL_ERRATUM_IFC_A003399 @@ -162,5 +162,5 @@ B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot 12) Update Flash's TLB entry Location : Board_init_r TLB entry : Search from TLB entries - EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS + EPN -->RPN : CFG_SYS_FLASH_BASE --> CFG_SYS_FLASH_BASE_PHYS Properties : Board specific size, AS0, I, G, IPROT diff --git a/doc/README.nand b/doc/README.nand index d1ce30768b..3765751253 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -99,16 +99,6 @@ Configuration Options: CONFIG_CMD_NAND_TORTURE Enables the torture command (see description of this command below). - CONFIG_SYS_NAND_MAX_ECCPOS - If specified, overrides the maximum number of ECC bytes - supported. Useful for reducing image size, especially with SPL. - This must be at least 48 if nand_base.c is used. - - CONFIG_SYS_NAND_MAX_OOBFREE - If specified, overrides the maximum number of free OOB regions - supported. Useful for reducing image size, especially with SPL. - This must be at least 2 if nand_base.c is used. - CONFIG_SYS_NAND_MAX_CHIPS The maximum number of NAND chips per device to be supported. @@ -144,7 +134,7 @@ Configuration Options: chip.IO_ADDR_R = ...; chip.IO_ADDR_W = ...; - if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_CHIPS, NULL)) + if (nand_scan_ident(mtd, CFG_SYS_MAX_NAND_CHIPS, NULL)) error out /* diff --git a/doc/README.omap3 b/doc/README.omap3 index 208714ad65..3a1ac8101d 100644 --- a/doc/README.omap3 +++ b/doc/README.omap3 @@ -146,11 +146,11 @@ implementation for OMAP3 works for you so the u-boot version should also. When you require the SPL to read with BCH8 there are two more configs to change: - * CONFIG_SYS_NAND_ECCPOS (must be the same as .eccpos in + * CFG_SYS_NAND_ECCPOS (must be the same as .eccpos in GPMC_NAND_HW_BCH8_ECC_LAYOUT defined in arch/arm/include/asm/arch-omap3/omap_gpmc.h) - * CONFIG_SYS_NAND_ECCSIZE must be 512 - * CONFIG_SYS_NAND_ECCBYTES must be 13 for this BCH8 setup + * CFG_SYS_NAND_ECCSIZE must be 512 + * CFG_SYS_NAND_ECCBYTES must be 13 for this BCH8 setup Acknowledgements ================ diff --git a/doc/README.pxe b/doc/README.pxe index d14d2bdcc9..172201093d 100644 --- a/doc/README.pxe +++ b/doc/README.pxe @@ -179,11 +179,19 @@ initrd <path> - if this label is chosen, use tftp to retrieve the initrd at <path>. it will be stored at the address indicated in the initrd_addr_r environment variable, and that address will be passed to bootm. + For FIT image, the initrd can be provided with the same value than + kernel, including configuration: + <path>#<conf>[#<extra-conf[#...]] + In this case, kernel_addr_r is passed to bootm. fdt <path> - if this label is chosen, use tftp to retrieve the fdt blob at <path>. it will be stored at the address indicated in the fdt_addr_r environment variable, and that address will be passed to bootm. + For FIT image, the device tree can be provided with the same value + than kernel, including configuration: + <path>#<conf>[#<extra-conf[#...]] + In this case, kernel_addr_r is passed to bootm. devicetree <path> - if this label is chosen, use tftp to retrieve the fdt blob at <path>. it will be stored at the address indicated in diff --git a/doc/README.serial_multi b/doc/README.serial_multi index c9049fd01d..0446fe9593 100644 --- a/doc/README.serial_multi +++ b/doc/README.serial_multi @@ -35,7 +35,7 @@ just after switching the console: setenv sout serial_scc; setenv baudrate 38400 After that press 'enter' at the SCC console. Note that baudrates <38400 -are not allowed on LWMON with watchdog enabled (see CONFIG_SYS_BAUDRATE_TABLE in +are not allowed on LWMON with watchdog enabled (see CFG_SYS_BAUDRATE_TABLE in include/configs/lwmon.h). diff --git a/doc/arch/m68k.rst b/doc/arch/m68k.rst index 15806dfaee..a9180fd785 100644 --- a/doc/arch/m68k.rst +++ b/doc/arch/m68k.rst @@ -93,10 +93,10 @@ Configuration to use a pre-loader ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ If U-Boot should be loaded to RAM and started by a pre-loader -CONFIG_MONITOR_IS_IN_RAM must be defined. If it is defined the +CONFIG_MONITOR_IS_IN_RAM must be enabled. If it is enabled the initial vector table and basic processor initialization will not be compiled in. The start address of U-Boot must be adjusted in -the boards config header file (CONFIG_SYS_MONITOR_BASE) and Makefile +the boards defconfig file (CONFIG_SYS_MONITOR_BASE) and Makefile (CONFIG_TEXT_BASE) to the load address. ColdFire CPU specific options/settings @@ -112,16 +112,16 @@ CONFIG_M5272: Other options, generally set inside include/configs/<boardname>.h, they may apply to one or more cpu for the ColdFire family: -CONFIG_SYS_MBAR: +CFG_SYS_MBAR: defines the base address of the MCF5272 configuration registers -CONFIG_SYS_SCR: +CFG_SYS_SCR: defines the contents of the System Configuration Register -CONFIG_SYS_SPR: +CFG_SYS_SPR: defines the contents of the System Protection Register -CONFIG_SYS_MFD: +CFG_SYS_MFD: defines the PLL Multiplication Factor Divider (see table 9-4 of MCF user manual) -CONFIG_SYS_RFD: +CFG_SYS_RFD: defines the PLL Reduce Frequency Devider (see table 9-4 of MCF user manual) CONFIG_SYS_CSx_BASE: @@ -136,33 +136,33 @@ CONFIG_SYS_CSx_RO: if set to 0 chip select x is read/write else chip select is read only CONFIG_SYS_CSx_WS: defines the number of wait states of chip select x -CONFIG_SYS_CACHE_ICACR: +CFG_SYS_CACHE_ICACR: cache-related registers config -CONFIG_SYS_CACHE_DCACR: +CFG_SYS_CACHE_DCACR: cache-related registers config CONFIG_SYS_CACHE_ACRX: cache-related registers config -CONFIG_SYS_SDRAM_BASE: +CFG_SYS_SDRAM_BASE: SDRAM config for SDRAM controller-specific registers -CONFIG_SYS_SDRAM_SIZE: +CFG_SYS_SDRAM_SIZE: SDRAM config for SDRAM controller-specific registers -CONFIG_SYS_SDRAM_BASEX: +CFG_SYS_SDRAM_BASEX: SDRAM config for SDRAM controller-specific registers -CONFIG_SYS_SDRAM_CFG1: +CFG_SYS_SDRAM_CFG1: SDRAM config for SDRAM controller-specific registers -CONFIG_SYS_SDRAM_CFG2: +CFG_SYS_SDRAM_CFG2: SDRAM config for SDRAM controller-specific registers -CONFIG_SYS_SDRAM_CTRL: +CFG_SYS_SDRAM_CTRL: SDRAM config for SDRAM controller-specific registers -CONFIG_SYS_SDRAM_MODE: +CFG_SYS_SDRAM_MODE: SDRAM config for SDRAM controller-specific registers -CONFIG_SYS_SDRAM_EMOD: +CFG_SYS_SDRAM_EMOD: SDRAM config for SDRAM controller-specific registers, please see arch/m68k/cpu/<specific_cpu>/start.S files to see how these options are used. CONFIG_MCFUART: defines enabling of ColdFire UART driver -CONFIG_SYS_UART_PORT: +CFG_SYS_UART_PORT: defines the UART port to be used (only a single UART can be actually enabled) -CONFIG_SYS_SBFHDR_SIZE: +CFG_SYS_SBFHDR_SIZE: size of the prepended SBF header, if any diff --git a/doc/arch/nios2.rst b/doc/arch/nios2.rst index 35defb0af0..34a75e7fb0 100644 --- a/doc/arch/nios2.rst +++ b/doc/arch/nios2.rst @@ -96,8 +96,8 @@ to 0xDxxx_xxxx. .. code-block:: c - #define CONFIG_SYS_SDRAM_BASE 0xc8000000 - #define CONFIG_SYS_SDRAM_SIZE 0x08000000 + #define CFG_SYS_SDRAM_BASE 0xc8000000 + #define CFG_SYS_SDRAM_SIZE 0x08000000 You will need to change the environment variables location and setting, too. You may change other configs to fit your board. diff --git a/doc/arch/sandbox/sandbox.rst b/doc/arch/sandbox/sandbox.rst index 34c4e06d9b..cd7f8a2cb0 100644 --- a/doc/arch/sandbox/sandbox.rst +++ b/doc/arch/sandbox/sandbox.rst @@ -56,11 +56,8 @@ To run sandbox U-Boot use something like:: Note: If you get errors about 'sdl-config: Command not found' you may need to install libsdl2.0-dev or similar to get SDL support. Alternatively you can -build sandbox without SDL (i.e. no display/keyboard support) by removing -the CONFIG_SANDBOX_SDL line in include/configs/sandbox.h or using:: - - make sandbox_defconfig all NO_SDL=1 - ./u-boot +build sandbox without SDL (i.e. no display/keyboard support) by disabling +CONFIG_SANDBOX_SDL in the .config file. U-Boot will start on your computer, showing a sandbox emulation of the serial console:: @@ -84,7 +81,7 @@ To exit, type 'poweroff' or press Ctrl-C. Console / LCD support --------------------- -Assuming that CONFIG_SANDBOX_SDL is defined when building, you can run the +Assuming that CONFIG_SANDBOX_SDL is enabled when building, you can run the sandbox with LCD and keyboard emulation, using something like:: ./u-boot -d u-boot.dtb -l @@ -618,7 +615,7 @@ Addr Config Usage ======= ======================== =============================== 0 CONFIG_SYS_FDT_LOAD_ADDR Device tree c000 CONFIG_BLOBLIST_ADDR Blob list - 10000 CONFIG_MALLOC_F_ADDR Early memory allocation + 10000 CFG_MALLOC_F_ADDR Early memory allocation f0000 CONFIG_PRE_CON_BUF_ADDR Pre-console buffer 100000 CONFIG_TRACE_EARLY_ADDR Early trace buffer (if enabled). Also used as the SPL load buffer in spl_test_load(). diff --git a/doc/arch/x86.rst b/doc/arch/x86.rst index 634387ac09..725a1ae586 100644 --- a/doc/arch/x86.rst +++ b/doc/arch/x86.rst @@ -355,8 +355,8 @@ environment variables if you add this to minnowmax.h: "ext2load scsi 0:2 04000000 /boot/initrd.img-3.13.0-58-generic; " \ "run boot" - #undef CONFIG_EXTRA_ENV_SETTINGS - #define CONFIG_EXTRA_ENV_SETTINGS "boot=zboot 03000000 0 04000000 ${filesize}" + #undef CFG_EXTRA_ENV_SETTINGS + #define CFG_EXTRA_ENV_SETTINGS "boot=zboot 03000000 0 04000000 ${filesize}" and change CONFIG_BOOTARGS value in configs/minnowmax_defconfig to:: diff --git a/doc/board/ti/am335x_evm.rst b/doc/board/ti/am335x_evm.rst index 7db9604ce0..ee4faec37c 100644 --- a/doc/board/ti/am335x_evm.rst +++ b/doc/board/ti/am335x_evm.rst @@ -57,7 +57,7 @@ Step-1: Building u-boot for NAND boot CONFIG_SYS_NAND_PAGE_SIZE number of main bytes in NAND page CONFIG_SYS_NAND_OOBSIZE number of OOB bytes in NAND page CONFIG_SYS_NAND_BLOCK_SIZE number of bytes in NAND erase-block - CONFIG_SYS_NAND_ECCPOS ECC map for NAND page + CFG_SYS_NAND_ECCPOS ECC map for NAND page CONFIG_NAND_OMAP_ECCSCHEME (refer doc/README.nand) Step-2: Flashing NAND via MMC/SD diff --git a/doc/build/tools.rst b/doc/build/tools.rst index c06f915274..ec01722925 100644 --- a/doc/build/tools.rst +++ b/doc/build/tools.rst @@ -44,4 +44,4 @@ applications using a linux toolchain (gcc, bash, etc), targeting respectively Launch the MSYS2 shell of the MSYS2 environment, and do the following:: $ make tools-only_defconfig - $ make tools-only NO_SDL=1 + $ make tools-only diff --git a/doc/develop/devicetree/control.rst b/doc/develop/devicetree/control.rst index c71570d64b..0b3b32be1b 100644 --- a/doc/develop/devicetree/control.rst +++ b/doc/develop/devicetree/control.rst @@ -135,7 +135,7 @@ control the boot process of Linux with bootm/bootz commands. To use this, put something like this in your board header file:: - #define CONFIG_EXTRA_ENV_SETTINGS "fdtcontroladdr=10000\0" + #define CFG_EXTRA_ENV_SETTINGS "fdtcontroladdr=10000\0" Build: diff --git a/doc/develop/distro.rst b/doc/develop/distro.rst index bc72aa951e..8016acad09 100644 --- a/doc/develop/distro.rst +++ b/doc/develop/distro.rst @@ -214,7 +214,7 @@ Required Environment Variables The U-Boot "syslinux" and "pxe boot" commands require a number of environment variables be set. Default values for these variables are often hard-coded into -CONFIG_EXTRA_ENV_SETTINGS in the board's U-Boot configuration file, so that +CFG_EXTRA_ENV_SETTINGS in the board's U-Boot configuration file, so that the user doesn't have to configure them. fdt_addr: diff --git a/doc/develop/driver-model/migration.rst b/doc/develop/driver-model/migration.rst index 43665de64f..fe1ae210de 100644 --- a/doc/develop/driver-model/migration.rst +++ b/doc/develop/driver-model/migration.rst @@ -99,7 +99,7 @@ The I2C subsystem has supported the driver model since early 2015. Maintainers should submit patches switching over to using CONFIG_DM_I2C and other base driver model options in time for inclusion in the 2021.10 release. -CONFIG_SYS_TIMER_RATE and CONFIG_SYS_TIMER_COUNTER +CFG_SYS_TIMER_RATE and CFG_SYS_TIMER_COUNTER -------------------------------------------------- Deadline: 2023.01 diff --git a/doc/device-tree-bindings/mtd/ti,elm.yaml b/doc/device-tree-bindings/mtd/ti,elm.yaml new file mode 100644 index 0000000000..87128c0045 --- /dev/null +++ b/doc/device-tree-bindings/mtd/ti,elm.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/ti,elm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments Error Location Module (ELM). + +maintainers: + - Roger Quadros <rogerq@kernel.org> + +description: + ELM module is used together with GPMC and NAND Flash to detect + errors and the location of the error based on BCH algorithms + so they can be corrected if possible. + +properties: + compatible: + enum: + - ti,am3352-elm + - ti,am64-elm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + description: Functional clock. + + clock-names: + items: + - const: fck + + power-domains: + maxItems: 1 + + ti,hwmods: + description: + Name of the HWMOD associated with ELM. This is for legacy + platforms only. + $ref: /schemas/types.yaml#/definitions/string + deprecated: true + +required: + - compatible + - reg + - interrupts + +allOf: + - if: + properties: + compatible: + contains: + const: ti,am64-elm + then: + required: + - clocks + - clock-names + - power-domains + +additionalProperties: false + +examples: + - | + elm: ecc@0 { + compatible = "ti,am3352-elm"; + reg = <0x0 0x2000>; + interrupts = <4>; + }; diff --git a/doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml b/doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml new file mode 100644 index 0000000000..4ac198814b --- /dev/null +++ b/doc/device-tree-bindings/mtd/ti,gpmc-nand.yaml @@ -0,0 +1,129 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/ti,gpmc-nand.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments GPMC NAND Flash controller. + +maintainers: + - Tony Lindgren <tony@atomide.com> + - Roger Quadros <rogerq@kernel.org> + +description: + GPMC NAND controller/Flash is represented as a child of the + GPMC controller node. + +properties: + compatible: + items: + - enum: + - ti,am64-nand + - ti,omap2-nand + + reg: + maxItems: 1 + + interrupts: + items: + - description: Interrupt for fifoevent + - description: Interrupt for termcount + + "#address-cells": true + + "#size-cells": true + + ti,nand-ecc-opt: + description: Desired ECC algorithm + $ref: /schemas/types.yaml#/definitions/string + enum: [sw, ham1, bch4, bch8, bch16] + + ti,nand-xfer-type: + description: Data transfer method between controller and chip. + $ref: /schemas/types.yaml#/definitions/string + enum: [prefetch-polled, polled, prefetch-dma, prefetch-irq] + default: prefetch-polled + + ti,elm-id: + description: + phandle to the ELM (Error Location Module). + $ref: /schemas/types.yaml#/definitions/phandle + + nand-bus-width: + description: + Bus width to the NAND chip + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [8, 16] + default: 8 + + rb-gpios: + description: + GPIO connection to R/B signal from NAND chip + maxItems: 1 + +patternProperties: + "@[0-9a-f]+$": + $ref: "/schemas/mtd/partitions/partition.yaml" + +allOf: + - $ref: "/schemas/memory-controllers/ti,gpmc-child.yaml" + +required: + - compatible + - reg + - ti,nand-ecc-opt + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/gpio/gpio.h> + + gpmc: memory-controller@50000000 { + compatible = "ti,am3352-gpmc"; + dmas = <&edma 52 0>; + dma-names = "rxtx"; + clocks = <&l3s_gclk>; + clock-names = "fck"; + reg = <0x50000000 0x2000>; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + gpmc,num-cs = <7>; + gpmc,num-waitpins = <2>; + #address-cells = <2>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + + ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */ + nand@0,0 { + compatible = "ti,omap2-nand"; + reg = <0 0 4>; /* device IO registers */ + interrupt-parent = <&gpmc>; + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ + <1 IRQ_TYPE_NONE>; /* termcount */ + ti,nand-xfer-type = "prefetch-dma"; + ti,nand-ecc-opt = "bch16"; + ti,elm-id = <&elm>; + #address-cells = <1>; + #size-cells = <1>; + + /* NAND generic properties */ + nand-bus-width = <8>; + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ + + /* GPMC properties*/ + gpmc,device-width = <1>; + + partition@0 { + label = "NAND.SPL"; + reg = <0x00000000 0x00040000>; + }; + partition@1 { + label = "NAND.SPL.backup1"; + reg = <0x00040000 0x00040000>; + }; + }; + }; diff --git a/doc/device-tree-bindings/video/exynos-dp.txt b/doc/device-tree-bindings/video/exynos-dp.txt index 464a85302e..273d8fc796 100644 --- a/doc/device-tree-bindings/video/exynos-dp.txt +++ b/doc/device-tree-bindings/video/exynos-dp.txt @@ -30,9 +30,9 @@ Optional properties: 8(WHITE_GRAY_BALCKBAR_64),9(MOBILE_WHITEBAR_32), 10(MOBILE_WHITEBAR_64) samsung,h-sync-polarity: Horizontal Sync polarity - CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH + CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH samsung,v-sync-polarity: Vertical Sync polarity - CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH + CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH samsung,interlaced: Progressive if 0, else Interlaced samsung,color-space: input video data format COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2 diff --git a/doc/device-tree-bindings/video/exynos-fb.txt b/doc/device-tree-bindings/video/exynos-fb.txt index b022f6163f..bff0cecfcf 100644 --- a/doc/device-tree-bindings/video/exynos-fb.txt +++ b/doc/device-tree-bindings/video/exynos-fb.txt @@ -23,15 +23,15 @@ Board(panel specific): samsung,vl-height: Height of display area in mm samsung,vl-clkp: Clock polarity - CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH + CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH samsung,vl-oep: Output Enable polarity - CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH + CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH samsung,vl-hsp: Horizontal Sync polarity - CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH + CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH samsung,vl-vsp: Vertical Sync polarity - CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH + CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH samsung,vl-dp: Data polarity - CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH + CFG_SYS_LOW if defined, else CONFIG_SYS_HIGH samsung,vl-cmd-allow-len: Wait end of frame samsung,winid: Window number on which data is to be displayed diff --git a/doc/imx/common/imx5.txt b/doc/imx/common/imx5.txt index ea0e144ced..6c8c2e594f 100644 --- a/doc/imx/common/imx5.txt +++ b/doc/imx/common/imx5.txt @@ -16,7 +16,7 @@ i.MX5x SoCs. of frequency deviation), avoiding system failure, or at least decreasing the likelihood of system failure. -1.2 CONFIG_SYS_MAIN_PWR_ON: Trigger MAIN_PWR_ON upon startup. +1.2 CFG_SYS_MAIN_PWR_ON: Trigger MAIN_PWR_ON upon startup. This option should be enabled for boards having a SYS_ON_OFF_CTL signal connected to GPIO1[23] and triggering the MAIN_PWR_ON signal like in the reference designs. diff --git a/doc/uImage.FIT/source_file_format.txt b/doc/uImage.FIT/source_file_format.txt index 4640e38e3c..269e1fa0b5 100644 --- a/doc/uImage.FIT/source_file_format.txt +++ b/doc/uImage.FIT/source_file_format.txt @@ -247,6 +247,7 @@ o config-1 |- kernel = "kernel sub-node unit name" |- fdt = "fdt sub-node unit-name" [, "fdt overlay sub-node unit-name", ...] |- loadables = "loadables sub-node unit-name" + |- script = " |- compatible = "vendor,board-style device tree compatible string" @@ -268,6 +269,8 @@ o config-1 of strings. U-Boot will load each binary at its given start-address and may optionally invoke additional post-processing steps on this binary based on its component image node type. + - script : The image to use when loading a U-Boot script (for use with the + source command). - compatible : The root compatible string of the U-Boot device tree that this configuration shall automatically match when CONFIG_FIT_BEST_MATCH is enabled. If this property is not provided, the compatible string will be diff --git a/doc/usage/cmd/qfw.rst b/doc/usage/cmd/qfw.rst index b3704b92d6..cc0e27c277 100644 --- a/doc/usage/cmd/qfw.rst +++ b/doc/usage/cmd/qfw.rst @@ -31,7 +31,7 @@ kernel_addr initrd_addr address to which the file specified by the -initrd parameter of QEMU shall be loaded. Defaults to environment variable *ramdiskaddr* and further to - the value of *CONFIG_RAMDISK_ADDR*. + the value of *CFG_RAMDISK_ADDR*. Examples -------- diff --git a/doc/usage/environment.rst b/doc/usage/environment.rst index 15897f63dd..2c44e5da6a 100644 --- a/doc/usage/environment.rst +++ b/doc/usage/environment.rst @@ -89,7 +89,7 @@ Old-style C environment Traditionally, the default environment is created in `include/env_default.h`, and can be augmented by various `CONFIG` defines. See that file for details. In -particular you can define `CONFIG_EXTRA_ENV_SETTINGS` in your board file +particular you can define `CFG_EXTRA_ENV_SETTINGS` in your board file to add environment variables. Board maintainers are encouraged to migrate to the text-based environment as it @@ -162,7 +162,7 @@ bootm_low for use by the bootm command. See also "bootm_size" environment variable. Address defined by "bootm_low" is also the base of the initial memory mapping for the Linux - kernel -- see the description of CONFIG_SYS_BOOTMAPSZ and + kernel -- see the description of CFG_SYS_BOOTMAPSZ and bootm_mapsize. bootm_mapsize @@ -170,7 +170,7 @@ bootm_mapsize This variable is given as a hexadecimal number and it defines the size of the memory region starting at base address bootm_low that is accessible by the Linux kernel - during early boot. If unset, CONFIG_SYS_BOOTMAPSZ is used + during early boot. If unset, CFG_SYS_BOOTMAPSZ is used as the default value if it is defined, and bootm_size is used otherwise. @@ -228,7 +228,7 @@ initrd_high is usually what you want since it allows for maximum initrd size. If for some reason you want to make sure that the initrd image is loaded below the - CONFIG_SYS_BOOTMAPSZ limit, you can set this environment + CFG_SYS_BOOTMAPSZ limit, you can set this environment variable to a value of "no" or "off" or "0". Alternatively, you can set it to a maximum upper address to use (U-Boot will still check that it |