18 files changed, 67 insertions, 31 deletions
diff --git a/doc/README.arm-relocation b/doc/README.arm-relocation
index bc6644911b9..6bb4e178474 100644
--- a/doc/README.arm-relocation
+++ b/doc/README.arm-relocation
@@ -41,7 +41,7 @@ Boards which are not fixed to support relocation will be REMOVED!
 -----------------------------------------------------------------------------
 
 For boards which boot from spl, it is possible to save one copy
-if CONFIG_SYS_TEXT_BASE == relocation address! This prevents that uboot code
+if CONFIG_TEXT_BASE == relocation address! This prevents that uboot code
 is copied again in relocate_code().
 
 example for the tx25 board booting from NAND Flash:
@@ -58,7 +58,7 @@ e) there it copy u-boot to CONFIG_SYS_NAND_U_BOOT_DST and
 f) u-boot code steps through board_init_f() and calculates
    the relocation address and copy itself to it
 
-If CONFIG_SYS_TEXT_BASE == relocation address, the copying of u-boot
+If CONFIG_TEXT_BASE == relocation address, the copying of u-boot
 in f) could be saved.
 
 -----------------------------------------------------------------------------
@@ -68,10 +68,10 @@ TODO
 - fill in struct bd_info infos (check)
 - adapt all boards
 
-- maybe adapt CONFIG_SYS_TEXT_BASE (this must be checked from board maintainers)
+- maybe adapt CONFIG_TEXT_BASE (this must be checked from board maintainers)
   This *must* be done for boards, which boot from NOR flash
 
-  on other boards if CONFIG_SYS_TEXT_BASE = relocation baseaddr, this saves
+  on other boards if CONFIG_TEXT_BASE = relocation baseaddr, this saves
   one copying from u-boot code.
 
 - new function dram_init_banksize() is actual board specific. Maybe
@@ -91,7 +91,7 @@ Relocation with SPL (example for the tx25 booting from NAND Flash):
 
 - This u-boot does no RAM init, nor CPU register setup. Just look
   where it has to copy and relocate itself to this address. If
-  relocate address = CONFIG_SYS_TEXT_BASE (not the same, as the
+  relocate address = CONFIG_TEXT_BASE (not the same, as the
   CONFIG_SPL_TEXT_BASE from the spl code), then there is no need
   to copy, just go on with bss clear and jump to board_init_r.
 
diff --git a/doc/SPL/README.omap3 b/doc/SPL/README.omap3
index c77ca4300af..c0f4bab29b3 100644
--- a/doc/SPL/README.omap3
+++ b/doc/SPL/README.omap3
@@ -36,17 +36,17 @@ Option 1 (SPL only):
 0x40200800 - 0x4020BBFF: Area for SPL text, data and rodata
 0x4020E000 - 0x4020FFFC: Area for the SPL stack.
 0x80000000 - 0x8007FFFF: Area for the SPL BSS.
-0x80100000: CONFIG_SYS_TEXT_BASE of U-Boot
+0x80100000: CONFIG_TEXT_BASE of U-Boot
 0x80208000 - 0x80307FFF: malloc() pool available to SPL.
 
 Option 2 (SPL or X-Loader):
 0x40200800 - 0x4020BBFF: Area for SPL text, data and rodata
 0x4020E000 - 0x4020FFFC: Area for the SPL stack.
-0x80008000: CONFIG_SYS_TEXT_BASE of U-Boot
+0x80008000: CONFIG_TEXT_BASE of U-Boot
 0x87000000 - 0x8707FFFF: Area for the SPL BSS.
 0x87080000 - 0x870FFFFF: malloc() pool available to SPL.
 
 For the areas that reside within DDR1 they must not be used prior to s_init()
-completing.  Note that CONFIG_SYS_TEXT_BASE must be clear of the areas that SPL
+completing.  Note that CONFIG_TEXT_BASE must be clear of the areas that SPL
 uses while running.  This is why we have two versions of the memory map that
 only vary in where the BSS and malloc pool reside.
diff --git a/doc/arch/m68k.rst b/doc/arch/m68k.rst
index 87a51e5b7db..15806dfaee1 100644
--- a/doc/arch/m68k.rst
+++ b/doc/arch/m68k.rst
@@ -97,7 +97,7 @@ CONFIG_MONITOR_IS_IN_RAM must be defined. If it is defined the
 initial vector table and basic processor initialization will not
 be compiled in. The start address of U-Boot must be adjusted in
 the boards config header file (CONFIG_SYS_MONITOR_BASE) and Makefile
-(CONFIG_SYS_TEXT_BASE) to the load address.
+(CONFIG_TEXT_BASE) to the load address.
 
 ColdFire CPU specific options/settings
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
diff --git a/doc/arch/sandbox.rst b/doc/arch/sandbox.rst
index 068d4a3be40..ed66f70f619 100644
--- a/doc/arch/sandbox.rst
+++ b/doc/arch/sandbox.rst
@@ -619,5 +619,5 @@ Addr      Config                     Usage
   f0000   CONFIG_PRE_CON_BUF_ADDR    Pre-console buffer
  100000   CONFIG_TRACE_EARLY_ADDR    Early trace buffer (if enabled). Also used
                                      as the SPL load buffer in spl_test_load().
- 200000   CONFIG_SYS_TEXT_BASE       Load buffer for U-Boot (sandbox_spl only)
+ 200000   CONFIG_TEXT_BASE           Load buffer for U-Boot (sandbox_spl only)
 =======   ========================   ===============================
diff --git a/doc/board/coreboot/coreboot.rst b/doc/board/coreboot/coreboot.rst
index 3792f9e1c8d..4a5f101cad2 100644
--- a/doc/board/coreboot/coreboot.rst
+++ b/doc/board/coreboot/coreboot.rst
@@ -26,7 +26,7 @@ this capability yet. The command is as follows::
    $ ./build/util/cbfstool/cbfstool build/coreboot.rom add-flat-binary \
      -f u-boot-dtb.bin -n fallback/payload -c lzma -l 0x1110000 -e 0x1110000
 
-Make sure 0x1110000 matches CONFIG_SYS_TEXT_BASE, which is the symbol address
+Make sure 0x1110000 matches CONFIG_TEXT_BASE, which is the symbol address
 of _x86boot_start (in arch/x86/cpu/start.S).
 
 If you want to use ELF as the coreboot payload, change U-Boot configuration to
@@ -64,7 +64,7 @@ Memory map
     10000000  Memory reserved by coreboot for mapping PCI devices
               (typical size 2151000, includes framebuffer)
      1920000  CONFIG_SYS_CAR_ADDR, fake Cache-as-RAM memory, used during startup
-     1110000  CONFIG_SYS_TEXT_BASE (start address of U-Boot code, before reloc)
+     1110000  CONFIG_TEXT_BASE (start address of U-Boot code, before reloc)
       110000  CONFIG_BLOBLIST_ADDR (before being relocated)
       100000  CONFIG_PRE_CON_BUF_ADDR
        f0000  ACPI tables set up by U-Boot
diff --git a/doc/board/google/chromebook_coral.rst b/doc/board/google/chromebook_coral.rst
index 4b585678dcf..8edbf0429cd 100644
--- a/doc/board/google/chromebook_coral.rst
+++ b/doc/board/google/chromebook_coral.rst
@@ -250,7 +250,7 @@ boots. Be warned that SPL can take 30 seconds without this cache! This is a
 known issue with Intel SoCs with modern DRAM and apparently cannot be improved.
 The MRC caches are used to work around this.
 
-Once SPL is finished it loads U-Boot into SDRAM at CONFIG_SYS_TEXT_BASE, which
+Once SPL is finished it loads U-Boot into SDRAM at CONFIG_TEXT_BASE, which
 is normally 1110000. Note that CAR is still active.
 
 
@@ -355,7 +355,7 @@ Partial memory map
        f0000       CONFIG_ROM_TABLE_ADDR
       120000       BSS (defined in u-boot-spl.lds)
       200000       FSP-S (which is run after U-Boot is relocated)
-     1110000       CONFIG_SYS_TEXT_BASE
+     1110000       CONFIG_TEXT_BASE
 
 
 Speeding up SPL for development
diff --git a/doc/board/google/chromebook_samus.rst b/doc/board/google/chromebook_samus.rst
index eab1128e4f9..822ba575e2f 100644
--- a/doc/board/google/chromebook_samus.rst
+++ b/doc/board/google/chromebook_samus.rst
@@ -91,7 +91,7 @@ Flash map for samus / broadwell:
    :fffd8000:	TPL_TEXT_BASE
    :fffa0000:	X86_MRC_ADDR
    :fff90000:	VGA_BIOS_ADDR
-   :ffed0000:	SYS_TEXT_BASE
+   :ffed0000:	TEXT_BASE
    :ffea0000:	X86_REFCODE_ADDR
    :ffe70000:	SPL_TEXT_BASE
    :ffbf8000:	CONFIG_ENV_OFFSET (environemnt offset)
diff --git a/doc/board/intel/minnowmax.rst b/doc/board/intel/minnowmax.rst
index 028121735ae..1ba25b50d21 100644
--- a/doc/board/intel/minnowmax.rst
+++ b/doc/board/intel/minnowmax.rst
@@ -56,7 +56,7 @@ Offset   Description         Controlling config
 500000   <spare>
 6ef000   Environment         CONFIG_ENV_OFFSET
 6f0000   MRC cache           CONFIG_ENABLE_MRC_CACHE
-700000   u-boot-dtb.bin      CONFIG_SYS_TEXT_BASE
+700000   u-boot-dtb.bin      CONFIG_TEXT_BASE
 7b0000   vga.bin             CONFIG_VGA_BIOS_ADDR
 7c0000   fsp.bin             CONFIG_FSP_ADDR
 7f8000   <spare>             (depends on size of fsp.bin)
diff --git a/doc/board/intel/slimbootloader.rst b/doc/board/intel/slimbootloader.rst
index 18f1cc0569c..87d71a55bdc 100644
--- a/doc/board/intel/slimbootloader.rst
+++ b/doc/board/intel/slimbootloader.rst
@@ -69,7 +69,7 @@ The PayloadId can be any 4 Bytes value.
     +GEN_CFG_DATA.PayloadId                     | 'U-BT'
 
 2. Update payload text base. PAYLOAD_EXE_BASE must be the same as U-Boot
-   CONFIG_SYS_TEXT_BASE in board/intel/slimbootloader/Kconfig.
+   CONFIG_TEXT_BASE in board/intel/slimbootloader/Kconfig.
    PAYLOAD_LOAD_HIGH must be 0::
 
     $ vi Platform/QemuBoardPkg/BoardConfig.py
@@ -122,7 +122,7 @@ Also, the PayloadId needs to be set for APL board.
 
 2. Update payload text base.
 
-* PAYLOAD_EXE_BASE must be the same as U-Boot CONFIG_SYS_TEXT_BASE
+* PAYLOAD_EXE_BASE must be the same as U-Boot CONFIG_TEXT_BASE
   in board/intel/slimbootloader/Kconfig.
 * PAYLOAD_LOAD_HIGH must be 0::
 
diff --git a/doc/board/nxp/mx6ul_14x14_evk.rst b/doc/board/nxp/mx6ul_14x14_evk.rst
index 8298bf8e1e7..3e57ba1ee81 100644
--- a/doc/board/nxp/mx6ul_14x14_evk.rst
+++ b/doc/board/nxp/mx6ul_14x14_evk.rst
@@ -74,9 +74,9 @@ The following script should be created to boot SPL + u-boot-dtb.img binaries:
      SDPU: jump -addr 0x877fffc0
      SDPU: done
 
-Please note that the address above is calculated based on SYS_TEXT_BASE address:
+Please note that the address above is calculated based on TEXT_BASE address:
 
-0x877fffc0 = 0x87800000 (SYS_TEXT_BASE) - 0x40 (U-Boot proper Header size)
+0x877fffc0 = 0x87800000 (TEXT_BASE) - 0x40 (U-Boot proper Header size)
 
 Power on the target and run the following command from U-Boot root directory:
 
diff --git a/doc/board/sipeed/maix.rst b/doc/board/sipeed/maix.rst
index 903f8831d70..4568bb3e4b7 100644
--- a/doc/board/sipeed/maix.rst
+++ b/doc/board/sipeed/maix.rst
@@ -93,7 +93,7 @@ The OpenSBI source can be downloaded via:
 As OpenSBI will be loaded at 0x80000000 we have to adjust the U-Boot text base.
 Furthermore we have to enable building U-Boot for S-mode::
 
-    CONFIG_SYS_TEXT_BASE=0x80020000
+    CONFIG_TEXT_BASE=0x80020000
     CONFIG_RISCV_SMODE=y
 
 Both settings are contained in sipeed_maix_smode_defconfig so we can build
@@ -115,7 +115,7 @@ To build OpenSBI with U-Boot as a payload:
     FW_PAYLOAD_OFFSET=0x20000 \
     FW_PAYLOAD_PATH=<path to U-Boot>/u-boot-dtb.bin
 
-The value of FW_PAYLOAD_OFFSET must match CONFIG_SYS_TEXT_BASE - 0x80000000.
+The value of FW_PAYLOAD_OFFSET must match CONFIG_TEXT_BASE - 0x80000000.
 
 The file to flash is build/platform/kendryte/k210/firmware/fw_payload.bin.
 
diff --git a/doc/chromium/chainload.rst b/doc/chromium/chainload.rst
index 7b6bb10d36d..b00ee94eaa4 100644
--- a/doc/chromium/chainload.rst
+++ b/doc/chromium/chainload.rst
@@ -140,7 +140,7 @@ bytes of U-Boot::
 
 
 The 'data' property of the FIT is set up to start at offset 0x100 bytes into
-the file. The change to CONFIG_SYS_TEXT_BASE is also an offset of 0x100 bytes
+the file. The change to CONFIG_TEXT_BASE is also an offset of 0x100 bytes
 from the load address. If this changes, you either need to modify U-Boot to be
 fully relocatable, or expect it to hang.
 
@@ -156,11 +156,11 @@ Open include/configs/rk3288_common.h
 
 Change::
 
-   #define CONFIG_SYS_TEXT_BASE		0x00100000
+   #define CONFIG_TEXT_BASE		0x00100000
 
 to::
 
-   #define CONFIG_SYS_TEXT_BASE		0x02000100
+   #define CONFIG_TEXT_BASE		0x02000100
 
 
 
@@ -254,4 +254,4 @@ it uses a fixed address to load the FIT and does not support load/exec
 addresses. This means that U-Boot must be able to boot from whatever
 address Depthcharge happens to use (it is the CONFIG_KERNEL_START setting
 in Depthcharge). In practice this means that the data in the kernel@1 FIT node
-(see above) must start at the same address as U-Boot's CONFIG_SYS_TEXT_BASE.
+(see above) must start at the same address as U-Boot's CONFIG_TEXT_BASE.
diff --git a/doc/develop/moveconfig.rst b/doc/develop/moveconfig.rst
index bfb7aff3582..ad8596e6c61 100644
--- a/doc/develop/moveconfig.rst
+++ b/doc/develop/moveconfig.rst
@@ -20,10 +20,10 @@ First, you must edit the Kconfig to add the menu entries for the configs
 you are moving.
 
 Then run this tool giving CONFIG names you want to move.
-For example, if you want to move CONFIG_CMD_USB and CONFIG_SYS_TEXT_BASE,
+For example, if you want to move CONFIG_CMD_USB and CONFIG_TEXT_BASE,
 simply type as follows::
 
-  $ tools/moveconfig.py CONFIG_CMD_USB CONFIG_SYS_TEXT_BASE
+  $ tools/moveconfig.py CONFIG_CMD_USB CONFIG_TEXT_BASE
 
 The tool walks through all the defconfig files and move the given CONFIGs.
 
diff --git a/doc/develop/tests_writing.rst b/doc/develop/tests_writing.rst
index 1ddf7a353a7..bb1145da268 100644
--- a/doc/develop/tests_writing.rst
+++ b/doc/develop/tests_writing.rst
@@ -74,6 +74,33 @@ NOT rely on running with sandbox, but instead should function correctly on any
 board supported by U-Boot.
 
 
+Mixing Python and C
+-------------------
+
+The best of both worlds is sometimes to have a Python test set things up and
+perform some operations, with a 'checker' C unit test doing the checks
+afterwards. This can be achieved with these steps:
+
+- Add the `UT_TESTF_MANUAL` flag to the checker test so that the `ut` command
+  does not run it by default
+- Add a `_norun` suffix to the name so that pytest knows to skip it too
+
+In your Python test use the `-f` flag to the `ut` command to force the checker
+test to run it, e.g.::
+
+   # Do the Python part
+   host load ...
+   bootm ...
+
+   # Run the checker to make sure that everything worked
+   ut -f bootstd vbe_test_fixup_norun
+
+Note that apart from the `UT_TESTF_MANUAL` flag, the code in a 'manual' C test
+is just like any other C test. It still uses ut_assert...() and other such
+constructs, in this case to check that the expected things happened in the
+Python test.
+
+
 How slow are Python tests?
 --------------------------
 
diff --git a/doc/imx/habv4/csf_examples/mx8m/csf.sh b/doc/imx/habv4/csf_examples/mx8m/csf.sh
index 7d267a7218d..7a9a05e6339 100644
--- a/doc/imx/habv4/csf_examples/mx8m/csf.sh
+++ b/doc/imx/habv4/csf_examples/mx8m/csf.sh
@@ -38,7 +38,7 @@ dd if=csf_spl.bin of=flash.bin bs=1 seek=${spl_dd_offset} conv=notrunc
 # 3) Sign u-boot.itb
 
 # fitImage tree
-fit_block_base=$(printf "0x%x" $(( $(sed -n "/CONFIG_SYS_TEXT_BASE=/ s@.*=@@p" .config) - $(sed -n "/CONFIG_FIT_EXTERNAL_OFFSET=/ s@.*=@@p" .config) - 0x200 - 0x40)) )
+fit_block_base=$(printf "0x%x" $(( $(sed -n "/CONFIG_TEXT_BASE=/ s@.*=@@p" .config) - $(sed -n "/CONFIG_FIT_EXTERNAL_OFFSET=/ s@.*=@@p" .config) - 0x200 - 0x40)) )
 fit_block_offset=$(printf "0x%s" $(fdtget -t x u-boot.dtb /binman/imx-boot/uboot offset))
 fit_block_size=$(printf "0x%x" $(( ( ($(fdtdump u-boot.itb 2>/dev/null | sed -n "/^...totalsize:/ s@.*\(0x[0-9a-f]\+\).*@\1@p") + 0x1000 - 0x1 ) & ~(0x1000 - 0x1)) + 0x20 )) )
 sed -i "/Blocks = / s@.*@  Blocks = $fit_block_base $fit_block_offset $fit_block_size \"flash.bin\", \\\\@" csf_fit.tmp
diff --git a/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt b/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt
index 747f7cd260f..3e3d38440f9 100644
--- a/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt
+++ b/doc/imx/habv4/guides/mx8m_spl_secure_boot.txt
@@ -79,7 +79,7 @@ code within it:
 
 The diagram below illustrate a signed U-Boot binary, DT blob and external
 ATF BL31 blob combined to form fitImage part of flash.bin container layout.
-The *load_address is derived from CONFIG_SYS_TEXT_BASE such that the U-Boot
+The *load_address is derived from CONFIG_TEXT_BASE such that the U-Boot
 binary *start is placed exactly at CONFIG_SPL_TEXT_BASE in DRAM, however the
 SPL moves the fitImage tree further to location:
  *load_address = CONFIG_SPL_TEXT_BASE - CONFIG_FIT_EXTERNAL_OFFSET (=12kiB) -
@@ -203,7 +203,7 @@ dd if=csf_spl.bin of=flash.bin bs=1 seek=${spl_dd_offset} conv=notrunc
 CSF "Blocks" line for csf_fit.txt can be generated as follows:
 ```
 # fitImage tree
-fit_block_base=$(printf "0x%x" $(( $(sed -n "/CONFIG_SYS_TEXT_BASE=/ s@.*=@@p" .config) - $(sed -n "/CONFIG_FIT_EXTERNAL_OFFSET=/ s@.*=@@p" .config) - 0x200 - 0x40)) )
+fit_block_base=$(printf "0x%x" $(( $(sed -n "/CONFIG_TEXT_BASE=/ s@.*=@@p" .config) - $(sed -n "/CONFIG_FIT_EXTERNAL_OFFSET=/ s@.*=@@p" .config) - 0x200 - 0x40)) )
 fit_block_offset=$(printf "0x%s" $(fdtget -t x u-boot.dtb /binman/imx-boot/uboot offset))
 fit_block_size=$(printf "0x%x" $(( ( $(fdtdump u-boot.itb 2>/dev/null | sed -n "/^...totalsize:/ s@.*\(0x[0-9a-f]\+\).*@\1@p") + 0x1000 - 0x1 ) & ~(0x1000 - 0x1) + 0x20 )) )
 sed -i "/Blocks = / s@.*@  Blocks = $fit_block_base $fit_block_offset $fit_block_size \"flash.bin\", \\\\@" csf_fit.tmp
diff --git a/doc/uImage.FIT/howto.txt b/doc/uImage.FIT/howto.txt
index 019dda24a08..6dbd17dc8ca 100644
--- a/doc/uImage.FIT/howto.txt
+++ b/doc/uImage.FIT/howto.txt
@@ -70,6 +70,12 @@ The SPL also records to a DT all additional images (called loadables) which are
 loaded. The information about loadables locations is passed via the DT node with
 fit-images name.
 
+Finally, if there are multiple xPL phases (e.g. SPL, VPL), images can be marked
+as intended for a particular phase using the 'phase' property. For example, if
+fit_image_load() is called with image_ph(IH_PHASE_SPL, IH_TYPE_FIRMWARE), then
+only the image listed into the "firmware" property where phase is set to "spl"
+will be loaded.
+
 Loadables Example
 -----------------
 Consider the following case for an ARM64 platform where U-Boot runs in EL2
diff --git a/doc/uImage.FIT/source_file_format.txt b/doc/uImage.FIT/source_file_format.txt
index 0a03c942bda..4640e38e3cc 100644
--- a/doc/uImage.FIT/source_file_format.txt
+++ b/doc/uImage.FIT/source_file_format.txt
@@ -190,6 +190,9 @@ the '/images' node should have the following layout:
     Xilinx Zynq UltraScale+ (ZymqMP) device.
     "u-boot,zynqmp-fpga-enc" - encrypted FPGA bitstream for Xilinx Zynq
     UltraScale+ (ZynqMP) device.
+  - phase : U-Boot phase for which the image is intended.
+    "spl" - image is an SPL image
+    "u-boot" - image is a U-Boot image
 
   Optional nodes:
   - hash-1 : Each hash sub-node represents separate hash or checksum