diff options
Diffstat (limited to 'cpu')
63 files changed, 358 insertions, 621 deletions
diff --git a/cpu/74xx_7xx/config.mk b/cpu/74xx_7xx/config.mk index 417d99f33b..324f62b836 100644 --- a/cpu/74xx_7xx/config.mk +++ b/cpu/74xx_7xx/config.mk @@ -23,4 +23,4 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing -PLATFORM_CPPFLAGS += -DCONFIG_74xx_7xx -ffixed-r2 -ffixed-r29 -mstring +PLATFORM_CPPFLAGS += -DCONFIG_74xx_7xx -ffixed-r2 -mstring diff --git a/cpu/arm1136/start.S b/cpu/arm1136/start.S index 17c7a83491..8b765f1e80 100644 --- a/cpu/arm1136/start.S +++ b/cpu/arm1136/start.S @@ -35,6 +35,25 @@ #endif .globl _start _start: b reset +#ifdef CONFIG_ONENAND_IPL + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + ldr pc, _hang + +_hang: + .word do_hang + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 + .word 0x12345678 /* now 16*4=64 */ +#else ldr pc, _undefined_instruction ldr pc, _software_interrupt ldr pc, _prefetch_abort @@ -51,6 +70,7 @@ _not_used: .word not_used _irq: .word irq _fiq: .word fiq _pad: .word 0x12345678 /* now 16*4=64 */ +#endif /* CONFIG_ONENAND_IPL */ .global _end_vect _end_vect: @@ -139,7 +159,9 @@ relocate: /* relocate U-Boot to RAM */ adr r0, _start /* r0 <- current position of code */ ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ cmp r0, r1 /* don't reloc during debug */ +#ifndef CONFIG_ONENAND_IPL beq stack_setup +#endif /* CONFIG_ONENAND_IPL */ ldr r2, _armboot_start ldr r3, _bss_start @@ -156,26 +178,36 @@ copy_loop: /* Set up the stack */ stack_setup: ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ +#ifdef CONFIG_ONENAND_IPL + sub sp, r0, #128 /* leave 32 words for abort-stack */ +#else sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */ #ifdef CONFIG_USE_IRQ sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif sub sp, r0, #12 /* leave 3 words for abort-stack */ +#endif /* CONFIG_ONENAND_IPL */ clear_bss: ldr r0, _bss_start /* find start of bss segment */ ldr r1, _bss_end /* stop here */ mov r2, #0x00000000 /* clear */ +#ifndef CONFIG_ONENAND_IPL clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 cmp r0, r1 bne clbss_l +#endif ldr pc, _start_armboot +#ifdef CONFIG_ONENAND_IPL +_start_armboot: .word start_oneboot +#else _start_armboot: .word start_armboot +#endif /* @@ -214,6 +246,8 @@ cpu_init_crit: bl lowlevel_init /* go setup pll,mux,memory */ mov lr, ip /* restore link */ mov pc, lr /* back to my caller */ + +#ifndef CONFIG_ONENAND_IPL /* ************************************************************************* * @@ -326,10 +360,17 @@ cpu_init_crit: .macro get_fiq_stack @ setup FIQ stack ldr sp, FIQ_STACK_START .endm +#endif /* CONFIG_ONENAND_IPL */ /* * exception handlers */ +#ifdef CONFIG_ONENAND_IPL + .align 5 +do_hang: + ldr sp, _TEXT_BASE /* use 32 words about stack */ + bl hang /* hang and never return */ +#else /* !CONFIG_ONENAND IPL */ .align 5 undefined_instruction: get_bad_stack @@ -415,3 +456,4 @@ rstctl: .word PM_RSTCTRL_WKUP #endif +#endif /* CONFIG_ONENAND_IPL */ diff --git a/cpu/at32ap/hsdramc.c b/cpu/at32ap/hsdramc.c index a936e03166..1fcfe75d74 100644 --- a/cpu/at32ap/hsdramc.c +++ b/cpu/at32ap/hsdramc.c @@ -38,6 +38,10 @@ unsigned long sdram_init(const struct sdram_info *info) unsigned long bus_hz; unsigned int i; + if (!info->refresh_period) + panic("ERROR: SDRAM refresh period == 0. " + "Please update the board code\n"); + tmp = (HSDRAMC1_BF(NC, info->col_bits - 8) | HSDRAMC1_BF(NR, info->row_bits - 11) | HSDRAMC1_BF(NB, info->bank_bits - 1) @@ -113,7 +117,7 @@ unsigned long sdram_init(const struct sdram_info *info) * 15.6 us is a typical value for a burst of length one */ bus_hz = get_sdram_clk_rate(); - hsdramc1_writel(TR, (156 * (bus_hz / 1000)) / 10000); + hsdramc1_writel(TR, info->refresh_period); printf("SDRAM: %u MB at address 0x%08lx\n", sdram_size >> 20, info->phys_addr); diff --git a/cpu/bf533/Makefile b/cpu/bf533/Makefile index dd4f299acd..ad48f1c5c1 100644 --- a/cpu/bf533/Makefile +++ b/cpu/bf533/Makefile @@ -28,12 +28,12 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a -START = start.o start1.o interrupt.o cache.o flush.o init_sdram.o +SOBJS = start.o start1.o interrupt.o cache.o flush.o init_sdram.o COBJS = cpu.o traps.o ints.o serial.o interrupts.o video.o EXTRA = init_sdram_bootrom_initblock.o -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) START := $(addprefix $(obj),$(START)) diff --git a/cpu/bf533/bf533_serial.h b/cpu/bf533/bf533_serial.h index 25b96a9f69..9970b723d5 100644 --- a/cpu/bf533/bf533_serial.h +++ b/cpu/bf533/bf533_serial.h @@ -49,8 +49,8 @@ #include <asm/blackfin.h> #define SYNC_ALL __asm__ __volatile__ ("ssync;\n") -#define ACCESS_LATCH *pUART_LCR |= UART_LCR_DLAB; -#define ACCESS_PORT_IER *pUART_LCR &= (~UART_LCR_DLAB); +#define ACCESS_LATCH *pUART_LCR |= DLAB; +#define ACCESS_PORT_IER *pUART_LCR &= (~DLAB); void serial_setbrg(void); static void local_put_char(char ch); diff --git a/cpu/bf533/cache.S b/cpu/bf533/cache.S index 03aebe4b4c..d9015c6d1a 100644 --- a/cpu/bf533/cache.S +++ b/cpu/bf533/cache.S @@ -2,6 +2,7 @@ #include <asm/linkage.h> #include <config.h> #include <asm/blackfin.h> +#include <asm/mach-common/bits/mpu.h> .text .align 2 @@ -11,7 +12,7 @@ ENTRY(_blackfin_icache_flush_range) P0 = R2; P1 = R1; CSYNC; -1: + 1: IFLUSH[P0++]; CC = P0 < P1(iu); IF CC JUMP 1b(bp); diff --git a/cpu/bf533/config.mk b/cpu/bf533/config.mk index 6a713c3f51..2caa3cc7d3 100644 --- a/cpu/bf533/config.mk +++ b/cpu/bf533/config.mk @@ -24,4 +24,4 @@ # MA 02110-1301 USA # -PLATFORM_RELFLAGS += -mcpu=bf533 -ffixed-P5 +PLATFORM_RELFLAGS += -mcpu=bf533 diff --git a/cpu/bf533/cpu.c b/cpu/bf533/cpu.c index 8118861f8d..edb771e33c 100644 --- a/cpu/bf533/cpu.c +++ b/cpu/bf533/cpu.c @@ -40,7 +40,7 @@ extern unsigned int dcplb_table[page_descriptor_table_size][2]; int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { - __asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_ISRAM) + __asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_INST_SRAM) ); return 0; @@ -100,22 +100,18 @@ void icache_enable(void) } - cli(); - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB; - sync(); - sti(); + SSYNC(); } void icache_disable(void) { - cli(); - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB); - sync(); - sti(); + SSYNC(); } int icache_status(void) @@ -175,14 +171,12 @@ void dcache_enable(void) } } - cli(); temp = *(unsigned int *)DMEM_CONTROL; - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)DMEM_CONTROL = ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | temp; - sync(); - sti(); + SSYNC(); } void dcache_disable(void) @@ -190,13 +184,11 @@ void dcache_disable(void) unsigned int *I0, *I1; int i; - cli(); - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)DMEM_CONTROL &= ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0); - sync(); - sti(); + SSYNC(); /* after disable dcache, * clear it so we don't confuse the next application diff --git a/cpu/bf533/init_sdram.S b/cpu/bf533/init_sdram.S index e1a8e2ff88..67a99e46bd 100644 --- a/cpu/bf533/init_sdram.S +++ b/cpu/bf533/init_sdram.S @@ -4,6 +4,10 @@ #include <config.h> #include <asm/blackfin.h> #include <asm/mem_init.h> +#include <asm/mach-common/bits/bootrom.h> +#include <asm/mach-common/bits/ebiu.h> +#include <asm/mach-common/bits/pll.h> +#include <asm/mach-common/bits/uart.h> .global init_sdram; #if (CONFIG_CCLK_DIV == 1) diff --git a/cpu/bf533/init_sdram_bootrom_initblock.S b/cpu/bf533/init_sdram_bootrom_initblock.S index 99ed920328..8694ca2c2c 100644 --- a/cpu/bf533/init_sdram_bootrom_initblock.S +++ b/cpu/bf533/init_sdram_bootrom_initblock.S @@ -4,6 +4,10 @@ #include <config.h> #include <asm/blackfin.h> #include <asm/mem_init.h> +#include <asm/mach-common/bits/bootrom.h> +#include <asm/mach-common/bits/ebiu.h> +#include <asm/mach-common/bits/pll.h> +#include <asm/mach-common/bits/uart.h> .global init_sdram; #if (CONFIG_CCLK_DIV == 1) diff --git a/cpu/bf533/interrupt.S b/cpu/bf533/interrupt.S index c356d53aa6..7556ec9fbd 100644 --- a/cpu/bf533/interrupt.S +++ b/cpu/bf533/interrupt.S @@ -42,9 +42,7 @@ #define ASSEMBLY #include <config.h> #include <asm/blackfin.h> -#include <asm/hw_irq.h> #include <asm/entry.h> -#include <asm/blackfin_defs.h> .global _blackfin_irq_panic; @@ -55,7 +53,7 @@ .global _evt_emulation _evt_emulation: SAVE_CONTEXT - r0 = IRQ_EMU; + r0 = 0; r1 = seqstat; sp += -12; call _blackfin_irq_panic; @@ -66,7 +64,7 @@ _evt_emulation: .global _evt_nmi _evt_nmi: SAVE_CONTEXT - r0 = IRQ_NMI; + r0 = 2; r1 = RETN; sp += -12; call _blackfin_irq_panic; @@ -88,7 +86,7 @@ _trap: .global _evt_rst _evt_rst: SAVE_CONTEXT - r0 = IRQ_RST; + r0 = 1; r1 = RETN; sp += -12; call _do_reset; @@ -98,7 +96,7 @@ _evt_rst_exit: rtn; irq_panic: - r0 = IRQ_EVX; + r0 = 3; r1 = sp; sp += -12; call _blackfin_irq_panic; @@ -115,7 +113,7 @@ _evt_ivhw_exit: .global _evt_timer _evt_timer: SAVE_CONTEXT - r0 = IRQ_CORETMR; + r0 = 6; sp += -12; /* Polling method used now. */ /* call timer_int; */ diff --git a/cpu/bf533/interrupts.c b/cpu/bf533/interrupts.c index 14d06cf8df..3d1c3bc8c2 100644 --- a/cpu/bf533/interrupts.c +++ b/cpu/bf533/interrupts.c @@ -35,8 +35,6 @@ */ #include <common.h> -#include <asm/machdep.h> -#include <asm/irq.h> #include <config.h> #include <asm/blackfin.h> #include "cpu.h" @@ -72,12 +70,10 @@ ulong get_tbclk(void) void enable_interrupts(void) { - restore_flags(int_flag); } int disable_interrupts(void) { - save_and_cli(int_flag); return 1; } diff --git a/cpu/bf533/ints.c b/cpu/bf533/ints.c index 55866896a0..05d9a1b67e 100644 --- a/cpu/bf533/ints.c +++ b/cpu/bf533/ints.c @@ -39,12 +39,9 @@ #include <common.h> #include <linux/stddef.h> #include <asm/system.h> -#include <asm/irq.h> #include <asm/traps.h> #include <asm/io.h> #include <asm/errno.h> -#include <asm/machdep.h> -#include <asm/setup.h> #include <asm/blackfin.h> #include "cpu.h" @@ -61,42 +58,40 @@ void blackfin_irq_panic(int reason, struct pt_regs *regs) void blackfin_init_IRQ(void) { - *(unsigned volatile long *)(SIC_IMASK) = SIC_UNMASK_ALL; - cli(); + *(unsigned volatile long *)(SIC_IMASK) = 0; #ifndef CONFIG_KGDB - *(unsigned volatile long *)(EVT_EMULATION_ADDR) = 0x0; + *(unsigned volatile long *)(EVT1) = 0x0; #endif - *(unsigned volatile long *)(EVT_NMI_ADDR) = + *(unsigned volatile long *)(EVT2) = (unsigned volatile long)evt_nmi; - *(unsigned volatile long *)(EVT_EXCEPTION_ADDR) = + *(unsigned volatile long *)(EVT3) = (unsigned volatile long)trap; - *(unsigned volatile long *)(EVT_HARDWARE_ERROR_ADDR) = + *(unsigned volatile long *)(EVT5) = (unsigned volatile long)evt_ivhw; - *(unsigned volatile long *)(EVT_RESET_ADDR) = + *(unsigned volatile long *)(EVT0) = (unsigned volatile long)evt_rst; - *(unsigned volatile long *)(EVT_TIMER_ADDR) = + *(unsigned volatile long *)(EVT6) = (unsigned volatile long)evt_timer; - *(unsigned volatile long *)(EVT_IVG7_ADDR) = + *(unsigned volatile long *)(EVT7) = (unsigned volatile long)evt_evt7; - *(unsigned volatile long *)(EVT_IVG8_ADDR) = + *(unsigned volatile long *)(EVT8) = (unsigned volatile long)evt_evt8; - *(unsigned volatile long *)(EVT_IVG9_ADDR) = + *(unsigned volatile long *)(EVT9) = (unsigned volatile long)evt_evt9; - *(unsigned volatile long *)(EVT_IVG10_ADDR) = + *(unsigned volatile long *)(EVT10) = (unsigned volatile long)evt_evt10; - *(unsigned volatile long *)(EVT_IVG11_ADDR) = + *(unsigned volatile long *)(EVT11) = (unsigned volatile long)evt_evt11; - *(unsigned volatile long *)(EVT_IVG12_ADDR) = + *(unsigned volatile long *)(EVT12) = (unsigned volatile long)evt_evt12; - *(unsigned volatile long *)(EVT_IVG13_ADDR) = + *(unsigned volatile long *)(EVT13) = (unsigned volatile long)evt_evt13; - *(unsigned volatile long *)(EVT_IVG14_ADDR) = + *(unsigned volatile long *)(EVT14) = (unsigned volatile long)evt_system_call; - *(unsigned volatile long *)(EVT_IVG15_ADDR) = + *(unsigned volatile long *)(EVT15) = (unsigned volatile long)evt_soft_int1; *(volatile unsigned long *)ILAT = 0; asm("csync;"); - sti(); *(volatile unsigned long *)IMASK = 0xffbf; asm("csync;"); } diff --git a/cpu/bf533/serial.c b/cpu/bf533/serial.c index 8ac6e3ff64..05fcfcccce 100644 --- a/cpu/bf533/serial.c +++ b/cpu/bf533/serial.c @@ -43,14 +43,12 @@ */ #include <common.h> -#include <asm/irq.h> #include <asm/system.h> -#include <asm/segment.h> #include <asm/bitops.h> #include <asm/delay.h> -#include <asm/uaccess.h> #include <asm/io.h> #include "bf533_serial.h" +#include <asm/mach-common/bits/uart.h> DECLARE_GLOBAL_DATA_PTR; @@ -85,30 +83,30 @@ void serial_setbrg(void) } /* Enable UART */ - *pUART_GCTL |= UART_GCTL_UCEN; - sync(); + *pUART_GCTL |= UCEN; + SSYNC(); /* Set DLAB in LCR to Access DLL and DLH */ ACCESS_LATCH; - sync(); + SSYNC(); *pUART_DLL = hw_baud_table[i].dl_low; - sync(); + SSYNC(); *pUART_DLH = hw_baud_table[i].dl_high; - sync(); + SSYNC(); /* Clear DLAB in LCR to Access THR RBR IER */ ACCESS_PORT_IER; - sync(); + SSYNC(); /* Enable ERBFI and ELSI interrupts * to poll SIC_ISR register*/ - *pUART_IER = UART_IER_ELSI | UART_IER_ERBFI | UART_IER_ETBEI; - sync(); + *pUART_IER = ELSI | ERBFI | ETBEI; + SSYNC(); /* Set LCR to Word Lengh 8-bit word select */ - *pUART_LCR = UART_LCR_WLS8; - sync(); + *pUART_LCR = WLS_8; + SSYNC(); return; } @@ -121,14 +119,14 @@ int serial_init(void) void serial_putc(const char c) { - if ((*pUART_LSR) & UART_LSR_TEMT) { + if ((*pUART_LSR) & TEMT) { if (c == '\n') serial_putc('\r'); local_put_char(c); } - while (!((*pUART_LSR) & UART_LSR_TEMT)) + while (!((*pUART_LSR) & TEMT)) SYNC_ALL; return; @@ -136,7 +134,7 @@ void serial_putc(const char c) int serial_tstc(void) { - if (*pUART_LSR & UART_LSR_DR) + if (*pUART_LSR & DR) return 1; else return 0; @@ -149,14 +147,14 @@ int serial_getc(void) int ret; /* Poll for RX Interrupt */ - while (!((isr_val = - *(volatile unsigned long *)SIC_ISR) & IRQ_UART_RX_BIT)) ; + while (!serial_tstc()) + continue; asm("csync;"); uart_lsr_val = *pUART_LSR; /* Clear status bit */ uart_rbr_val = *pUART_RBR; /* getc() */ - if (isr_val & IRQ_UART_ERROR_BIT) { + if (uart_lsr_val & (OE|PE|FE|BI)) { ret = -1; } else { ret = uart_rbr_val & 0xff; @@ -177,19 +175,12 @@ static void local_put_char(char ch) int flags = 0; unsigned long isr_val; - save_and_cli(flags); - /* Poll for TX Interruput */ - while (!((isr_val = *pSIC_ISR) & IRQ_UART_TX_BIT)) ; + while (!(*pUART_LSR & THRE)) + continue; asm("csync;"); *pUART_THR = ch; /* putc() */ - if (isr_val & IRQ_UART_ERROR_BIT) { - printf("?"); - } - - restore_flags(flags); - return; } diff --git a/cpu/bf533/start.S b/cpu/bf533/start.S index 67a60cf21e..c32fef6163 100644 --- a/cpu/bf533/start.S +++ b/cpu/bf533/start.S @@ -41,19 +41,16 @@ #include <config.h> #include <asm/blackfin.h> +#include <asm/mach-common/bits/core.h> +#include <asm/mach-common/bits/dma.h> +#include <asm/mach-common/bits/pll.h> + .global _stext; .global __bss_start; .global start; .global _start; -.global _rambase; -.global _ramstart; -.global _ramend; -.global _bf533_data_dest; -.global _bf533_data_size; .global edata; -.global _initialize; .global _exit; -.global flashdataend; .global init_sdram; #if (CONFIG_CCLK_DIV == 1) @@ -143,8 +140,8 @@ no_soft_reset: nop; /* Clear EVT registers */ - p0.h = (EVT_EMULATION_ADDR >> 16); - p0.l = (EVT_EMULATION_ADDR & 0xFFFF); + p0.h = (EVT0 >> 16); + p0.l = (EVT0 & 0xFFFF); p0 += 8; p1 = 14; r1 = 0; @@ -200,8 +197,8 @@ loop1: */ /* To keep ourselves in the supervisor mode */ - p0.l = (EVT_IVG15_ADDR & 0xFFFF); - p0.h = (EVT_IVG15_ADDR >> 16); + p0.l = (EVT15 & 0xFFFF); + p0.h = (EVT15 >> 16); p1.l = _real_start; p1.h = _real_start; @@ -209,8 +206,8 @@ loop1: p0.l = (IMASK & 0xFFFF); p0.h = (IMASK >> 16); - r0.l = LO(IVG15_POS); - r0.h = HI(IVG15_POS); + r0.l = LO(EVT_IVG15); + r0.h = HI(EVT_IVG15); [p0] = r0; raise 15; p0.l = WAIT_HERE; @@ -236,8 +233,8 @@ copy: R1.H = reset_end; R1.L = reset_end; R2 = R1 - R0; /* Count */ - R1.H = hi(L1_ISRAM); /* Destination Address (high) */ - R1.L = lo(L1_ISRAM); /* Destination Address (low) */ + R1.H = hi(L1_INST_SRAM); /* Destination Address (high) */ + R1.L = lo(L1_INST_SRAM); /* Destination Address (low) */ R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */ /* Destination DMAConfig Value (8-bit words) */ R4.L = (DI_EN | WNR | DMAEN); diff --git a/cpu/bf533/traps.c b/cpu/bf533/traps.c index 19b1fde41d..7e156d5110 100644 --- a/cpu/bf533/traps.c +++ b/cpu/bf533/traps.c @@ -36,14 +36,13 @@ #include <common.h> #include <linux/types.h> #include <asm/errno.h> -#include <asm/irq.h> #include <asm/system.h> #include <asm/traps.h> -#include <asm/machdep.h> #include "cpu.h" -#include <asm/arch/anomaly.h> #include <asm/cplb.h> #include <asm/io.h> +#include <asm/mach-common/bits/core.h> +#include <asm/mach-common/bits/mpu.h> void init_IRQ(void) { @@ -68,7 +67,7 @@ static unsigned int cplb_sizes[4] = void trap_c(struct pt_regs *regs) { unsigned int addr; - unsigned long trapnr = (regs->seqstat) & SEQSTAT_EXCAUSE; + unsigned long trapnr = (regs->seqstat) & EXCAUSE; unsigned int i, j, size, *I0, *I1; unsigned short data = 0; @@ -76,7 +75,7 @@ void trap_c(struct pt_regs *regs) /* 0x26 - Data CPLB Miss */ case VEC_CPLB_M: -#ifdef ANOMALY_05000261 +#if ANOMALY_05000261 /* * Work around an anomaly: if we see a new DCPLB fault, * return without doing anything. Then, @@ -118,16 +117,16 @@ void trap_c(struct pt_regs *regs) /* Turn the cache off */ if (data) { - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)DMEM_CONTROL &= ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0); - sync(); + SSYNC(); } else { - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB); - sync(); + SSYNC(); } if (data) { @@ -173,16 +172,16 @@ void trap_c(struct pt_regs *regs) /* Turn the cache back on */ if (data) { j = *(unsigned int *)DMEM_CONTROL; - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)DMEM_CONTROL = ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | j; - sync(); + SSYNC(); } else { - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB; - sync(); + SSYNC(); } break; diff --git a/cpu/bf537/Makefile b/cpu/bf537/Makefile index 8b0f9c0e93..06d1aae4e2 100644 --- a/cpu/bf537/Makefile +++ b/cpu/bf537/Makefile @@ -28,12 +28,12 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a -START = start.o start1.o interrupt.o cache.o flush.o init_sdram.o +SOBJS = start.o start1.o interrupt.o cache.o flush.o init_sdram.o COBJS = cpu.o traps.o ints.o serial.o interrupts.o video.o i2c.o EXTRA = init_sdram_bootrom_initblock.o -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) START := $(addprefix $(obj),$(START)) diff --git a/cpu/bf537/cache.S b/cpu/bf537/cache.S index 5bda5bf97f..d9015c6d1a 100644 --- a/cpu/bf537/cache.S +++ b/cpu/bf537/cache.S @@ -2,6 +2,7 @@ #include <asm/linkage.h> #include <config.h> #include <asm/blackfin.h> +#include <asm/mach-common/bits/mpu.h> .text .align 2 diff --git a/cpu/bf537/config.mk b/cpu/bf537/config.mk index 8a35789f13..fbbe75dede 100644 --- a/cpu/bf537/config.mk +++ b/cpu/bf537/config.mk @@ -24,4 +24,4 @@ # MA 02110-1301 USA # -PLATFORM_RELFLAGS += -mcpu=bf537 -ffixed-P5 +PLATFORM_RELFLAGS += -mcpu=bf537 diff --git a/cpu/bf537/cpu.c b/cpu/bf537/cpu.c index 62f603bdb0..7233908a07 100644 --- a/cpu/bf537/cpu.c +++ b/cpu/bf537/cpu.c @@ -40,7 +40,7 @@ extern unsigned int dcplb_table[page_descriptor_table_size][2]; int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { - __asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_ISRAM) + __asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_INST_SRAM) ); return 0; @@ -103,24 +103,20 @@ void icache_enable(void) } - cli(); - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB; - sync(); - sti(); + SSYNC(); } void icache_disable(void) { if ((*pCHIPID >> 28) < 2) return; - cli(); - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB); - sync(); - sti(); + SSYNC(); } int icache_status(void) @@ -180,14 +176,12 @@ void dcache_enable(void) } } - cli(); temp = *(unsigned int *)DMEM_CONTROL; - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)DMEM_CONTROL = ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | temp; - sync(); - sti(); + SSYNC(); } void dcache_disable(void) @@ -195,13 +189,11 @@ void dcache_disable(void) unsigned int *I0, *I1; int i; - cli(); - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)DMEM_CONTROL &= ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0); - sync(); - sti(); + SSYNC(); /* after disable dcache, * clear it so we don't confuse the next application diff --git a/cpu/bf537/i2c.c b/cpu/bf537/i2c.c index 0daba63b68..ab7dd388c9 100644 --- a/cpu/bf537/i2c.c +++ b/cpu/bf537/i2c.c @@ -21,53 +21,10 @@ #include <asm/blackfin.h> #include <i2c.h> #include <asm/io.h> +#include <asm/mach-common/bits/twi.h> DECLARE_GLOBAL_DATA_PTR; -#define bfin_read16(addr) ({ unsigned __v; \ - __asm__ __volatile__ (\ - "%0 = w[%1] (z);\n\t"\ - : "=d"(__v) : "a"(addr)); (unsigned short)__v; }) - -#define bfin_write16(addr,val) ({\ - __asm__ __volatile__ (\ - "w[%0] = %1;\n\t"\ - : : "a"(addr) , "d"(val) : "memory");}) - -/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ -#define bfin_read_TWI_CLKDIV() bfin_read16(TWI_CLKDIV) -#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI_CLKDIV,val) -#define bfin_read_TWI_CONTROL() bfin_read16(TWI_CONTROL) -#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI_CONTROL,val) -#define bfin_read_TWI_SLAVE_CTL() bfin_read16(TWI_SLAVE_CTL) -#define bfin_write_TWI_SLAVE_CTL(val) bfin_write16(TWI_SLAVE_CTL,val) -#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI_SLAVE_STAT) -#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT,val) -#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI_SLAVE_ADDR) -#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR,val) -#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI_MASTER_CTL) -#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL,val) -#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI_MASTER_STAT) -#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT,val) -#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI_MASTER_ADDR) -#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR,val) -#define bfin_read_TWI_INT_STAT() bfin_read16(TWI_INT_STAT) -#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI_INT_STAT,val) -#define bfin_read_TWI_INT_MASK() bfin_read16(TWI_INT_MASK) -#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI_INT_MASK,val) -#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI_FIFO_CTL) -#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI_FIFO_CTL,val) -#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI_FIFO_STAT) -#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI_FIFO_STAT,val) -#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI_XMT_DATA8) -#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI_XMT_DATA8,val) -#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI_XMT_DATA16) -#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16,val) -#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI_RCV_DATA8) -#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI_RCV_DATA8,val) -#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI_RCV_DATA16) -#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16,val) - #ifdef DEBUG_I2C #define PRINTD(fmt,args...) do { \ if (gd->have_console) \ diff --git a/cpu/bf537/init_sdram.S b/cpu/bf537/init_sdram.S index 897a5890ed..e9975000a2 100644 --- a/cpu/bf537/init_sdram.S +++ b/cpu/bf537/init_sdram.S @@ -4,6 +4,10 @@ #include <config.h> #include <asm/blackfin.h> #include <asm/mem_init.h> +#include <asm/mach-common/bits/bootrom.h> +#include <asm/mach-common/bits/ebiu.h> +#include <asm/mach-common/bits/pll.h> +#include <asm/mach-common/bits/uart.h> .global init_sdram; #if (BFIN_BOOT_MODE != BF537_UART_BOOT) diff --git a/cpu/bf537/init_sdram_bootrom_initblock.S b/cpu/bf537/init_sdram_bootrom_initblock.S index f9adbb9715..197b836067 100644 --- a/cpu/bf537/init_sdram_bootrom_initblock.S +++ b/cpu/bf537/init_sdram_bootrom_initblock.S @@ -4,6 +4,10 @@ #include <config.h> #include <asm/blackfin.h> #include <asm/mem_init.h> +#include <asm/mach-common/bits/bootrom.h> +#include <asm/mach-common/bits/ebiu.h> +#include <asm/mach-common/bits/pll.h> +#include <asm/mach-common/bits/uart.h> .global init_sdram; #if (BFIN_BOOT_MODE != BF537_UART_BOOT) diff --git a/cpu/bf537/interrupt.S b/cpu/bf537/interrupt.S index a71df55a93..fe850bf2e3 100644 --- a/cpu/bf537/interrupt.S +++ b/cpu/bf537/interrupt.S @@ -42,9 +42,7 @@ #define ASSEMBLY #include <config.h> #include <asm/blackfin.h> -#include <asm/hw_irq.h> #include <asm/entry.h> -#include <asm/blackfin_defs.h> .global _blackfin_irq_panic; @@ -55,7 +53,7 @@ .global _evt_emulation _evt_emulation: SAVE_CONTEXT - r0 = IRQ_EMU; + r0 = 0; r1 = seqstat; sp += -12; call _blackfin_irq_panic; @@ -66,7 +64,7 @@ _evt_emulation: .global _evt_nmi _evt_nmi: SAVE_CONTEXT - r0 = IRQ_NMI; + r0 = 2; r1 = RETN; sp += -12; call _blackfin_irq_panic; @@ -88,7 +86,7 @@ _trap: .global _evt_rst _evt_rst: SAVE_CONTEXT - r0 = IRQ_RST; + r0 = 1; r1 = RETN; sp += -12; call _do_reset; @@ -98,7 +96,7 @@ _evt_rst_exit: rtn; irq_panic: - r0 = IRQ_EVX; + r0 = 3; r1 = sp; sp += -12; call _blackfin_irq_panic; @@ -115,7 +113,7 @@ _evt_ivhw_exit: .global _evt_timer _evt_timer: SAVE_CONTEXT - r0 = IRQ_CORETMR; + r0 = 6; sp += -12; /* Polling method used now. */ /* call timer_int; */ diff --git a/cpu/bf537/interrupts.c b/cpu/bf537/interrupts.c index d2213b1156..853fa492c7 100644 --- a/cpu/bf537/interrupts.c +++ b/cpu/bf537/interrupts.c @@ -35,8 +35,6 @@ */ #include <common.h> -#include <asm/machdep.h> -#include <asm/irq.h> #include <config.h> #include <asm/blackfin.h> #include "cpu.h" @@ -72,12 +70,10 @@ ulong get_tbclk (void) void enable_interrupts(void) { - restore_flags(int_flag); } int disable_interrupts(void) { - save_and_cli(int_flag); return 1; } diff --git a/cpu/bf537/ints.c b/cpu/bf537/ints.c index 55866896a0..05d9a1b67e 100644 --- a/cpu/bf537/ints.c +++ b/cpu/bf537/ints.c @@ -39,12 +39,9 @@ #include <common.h> #include <linux/stddef.h> #include <asm/system.h> -#include <asm/irq.h> #include <asm/traps.h> #include <asm/io.h> #include <asm/errno.h> -#include <asm/machdep.h> -#include <asm/setup.h> #include <asm/blackfin.h> #include "cpu.h" @@ -61,42 +58,40 @@ void blackfin_irq_panic(int reason, struct pt_regs *regs) void blackfin_init_IRQ(void) { - *(unsigned volatile long *)(SIC_IMASK) = SIC_UNMASK_ALL; - cli(); + *(unsigned volatile long *)(SIC_IMASK) = 0; #ifndef CONFIG_KGDB - *(unsigned volatile long *)(EVT_EMULATION_ADDR) = 0x0; + *(unsigned volatile long *)(EVT1) = 0x0; #endif - *(unsigned volatile long *)(EVT_NMI_ADDR) = + *(unsigned volatile long *)(EVT2) = (unsigned volatile long)evt_nmi; - *(unsigned volatile long *)(EVT_EXCEPTION_ADDR) = + *(unsigned volatile long *)(EVT3) = (unsigned volatile long)trap; - *(unsigned volatile long *)(EVT_HARDWARE_ERROR_ADDR) = + *(unsigned volatile long *)(EVT5) = (unsigned volatile long)evt_ivhw; - *(unsigned volatile long *)(EVT_RESET_ADDR) = + *(unsigned volatile long *)(EVT0) = (unsigned volatile long)evt_rst; - *(unsigned volatile long *)(EVT_TIMER_ADDR) = + *(unsigned volatile long *)(EVT6) = (unsigned volatile long)evt_timer; - *(unsigned volatile long *)(EVT_IVG7_ADDR) = + *(unsigned volatile long *)(EVT7) = (unsigned volatile long)evt_evt7; - *(unsigned volatile long *)(EVT_IVG8_ADDR) = + *(unsigned volatile long *)(EVT8) = (unsigned volatile long)evt_evt8; - *(unsigned volatile long *)(EVT_IVG9_ADDR) = + *(unsigned volatile long *)(EVT9) = (unsigned volatile long)evt_evt9; - *(unsigned volatile long *)(EVT_IVG10_ADDR) = + *(unsigned volatile long *)(EVT10) = (unsigned volatile long)evt_evt10; - *(unsigned volatile long *)(EVT_IVG11_ADDR) = + *(unsigned volatile long *)(EVT11) = (unsigned volatile long)evt_evt11; - *(unsigned volatile long *)(EVT_IVG12_ADDR) = + *(unsigned volatile long *)(EVT12) = (unsigned volatile long)evt_evt12; - *(unsigned volatile long *)(EVT_IVG13_ADDR) = + *(unsigned volatile long *)(EVT13) = (unsigned volatile long)evt_evt13; - *(unsigned volatile long *)(EVT_IVG14_ADDR) = + *(unsigned volatile long *)(EVT14) = (unsigned volatile long)evt_system_call; - *(unsigned volatile long *)(EVT_IVG15_ADDR) = + *(unsigned volatile long *)(EVT15) = (unsigned volatile long)evt_soft_int1; *(volatile unsigned long *)ILAT = 0; asm("csync;"); - sti(); *(volatile unsigned long *)IMASK = 0xffbf; asm("csync;"); } diff --git a/cpu/bf537/serial.c b/cpu/bf537/serial.c index f7a2483ffb..3c6a37016d 100644 --- a/cpu/bf537/serial.c +++ b/cpu/bf537/serial.c @@ -43,14 +43,12 @@ */ #include <common.h> -#include <asm/irq.h> #include <asm/system.h> -#include <asm/segment.h> #include <asm/bitops.h> #include <asm/delay.h> -#include <asm/uaccess.h> #include <asm/io.h> #include "serial.h" +#include <asm/mach-common/bits/uart.h> DECLARE_GLOBAL_DATA_PTR; @@ -85,30 +83,30 @@ void serial_setbrg(void) } /* Enable UART */ - *pUART_GCTL |= UART_GCTL_UCEN; - sync(); + *pUART0_GCTL |= UCEN; + SSYNC(); /* Set DLAB in LCR to Access DLL and DLH */ ACCESS_LATCH; - sync(); + SSYNC(); - *pUART_DLL = hw_baud_table[i].dl_low; - sync(); - *pUART_DLH = hw_baud_table[i].dl_high; - sync(); + *pUART0_DLL = hw_baud_table[i].dl_low; + SSYNC(); + *pUART0_DLH = hw_baud_table[i].dl_high; + SSYNC(); /* Clear DLAB in LCR to Access THR RBR IER */ ACCESS_PORT_IER; - sync(); + SSYNC(); /* Enable ERBFI and ELSI interrupts * to poll SIC_ISR register*/ - *pUART_IER = UART_IER_ELSI | UART_IER_ERBFI | UART_IER_ETBEI; - sync(); + *pUART0_IER = ELSI | ERBFI | ETBEI; + SSYNC(); /* Set LCR to Word Lengh 8-bit word select */ - *pUART_LCR = UART_LCR_WLS8; - sync(); + *pUART0_LCR = WLS_8; + SSYNC(); return; } @@ -121,14 +119,14 @@ int serial_init(void) void serial_putc(const char c) { - if ((*pUART_LSR) & UART_LSR_TEMT) { + if ((*pUART0_LSR) & TEMT) { if (c == '\n') serial_putc('\r'); local_put_char(c); } - while (!((*pUART_LSR) & UART_LSR_TEMT)) + while (!((*pUART0_LSR) & TEMT)) SYNC_ALL; return; @@ -136,7 +134,7 @@ void serial_putc(const char c) int serial_tstc(void) { - if (*pUART_LSR & UART_LSR_DR) + if (*pUART0_LSR & DR) return 1; else return 0; @@ -149,14 +147,14 @@ int serial_getc(void) int ret; /* Poll for RX Interrupt */ - while (!((isr_val = - *(volatile unsigned long *)SIC_ISR) & IRQ_UART_RX_BIT)) ; + while (!serial_tstc()) + continue; asm("csync;"); - uart_lsr_val = *pUART_LSR; /* Clear status bit */ - uart_rbr_val = *pUART_RBR; /* getc() */ + uart_lsr_val = *pUART0_LSR; /* Clear status bit */ + uart_rbr_val = *pUART0_RBR; /* getc() */ - if (isr_val & IRQ_UART_ERROR_BIT) { + if (uart_lsr_val & (OE|PE|FE|BI)) { ret = -1; } else { ret = uart_rbr_val & 0xff; @@ -177,19 +175,12 @@ static void local_put_char(char ch) int flags = 0; unsigned long isr_val; - save_and_cli(flags); - /* Poll for TX Interruput */ - while (!((isr_val = *pSIC_ISR) & IRQ_UART_TX_BIT)) ; + while (!(*pUART0_LSR & THRE)) + continue; asm("csync;"); - *pUART_THR = ch; /* putc() */ - - if (isr_val & IRQ_UART_ERROR_BIT) { - printf("?"); - } - - restore_flags(flags); + *pUART0_THR = ch; /* putc() */ return; } diff --git a/cpu/bf537/serial.h b/cpu/bf537/serial.h index 76555c279d..e4e0b9aec6 100644 --- a/cpu/bf537/serial.h +++ b/cpu/bf537/serial.h @@ -49,8 +49,8 @@ #include <asm/blackfin.h> #define SYNC_ALL __asm__ __volatile__ ("ssync;\n") -#define ACCESS_LATCH *pUART_LCR |= UART_LCR_DLAB; -#define ACCESS_PORT_IER *pUART_LCR &= (~UART_LCR_DLAB); +#define ACCESS_LATCH *pUART0_LCR |= DLAB; +#define ACCESS_PORT_IER *pUART0_LCR &= (~DLAB); void serial_setbrg(void); static void local_put_char(char ch); diff --git a/cpu/bf537/start.S b/cpu/bf537/start.S index 4e02bcb9e5..a48f3c6c7b 100644 --- a/cpu/bf537/start.S +++ b/cpu/bf537/start.S @@ -41,19 +41,16 @@ #include <config.h> #include <asm/blackfin.h> +#include <asm/mach-common/bits/core.h> +#include <asm/mach-common/bits/dma.h> +#include <asm/mach-common/bits/pll.h> + .global _stext; .global __bss_start; .global start; .global _start; -.global _rambase; -.global _ramstart; -.global _ramend; -.global _bf533_data_dest; -.global _bf533_data_size; .global edata; -.global _initialize; .global _exit; -.global flashdataend; .global init_sdram; .global _icache_enable; .global _dcache_enable; @@ -151,8 +148,8 @@ no_soft_reset: nop; /* Clear EVT registers */ - p0.h = (EVT_EMULATION_ADDR >> 16); - p0.l = (EVT_EMULATION_ADDR & 0xFFFF); + p0.h = (EVT0 >> 16); + p0.l = (EVT0 & 0xFFFF); p0 += 8; p1 = 14; r1 = 0; @@ -291,8 +288,8 @@ postcopy: R1.H = (CFG_FLASH_BASE >> 16); R1.L = (CFG_FLASH_BASE & 0xFFFF); R0 = R0 + R1; /* Source Address */ - R1.H = hi(L1_ISRAM); /* Destination Address (high) */ - R1.L = lo(L1_ISRAM); /* Destination Address (low) */ + R1.H = hi(L1_INST_SRAM); /* Destination Address (high) */ + R1.L = lo(L1_INST_SRAM); /* Destination Address (low) */ R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */ /* Destination DMAConfig Value (8-bit words) */ R4.L = (DI_EN | WNR | DMAEN); @@ -415,8 +412,8 @@ loop1: */ /* To keep ourselves in the supervisor mode */ - p0.l = (EVT_IVG15_ADDR & 0xFFFF); - p0.h = (EVT_IVG15_ADDR >> 16); + p0.l = (EVT15 & 0xFFFF); + p0.h = (EVT15 >> 16); p1.l = _real_start; p1.h = _real_start; @@ -424,8 +421,8 @@ loop1: p0.l = (IMASK & 0xFFFF); p0.h = (IMASK >> 16); - r0.l = LO(IVG15_POS); - r0.h = HI(IVG15_POS); + r0.l = LO(EVT_IVG15); + r0.h = HI(EVT_IVG15); [p0] = r0; raise 15; p0.l = WAIT_HERE; @@ -495,8 +492,8 @@ copy: R1.H = reset_end; R1.L = reset_end; R2 = R1 - R0; /* Count */ - R1.H = hi(L1_ISRAM); /* Destination Address (high) */ - R1.L = lo(L1_ISRAM); /* Destination Address (low) */ + R1.H = hi(L1_INST_SRAM); /* Destination Address (high) */ + R1.L = lo(L1_INST_SRAM); /* Destination Address (low) */ R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */ R4.L = (DI_EN | WNR | DMAEN); /* Destination DMAConfig Value (8-bit words) */ diff --git a/cpu/bf537/traps.c b/cpu/bf537/traps.c index 4e18e27df4..51de322aed 100644 --- a/cpu/bf537/traps.c +++ b/cpu/bf537/traps.c @@ -36,14 +36,13 @@ #include <common.h> #include <linux/types.h> #include <asm/errno.h> -#include <asm/irq.h> #include <asm/system.h> #include <asm/traps.h> -#include <asm/machdep.h> #include "cpu.h" -#include <asm/arch/anomaly.h> #include <asm/cplb.h> #include <asm/io.h> +#include <asm/mach-common/bits/core.h> +#include <asm/mach-common/bits/mpu.h> void init_IRQ(void) { @@ -68,7 +67,7 @@ static unsigned int cplb_sizes[4] = void trap_c(struct pt_regs *regs) { unsigned int addr; - unsigned long trapnr = (regs->seqstat) & SEQSTAT_EXCAUSE; + unsigned long trapnr = (regs->seqstat) & EXCAUSE; unsigned int i, j, size, *I0, *I1; unsigned short data = 0; @@ -76,7 +75,7 @@ void trap_c(struct pt_regs *regs) /* 0x26 - Data CPLB Miss */ case VEC_CPLB_M: -#ifdef ANOMALY_05000261 +#if ANOMALY_05000261 /* * Work around an anomaly: if we see a new DCPLB fault, * return without doing anything. Then, @@ -118,16 +117,16 @@ void trap_c(struct pt_regs *regs) /* Turn the cache off */ if (data) { - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)DMEM_CONTROL &= ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0); - sync(); + SSYNC(); } else { - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB); - sync(); + SSYNC(); } if (data) { @@ -173,16 +172,16 @@ void trap_c(struct pt_regs *regs) /* Turn the cache back on */ if (data) { j = *(unsigned int *)DMEM_CONTROL; - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)DMEM_CONTROL = ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | j; - sync(); + SSYNC(); } else { - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB; - sync(); + SSYNC(); } break; diff --git a/cpu/bf561/Makefile b/cpu/bf561/Makefile index 29471694d9..418a4370eb 100644 --- a/cpu/bf561/Makefile +++ b/cpu/bf561/Makefile @@ -28,12 +28,12 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a -START = start.o start1.o interrupt.o cache.o flush.o init_sdram.o +SOBJS = start.o start1.o interrupt.o cache.o flush.o init_sdram.o COBJS = cpu.o traps.o ints.o serial.o interrupts.o video.o EXTRA = init_sdram_bootrom_initblock.o -SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) START := $(addprefix $(obj),$(START)) diff --git a/cpu/bf561/cache.S b/cpu/bf561/cache.S index 5bda5bf97f..d9015c6d1a 100644 --- a/cpu/bf561/cache.S +++ b/cpu/bf561/cache.S @@ -2,6 +2,7 @@ #include <asm/linkage.h> #include <config.h> #include <asm/blackfin.h> +#include <asm/mach-common/bits/mpu.h> .text .align 2 diff --git a/cpu/bf561/config.mk b/cpu/bf561/config.mk index f4dc04bfc9..3628a026b0 100644 --- a/cpu/bf561/config.mk +++ b/cpu/bf561/config.mk @@ -24,4 +24,4 @@ # MA 02110-1301 USA # -PLATFORM_RELFLAGS += -mcpu=bf561 -ffixed-P5 +PLATFORM_RELFLAGS += -mcpu=bf561 diff --git a/cpu/bf561/cpu.c b/cpu/bf561/cpu.c index 5b907cd1ef..e0dd2f5ea8 100644 --- a/cpu/bf561/cpu.c +++ b/cpu/bf561/cpu.c @@ -40,7 +40,7 @@ extern unsigned int dcplb_table[page_descriptor_table_size][2]; int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { - __asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_ISRAM) + __asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_INST_SRAM) ); return 0; @@ -100,22 +100,18 @@ void icache_enable(void) } - cli(); - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB; - sync(); - sti(); + SSYNC(); } void icache_disable(void) { - cli(); - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB); - sync(); - sti(); + SSYNC(); } int icache_status(void) @@ -175,14 +171,12 @@ void dcache_enable(void) } } - cli(); temp = *(unsigned int *)DMEM_CONTROL; - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)DMEM_CONTROL = ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | temp; - sync(); - sti(); + SSYNC(); } void dcache_disable(void) @@ -191,13 +185,11 @@ void dcache_disable(void) unsigned int *I0, *I1; int i; - cli(); - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)DMEM_CONTROL &= ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0); - sync(); - sti(); + SSYNC(); /* after disable dcache, clear it so we don't confuse the next application */ I0 = (unsigned int *)DCPLB_ADDR0; diff --git a/cpu/bf561/init_sdram.S b/cpu/bf561/init_sdram.S index d763f274f9..f5ccf30f9a 100644 --- a/cpu/bf561/init_sdram.S +++ b/cpu/bf561/init_sdram.S @@ -4,6 +4,10 @@ #include <config.h> #include <asm/blackfin.h> #include <asm/mem_init.h> +#include <asm/mach-common/bits/bootrom.h> +#include <asm/mach-common/bits/ebiu.h> +#include <asm/mach-common/bits/pll.h> +#include <asm/mach-common/bits/uart.h> .global init_sdram; #if (CONFIG_CCLK_DIV == 1) diff --git a/cpu/bf561/init_sdram_bootrom_initblock.S b/cpu/bf561/init_sdram_bootrom_initblock.S index 5e3c88ab6f..9cc5e78b04 100644 --- a/cpu/bf561/init_sdram_bootrom_initblock.S +++ b/cpu/bf561/init_sdram_bootrom_initblock.S @@ -4,6 +4,10 @@ #include <config.h> #include <asm/blackfin.h> #include <asm/mem_init.h> +#include <asm/mach-common/bits/bootrom.h> +#include <asm/mach-common/bits/ebiu.h> +#include <asm/mach-common/bits/pll.h> +#include <asm/mach-common/bits/uart.h> .global init_sdram; #if (CONFIG_CCLK_DIV == 1) diff --git a/cpu/bf561/interrupt.S b/cpu/bf561/interrupt.S index 21839ce7de..a10eaabe54 100644 --- a/cpu/bf561/interrupt.S +++ b/cpu/bf561/interrupt.S @@ -42,9 +42,7 @@ #define ASSEMBLY #include <config.h> #include <asm/blackfin.h> -#include <asm/hw_irq.h> #include <asm/entry.h> -#include <asm/blackfin_defs.h> .global _blackfin_irq_panic; @@ -55,7 +53,7 @@ .global _evt_emulation _evt_emulation: SAVE_CONTEXT - r0 = IRQ_EMU; + r0 = 0; r1 = seqstat; sp += -12; call _blackfin_irq_panic; @@ -66,7 +64,7 @@ _evt_emulation: .global _evt_nmi _evt_nmi: SAVE_CONTEXT - r0 = IRQ_NMI; + r0 = 2; r1 = RETN; sp += -12; call _blackfin_irq_panic; @@ -88,7 +86,7 @@ _trap: .global _evt_rst _evt_rst: SAVE_CONTEXT - r0 = IRQ_RST; + r0 = 1; r1 = RETN; sp += -12; call _do_reset; @@ -98,7 +96,7 @@ _evt_rst_exit: rtn; irq_panic: - r0 = IRQ_EVX; + r0 = 3; r1 = sp; sp += -12; call _blackfin_irq_panic; @@ -115,7 +113,7 @@ _evt_ivhw_exit: .global _evt_timer _evt_timer: SAVE_CONTEXT - r0 = IRQ_CORETMR; + r0 = 6; sp += -12; /* Polling method used now. */ /* call timer_int; */ diff --git a/cpu/bf561/interrupts.c b/cpu/bf561/interrupts.c index ecbc6addfc..78800611a3 100644 --- a/cpu/bf561/interrupts.c +++ b/cpu/bf561/interrupts.c @@ -35,8 +35,6 @@ */ #include <common.h> -#include <asm/machdep.h> -#include <asm/irq.h> #include <config.h> #include <asm/blackfin.h> #include "cpu.h" @@ -72,12 +70,10 @@ ulong get_tbclk(void) void enable_interrupts(void) { - restore_flags(int_flag); } int disable_interrupts(void) { - save_and_cli(int_flag); return 1; } diff --git a/cpu/bf561/ints.c b/cpu/bf561/ints.c index 27a38a3493..d6aa393170 100644 --- a/cpu/bf561/ints.c +++ b/cpu/bf561/ints.c @@ -39,12 +39,9 @@ #include <common.h> #include <linux/stddef.h> #include <asm/system.h> -#include <asm/irq.h> #include <asm/traps.h> #include <asm/io.h> #include <asm/errno.h> -#include <asm/machdep.h> -#include <asm/setup.h> #include <asm/blackfin.h> #include "cpu.h" @@ -61,42 +58,40 @@ void blackfin_irq_panic(int reason, struct pt_regs *regs) void blackfin_init_IRQ(void) { - *(unsigned volatile long *)(SIC_IMASK) = SIC_UNMASK_ALL; - cli(); + *(unsigned volatile long *)(SICA_IMASK0) = 0; #ifndef CONFIG_KGDB - *(unsigned volatile long *)(EVT_EMULATION_ADDR) = 0x0; + *(unsigned volatile long *)(EVT1) = 0x0; #endif - *(unsigned volatile long *)(EVT_NMI_ADDR) = + *(unsigned volatile long *)(EVT2) = (unsigned volatile long)evt_nmi; - *(unsigned volatile long *)(EVT_EXCEPTION_ADDR) = + *(unsigned volatile long *)(EVT3) = (unsigned volatile long)trap; - *(unsigned volatile long *)(EVT_HARDWARE_ERROR_ADDR) = + *(unsigned volatile long *)(EVT5) = (unsigned volatile long)evt_ivhw; - *(unsigned volatile long *)(EVT_RESET_ADDR) = + *(unsigned volatile long *)(EVT0) = (unsigned volatile long)evt_rst; - *(unsigned volatile long *)(EVT_TIMER_ADDR) = + *(unsigned volatile long *)(EVT6) = (unsigned volatile long)evt_timer; - *(unsigned volatile long *)(EVT_IVG7_ADDR) = + *(unsigned volatile long *)(EVT7) = (unsigned volatile long)evt_evt7; - *(unsigned volatile long *)(EVT_IVG8_ADDR) = + *(unsigned volatile long *)(EVT8) = (unsigned volatile long)evt_evt8; - *(unsigned volatile long *)(EVT_IVG9_ADDR) = + *(unsigned volatile long *)(EVT9) = (unsigned volatile long)evt_evt9; - *(unsigned volatile long *)(EVT_IVG10_ADDR) = + *(unsigned volatile long *)(EVT10) = (unsigned volatile long)evt_evt10; - *(unsigned volatile long *)(EVT_IVG11_ADDR) = + *(unsigned volatile long *)(EVT11) = (unsigned volatile long)evt_evt11; - *(unsigned volatile long *)(EVT_IVG12_ADDR) = + *(unsigned volatile long *)(EVT12) = (unsigned volatile long)evt_evt12; - *(unsigned volatile long *)(EVT_IVG13_ADDR) = + *(unsigned volatile long *)(EVT13) = (unsigned volatile long)evt_evt13; - *(unsigned volatile long *)(EVT_IVG14_ADDR) = + *(unsigned volatile long *)(EVT14) = (unsigned volatile long)evt_system_call; - *(unsigned volatile long *)(EVT_IVG15_ADDR) = + *(unsigned volatile long *)(EVT15) = (unsigned volatile long)evt_soft_int1; *(volatile unsigned long *)ILAT = 0; asm("csync;"); - sti(); *(volatile unsigned long *)IMASK = 0xffbf; asm("csync;"); } diff --git a/cpu/bf561/serial.c b/cpu/bf561/serial.c index bc5a4f5726..a398fd5f84 100644 --- a/cpu/bf561/serial.c +++ b/cpu/bf561/serial.c @@ -43,14 +43,12 @@ */ #include <common.h> -#include <asm/irq.h> #include <asm/system.h> -#include <asm/segment.h> #include <asm/bitops.h> #include <asm/delay.h> -#include <asm/uaccess.h> #include "serial.h" #include <asm/io.h> +#include <asm/mach-common/bits/uart.h> DECLARE_GLOBAL_DATA_PTR; @@ -85,32 +83,32 @@ void serial_setbrg(void) } /* Enable UART */ - *pUART_GCTL |= UART_GCTL_UCEN; - sync(); + *pUART_GCTL |= UCEN; + SSYNC(); /* Set DLAB in LCR to Access DLL and DLH */ ACCESS_LATCH; - sync(); + SSYNC(); *pUART_DLL = hw_baud_table[i].dl_low; - sync(); + SSYNC(); *pUART_DLH = hw_baud_table[i].dl_high; - sync(); + SSYNC(); /* Clear DLAB in LCR to Access THR RBR IER */ ACCESS_PORT_IER; - sync(); + SSYNC(); /* * Enable ERBFI and ELSI interrupts * to poll SIC_ISR register */ - *pUART_IER = UART_IER_ELSI | UART_IER_ERBFI | UART_IER_ETBEI; - sync(); + *pUART_IER = ELSI | ERBFI | ETBEI; + SSYNC(); /* Set LCR to Word Lengh 8-bit word select */ - *pUART_LCR = UART_LCR_WLS8; - sync(); + *pUART_LCR = WLS_8; + SSYNC(); return; } @@ -123,14 +121,14 @@ int serial_init(void) void serial_putc(const char c) { - if ((*pUART_LSR) & UART_LSR_TEMT) { + if ((*pUART_LSR) & TEMT) { if (c == '\n') serial_putc('\r'); local_put_char(c); } - while (!((*pUART_LSR) & UART_LSR_TEMT)) + while (!((*pUART_LSR) & TEMT)) SYNC_ALL; return; @@ -138,7 +136,7 @@ void serial_putc(const char c) int serial_tstc(void) { - if (*pUART_LSR & UART_LSR_DR) + if (*pUART_LSR & DR) return 1; else return 0; @@ -151,14 +149,14 @@ int serial_getc(void) int ret; /* Poll for RX Interrupt */ - while (!((isr_val = - *(volatile unsigned long *)SIC_ISR) & IRQ_UART_RX_BIT)) ; + while (!serial_tstc()) + continue; asm("csync;"); uart_lsr_val = *pUART_LSR; /* Clear status bit */ uart_rbr_val = *pUART_RBR; /* getc() */ - if (isr_val & IRQ_UART_ERROR_BIT) { + if (uart_lsr_val & (OE|PE|FE|BI)) { ret = -1; } else { ret = uart_rbr_val & 0xff; @@ -179,19 +177,12 @@ static void local_put_char(char ch) int flags = 0; unsigned long isr_val; - save_and_cli(flags); - /* Poll for TX Interruput */ - while (!((isr_val = *pSIC_ISR) & IRQ_UART_TX_BIT)) ; + while (!(*pUART_LSR & THRE)) + continue; asm("csync;"); *pUART_THR = ch; /* putc() */ - if (isr_val & IRQ_UART_ERROR_BIT) { - printf("?"); - } - - restore_flags(flags); - return; } diff --git a/cpu/bf561/serial.h b/cpu/bf561/serial.h index c1cbf36acf..647560c35c 100644 --- a/cpu/bf561/serial.h +++ b/cpu/bf561/serial.h @@ -49,8 +49,8 @@ #include <asm/blackfin.h> #define SYNC_ALL __asm__ __volatile__ ("ssync;\n") -#define ACCESS_LATCH *pUART_LCR |= UART_LCR_DLAB; -#define ACCESS_PORT_IER *pUART_LCR &= (~UART_LCR_DLAB); +#define ACCESS_LATCH *pUART_LCR |= DLAB; +#define ACCESS_PORT_IER *pUART_LCR &= (~DLAB); void serial_setbrg(void); static void local_put_char(char ch); diff --git a/cpu/bf561/start.S b/cpu/bf561/start.S index bd26cf32f6..6565de8cfd 100644 --- a/cpu/bf561/start.S +++ b/cpu/bf561/start.S @@ -41,17 +41,16 @@ #include <config.h> #include <asm/blackfin.h> +#include <asm/mach-common/bits/core.h> +#include <asm/mach-common/bits/dma.h> +#include <asm/mach-common/bits/pll.h> + .global _stext; .global __bss_start; .global start; .global _start; -.global _rambase; -.global _ramstart; -.global _ramend; .global edata; -.global _initialize; .global _exit; -.global flashdataend; .global init_sdram; .text @@ -127,16 +126,16 @@ no_soft_reset: nop; /* Clear EVT registers */ - p0.h = (EVT_EMULATION_ADDR >> 16); - p0.l = (EVT_EMULATION_ADDR & 0xFFFF); + p0.h = (EVT0 >> 16); + p0.l = (EVT0 & 0xFFFF); p0 += 8; p1 = 14; r1 = 0; LSETUP(4,4) lc0 = p1; [ p0 ++ ] = r1; - p0.h = hi(SIC_IWR); - p0.l = lo(SIC_IWR); + p0.h = hi(SICA_IWR0); + p0.l = lo(SICA_IWR0); r0.l = 0x1; w[p0] = r0.l; SSYNC; @@ -193,8 +192,8 @@ loop1: */ /* To keep ourselves in the supervisor mode */ - p0.l = (EVT_IVG15_ADDR & 0xFFFF); - p0.h = (EVT_IVG15_ADDR >> 16); + p0.l = (EVT15 & 0xFFFF); + p0.h = (EVT15 >> 16); p1.l = _real_start; p1.h = _real_start; @@ -202,8 +201,8 @@ loop1: p0.l = (IMASK & 0xFFFF); p0.h = (IMASK >> 16); - r0.l = LO(IVG15_POS); - r0.h = HI(IVG15_POS); + r0.l = LO(EVT_IVG15); + r0.h = HI(EVT_IVG15); [p0] = r0; raise 15; p0.l = WAIT_HERE; @@ -218,13 +217,6 @@ WAIT_HERE: _real_start: [ -- sp ] = reti; -#ifdef CONFIG_EZKIT561 - p0.l = (WDOG_CTL & 0xFFFF); - p0.h = (WDOG_CTL >> 16); - r0 = WATCHDOG_DISABLE(z); - w[p0] = r0; -#endif - /* DMA reset code to Hi of L1 SRAM */ copy: P1.H = hi(SYSMMR_BASE); /* P1 Points to the beginning of SYSTEM MMR Space */ @@ -235,37 +227,37 @@ copy: R1.H = reset_end; R1.L = reset_end; R2 = R1 - R0; /* Count */ - R1.H = hi(L1_ISRAM); /* Destination Address (high) */ - R1.L = lo(L1_ISRAM); /* Destination Address (low) */ + R1.H = hi(L1_INST_SRAM); /* Destination Address (high) */ + R1.L = lo(L1_INST_SRAM); /* Destination Address (low) */ R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */ R4.L = (DI_EN | WNR | DMAEN); /* Destination DMAConfig Value (8-bit words) */ DMA: R6 = 0x1 (Z); - W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */ - W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */ + W[P1+OFFSET_(IMDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */ + W[P1+OFFSET_(IMDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */ - [P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */ - W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */ + [P1+OFFSET_(IMDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */ + W[P1+OFFSET_(IMDMA_S0_X_COUNT)] = R2; /* Set Source Count */ /* Set Source DMAConfig = DMA Enable, Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */ - W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3; + W[P1+OFFSET_(IMDMA_S0_CONFIG)] = R3; - [P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */ - W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */ + [P1+OFFSET_(IMDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */ + W[P1+OFFSET_(IMDMA_D0_X_COUNT)] = R2; /* Set Destination Count */ /* Set Destination DMAConfig = DMA Enable, Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */ - W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4; + W[P1+OFFSET_(IMDMA_D0_CONFIG)] = R4; WAIT_DMA_DONE: - p0.h = hi(MDMA_D0_IRQ_STATUS); - p0.l = lo(MDMA_D0_IRQ_STATUS); + p0.h = hi(IMDMA_D0_IRQ_STATUS); + p0.l = lo(IMDMA_D0_IRQ_STATUS); R0 = W[P0](Z); CC = BITTST(R0, 0); if ! CC jump WAIT_DMA_DONE R0 = 0x1; - W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */ + W[P1+OFFSET_(IMDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */ /* Initialize BSS Section with 0 s */ p1.l = __bss_start; diff --git a/cpu/bf561/traps.c b/cpu/bf561/traps.c index 7e2dcd17ad..e35620c9ae 100644 --- a/cpu/bf561/traps.c +++ b/cpu/bf561/traps.c @@ -36,14 +36,13 @@ #include <common.h> #include <linux/types.h> #include <asm/errno.h> -#include <asm/irq.h> #include <asm/system.h> #include <asm/traps.h> -#include <asm/machdep.h> #include "cpu.h" -#include <asm/arch/anomaly.h> #include <asm/cplb.h> #include <asm/io.h> +#include <asm/mach-common/bits/core.h> +#include <asm/mach-common/bits/mpu.h> void init_IRQ(void) { @@ -68,7 +67,7 @@ static unsigned int cplb_sizes[4] = void trap_c(struct pt_regs *regs) { unsigned int addr; - unsigned long trapnr = (regs->seqstat) & SEQSTAT_EXCAUSE; + unsigned long trapnr = (regs->seqstat) & EXCAUSE; unsigned int i, j, size, *I0, *I1; unsigned short data = 0; @@ -76,7 +75,7 @@ void trap_c(struct pt_regs *regs) /* 0x26 - Data CPLB Miss */ case VEC_CPLB_M: -#ifdef ANOMALY_05000261 +#if ANOMALY_05000261 /* * Work around an anomaly: if we see a new DCPLB fault, return * without doing anything. Then, if we get the same fault again, @@ -118,16 +117,16 @@ void trap_c(struct pt_regs *regs) /* Turn the cache off */ if (data) { - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)DMEM_CONTROL &= ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0); - sync(); + SSYNC(); } else { - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB); - sync(); + SSYNC(); } if (data) { @@ -173,16 +172,16 @@ void trap_c(struct pt_regs *regs) /* Turn the cache back on */ if (data) { j = *(unsigned int *)DMEM_CONTROL; - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)DMEM_CONTROL = ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | j; - sync(); + SSYNC(); } else { - sync(); + SSYNC(); asm(" .align 8; "); *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB; - sync(); + SSYNC(); } break; diff --git a/cpu/mpc512x/config.mk b/cpu/mpc512x/config.mk index 8a07c5a3b6..5b7e1f2682 100644 --- a/cpu/mpc512x/config.mk +++ b/cpu/mpc512x/config.mk @@ -22,4 +22,4 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi PLATFORM_CPPFLAGS += -DCONFIG_MPC512X -DCONFIG_E300 \ - -ffixed-r2 -ffixed-r29 -msoft-float -mcpu=603e + -ffixed-r2 -msoft-float -mcpu=603e diff --git a/cpu/mpc512x/start.S b/cpu/mpc512x/start.S index 244c69b812..5a9d8687f5 100644 --- a/cpu/mpc512x/start.S +++ b/cpu/mpc512x/start.S @@ -479,52 +479,6 @@ get_pvr: mfspr r3, PVR blr -/*------------------------------------------------------------------------------- */ -/* Function: ppcDcbf */ -/* Description: Data Cache block flush */ -/* Input: r3 = effective address */ -/* Output: none. */ -/*------------------------------------------------------------------------------- */ - .globl ppcDcbf -ppcDcbf: - dcbf r0,r3 - blr - -/*------------------------------------------------------------------------------- */ -/* Function: ppcDcbi */ -/* Description: Data Cache block Invalidate */ -/* Input: r3 = effective address */ -/* Output: none. */ -/*------------------------------------------------------------------------------- */ - .globl ppcDcbi -ppcDcbi: - dcbi r0,r3 - blr - -/*-------------------------------------------------------------------------- - * Function: ppcDcbz - * Description: Data Cache block zero. - * Input: r3 = effective address - * Output: none. - *-------------------------------------------------------------------------- */ - - .globl ppcDcbz -ppcDcbz: - dcbz r0,r3 - blr - - .globl ppcDWstore -ppcDWstore: - lfd 1, 0(r4) - stfd 1, 0(r3) - blr - - .globl ppcDWload -ppcDWload: - lfd 1, 0(r3) - stfd 1, 0(r4) - blr - /*-------------------------------------------------------------------*/ /* diff --git a/cpu/mpc5xx/config.mk b/cpu/mpc5xx/config.mk index 64cd60071a..6d66c32bee 100644 --- a/cpu/mpc5xx/config.mk +++ b/cpu/mpc5xx/config.mk @@ -30,7 +30,7 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -PLATFORM_CPPFLAGS += -DCONFIG_5xx -ffixed-r2 -ffixed-r29 -mpowerpc -msoft-float +PLATFORM_CPPFLAGS += -DCONFIG_5xx -ffixed-r2 -mpowerpc -msoft-float # Use default linker script. Board port can override in board/*/config.mk LDSCRIPT := $(SRCTREE)/cpu/mpc5xx/u-boot.lds diff --git a/cpu/mpc5xxx/config.mk b/cpu/mpc5xxx/config.mk index 0df51babd7..b0ce2ee9e3 100644 --- a/cpu/mpc5xxx/config.mk +++ b/cpu/mpc5xxx/config.mk @@ -23,7 +23,7 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -PLATFORM_CPPFLAGS += -DCONFIG_MPC5xxx -ffixed-r2 -ffixed-r29 \ +PLATFORM_CPPFLAGS += -DCONFIG_MPC5xxx -ffixed-r2 \ -mstring -mcpu=603e -mmultiple # Use default linker script. Board port can override in board/*/config.mk diff --git a/cpu/mpc8220/config.mk b/cpu/mpc8220/config.mk index 8e3ba54287..5819048d01 100644 --- a/cpu/mpc8220/config.mk +++ b/cpu/mpc8220/config.mk @@ -23,7 +23,7 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -PLATFORM_CPPFLAGS += -DCONFIG_MPC8220 -ffixed-r2 -ffixed-r29 \ +PLATFORM_CPPFLAGS += -DCONFIG_MPC8220 -ffixed-r2 \ -mstring -mcpu=603e -mmultiple # Use default linker script. Board port can override in board/*/config.mk diff --git a/cpu/mpc824x/config.mk b/cpu/mpc824x/config.mk index 66207f4354..1bb0487bd3 100644 --- a/cpu/mpc824x/config.mk +++ b/cpu/mpc824x/config.mk @@ -23,7 +23,7 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing -PLATFORM_CPPFLAGS += -DCONFIG_MPC824X -ffixed-r2 -ffixed-r29 -mstring -mcpu=603e -msoft-float +PLATFORM_CPPFLAGS += -DCONFIG_MPC824X -ffixed-r2 -mstring -mcpu=603e -msoft-float # Use default linker script. Board port can override in board/*/config.mk LDSCRIPT := $(SRCTREE)/cpu/mpc824x/u-boot.lds diff --git a/cpu/mpc8260/config.mk b/cpu/mpc8260/config.mk index 683b6fbf2b..2cb027093b 100644 --- a/cpu/mpc8260/config.mk +++ b/cpu/mpc8260/config.mk @@ -23,7 +23,7 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -PLATFORM_CPPFLAGS += -DCONFIG_8260 -DCONFIG_CPM2 -ffixed-r2 -ffixed-r29 \ +PLATFORM_CPPFLAGS += -DCONFIG_8260 -DCONFIG_CPM2 -ffixed-r2 \ -mstring -mcpu=603e -mmultiple # Use default linker script. Board port can override in board/*/config.mk diff --git a/cpu/mpc83xx/config.mk b/cpu/mpc83xx/config.mk index ecf8a60bbe..2f0f1ce1ef 100644 --- a/cpu/mpc83xx/config.mk +++ b/cpu/mpc83xx/config.mk @@ -23,7 +23,7 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi PLATFORM_CPPFLAGS += -DCONFIG_MPC83XX -DCONFIG_E300 \ - -ffixed-r2 -ffixed-r29 -msoft-float + -ffixed-r2 -msoft-float # Use default linker script. Board port can override in board/*/config.mk LDSCRIPT := $(SRCTREE)/cpu/mpc83xx/u-boot.lds diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S index 1dfbf62239..309eb30e8e 100644 --- a/cpu/mpc83xx/start.S +++ b/cpu/mpc83xx/start.S @@ -840,40 +840,6 @@ get_pvr: mfspr r3, PVR blr -/*------------------------------------------------------------------------------- */ -/* Function: ppcDcbf */ -/* Description: Data Cache block flush */ -/* Input: r3 = effective address */ -/* Output: none. */ -/*------------------------------------------------------------------------------- */ - .globl ppcDcbf -ppcDcbf: - dcbf r0,r3 - blr - -/*------------------------------------------------------------------------------- */ -/* Function: ppcDcbi */ -/* Description: Data Cache block Invalidate */ -/* Input: r3 = effective address */ -/* Output: none. */ -/*------------------------------------------------------------------------------- */ - .globl ppcDcbi -ppcDcbi: - dcbi r0,r3 - blr - -/*-------------------------------------------------------------------------- - * Function: ppcDcbz - * Description: Data Cache block zero. - * Input: r3 = effective address - * Output: none. - *-------------------------------------------------------------------------- */ - - .globl ppcDcbz -ppcDcbz: - dcbz r0,r3 - blr - .globl ppcDWstore ppcDWstore: lfd 1, 0(r4) diff --git a/cpu/mpc85xx/config.mk b/cpu/mpc85xx/config.mk index 6121074349..f6df702e52 100644 --- a/cpu/mpc85xx/config.mk +++ b/cpu/mpc85xx/config.mk @@ -23,4 +23,5 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx -DCONFIG_E500 -ffixed-r2 -ffixed-r29 -Wa,-me500 -msoft-float -mno-string +PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx -DCONFIG_E500 -ffixed-r2 \ + -Wa,-me500 -msoft-float -mno-string diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c index 27de37afa8..952f30cf39 100644 --- a/cpu/mpc85xx/speed.c +++ b/cpu/mpc85xx/speed.c @@ -75,6 +75,9 @@ int get_clocks (void) get_sys_info (&sys_info); gd->cpu_clk = sys_info.freqProcessor; gd->bus_clk = sys_info.freqSystemBus; + gd->i2c1_clk = sys_info.freqSystemBus; + gd->i2c2_clk = sys_info.freqSystemBus; + #if defined(CONFIG_CPM2) gd->vco_out = 2*sys_info.freqSystemBus; gd->cpm_clk = gd->vco_out / 2; diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index e8e5eb297d..eb24dbc430 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -757,51 +757,6 @@ in32r: lwbrx r3,r0,r3 blr -/*------------------------------------------------------------------------------- */ -/* Function: ppcDcbf */ -/* Description: Data Cache block flush */ -/* Input: r3 = effective address */ -/* Output: none. */ -/*------------------------------------------------------------------------------- */ - .globl ppcDcbf -ppcDcbf: - dcbf r0,r3 - blr - -/*------------------------------------------------------------------------------- */ -/* Function: ppcDcbi */ -/* Description: Data Cache block Invalidate */ -/* Input: r3 = effective address */ -/* Output: none. */ -/*------------------------------------------------------------------------------- */ - .globl ppcDcbi -ppcDcbi: - dcbi r0,r3 - blr - -/*-------------------------------------------------------------------------- - * Function: ppcDcbz - * Description: Data Cache block zero. - * Input: r3 = effective address - * Output: none. - *-------------------------------------------------------------------------- */ - - .globl ppcDcbz -ppcDcbz: - dcbz r0,r3 - blr - -/*------------------------------------------------------------------------------- */ -/* Function: ppcSync */ -/* Description: Processor Synchronize */ -/* Input: none. */ -/* Output: none. */ -/*------------------------------------------------------------------------------- */ - .globl ppcSync -ppcSync: - sync - blr - /*------------------------------------------------------------------------------*/ /* diff --git a/cpu/mpc86xx/config.mk b/cpu/mpc86xx/config.mk index 3c54f4ad39..d767269ad3 100644 --- a/cpu/mpc86xx/config.mk +++ b/cpu/mpc86xx/config.mk @@ -23,4 +23,4 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx -ffixed-r2 -ffixed-r29 -mstring +PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx -ffixed-r2 -mstring diff --git a/cpu/mpc86xx/speed.c b/cpu/mpc86xx/speed.c index 4f7e8f17dc..7e884f8e01 100644 --- a/cpu/mpc86xx/speed.c +++ b/cpu/mpc86xx/speed.c @@ -105,6 +105,8 @@ int get_clocks(void) get_sys_info(&sys_info); gd->cpu_clk = sys_info.freqProcessor; gd->bus_clk = sys_info.freqSystemBus; + gd->i2c1_clk = sys_info.freqSystemBus; + gd->i2c2_clk = sys_info.freqSystemBus; if (gd->cpu_clk != 0) return 0; diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S index f163521a2f..c71c92659d 100644 --- a/cpu/mpc86xx/start.S +++ b/cpu/mpc86xx/start.S @@ -721,50 +721,6 @@ in32r: blr /* - * Function: ppcDcbf - * Description: Data Cache block flush - * Input: r3 = effective address - * Output: none. - */ - .globl ppcDcbf -ppcDcbf: - dcbf r0,r3 - blr - -/* - * Function: ppcDcbi - * Description: Data Cache block Invalidate - * Input: r3 = effective address - * Output: none. - */ - .globl ppcDcbi -ppcDcbi: - dcbi r0,r3 - blr - -/* - * Function: ppcDcbz - * Description: Data Cache block zero. - * Input: r3 = effective address - * Output: none. - */ - .globl ppcDcbz -ppcDcbz: - dcbz r0,r3 - blr - -/* - * Function: ppcSync - * Description: Processor Synchronize - * Input: none. - * Output: none. - */ - .globl ppcSync -ppcSync: - sync - blr - -/* * void relocate_code (addr_sp, gd, addr_moni) * * This "function" does not return, instead it continues in RAM @@ -780,7 +736,7 @@ relocate_code: mr r1, r3 /* Set new stack pointer */ mr r9, r4 /* Save copy of Global Data pointer */ - mr r29, r9 /* Save for DECLARE_GLOBAL_DATA_PTR */ + mr r2, r9 /* Save for DECLARE_GLOBAL_DATA_PTR */ mr r10, r5 /* Save copy of Destination Address */ mr r3, r5 /* Destination Address */ diff --git a/cpu/mpc8xx/config.mk b/cpu/mpc8xx/config.mk index bfa6625fa8..6031e7f76a 100644 --- a/cpu/mpc8xx/config.mk +++ b/cpu/mpc8xx/config.mk @@ -23,4 +23,4 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing -PLATFORM_CPPFLAGS += -DCONFIG_8xx -ffixed-r2 -ffixed-r29 -mstring -mcpu=860 -msoft-float +PLATFORM_CPPFLAGS += -DCONFIG_8xx -ffixed-r2 -mstring -mcpu=860 -msoft-float diff --git a/cpu/ppc4xx/config.mk b/cpu/ppc4xx/config.mk index 4fd510899c..311c97b732 100644 --- a/cpu/ppc4xx/config.mk +++ b/cpu/ppc4xx/config.mk @@ -22,7 +22,7 @@ # PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing -PLATFORM_CPPFLAGS += -DCONFIG_4xx -ffixed-r2 -ffixed-r29 -mstring -msoft-float +PLATFORM_CPPFLAGS += -DCONFIG_4xx -ffixed-r2 -mstring -msoft-float cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/') is440=$(shell grep CONFIG_440 $(TOPDIR)/include/$(cfg)) diff --git a/cpu/ppc4xx/denali_spd_ddr2.c b/cpu/ppc4xx/denali_spd_ddr2.c index 825bc2139c..60f89c97fc 100644 --- a/cpu/ppc4xx/denali_spd_ddr2.c +++ b/cpu/ppc4xx/denali_spd_ddr2.c @@ -3,7 +3,7 @@ * This SPD SDRAM detection code supports AMCC PPC44x CPUs with a Denali-core * DDR2 controller, specifically the 440EPx/GRx. * - * (C) Copyright 2007 + * (C) Copyright 2007-2008 * Larry Johnson, lrj@acm.org. * * Based primarily on cpu/ppc4xx/4xx_spd_ddr2.c, which is... @@ -77,10 +77,10 @@ * memory. * * If at some time this restriction doesn't apply anymore, just define - * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup + * CONFIG_4xx_DCACHE in the board config file and this code should setup * everything correctly. */ -#if defined(CFG_ENABLE_SDRAM_CACHE) +#if defined(CONFIG_4xx_DCACHE) #define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */ #else #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */ diff --git a/cpu/ppc4xx/ndfc.c b/cpu/ppc4xx/ndfc.c index ec1b38cffa..9e2229daf9 100644 --- a/cpu/ppc4xx/ndfc.c +++ b/cpu/ppc4xx/ndfc.c @@ -121,8 +121,8 @@ static int ndfc_calculate_ecc(struct mtd_info *mtdinfo, /* The NDFC uses Smart Media (SMC) bytes order */ - ecc_code[0] = p[2]; - ecc_code[1] = p[1]; + ecc_code[0] = p[1]; + ecc_code[1] = p[2]; ecc_code[2] = p[3]; return 0; diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 77c2aa4117..d8df67b0da 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -110,6 +110,10 @@ # endif #endif /* CFG_INIT_DCACHE_CS */ +#if (defined(CFG_INIT_RAM_DCACHE) && (CFG_INIT_RAM_END > (4 << 10))) +#error Only 4k of init-ram is supported - please adjust CFG_INIT_RAM_END! +#endif + #define function_prolog(func_name) .text; \ .align 2; \ .globl func_name; \ @@ -1306,39 +1310,6 @@ in32r: lwbrx r3,r0,r3 blr -/*------------------------------------------------------------------------------- */ -/* Function: ppcDcbf */ -/* Description: Data Cache block flush */ -/* Input: r3 = effective address */ -/* Output: none. */ -/*------------------------------------------------------------------------------- */ - .globl ppcDcbf -ppcDcbf: - dcbf r0,r3 - blr - -/*------------------------------------------------------------------------------- */ -/* Function: ppcDcbi */ -/* Description: Data Cache block Invalidate */ -/* Input: r3 = effective address */ -/* Output: none. */ -/*------------------------------------------------------------------------------- */ - .globl ppcDcbi -ppcDcbi: - dcbi r0,r3 - blr - -/*------------------------------------------------------------------------------- */ -/* Function: ppcSync */ -/* Description: Processor Synchronize */ -/* Input: none. */ -/* Output: none. */ -/*------------------------------------------------------------------------------- */ - .globl ppcSync -ppcSync: - sync - blr - /* * void relocate_code (addr_sp, gd, addr_moni) * |