diff options
Diffstat (limited to 'cpu')
-rw-r--r-- | cpu/mpc5xxx/cpu.c | 2 | ||||
-rw-r--r-- | cpu/mpc83xx/cpu.c | 2 | ||||
-rw-r--r-- | cpu/mpc83xx/spd_sdram.c | 4 | ||||
-rw-r--r-- | cpu/ppc4xx/sdram.c | 214 |
4 files changed, 111 insertions, 111 deletions
diff --git a/cpu/mpc5xxx/cpu.c b/cpu/mpc5xxx/cpu.c index 5ad4baa94eb..6b6f8282cf3 100644 --- a/cpu/mpc5xxx/cpu.c +++ b/cpu/mpc5xxx/cpu.c @@ -58,7 +58,7 @@ int checkcpu (void) break; } - printf (" v%d.%d, Core v%d.%d", SVR_MJREV (svr), SVR_MNREV (svr), + printf (" v%d.%d, Core v%d.%d", SVR_MJREV (svr), SVR_MNREV (svr), PVR_MAJ(pvr), PVR_MIN(pvr)); #endif printf (" at %s MHz\n", strmhz (buf, clock)); diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index 7ca1cebc049..20bba6c66b6 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -260,7 +260,7 @@ int dma_xfer(void *dest, u32 count, void *src) dmamr0 = (DMA_CHANNEL_TRANSFER_MODE_DIRECT | DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B | DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN); - + dma->dmamr0 = swab32(dmamr0); __asm__ __volatile__ ("sync"); diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index b4012a8ddfc..48624feca61 100644 --- a/cpu/mpc83xx/spd_sdram.c +++ b/cpu/mpc83xx/spd_sdram.c @@ -1,7 +1,7 @@ /* * (C) Copyright 2006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * + * * Copyright 2004 Freescale Semiconductor. * (C) Copyright 2003 Motorola Inc. * Xianghua Xiao (X.Xiao@motorola.com) @@ -426,7 +426,7 @@ static __inline__ unsigned long get_tbms (void) /* * Initialize all of memory for ECC, then enable errors. */ -//#define CONFIG_DDR_ECC_INIT_VIA_DMA +/* #define CONFIG_DDR_ECC_INIT_VIA_DMA */ void ddr_enable_ecc(unsigned int dram_size) { uint *p; diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c index c5ab01738c5..e31d59d80ea 100644 --- a/cpu/ppc4xx/sdram.c +++ b/cpu/ppc4xx/sdram.c @@ -18,7 +18,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -38,17 +38,17 @@ #ifndef CFG_SDRAM_TABLE sdram_conf_t mb0cf[] = { - {(128 << 20), 13, 0x000A4001}, /* (0-128MB) Address Mode 3, 13x10(4) */ - {(64 << 20), 13, 0x00084001}, /* (0-64MB) Address Mode 3, 13x9(4) */ - {(32 << 20), 12, 0x00062001}, /* (0-32MB) Address Mode 2, 12x9(4) */ - {(16 << 20), 12, 0x00046001}, /* (0-16MB) Address Mode 4, 12x8(4) */ - {(4 << 20), 11, 0x00008001}, /* (0-4MB) Address Mode 5, 11x8(2) */ + {(128 << 20), 13, 0x000A4001}, /* (0-128MB) Address Mode 3, 13x10(4) */ + {(64 << 20), 13, 0x00084001}, /* (0-64MB) Address Mode 3, 13x9(4) */ + {(32 << 20), 12, 0x00062001}, /* (0-32MB) Address Mode 2, 12x9(4) */ + {(16 << 20), 12, 0x00046001}, /* (0-16MB) Address Mode 4, 12x8(4) */ + {(4 << 20), 11, 0x00008001}, /* (0-4MB) Address Mode 5, 11x8(2) */ }; #else sdram_conf_t mb0cf[] = CFG_SDRAM_TABLE; #endif -#define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0])) +#define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0])) #ifndef CONFIG_440 @@ -65,76 +65,76 @@ static ulong ns2clks(ulong ns) static ulong compute_sdtr1(ulong speed) { #ifdef CFG_SDRAM_CASL - ulong tmp; - ulong sdtr1 = 0; - - /* CASL */ - if (CFG_SDRAM_CASL < 2) - sdtr1 |= (1 << SDRAM0_TR_CASL); - else - if (CFG_SDRAM_CASL > 4) - sdtr1 |= (3 << SDRAM0_TR_CASL); - else - sdtr1 |= ((CFG_SDRAM_CASL-1) << SDRAM0_TR_CASL); - - /* PTA */ - tmp = ns2clks(CFG_SDRAM_PTA); - if ((tmp >= 2) && (tmp <= 4)) - sdtr1 |= ((tmp-1) << SDRAM0_TR_PTA); - else - sdtr1 |= ((4-1) << SDRAM0_TR_PTA); - - /* CTP */ - tmp = ns2clks(CFG_SDRAM_CTP); - if ((tmp >= 2) && (tmp <= 4)) - sdtr1 |= ((tmp-1) << SDRAM0_TR_CTP); - else - sdtr1 |= ((4-1) << SDRAM0_TR_CTP); - - /* LDF */ - tmp = ns2clks(CFG_SDRAM_LDF); - if ((tmp >= 2) && (tmp <= 4)) - sdtr1 |= ((tmp-1) << SDRAM0_TR_LDF); - else - sdtr1 |= ((2-1) << SDRAM0_TR_LDF); - - /* RFTA */ - tmp = ns2clks(CFG_SDRAM_RFTA); - if ((tmp >= 4) && (tmp <= 10)) - sdtr1 |= ((tmp-4) << SDRAM0_TR_RFTA); - else - sdtr1 |= ((10-4) << SDRAM0_TR_RFTA); - - /* RCD */ - tmp = ns2clks(CFG_SDRAM_RCD); - if ((tmp >= 2) && (tmp <= 4)) - sdtr1 |= ((tmp-1) << SDRAM0_TR_RCD); - else - sdtr1 |= ((4-1) << SDRAM0_TR_RCD); - - return sdtr1; + ulong tmp; + ulong sdtr1 = 0; + + /* CASL */ + if (CFG_SDRAM_CASL < 2) + sdtr1 |= (1 << SDRAM0_TR_CASL); + else + if (CFG_SDRAM_CASL > 4) + sdtr1 |= (3 << SDRAM0_TR_CASL); + else + sdtr1 |= ((CFG_SDRAM_CASL-1) << SDRAM0_TR_CASL); + + /* PTA */ + tmp = ns2clks(CFG_SDRAM_PTA); + if ((tmp >= 2) && (tmp <= 4)) + sdtr1 |= ((tmp-1) << SDRAM0_TR_PTA); + else + sdtr1 |= ((4-1) << SDRAM0_TR_PTA); + + /* CTP */ + tmp = ns2clks(CFG_SDRAM_CTP); + if ((tmp >= 2) && (tmp <= 4)) + sdtr1 |= ((tmp-1) << SDRAM0_TR_CTP); + else + sdtr1 |= ((4-1) << SDRAM0_TR_CTP); + + /* LDF */ + tmp = ns2clks(CFG_SDRAM_LDF); + if ((tmp >= 2) && (tmp <= 4)) + sdtr1 |= ((tmp-1) << SDRAM0_TR_LDF); + else + sdtr1 |= ((2-1) << SDRAM0_TR_LDF); + + /* RFTA */ + tmp = ns2clks(CFG_SDRAM_RFTA); + if ((tmp >= 4) && (tmp <= 10)) + sdtr1 |= ((tmp-4) << SDRAM0_TR_RFTA); + else + sdtr1 |= ((10-4) << SDRAM0_TR_RFTA); + + /* RCD */ + tmp = ns2clks(CFG_SDRAM_RCD); + if ((tmp >= 2) && (tmp <= 4)) + sdtr1 |= ((tmp-1) << SDRAM0_TR_RCD); + else + sdtr1 |= ((4-1) << SDRAM0_TR_RCD); + + return sdtr1; #else /* CFG_SDRAM_CASL */ - /* - * If no values are configured in the board config file - * use the default values, which seem to be ok for most - * boards. - * - * REMARK: - * For new board ports we strongly recommend to define the - * correct values for the used SDRAM chips in your board - * config file (see PPChameleonEVB.h) - */ - if (speed > 100000000) { - /* - * 133 MHz SDRAM - */ - return 0x01074015; - } else { - /* - * default: 100 MHz SDRAM - */ - return 0x0086400d; - } + /* + * If no values are configured in the board config file + * use the default values, which seem to be ok for most + * boards. + * + * REMARK: + * For new board ports we strongly recommend to define the + * correct values for the used SDRAM chips in your board + * config file (see PPChameleonEVB.h) + */ + if (speed > 100000000) { + /* + * 133 MHz SDRAM + */ + return 0x01074015; + } else { + /* + * default: 100 MHz SDRAM + */ + return 0x0086400d; + } #endif /* CFG_SDRAM_CASL */ } @@ -142,24 +142,24 @@ static ulong compute_sdtr1(ulong speed) static ulong compute_rtr(ulong speed, ulong rows, ulong refresh) { #ifdef CFG_SDRAM_CASL - ulong tmp; + ulong tmp; - tmp = ((refresh*1000*1000) / (1 << rows)) * (speed / 1000); - tmp /= 1000000; + tmp = ((refresh*1000*1000) / (1 << rows)) * (speed / 1000); + tmp /= 1000000; - return ((tmp & 0x00003FF8) << 16); + return ((tmp & 0x00003FF8) << 16); #else /* CFG_SDRAM_CASL */ - if (speed > 100000000) { - /* - * 133 MHz SDRAM - */ + if (speed > 100000000) { + /* + * 133 MHz SDRAM + */ return 0x07f00000; - } else { - /* - * default: 100 MHz SDRAM - */ + } else { + /* + * default: 100 MHz SDRAM + */ return 0x05f00000; - } + } #endif /* CFG_SDRAM_CASL */ } @@ -172,19 +172,19 @@ void sdram_init(void) ulong sdtr1; int i; - /* - * Determine SDRAM speed - */ - speed = get_bus_freq(0); /* parameter not used on ppc4xx */ + /* + * Determine SDRAM speed + */ + speed = get_bus_freq(0); /* parameter not used on ppc4xx */ - /* - * sdtr1 (register SDRAM0_TR) must take into account timings listed - * in SDRAM chip datasheet. rtr (register SDRAM0_RTR) must take into - * account actual SDRAM size. So we can set up sdtr1 according to what - * is specified in board configuration file while rtr dependds on SDRAM - * size we are assuming before detection. - */ - sdtr1 = compute_sdtr1(speed); + /* + * sdtr1 (register SDRAM0_TR) must take into account timings listed + * in SDRAM chip datasheet. rtr (register SDRAM0_RTR) must take into + * account actual SDRAM size. So we can set up sdtr1 according to what + * is specified in board configuration file while rtr dependds on SDRAM + * size we are assuming before detection. + */ + sdtr1 = compute_sdtr1(speed); for (i=0; i<N_MB0CF; i++) { /* @@ -343,8 +343,8 @@ static void ecc_init(ulong start, ulong size) * Autodetect onboard DDR SDRAM on 440 platforms * * NOTE: Some of the hardcoded values are hardware dependant, - * so this should be extended for other future boards - * using this routine! + * so this should be extended for other future boards + * using this routine! */ long int initdram(int board_type) { @@ -360,11 +360,11 @@ long int initdram(int board_type) /* * Setup some default */ - mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */ - mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ + mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */ + mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */ - mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ + mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ /* * Following for CAS Latency = 2.5 @ 133 MHz PLB @@ -379,7 +379,7 @@ long int initdram(int board_type) /* * Enable the controller, then wait for DCEN to complete */ - mtsdram(mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ + mtsdram(mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ udelay(10000); if (get_ram_size(0, mb0cf[i].size) == mb0cf[i].size) { |