diff options
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/mpc5xxx/fec.c | 2 | ||||
| -rw-r--r-- | cpu/ppc4xx/cpu_init.c | 14 | ||||
| -rw-r--r-- | cpu/ppc4xx/start.S | 6 |
3 files changed, 16 insertions, 6 deletions
diff --git a/cpu/mpc5xxx/fec.c b/cpu/mpc5xxx/fec.c index 19737ce868..37fe3e7153 100644 --- a/cpu/mpc5xxx/fec.c +++ b/cpu/mpc5xxx/fec.c @@ -882,7 +882,7 @@ int mpc5xxx_fec_initialize(bd_t * bis) defined(CONFIG_ICECUBE) || defined(CONFIG_INKA4X0) || \ defined(CONFIG_MCC200) || defined(CONFIG_O2DNT) || \ defined(CONFIG_PM520) || defined(CONFIG_TOP5200) || \ - defined(CONFIG_TQM5200) + defined(CONFIG_TQM5200) || defined(CONFIG_V38B) # ifndef CONFIG_FEC_10MBIT fec->xcv_type = MII100; # else diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index b27567fa4d..def46f15ca 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -226,13 +226,19 @@ cpu_init_f (void) /* * GPIO0 setup (select GPIO or alternate function) */ - out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */ +#if defined(CFG_GPIO0_OR) + out32(GPIO0_OR, CFG_GPIO0_OR); /* set initial state of output pins */ +#endif +#if defined(CFG_GPIO0_ODR) + out32(GPIO0_ODR, CFG_GPIO0_ODR); /* open-drain select */ +#endif + out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */ out32(GPIO0_OSRL, CFG_GPIO0_OSRL); - out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */ + out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */ out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L); - out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */ + out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */ out32(GPIO0_TSRL, CFG_GPIO0_TSRL); - out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */ + out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */ /* * Set EMAC noise filter bits diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 3f2931411f..3fe13daaf3 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -1697,7 +1697,8 @@ ppc405ep_init: mtdcr ebccfgd,r3 #endif - addi r3,0,CPC0_PCI_HOST_CFG_EN +#ifndef CFG_CPC0_PCI + li r3,CPC0_PCI_HOST_CFG_EN #ifdef CONFIG_BUBINGA /* !----------------------------------------------------------------------- @@ -1712,6 +1713,9 @@ ppc405ep_init: beq ..pci_cfg_set /* if not set, then bypass reg write*/ #endif ori r3,r3,CPC0_PCI_ARBIT_EN +#else /* CFG_CPC0_PCI */ + li r3,CFG_CPC0_PCI +#endif /* CFG_CPC0_PCI */ ..pci_cfg_set: mtdcr CPC0_PCI, r3 /* Enable internal arbiter*/ |