diff options
Diffstat (limited to 'cpu/mpc512x')
-rw-r--r-- | cpu/mpc512x/cpu.c | 11 | ||||
-rw-r--r-- | cpu/mpc512x/iopin.c | 25 | ||||
-rw-r--r-- | cpu/mpc512x/serial.c | 15 | ||||
-rw-r--r-- | cpu/mpc512x/start.S | 46 |
4 files changed, 80 insertions, 17 deletions
diff --git a/cpu/mpc512x/cpu.c b/cpu/mpc512x/cpu.c index b9069b065e7..afcf78f0d67 100644 --- a/cpu/mpc512x/cpu.c +++ b/cpu/mpc512x/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. + * Copyright (C) 2004-2006, 2009 Freescale Semiconductor, Inc. All right reserved. * (C) Copyright 2007 DENX Software Engineering * * See file CREDITS for list of people who contributed to this @@ -53,6 +53,9 @@ int checkcpu (void) case SPR_5121E: puts ("MPC5121e "); break; + case SPR_5125: + puts ("MPC5125 "); + break; default: printf ("Unknown part ID %08x ", spridr & 0xffff0000); } @@ -71,6 +74,8 @@ int checkcpu (void) return 0; } +#define RESET_MAGIC_WORD 0x52535445 + int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) @@ -87,11 +92,11 @@ do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) /* * Enable Reset Control Reg - "RSTE" is the magic word that let us go */ - immap->reset.rpr = 0x52535445; + immap->reset.rpr = RESET_MAGIC_WORD; /* Verify Reset Control Reg is enabled */ while (!((immap->reset.rcer) & RCER_CRE)) - ; + immap->reset.rpr = RESET_MAGIC_WORD; printf ("Resetting the board.\n"); udelay(200); diff --git a/cpu/mpc512x/iopin.c b/cpu/mpc512x/iopin.c index 78f4fa1e8cc..4067eb21416 100644 --- a/cpu/mpc512x/iopin.c +++ b/cpu/mpc512x/iopin.c @@ -24,26 +24,41 @@ #include <common.h> #include <linux/types.h> #include <mpc512x.h> +#include <asm/io.h> void iopin_initialize(iopin_t *ioregs_init, int len) { short i, j, p; - u_long *reg; immap_t *im = (immap_t *)CONFIG_SYS_IMMR; +#ifdef CONFIG_ADS5125 + u_char *reg; +#else + u_long *reg; +#endif - reg = (u_long *)&(im->io_ctrl.regs[0]); - + reg = &im->io_ctrl.regs[0]; if (sizeof(ioregs_init) == 0) return; for (i = 0; i < len; i++) { +#ifdef CONFIG_ADS5125 + for (p = 0, j = ioregs_init[i].p_offset; + p < ioregs_init[i].nr_pins; p++, j++) { + if (ioregs_init[i].bit_or) + setbits(8, &(reg[j]), ioregs_init[i].val); + else + out_8(®[j], ioregs_init[i].val); + } +#else for (p = 0, j = ioregs_init[i].p_offset / sizeof(u_long); p < ioregs_init[i].nr_pins; p++, j++) { if (ioregs_init[i].bit_or) - reg[j] |= ioregs_init[i].val; + setbits(be32, &(reg[j]), ioregs_init[i].val); else - reg[j] = ioregs_init[i].val; + out_be32(®[j], ioregs_init[i].val); } +#endif } + return; } diff --git a/cpu/mpc512x/serial.c b/cpu/mpc512x/serial.c index 7db87a80a1a..6c334fbe971 100644 --- a/cpu/mpc512x/serial.c +++ b/cpu/mpc512x/serial.c @@ -67,8 +67,10 @@ int serial_init(void) fifo_init (psc); +#ifndef ADS5125 /* set MR register to point to MR1 */ psc->command = PSC_SEL_MODE_REG_1; +#endif /* disable Tx/Rx */ psc->command = PSC_TX_DISABLE | PSC_RX_DISABLE; @@ -79,15 +81,22 @@ int serial_init(void) /* switch to UART mode */ psc->sicr = 0; - /* mode register points to mr1 */ /* configure parity, bit length and so on in mode register 1*/ +#ifdef CONFIG_ADS5125 + psc->mr1 = PSC_MODE_8_BITS | PSC_MODE_PARNONE; + psc->mr2 = PSC_MODE_1_STOPBIT; + + /* calculate divisor for setting PSC CTUR and CTLR registers */ + div = gd->ips_clk/(16 * gd->baudrate); +#else + /* mode register points to mr1 */ psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE; /* now, mode register points to mr2 */ psc->mode = PSC_MODE_1_STOPBIT; - - /* calculate dividor for setting PSC CTUR and CTLR registers */ + /* calculate divisor for setting PSC CTUR and CTLR registers */ baseclk = (gd->ips_clk + 8) / 16; div = (baseclk + (gd->baudrate / 2)) / gd->baudrate; +#endif psc->ctur = (div >> 8) & 0xff; /* set baudrate */ diff --git a/cpu/mpc512x/start.S b/cpu/mpc512x/start.S index 360682dafcf..3623ce57144 100644 --- a/cpu/mpc512x/start.S +++ b/cpu/mpc512x/start.S @@ -190,16 +190,35 @@ _end_of_vectors: boot_cold: /* Save msr contents */ mfmsr r5 + lis r4, CONFIG_DEFAULT_IMMR@h /* Set IMMR area to our preferred location */ - lis r4, CONFIG_DEFAULT_IMMR@h + mfspr r6, MBAR lis r3, CONFIG_SYS_IMMR@h ori r3, r3, CONFIG_SYS_IMMR@l + + /* see if it has already been set (RAMBOOT or BDI configured) */ + + cmpw r3, r6 + beq 1f stw r3, IMMRBAR(r4) - mtspr MBAR, r3 /* IMMRBAR is mirrored into the MBAR SPR (311) */ + /* IMMRBAR is mirrored into the MBAR SPR (311) */ + mtspr MBAR, r3 + +1: lwz r4, RCWHR(r3) + lis r5, NAND_BOOT + and. r4, r4, r5 + beq 3f + + /* in NAND boot reset the NFC Access Window */ + li r4, 0 + lis r4, START_REG(CFG_NAND_BASE) + stw r4, NFCBAR(r3) + lwz r4, NFCBAR(r3) + isync /* Initialise the machine */ - bl cpu_early_init +3: bl cpu_early_init /* * Set up Local Access Windows: @@ -207,15 +226,16 @@ boot_cold: * 1) Boot/CS0 (boot FLASH) * 2) On-chip SRAM (initial stack purposes) */ - + isync /* Boot CS/CS0 window range */ lis r3, CONFIG_SYS_IMMR@h ori r3, r3, CONFIG_SYS_IMMR@l - + #if(BOARD_TYPE==BOARD_TYPE_5125_MPU) + #else lis r4, START_REG(CONFIG_SYS_FLASH_BASE) ori r4, r4, STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE) stw r4, LPCS0AW(r3) - +#endif /* * The SRAM window has a fixed size (256K), so only the start address * is necessary @@ -235,13 +255,27 @@ boot_cold: * Set configuration of the Boot/CS0, the SRAM window does not have a * config register so no params can be set for it */ +#if(BOARD_TYPE==BOARD_TYPE_5125_MPU) +#else lis r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@h ori r3, r3, (CONFIG_SYS_IMMR + LPC_OFFSET)@l lis r4, CONFIG_SYS_CS0_CFG@h ori r4, r4, CONFIG_SYS_CS0_CFG@l stw r4, CS0_CONFIG(r3) +#endif +#ifdef CONFIG_ADS5125 /* CS2 FUNC MUX must be done before CS is enabled */ + lis r4, (CONFIG_SYS_IOCTRL_ADDR)@h + ori r4, r4, (CONFIG_SYS_IOCTRL_ADDR)@l + li r5, IOCTRL_MUX_CS2 + stb r5, IO_CTRL_LPC_AX03(r4) +/* change the pin muxing on PSC9 here in case it is being used as console*/ + li r5, IOCTRL_MUX_PSC9 + stb r5, IO_CTRL_I2C1_SCL(r4) + stb r5, IO_CTRL_I2C1_SDA(r4) + +#endif /* Master enable all CS's */ lis r4, CS_CTRL_ME@h ori r4, r4, CS_CTRL_ME@l |