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-rw-r--r--board/freescale/mpc8541cds/mpc8541cds.c14
-rw-r--r--board/freescale/mpc8548cds/mpc8548cds.c10
-rw-r--r--board/freescale/mpc8555cds/mpc8555cds.c14
-rw-r--r--board/freescale/mpc8560ads/mpc8560ads.c1
-rw-r--r--board/freescale/mpc8568mds/mpc8568mds.c10
-rw-r--r--board/freescale/mpc8569mds/Makefile55
-rw-r--r--board/freescale/mpc8569mds/bcsr.c49
-rw-r--r--board/freescale/mpc8569mds/bcsr.h82
-rw-r--r--board/freescale/mpc8569mds/config.mk30
-rw-r--r--board/freescale/mpc8569mds/ddr.c84
-rw-r--r--board/freescale/mpc8569mds/law.c59
-rw-r--r--board/freescale/mpc8569mds/mpc8569mds.c329
-rw-r--r--board/freescale/mpc8569mds/tlb.c103
-rw-r--r--board/freescale/mpc8569mds/u-boot.lds143
-rw-r--r--board/freescale/mpc8641hpcn/mpc8641hpcn.c9
-rw-r--r--board/inka4x0/Makefile4
-rw-r--r--board/inka4x0/inka4x0.c171
-rw-r--r--board/inka4x0/inkadiag.c514
-rw-r--r--board/sbc8548/sbc8548.c10
-rw-r--r--board/sbc8641d/sbc8641d.c9
20 files changed, 1607 insertions, 93 deletions
diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c
index e6025c8a567..c30d966b6e6 100644
--- a/board/freescale/mpc8541cds/mpc8541cds.c
+++ b/board/freescale/mpc8541cds/mpc8541cds.c
@@ -372,21 +372,21 @@ sdram_init(void)
cpu_board_rev = get_cpu_board_revision();
lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
- lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1617;
+ lsdmr_common |= LSDMR_BSMA1617;
} else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
- lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1516;
+ lsdmr_common |= LSDMR_BSMA1516;
} else {
/*
* Assume something unable to identify itself is
* really old, and likely has lines 16/17 mapped.
*/
- lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1617;
+ lsdmr_common |= LSDMR_BSMA1617;
}
/*
* Issue PRECHARGE ALL command.
*/
- lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_PCHALL;
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
@@ -396,7 +396,7 @@ sdram_init(void)
* Issue 8 AUTO REFRESH commands.
*/
for (idx = 0; idx < 8; idx++) {
- lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH;
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
@@ -406,7 +406,7 @@ sdram_init(void)
/*
* Issue 8 MODE-set command.
*/
- lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_MRW;
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
@@ -415,7 +415,7 @@ sdram_init(void)
/*
* Issue NORMAL OP command.
*/
- lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_NORMAL;
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c
index 70320ea1a74..efb2c5b8c2d 100644
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -185,12 +185,12 @@ sdram_init(void)
*/
cpu_board_rev = get_cpu_board_revision();
lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
- lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1516;
+ lsdmr_common |= LSDMR_BSMA1516;
/*
* Issue PRECHARGE ALL command.
*/
- lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_PCHALL;
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
@@ -200,7 +200,7 @@ sdram_init(void)
* Issue 8 AUTO REFRESH commands.
*/
for (idx = 0; idx < 8; idx++) {
- lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH;
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
@@ -210,7 +210,7 @@ sdram_init(void)
/*
* Issue 8 MODE-set command.
*/
- lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_MRW;
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
@@ -219,7 +219,7 @@ sdram_init(void)
/*
* Issue NORMAL OP command.
*/
- lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_NORMAL;
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c
index 53d5a936af3..ecddd0d9c43 100644
--- a/board/freescale/mpc8555cds/mpc8555cds.c
+++ b/board/freescale/mpc8555cds/mpc8555cds.c
@@ -371,21 +371,21 @@ sdram_init(void)
cpu_board_rev = get_cpu_board_revision();
lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
- lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1617;
+ lsdmr_common |= LSDMR_BSMA1617;
} else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
- lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1516;
+ lsdmr_common |= LSDMR_BSMA1516;
} else {
/*
* Assume something unable to identify itself is
* really old, and likely has lines 16/17 mapped.
*/
- lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1617;
+ lsdmr_common |= LSDMR_BSMA1617;
}
/*
* Issue PRECHARGE ALL command.
*/
- lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_PCHALL;
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
@@ -395,7 +395,7 @@ sdram_init(void)
* Issue 8 AUTO REFRESH commands.
*/
for (idx = 0; idx < 8; idx++) {
- lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH;
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
@@ -405,7 +405,7 @@ sdram_init(void)
/*
* Issue 8 MODE-set command.
*/
- lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_MRW;
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
@@ -414,7 +414,7 @@ sdram_init(void)
/*
* Issue NORMAL OP command.
*/
- lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_NORMAL;
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c
index ac7778e25c7..2bca0f28ebf 100644
--- a/board/freescale/mpc8560ads/mpc8560ads.c
+++ b/board/freescale/mpc8560ads/mpc8560ads.c
@@ -36,6 +36,7 @@
#include <miiphy.h>
#include <libfdt.h>
#include <fdt_support.h>
+#include <asm/fsl_lbc.h>
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size);
diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c
index 915fae7fa40..97f465122bb 100644
--- a/board/freescale/mpc8568mds/mpc8568mds.c
+++ b/board/freescale/mpc8568mds/mpc8568mds.c
@@ -243,12 +243,12 @@ sdram_init(void)
* MPC8568 uses "new" 15-16 style addressing.
*/
lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
- lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1516;
+ lsdmr_common |= LSDMR_BSMA1516;
/*
* Issue PRECHARGE ALL command.
*/
- lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_PCHALL;
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
@@ -258,7 +258,7 @@ sdram_init(void)
* Issue 8 AUTO REFRESH commands.
*/
for (idx = 0; idx < 8; idx++) {
- lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH;
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
@@ -268,7 +268,7 @@ sdram_init(void)
/*
* Issue 8 MODE-set command.
*/
- lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_MRW;
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
@@ -277,7 +277,7 @@ sdram_init(void)
/*
* Issue NORMAL OP command.
*/
- lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_NORMAL;
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
diff --git a/board/freescale/mpc8569mds/Makefile b/board/freescale/mpc8569mds/Makefile
new file mode 100644
index 00000000000..23805ea41a4
--- /dev/null
+++ b/board/freescale/mpc8569mds/Makefile
@@ -0,0 +1,55 @@
+#
+# Copyright 2004-2009 Freescale Semiconductor.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y += $(BOARD).o
+COBJS-y += bcsr.o
+COBJS-y += ddr.o
+COBJS-y += law.o
+COBJS-y += tlb.o
+
+SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS) $(SOBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/mpc8569mds/bcsr.c b/board/freescale/mpc8569mds/bcsr.c
new file mode 100644
index 00000000000..5adffc23e3f
--- /dev/null
+++ b/board/freescale/mpc8569mds/bcsr.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#include "bcsr.h"
+
+void enable_8569mds_flash_write()
+{
+ setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 11), BCSR17_FLASH_nWP);
+}
+
+void disable_8569mds_flash_write()
+{
+ clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP);
+}
+
+void enable_8569mds_qe_mdio()
+{
+ setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7),
+ BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN);
+ setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8),
+ BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN);
+}
+
+void disable_8569mds_brd_eeprom_write_protect()
+{
+ clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7), BCSR7_BRD_WRT_PROTECT);
+}
diff --git a/board/freescale/mpc8569mds/bcsr.h b/board/freescale/mpc8569mds/bcsr.h
new file mode 100644
index 00000000000..8efe9bd4bf0
--- /dev/null
+++ b/board/freescale/mpc8569mds/bcsr.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __BCSR_H_
+#define __BCSR_H_
+
+#include <common.h>
+
+/* BCSR Bit definitions*/
+/****************************************/
+/* BCSR defines */
+/****************************************/
+#define BCSR6_UPC1_EN 0x80
+#define BCSR6_UPC1_POS_EN 0x40
+#define BCSR6_UPC1_ADDR_EN 0x20
+#define BCSR6_UPC1_DEV2 0x10
+#define BCSR6_SD_ENABLE 0x04
+#define BCSR6_TDM2G_EN 0x02
+#define BCSR6_UCC7_RMII_EN 0x01
+
+#define BCSR7_UCC1_GETH_EN 0x80
+#define BCSR7_UCC1_RGMII_EN 0x40
+#define BCSR7_UCC1_RTBI_EN 0x20
+#define BCSR7_GETHRST_MRVL 0x04
+#define BCSR7_BRD_WRT_PROTECT 0x02
+
+#define BCSR8_UCC2_GETH_EN 0x80
+#define BCSR8_UCC2_RGMII_EN 0x40
+#define BCSR8_UCC2_RTBI_EN 0x20
+#define BCSR8_UEM_MARVEL_RESET 0x02
+
+#define BCSR9_UCC3_GETH_EN 0x80
+#define BCSR9_UCC3_RGMII_EN 0x40
+#define BCSR9_UCC3_RTBI_EN 0x20
+#define BCSR9_UCC3_RMII_EN 0x10
+#define BCSR9_UCC3_UEM_MICREL 0x01
+
+#define BCSR10_UCC4_GETH_EN 0x80
+#define BCSR10_UCC4_RGMII_EN 0x40
+#define BCSR10_UCC4_RTBI_EN 0x20
+
+#define BCSR11_LED0 0x40
+#define BCSR11_LED1 0x20
+#define BCSR11_LED2 0x10
+
+#define BCSR12_UCC6_RMII_EN 0x20
+#define BCSR12_UCC8_RMII_EN 0x20
+
+#define BCSR15_SMII6_DIS 0x08
+#define BCSR15_SMII8_DIS 0x04
+
+#define BCSR16_UPC1_DEV2 0x02
+
+#define BCSR17_FLASH_nWP 0x01
+
+/*BCSR Utils functions*/
+
+void enable_8569mds_flash_write(void);
+void disable_8569mds_flash_write(void);
+void enable_8569mds_qe_mdio(void);
+void disable_8569mds_brd_eeprom_write_protect(void);
+
+#endif /* __BCSR_H_ */
diff --git a/board/freescale/mpc8569mds/config.mk b/board/freescale/mpc8569mds/config.mk
new file mode 100644
index 00000000000..36b344e2526
--- /dev/null
+++ b/board/freescale/mpc8569mds/config.mk
@@ -0,0 +1,30 @@
+#
+# Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# mpc8569mds board
+#
+TEXT_BASE = 0xfff80000
+
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC8569=1
diff --git a/board/freescale/mpc8569mds/ddr.c b/board/freescale/mpc8569mds/ddr.c
new file mode 100644
index 00000000000..4b4533eb502
--- /dev/null
+++ b/board/freescale/mpc8569mds/ddr.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+static void
+get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+ i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t));
+}
+
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+ return get_ddr_freq(0);
+}
+
+void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd,
+ unsigned int ctrl_num)
+{
+ unsigned int i;
+ unsigned int i2c_address = 0;
+
+ for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+ if (ctrl_num == 0 && i == 0)
+ i2c_address = SPD_EEPROM_ADDRESS1;
+ if (ctrl_num == 0 && i == 1)
+ i2c_address = SPD_EEPROM_ADDRESS2;
+ get_spd(&(ctrl_dimms_spd[i]), i2c_address);
+ }
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ /*
+ * Factors to consider for clock adjust:
+ * - number of chips on bus
+ * - position of slot
+ * - DDR1 vs. DDR2?
+ * - ???
+ *
+ * This needs to be determined on a board-by-board basis.
+ * 0110 3/4 cycle late
+ * 0111 7/8 cycle late
+ */
+ popts->clk_adjust = 6;
+
+ /*
+ * Factors to consider for CPO:
+ * - frequency
+ * - ddr1 vs. ddr2
+ */
+ popts->cpo_override = 0xff;
+
+ /*
+ * Factors to consider for write data delay:
+ * - number of DIMMs
+ *
+ * 1 = 1/4 clock delay
+ * 2 = 1/2 clock delay
+ * 3 = 3/4 clock delay
+ * 4 = 1 clock delay
+ * 5 = 5/4 clock delay
+ * 6 = 3/2 clock delay
+ */
+ popts->write_data_delay = 2;
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+}
diff --git a/board/freescale/mpc8569mds/law.c b/board/freescale/mpc8569mds/law.c
new file mode 100644
index 00000000000..e7381aae650
--- /dev/null
+++ b/board/freescale/mpc8569mds/law.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+/*
+ * LAW(Local Access Window) configuration:
+ *
+ *0) 0x0000_0000 0x7fff_ffff DDR 2G
+ *1) 0xa000_0000 0xbfff_ffff PCIe MEM 512MB
+ *-) 0xe000_0000 0xe00f_ffff CCSR 1M
+ *2) 0xe280_0000 0xe2ff_ffff PCIe I/O 8M
+ *3) 0xc000_0000 0xdfff_ffff SRIO 512MB
+ *4.a) 0xf000_0000 0xf3ff_ffff SDRAM 64MB
+ *4.b) 0xf800_0000 0xf800_7fff BCSR 32KB
+ *4.c) 0xf800_8000 0xf800_ffff PIB (CS4) 32KB
+ *4.d) 0xf801_0000 0xf801_7fff PIB (CS5) 32KB
+ *4.e) 0xfe00_0000 0xffff_ffff Flash 32MB
+ *
+ *Notes:
+ * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
+ * If flash is 8M at default position (last 8M), no LAW needed.
+ *
+ */
+
+struct law_entry law_table[] = {
+#ifndef CONFIG_SPD_EEPROM
+ SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_1G, LAW_TRGT_IF_DDR),
+#endif
+ SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1),
+ SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
+ SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c
new file mode 100644
index 00000000000..53fef43f359
--- /dev/null
+++ b/board/freescale/mpc8569mds/mpc8569mds.c
@@ -0,0 +1,329 @@
+/*
+ * Copyright 2009 Freescale Semiconductor.
+ *
+ * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/immap_fsl_pci.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/io.h>
+#include <spd_sdram.h>
+#include <i2c.h>
+#include <ioports.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+#include "bcsr.h"
+
+phys_size_t fixed_sdram(void);
+
+const qe_iop_conf_t qe_iop_conf_tab[] = {
+ /* QE_MUX_MDC */
+ {2, 31, 1, 0, 1}, /* QE_MUX_MDC */
+
+ /* QE_MUX_MDIO */
+ {2, 30, 3, 0, 2}, /* QE_MUX_MDIO */
+
+ /* UCC_1_RGMII */
+ {2, 11, 2, 0, 1}, /* CLK12 */
+ {0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */
+ {0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */
+ {0, 2, 1, 0, 1}, /* ENET1_TXD2_SER1_TXD2 */
+ {0, 3, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
+ {0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */
+ {0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */
+ {0, 8, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
+ {0, 9, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
+ {0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
+ {0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */
+ {2, 8, 2, 0, 1}, /* ENET1_GRXCLK */
+ {2, 20, 1, 0, 2}, /* ENET1_GTXCLK */
+
+ /* UCC_2_RGMII */
+ {2, 16, 2, 0, 3}, /* CLK17 */
+ {0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */
+ {0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */
+ {0, 16, 1, 0, 1}, /* ENET2_TXD2_SER2_TXD2 */
+ {0, 17, 1, 0, 1}, /* ENET2_TXD3_SER2_TXD3 */
+ {0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */
+ {0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */
+ {0, 22, 2, 0, 1}, /* ENET2_RXD2_SER2_RXD2 */
+ {0, 23, 2, 0, 1}, /* ENET2_RXD3_SER2_RXD3 */
+ {0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */
+ {0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */
+ {2, 3, 2, 0, 1}, /* ENET2_GRXCLK */
+ {2, 2, 1, 0, 2}, /* ENET2_GTXCLK */
+
+ {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
+};
+
+void local_bus_init(void);
+
+int board_early_init_f (void)
+{
+ /*
+ * Initialize local bus.
+ */
+ local_bus_init ();
+
+ enable_8569mds_flash_write();
+
+#ifdef CONFIG_QE
+ enable_8569mds_qe_mdio();
+#endif
+
+#if CONFIG_SYS_I2C2_OFFSET
+ /* Enable I2C2 signals instead of SD signals */
+ volatile struct ccsr_gur *gur;
+ gur = (struct ccsr_gur *)(CONFIG_SYS_IMMR + 0xe0000);
+ gur->plppar1 &= ~PLPPAR1_I2C_BIT_MASK;
+ gur->plppar1 |= PLPPAR1_I2C2_VAL;
+ gur->plpdir1 &= ~PLPDIR1_I2C_BIT_MASK;
+ gur->plpdir1 |= PLPDIR1_I2C2_VAL;
+
+ disable_8569mds_brd_eeprom_write_protect();
+#endif
+
+ return 0;
+}
+
+int checkboard (void)
+{
+ printf ("Board: 8569 MDS\n");
+
+ return 0;
+}
+
+phys_size_t
+initdram(int board_type)
+{
+ long dram_size = 0;
+
+ puts("Initializing\n");
+
+#if defined(CONFIG_DDR_DLL)
+ /*
+ * Work around to stabilize DDR DLL MSYNC_IN.
+ * Errata DDR9 seems to have been fixed.
+ * This is now the workaround for Errata DDR11:
+ * Override DLL = 1, Course Adj = 1, Tap Select = 0
+ */
+ volatile ccsr_gur_t *gur =
+ (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+ out_be32(&gur->ddrdllcr, 0x81000000);
+ udelay(200);
+#endif
+
+#ifdef CONFIG_SPD_EEPROM
+ dram_size = fsl_ddr_sdram();
+#else
+ dram_size = fixed_sdram();
+#endif
+
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+
+ puts(" DDR: ");
+ return dram_size;
+}
+
+#if !defined(CONFIG_SPD_EEPROM)
+phys_size_t fixed_sdram(void)
+{
+ volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+ uint d_init;
+
+ out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
+ out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
+ out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+ out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+ out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+ out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+ out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
+ out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
+ out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_SDRAM_MODE);
+ out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_SDRAM_MODE_2);
+ out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_SDRAM_INTERVAL);
+ out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
+ out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
+ out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
+ out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
+ out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL);
+ out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL);
+ out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
+#if defined (CONFIG_DDR_ECC)
+ out_be32(&ddr->err_int_en, CONFIG_SYS_DDR_ERR_INT_EN);
+ out_be32(&ddr->err_disable, CONFIG_SYS_DDR_ERR_DIS);
+ out_be32(&ddr->err_sbe, CONFIG_SYS_DDR_SBE);
+#endif
+ udelay(500);
+
+ out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
+#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+ d_init = 1;
+ debug("DDR - 1st controller: memory initializing\n");
+ /*
+ * Poll until memory is initialized.
+ * 512 Meg at 400 might hit this 200 times or so.
+ */
+ while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
+ udelay(1000);
+ }
+ debug("DDR: memory initialized\n\n");
+ udelay(500);
+#endif
+ return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+}
+#endif
+
+/*
+ * Initialize Local Bus
+ */
+void
+local_bus_init(void)
+{
+ volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+
+ uint clkdiv;
+ uint lbc_hz;
+ sys_info_t sysinfo;
+
+ get_sys_info(&sysinfo);
+ clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
+ lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
+
+ out_be32(&gur->lbiuiplldcr1, 0x00078080);
+ if (clkdiv == 16)
+ out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
+ else if (clkdiv == 8)
+ out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
+ else if (clkdiv == 4)
+ out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
+
+ out_be32(&lbc->lcrr, (u32)in_be32(&lbc->lcrr)| 0x00030000);
+}
+
+#ifdef CONFIG_PCIE1
+static struct pci_controller pcie1_hose;
+#endif /* CONFIG_PCIE1 */
+
+extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
+extern void fsl_pci_init(struct pci_controller *hose);
+
+int first_free_busno = 0;
+
+#ifdef CONFIG_PCI
+void
+pci_init_board(void)
+{
+ volatile ccsr_gur_t *gur;
+ uint io_sel;
+ uint host_agent;
+
+ gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+ host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
+
+#ifdef CONFIG_PCIE1
+{
+ volatile ccsr_fsl_pci_t *pci;
+ struct pci_controller *hose;
+ int pcie_ep;
+ struct pci_region *r;
+ int pcie_configured;
+
+ pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
+ hose = &pcie1_hose;
+ pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
+ r = hose->regions;
+ pcie_configured = io_sel >= 1;
+
+ if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
+ printf ("\n PCIE connected to slot as %s (base address %x)",
+ pcie_ep ? "End Point" : "Root Complex",
+ (uint)pci);
+
+ if (pci->pme_msg_det) {
+ pci->pme_msg_det = 0xffffffff;
+ debug (" with errors. Clearing. Now 0x%08x",
+ pci->pme_msg_det);
+ }
+ printf ("\n");
+
+ /* inbound */
+ r += fsl_pci_setup_inbound_windows(r);
+
+ /* outbound memory */
+ pci_set_region(r++,
+ CONFIG_SYS_PCIE1_MEM_BUS,
+ CONFIG_SYS_PCIE1_MEM_PHYS,
+ CONFIG_SYS_PCIE1_MEM_SIZE,
+ PCI_REGION_MEM);
+
+ /* outbound io */
+ pci_set_region(r++,
+ CONFIG_SYS_PCIE1_IO_BUS,
+ CONFIG_SYS_PCIE1_IO_PHYS,
+ CONFIG_SYS_PCIE1_IO_SIZE,
+ PCI_REGION_IO);
+
+ hose->region_count = r - hose->regions;
+
+ hose->first_busno=first_free_busno;
+ pci_setup_indirect(hose, (int) &pci->cfg_addr,
+ (int) &pci->cfg_data);
+
+ fsl_pci_init(hose);
+ printf ("PCIE on bus %02x - %02x\n",
+ hose->first_busno,hose->last_busno);
+
+ first_free_busno=hose->last_busno+1;
+
+ } else {
+ printf (" PCIE: disabled\n");
+ }
+}
+#else
+ gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
+#endif
+}
+#endif /* CONFIG_PCI */
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
+ struct pci_controller *hose);
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ ft_cpu_setup(blob, bd);
+
+#ifdef CONFIG_PCIE1
+ ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
+#endif
+}
+#endif
diff --git a/board/freescale/mpc8569mds/tlb.c b/board/freescale/mpc8569mds/tlb.c
new file mode 100644
index 00000000000..d3b251e7977
--- /dev/null
+++ b/board/freescale/mpc8569mds/tlb.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 Initializations */
+ /*
+ * TLBe 0: 16M Non-cacheable, guarded
+ * 0xff000000 16M FLASH (upper half)
+ * Out of reset this entry is only 4K.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000,
+ CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_16M, 1),
+
+ /*
+ * TLBe 1: 16M Non-cacheable, guarded
+ * 0xfe000000 16M FLASH (lower half)
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_16M, 1),
+
+ /*
+ * TLBe 2: 256M Non-cacheable, guarded
+ * 0xa00000000 256M PCIe MEM (lower half)
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+ /*
+ * TLBe 3: 256M Non-cacheable, guarded
+ * 0xb00000000 256M PCIe MEM (higher half)
+ */
+ SET_TLB_ENTRY(1, (CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000),
+ (CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000),
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_256M, 1),
+
+ /*
+ * TLBe 4: 64M Non-cacheable, guarded
+ * 0xe000_0000 1M CCSRBAR
+ * 0xe280_0000 8M PCIe IO
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_64M, 1),
+
+ /*
+ * TLBe 5: 256K Non-cacheable, guarded
+ * 0xf8000000 32K BCSR
+ * 0xf8008000 32K PIB (CS4)
+ * 0xf8010000 32K PIB (CS5)
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256K, 1),
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/mpc8569mds/u-boot.lds b/board/freescale/mpc8569mds/u-boot.lds
new file mode 100644
index 00000000000..0b2ea7549f2
--- /dev/null
+++ b/board/freescale/mpc8569mds/u-boot.lds
@@ -0,0 +1,143 @@
+/*
+ * Copyright 2004-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+ __DYNAMIC = 0; */
+PHDRS
+{
+ text PT_LOAD;
+ bss PT_LOAD;
+}
+
+SECTIONS
+{
+ /* Read-only sections, merged into text segment: */
+ . = + SIZEOF_HEADERS;
+ .interp : { *(.interp) }
+ .hash : { *(.hash) }
+ .dynsym : { *(.dynsym) }
+ .dynstr : { *(.dynstr) }
+ .rel.text : { *(.rel.text) }
+ .rela.text : { *(.rela.text) }
+ .rel.data : { *(.rel.data) }
+ .rela.data : { *(.rela.data) }
+ .rel.rodata : { *(.rel.rodata) }
+ .rela.rodata : { *(.rela.rodata) }
+ .rel.got : { *(.rel.got) }
+ .rela.got : { *(.rela.got) }
+ .rel.ctors : { *(.rel.ctors) }
+ .rela.ctors : { *(.rela.ctors) }
+ .rel.dtors : { *(.rel.dtors) }
+ .rela.dtors : { *(.rela.dtors) }
+ .rel.bss : { *(.rel.bss) }
+ .rela.bss : { *(.rela.bss) }
+ .rel.plt : { *(.rel.plt) }
+ .rela.plt : { *(.rela.plt) }
+ .init : { *(.init) }
+ .plt : { *(.plt) }
+ .text :
+ {
+ *(.text)
+ *(.fixup)
+ *(.got1)
+ } :text
+ _etext = .;
+ PROVIDE (etext = .);
+ .rodata :
+ {
+ *(.eh_frame)
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ } :text
+ .fini : { *(.fini) } =0
+ .ctors : { *(.ctors) }
+ .dtors : { *(.dtors) }
+
+ /* Read-write section, merged into data segment: */
+ . = (. + 0x00FF) & 0xFFFFFF00;
+ _erotext = .;
+ PROVIDE (erotext = .);
+ .reloc :
+ {
+ *(.got)
+ _GOT2_TABLE_ = .;
+ *(.got2)
+ _FIXUP_TABLE_ = .;
+ *(.fixup)
+ }
+ __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+ __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+ .data :
+ {
+ *(.data)
+ *(.data1)
+ *(.sdata)
+ *(.sdata2)
+ *(.dynamic)
+ CONSTRUCTORS
+ }
+ _edata = .;
+ PROVIDE (edata = .);
+
+ . = .;
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
+ . = ALIGN(256);
+ __init_begin = .;
+ .text.init : { *(.text.init) }
+ .data.init : { *(.data.init) }
+ . = ALIGN(256);
+ __init_end = .;
+
+ .bootpg ADDR(.text) + 0x7f000 :
+ {
+ cpu/mpc85xx/start.o (.bootpg)
+ } :text = 0xffff
+
+ .resetvec ADDR(.text) + 0x7fffc :
+ {
+ *(.resetvec)
+ } :text = 0xffff
+
+ . = ADDR(.text) + 0x80000;
+
+ __bss_start = .;
+ .bss (NOLOAD) :
+ {
+ *(.sbss) *(.scommon)
+ *(.dynbss)
+ *(.bss)
+ *(COMMON)
+ } :bss
+
+ . = ALIGN(4);
+ _end = . ;
+ PROVIDE (end = .);
+}
diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
index c94fc3f1d9c..ef0095ab75f 100644
--- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -374,3 +374,12 @@ void board_reset(void)
while (1)
;
}
+
+#ifdef CONFIG_MP
+extern void cpu_mp_lmb_reserve(struct lmb *lmb);
+
+void board_lmb_reserve(struct lmb *lmb)
+{
+ cpu_mp_lmb_reserve(lmb);
+}
+#endif
diff --git a/board/inka4x0/Makefile b/board/inka4x0/Makefile
index 442e2d0df25..82aa9500172 100644
--- a/board/inka4x0/Makefile
+++ b/board/inka4x0/Makefile
@@ -1,5 +1,5 @@
#
-# (C) Copyright 2003-2006
+# (C) Copyright 2003-2009
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
-COBJS := $(BOARD).o
+COBJS := $(BOARD).o inkadiag.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
diff --git a/board/inka4x0/inka4x0.c b/board/inka4x0/inka4x0.c
index 507196bb2f8..7428b9264a8 100644
--- a/board/inka4x0/inka4x0.c
+++ b/board/inka4x0/inka4x0.c
@@ -1,6 +1,9 @@
/*
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * (C) Copyright 2008-2009
+ * Andreas Pfefferle, DENX Software Engineering, ap@denx.de.
+ *
+ * (C) Copyright 2009
+ * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
*
* (C) Copyright 2004
* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
@@ -8,6 +11,9 @@
* (C) Copyright 2004
* Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -27,6 +33,7 @@
* MA 02111-1307 USA
*/
+#include <asm/io.h>
#include <common.h>
#include <mpc5xxx.h>
#include <pci.h>
@@ -48,41 +55,35 @@
#ifndef CONFIG_SYS_RAMBOOT
static void sdram_start (int hi_addr)
{
+ volatile struct mpc5xxx_sdram *sdram =
+ (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
long hi_addr_bit = hi_addr ? 0x01000000 : 0;
/* unlock mode register */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
- __asm__ volatile ("sync");
+ out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000000 | hi_addr_bit);
/* precharge all banks */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
- __asm__ volatile ("sync");
+ out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);
#if SDRAM_DDR
/* set mode register: extended mode */
- *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
- __asm__ volatile ("sync");
+ out_be32(&sdram->mode, SDRAM_EMODE);
/* set mode register: reset DLL */
- *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
- __asm__ volatile ("sync");
+ out_be32(&sdram->mode, SDRAM_MODE | 0x04000000);
#endif
/* precharge all banks */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
- __asm__ volatile ("sync");
+ out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000002 | hi_addr_bit);
/* auto refresh */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
- __asm__ volatile ("sync");
+ out_be32(&sdram->ctrl, SDRAM_CONTROL | 0x80000004 | hi_addr_bit);
/* set mode register */
- *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
- __asm__ volatile ("sync");
+ out_be32(&sdram->mode, SDRAM_MODE);
/* normal operation */
- *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
- __asm__ volatile ("sync");
+ out_be32(&sdram->ctrl, SDRAM_CONTROL | hi_addr_bit);
}
#endif
@@ -94,24 +95,27 @@ static void sdram_start (int hi_addr)
phys_size_t initdram (int board_type)
{
+ volatile struct mpc5xxx_mmap_ctl *mm =
+ (struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
+ volatile struct mpc5xxx_cdm *cdm =
+ (struct mpc5xxx_cdm *) MPC5XXX_CDM;
+ volatile struct mpc5xxx_sdram *sdram =
+ (struct mpc5xxx_sdram *) MPC5XXX_SDRAM;
ulong dramsize = 0;
#ifndef CONFIG_SYS_RAMBOOT
long test1, test2;
/* setup SDRAM chip selects */
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c; /* 512MB at 0x0 */
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000; /* disabled */
- __asm__ volatile ("sync");
+ out_be32(&mm->sdram0, 0x0000001c); /* 512MB at 0x0 */
+ out_be32(&mm->sdram1, 0x40000000); /* disabled */
/* setup config registers */
- *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
- *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
- __asm__ volatile ("sync");
+ out_be32(&sdram->config1, SDRAM_CONFIG1);
+ out_be32(&sdram->config2, SDRAM_CONFIG2);
#if SDRAM_DDR
/* set tap delay */
- *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
- __asm__ volatile ("sync");
+ out_be32(&cdm->porcfg, SDRAM_TAPDELAY);
#endif
/* find RAM size using SDRAM CS0 only */
@@ -133,17 +137,17 @@ phys_size_t initdram (int board_type)
/* set SDRAM CS0 size according to the amount of RAM found */
if (dramsize > 0) {
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
- __builtin_ffs(dramsize >> 20) - 1;
+ out_be32(&mm->sdram0, 0x13 +
+ __builtin_ffs(dramsize >> 20) - 1);
} else {
- *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
+ out_be32(&mm->sdram0, 0); /* disabled */
}
- *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
+ out_be32(&mm->sdram1, dramsize); /* disabled */
#else /* CONFIG_SYS_RAMBOOT */
/* retrieve size of memory connected to SDRAM CS0 */
- dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
+ dramsize = in_be32(&mm->sdram0) & 0xFF;
if (dramsize >= 0x13) {
dramsize = (1 << (dramsize - 0x13)) << 20;
} else {
@@ -162,17 +166,34 @@ int checkboard (void)
void flash_preinit(void)
{
+ volatile struct mpc5xxx_lpb *lpb = (struct mpc5xxx_lpb *)MPC5XXX_LPB;
+
/*
* Now, when we are in RAM, enable flash write
* access for detection process.
- * Note that CS_BOOT cannot be cleared when
+ * Note that CS_BOOT (CS0) cannot be cleared when
* executing in flash.
*/
- *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
+ clrbits_be32(&lpb->cs0_cfg, 0x1); /* clear RO */
+}
+
+int misc_init_r (void) {
+ extern int inkadiag_init_r (void);
+
+ /*
+ * The command table used for the subcommands of inkadiag
+ * needs to be relocated manually.
+ */
+ return inkadiag_init_r();
}
int misc_init_f (void)
{
+ volatile struct mpc5xxx_gpio *gpio =
+ (struct mpc5xxx_gpio *) MPC5XXX_GPIO;
+ volatile struct mpc5xxx_wu_gpio *wu_gpio =
+ (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
+ volatile struct mpc5xxx_gpt *gpt;
char tmp[10];
int i, br;
@@ -186,40 +207,60 @@ int misc_init_f (void)
/* Initialize GPIO output pins.
*/
/* Configure GPT as GPIO output (and set them as they control low-active LEDs */
- *(vu_long *)MPC5XXX_GPT0_ENABLE =
- *(vu_long *)MPC5XXX_GPT1_ENABLE =
- *(vu_long *)MPC5XXX_GPT2_ENABLE =
- *(vu_long *)MPC5XXX_GPT3_ENABLE =
- *(vu_long *)MPC5XXX_GPT4_ENABLE =
- *(vu_long *)MPC5XXX_GPT5_ENABLE = 0x34;
+ for (i = 0; i <= 5; i++) {
+ gpt = (struct mpc5xxx_gpt *)(MPC5XXX_GPT + (i * 0x10));
+ out_be32(&gpt->emsr, 0x34);
+ }
/* Configure GPT7 as PWM timer, 1kHz, no ints. */
- *(vu_long *)MPC5XXX_GPT7_ENABLE = 0;/* Disable */
- *(vu_long *)MPC5XXX_GPT7_COUNTER = 0x020000fe;
- *(vu_long *)MPC5XXX_GPT7_PWMCFG = (br << 16);
- *(vu_long *)MPC5XXX_GPT7_ENABLE = 0x3;/* Enable PWM mode and start */
+ gpt = (struct mpc5xxx_gpt *)(MPC5XXX_GPT + (7 * 0x10));
+ out_be32(&gpt->emsr, 0); /* Disable */
+ out_be32(&gpt->cir, 0x020000fe);
+ out_be32(&gpt->pwmcr, (br << 16));
+ out_be32(&gpt->emsr, 0x3); /* Enable PWM mode and start */
/* Configure PSC3_6,7 as GPIO output */
- *(vu_long *)MPC5XXX_GPIO_ENABLE |= 0x00003000;
- *(vu_long *)MPC5XXX_GPIO_DIR |= 0x00003000;
-
- /* Configure PSC3_8 as GPIO output, no interrupt */
- *(vu_long *)MPC5XXX_GPIO_SI_ENABLE |= 0x04000000;
- *(vu_long *)MPC5XXX_GPIO_SI_DIR |= 0x04000000;
- *(vu_long *)MPC5XXX_GPIO_SI_IEN &= ~0x04000000;
+ setbits_be32(&gpio->simple_gpioe, MPC5XXX_GPIO_SIMPLE_PSC3_6 |
+ MPC5XXX_GPIO_SIMPLE_PSC3_7);
+ setbits_be32(&gpio->simple_ddr, MPC5XXX_GPIO_SIMPLE_PSC3_6 |
+ MPC5XXX_GPIO_SIMPLE_PSC3_7);
/* Configure PSC3_9 and GPIO_WKUP6,7 as GPIO output */
- *(vu_long *)MPC5XXX_WU_GPIO_ENABLE |= 0xc4000000;
- *(vu_long *)MPC5XXX_WU_GPIO_DIR |= 0xc4000000;
+ setbits_8(&wu_gpio->enable, MPC5XXX_GPIO_WKUP_6 |
+ MPC5XXX_GPIO_WKUP_7 |
+ MPC5XXX_GPIO_WKUP_PSC3_9);
+ setbits_8(&wu_gpio->ddr, MPC5XXX_GPIO_WKUP_6 |
+ MPC5XXX_GPIO_WKUP_7 |
+ MPC5XXX_GPIO_WKUP_PSC3_9);
/* Set LR mirror bit because it is low-active */
- *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_WKUP_7;
+ setbits_8(&wu_gpio->dvo, MPC5XXX_GPIO_WKUP_7);
+
+ /* Reset Coral-P graphics controller */
+ setbits_8(&wu_gpio->dvo, MPC5XXX_GPIO_WKUP_PSC3_9);
+
+ /* Enable display backlight */
+ clrbits_8(&gpio->sint_inten, MPC5XXX_GPIO_SINT_PSC3_8);
+ setbits_8(&gpio->sint_gpioe, MPC5XXX_GPIO_SINT_PSC3_8);
+ setbits_8(&gpio->sint_ddr, MPC5XXX_GPIO_SINT_PSC3_8);
+ setbits_8(&gpio->sint_dvo, MPC5XXX_GPIO_SINT_PSC3_8);
+
/*
- * Reset Coral-P graphics controller
+ * Configure three wire serial interface to RTC (PSC1_4,
+ * PSC2_4, PSC3_4, PSC3_5)
*/
- *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC3_9;
- *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC3_9;
- *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC3_9;
+ setbits_8(&wu_gpio->enable, MPC5XXX_GPIO_WKUP_PSC1_4 |
+ MPC5XXX_GPIO_WKUP_PSC2_4);
+ setbits_8(&wu_gpio->ddr, MPC5XXX_GPIO_WKUP_PSC1_4 |
+ MPC5XXX_GPIO_WKUP_PSC2_4);
+ clrbits_8(&wu_gpio->dvo, MPC5XXX_GPIO_WKUP_PSC1_4);
+ clrbits_8(&gpio->sint_inten, MPC5XXX_GPIO_SINT_PSC3_4 |
+ MPC5XXX_GPIO_SINT_PSC3_5);
+ setbits_8(&gpio->sint_gpioe, MPC5XXX_GPIO_SINT_PSC3_4 |
+ MPC5XXX_GPIO_SINT_PSC3_5);
+ setbits_8(&gpio->sint_ddr, MPC5XXX_GPIO_SINT_PSC3_5);
+ clrbits_8(&gpio->sint_dvo, MPC5XXX_GPIO_SINT_PSC3_5);
+
return 0;
}
@@ -238,25 +279,31 @@ void pci_init_board(void)
void init_ide_reset (void)
{
+ volatile struct mpc5xxx_wu_gpio *wu_gpio =
+ (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
+
debug ("init_ide_reset\n");
/* Configure PSC1_4 as GPIO output for ATA reset */
- *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
- *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
+ setbits_8(&wu_gpio->enable, MPC5XXX_GPIO_WKUP_PSC1_4);
+ setbits_8(&wu_gpio->ddr, MPC5XXX_GPIO_WKUP_PSC1_4);
/* Deassert reset */
- *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
+ setbits_8(&wu_gpio->dvo, MPC5XXX_GPIO_WKUP_PSC1_4);
}
void ide_set_reset (int idereset)
{
+ volatile struct mpc5xxx_wu_gpio *wu_gpio =
+ (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
+
debug ("ide_reset(%d)\n", idereset);
if (idereset) {
- *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
+ clrbits_8(&wu_gpio->dvo, MPC5XXX_GPIO_WKUP_PSC1_4);
/* Make a delay. MPC5200 spec says 25 usec min */
udelay(500000);
} else {
- *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
+ setbits_8(&wu_gpio->dvo, MPC5XXX_GPIO_WKUP_PSC1_4);
}
}
#endif
diff --git a/board/inka4x0/inkadiag.c b/board/inka4x0/inkadiag.c
new file mode 100644
index 00000000000..06c980713bd
--- /dev/null
+++ b/board/inka4x0/inkadiag.c
@@ -0,0 +1,514 @@
+/*
+ * (C) Copyright 2008, 2009 Andreas Pfefferle,
+ * DENX Software Engineering, ap@denx.de.
+ * (C) Copyright 2009 Detlev Zundel,
+ * DENX Software Engineering, dzu@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/io.h>
+#include <common.h>
+#include <config.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+
+#include <command.h>
+
+/* This is needed for the includes in ns16550.h */
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#include <ns16550.h>
+
+#define GPIO_BASE ((u_char *)CONFIG_SYS_CS3_START)
+
+#define DIGIN_TOUCHSCR_MASK 0x00003000 /* Inputs 12-13 */
+#define DIGIN_KEYB_MASK 0x00010000 /* Input 16 */
+
+#define DIGIN_DRAWER_SW1 0x00400000 /* Input 22 */
+#define DIGIN_DRAWER_SW2 0x00800000 /* Input 23 */
+
+#define DIGIO_LED0 0x00000001 /* Output 0 */
+#define DIGIO_LED1 0x00000002 /* Output 1 */
+#define DIGIO_LED2 0x00000004 /* Output 2 */
+#define DIGIO_LED3 0x00000008 /* Output 3 */
+#define DIGIO_LED4 0x00000010 /* Output 4 */
+#define DIGIO_LED5 0x00000020 /* Output 5 */
+
+#define DIGIO_DRAWER1 0x00000100 /* Output 8 */
+#define DIGIO_DRAWER2 0x00000200 /* Output 9 */
+
+#define SERIAL_PORT_BASE ((u_char *)CONFIG_SYS_CS2_START)
+
+#define PSC_OP1_RTS 0x01
+#define PSC_OP0_RTS 0x01
+
+/*
+ * Table with supported baudrates (defined in inka4x0.h)
+ */
+static const unsigned long baudrate_table[] = CONFIG_SYS_BAUDRATE_TABLE;
+#define N_BAUDRATES (sizeof(baudrate_table) / sizeof(baudrate_table[0]))
+
+static unsigned int inka_digin_get_input(void)
+{
+ return in_8(GPIO_BASE + 0) << 0 | in_8(GPIO_BASE + 1) << 8 |
+ in_8(GPIO_BASE + 2) << 16 | in_8(GPIO_BASE + 3) << 24;
+}
+
+#define LED_HIGH(NUM) \
+ do { \
+ setbits_be32((unsigned *)MPC5XXX_GPT##NUM##_ENABLE, 0x10); \
+ } while (0)
+
+#define LED_LOW(NUM) \
+ do { \
+ clrbits_be32((unsigned *)MPC5XXX_GPT##NUM##_ENABLE, 0x10); \
+ } while (0)
+
+#define CHECK_LED(NUM) \
+ do { \
+ if (state & (1 << NUM)) { \
+ LED_HIGH(NUM); \
+ } else { \
+ LED_LOW(NUM); \
+ } \
+ } while (0)
+
+static void inka_digio_set_output(unsigned int state, int which)
+{
+ volatile struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+
+ if (which == 0) {
+ /* other */
+ CHECK_LED(0);
+ CHECK_LED(1);
+ CHECK_LED(2);
+ CHECK_LED(3);
+ CHECK_LED(4);
+ CHECK_LED(5);
+ } else {
+ if (which == 1) {
+ /* drawer1 */
+ if (state) {
+ clrbits_be32(&gpio->simple_dvo, 0x1000);
+ udelay(1);
+ setbits_be32(&gpio->simple_dvo, 0x1000);
+ } else {
+ setbits_be32(&gpio->simple_dvo, 0x1000);
+ udelay(1);
+ clrbits_be32(&gpio->simple_dvo, 0x1000);
+ }
+ }
+ if (which == 2) {
+ /* drawer 2 */
+ if (state) {
+ clrbits_be32(&gpio->simple_dvo, 0x2000);
+ udelay(1);
+ setbits_be32(&gpio->simple_dvo, 0x2000);
+ } else {
+ setbits_be32(&gpio->simple_dvo, 0x2000);
+ udelay(1);
+ clrbits_be32(&gpio->simple_dvo, 0x2000);
+ }
+ }
+ }
+ udelay(1);
+}
+
+static int do_inkadiag_io(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *argv[]) {
+ unsigned int state, val;
+
+ switch (argc) {
+ case 3:
+ /* Write a value */
+ val = simple_strtol(argv[2], NULL, 16);
+
+ if (strcmp(argv[1], "drawer1") == 0) {
+ inka_digio_set_output(val, 1);
+ } else if (strcmp(argv[1], "drawer2") == 0) {
+ inka_digio_set_output(val, 2);
+ } else if (strcmp(argv[1], "other") == 0)
+ inka_digio_set_output(val, 0);
+ else {
+ printf("Invalid argument: %s\n", argv[1]);
+ return -1;
+ }
+ /* fall through */
+ case 2:
+ /* Read a value */
+ state = inka_digin_get_input();
+
+ if (strcmp(argv[1], "drawer1") == 0) {
+ val = (state & DIGIN_DRAWER_SW1) >> (ffs(DIGIN_DRAWER_SW1) - 1);
+ } else if (strcmp(argv[1], "drawer2") == 0) {
+ val = (state & DIGIN_DRAWER_SW2) >> (ffs(DIGIN_DRAWER_SW2) - 1);
+ } else if (strcmp(argv[1], "other") == 0) {
+ val = ((state & DIGIN_KEYB_MASK) >> (ffs(DIGIN_KEYB_MASK) - 1))
+ | (state & DIGIN_TOUCHSCR_MASK) >> (ffs(DIGIN_TOUCHSCR_MASK) - 2);
+ } else {
+ printf("Invalid argument: %s\n", argv[1]);
+ return -1;
+ }
+ printf("exit code: 0x%X\n", val);
+ return 0;
+ default:
+ cmd_usage(cmdtp);
+ break;
+ }
+
+ return -1;
+}
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int ser_init(volatile struct mpc5xxx_psc *psc, int baudrate)
+{
+ unsigned long baseclk;
+ int div;
+
+ /* reset PSC */
+ out_8(&psc->command, PSC_SEL_MODE_REG_1);
+
+ /* select clock sources */
+
+ out_be16(&psc->psc_clock_select, 0);
+ baseclk = (gd->ipb_clk + 16) / 32;
+
+ /* switch to UART mode */
+ out_be32(&psc->sicr, 0);
+
+ /* configure parity, bit length and so on */
+
+ out_8(&psc->mode, PSC_MODE_8_BITS | PSC_MODE_PARNONE);
+ out_8(&psc->mode, PSC_MODE_ONE_STOP);
+
+ /* set up UART divisor */
+ div = (baseclk + (baudrate / 2)) / baudrate;
+ out_8(&psc->ctur, (div >> 8) & 0xff);
+ out_8(&psc->ctlr, div & 0xff);
+
+ /* disable all interrupts */
+ out_be16(&psc->psc_imr, 0);
+
+ /* reset and enable Rx/Tx */
+ out_8(&psc->command, PSC_RST_RX);
+ out_8(&psc->command, PSC_RST_TX);
+ out_8(&psc->command, PSC_RX_ENABLE | PSC_TX_ENABLE);
+
+ return 0;
+}
+
+static void ser_putc(volatile struct mpc5xxx_psc *psc, const char c)
+{
+ /* Wait 1 second for last character to go. */
+ int i = 0;
+
+ while (!(psc->psc_status & PSC_SR_TXEMP) && (i++ < 1000000/10))
+ udelay(10);
+ psc->psc_buffer_8 = c;
+
+}
+
+static int ser_getc(volatile struct mpc5xxx_psc *psc)
+{
+ /* Wait for a character to arrive. */
+ int i = 0;
+
+ while (!(in_be16(&psc->psc_status) & PSC_SR_RXRDY) && (i++ < 1000000/10))
+ udelay(10);
+
+ return in_8(&psc->psc_buffer_8);
+}
+
+static int do_inkadiag_serial(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *argv[]) {
+ volatile struct NS16550 *uart;
+ volatile struct mpc5xxx_psc *psc;
+ unsigned int num, mode;
+ int combrd, baudrate, i, j, len;
+ int address;
+
+ if (argc < 5) {
+ cmd_usage(cmdtp);
+ return 1;
+ }
+
+ argc--;
+ argv++;
+
+ num = simple_strtol(argv[0], NULL, 0);
+ if (num < 0 || num > 11) {
+ printf("invalid argument for num: %d\n", num);
+ return -1;
+ }
+
+ mode = simple_strtol(argv[1], NULL, 0);
+
+ combrd = 0;
+ baudrate = simple_strtoul(argv[2], NULL, 10);
+ for (i=0; i<N_BAUDRATES; ++i) {
+ if (baudrate == baudrate_table[i])
+ break;
+ }
+ if (i == N_BAUDRATES) {
+ printf("## Baudrate %d bps not supported\n",
+ baudrate);
+ return 1;
+ }
+ combrd = 115200 / baudrate;
+
+ uart = (struct NS16550 *)(SERIAL_PORT_BASE + (num << 3));
+
+ printf("Testing uart %d.\n\n", num);
+
+ if ((num >= 0) && (num <= 7)) {
+ if (mode & 1) {
+ /* turn on 'loopback' mode */
+ out_8(&uart->mcr, MCR_LOOP);
+ } else {
+ /*
+ * establish the UART's operational parameters
+ * set DLAB=1, so rbr accesses DLL
+ */
+ out_8(&uart->lcr, LCR_DLAB);
+ /* set baudrate */
+ out_8(&uart->rbr, combrd);
+ /* set data-format: 8-N-1 */
+ out_8(&uart->lcr, LCR_WLS_8);
+ }
+
+ if (mode & 2) {
+ /* set request to send */
+ out_8(&uart->mcr, MCR_RTS);
+ udelay(10);
+ /* check clear to send */
+ if ((in_8(&uart->msr) & MSR_CTS) == 0x00)
+ return -1;
+ }
+ if (mode & 4) {
+ /* set data terminal ready */
+ out_8(&uart->mcr, MCR_DTR);
+ udelay(10);
+ /* check data set ready and carrier detect */
+ if ((in_8(&uart->msr) & (MSR_DSR | MSR_DCD))
+ != (MSR_DSR | MSR_DCD))
+ return -1;
+ }
+
+ /* write each message-character, read it back, and display it */
+ for (i = 0, len = strlen(argv[3]); i < len; ++i) {
+ j = 0;
+ while ((in_8(&uart->lsr) & LSR_THRE) == 0x00) {
+ if (j++ > CONFIG_SYS_HZ)
+ break;
+ udelay(10);
+ }
+ out_8(&uart->rbr, argv[3][i]);
+ j = 0;
+ while ((in_8(&uart->lsr) & LSR_DR) == 0x00) {
+ if (j++ > CONFIG_SYS_HZ)
+ break;
+ udelay(10);
+ }
+ printf("%c", in_8(&uart->rbr));
+ }
+ printf("\n\n");
+ out_8(&uart->mcr, 0x00);
+ } else {
+ address = 0;
+
+ switch (num) {
+ case 8:
+ address = MPC5XXX_PSC6;
+ break;
+ case 9:
+ address = MPC5XXX_PSC3;
+ break;
+ case 10:
+ address = MPC5XXX_PSC2;
+ break;
+ case 11:
+ address = MPC5XXX_PSC1;
+ break;
+ }
+ psc = (struct mpc5xxx_psc *)address;
+ ser_init(psc, simple_strtol(argv[2], NULL, 0));
+ if (mode & 2) {
+ /* set request to send */
+ out_8(&psc->op0, PSC_OP0_RTS);
+ udelay(10);
+ /* check clear to send */
+ if ((in_8(&psc->ip) & PSC_IPCR_CTS) == 0)
+ return -1;
+ }
+ len = strlen(argv[3]);
+ for (i = 0; i < len; ++i) {
+ ser_putc(psc, argv[3][i]);
+ printf("%c", ser_getc(psc));
+ }
+ printf("\n\n");
+ }
+ return 0;
+}
+
+#define BUZZER_GPT (MPC5XXX_GPT + 0x60) /* GPT6 */
+static void buzzer_turn_on(unsigned int freq)
+{
+ volatile struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)(BUZZER_GPT);
+
+ const u32 prescale = gd->ipb_clk / freq / 128;
+ const u32 count = 128;
+ const u32 width = 64;
+
+ gpt->cir = (prescale << 16) | count;
+ gpt->pwmcr = width << 16;
+ gpt->emsr = 3; /* Timer enabled for PWM */
+}
+
+static void buzzer_turn_off(void)
+{
+ volatile struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)(BUZZER_GPT);
+
+ gpt->emsr = 0;
+}
+
+static int do_inkadiag_buzzer(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *argv[]) {
+
+ unsigned int period, freq;
+ int prev, i;
+
+ if (argc != 3) {
+ cmd_usage(cmdtp);
+ return 1;
+ }
+
+ argc--;
+ argv++;
+
+ period = simple_strtol(argv[0], NULL, 0);
+ if (!period)
+ printf("Zero period is senseless\n");
+ argc--;
+ argv++;
+
+ freq = simple_strtol(argv[0], NULL, 0);
+ /* avoid zero prescale in buzzer_turn_on() */
+ if (freq > gd->ipb_clk / 128) {
+ printf("%dHz exceeds maximum (%ldHz)\n", freq,
+ gd->ipb_clk / 128);
+ } else if (!freq)
+ printf("Zero frequency is senseless\n");
+ else
+ buzzer_turn_on(freq);
+
+ clear_ctrlc();
+ prev = disable_ctrlc(0);
+
+ printf("Buzzing for %d ms. Type ^C to abort!\n\n", period);
+
+ i = 0;
+ while (!ctrlc() && (i++ < CONFIG_SYS_HZ))
+ udelay(period);
+
+ clear_ctrlc();
+ disable_ctrlc(prev);
+
+ buzzer_turn_off();
+
+ return 0;
+}
+
+static int do_inkadiag_help(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
+
+cmd_tbl_t cmd_inkadiag_sub[] = {
+ U_BOOT_CMD_MKENT(io, 1, 1, do_inkadiag_io, "read digital input",
+ "<drawer1|drawer2|other> [value] - get or set specified signal\n"),
+ U_BOOT_CMD_MKENT(serial, 4, 1, do_inkadiag_serial, "test serial port",
+ "<num> <mode> <baudrate> <msg> - test uart num [0..11] in mode\n"
+ "and baudrate with msg\n"),
+ U_BOOT_CMD_MKENT(buzzer, 2, 1, do_inkadiag_buzzer, "activate buzzer",
+ "<period> <freq> - turn buzzer on for period ms with freq hz\n"),
+ U_BOOT_CMD_MKENT(help, 4, 1, do_inkadiag_help, "get help",
+ "[command] - get help for command\n"),
+};
+
+static int do_inkadiag_help(cmd_tbl_t *cmdtp, int flag,
+ int argc, char *argv[]) {
+ extern int _do_help (cmd_tbl_t *cmd_start, int cmd_items,
+ cmd_tbl_t *cmdtp, int flag,
+ int argc, char *argv[]);
+ /* do_help prints command name - we prepend inkadiag to our subcommands! */
+#ifdef CONFIG_SYS_LONGHELP
+ puts ("inkadiag ");
+#endif
+ return _do_help(&cmd_inkadiag_sub[0],
+ ARRAY_SIZE(cmd_inkadiag_sub), cmdtp, flag, argc, argv);
+}
+
+static int do_inkadiag(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *argv[]) {
+ cmd_tbl_t *c;
+
+ c = find_cmd_tbl(argv[1], &cmd_inkadiag_sub[0], ARRAY_SIZE(cmd_inkadiag_sub));
+
+ if (c) {
+ argc--;
+ argv++;
+ return c->cmd(c, flag, argc, argv);
+ } else {
+ /* Unrecognized command */
+ cmd_usage(cmdtp);
+ return 1;
+ }
+}
+
+U_BOOT_CMD(inkadiag, 6, 1, do_inkadiag,
+ "inkadiag - inka diagnosis\n",
+ "[inkadiag what ...]\n"
+ " - perform a diagnosis on inka hardware\n"
+ "'inkadiag' performs hardware tests.\n\n");
+
+/* Relocate the command table function pointers when running in RAM */
+int inkadiag_init_r (void) {
+ cmd_tbl_t *cmdtp;
+
+ for (cmdtp = &cmd_inkadiag_sub[0]; cmdtp !=
+ &cmd_inkadiag_sub[ARRAY_SIZE(cmd_inkadiag_sub)]; cmdtp++) {
+ ulong addr;
+
+ addr = (ulong) (cmdtp->cmd) + gd->reloc_off;
+ cmdtp->cmd = (int (*)(struct cmd_tbl_s *, int, int, char *[]))addr;
+
+ addr = (ulong)(cmdtp->name) + gd->reloc_off;
+ cmdtp->name = (char *)addr;
+
+ if (cmdtp->usage) {
+ addr = (ulong)(cmdtp->usage) + gd->reloc_off;
+ cmdtp->usage = (char *)addr;
+ }
+#ifdef CONFIG_SYS_LONGHELP
+ if (cmdtp->help) {
+ addr = (ulong)(cmdtp->help) + gd->reloc_off;
+ cmdtp->help = (char *)addr;
+ }
+#endif
+ }
+ return 0;
+}
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index a77942022a7..088f8045daa 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -184,12 +184,12 @@ sdram_init(void)
* MPC8548 uses "new" 15-16 style addressing.
*/
lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
- lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1516;
+ lsdmr_common |= LSDMR_BSMA1516;
/*
* Issue PRECHARGE ALL command.
*/
- lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_PCHALL;
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
@@ -199,7 +199,7 @@ sdram_init(void)
* Issue 8 AUTO REFRESH commands.
*/
for (idx = 0; idx < 8; idx++) {
- lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH;
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
@@ -209,7 +209,7 @@ sdram_init(void)
/*
* Issue 8 MODE-set command.
*/
- lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_MRW;
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
@@ -218,7 +218,7 @@ sdram_init(void)
/*
* Issue NORMAL OP command.
*/
- lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_NORMAL;
+ lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
asm("sync;msync");
*sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr);
diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c
index 52ad2d86c9d..9f696387eb2 100644
--- a/board/sbc8641d/sbc8641d.c
+++ b/board/sbc8641d/sbc8641d.c
@@ -413,3 +413,12 @@ void board_reset(void)
__asm__ __volatile__ ("rfi");
#endif
}
+
+#ifdef CONFIG_MP
+extern void cpu_mp_lmb_reserve(struct lmb *lmb);
+
+void board_lmb_reserve(struct lmb *lmb)
+{
+ cpu_mp_lmb_reserve(lmb);
+}
+#endif
generated by cgit v1.2.3 (git 2.0.4) at 2024-10-01 18:44:05 +0000