diff options
Diffstat (limited to 'board')
144 files changed, 2498 insertions, 11430 deletions
diff --git a/board/armadillo/armadillo.c b/board/armadillo/armadillo.c deleted file mode 100644 index a825144c5c..0000000000 --- a/board/armadillo/armadillo.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2005 Rowel Atienza <rowel@diwalabs.com> - * Armadillo board HT1070 - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <netdev.h> -#include <clps7111.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ - - -/* - * Miscelaneous platform dependent initialisations - */ - -int board_init (void) -{ - /* Activate LED flasher */ - IO_LEDFLSH = 0x40; - - /* arch number MACH_TYPE_ARMADILLO - not official*/ - gd->bd->bi_arch_number = 83; - - /* location of boot parameters */ - gd->bd->bi_boot_params = 0xc0000100; - - return 0; -} - -int dram_init (void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return (0); -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_CS8900 - rc = cs8900_initialize(0, CONFIG_CS8900_BASE); -#endif - return rc; -} -#endif diff --git a/board/armadillo/config.mk b/board/armadillo/config.mk deleted file mode 100644 index ecb8b745cf..0000000000 --- a/board/armadillo/config.mk +++ /dev/null @@ -1,29 +0,0 @@ -# -# (C) Copyright 2000 -# Sysgo Real-Time Solutions, GmbH <www.elinos.com> -# Marius Groeger <mgroeger@sysgo.de> -# -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -#address where u-boot will be relocated -CONFIG_SYS_TEXT_BASE = 0xc0f80000 diff --git a/board/armadillo/flash.c b/board/armadillo/flash.c deleted file mode 100644 index cf7d7f6a64..0000000000 --- a/board/armadillo/flash.c +++ /dev/null @@ -1,340 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2005 Rowel Atienza <rowel@diwalabs.com> - * Flash driver for armadillo board HT1070 - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -#define FLASH_BANK_SIZE 0x400000 - -/*value used by hermit is 0x200*/ -/*document says sector size is either 64k in low mem reg and 8k in high mem reg*/ -#define MAIN_SECT_SIZE 0x10000 - -#define UNALIGNED_MASK (3) -#define FL_WORD(addr) (*(volatile unsigned short*)(addr)) -#define FLASH_TIMEOUT 20000000 - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -/*----------------------------------------------------------------------- - */ - -ulong flash_init (void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - - flash_info[i].flash_id = (FUJ_MANUFACT & FLASH_VENDMASK); - /*(INTEL_ID_28F128J3 & FLASH_TYPEMASK); */ - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); - if (i == 0) - flashbase = PHYS_FLASH_1; - else - panic ("configured too many flash banks!\n"); - for (j = 0; j < flash_info[i].sector_count; j++) { - flash_info[i].start[j] = - flashbase + j * MAIN_SECT_SIZE; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case (FUJ_MANUFACT & FLASH_VENDMASK): - printf ("Fujitsu: "); - break; - default: - printf ("Unknown Vendor "); - break; - } -/* - switch (info->flash_id & FLASH_TYPEMASK) { - case (INTEL_ID_28F128J3 & FLASH_TYPEMASK): - printf ("28F128J3 (128Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - goto Done; - break; - } -*/ - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - -/* -Done: ; -*/ -} - -/* - * * Loop until both write state machines complete. - * */ -static unsigned short flash_status_wait (unsigned long addr, - unsigned short value) -{ - unsigned short status; - long timeout = FLASH_TIMEOUT; - - while (((status = (FL_WORD (addr))) != value) && timeout > 0) { - timeout--; - } - return status; -} - -/* - * Loop until the Write State machine is ready, then do a full error - * check. Clear status and leave the flash in Read Array mode; return - * 0 for no error, -1 for error. - */ -static int flash_status_full_check (unsigned long addr, unsigned short value1, - unsigned short value2) -{ - unsigned short status1, status2; - - status1 = flash_status_wait (addr, value1); - status2 = flash_status_wait (addr + 2, value2); - return (status1 != value1 || status2 != value2) ? -1 : 0; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - int rc = ERR_OK; - unsigned long base; - unsigned long addr; - ulong start; - - if ((info->flash_id & FLASH_VENDMASK) != - (FUJ_MANUFACT & FLASH_VENDMASK)) { - return ERR_UNKNOWN_FLASH_VENDOR; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) - return ERR_PROTECTED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - flag = disable_interrupts (); - - printf ("Erasing %d sectors starting at sector %2d.\n" - "This make take some time ... ", - s_last - s_first, sect); - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { - /* ARM simple, non interrupt dependent timer */ - start = get_timer(0); - - if (info->protect[sect] == 0) { /* not protected */ - - addr = sect * MAIN_SECT_SIZE; - addr &= ~(unsigned long) UNALIGNED_MASK; /* word align */ - base = addr & 0xF0000000; - - FL_WORD (base + (0x555 << 1)) = 0xAA; - FL_WORD (base + (0x2AA << 1)) = 0x55; - FL_WORD (base + (0x555 << 1)) = 0x80; - FL_WORD (base + (0x555 << 1)) = 0xAA; - FL_WORD (base + (0x2AA << 1)) = 0x55; - FL_WORD (addr) = 0x30; - if (flash_status_full_check (addr, 0xFFFF, 0xFFFF)) - return ERR_PROTECTED; - } - } - printf ("\nDone.\n"); - if (ctrlc ()) - printf ("User Interrupt!\n"); - - /* allow flash to settle - wait 10 ms */ - udelay_masked (10000); - - if (flag) - enable_interrupts (); - - return rc; -} - - -/*----------------------------------------------------------------------- - * Copy memory to flash - */ - -static int write_word (flash_info_t * info, ulong dest, ushort data) -{ - int flag; - unsigned long base; - ulong start; - - /* Check if Flash is (sufficiently) erased - */ - if ((FL_WORD (dest) & data) != data) - return ERR_NOT_ERASED; - - /*if(dest & UNALIGNED_MASK) return ERR_ALIGN; */ - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - flag = disable_interrupts (); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - base = dest & 0xF0000000; - FL_WORD (base + (0x555 << 1)) = 0xAA; - FL_WORD (base + (0x2AA << 1)) = 0x55; - FL_WORD (base + (0x555 << 1)) = 0xA0; - FL_WORD (dest) = data; - /*printf("writing 0x%p = 0x%x\n",dest,data); */ - if (flash_status_wait (dest, data) != data) - return ERR_PROG_ERROR; - - if (flag) - enable_interrupts (); - - return ERR_OK; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash. - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - ushort data; - int l; - int i, rc; - - wp = (addr & ~1); /* get lower word aligned address */ - printf ("Writing %lu short data to 0x%lx from 0x%p.\n ", cnt, wp, src); - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - for (; i < 2 && cnt > 0; ++i) { - data = (data >> 8) | (*src++ << 8); - --cnt; - ++cp; - } - for (; cnt == 0 && i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 2; - } - - /* - * handle word aligned part - */ - while (cnt >= 2) { - data = *((vu_short *) src); - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - src += 2; - wp += 2; - cnt -= 2; - } - - if (cnt == 0) { - printf ("\nDone.\n"); - return ERR_OK; - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 8); - --cnt; - } - for (; i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - - return write_word (info, wp, data); -} diff --git a/board/armadillo/lowlevel_init.S b/board/armadillo/lowlevel_init.S deleted file mode 100644 index e7d373d274..0000000000 --- a/board/armadillo/lowlevel_init.S +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Initialization stuff - taken from hermit - * (C) Copyright 2005 Rowel Atienza <rowel@diwalabs.com> - * Armadillo board HT1070 - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include <config.h> -#include <version.h> - - -/* some parameters for the board */ -/* setting up the memory */ -#define SRAM_START 0x60000000 -#define SRAM_SIZE 0x0000c000 - -.globl lowlevel_init -lowlevel_init: - mov r0, #0x70 /* 32-bit code + data, MMU mandatory */ - mcr p15, 0, r0, c1, c0, 0 /* MMU init */ - - mov r0, #0 - mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ - mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ - - mov r0, #0x80000000 /* I/O base */ - - mov r1, #0x6 /* CLKCTL_73 in SYSCON3 */ - add r2, r0, #0x2200 /* address of SYSCON3 in r2 */ - str r1, [r2] /* set clock speed to 73.728 MHz */ - - mov r1, #0x81 /* 64KHz DRAM refresh period */ - str r1, [r0, #0x200] /* set DRFPR */ - - mov r1, #0x500 /* permanent enable, 16bits wide */ - add r1, r1, #0x42 /* 128Mbit, CAS lat = 2 SDRAM */ - add r2, r0, #0x2300 /* load address in r2 */ - str r1, [r2] - - mov r1, #0x100 /* SDRAM refresh rate */ - add r2, r0, #0x2340 /* load address in r2 */ - str r1, [r2] - - mov sp, #SRAM_START /* init stack pointer */ - add sp, sp, #SRAM_SIZE - - /* everything is fine now */ - mov pc, lr diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c index 9bb56b5208..c8d2bc7bac 100644 --- a/board/armltd/integrator/integrator.c +++ b/board/armltd/integrator/integrator.c @@ -86,15 +86,9 @@ int misc_init_r (void) return (0); } -/****************************** - Routine: - Description: -******************************/ int dram_init (void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; #ifdef CONFIG_CM_SPD_DETECT { extern void dram_query(void); @@ -118,8 +112,13 @@ extern void dram_query(void); */ sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4; gd->bd->bi_dram[0].size = 0x01000000 << sdram_shift; - + gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + 0x01000000 << sdram_shift); } +#else + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + PHYS_SDRAM_1_SIZE); #endif /* CM_SPD_DETECT */ return 0; diff --git a/board/armltd/integrator/lowlevel_init.S b/board/armltd/integrator/lowlevel_init.S index ab9589c95c..6f55bb548c 100644 --- a/board/armltd/integrator/lowlevel_init.S +++ b/board/armltd/integrator/lowlevel_init.S @@ -199,7 +199,7 @@ cm_remap: /* Now 0x00000000 is writeable, replace the vectors */ ldr r0, =_start /* r0 <- start of vectors */ - ldr r2, =_armboot_start /* r2 <- past vectors */ + ldr r2, =_TEXT_BASE /* r2 <- past vectors */ sub r1,r1,r1 /* destination 0x00000000 */ copy_vec: diff --git a/board/armltd/integrator/split_by_variant.sh b/board/armltd/integrator/split_by_variant.sh deleted file mode 100755 index 19fc832c2a..0000000000 --- a/board/armltd/integrator/split_by_variant.sh +++ /dev/null @@ -1,220 +0,0 @@ -#!/bin/sh - -mkdir -p ${obj}include -mkdir -p ${obj}board/armltd/integrator - -config_file=${obj}include/config.h - -if [ "$1" = "ap" ] -then -# --------------------------------------------------------- -# Set the platform defines -# --------------------------------------------------------- -cat > ${config_file} << _EOF -/* Integrator configuration implied by Makefile target */ -#define CONFIG_INTEGRATOR /* Integrator board */ -#define CONFIG_ARCH_INTEGRATOR 1 /* Integrator/AP */ -_EOF - -# --------------------------------------------------------- -# Set the core module defines according to Core Module -# --------------------------------------------------------- -cpu="arm_intcm" -variant="unknown core module" - -if [ "$2" = "" ] -then - echo "$0:: No parameters - using arm_intcm" -else - case "$2" in - ap7_config) - cpu="arm_intcm" - variant="unported core module CM7TDMI" - ;; - - ap966) - cpu="arm_intcm" - variant="unported core module CM966E-S" - ;; - - ap922_config) - cpu="arm_intcm" - variant="unported core module CM922T" - ;; - - integratorap_config | \ - ap_config) - cpu="arm_intcm" - variant="unspecified core module" - ;; - - ap720t_config) - cpu="arm720t" - echo "#define CONFIG_CM720T 1 /* CPU core is ARM720T */" \ - >> ${config_file} - variant="Core module CM720T" - ;; - - ap922_XA10_config) - cpu="arm_intcm" - variant="unported core module CM922T_XA10" - echo "#define CONFIG_CM922T_XA10 1 /* CPU core is ARM922T_XA10 */" \ - >> ${config_file} - ;; - - ap920t_config) - cpu="arm920t" - variant="Core module CM920T" - echo "#define CONFIG_CM920T 1 /* CPU core is ARM920T */" \ - >> ${config_file} - ;; - - ap926ejs_config) - cpu="arm926ejs" - variant="Core module CM926EJ-S" - echo "#define CONFIG_CM926EJ_S 1 /* CPU core is ARM926EJ-S */" \ - >> ${config_file} - ;; - - ap946es_config) - cpu="arm946es" - variant="Core module CM946E-S" - echo "#define CONFIG_CM946E_S 1 /* CPU core is ARM946E-S */" \ - >> ${config_file} - ;; - - *) - echo "$0:: Unknown core module" - variant="unknown core module" - cpu="arm_intcm" - ;; - - esac -fi - -case "$cpu" in - arm_intcm) - cat >> ${config_file} << _EOF -/* Core module undefined/not ported */ -#define CONFIG_ARM_INTCM 1 -#undef CONFIG_CM_MULTIPLE_SSRAM /* CM may not have multiple SSRAM mapping */ -#undef CONFIG_CM_SPD_DETECT /* CM may not support SPD query */ -#undef CONFIG_CM_REMAP /* CM may not support remapping */ -#undef CONFIG_CM_INIT /* CM may not have initialization reg */ -#undef CONFIG_CM_TCRAM /* CM may not have TCRAM */ -/* May not be processor without cache support */ -#define CONFIG_SYS_ICACHE_OFF 1 -#define CONFIG_SYS_DCACHE_OFF 1 -_EOF - ;; - - arm720t) - cat >> ${config_file} << _EOF -/* May not be processor without cache support */ -#define CONFIG_SYS_ICACHE_OFF 1 -#define CONFIG_SYS_DCACHE_OFF 1 -_EOF - ;; -esac - -else - -# --------------------------------------------------------- -# Set the platform defines -# --------------------------------------------------------- -cat >> ${config_file} << _EOF -/* Integrator configuration implied by Makefile target */ -#define CONFIG_INTEGRATOR /* Integrator board */ -#define CONFIG_ARCH_CINTEGRATOR 1 /* Integrator/CP */ -_EOF - -cpu="arm_intcm" -variant="unknown core module" - -if [ "$2" = "" ] -then - echo "$0:: No parameters - using arm_intcm" -else - case "$2" in - ap966) - cpu="arm_intcm" - variant="unported core module CM966E-S" - ;; - - ap922_config) - cpu="arm_intcm" - variant="unported core module CM922T" - ;; - - integratorcp_config | \ - cp_config) - cpu="arm_intcm" - variant="unspecified core module" - ;; - - cp922_XA10_config) - cpu="arm_intcm" - variant="unported core module CM922T_XA10" - echo "#define CONFIG_CM922T_XA10 1 /* CPU core is ARM922T_XA10 */" \ - >> ${config_file} - ;; - - cp920t_config) - cpu="arm920t" - variant="Core module CM920T" - echo "#define CONFIG_CM920T 1 /* CPU core is ARM920T */" \ - >> ${config_file} - ;; - - cp926ejs_config) - cpu="arm926ejs" - variant="Core module CM926EJ-S" - echo "#define CONFIG_CM926EJ_S 1 /* CPU core is ARM926EJ-S */" \ - >> ${config_file} - ;; - - - cp946es_config) - cpu="arm946es" - variant="Core module CM946E-S" - echo "#define CONFIG_CM946E_S 1 /* CPU core is ARM946E-S */" \ - >> ${config_file} - ;; - - cp1136_config) - cpu="arm1136" - variant="Core module CM1136EJF-S" - echo "#define CONFIG_CM1136EJF_S 1 /* CPU core is ARM1136JF-S */" \ - >> ${config_file} - ;; - - *) - echo "$0:: Unknown core module" - variant="unknown core module" - cpu="arm_intcm" - ;; - - esac - -fi - -if [ "$cpu" = "arm_intcm" ] -then - cat >> ${config_file} << _EOF -/* Core module undefined/not ported */ -#define CONFIG_ARM_INTCM 1 -#undef CONFIG_CM_MULTIPLE_SSRAM /* CM may not have multiple SSRAM mapping */ -#undef CONFIG_CM_SPD_DETECT /* CM may not support SPD query */ -#undef CONFIG_CM_REMAP /* CM may not support remapping */ -#undef CONFIG_CM_INIT /* CM may not have initialization reg */ -#undef CONFIG_CM_TCRAM /* CM may not have TCRAM */ -_EOF -fi - -fi # ap - -# --------------------------------------------------------- -# Complete the configuration -# --------------------------------------------------------- -$MKCONFIG -a -n "${2%%_config}" integrator$1 arm $cpu integrator armltd -echo "Variant: $variant with core $cpu" diff --git a/board/armltd/versatile/versatile.c b/board/armltd/versatile/versatile.c index ee8cb5e3c7..4a5c31dbf7 100644 --- a/board/armltd/versatile/versatile.c +++ b/board/armltd/versatile/versatile.c @@ -94,7 +94,7 @@ int misc_init_r (void) int dram_init (void) { /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE); return 0; } diff --git a/board/assabet/Makefile b/board/assabet/Makefile deleted file mode 100644 index b3cf4aa01c..0000000000 --- a/board/assabet/Makefile +++ /dev/null @@ -1,53 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# 2004 (c) MontaVista Software, Inc. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := assabet.o -SOBJS := setup.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/assabet/assabet.c b/board/assabet/assabet.c deleted file mode 100644 index 753c8d2435..0000000000 --- a/board/assabet/assabet.c +++ /dev/null @@ -1,131 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * 2004 (c) MontaVista Software, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <netdev.h> -#include <SA-1100.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ - -/* - * Board dependent initialisation - */ - -#define ECOR 0x8000 -#define ECOR_RESET 0x80 -#define ECOR_LEVEL_IRQ 0x40 -#define ECOR_WR_ATTRIB 0x04 -#define ECOR_ENABLE 0x01 - -#define ECSR 0x8002 -#define ECSR_IOIS8 0x20 -#define ECSR_PWRDWN 0x04 -#define ECSR_INT 0x02 -#define SMC_IO_SHIFT 2 -#define NCR_0 (*((volatile u_char *)(0x100000a0))) -#define NCR_ENET_OSC_EN (1<<3) - -static inline u8 -readb(volatile u8 * p) -{ - return *p; -} - -static inline void -writeb(u8 v, volatile u8 * p) -{ - *p = v; -} - -static void -smc_init(void) -{ - u8 ecor; - u8 ecsr; - volatile u8 *addr = (volatile u8 *)(0x18000000 + (1 << 25)); - - NCR_0 |= NCR_ENET_OSC_EN; - udelay(100); - - ecor = readb(addr + (ECOR << SMC_IO_SHIFT)) & ~ECOR_RESET; - writeb(ecor | ECOR_RESET, addr + (ECOR << SMC_IO_SHIFT)); - udelay(100); - - /* - * The device will ignore all writes to the enable bit while - * reset is asserted, even if the reset bit is cleared in the - * same write. Must clear reset first, then enable the device. - */ - writeb(ecor, addr + (ECOR << SMC_IO_SHIFT)); - writeb(ecor | ECOR_ENABLE, addr + (ECOR << SMC_IO_SHIFT)); - - /* - * Set the appropriate byte/word mode. - */ - ecsr = readb(addr + (ECSR << SMC_IO_SHIFT)) & ~ECSR_IOIS8; - ecsr |= ECSR_IOIS8; - writeb(ecsr, addr + (ECSR << SMC_IO_SHIFT)); - udelay(100); -} - -static void -neponset_init(void) -{ - smc_init(); -} - -int -board_init(void) -{ - gd->bd->bi_arch_number = MACH_TYPE_ASSABET; - gd->bd->bi_boot_params = 0xc0000100; - - neponset_init(); - - return 0; -} - -int -dram_init(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return (0); -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_LAN91C96 - rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE); -#endif - return rc; -} -#endif diff --git a/board/assabet/config.mk b/board/assabet/config.mk deleted file mode 100644 index d9866a0eb2..0000000000 --- a/board/assabet/config.mk +++ /dev/null @@ -1,7 +0,0 @@ -# -# SA-1110 based Intel Assabet board -# -# The Intel Assabet 1 bank of 32 MiB SDRAM -# - -CONFIG_SYS_TEXT_BASE = 0xc1f00000 diff --git a/board/assabet/setup.S b/board/assabet/setup.S deleted file mode 100644 index 56ea0dd928..0000000000 --- a/board/assabet/setup.S +++ /dev/null @@ -1,136 +0,0 @@ -/* - * Memory Setup stuff - taken from blob memsetup.S - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and - * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) - * 2004 (c) MontaVista Software, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include "config.h" -#include "version.h" - - -/*----------------------------------------------------------------------- - * Board defines: - */ - -#define MDCNFG 0x00 -#define MDCAS00 0x04 -#define MDCAS01 0x08 -#define MDCAS02 0x0C -#define MSC0 0x10 -#define MSC1 0x14 -#define MECR 0x18 -#define MDREFR 0x1C -#define MDCAS20 0x20 -#define MDCAS21 0x24 -#define MDCAS22 0x28 -#define MSC2 0x2C -#define SMCNFG 0x30 - -#define ASSABET_BCR (0x12000000) -#define ASSABET_BCR_DB1110 (0x00a07490 | (0<<16) | (0<<17)) -#define ASSABET_SCR_nNEPONSET (1 << 9) -#define NEPONSET_LEDS (0x10000010) - - -/*----------------------------------------------------------------------- - * Setup parameters for the board: - */ - - -MEM_BASE: .long 0xa0000000 -MEM_START: .long 0xc0000000 - -mdcnfg: .long 0x72547254 -mdcas00: .long 0xaaaaaa7f -mdcas01: .long 0xaaaaaaaa -mdcas02: .long 0xaaaaaaaa -msc0: .long 0x4b384370 -msc1: .long 0x22212419 -mecr: .long 0x994a994a -mdrefr: .long 0x04340327 -mdcas20: .long 0xaaaaaa7f -mdcas21: .long 0xaaaaaaaa -mdcas22: .long 0xaaaaaaaa -msc2: .long 0x42196669 -smcnfg: .long 0x00000000 - -BCR: .long ASSABET_BCR -BCR_DB1110: .long ASSABET_BCR_DB1110 -LEDS: .long NEPONSET_LEDS - - - .globl lowlevel_init -lowlevel_init: - - /* Setting up the memory and stuff */ - - ldr r0, MEM_BASE - ldr r1, mdcas00 - str r1, [r0, #MDCAS00] - ldr r1, mdcas01 - str r1, [r0, #MDCAS01] - ldr r1, mdcas02 - str r1, [r0, #MDCAS02] - ldr r1, mdcas20 - str r1, [r0, #MDCAS20] - ldr r1, mdcas21 - str r1, [r0, #MDCAS21] - ldr r1, mdcas22 - str r1, [r0, #MDCAS22] - ldr r1, mdrefr - str r1, [r0, #MDREFR] - ldr r1, mecr - str r1, [r0, #MECR] - ldr r1, msc0 - str r1, [r0, #MSC0] - ldr r1, msc1 - str r1, [r0, #MSC1] - ldr r1, msc2 - str r1, [r0, #MSC2] - ldr r1, smcnfg - str r1, [r0, #SMCNFG] - - ldr r1, mdcnfg - str r1, [r0, #MDCNFG] - - /* Load something to activate bank */ - ldr r2, MEM_START -.rept 8 - ldr r3, [r2] -.endr - - /* Enable SDRAM */ - orr r1, r1, #0x00000001 - str r1, [r0, #MDCNFG] - - ldr r1, BCR - ldr r2, BCR_DB1110 - str r2, [r1] - - ldr r1, LEDS - mov r0, #0x3 - str r0, [r1] - - /* All done... */ - mov pc, lr diff --git a/board/atmel/at91cap9adk/Makefile b/board/atmel/at91cap9adk/Makefile deleted file mode 100644 index 2eec0ce231..0000000000 --- a/board/atmel/at91cap9adk/Makefile +++ /dev/null @@ -1,56 +0,0 @@ -# -# (C) Copyright 2003-2008 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2008 -# Stelian Pop <stelian.pop@leadtechdesign.com> -# Lead Tech Design <www.leadtechdesign.com> -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += at91cap9adk.o -COBJS-y += led.o -COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/atmel/at91cap9adk/at91cap9adk.c b/board/atmel/at91cap9adk/at91cap9adk.c deleted file mode 100644 index 2ab8bc2c43..0000000000 --- a/board/atmel/at91cap9adk/at91cap9adk.c +++ /dev/null @@ -1,352 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop <stelian.pop@leadtechdesign.com> - * Lead Tech Design <www.leadtechdesign.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/arch/at91cap9.h> -#include <asm/arch/at91cap9_matrix.h> -#include <asm/arch/at91sam9_smc.h> -#include <asm/arch/at91_common.h> -#include <asm/arch/at91_pmc.h> -#include <asm/arch/at91_rstc.h> -#include <asm/arch/clk.h> -#include <asm/arch/gpio.h> -#include <asm/arch/io.h> -#include <asm/arch/hardware.h> -#include <lcd.h> -#include <atmel_lcdc.h> -#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) -#include <net.h> -#endif -#include <netdev.h> - -#define MP_BLOCK_3_BASE 0xFDF00000 - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ -/* - * Miscelaneous platform dependent initialisations - */ - -static void at91cap9_slowclock_hw_init(void) -{ - /* - * On AT91CAP9 revC CPUs, the slow clock can be based on an - * internal impreciseRC oscillator or an external 32kHz oscillator. - * Switch to the latter. - */ -#define ARCH_ID_AT91CAP9_REVB 0x399 -#define ARCH_ID_AT91CAP9_REVC 0x601 - if (at91_sys_read(AT91_PMC_VER) == ARCH_ID_AT91CAP9_REVC) { - unsigned i, tmp = at91_sys_read(AT91_SCKCR); - if ((tmp & AT91CAP9_SCKCR_OSCSEL) == AT91CAP9_SCKCR_OSCSEL_RC) { - timer_init(); - tmp |= AT91CAP9_SCKCR_OSC32EN; - at91_sys_write(AT91_SCKCR, tmp); - for (i = 0; i < 1200; i++) - udelay(1000); - tmp |= AT91CAP9_SCKCR_OSCSEL_32; - at91_sys_write(AT91_SCKCR, tmp); - udelay(200); - tmp &= ~AT91CAP9_SCKCR_RCEN; - at91_sys_write(AT91_SCKCR, tmp); - } - } -} - -static void at91cap9_nor_hw_init(void) -{ - unsigned long csa; - - /* Ensure EBI supply is 3.3V */ - csa = at91_sys_read(AT91_MATRIX_EBICSA); - at91_sys_write(AT91_MATRIX_EBICSA, - csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V); - /* Configure SMC CS0 for parallel flash */ - at91_sys_write(AT91_SMC_SETUP(0), - AT91_SMC_NWESETUP_(4) | AT91_SMC_NCS_WRSETUP_(2) | - AT91_SMC_NRDSETUP_(4) | AT91_SMC_NCS_RDSETUP_(2)); - at91_sys_write(AT91_SMC_PULSE(0), - AT91_SMC_NWEPULSE_(8) | AT91_SMC_NCS_WRPULSE_(10) | - AT91_SMC_NRDPULSE_(8) | AT91_SMC_NCS_RDPULSE_(10)); - at91_sys_write(AT91_SMC_CYCLE(0), - AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16)); - at91_sys_write(AT91_SMC_MODE(0), - AT91_SMC_READMODE | AT91_SMC_WRITEMODE | - AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | - AT91_SMC_DBW_16 | AT91_SMC_TDF_(1)); -} - -#ifdef CONFIG_CMD_NAND -static void at91cap9_nand_hw_init(void) -{ - unsigned long csa; - - /* Enable CS3 */ - csa = at91_sys_read(AT91_MATRIX_EBICSA); - at91_sys_write(AT91_MATRIX_EBICSA, - csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA | - AT91_MATRIX_EBI_VDDIOMSEL_3_3V); - - /* Configure SMC CS3 for NAND/SmartMedia */ - at91_sys_write(AT91_SMC_SETUP(3), - AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(1) | - AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(1)); - at91_sys_write(AT91_SMC_PULSE(3), - AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(6) | - AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(6)); - at91_sys_write(AT91_SMC_CYCLE(3), - AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(8)); - at91_sys_write(AT91_SMC_MODE(3), - AT91_SMC_READMODE | AT91_SMC_WRITEMODE | - AT91_SMC_EXNWMODE_DISABLE | -#ifdef CONFIG_SYS_NAND_DBW_16 - AT91_SMC_DBW_16 | -#else /* CONFIG_SYS_NAND_DBW_8 */ - AT91_SMC_DBW_8 | -#endif - AT91_SMC_TDF_(1)); - - at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_PIOABCD); - - /* RDY/BSY is not connected */ - - /* Enable NandFlash */ - at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); -} -#endif - -#ifdef CONFIG_MACB -static void at91cap9_macb_hw_init(void) -{ - /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_EMAC); - - /* - * Disable pull-up on: - * RXDV (PB22) => PHY normal mode (not Test mode) - * ERX0 (PB25) => PHY ADDR0 - * ERX1 (PB26) => PHY ADDR1 => PHYADDR = 0x0 - * - * PHY has internal pull-down - */ - writel(pin_to_mask(AT91_PIN_PB22) | - pin_to_mask(AT91_PIN_PB25) | - pin_to_mask(AT91_PIN_PB26), - pin_to_controller(AT91_PIN_PA0) + PIO_PUDR); - - /* Need to reset PHY -> 500ms reset */ - at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | - (AT91_RSTC_ERSTL & (0x0D << 8)) | - AT91_RSTC_URSTEN); - - at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); - - /* Wait for end hardware reset */ - while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)); - - /* Restore NRST value */ - at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | - (AT91_RSTC_ERSTL & (0x0 << 8)) | - AT91_RSTC_URSTEN); - - /* Re-enable pull-up */ - writel(pin_to_mask(AT91_PIN_PB22) | - pin_to_mask(AT91_PIN_PB25) | - pin_to_mask(AT91_PIN_PB26), - pin_to_controller(AT91_PIN_PA0) + PIO_PUER); - - at91_macb_hw_init(); - - /* Unlock EMAC, 3 0 2 1 sequence */ -#define MP_MAC_KEY0 0x5969cb2a -#define MP_MAC_KEY1 0xb4a1872e -#define MP_MAC_KEY2 0x05683fbc -#define MP_MAC_KEY3 0x3634fba4 -#define UNLOCK_MAC 0x00000008 - writel(MP_MAC_KEY3, MP_BLOCK_3_BASE + 0x3c); - writel(MP_MAC_KEY0, MP_BLOCK_3_BASE + 0x30); - writel(MP_MAC_KEY2, MP_BLOCK_3_BASE + 0x38); - writel(MP_MAC_KEY1, MP_BLOCK_3_BASE + 0x34); - writel(UNLOCK_MAC, MP_BLOCK_3_BASE + 0x40); -} -#endif - -#ifdef CONFIG_USB_OHCI_NEW -static void at91cap9_uhp_hw_init(void) -{ - /* Unlock USB OHCI, 3 2 0 1 sequence */ -#define MP_OHCI_KEY0 0x896c11ca -#define MP_OHCI_KEY1 0x68ebca21 -#define MP_OHCI_KEY2 0x4823efbc -#define MP_OHCI_KEY3 0x8651aae4 -#define UNLOCK_OHCI 0x00000010 - writel(MP_OHCI_KEY3, MP_BLOCK_3_BASE + 0x3c); - writel(MP_OHCI_KEY2, MP_BLOCK_3_BASE + 0x38); - writel(MP_OHCI_KEY0, MP_BLOCK_3_BASE + 0x30); - writel(MP_OHCI_KEY1, MP_BLOCK_3_BASE + 0x34); - writel(UNLOCK_OHCI, MP_BLOCK_3_BASE + 0x40); -} -#endif - -#ifdef CONFIG_LCD -vidinfo_t panel_info = { - vl_col: 240, - vl_row: 320, - vl_clk: 4965000, - vl_sync: ATMEL_LCDC_INVLINE_INVERTED | - ATMEL_LCDC_INVFRAME_INVERTED, - vl_bpix: 3, - vl_tft: 1, - vl_hsync_len: 5, - vl_left_margin: 1, - vl_right_margin:33, - vl_vsync_len: 1, - vl_upper_margin:1, - vl_lower_margin:0, - mmio: AT91CAP9_LCDC_BASE, -}; - -void lcd_enable(void) -{ - at91_set_gpio_value(AT91_PIN_PC0, 0); /* power up */ -} - -void lcd_disable(void) -{ - at91_set_gpio_value(AT91_PIN_PC0, 1); /* power down */ -} - -static void at91cap9_lcd_hw_init(void) -{ - at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */ - at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */ - at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */ - at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */ - at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */ - at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */ - at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */ - at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */ - at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */ - at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */ - at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */ - at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */ - at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */ - at91_set_A_periph(AT91_PIN_PC17, 0); /* LCDD13 */ - at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */ - at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */ - at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */ - at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */ - at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */ - at91_set_A_periph(AT91_PIN_PC25, 0); /* LCDD21 */ - at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */ - at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */ - - at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_LCDC); - - gd->fb_base = 0; -} - -#ifdef CONFIG_LCD_INFO -#include <nand.h> -#include <version.h> - -void lcd_show_board_info(void) -{ - ulong dram_size, nand_size; - int i; - char temp[32]; - - lcd_printf ("%s\n", U_BOOT_VERSION); - lcd_printf ("(C) 2008 ATMEL Corp\n"); - lcd_printf ("at91support@atmel.com\n"); - lcd_printf ("%s CPU at %s MHz\n", - CONFIG_SYS_AT91_CPU_NAME, - strmhz(temp, get_cpu_clk_rate())); - - dram_size = 0; - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) - dram_size += gd->bd->bi_dram[i].size; - nand_size = 0; - for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) - nand_size += nand_info[i].size; - lcd_printf (" %ld MB SDRAM, %ld MB NAND\n", - dram_size >> 20, - nand_size >> 20 ); -} -#endif /* CONFIG_LCD_INFO */ -#endif - -int board_init(void) -{ - /* Enable Ctrlc */ - console_init_f(); - - /* arch number of AT91CAP9ADK-Board */ - gd->bd->bi_arch_number = MACH_TYPE_AT91CAP9ADK; - /* adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - at91_serial_hw_init(); - at91cap9_slowclock_hw_init(); - at91cap9_nor_hw_init(); -#ifdef CONFIG_CMD_NAND - at91cap9_nand_hw_init(); -#endif -#ifdef CONFIG_HAS_DATAFLASH - at91_spi0_hw_init(1 << 0); -#endif -#ifdef CONFIG_MACB - at91cap9_macb_hw_init(); -#endif -#ifdef CONFIG_USB_OHCI_NEW - at91cap9_uhp_hw_init(); -#endif -#ifdef CONFIG_LCD - at91cap9_lcd_hw_init(); -#endif - return 0; -} - -int dram_init(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; - return 0; -} - -#ifdef CONFIG_RESET_PHY_R -void reset_phy(void) -{ -} -#endif - -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)AT91CAP9_BASE_EMAC, 0x00); -#endif - return rc; -} diff --git a/board/atmel/at91cap9adk/config.mk b/board/atmel/at91cap9adk/config.mk deleted file mode 100644 index 797da0eafe..0000000000 --- a/board/atmel/at91cap9adk/config.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x73000000 diff --git a/board/atmel/at91cap9adk/led.c b/board/atmel/at91cap9adk/led.c deleted file mode 100644 index 14aea994e9..0000000000 --- a/board/atmel/at91cap9adk/led.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop <stelian.pop@leadtechdesign.com> - * Lead Tech Design <www.leadtechdesign.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/arch/at91cap9.h> -#include <asm/arch/at91_pmc.h> -#include <asm/arch/gpio.h> -#include <asm/arch/io.h> - -void coloured_LED_init(void) -{ - /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_PIOABCD); - - at91_set_gpio_output(CONFIG_RED_LED, 1); - at91_set_gpio_output(CONFIG_GREEN_LED, 1); - at91_set_gpio_output(CONFIG_YELLOW_LED, 1); - - at91_set_gpio_output(CONFIG_RED_LED, 0); - at91_set_gpio_output(CONFIG_GREEN_LED, 1); - at91_set_gpio_output(CONFIG_YELLOW_LED, 1); -} diff --git a/board/atmel/at91cap9adk/partition.c b/board/atmel/at91cap9adk/partition.c deleted file mode 100644 index 7e1d46f530..0000000000 --- a/board/atmel/at91cap9adk/partition.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * (C) Copyright 2008 - * Ulf Samuelsson <ulf@atmel.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ -#include <common.h> -#include <config.h> -#include <asm/hardware.h> -#include <dataflash.h> - -AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS]; - -struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = { - {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ -}; - -/*define the area offsets*/ -dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { - {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"}, - {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"}, - {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"}, - {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"}, - {0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"}, -}; diff --git a/board/atmel/at91rm9200dk/Makefile b/board/atmel/at91rm9200dk/Makefile deleted file mode 100644 index bc3dbc609d..0000000000 --- a/board/atmel/at91rm9200dk/Makefile +++ /dev/null @@ -1,56 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS-y += $(BOARD).o -COBJS-y += flash.o -COBJS-y += led.o -ifdef CONFIG_HAS_DATAFLASH -COBJS-$(CONFIG_DATAFLASH_MMC_SELECT) += mux.o -COBJS-y += partition.o -endif - -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/atmel/at91rm9200dk/at91rm9200dk.c b/board/atmel/at91rm9200dk/at91rm9200dk.c deleted file mode 100644 index 49b5fe3203..0000000000 --- a/board/atmel/at91rm9200dk/at91rm9200dk.c +++ /dev/null @@ -1,167 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <exports.h> -#include <netdev.h> -#include <asm/arch/AT91RM9200.h> -#include <asm/io.h> - -#if defined(CONFIG_DRIVER_ETHER) -#include <at91rm9200_net.h> -#include <dm9161.h> -#endif - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ -/* - * Miscelaneous platform dependent initialisations - */ - -int board_init (void) -{ - /* Enable Ctrlc */ - console_init_f (); - - /* Correct IRDA resistor problem */ - /* Set PA23_TXD in Output */ - ((AT91PS_PIO) AT91C_BASE_PIOA)->PIO_OER = AT91C_PA23_TXD2; - - /* memory and cpu-speed are setup before relocation */ - /* so we do _nothing_ here */ - - /* arch number of AT91RM9200DK-Board */ - gd->bd->bi_arch_number = MACH_TYPE_AT91RM9200DK; - /* adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - return 0; -} - -void board_reset (void) -{ - AT91PS_PIO pio = AT91C_BASE_PIOA; - - /* Clear PA19 to trigger the hard reset */ - writel(0x00080000, pio->PIO_CODR); - writel(0x00080000, pio->PIO_OER); - writel(0x00080000, pio->PIO_PER); -} - -int dram_init (void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; - return 0; -} - -#ifdef CONFIG_DRIVER_ETHER -#if defined(CONFIG_CMD_NET) - -/* - * Name: - * at91rm9200_GetPhyInterface - * Description: - * Initialise the interface functions to the PHY - * Arguments: - * None - * Return value: - * None - */ -void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops) -{ - p_phyops->Init = dm9161_InitPhy; - p_phyops->IsPhyConnected = dm9161_IsPhyConnected; - p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed; - p_phyops->AutoNegotiate = dm9161_AutoNegotiate; -} - -#endif -#endif /* CONFIG_DRIVER_ETHER */ - -#ifdef CONFIG_DRIVER_AT91EMAC -int board_eth_init(bd_t *bis) -{ - int rc = 0; - rc = at91emac_register(bis, 0); - return rc; -} -#endif - -/* - * Disk On Chip (NAND) Millenium initialization. - * The NAND lives in the CS2* space - */ -#if defined(CONFIG_CMD_NAND) -extern ulong nand_probe (ulong physadr); - -#define AT91_SMARTMEDIA_BASE 0x40000000 /* physical address to access memory on NCS3 */ -void nand_init (void) -{ - /* Setup Smart Media, fitst enable the address range of CS3 */ - *AT91C_EBI_CSA |= AT91C_EBI_CS3A_SMC_SmartMedia; - /* set the bus interface characteristics based on - tDS Data Set up Time 30 - ns - tDH Data Hold Time 20 - ns - tALS ALE Set up Time 20 - ns - 16ns at 60 MHz ~= 3 */ -/*memory mapping structures */ -#define SM_ID_RWH (5 << 28) -#define SM_RWH (1 << 28) -#define SM_RWS (0 << 24) -#define SM_TDF (1 << 8) -#define SM_NWS (3) - AT91C_BASE_SMC2->SMC2_CSR[3] = (SM_RWH | SM_RWS | - AT91C_SMC2_ACSS_STANDARD | AT91C_SMC2_DBW_8 | - SM_TDF | AT91C_SMC2_WSEN | SM_NWS); - - /* enable the SMOE line PC0=SMCE, A21=CLE, A22=ALE */ - *AT91C_PIOC_ASR = AT91C_PC0_BFCK | AT91C_PC1_BFRDY_SMOE | - AT91C_PC3_BFBAA_SMWE; - *AT91C_PIOC_PDR = AT91C_PC0_BFCK | AT91C_PC1_BFRDY_SMOE | - AT91C_PC3_BFBAA_SMWE; - - /* Configure PC2 as input (signal READY of the SmartMedia) */ - *AT91C_PIOC_PER = AT91C_PC2_BFAVD; /* enable direct output enable */ - *AT91C_PIOC_ODR = AT91C_PC2_BFAVD; /* disable output */ - - /* Configure PB1 as input (signal Card Detect of the SmartMedia) */ - *AT91C_PIOB_PER = AT91C_PIO_PB1; /* enable direct output enable */ - *AT91C_PIOB_ODR = AT91C_PIO_PB1; /* disable output */ - - /* PIOB and PIOC clock enabling */ - *AT91C_PMC_PCER = 1 << AT91C_ID_PIOB; - *AT91C_PMC_PCER = 1 << AT91C_ID_PIOC; - - if (*AT91C_PIOB_PDSR & AT91C_PIO_PB1) - printf (" No SmartMedia card inserted\n"); -#ifdef DEBUG - printf (" SmartMedia card inserted\n"); - - printf ("Probing at 0x%.8x\n", AT91_SMARTMEDIA_BASE); -#endif - printf ("%4lu MB\n", nand_probe(AT91_SMARTMEDIA_BASE) >> 20); -} -#endif diff --git a/board/atmel/at91rm9200dk/config.mk b/board/atmel/at91rm9200dk/config.mk deleted file mode 100644 index 207769233e..0000000000 --- a/board/atmel/at91rm9200dk/config.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x21f00000 diff --git a/board/atmel/at91rm9200dk/flash.c b/board/atmel/at91rm9200dk/flash.c deleted file mode 100644 index be2274362c..0000000000 --- a/board/atmel/at91rm9200dk/flash.c +++ /dev/null @@ -1,504 +0,0 @@ -/* - * (C) Copyright 2002 - * Lineo, Inc. <www.lineo.com> - * Bernhard Kuhn <bkuhn@lineo.com> - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke <azu@sysgo.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -ulong myflush(void); - - -/* Flash Organization Structure */ -typedef struct OrgDef -{ - unsigned int sector_number; - unsigned int sector_size; -} OrgDef; - - -/* Flash Organizations */ -OrgDef OrgAT49BV16x4[] = -{ - { 8, 8*1024 }, /* 8 * 8 kBytes sectors */ - { 2, 32*1024 }, /* 2 * 32 kBytes sectors */ - { 30, 64*1024 }, /* 30 * 64 kBytes sectors */ -}; - -OrgDef OrgAT49BV16x4A[] = -{ - { 8, 8*1024 }, /* 8 * 8 kBytes sectors */ - { 31, 64*1024 }, /* 31 * 64 kBytes sectors */ -}; - -OrgDef OrgAT49BV6416[] = -{ - { 8, 8*1024 }, /* 8 * 8 kBytes sectors */ - { 127, 64*1024 }, /* 127 * 64 kBytes sectors */ -}; - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -/* AT49BV1614A Codes */ -#define FLASH_CODE1 0xAA -#define FLASH_CODE2 0x55 -#define ID_IN_CODE 0x90 -#define ID_OUT_CODE 0xF0 - - -#define CMD_READ_ARRAY 0x00F0 -#define CMD_UNLOCK1 0x00AA -#define CMD_UNLOCK2 0x0055 -#define CMD_ERASE_SETUP 0x0080 -#define CMD_ERASE_CONFIRM 0x0030 -#define CMD_PROGRAM 0x00A0 -#define CMD_UNLOCK_BYPASS 0x0020 -#define CMD_SECTOR_UNLOCK 0x0070 - -#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00005555<<1))) -#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00002AAA<<1))) - -#define BIT_ERASE_DONE 0x0080 -#define BIT_RDY_MASK 0x0080 -#define BIT_PROGRAM_ERROR 0x0020 -#define BIT_TIMEOUT 0x80000000 /* our flag */ - -#define READY 1 -#define ERR 2 -#define TMO 4 - -/*----------------------------------------------------------------------- - */ -void flash_identification (flash_info_t * info) -{ - volatile u16 manuf_code, device_code, add_device_code; - - MEM_FLASH_ADDR1 = FLASH_CODE1; - MEM_FLASH_ADDR2 = FLASH_CODE2; - MEM_FLASH_ADDR1 = ID_IN_CODE; - - manuf_code = *(volatile u16 *) CONFIG_SYS_FLASH_BASE; - device_code = *(volatile u16 *) (CONFIG_SYS_FLASH_BASE + 2); - add_device_code = *(volatile u16 *) (CONFIG_SYS_FLASH_BASE + (3 << 1)); - - MEM_FLASH_ADDR1 = FLASH_CODE1; - MEM_FLASH_ADDR2 = FLASH_CODE2; - MEM_FLASH_ADDR1 = ID_OUT_CODE; - - /* Vendor type */ - info->flash_id = ATM_MANUFACT & FLASH_VENDMASK; - printf ("Atmel: "); - - if ((device_code & FLASH_TYPEMASK) == (ATM_ID_BV1614 & FLASH_TYPEMASK)) { - - if ((add_device_code & FLASH_TYPEMASK) == - (ATM_ID_BV1614A & FLASH_TYPEMASK)) { - info->flash_id |= ATM_ID_BV1614A & FLASH_TYPEMASK; - printf ("AT49BV1614A (16Mbit)\n"); - } else { /* AT49BV1614 Flash */ - info->flash_id |= ATM_ID_BV1614 & FLASH_TYPEMASK; - printf ("AT49BV1614 (16Mbit)\n"); - } - - } else if ((device_code & FLASH_TYPEMASK) == (ATM_ID_BV6416 & FLASH_TYPEMASK)) { - info->flash_id |= ATM_ID_BV6416 & FLASH_TYPEMASK; - printf ("AT49BV6416 (64Mbit)\n"); - } -} - -ushort flash_number_sector(OrgDef *pOrgDef, unsigned int nb_blocks) -{ - int i, nb_sectors = 0; - - for (i=0; i<nb_blocks; i++){ - nb_sectors += pOrgDef[i].sector_number; - } - - return nb_sectors; -} - -void flash_unlock_sector(flash_info_t * info, unsigned int sector) -{ - volatile u16 *addr = (volatile u16 *) (info->start[sector]); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - *addr = CMD_SECTOR_UNLOCK; -} - - -ulong flash_init (void) -{ - int i, j, k; - unsigned int flash_nb_blocks, sector; - unsigned int start_address; - OrgDef *pOrgDef; - - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - - flash_identification (&flash_info[i]); - - if ((flash_info[i].flash_id & FLASH_TYPEMASK) == - (ATM_ID_BV1614 & FLASH_TYPEMASK)) { - - pOrgDef = OrgAT49BV16x4; - flash_nb_blocks = sizeof (OrgAT49BV16x4) / sizeof (OrgDef); - } else if ((flash_info[i].flash_id & FLASH_TYPEMASK) == - (ATM_ID_BV1614A & FLASH_TYPEMASK)){ /* AT49BV1614A Flash */ - - pOrgDef = OrgAT49BV16x4A; - flash_nb_blocks = sizeof (OrgAT49BV16x4A) / sizeof (OrgDef); - } else if ((flash_info[i].flash_id & FLASH_TYPEMASK) == - (ATM_ID_BV6416 & FLASH_TYPEMASK)){ /* AT49BV6416 Flash */ - - pOrgDef = OrgAT49BV6416; - flash_nb_blocks = sizeof (OrgAT49BV6416) / sizeof (OrgDef); - } else { - flash_nb_blocks = 0; - pOrgDef = OrgAT49BV16x4; - } - - flash_info[i].sector_count = flash_number_sector(pOrgDef, flash_nb_blocks); - memset (flash_info[i].protect, 0, flash_info[i].sector_count); - - if (i == 0) - flashbase = PHYS_FLASH_1; - else - panic ("configured too many flash banks!\n"); - - sector = 0; - start_address = flashbase; - flash_info[i].size = 0; - - for (j = 0; j < flash_nb_blocks; j++) { - for (k = 0; k < pOrgDef[j].sector_number; k++) { - flash_info[i].start[sector++] = start_address; - start_address += pOrgDef[j].sector_size; - flash_info[i].size += pOrgDef[j].sector_size; - } - } - - size += flash_info[i].size; - - if ((flash_info[i].flash_id & FLASH_TYPEMASK) == - (ATM_ID_BV6416 & FLASH_TYPEMASK)){ /* AT49BV6416 Flash */ - - /* Unlock all sectors at reset */ - for (j=0; j<flash_info[i].sector_count; j++){ - flash_unlock_sector(&flash_info[i], j); - } - } - } - - /* Protect binary boot image */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + CONFIG_SYS_BOOT_SIZE - 1, &flash_info[0]); - - /* Protect environment variables */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); - - /* Protect U-Boot gzipped image */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_U_BOOT_BASE, - CONFIG_SYS_U_BOOT_BASE + CONFIG_SYS_U_BOOT_SIZE - 1, &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case (ATM_MANUFACT & FLASH_VENDMASK): - printf ("Atmel: "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (ATM_ID_BV1614 & FLASH_TYPEMASK): - printf ("AT49BV1614 (16Mbit)\n"); - break; - case (ATM_ID_BV1614A & FLASH_TYPEMASK): - printf ("AT49BV1614A (16Mbit)\n"); - break; - case (ATM_ID_BV6416 & FLASH_TYPEMASK): - printf ("AT49BV6416 (64Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - return; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - ulong result; - int iflag, cflag, prot, sect; - int rc = ERR_OK; - int chip1; - ulong start; - - /* first look for protection bits */ - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (ATM_MANUFACT & FLASH_VENDMASK)) { - return ERR_UNKNOWN_FLASH_VENDOR; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) - return ERR_PROTECTED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - cflag = icache_status (); - icache_disable (); - iflag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - if (info->protect[sect] == 0) { /* not protected */ - volatile u16 *addr = (volatile u16 *) (info->start[sect]); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - *addr = CMD_ERASE_CONFIRM; - - /* wait until flash is ready */ - chip1 = 0; - - do { - result = *addr; - - /* check timeout */ - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - chip1 = TMO; - break; - } - - if (!chip1 && (result & 0xFFFF) & BIT_ERASE_DONE) - chip1 = READY; - - } while (!chip1); - - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - - if (chip1 == ERR) { - rc = ERR_PROG_ERROR; - goto outahere; - } - if (chip1 == TMO) { - rc = ERR_TIMOUT; - goto outahere; - } - - printf ("ok.\n"); - } else { /* it was protected */ - printf ("protected!\n"); - } - } - - if (ctrlc ()) - printf ("User Interrupt!\n"); - -outahere: - /* allow flash to settle - wait 10 ms */ - udelay_masked (10000); - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash - */ - -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - volatile u16 *addr = (volatile u16 *) dest; - ulong result; - int rc = ERR_OK; - int cflag, iflag; - int chip1; - ulong start; - - /* - * Check if Flash is (sufficiently) erased - */ - result = *addr; - if ((result & data) != data) - return ERR_NOT_ERASED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - cflag = icache_status (); - icache_disable (); - iflag = disable_interrupts (); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_PROGRAM; - *addr = data; - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait until flash is ready */ - chip1 = 0; - do { - result = *addr; - - /* check timeout */ - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { - chip1 = ERR | TMO; - break; - } - if (!chip1 && ((result & 0x80) == (data & 0x80))) - chip1 = READY; - - } while (!chip1); - - *addr = CMD_READ_ARRAY; - - if (chip1 == ERR || *addr != data) - rc = ERR_PROG_ERROR; - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash. - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong wp, data; - int rc; - - if (addr & 1) { - printf ("unaligned destination not supported\n"); - return ERR_ALIGN; - }; - - if ((int) src & 1) { - printf ("unaligned source not supported\n"); - return ERR_ALIGN; - }; - - wp = addr; - - while (cnt >= 2) { - data = *((volatile u16 *) src); - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - src += 2; - wp += 2; - cnt -= 2; - } - - if (cnt == 1) { - data = (*((volatile u8 *) src)) | (*((volatile u8 *) (wp + 1)) << - 8); - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - src += 1; - wp += 1; - cnt -= 1; - }; - - return ERR_OK; -} diff --git a/board/atmel/at91rm9200dk/led.c b/board/atmel/at91rm9200dk/led.c deleted file mode 100644 index 47a3bfce68..0000000000 --- a/board/atmel/at91rm9200dk/led.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * (C) Copyright 2006 - * Atmel Nordic AB <www.atmel.com> - * Ulf Samuelsson <ulf@atmel.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/arch/AT91RM9200.h> - -#define GREEN_LED AT91C_PIO_PB0 -#define YELLOW_LED AT91C_PIO_PB1 -#define RED_LED AT91C_PIO_PB2 - -void green_LED_on(void) -{ - AT91PS_PIO PIOB = AT91C_BASE_PIOB; - PIOB->PIO_CODR = GREEN_LED; -} - -void yellow_LED_on(void) -{ - AT91PS_PIO PIOB = AT91C_BASE_PIOB; - PIOB->PIO_CODR = YELLOW_LED; -} - -void red_LED_on(void) -{ - AT91PS_PIO PIOB = AT91C_BASE_PIOB; - PIOB->PIO_CODR = RED_LED; -} - -void green_LED_off(void) -{ - AT91PS_PIO PIOB = AT91C_BASE_PIOB; - PIOB->PIO_SODR = GREEN_LED; -} - -void yellow_LED_off(void) -{ - AT91PS_PIO PIOB = AT91C_BASE_PIOB; - PIOB->PIO_SODR = YELLOW_LED; -} - -void red_LED_off(void) -{ - AT91PS_PIO PIOB = AT91C_BASE_PIOB; - PIOB->PIO_SODR = RED_LED; -} - - -void coloured_LED_init (void) -{ - AT91PS_PIO PIOB = AT91C_BASE_PIOB; - AT91PS_PMC PMC = AT91C_BASE_PMC; - PMC->PMC_PCER = (1 << AT91C_ID_PIOB); /* Enable PIOB clock */ - /* Disable peripherals on LEDs */ - PIOB->PIO_PER = AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0; - /* Enable pins as outputs */ - PIOB->PIO_OER = AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0; - /* Turn all LEDs OFF */ - PIOB->PIO_SODR = AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0; -} diff --git a/board/atmel/at91rm9200dk/mux.c b/board/atmel/at91rm9200dk/mux.c deleted file mode 100644 index a00563ede8..0000000000 --- a/board/atmel/at91rm9200dk/mux.c +++ /dev/null @@ -1,29 +0,0 @@ -#include <config.h> -#include <common.h> -#include <asm/hardware.h> -#include <dataflash.h> - -int AT91F_GetMuxStatus(void) { - AT91C_BASE_PIOB->PIO_PER = CONFIG_SYS_DATAFLASH_MMC_PIO; /* Set in PIO mode */ - AT91C_BASE_PIOB->PIO_OER = CONFIG_SYS_DATAFLASH_MMC_PIO; /* Configure in output */ - - - if(AT91C_BASE_PIOB->PIO_ODSR & CONFIG_SYS_DATAFLASH_MMC_PIO) - return 1; - - return 0; -} - -void AT91F_SelectMMC(void) { - AT91C_BASE_PIOB->PIO_PER = CONFIG_SYS_DATAFLASH_MMC_PIO; /* Set in PIO mode */ - AT91C_BASE_PIOB->PIO_OER = CONFIG_SYS_DATAFLASH_MMC_PIO; /* Configure in output */ - /* Set Output */ - AT91C_BASE_PIOB->PIO_SODR = CONFIG_SYS_DATAFLASH_MMC_PIO; -} - -void AT91F_SelectSPI(void) { - AT91C_BASE_PIOB->PIO_PER = CONFIG_SYS_DATAFLASH_MMC_PIO; /* Set in PIO mode */ - AT91C_BASE_PIOB->PIO_OER = CONFIG_SYS_DATAFLASH_MMC_PIO; /* Configure in output */ - /* Clear Output */ - AT91C_BASE_PIOB->PIO_CODR = CONFIG_SYS_DATAFLASH_MMC_PIO; -} diff --git a/board/atmel/at91rm9200dk/partition.c b/board/atmel/at91rm9200dk/partition.c deleted file mode 100644 index c739b116bf..0000000000 --- a/board/atmel/at91rm9200dk/partition.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * (C) Copyright 2008 - * Ulf Samuelsson <ulf@atmel.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ -#include <common.h> -#include <config.h> -#include <asm/hardware.h> -#include <dataflash.h> - -AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS]; - -struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = { - {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ - {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3, 3} -}; - -/*define the area offsets*/ -dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { - {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"}, - {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"}, - {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"}, - {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"}, - {0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"}, -}; diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c index f92b20f4a8..24a86063bf 100644 --- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c +++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c @@ -23,17 +23,14 @@ */ #include <common.h> -#include <asm/sizes.h> -#include <asm/arch/at91sam9g45.h> -#include <asm/arch/at91sam9_matrix.h> +#include <asm/io.h> +#include <asm/arch/at91sam9g45_matrix.h> #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/at91_rstc.h> -#include <asm/arch/clk.h> #include <asm/arch/gpio.h> -#include <asm/arch/io.h> -#include <asm/arch/hardware.h> +#include <asm/arch/clk.h> #include <lcd.h> #include <atmel_lcdc.h> #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) @@ -49,35 +46,38 @@ DECLARE_GLOBAL_DATA_PTR; */ #ifdef CONFIG_CMD_NAND -static void at91sam9m10g45ek_nand_hw_init(void) +void at91sam9m10g45ek_nand_hw_init(void) { + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; unsigned long csa; /* Enable CS3 */ - csa = at91_sys_read(AT91_MATRIX_EBICSA); - at91_sys_write(AT91_MATRIX_EBICSA, - csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA); + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; + writel(csa, &matrix->ebicsa); /* Configure SMC CS3 for NAND/SmartMedia */ - at91_sys_write(AT91_SMC_SETUP(3), - AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC_PULSE(3), - AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(3) | - AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(2)); - at91_sys_write(AT91_SMC_CYCLE(3), - AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(4)); - at91_sys_write(AT91_SMC_MODE(3), - AT91_SMC_READMODE | AT91_SMC_WRITEMODE | - AT91_SMC_EXNWMODE_DISABLE | + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | #ifdef CONFIG_SYS_NAND_DBW_16 - AT91_SMC_DBW_16 | + AT91_SMC_MODE_DBW_16 | #else /* CONFIG_SYS_NAND_DBW_8 */ - AT91_SMC_DBW_8 | + AT91_SMC_MODE_DBW_8 | #endif - AT91_SMC_TDF_(3)); + AT91_SMC_MODE_TDF_CYCLE(3), + &smc->cs[3].mode); - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIOC); + writel(1 << ATMEL_ID_PIOC, &pmc->pcer); /* Configure RDY/BSY */ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); @@ -90,7 +90,9 @@ static void at91sam9m10g45ek_nand_hw_init(void) #ifdef CONFIG_CMD_USB static void at91sam9m10g45ek_usb_hw_init(void) { - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIODE); + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + writel(1 << ATMEL_ID_PIODE, &pmc->pcer); at91_set_gpio_output(AT91_PIN_PD1, 0); at91_set_gpio_output(AT91_PIN_PD3, 0); @@ -100,47 +102,50 @@ static void at91sam9m10g45ek_usb_hw_init(void) #ifdef CONFIG_MACB static void at91sam9m10g45ek_macb_hw_init(void) { - unsigned long rstc; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; + struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC; + unsigned long erstl; /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_EMAC); + writel(1 << ATMEL_ID_EMAC, &pmc->pcer); /* * Disable pull-up on: - * RXDV (PA15) => PHY normal mode (not Test mode) - * ERX0 (PA12) => PHY ADDR0 - * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0 + * RXDV (PA15) => PHY normal mode (not Test mode) + * ERX0 (PA12) => PHY ADDR0 + * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0 * * PHY has internal pull-down */ writel(pin_to_mask(AT91_PIN_PA15) | pin_to_mask(AT91_PIN_PA12) | pin_to_mask(AT91_PIN_PA13), - pin_to_controller(AT91_PIN_PA0) + PIO_PUDR); + &pioa->pudr); - rstc = at91_sys_read(AT91_RSTC_MR); + erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; /* Need to reset PHY -> 500ms reset */ - at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | - (AT91_RSTC_ERSTL & (0x0D << 8)) | - AT91_RSTC_URSTEN); + writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) | + AT91_RSTC_MR_URSTEN, &rstc->mr); - at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); + writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); /* Wait for end hardware reset */ - while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)); + while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) + ; /* Restore NRST value */ - at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | - (rstc) | - AT91_RSTC_URSTEN); + writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, + &rstc->mr); /* Re-enable pull-up */ writel(pin_to_mask(AT91_PIN_PA15) | pin_to_mask(AT91_PIN_PA12) | pin_to_mask(AT91_PIN_PA13), - pin_to_controller(AT91_PIN_PA0) + PIO_PUER); + &pioa->puer); + /* And the pins. */ at91_macb_hw_init(); } #endif @@ -161,7 +166,7 @@ vidinfo_t panel_info = { vl_vsync_len: 1, vl_upper_margin:40, vl_lower_margin:1, - mmio: AT91SAM9G45_LCDC_BASE, + mmio : ATMEL_BASE_LCDC, }; @@ -177,6 +182,8 @@ void lcd_disable(void) static void at91sam9m10g45ek_lcd_hw_init(void) { + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */ at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */ at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */ @@ -208,7 +215,7 @@ static void at91sam9m10g45ek_lcd_hw_init(void) at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */ at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_LCDC); + writel(1 << ATMEL_ID_LCDC, &pmc->pcer); gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE; } @@ -227,7 +234,7 @@ void lcd_show_board_info(void) lcd_printf ("(C) 2008 ATMEL Corp\n"); lcd_printf ("at91support@atmel.com\n"); lcd_printf ("%s CPU at %s MHz\n", - CONFIG_SYS_AT91_CPU_NAME, + ATMEL_CPU_NAME, strmhz(temp, get_cpu_clk_rate())); dram_size = 0; @@ -243,6 +250,12 @@ void lcd_show_board_info(void) #endif /* CONFIG_LCD_INFO */ #endif +int board_early_init_f(void) +{ + at91_seriald_hw_init(); + return 0; +} + int board_init(void) { /* Enable Ctrlc */ @@ -254,10 +267,10 @@ int board_init(void) #elif defined CONFIG_AT91SAM9G45EKES gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G45EKES; #endif + /* adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - at91_serial_hw_init(); #ifdef CONFIG_CMD_NAND at91sam9m10g45ek_nand_hw_init(); #endif @@ -270,11 +283,9 @@ int board_init(void) #ifdef CONFIG_ATMEL_SPI at91_spi0_hw_init(1 << 4); #endif - #ifdef CONFIG_MACB at91sam9m10g45ek_macb_hw_init(); #endif - #ifdef CONFIG_LCD at91sam9m10g45ek_lcd_hw_init(); #endif @@ -283,8 +294,8 @@ int board_init(void) int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); return 0; } @@ -298,7 +309,7 @@ int board_eth_init(bd_t *bis) { int rc = 0; #ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)AT91SAM9G45_BASE_EMAC, 0x00); + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); #endif return rc; } diff --git a/board/atmel/at91sam9m10g45ek/led.c b/board/atmel/at91sam9m10g45ek/led.c index ff59a2d5d3..dadbd6a761 100644 --- a/board/atmel/at91sam9m10g45ek/led.c +++ b/board/atmel/at91sam9m10g45ek/led.c @@ -23,15 +23,17 @@ */ #include <common.h> +#include <asm/io.h> #include <asm/arch/at91sam9g45.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/gpio.h> -#include <asm/arch/io.h> void coloured_LED_init(void) { + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIODE); + writel(1 << ATMEL_ID_PIODE, &pmc->pcer); at91_set_gpio_output(CONFIG_RED_LED, 1); at91_set_gpio_output(CONFIG_GREEN_LED, 1); diff --git a/board/calao/sbc35_a9g20/sbc35_a9g20.c b/board/calao/sbc35_a9g20/sbc35_a9g20.c index 9df45c0ea3..5f448d9f50 100644 --- a/board/calao/sbc35_a9g20/sbc35_a9g20.c +++ b/board/calao/sbc35_a9g20/sbc35_a9g20.c @@ -26,15 +26,14 @@ */ #include <common.h> -#include <asm/arch/at91sam9260.h> +#include <asm/io.h> #include <asm/arch/at91sam9260_matrix.h> #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/at91_rstc.h> #include <asm/arch/gpio.h> -#include <asm/arch/io.h> -#include <asm/arch/hardware.h> + #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) #include <net.h> #endif @@ -50,33 +49,36 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_CMD_NAND static void sbc35_a9g20_nand_hw_init(void) { + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; unsigned long csa; /* Enable CS3 */ - csa = at91_sys_read(AT91_MATRIX_EBICSA); - at91_sys_write(AT91_MATRIX_EBICSA, - csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA; + writel(csa, &matrix->ebicsa); /* Configure SMC CS3 for NAND/SmartMedia */ - at91_sys_write(AT91_SMC_SETUP(3), - AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC_PULSE(3), - AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | - AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); - at91_sys_write(AT91_SMC_CYCLE(3), - AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); - at91_sys_write(AT91_SMC_MODE(3), - AT91_SMC_READMODE | AT91_SMC_WRITEMODE | - AT91_SMC_EXNWMODE_DISABLE | + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | #ifdef CONFIG_SYS_NAND_DBW_16 - AT91_SMC_DBW_16 | + AT91_SMC_MODE_DBW_16 | #else /* CONFIG_SYS_NAND_DBW_8 */ - AT91_SMC_DBW_8 | + AT91_SMC_MODE_DBW_8 | #endif - AT91_SMC_TDF_(2)); + AT91_SMC_MODE_TDF_CYCLE(2), + &smc->cs[3].mode); - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC); + writel(1 << ATMEL_ID_PIOC, &pmc->pcer); /* Configure RDY/BSY */ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); @@ -89,10 +91,13 @@ static void sbc35_a9g20_nand_hw_init(void) #ifdef CONFIG_MACB static void sbc35_a9g20_macb_hw_init(void) { - unsigned long rstc; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; + struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC; + unsigned long erstl; - /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC); + /* Enable EMAC clock */ + writel(1 << ATMEL_ID_EMAC0, &pmc->pcer); /* * Disable pull-up on: @@ -111,24 +116,23 @@ static void sbc35_a9g20_macb_hw_init(void) pin_to_mask(AT91_PIN_PA25) | pin_to_mask(AT91_PIN_PA26) | pin_to_mask(AT91_PIN_PA28), - pin_to_controller(AT91_PIN_PA0) + PIO_PUDR); + &pioa->pudr); - rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL; + erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; /* Need to reset PHY -> 500ms reset */ - at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | - (AT91_RSTC_ERSTL & (0x0D << 8)) | - AT91_RSTC_URSTEN); + writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) | + AT91_RSTC_MR_URSTEN, &rstc->mr); - at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); + writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); /* Wait for end hardware reset */ - while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)); + while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) + ; /* Restore NRST value */ - at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | - (rstc) | - AT91_RSTC_URSTEN); + writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, + &rstc->mr); /* Re-enable pull-up */ writel(pin_to_mask(AT91_PIN_PA14) | @@ -137,7 +141,7 @@ static void sbc35_a9g20_macb_hw_init(void) pin_to_mask(AT91_PIN_PA25) | pin_to_mask(AT91_PIN_PA26) | pin_to_mask(AT91_PIN_PA28), - pin_to_controller(AT91_PIN_PA0) + PIO_PUER); + &pioa->puer); at91_macb_hw_init(); } @@ -150,9 +154,9 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_SBC35_A9G20; /* adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - at91_serial_hw_init(); + at91_seriald_hw_init(); sbc35_a9g20_nand_hw_init(); #ifdef CONFIG_ATMEL_SPI at91_spi0_hw_init(1 << 4 | 1 << 5); @@ -166,11 +170,9 @@ int board_init(void) int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM; - if(get_ram_size((long *) PHYS_SDRAM, PHYS_SDRAM_SIZE) != PHYS_SDRAM_SIZE) - return -1; - - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + gd->ram_size = get_ram_size( + (void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); return 0; } @@ -184,7 +186,7 @@ int board_eth_init(bd_t *bis) { int rc = 0; #ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x00); + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00); #endif return rc; } diff --git a/board/calao/tny_a9260/tny_a9260.c b/board/calao/tny_a9260/tny_a9260.c index d51ca150cc..ab51a335a0 100644 --- a/board/calao/tny_a9260/tny_a9260.c +++ b/board/calao/tny_a9260/tny_a9260.c @@ -26,14 +26,12 @@ */ #include <common.h> -#include <asm/arch/at91sam9260.h> #include <asm/arch/at91sam9_matrix.h> #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/at91_rstc.h> #include <asm/arch/gpio.h> -#include <asm/arch/io.h> #include <asm/arch/hardware.h> DECLARE_GLOBAL_DATA_PTR; @@ -45,33 +43,36 @@ DECLARE_GLOBAL_DATA_PTR; static void tny_a9260_nand_hw_init(void) { + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; unsigned long csa; - /* Enable CS3 */ - csa = at91_sys_read(AT91_MATRIX_EBICSA); - at91_sys_write(AT91_MATRIX_EBICSA, - csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); + /* Assign CS3 to NAND/SmartMedia Interface */ + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA; + writel(csa, &matrix->ebicsa); /* Configure SMC CS3 for NAND/SmartMedia */ - at91_sys_write(AT91_SMC_SETUP(3), - AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC_PULSE(3), - AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | - AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); - at91_sys_write(AT91_SMC_CYCLE(3), - AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); - at91_sys_write(AT91_SMC_MODE(3), - AT91_SMC_READMODE | AT91_SMC_WRITEMODE | - AT91_SMC_EXNWMODE_DISABLE | + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | #ifdef CONFIG_SYS_NAND_DBW_16 - AT91_SMC_DBW_16 | + AT91_SMC_MODE_DBW_16 | #else /* CONFIG_SYS_NAND_DBW_8 */ - AT91_SMC_DBW_8 | + AT91_SMC_MODE_DBW_8 | #endif - AT91_SMC_TDF_(2)); + AT91_SMC_MODE_TDF_CYCLE(2), + &smc->cs[3].mode); - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC); + writel(1 << ATMEL_ID_PIOC, &pmc->pcer); /* Configure RDY/BSY */ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); @@ -91,9 +92,9 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_TNY_A9G20; #endif /* adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - at91_serial_hw_init(); + at91_seriald_hw_init(); tny_a9260_nand_hw_init(); at91_spi0_hw_init(1 << 5); return 0; @@ -101,10 +102,8 @@ int board_init(void) int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM; - if(get_ram_size((long *) PHYS_SDRAM, PHYS_SDRAM_SIZE) != PHYS_SDRAM_SIZE) - return -1; - - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + gd->ram_size = get_ram_size( + (void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); return 0; } diff --git a/board/cm_t35/cm_t35.c b/board/cm_t35/cm_t35.c index f82111bac2..420cd70dee 100644 --- a/board/cm_t35/cm_t35.c +++ b/board/cm_t35/cm_t35.c @@ -313,6 +313,14 @@ void set_muxconf_regs(void) cm_t3730_set_muxconf(); } +#ifdef CONFIG_GENERIC_MMC +int board_mmc_init(bd_t *bis) +{ + omap_mmc_init(0); + return 0; +} +#endif + /* * Routine: setup_net_chip_gmpc * Description: Setting up the configuration GPMC registers specific to the diff --git a/board/cmc_pu2/Makefile b/board/cmc_pu2/Makefile deleted file mode 100644 index a60f2e9612..0000000000 --- a/board/cmc_pu2/Makefile +++ /dev/null @@ -1,50 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := cmc_pu2.o flash.o load_sernum_ethaddr.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/cmc_pu2/cmc_pu2.c b/board/cmc_pu2/cmc_pu2.c deleted file mode 100644 index 0ac851c97f..0000000000 --- a/board/cmc_pu2/cmc_pu2.c +++ /dev/null @@ -1,192 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * Modified for CMC_PU2 (removed Smart Media support) by Gary Jennejohn - * (2004) garyj@denx.de - * - * Modified for CMC_BASIC by Martin Krause (2005), TQ-Systems GmbH - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/mach-types.h> -#include <asm/arch/AT91RM9200.h> -#include <asm/io.h> -#include <netdev.h> -#if defined(CONFIG_DRIVER_ETHER) -#include <at91rm9200_net.h> -#include <dm9161.h> -#endif - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ -/* - * Miscelaneous platform dependent initialisations - */ -#define CMC_HP_BASIC 1 -#define CMC_PU2 2 -#define CMC_BASIC 4 - -int hw_detect (void); - -int board_init (void) -{ - AT91PS_PIO piob = AT91C_BASE_PIOB; - AT91PS_PIO pioc = AT91C_BASE_PIOC; - - /* Enable Ctrlc */ - console_init_f (); - - /* Correct IRDA resistor problem */ - /* Set PA23_TXD in Output */ - /* (AT91PS_PIO) AT91C_BASE_PIOA->PIO_OER = AT91C_PA23_TXD2; */ - - /* memory and cpu-speed are setup before relocation */ - /* so we do _nothing_ here */ - - /* PIOB and PIOC clock enabling */ - *AT91C_PMC_PCER = 1 << AT91C_ID_PIOB; - *AT91C_PMC_PCER = 1 << AT91C_ID_PIOC; - - /* - * configure PC0-PC3 as input without pull ups, so RS485 driver enable - * (CMC-PU2) and digital outputs (CMC-BASIC) are deactivated. - */ - pioc->PIO_ODR = AT91C_PIO_PC0 | AT91C_PIO_PC1 | - AT91C_PIO_PC2 | AT91C_PIO_PC3; - pioc->PIO_PPUDR = AT91C_PIO_PC0 | AT91C_PIO_PC1 | - AT91C_PIO_PC2 | AT91C_PIO_PC3; - pioc->PIO_PER = AT91C_PIO_PC0 | AT91C_PIO_PC1 | - AT91C_PIO_PC2 | AT91C_PIO_PC3; - - /* - * On CMC-PU2 board configure PB3-PB6 to input without pull ups to - * clear the duo LEDs (the external pull downs assure a proper - * signal). On CMC-BASIC and CMC-HP-BASIC set PB3-PB6 to output and - * drive it high, to configure current measurement on AINx. - */ - if (hw_detect() & CMC_PU2) { - piob->PIO_ODR = AT91C_PIO_PB3 | AT91C_PIO_PB4 | - AT91C_PIO_PB5 | AT91C_PIO_PB6; - } - else if ((hw_detect() & CMC_BASIC) || (hw_detect() & CMC_HP_BASIC)) { - piob->PIO_SODR = AT91C_PIO_PB3 | AT91C_PIO_PB4 | - AT91C_PIO_PB5 | AT91C_PIO_PB6; - piob->PIO_OER = AT91C_PIO_PB3 | AT91C_PIO_PB4 | - AT91C_PIO_PB5 | AT91C_PIO_PB6; - } - piob->PIO_PPUDR = AT91C_PIO_PB3 | AT91C_PIO_PB4 | - AT91C_PIO_PB5 | AT91C_PIO_PB6; - piob->PIO_PER = AT91C_PIO_PB3 | AT91C_PIO_PB4 | - AT91C_PIO_PB5 | AT91C_PIO_PB6; - - /* - * arch number of CMC_PU2-Board. MACH_TYPE_CMC_PU2 is not supported in - * the linuxarm kernel, yet. - */ - /* gd->bd->bi_arch_number = MACH_TYPE_CMC_PU2; */ - gd->bd->bi_arch_number = 251; - /* adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - return 0; -} - -int dram_init (void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; - return 0; -} - -int checkboard (void) -{ - if (hw_detect() & CMC_PU2) - puts ("Board: CMC-PU2 (Rittal GmbH)\n"); - else if (hw_detect() & CMC_BASIC) - puts ("Board: CMC-BASIC (Rittal GmbH)\n"); - else if (hw_detect() & CMC_HP_BASIC) - puts ("Board: CMC-HP-BASIC (Rittal GmbH)\n"); - else - puts ("Board: unknown\n"); - return 0; -} - -int hw_detect (void) -{ - AT91PS_PIO pio = AT91C_BASE_PIOB; - - /* PIOB clock enabling */ - *AT91C_PMC_PCER = 1 << AT91C_ID_PIOB; - - /* configure PB12 as input without pull up */ - pio->PIO_ODR = AT91C_PIO_PB12; - pio->PIO_PPUDR = AT91C_PIO_PB12; - pio->PIO_PER = AT91C_PIO_PB12; - - /* configure PB13 as input without pull up */ - pio->PIO_ODR = AT91C_PIO_PB13; - pio->PIO_PPUDR = AT91C_PIO_PB13; - pio->PIO_PER = AT91C_PIO_PB13; - - /* read board identification pin */ - if (pio->PIO_PDSR & AT91C_PIO_PB12) - return ((pio->PIO_PDSR & AT91C_PIO_PB13) - ? CMC_PU2 : 0); - else - return ((pio->PIO_PDSR & AT91C_PIO_PB13) - ? CMC_HP_BASIC : CMC_BASIC); -} - -#ifdef CONFIG_DRIVER_ETHER -#if defined(CONFIG_CMD_NET) - -/* - * Name: - * at91rm9200_GetPhyInterface - * Description: - * Initialise the interface functions to the PHY - * Arguments: - * None - * Return value: - * None - */ -void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops) -{ - p_phyops->Init = dm9161_InitPhy; - p_phyops->IsPhyConnected = dm9161_IsPhyConnected; - p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed; - p_phyops->AutoNegotiate = dm9161_AutoNegotiate; -} - -#endif -#endif /* CONFIG_DRIVER_ETHER */ - -#ifdef CONFIG_DRIVER_AT91EMAC -int board_eth_init(bd_t *bis) -{ - int rc = 0; - rc = at91emac_register(bis, 0); - return rc; -} -#endif diff --git a/board/cmc_pu2/config.mk b/board/cmc_pu2/config.mk deleted file mode 100644 index cdb8a5f571..0000000000 --- a/board/cmc_pu2/config.mk +++ /dev/null @@ -1,3 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x20F00000 -## For testing: load at 0x20100000 and "go" at 0x201000A4 -#CONFIG_SYS_TEXT_BASE = 0x20100000 diff --git a/board/cmc_pu2/flash.c b/board/cmc_pu2/flash.c deleted file mode 100644 index d10faab52a..0000000000 --- a/board/cmc_pu2/flash.c +++ /dev/null @@ -1,469 +0,0 @@ -/* - * (C) Copyright 2003-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * Modified for the CMC PU2 by (C) Copyright 2004 Gary Jennejohn - * garyj@denx.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -#ifndef CONFIG_ENV_ADDR -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#endif - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#define FLASH_CYCLE1 0x0555 -#define FLASH_CYCLE2 0x02AA - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(vu_short *addr, flash_info_t *info); -static void flash_reset(flash_info_t *info); -static int write_word_amd(flash_info_t *info, vu_short *dest, ushort data); -static flash_info_t *flash_get_info(ulong base); - -/*----------------------------------------------------------------------- - * flash_init() - * - * sets up flash_info and returns size of FLASH (bytes) - */ -unsigned long flash_init (void) -{ - unsigned long size = 0; - ulong flashbase = CONFIG_SYS_FLASH_BASE; - - /* Init: no FLASHes known */ - memset(&flash_info[0], 0, sizeof(flash_info_t)); - - flash_info[0].size = flash_get_size((vu_short *)flashbase, &flash_info[0]); - - size = flash_info[0].size; - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - flash_get_info(CONFIG_SYS_MONITOR_BASE)); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR+CONFIG_ENV_SIZE-1, - flash_get_info(CONFIG_ENV_ADDR)); -#endif - - return size ? size : 1; -} - -/*----------------------------------------------------------------------- - */ -static void flash_reset(flash_info_t *info) -{ - vu_short *base = (vu_short *)(info->start[0]); - - /* Put FLASH back in read mode */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) - *base = 0x00FF; /* Intel Read Mode */ - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) - *base = 0x00F0; /* AMD Read Mode */ -} - -/*----------------------------------------------------------------------- - */ - -static flash_info_t *flash_get_info(ulong base) -{ - int i; - flash_info_t * info; - - info = NULL; - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) { - info = & flash_info[i]; - if (info->size && info->start[0] <= base && - base <= info->start[0] + info->size - 1) - break; - } - - return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info; -} - -/*----------------------------------------------------------------------- - */ - -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_INTEL: printf ("INTEL "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_S29GL064M: - printf ("S29GL064M-R6 (64Mbit, uniform sector size)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, - info->sector_count); - - printf (" Sector Start Addresses:"); - - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -ulong flash_get_size (vu_short *addr, flash_info_t *info) -{ - int i; - ushort value; - ulong base = (ulong)addr; - - /* Write auto select command sequence */ - addr[FLASH_CYCLE1] = 0x00AA; /* for AMD, Intel ignores this */ - addr[FLASH_CYCLE2] = 0x0055; /* for AMD, Intel ignores this */ - addr[FLASH_CYCLE1] = 0x0090; /* selects Intel or AMD */ - - /* read Manufacturer ID */ - udelay(100); - value = addr[0]; - debug ("Manufacturer ID: %04X\n", value); - - switch (value) { - - case (AMD_MANUFACT & 0xFFFF): - debug ("Manufacturer: AMD (Spansion)\n"); - info->flash_id = FLASH_MAN_AMD; - break; - - case (INTEL_MANUFACT & 0xFFFF): - debug ("Manufacturer: Intel (not supported yet)\n"); - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - printf ("Unknown Manufacturer ID: %04X\n", value); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - goto out; - } - - value = addr[1]; - debug ("Device ID: %04X\n", value); - - switch (addr[1]) { - - case (AMD_ID_MIRROR & 0xFFFF): - debug ("Mirror Bit flash: addr[14] = %08X addr[15] = %08X\n", - addr[14], addr[15]); - - switch(addr[14]) { - case (AMD_ID_GL064M_2 & 0xFFFF): - if (addr[15] != (AMD_ID_GL064M_3 & 0xffff)) { - printf ("Chip: S29GLxxxM -> unknown\n"); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - } else { - debug ("Chip: S29GL064M-R6\n"); - info->flash_id += FLASH_S29GL064M; - info->sector_count = 128; - info->size = 0x00800000; - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base; - base += 0x10000; - } - } - break; /* => 16 MB */ - default: - printf ("Chip: *** unknown ***\n"); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - break; - - default: - printf ("Unknown Device ID: %04X\n", value); - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - -out: - /* Put FLASH back in read mode */ - flash_reset(info); - - return (info->size); -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_short *addr = (vu_short *)(info->start[0]); - int flag, prot, sect, ssect, l_sect; - ulong now, last, start; - - debug ("flash_erase: first: %d last: %d\n", s_first, s_last); - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - /* - * Start erase on unprotected sectors. - * Since the flash can erase multiple sectors with one command - * we take advantage of that by doing the erase in chunks of - * 3 sectors. - */ - for (sect = s_first; sect <= s_last; ) { - l_sect = -1; - - addr[FLASH_CYCLE1] = 0x00AA; - addr[FLASH_CYCLE2] = 0x0055; - addr[FLASH_CYCLE1] = 0x0080; - addr[FLASH_CYCLE1] = 0x00AA; - addr[FLASH_CYCLE2] = 0x0055; - - /* do the erase in chunks of at most 3 sectors */ - for (ssect = 0; ssect < 3; ssect++) { - if ((sect + ssect) > s_last) - break; - if (info->protect[sect + ssect] == 0) { /* not protected */ - addr = (vu_short *)(info->start[sect + ssect]); - addr[0] = 0x0030; - l_sect = sect + ssect; - } - } - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer(0); - last = 0; - addr = (vu_short *)(info->start[l_sect]); - while ((addr[0] & 0x0080) != 0x0080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - addr = (vu_short *)info->start[0]; - addr[0] = 0x00F0; /* reset bank */ - sect += ssect; - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - -DONE: - /* reset to read mode */ - addr = (vu_short *)info->start[0]; - addr[0] = 0x00F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong wp, data; - int rc; - - if (addr & 1) { - printf ("unaligned destination not supported\n"); - return ERR_ALIGN; - }; - - if ((int) src & 1) { - printf ("unaligned source not supported\n"); - return ERR_ALIGN; - }; - - wp = addr; - - while (cnt >= 2) { - data = *((vu_short *)src); - if ((rc = write_word_amd(info, (vu_short *)wp, data)) != 0) { -printf ("write_buff 1: write_word_amd() rc=%d\n", rc); - return (rc); - } - src += 2; - wp += 2; - cnt -= 2; - } - - if (cnt == 0) { - return (ERR_OK); - } - - if (cnt == 1) { - data = (*((volatile u8 *) src)) | (*((volatile u8 *) (wp + 1)) << 8); - if ((rc = write_word_amd(info, (vu_short *)wp, data)) != 0) { -printf ("write_buff 1: write_word_amd() rc=%d\n", rc); - return (rc); - } - src += 1; - wp += 1; - cnt -= 1; - } - - return ERR_OK; -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for AMD FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_amd (flash_info_t *info, vu_short *dest, ushort data) -{ - int flag; - vu_short *base; /* first address in flash bank */ - ulong start; - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - base = (vu_short *)(info->start[0]); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - base[FLASH_CYCLE1] = 0x00AA; /* unlock */ - base[FLASH_CYCLE2] = 0x0055; /* unlock */ - base[FLASH_CYCLE1] = 0x00A0; /* selects program mode */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer(0); - - /* data polling for D7 */ - while ((*dest & 0x0080) != (data & 0x0080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *dest = 0x00F0; /* reset bank */ - return (1); - } - } - return (0); -} diff --git a/board/cmc_pu2/load_sernum_ethaddr.c b/board/cmc_pu2/load_sernum_ethaddr.c deleted file mode 100644 index 6f85dd95b3..0000000000 --- a/board/cmc_pu2/load_sernum_ethaddr.c +++ /dev/null @@ -1,113 +0,0 @@ -/* - * (C) Copyright 2000, 2001, 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2005 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* #define DEBUG */ - -#include <common.h> -#include <net.h> - -#define I2C_CHIP 0x50 /* I2C bus address of onboard EEPROM */ -#define I2C_ALEN 1 /* length of EEPROM addresses in bytes */ -#define I2C_OFFSET 0x0 /* start address of manufacturere data block - * in EEPROM */ - -/* 64 Byte manufacturer data block in EEPROM */ -struct manufacturer_data { - unsigned int serial_number; /* serial number (0...999999) */ - unsigned short hardware; /* hardware version (e.g. V1.02) */ - unsigned short manuf_date; /* manufacture date (e.g. 25/02) */ - unsigned char name[20]; /* device name (in CHIP.INI) */ - unsigned char macadr[6]; /* MAC address */ - signed char a_kal[4]; /* calibration value for U */ - signed char i_kal[4]; /* calibration value for I */ - unsigned char reserve[18]; /* reserved */ - unsigned short save_nr; /* save count */ - unsigned short chksum; /* checksum */ -}; - - -int i2c_read (unsigned char chip, unsigned int addr, int alen, - unsigned char *buffer, int len); - -/*----------------------------------------------------------------------- - * Process manufacturer data block in EEPROM: - * - * If we boot on a system fresh from factory, check if the manufacturer data - * in the EEPROM is valid and save some information it contains. - * - * CMC manufacturer data is defined as follows: - * - * - located in the onboard EEPROM - * - starts at offset 0x0 - * - size 0x00000040 - * - * Internal structure: see struct definition - */ - -int misc_init_r(void) -{ - struct manufacturer_data data; - char serial [9]; - unsigned short chksum; - unsigned char *p; - unsigned short i; - -#if !defined(CONFIG_HARD_I2C) && !defined(CONFIG_SOFT_I2C) -#error you must define some I2C support (CONFIG_HARD_I2C or CONFIG_SOFT_I2C) -#endif - if (i2c_read(I2C_CHIP, I2C_OFFSET, I2C_ALEN, (unsigned char *)&data, - sizeof(data)) != 0) { - puts ("Error reading manufacturer data from EEPROM\n"); - return -1; - } - - /* check if manufacturer data block is valid */ - p = (unsigned char *)&data; - chksum = 0; - for (i = 0; i < (sizeof(data) - sizeof(data.chksum)); i++) - chksum += *p++; - - debug ("checksum of manufacturer data block: %#.4x\n", chksum); - - if (chksum != data.chksum) { - puts ("Error: manufacturer data block has invalid checksum\n"); - return -1; - } - - /* copy serial number */ - sprintf (serial, "%d", data.serial_number); - - /* set serial# and ethaddr if not yet defined */ - if (getenv("serial#") == NULL) { - setenv ("serial#", serial); - } - - if (getenv("ethaddr") == NULL) { - eth_setenv_enetaddr("ethaddr", data.macadr); - } - - return 0; -} diff --git a/board/comelit/dig297/dig297.c b/board/comelit/dig297/dig297.c index 0062f120d7..a7071cd554 100644 --- a/board/comelit/dig297/dig297.c +++ b/board/comelit/dig297/dig297.c @@ -37,6 +37,7 @@ #include <netdev.h> #include <twl4030.h> #include <asm/io.h> +#include <asm/arch/mmc_host_def.h> #include <asm/arch/omap3-regs.h> #include <asm/arch/mux.h> #include <asm/arch/mem.h> @@ -145,6 +146,14 @@ void set_muxconf_regs(void) MUX_DIG297(); } +#ifdef CONFIG_GENERIC_MMC +int board_mmc_init(bd_t *bis) +{ + omap_mmc_init(0); + return 0; +} +#endif + #ifdef CONFIG_CMD_NET /* * Routine: setup_net_chip diff --git a/board/csb637/Makefile b/board/csb637/Makefile deleted file mode 100644 index a5484ae35d..0000000000 --- a/board/csb637/Makefile +++ /dev/null @@ -1,50 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := csb637.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/csb637/config.mk b/board/csb637/config.mk deleted file mode 100644 index e2cc8a6eea..0000000000 --- a/board/csb637/config.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x23fc0000 diff --git a/board/csb637/csb637.c b/board/csb637/csb637.c deleted file mode 100644 index d7fdcc4f73..0000000000 --- a/board/csb637/csb637.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * (C) Copyright 2005 REA Elektronik GmbH <www.rea.de> - * Anders Larsen <alarsen@rea.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/arch/AT91RM9200.h> -#include <netdev.h> -#include <asm/io.h> -#if defined(CONFIG_DRIVER_ETHER) -#include <at91rm9200_net.h> -#include <bcm5221.h> -#endif - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ -/* - * Miscelaneous platform dependent initialisations - */ - -int board_init (void) -{ - /* Enable Ctrlc */ - console_init_f (); - - /* memory and cpu-speed are setup before relocation */ - /* so we do _nothing_ here */ - - /* arch number of CSB637-Board */ - gd->bd->bi_arch_number = MACH_TYPE_CSB637; - /* adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - return 0; -} - -int dram_init (void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; - return 0; -} - -#ifdef CONFIG_DRIVER_ETHER -#if defined(CONFIG_CMD_NET) - -/* - * Name: - * at91rm9200_GetPhyInterface - * Description: - * Initialise the interface functions to the PHY - * Arguments: - * None - * Return value: - * None - */ -void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops) -{ - p_phyops->Init = bcm5221_InitPhy; - p_phyops->IsPhyConnected = bcm5221_IsPhyConnected; - p_phyops->GetLinkSpeed = bcm5221_GetLinkSpeed; - p_phyops->AutoNegotiate = bcm5221_AutoNegotiate; -} - -#endif -#endif /* CONFIG_DRIVER_ETHER */ - -#ifdef CONFIG_DRIVER_AT91EMAC -int board_eth_init(bd_t *bis) -{ - int rc = 0; - rc = at91emac_register(bis, 0); - return rc; -} -#endif diff --git a/board/dave/B2/B2.c b/board/dave/B2/B2.c deleted file mode 100644 index 096ebbd16c..0000000000 --- a/board/dave/B2/B2.c +++ /dev/null @@ -1,139 +0,0 @@ -/* - * (C) Copyright 2004 - * DAVE Srl - * http://www.dave-tech.it - * http://www.wawnet.biz - * mailto:info@wawnet.biz - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <netdev.h> -#include <asm/hardware.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Miscelaneous platform dependent initialization - */ - -int board_init (void) -{ - u32 temp; - - /* Configuration Port Control Register*/ - /* Port A */ - PCONA = 0x3ff; - - /* Port B */ - PCONB = 0xff; - PDATB = 0xFFFF; - - /* Port C */ - /* - PCONC = 0xff55ff15; - PDATC = 0x0; - PUPC = 0xffff; - */ - - /* Port D */ - /* - PCOND = 0xaaaa; - PUPD = 0xff; - */ - - /* Port E */ - PCONE = 0x0001aaa9; - PDATE = 0x0; - PUPE = 0xff; - - /* Port F */ - PCONF = 0x124955; - PDATF = 0xff; /* B2-eth_reset tied high level */ - /* - PUPF = 0x1e3; - */ - - /* Port G */ - PUPG = 0x1; - PCONG = 0x3; /*PG0= EINT0= ETH_INT prepared for linux kernel*/ - - INTMSK = 0x03fffeff; - INTCON = 0x05; - - /* - Configure chip ethernet interrupt as High level - Port G EINT 0-7 EINT0 -> CHIP ETHERNET - */ - temp = EXTINT; - temp &= ~0x7; - temp |= 0x1; /*LEVEL_HIGH*/ - EXTINT = temp; - - /* - Reset SMSC LAN91C96 chip - */ - temp= PCONF; - temp |= 0x00000040; - PCONF = temp; - - /* Reset high */ - temp = PDATF; - temp |= (1 << 3); - PDATF = temp; - - /* Short delay */ - for (temp=0;temp<10;temp++) - { - /* NOP */ - } - - /* Reset low */ - temp = PDATF; - temp &= ~(1 << 3); - PDATF = temp; - - /* arch number MACH_TYPE_MBA44B0 */ - gd->bd->bi_arch_number = MACH_TYPE_S3C44B0; - - /* location of boot parameters */ - gd->bd->bi_boot_params = 0x0c000100; - - return 0; -} - -int dram_init (void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return (0); -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_LAN91C96 - rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE); -#endif - return rc; -} -#endif diff --git a/board/dave/B2/Makefile b/board/dave/B2/Makefile deleted file mode 100644 index b981579a8e..0000000000 --- a/board/dave/B2/Makefile +++ /dev/null @@ -1,55 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2002 -# Sysgo Real-Time Solutions, GmbH <www.elinos.com> -# Marius Groeger <mgroeger@sysgo.de> -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := B2.o flash.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/dave/B2/config.mk b/board/dave/B2/config.mk deleted file mode 100644 index f7b686a1eb..0000000000 --- a/board/dave/B2/config.mk +++ /dev/null @@ -1,30 +0,0 @@ -# -# (C) Copyright 2000 -# Sysgo Real-Time Solutions, GmbH <www.elinos.com> -# Marius Groeger <mgroeger@sysgo.de> -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -CONFIG_SYS_TEXT_BASE = 0x0C100000 - -PLATFORM_CPPFLAGS += -Uarm diff --git a/board/dave/B2/flash.c b/board/dave/B2/flash.c deleted file mode 100644 index bb892e6700..0000000000 --- a/board/dave/B2/flash.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * (C) Copyright 2001 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/hardware.h> - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); -static void flash_get_offsets (ulong base, flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ -#ifdef __DEBUG_START_FROM_SRAM__ - return CONFIG_SYS_DUMMY_FLASH_SIZE; -#else - unsigned long size_b0; - int i; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ - - size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0<<20); - } - - /* Setup offsets */ - flash_get_offsets (0, &flash_info[0]); - - /* Monitor protection ON by default */ - (void)flash_protect(FLAG_PROTECT_SET, - -CONFIG_SYS_MONITOR_LEN, - 0xffffffff, - &flash_info[0]); - - flash_info[0].size = size_b0; - - return (size_b0); -#endif -} diff --git a/board/dave/B2/lowlevel_init.S b/board/dave/B2/lowlevel_init.S deleted file mode 100644 index 2f3a3645ed..0000000000 --- a/board/dave/B2/lowlevel_init.S +++ /dev/null @@ -1,167 +0,0 @@ -/* - * (C) Copyright 2004 - * DAVE Srl - * - * http://www.dave-tech.it - * http://www.wawnet.biz - * mailto:info@wawnet.biz - * - * memsetup-sa1110.S (blob): memory setup for various SA1110 architectures - * Modified By MATTO - * - * Copyright (C) 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -/* - * Documentation: - * Intel Corporation, "Intel StrongARM SA-1110 Microprocessor - * Advanced Developer's manual, December 1999 - * - * Intel has a very hard to find SDRAM configurator on their web site: - * http://appzone.intel.com/hcd/sa1110/memory/index.asp - * - * NOTE: This code assumes that an SA1110 CPU *always* uses SDRAM. This - * appears to be true, but it might be possible that somebody designs a - * board with mixed EDODRAM/SDRAM memory (which is a bad idea). -- Erik - * - * 04-10-2001: SELETZ - * - separated memory config for multiple platform support - * - perform SA1110 Hardware Reset Procedure - * - */ - -.equ B0_Tacs, 0x0 /* 0clk */ -.equ B0_Tcos, 0x0 /* 0clk */ -.equ B0_Tacc, 0x4 /* 6clk */ -.equ B0_Tcoh, 0x0 /* 0clk */ -.equ B0_Tah, 0x0 /* 0clk */ -.equ B0_Tacp, 0x0 /* 0clk */ -.equ B0_PMC, 0x0 /* normal(1data) */ -/* Bank 1 parameter */ -.equ B1_Tacs, 0x3 /* 4clk */ -.equ B1_Tcos, 0x3 /* 4clk */ -.equ B1_Tacc, 0x7 /* 14clkv */ -.equ B1_Tcoh, 0x3 /* 4clk */ -.equ B1_Tah, 0x3 /* 4clk */ -.equ B1_Tacp, 0x3 /* 6clk */ -.equ B1_PMC, 0x0 /* normal(1data) */ - -/* Bank 2 parameter - LAN91C96 */ -.equ B2_Tacs, 0x3 /* 4clk */ -.equ B2_Tcos, 0x3 /* 4clk */ -.equ B2_Tacc, 0x7 /* 14clk */ -.equ B2_Tcoh, 0x3 /* 4clk */ -.equ B2_Tah, 0x3 /* 4clk */ -.equ B2_Tacp, 0x3 /* 6clk */ -.equ B2_PMC, 0x0 /* normal(1data) */ - -/* Bank 3 parameter */ -.equ B3_Tacs, 0x3 /* 4clk */ -.equ B3_Tcos, 0x3 /* 4clk */ -.equ B3_Tacc, 0x7 /* 14clk */ -.equ B3_Tcoh, 0x3 /* 4clk */ -.equ B3_Tah, 0x3 /* 4clk */ -.equ B3_Tacp, 0x3 /* 6clk */ -.equ B3_PMC, 0x0 /* normal(1data) */ - -/* Bank 4 parameter */ -.equ B4_Tacs, 0x3 /* 4clk */ -.equ B4_Tcos, 0x3 /* 4clk */ -.equ B4_Tacc, 0x7 /* 14clk */ -.equ B4_Tcoh, 0x3 /* 4clk */ -.equ B4_Tah, 0x3 /* 4clk */ -.equ B4_Tacp, 0x3 /* 6clk */ -.equ B4_PMC, 0x0 /* normal(1data) */ - -/* Bank 5 parameter */ -.equ B5_Tacs, 0x3 /* 4clk */ -.equ B5_Tcos, 0x3 /* 4clk */ -.equ B5_Tacc, 0x7 /* 14clk */ -.equ B5_Tcoh, 0x3 /* 4clk */ -.equ B5_Tah, 0x3 /* 4clk */ -.equ B5_Tacp, 0x3 /* 6clk */ -.equ B5_PMC, 0x0 /* normal(1data) */ - -/* Bank 6(if SROM) parameter */ -.equ B6_Tacs, 0x3 /* 4clk */ -.equ B6_Tcos, 0x3 /* 4clk */ -.equ B6_Tacc, 0x7 /* 14clk */ -.equ B6_Tcoh, 0x3 /* 4clk */ -.equ B6_Tah, 0x3 /* 4clk */ -.equ B6_Tacp, 0x3 /* 6clk */ -.equ B6_PMC, 0x0 /* normal(1data) */ - -/* Bank 7(if SROM) parameter */ -.equ B7_Tacs, 0x3 /* 4clk */ -.equ B7_Tcos, 0x3 /* 4clk */ -.equ B7_Tacc, 0x7 /* 14clk */ -.equ B7_Tcoh, 0x3 /* 4clk */ -.equ B7_Tah, 0x3 /* 4clk */ -.equ B7_Tacp, 0x3 /* 6clk */ -.equ B7_PMC, 0x0 /* normal(1data) */ - -/* Bank 6 parameter */ -.equ B6_MT, 0x3 /* SDRAM */ -.equ B6_Trcd, 0x0 /* 2clk */ -.equ B6_SCAN, 0x0 /* 10bit */ - -.equ B7_MT, 0x3 /* SDRAM */ -.equ B7_Trcd, 0x0 /* 2clk */ -.equ B7_SCAN, 0x0 /* 10bit */ - - -/* REFRESH parameter */ -.equ REFEN, 0x1 /* Refresh enable */ -.equ TREFMD, 0x0 /* CBR(CAS before RAS)/Auto refresh */ -.equ Trp, 0x0 /* 2clk */ -.equ Trc, 0x3 /* 0x1=5clk 0x3=11clk*/ -.equ Tchr, 0x0 /* 0x2=3clk 0x0=0clks */ -.equ REFCNT, 879 - -MEMORY_CONFIG: - .long 0x12111900 /* Bank0 = OM[1:0] , Bank1-7 16bit, Bank2=Nowait,UB/LB*/ - .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) /*GCS0*/ - .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) /*GCS1*/ - .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) /*GCS2*/ - .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) /*GCS3*/ - .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) /*GCS4*/ - .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) /*GCS5*/ - .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) /*GCS6*/ - .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) /*GCS7*/ - .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) /*REFRESH RFEN=1, TREFMD=0, trp=3clk, trc=5clk, tchr=3clk,count=1019*/ - .word 0x17 /*SCLK power down mode, BANKSIZE 16M/16M*/ - .word 0x20 /*MRSR6 CL=2clk*/ - .word 0x20 /*MRSR7*/ - - -.globl lowlevel_init -lowlevel_init: - - /* - the next instruction fail due memory relocation... - we'll find the right MEMORY_CONFIG address with the next 3 lines... - */ - /*ldr r0, =MEMORY_CONFIG*/ - mov r0, pc - ldr r1, =(0x38+4) - sub r0, r0, r1 - - ldmia r0, {r1-r13} - ldr r0, =0x01c80000 - stmia r0, {r1-r13} - mov pc, lr diff --git a/board/davedenx/qong/fpga.c b/board/davedenx/qong/fpga.c index 789acf0696..6536a0b695 100644 --- a/board/davedenx/qong/fpga.c +++ b/board/davedenx/qong/fpga.c @@ -25,7 +25,7 @@ #include <common.h> #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> -#include <mxc_gpio.h> +#include <asm/gpio.h> #include <fpga.h> #include <lattice.h> #include "qong_fpga.h" @@ -41,22 +41,22 @@ static void qong_jtag_init(void) static void qong_fpga_jtag_set_tdi(int value) { - mxc_gpio_set(QONG_FPGA_TDI_PIN, value); + gpio_set_value(QONG_FPGA_TDI_PIN, value); } static void qong_fpga_jtag_set_tms(int value) { - mxc_gpio_set(QONG_FPGA_TMS_PIN, value); + gpio_set_value(QONG_FPGA_TMS_PIN, value); } static void qong_fpga_jtag_set_tck(int value) { - mxc_gpio_set(QONG_FPGA_TCK_PIN, value); + gpio_set_value(QONG_FPGA_TCK_PIN, value); } static int qong_fpga_jtag_get_tdo(void) { - return mxc_gpio_get(QONG_FPGA_TDO_PIN); + return gpio_get_value(QONG_FPGA_TDO_PIN); } lattice_board_specific_func qong_fpga_fns = { diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c index ec22627680..99432edabc 100644 --- a/board/davedenx/qong/qong.c +++ b/board/davedenx/qong/qong.c @@ -28,7 +28,7 @@ #include <asm/io.h> #include <nand.h> #include <fsl_pmic.h> -#include <mxc_gpio.h> +#include <asm/gpio.h> #include "qong_fpga.h" #include <watchdog.h> @@ -51,9 +51,9 @@ int dram_init (void) static void qong_fpga_reset(void) { - mxc_gpio_set(QONG_FPGA_RST_PIN, 0); + gpio_set_value(QONG_FPGA_RST_PIN, 0); udelay(30); - mxc_gpio_set(QONG_FPGA_RST_PIN, 1); + gpio_set_value(QONG_FPGA_RST_PIN, 1); udelay(300); } @@ -76,21 +76,20 @@ int board_early_init_f (void) /* FPGA reset Pin */ /* rstn = 0 */ - mxc_gpio_set(QONG_FPGA_RST_PIN, 0); - mxc_gpio_direction(QONG_FPGA_RST_PIN, MXC_GPIO_DIRECTION_OUT); + gpio_direction_output(QONG_FPGA_RST_PIN, 0); /* set interrupt pin as input */ - mxc_gpio_direction(QONG_FPGA_IRQ_PIN, MXC_GPIO_DIRECTION_IN); + gpio_direction_input(QONG_FPGA_IRQ_PIN); /* FPGA JTAG Interface */ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS6, MUX_CTL_GPIO)); mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK6, MUX_CTL_GPIO)); mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CAPTURE, MUX_CTL_GPIO)); mx31_gpio_mux(IOMUX_MODE(MUX_CTL_COMPARE, MUX_CTL_GPIO)); - mxc_gpio_direction(QONG_FPGA_TCK_PIN, MXC_GPIO_DIRECTION_OUT); - mxc_gpio_direction(QONG_FPGA_TMS_PIN, MXC_GPIO_DIRECTION_OUT); - mxc_gpio_direction(QONG_FPGA_TDI_PIN, MXC_GPIO_DIRECTION_OUT); - mxc_gpio_direction(QONG_FPGA_TDO_PIN, MXC_GPIO_DIRECTION_IN); + gpio_direction_output(QONG_FPGA_TCK_PIN, 0); + gpio_direction_output(QONG_FPGA_TMS_PIN, 0); + gpio_direction_output(QONG_FPGA_TDI_PIN, 0); + gpio_direction_input(QONG_FPGA_TDO_PIN); #endif /* setup pins for UART1 */ @@ -263,27 +262,26 @@ static void board_nand_setup(void) qong_fpga_reset(); /* Enable NAND flash */ - mxc_gpio_set(15, 1); - mxc_gpio_set(14, 1); - mxc_gpio_direction(15, MXC_GPIO_DIRECTION_OUT); - mxc_gpio_direction(16, MXC_GPIO_DIRECTION_IN); - mxc_gpio_direction(14, MXC_GPIO_DIRECTION_IN); - mxc_gpio_set(15, 0); + gpio_set_value(15, 1); + gpio_set_value(14, 1); + gpio_direction_output(15, 0); + gpio_direction_input(16); + gpio_direction_input(14); } int qong_nand_rdy(void *chip) { udelay(1); - return mxc_gpio_get(16); + return gpio_get_value(16); } void qong_nand_select_chip(struct mtd_info *mtd, int chip) { if (chip >= 0) - mxc_gpio_set(15, 0); + gpio_set_value(15, 0); else - mxc_gpio_set(15, 1); + gpio_set_value(15, 1); } diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index 73eaa48b0b..2f950e7bdf 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -30,6 +30,7 @@ #include <asm/arch/emac_defs.h> #include <asm/io.h> #include <asm/arch/davinci_misc.h> +#include <hwconfig.h> DECLARE_GLOBAL_DATA_PTR; @@ -105,6 +106,57 @@ const struct pinmux_config nand_pins[] = { { pinmux(12), 1, 5 }, { pinmux(12), 1, 6 } }; +#elif defined(CONFIG_USE_NOR) +/* NOR pin muxer settings */ +const struct pinmux_config nor_pins[] = { + /* GP0[11] is required for NOR to work on Rev 3 EVMs */ + { pinmux(0), 8, 4 }, /* GP0[11] */ + { pinmux(5), 1, 6 }, + { pinmux(6), 1, 6 }, + { pinmux(7), 1, 0 }, + { pinmux(7), 1, 4 }, + { pinmux(7), 1, 5 }, + { pinmux(8), 1, 0 }, + { pinmux(8), 1, 1 }, + { pinmux(8), 1, 2 }, + { pinmux(8), 1, 3 }, + { pinmux(8), 1, 4 }, + { pinmux(8), 1, 5 }, + { pinmux(8), 1, 6 }, + { pinmux(8), 1, 7 }, + { pinmux(9), 1, 0 }, + { pinmux(9), 1, 1 }, + { pinmux(9), 1, 2 }, + { pinmux(9), 1, 3 }, + { pinmux(9), 1, 4 }, + { pinmux(9), 1, 5 }, + { pinmux(9), 1, 6 }, + { pinmux(9), 1, 7 }, + { pinmux(10), 1, 0 }, + { pinmux(10), 1, 1 }, + { pinmux(10), 1, 2 }, + { pinmux(10), 1, 3 }, + { pinmux(10), 1, 4 }, + { pinmux(10), 1, 5 }, + { pinmux(10), 1, 6 }, + { pinmux(10), 1, 7 }, + { pinmux(11), 1, 0 }, + { pinmux(11), 1, 1 }, + { pinmux(11), 1, 2 }, + { pinmux(11), 1, 3 }, + { pinmux(11), 1, 4 }, + { pinmux(11), 1, 5 }, + { pinmux(11), 1, 6 }, + { pinmux(11), 1, 7 }, + { pinmux(12), 1, 0 }, + { pinmux(12), 1, 1 }, + { pinmux(12), 1, 2 }, + { pinmux(12), 1, 3 }, + { pinmux(12), 1, 4 }, + { pinmux(12), 1, 5 }, + { pinmux(12), 1, 6 }, + { pinmux(12), 1, 7 } +}; #endif #ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII @@ -114,6 +166,64 @@ const struct pinmux_config nand_pins[] = { #endif #endif /* CONFIG_DRIVER_TI_EMAC */ +void dsp_lpsc_on(unsigned domain, unsigned int id) +{ + dv_reg_p mdstat, mdctl, ptstat, ptcmd; + struct davinci_psc_regs *psc_regs; + + psc_regs = davinci_psc0_regs; + mdstat = &psc_regs->psc0.mdstat[id]; + mdctl = &psc_regs->psc0.mdctl[id]; + ptstat = &psc_regs->ptstat; + ptcmd = &psc_regs->ptcmd; + + while (*ptstat & (0x1 << domain)) + ; + + if ((*mdstat & 0x1f) == 0x03) + return; /* Already on and enabled */ + + *mdctl |= 0x03; + + *ptcmd = 0x1 << domain; + + while (*ptstat & (0x1 << domain)) + ; + while ((*mdstat & 0x1f) != 0x03) + ; /* Probably an overkill... */ +} + +static void dspwake(void) +{ + unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE; + u32 val; + + /* if the device is ARM only, return */ + if ((readl(CHIP_REV_ID_REG) & 0x3f) == 0x10) + return; + + if (hwconfig_subarg_cmp_f("dsp", "wake", "no", NULL)) + return; + + *resetvect++ = 0x1E000; /* DSP Idle */ + /* clear out the next 10 words as NOP */ + memset(resetvect, 0, sizeof(unsigned) *10); + + /* setup the DSP reset vector */ + writel(DAVINCI_L3CBARAM_BASE, HOST1CFG); + + dsp_lpsc_on(1, DAVINCI_LPSC_GEM); + val = readl(PSC0_MDCTL + (15 * 4)); + val |= 0x100; + writel(val, (PSC0_MDCTL + (15 * 4))); +} + +int misc_init_r(void) +{ + dspwake(); + return 0; +} + static const struct pinmux_resource pinmuxes[] = { #ifdef CONFIG_SPI_FLASH PINMUX_ITEM(spi1_pins), @@ -122,6 +232,8 @@ static const struct pinmux_resource pinmuxes[] = { PINMUX_ITEM(i2c_pins), #ifdef CONFIG_NAND_DAVINCI PINMUX_ITEM(nand_pins), +#elif defined(CONFIG_USE_NOR) + PINMUX_ITEM(nor_pins), #endif }; @@ -168,6 +280,7 @@ u32 get_board_rev(void) int board_init(void) { + u32 val; #ifndef CONFIG_USE_IRQ irq_init(); #endif @@ -215,6 +328,16 @@ int board_init(void) if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes))) return 1; +#ifdef CONFIG_USE_NOR + /* Set the GPIO direction as output */ + clrbits_be32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11)); + + /* Set the output as low */ + val = readl(GPIO_BANK0_REG_SET_ADDR); + val |= (0x01 << 11); + writel(val, GPIO_BANK0_REG_CLR_ADDR); +#endif + #ifdef CONFIG_DRIVER_TI_EMAC if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0) return 1; diff --git a/board/edb93xx/Makefile b/board/edb93xx/Makefile deleted file mode 100644 index dcaed06b30..0000000000 --- a/board/edb93xx/Makefile +++ /dev/null @@ -1,50 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := edb93xx.o flash_cfg.o pll_cfg.o sdram_cfg.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak .depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/edb93xx/config.mk b/board/edb93xx/config.mk deleted file mode 100644 index fab59ef73c..0000000000 --- a/board/edb93xx/config.mk +++ /dev/null @@ -1,33 +0,0 @@ -LDSCRIPT := $(SRCTREE)/arch/arm/cpu/arm920t/ep93xx/u-boot.lds - -ifdef CONFIG_EDB9301 -CONFIG_SYS_TEXT_BASE = 0x05700000 -endif - -ifdef CONFIG_EDB9302 -CONFIG_SYS_TEXT_BASE = 0x05700000 -endif - -ifdef CONFIG_EDB9302A -CONFIG_SYS_TEXT_BASE = 0xc5700000 -endif - -ifdef CONFIG_EDB9307 -CONFIG_SYS_TEXT_BASE = 0x01f00000 -endif - -ifdef CONFIG_EDB9307A -CONFIG_SYS_TEXT_BASE = 0xc1f00000 -endif - -ifdef CONFIG_EDB9312 -CONFIG_SYS_TEXT_BASE = 0x01f00000 -endif - -ifdef CONFIG_EDB9315 -CONFIG_SYS_TEXT_BASE = 0x01f00000 -endif - -ifdef CONFIG_EDB9315A -CONFIG_SYS_TEXT_BASE = 0xc1f00000 -endif diff --git a/board/edb93xx/early_udelay.h b/board/edb93xx/early_udelay.h deleted file mode 100644 index 185283d98d..0000000000 --- a/board/edb93xx/early_udelay.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -/* delay execution before timers are initialized */ -static inline void early_udelay(uint32_t usecs) -{ - /* loop takes 4 cycles at 5.0ns (fastest case, running at 200MHz) */ - register uint32_t loops = usecs * (1000 / 20); - - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} diff --git a/board/edb93xx/edb93xx.c b/board/edb93xx/edb93xx.c deleted file mode 100644 index dde30ffdc2..0000000000 --- a/board/edb93xx/edb93xx.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net> - * - * (C) Copyright 2002 2003 - * Network Audio Technologies, Inc. <www.netaudiotech.com> - * Adam Bezanson <bezanson@netaudiotech.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <netdev.h> -#include <asm/arch/ep93xx.h> -#include <asm/io.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define MAX_BANK_SIZE 0x04000000 /* 64 MB */ - -static ulong const bank_addr[CONFIG_NR_DRAM_BANKS] = { - PHYS_SDRAM_1, -#ifdef PHYS_SDRAM_2 - PHYS_SDRAM_2, -#endif -#ifdef PHYS_SDRAM_3 - PHYS_SDRAM_3, -#endif -#ifdef PHYS_SDRAM_4 - PHYS_SDRAM_4 -#endif -}; - -int board_init(void) -{ - struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; - - icache_enable(); - -#ifdef USE_920T_MMU - dcache_enable(); -#endif - - /* - * set UARTBAUD bit to drive UARTs with 14.7456MHz instead of - * 14.7456/2 MHz - */ - uint32_t value = readl(&syscon->pwrcnt); - value |= SYSCON_PWRCNT_UART_BAUD; - writel(value, &syscon->pwrcnt); - - /* Enable the uart in devicecfg */ - value = readl(&syscon->devicecfg); - value |= 1<<18 /* U1EN */; - writel(0xAA, &syscon->sysswlock); - writel(value, &syscon->devicecfg); - - /* Machine number, as defined in linux/arch/arm/tools/mach-types */ - gd->bd->bi_arch_number = CONFIG_MACH_TYPE; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; - - /* We have a console */ - gd->have_console = 1; - - return 0; -} - -int board_eth_init(bd_t *bd) -{ - return ep93xx_eth_initialize(0, MAC_BASE); -} - -int dram_init(void) -{ - unsigned int *src, *dst; - int i; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - const ulong bank_size = get_ram_size((long *)bank_addr[i], - MAX_BANK_SIZE); - if (bank_size) { - gd->bd->bi_dram[i].start = bank_addr[i]; - gd->bd->bi_dram[i].size = bank_size; - } - } - - /* copy exception vectors */ - src = (unsigned int *)_armboot_start; - dst = (unsigned int *)PHYS_SDRAM_1; - memcpy(dst, src, 16 * sizeof(unsigned int)); - - return 0; -} diff --git a/board/edb93xx/flash_cfg.c b/board/edb93xx/flash_cfg.c deleted file mode 100644 index a4c20486c0..0000000000 --- a/board/edb93xx/flash_cfg.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Flash setup for Cirrus edb93xx boards - * - * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/arch/ep93xx.h> -#include <asm/io.h> - -#define SMC_BCR6_VALUE (2 << SMC_BCR_IDCY_SHIFT | 5 << SMC_BCR_WST1_SHIFT | \ - SMC_BCR_BLE | 2 << SMC_BCR_WST2_SHIFT | \ - 1 << SMC_BCR_MW_SHIFT) - -void flash_cfg(void) -{ - struct smc_regs *smc = (struct smc_regs *)SMC_BASE; - - writel(SMC_BCR6_VALUE, &smc->bcr6); -} diff --git a/board/edb93xx/pll_cfg.c b/board/edb93xx/pll_cfg.c deleted file mode 100644 index a687af0a01..0000000000 --- a/board/edb93xx/pll_cfg.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * PLL setup for Cirrus edb93xx boards - * - * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net> - * - * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/io.h> -#include "pll_cfg.h" -#include "early_udelay.h" - -void pll_cfg(void) -{ - struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE; - - /* setup PLL1 */ - writel(CLKSET1_VAL, &syscon->clkset1); - - /* - * flush the pipeline - * writing to CLKSET1 causes the EP93xx to enter standby for between - * 8 ms to 16 ms, until PLL1 stabilizes - */ - asm("nop"); - asm("nop"); - asm("nop"); - asm("nop"); - asm("nop"); - - /* setup PLL2 */ - writel(CLKSET2_VAL, &syscon->clkset2); - - /* - * the user's guide recommends to wait at least 1 ms for PLL2 to - * stabilize - */ - early_udelay(1000); -} diff --git a/board/edb93xx/pll_cfg.h b/board/edb93xx/pll_cfg.h deleted file mode 100644 index 0b6f469340..0000000000 --- a/board/edb93xx/pll_cfg.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - * PLL register values for Cirrus edb93xx boards - * - * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <asm/arch/ep93xx.h> - -#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) || \ - defined(CONFIG_EDB9302A) -/* - * fclk_div: 2, nbyp1: 1, hclk_div: 5, pclk_div: 2 - * pll1_x1: 294912000.000000, pll1_x2ip: 36864000.000000, - * pll1_x2: 331776000.000000, pll1_out: 331776000.000000 - */ -#define CLKSET1_VAL (7 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \ - 8 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \ - 19 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \ - 1 << SYSCON_CLKSET1_PCLK_DIV_SHIFT | \ - 3 << SYSCON_CLKSET1_HCLK_DIV_SHIFT | \ - SYSCON_CLKSET1_NBYP1 | \ - 1 << SYSCON_CLKSET1_FCLK_DIV_SHIFT) -#elif defined(CONFIG_EDB9307) || defined(CONFIG_EDB9307A) || \ - defined CONFIG_EDB9312 || defined(CONFIG_EDB9315) || \ - defined(CONFIG_EDB9315A) -/* - * fclk_div: 2, nbyp1: 1, hclk_div: 4, pclk_div: 2 - * pll1_x1: 3096576000.000000, pll1_x2ip: 129024000.000000, - * pll1_x2: 3999744000.000000, pll1_out: 1999872000.000000 - */ -#define CLKSET1_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \ - 30 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \ - 20 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \ - 1 << SYSCON_CLKSET1_PCLK_DIV_SHIFT | \ - 2 << SYSCON_CLKSET1_HCLK_DIV_SHIFT | \ - SYSCON_CLKSET1_NBYP1 | \ - 1 << SYSCON_CLKSET1_FCLK_DIV_SHIFT) -#else -#error "Undefined board" -#endif - -/* - * usb_div: 4, nbyp2: 1, pll2_en: 1 - * pll2_x1: 368640000.000000, pll2_x2ip: 15360000.000000, - * pll2_x2: 384000000.000000, pll2_out: 192000000.000000 - */ -#define CLKSET2_VAL (23 << SYSCON_CLKSET_PLL_X2IPD_SHIFT | \ - 24 << SYSCON_CLKSET_PLL_X2FBD2_SHIFT | \ - 24 << SYSCON_CLKSET_PLL_X1FBD1_SHIFT | \ - 1 << SYSCON_CLKSET_PLL_PS_SHIFT | \ - SYSCON_CLKSET2_PLL2_EN | \ - SYSCON_CLKSET2_NBYP2 | \ - 3 << SYSCON_CLKSET2_USB_DIV_SHIFT) diff --git a/board/edb93xx/sdram_cfg.c b/board/edb93xx/sdram_cfg.c deleted file mode 100644 index 440ad11fcb..0000000000 --- a/board/edb93xx/sdram_cfg.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - * Copyright (C) 2009, 2010 Matthias Kaehlcke <matthias@kaehlcke.net> - * - * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <asm/io.h> -#include "sdram_cfg.h" -#include "early_udelay.h" - -#define PROGRAM_MODE_REG(bank) (*(volatile uint32_t *) \ - (SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank | SDRAM_MODE_REG_VAL)) - -#define PRECHARGE_BANK(bank) (*(volatile uint32_t *) \ - (SDRAM_BASE_ADDR | SDRAM_BANK_SEL_##bank)) = 0 - -static void precharge_all_banks(void); -static void setup_refresh_timer(void); -static void program_mode_registers(void); - -void sdram_cfg(void) -{ - struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE; - - writel(SDRAM_DEVCFG_VAL, &sdram->SDRAM_DEVCFG_REG); - - /* Issue continous NOP commands */ - writel(GLCONFIG_INIT | GLCONFIG_MRS | GLCONFIG_CKE, &sdram->glconfig); - - early_udelay(200); - - precharge_all_banks(); - - setup_refresh_timer(); - - program_mode_registers(); - - /* Select normal operation mode */ - writel(GLCONFIG_CKE, &sdram->glconfig); -} - -static void precharge_all_banks(void) -{ - struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE; - - /* Issue PRECHARGE ALL commands */ - writel(GLCONFIG_INIT | GLCONFIG_CKE, &sdram->glconfig); - - /* - * Errata of most EP93xx revisions say that PRECHARGE ALL isn't always - * issued - * - * Cirrus proposes a workaround which consists in performing a read from - * each bank to force the precharge. This causes some boards to hang. - * Writing to the SDRAM banks instead of reading has the same - * side-effect (the SDRAM controller issues the necessary precharges), - * but is known to work on all supported boards - */ - - PRECHARGE_BANK(0); - -#if (CONFIG_NR_DRAM_BANKS >= 2) - PRECHARGE_BANK(1); -#endif - -#if (CONFIG_NR_DRAM_BANKS >= 3) - PRECHARGE_BANK(2); -#endif - -#if (CONFIG_NR_DRAM_BANKS == 4) - PRECHARGE_BANK(3); -#endif -} - -static void setup_refresh_timer(void) -{ - struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE; - - /* Load refresh timer with 10 to issue refresh every 10 cycles */ - writel(0x0a, &sdram->refrshtimr); - - /* - * Wait at least 80 clock cycles to provide 8 refresh cycles - * to all SDRAMs - */ - early_udelay(1); - - /* - * Program refresh timer with normal value - * We need 8192 refresh cycles every 64ms - * at 15ns (HCLK >= 66MHz) per cycle: - * 64ms / 8192 = 7.8125us - * 7.8125us / 15ns = 520 (0x208) - */ - /* - * TODO: redboot uses 0x1e0 for the slowest possible device - * but i don't understand how this value is calculated - */ - writel(0x208, &sdram->refrshtimr); -} - -static void program_mode_registers(void) -{ - struct sdram_regs *sdram = (struct sdram_regs *)SDRAM_BASE; - - /* Select mode register update mode */ - writel(GLCONFIG_MRS | GLCONFIG_CKE, &sdram->glconfig); - - /* - * The mode registers are programmed by performing a read from each - * SDRAM bank. The value of the address that is read defines the value - * that is written into the mode register - */ - - PROGRAM_MODE_REG(0); - -#if (CONFIG_NR_DRAM_BANKS >= 2) - PROGRAM_MODE_REG(1); -#endif - -#if (CONFIG_NR_DRAM_BANKS >= 3) - PROGRAM_MODE_REG(2); -#endif - -#if (CONFIG_NR_DRAM_BANKS == 4) - PROGRAM_MODE_REG(3); -#endif -} diff --git a/board/edb93xx/sdram_cfg.h b/board/edb93xx/sdram_cfg.h deleted file mode 100644 index 757b63c256..0000000000 --- a/board/edb93xx/sdram_cfg.h +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net> - * - * Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <asm/arch/ep93xx.h> - -#define SDRAM_BASE_ADDR PHYS_SDRAM_1 - -#ifdef CONFIG_EDB93XX_SDCS0 -#define SDRAM_DEVCFG_REG devcfg0 -#elif defined(CONFIG_EDB93XX_SDCS3) -#define SDRAM_DEVCFG_REG devcfg3 -#else -#error "SDRAM bank configuration" -#endif - -#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) || \ - defined(CONFIG_EDB9302A) -/* - * 1x Samsung K4S561632C-TC/L75 4M x 16bit x 4 banks SDRAM - * - * CLK cycle time min: - * @ CAS latency = 3: 7.5ns - * @ CAS latency = 2: 10ns - * We're running at 66MHz (15ns cycle time) external bus speed (HCLK), - * so it's safe to use CAS latency = 2 - * - * RAS-to-CAS delay min: - * 20ns - * At 15ns cycle time, we use RAS-to-CAS delay = 2 - * - * SROMLL = 1: Swap BA[1:0] with A[13:12], making the SDRAM appear - * as four blocks of 8MB size, instead of eight blocks of 4MB size: - * - * EDB9301/EDB9302: - * - * 0x00000000 - 0x007fffff - * 0x01000000 - 0x017fffff - * 0x04000000 - 0x047fffff - * 0x05000000 - 0x057fffff - * - * - * EDB9302a: - * - * 0xc0000000 - 0xc07fffff - * 0xc1000000 - 0xc17fffff - * 0xc4000000 - 0xc47fffff - * 0xc5000000 - 0xc57fffff - * - * BANKCOUNT = 1: This is a device with four banks - */ - -#define SDRAM_DEVCFG_VAL (SDRAM_DEVCFG_BANKCOUNT | \ - SDRAM_DEVCFG_SROMLL | \ - SDRAM_DEVCFG_CASLAT_2 | \ - SDRAM_DEVCFG_RASTOCAS_2 | \ - SDRAM_DEVCFG_EXTBUSWIDTH) - -/* - * 16 bit ext. bus - * - * A[22:09] is output as SYA[13:0] - * CAS latency: 2 - * Burst type: sequential - * Burst length: 8 (required for 16 bit ext. bus) - * SYA[13:0] = 0x0023 - */ -#define SDRAM_MODE_REG_VAL 0x4600 - -#define SDRAM_BANK_SEL_0 0x00000000 /* A[22:21] = b00 */ -#define SDRAM_BANK_SEL_1 0x00200000 /* A[22:21] = b01 */ -#define SDRAM_BANK_SEL_2 0x00400000 /* A[22:21] = b10 */ -#define SDRAM_BANK_SEL_3 0x00600000 /* A[22:21] = b11 */ - -#elif defined(CONFIG_EDB9307) || defined(CONFIG_EDB9307A) || \ - defined CONFIG_EDB9312 || defined(CONFIG_EDB9315) || \ - defined(CONFIG_EDB9315A) -/* - * 2x Samsung K4S561632C-TC/L75 4M x 16bit x 4 banks SDRAM - * - * CLK cycle time min: - * @ CAS latency = 3: 7.5ns - * @ CAS latency = 2: 10ns - * We're running at 100MHz (10ns cycle time) external bus speed (HCLK), - * so it's safe to use CAS latency = 2 - * - * RAS-to-CAS delay min: - * 20ns - * At 10ns cycle time, we use RAS-to-CAS delay = 2 - * - * EDB9307, EDB9312, EDB9315: - * - * 0x00000000 - 0x01ffffff - * 0x04000000 - 0x05ffffff - * - * - * EDB9307a, EDB9315a: - * - * 0xc0000000 - 0xc1ffffff - * 0xc4000000 - 0xc5ffffff - */ - -#define SDRAM_DEVCFG_VAL (SDRAM_DEVCFG_BANKCOUNT | \ - SDRAM_DEVCFG_SROMLL | \ - SDRAM_DEVCFG_CASLAT_2 | \ - SDRAM_DEVCFG_RASTOCAS_2) - -/* - * 32 bit ext. bus - * - * A[23:10] is output as SYA[13:0] - * CAS latency: 2 - * Burst type: sequential - * Burst length: 4 - * SYA[13:0] = 0x0022 - */ -#define SDRAM_MODE_REG_VAL 0x8800 - -#define SDRAM_BANK_SEL_0 0x00000000 /* A[23:22] = b00 */ -#define SDRAM_BANK_SEL_1 0x00400000 /* A[23:22] = b01 */ -#define SDRAM_BANK_SEL_2 0x00800000 /* A[23:22] = b10 */ -#define SDRAM_BANK_SEL_3 0x00c00000 /* A[23:22] = b11 */ -#endif diff --git a/board/efikamx/efikamx.c b/board/efikamx/efikamx.c index 4b3691808e..5be1f6ca58 100644 --- a/board/efikamx/efikamx.c +++ b/board/efikamx/efikamx.c @@ -27,7 +27,7 @@ #include <asm/arch/imx-regs.h> #include <asm/arch/mx5x_pins.h> #include <asm/arch/iomux.h> -#include <mxc_gpio.h> +#include <asm/gpio.h> #include <asm/errno.h> #include <asm/arch/sys_proto.h> #include <asm/arch/crm_regs.h> @@ -76,28 +76,23 @@ u32 get_efika_rev(void) * rev1.4: 1,0,0 */ mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO); - mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0), - MXC_GPIO_DIRECTION_OUT); /* set to 1 in order to get correct value on board rev1.1 */ - mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0), 1); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0), 1); mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO); mxc_iomux_set_pad(MX51_PIN_NANDF_CS0, PAD_CTL_100K_PU); - mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0), - MXC_GPIO_DIRECTION_IN); - rev |= (!!mxc_gpio_get(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0))) << 0; + gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0)); + rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0))) << 0; mxc_request_iomux(MX51_PIN_NANDF_CS1, IOMUX_CONFIG_GPIO); mxc_iomux_set_pad(MX51_PIN_NANDF_CS1, PAD_CTL_100K_PU); - mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1), - MXC_GPIO_DIRECTION_IN); - rev |= (!!mxc_gpio_get(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1))) << 1; + gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1)); + rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1))) << 1; mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_GPIO); mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, PAD_CTL_100K_PU); - mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3), - MXC_GPIO_DIRECTION_IN); - rev |= (!!mxc_gpio_get(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3))) << 2; + gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3)); + rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3))) << 2; return (~rev & 0x7) + 1; } @@ -154,15 +149,11 @@ static void setup_iomux_spi(void) /* Configure SS0 as a GPIO */ mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_GPIO); - mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0), - MXC_GPIO_DIRECTION_OUT); - mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0), 0); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0), 0); /* Configure SS1 as a GPIO */ mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_GPIO); - mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1), - MXC_GPIO_DIRECTION_OUT); - mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1), 1); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1), 1); /* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */ mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0); @@ -282,9 +273,9 @@ int board_mmc_getcd(u8 *absent, struct mmc *mmc) struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) - *absent = mxc_gpio_get(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0)); + *absent = gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0)); else - *absent = mxc_gpio_get(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8)); + *absent = gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8)); return 0; } @@ -307,10 +298,8 @@ int board_mmc_init(bd_t *bis) PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_SRE_FAST); - mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0), - MXC_GPIO_DIRECTION_IN); - mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_GPIO1_1), - MXC_GPIO_DIRECTION_IN); + gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0)); + gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_1)); /* Internal SDHC1 IOMUX + SDHC2 IOMUX on old boards */ if (get_efika_rev() < EFIKAMX_BOARD_REV_12) { @@ -389,10 +378,8 @@ int board_mmc_init(bd_t *bis) PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_SRE_FAST); - mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8), - MXC_GPIO_DIRECTION_IN); - mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_GPIO1_7), - MXC_GPIO_DIRECTION_IN); + gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8)); + gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_7)); ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]); if (!ret) @@ -508,25 +495,24 @@ void setup_iomux_led(void) { /* Blue LED */ mxc_request_iomux(MX51_PIN_CSI1_D9, IOMUX_CONFIG_ALT3); - mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), - MXC_GPIO_DIRECTION_OUT); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), 0); + /* Green LED */ mxc_request_iomux(MX51_PIN_CSI1_VSYNC, IOMUX_CONFIG_ALT3); - mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC), - MXC_GPIO_DIRECTION_OUT); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC), 0); + /* Red LED */ mxc_request_iomux(MX51_PIN_CSI1_HSYNC, IOMUX_CONFIG_ALT3); - mxc_gpio_direction(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC), - MXC_GPIO_DIRECTION_OUT); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC), 0); } void efikamx_toggle_led(uint32_t mask) { - mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), mask & EFIKAMX_LED_BLUE); - mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC), + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC), mask & EFIKAMX_LED_GREEN); - mxc_gpio_set(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC), + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC), mask & EFIKAMX_LED_RED); } diff --git a/board/esd/meesc/config.mk b/board/esd/meesc/config.mk deleted file mode 100644 index 207769233e..0000000000 --- a/board/esd/meesc/config.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x21f00000 diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c index 41fa3e1567..ad43531cb1 100644 --- a/board/esd/meesc/meesc.c +++ b/board/esd/meesc/meesc.c @@ -3,7 +3,7 @@ * Stelian Pop <stelian.pop@leadtechdesign.com> * Lead Tech Design <www.leadtechdesign.com> * - * (C) Copyright 2009-2010 + * (C) Copyright 2009-2011 * Daniel Gorsulowski <daniel.gorsulowski@esd.eu> * esd electronic system design gmbh <www.esd.eu> * @@ -27,7 +27,7 @@ */ #include <common.h> -#include <asm/arch/at91sam9263.h> +#include <asm/io.h> #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> @@ -35,8 +35,6 @@ #include <asm/arch/at91_matrix.h> #include <asm/arch/at91_pio.h> #include <asm/arch/clk.h> -#include <asm/arch/hardware.h> -#include <asm/arch/io.h> #include <netdev.h> DECLARE_GLOBAL_DATA_PTR; @@ -67,8 +65,8 @@ int get_hw_rev(void) static void meesc_nand_hw_init(void) { unsigned long csa; - at91_smc_t *smc = (at91_smc_t *) AT91_SMC0_BASE; - at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE; + at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0; + at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX; /* Enable CS3 */ csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A; @@ -88,7 +86,7 @@ static void meesc_nand_hw_init(void) writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | AT91_SMC_MODE_EXNW_DISABLE | AT91_SMC_MODE_DBW_8 | - AT91_SMC_MODE_TDF_CYCLE(2), + AT91_SMC_MODE_TDF_CYCLE(3), &smc->cs[3].mode); /* Configure RDY/BSY */ @@ -102,9 +100,9 @@ static void meesc_nand_hw_init(void) #ifdef CONFIG_MACB static void meesc_macb_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; /* Enable clock */ - writel(1 << AT91SAM9263_ID_EMAC, &pmc->pcer); + writel(1 << ATMEL_ID_EMAC, &pmc->pcer); at91_macb_hw_init(); } #endif @@ -117,7 +115,7 @@ static void meesc_macb_hw_init(void) */ static void meesc_ethercat_hw_init(void) { - at91_smc_t *smc1 = (at91_smc_t *) AT91_SMC1_BASE; + at91_smc_t *smc1 = (at91_smc_t *) ATMEL_BASE_SMC1; /* Configure SMC EBI1_CS0 for EtherCAT */ writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | @@ -142,8 +140,9 @@ static void meesc_ethercat_hw_init(void) int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = get_ram_size((long *) PHYS_SDRAM, (1 << 27)); + gd->ram_size = get_ram_size( + (void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); return 0; } @@ -151,7 +150,7 @@ int board_eth_init(bd_t *bis) { int rc = 0; #ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)AT91_EMAC_BASE, 0x00); + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00); #endif return rc; } @@ -225,7 +224,7 @@ int misc_init_r(void) { char *str; char buf[32]; - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; /* * Normally the processor clock has a divisor of 2. @@ -246,24 +245,28 @@ int misc_init_r(void) } #endif /* CONFIG_MISC_INIT_R */ -int board_init(void) +int board_early_init_f(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - /* Peripheral Clock Enable Register */ - writel(1 << AT91SAM9263_ID_PIOA | - 1 << AT91SAM9263_ID_PIOB | - 1 << AT91SAM9263_ID_PIOCDE | - 1 << AT91SAM9263_ID_UHP, + /* enable all clocks */ + writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) | + (1 << ATMEL_ID_PIOCDE) | (1 << ATMEL_ID_UHP), &pmc->pcer); + at91_seriald_hw_init(); + + return 0; +} + +int board_init(void) +{ /* initialize ET1100 Controller */ meesc_ethercat_hw_init(); /* adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - at91_serial_hw_init(); #ifdef CONFIG_CMD_NAND meesc_nand_hw_init(); #endif diff --git a/board/freescale/mx35pdk/lowlevel_init.S b/board/freescale/mx35pdk/lowlevel_init.S index 9b0f1b5259..9fd04cbdb8 100644 --- a/board/freescale/mx35pdk/lowlevel_init.S +++ b/board/freescale/mx35pdk/lowlevel_init.S @@ -193,10 +193,11 @@ mov r2, #0x00 mov r1, #CSD0_BASE_ADDR bl setup_sdram_bank - cmp r3, #0x0 - orreq r5, r5, #1 - eorne r2, r2, #0x1 - blne setup_sdram_bank + + mov r5, #0x00 + mov r2, #0x00 + mov r1, #CSD1_BASE_ADDR + bl setup_sdram_bank mov lr, fp diff --git a/board/freescale/mx35pdk/mx35pdk.c b/board/freescale/mx35pdk/mx35pdk.c index da926e5781..9eefe5ee16 100644 --- a/board/freescale/mx35pdk/mx35pdk.c +++ b/board/freescale/mx35pdk/mx35pdk.c @@ -34,7 +34,7 @@ #include <mc9sdz60.h> #include <mc13892.h> #include <linux/types.h> -#include <mxc_gpio.h> +#include <asm/gpio.h> #include <asm/arch/sys_proto.h> #include <netdev.h> @@ -52,12 +52,25 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { - gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, - PHYS_SDRAM_1_SIZE); + u32 size1, size2; + + size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); + size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); + + gd->ram_size = size1 + size2; return 0; } +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; +} + static void setup_iomux_i2c(void) { int pad; @@ -227,8 +240,7 @@ int board_late_init(void) mxc_request_iomux(MX35_PIN_COMPARE, MUX_CONFIG_GPIO); mxc_iomux_set_input(MUX_IN_GPIO1_IN_5, INPUT_CTL_PATH0); - mxc_gpio_direction(37, MXC_GPIO_DIRECTION_OUT); - mxc_gpio_set(37, 1); + gpio_direction_output(37, 1); } val = mc9sdz60_reg_read(MC9SDZ60_REG_GPIO_1) | 0x04; diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index fd7342f112..94ea1f2905 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -22,6 +22,7 @@ #include <common.h> #include <asm/io.h> +#include <asm/gpio.h> #include <asm/arch/imx-regs.h> #include <asm/arch/mx5x_pins.h> #include <asm/arch/iomux.h> @@ -180,7 +181,6 @@ static void setup_iomux_spi(void) static void power_init(void) { unsigned int val; - unsigned int reg; struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE; /* Write needed to Power Gate 2 register */ @@ -249,13 +249,7 @@ static void power_init(void) pmic_reg_write(REG_MODE_1, val); udelay(200); - reg = readl(GPIO2_BASE_ADDR + 0x0); - reg &= ~0x4000; /* Lower reset line */ - writel(reg, GPIO2_BASE_ADDR + 0x0); - - reg = readl(GPIO2_BASE_ADDR + 0x4); - reg |= 0x4000; /* configure GPIO lines as output */ - writel(reg, GPIO2_BASE_ADDR + 0x4); + gpio_direction_output(46, 0); /* Reset the ethernet controller over GPIO */ writel(0x1, IOMUXC_BASE_ADDR + 0x0AC); @@ -267,9 +261,7 @@ static void power_init(void) udelay(500); - reg = readl(GPIO2_BASE_ADDR + 0x0); - reg |= 0x4000; - writel(reg, GPIO2_BASE_ADDR + 0x0); + gpio_set_value(46, 1); } #ifdef CONFIG_FSL_ESDHC @@ -278,9 +270,9 @@ int board_mmc_getcd(u8 *cd, struct mmc *mmc) struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) - *cd = readl(GPIO1_BASE_ADDR) & 0x01; + *cd = gpio_get_value(0); else - *cd = readl(GPIO1_BASE_ADDR) & 0x40; + *cd = gpio_get_value(6); return 0; } diff --git a/board/freescale/mx53ard/imximage_dd3.cfg b/board/freescale/mx53ard/imximage_dd3.cfg index 0f298abbd5..50e05afa62 100644 --- a/board/freescale/mx53ard/imximage_dd3.cfg +++ b/board/freescale/mx53ard/imximage_dd3.cfg @@ -83,14 +83,14 @@ DATA 4 0x63fd9004 0x0002002d DATA 4 0x63fd901c 0x00008032 DATA 4 0x63fd901c 0x00008033 DATA 4 0x63fd901c 0x00028031 -DATA 4 0x63fd901c 0x092080b0 +DATA 4 0x63fd901c 0x052080b0 DATA 4 0x63fd901c 0x04008040 DATA 4 0x63fd901c 0x0000803a DATA 4 0x63fd901c 0x0000803b DATA 4 0x63fd901c 0x00028039 -DATA 4 0x63fd901c 0x09208138 +DATA 4 0x63fd901c 0x05208138 DATA 4 0x63fd901c 0x04008048 -DATA 4 0x63fd9020 0x00001800 +DATA 4 0x63fd9020 0x00005800 DATA 4 0x63fd9040 0x04b80003 DATA 4 0x63fd9058 0x00022227 DATA 4 0x63fd901C 0x00000000 diff --git a/board/freescale/mx53ard/mx53ard.c b/board/freescale/mx53ard/mx53ard.c index 134603a7cf..6e3360b65f 100644 --- a/board/freescale/mx53ard/mx53ard.c +++ b/board/freescale/mx53ard/mx53ard.c @@ -31,7 +31,7 @@ #include <netdev.h> #include <mmc.h> #include <fsl_esdhc.h> -#include <mxc_gpio.h> +#include <asm/gpio.h> #define ETHERNET_INT (1 * 32 + 31) /* GPIO2_31 */ @@ -93,9 +93,9 @@ int board_mmc_getcd(u8 *cd, struct mmc *mmc) struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) - *cd = mxc_gpio_get(1); /*GPIO1_1*/ + *cd = gpio_get_value(1); /*GPIO1_1*/ else - *cd = mxc_gpio_get(4); /*GPIO1_4*/ + *cd = gpio_get_value(4); /*GPIO1_4*/ return 0; } @@ -176,7 +176,7 @@ static void weim_smc911x_iomux(void) { /* ETHERNET_INT as GPIO2_31 */ mxc_request_iomux(MX53_PIN_EIM_EB3, IOMUX_CONFIG_ALT1); - mxc_gpio_direction(ETHERNET_INT, MXC_GPIO_DIRECTION_IN); + gpio_direction_input(ETHERNET_INT); /* Data bus */ mxc_request_iomux(MX53_PIN_EIM_D16, IOMUX_CONFIG_ALT0); diff --git a/board/freescale/mx53evk/mx53evk.c b/board/freescale/mx53evk/mx53evk.c index 88095dc7ae..81857ffed3 100644 --- a/board/freescale/mx53evk/mx53evk.c +++ b/board/freescale/mx53evk/mx53evk.c @@ -33,7 +33,7 @@ #include <mmc.h> #include <fsl_esdhc.h> #include <fsl_pmic.h> -#include <mxc_gpio.h> +#include <asm/gpio.h> #include <mc13892.h> DECLARE_GLOBAL_DATA_PTR; @@ -213,9 +213,9 @@ int board_mmc_getcd(u8 *cd, struct mmc *mmc) struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) - *cd = mxc_gpio_get(77); /*GPIO3_13*/ + *cd = gpio_get_value(77); /*GPIO3_13*/ else - *cd = mxc_gpio_get(75); /*GPIO3_11*/ + *cd = gpio_get_value(75); /*GPIO3_11*/ return 0; } diff --git a/board/freescale/mx53loco/imximage.cfg b/board/freescale/mx53loco/imximage.cfg index ce9c8fc3e3..f30258eda4 100644 --- a/board/freescale/mx53loco/imximage.cfg +++ b/board/freescale/mx53loco/imximage.cfg @@ -83,14 +83,14 @@ DATA 4 0x63fd9004 0x0002002d DATA 4 0x63fd901c 0x00008032 DATA 4 0x63fd901c 0x00008033 DATA 4 0x63fd901c 0x00028031 -DATA 4 0x63fd901c 0x092080b0 +DATA 4 0x63fd901c 0x052080b0 DATA 4 0x63fd901c 0x04008040 DATA 4 0x63fd901c 0x0000803a DATA 4 0x63fd901c 0x0000803b DATA 4 0x63fd901c 0x00028039 -DATA 4 0x63fd901c 0x09208138 +DATA 4 0x63fd901c 0x05208138 DATA 4 0x63fd901c 0x04008048 -DATA 4 0x63fd9020 0x00001800 +DATA 4 0x63fd9020 0x00005800 DATA 4 0x63fd9040 0x04b80003 DATA 4 0x63fd9058 0x00022227 DATA 4 0x63fd901c 0x00000000 diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index 18b388eeda..ade100608d 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -34,7 +34,7 @@ #include <i2c.h> #include <mmc.h> #include <fsl_esdhc.h> -#include <mxc_gpio.h> +#include <asm/gpio.h> DECLARE_GLOBAL_DATA_PTR; @@ -146,9 +146,9 @@ int board_mmc_getcd(u8 *cd, struct mmc *mmc) struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) - *cd = mxc_gpio_get(77); /*GPIO3_13*/ + *cd = gpio_get_value(77); /*GPIO3_13*/ else - *cd = mxc_gpio_get(75); /*GPIO3_11*/ + *cd = gpio_get_value(75); /*GPIO3_11*/ return 0; } diff --git a/board/freescale/mx53smd/imximage.cfg b/board/freescale/mx53smd/imximage.cfg index 0f298abbd5..50e05afa62 100644 --- a/board/freescale/mx53smd/imximage.cfg +++ b/board/freescale/mx53smd/imximage.cfg @@ -83,14 +83,14 @@ DATA 4 0x63fd9004 0x0002002d DATA 4 0x63fd901c 0x00008032 DATA 4 0x63fd901c 0x00008033 DATA 4 0x63fd901c 0x00028031 -DATA 4 0x63fd901c 0x092080b0 +DATA 4 0x63fd901c 0x052080b0 DATA 4 0x63fd901c 0x04008040 DATA 4 0x63fd901c 0x0000803a DATA 4 0x63fd901c 0x0000803b DATA 4 0x63fd901c 0x00028039 -DATA 4 0x63fd901c 0x09208138 +DATA 4 0x63fd901c 0x05208138 DATA 4 0x63fd901c 0x04008048 -DATA 4 0x63fd9020 0x00001800 +DATA 4 0x63fd9020 0x00005800 DATA 4 0x63fd9040 0x04b80003 DATA 4 0x63fd9058 0x00022227 DATA 4 0x63fd901C 0x00000000 diff --git a/board/freescale/mx53smd/mx53smd.c b/board/freescale/mx53smd/mx53smd.c index 21b5d14c02..4a7ee550d5 100644 --- a/board/freescale/mx53smd/mx53smd.c +++ b/board/freescale/mx53smd/mx53smd.c @@ -31,7 +31,7 @@ #include <netdev.h> #include <mmc.h> #include <fsl_esdhc.h> -#include <mxc_gpio.h> +#include <asm/gpio.h> DECLARE_GLOBAL_DATA_PTR; @@ -139,7 +139,7 @@ struct fsl_esdhc_cfg esdhc_cfg[1] = { int board_mmc_getcd(u8 *cd, struct mmc *mmc) { - *cd = mxc_gpio_get(77); /*GPIO3_13*/ + *cd = gpio_get_value(77); /*GPIO3_13*/ return 0; } diff --git a/board/kb9202/Makefile b/board/kb9202/Makefile deleted file mode 100644 index 49be161fa2..0000000000 --- a/board/kb9202/Makefile +++ /dev/null @@ -1,53 +0,0 @@ -# -# (C) Copyright 2003-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -# Adapted for KwikByte KB920x boards - APR2005 -# -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := kb9202.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/kb9202/config.mk b/board/kb9202/config.mk deleted file mode 100644 index 207769233e..0000000000 --- a/board/kb9202/config.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x21f00000 diff --git a/board/kb9202/kb9202.c b/board/kb9202/kb9202.c deleted file mode 100644 index 3164cc5ac4..0000000000 --- a/board/kb9202/kb9202.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * Adapted for KwikByte KB920x board from at91rm9200dk.c: 22APR2005 - */ - -#include <common.h> -#include <asm/arch/AT91RM9200.h> -#include <asm/io.h> -#include <netdev.h> -#if defined(CONFIG_DRIVER_ETHER) -#include <at91rm9200_net.h> -#include <lxt971a.h> -#endif - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Miscelaneous platform dependent initialisations - */ - -void lowlevel_init(void) { - /* Required by assembly functions - do nothing */ -} - -int board_init (void) -{ - /* Enable Ctrlc */ - console_init_f (); - - /* memory and cpu-speed are setup before relocation */ - /* so we do _nothing_ here */ - - gd->bd->bi_arch_number = MACH_TYPE_KB9200; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - - return 0; -} - -int dram_init (void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; - return 0; -} - -#ifdef CONFIG_DRIVER_ETHER -#if defined(CONFIG_CMD_NET) - -unsigned int lxt972_IsPhyConnected (AT91PS_EMAC p_mac); -UCHAR lxt972_GetLinkSpeed (AT91PS_EMAC p_mac); -UCHAR lxt972_InitPhy (AT91PS_EMAC p_mac); -UCHAR lxt972_AutoNegotiate (AT91PS_EMAC p_mac, int *status); - -/* - * Name: - * at91rm9200_GetPhyInterface - * Description: - * Initialise the interface functions to the PHY - * Arguments: - * None - * Return value: - * None - */ -void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops) -{ - p_phyops->Init = lxt972_InitPhy; - p_phyops->IsPhyConnected = lxt972_IsPhyConnected; - p_phyops->GetLinkSpeed = lxt972_GetLinkSpeed; - p_phyops->AutoNegotiate = lxt972_AutoNegotiate; -} - -#endif -#endif /* CONFIG_DRIVER_ETHER */ - -#ifdef CONFIG_DRIVER_AT91EMAC -int board_eth_init(bd_t *bis) -{ - int rc = 0; - rc = at91emac_register(bis, 0); - return rc; -} -#endif diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c index bbb6e834ec..c0a006a7b3 100644 --- a/board/logicpd/am3517evm/am3517evm.c +++ b/board/logicpd/am3517evm/am3517evm.c @@ -28,6 +28,7 @@ #include <asm/arch/mem.h> #include <asm/arch/mux.h> #include <asm/arch/sys_proto.h> +#include <asm/arch/mmc_host_def.h> #include <asm/mach-types.h> #include <i2c.h> #include "am3517evm.h" @@ -74,3 +75,11 @@ void set_muxconf_regs(void) { MUX_AM3517EVM(); } + +#ifdef CONFIG_GENERIC_MMC +int board_mmc_init(bd_t *bis) +{ + omap_mmc_init(0); + return 0; +} +#endif diff --git a/board/logicpd/zoom1/zoom1.c b/board/logicpd/zoom1/zoom1.c index 7ef13cc623..dec0b2611f 100644 --- a/board/logicpd/zoom1/zoom1.c +++ b/board/logicpd/zoom1/zoom1.c @@ -34,6 +34,7 @@ #include <netdev.h> #include <twl4030.h> #include <asm/io.h> +#include <asm/arch/mmc_host_def.h> #include <asm/arch/mux.h> #include <asm/arch/sys_proto.h> #include <asm/mach-types.h> @@ -88,6 +89,14 @@ void set_muxconf_regs(void) MUX_ZOOM1_MDK(); } +#ifdef CONFIG_GENERIC_MMC +int board_mmc_init(bd_t *bis) +{ + omap_mmc_init(0); + return 0; +} +#endif + #ifdef CONFIG_CMD_NET int board_eth_init(bd_t *bis) { diff --git a/board/logicpd/zoom2/zoom2.c b/board/logicpd/zoom2/zoom2.c index 76793e42e7..800113a976 100644 --- a/board/logicpd/zoom2/zoom2.c +++ b/board/logicpd/zoom2/zoom2.c @@ -35,6 +35,7 @@ #endif #include <twl4030.h> #include <asm/io.h> +#include <asm/arch/mmc_host_def.h> #include <asm/arch/gpio.h> #include <asm/arch/mem.h> #include <asm/arch/mux.h> @@ -180,6 +181,14 @@ void set_muxconf_regs (void) MUX_ZOOM2 (); } +#ifdef CONFIG_GENERIC_MMC +int board_mmc_init(bd_t *bis) +{ + omap_mmc_init(0); + return 0; +} +#endif + #ifdef CONFIG_CMD_NET int board_eth_init(bd_t *bis) { diff --git a/board/lpd7a40x/Makefile b/board/lpd7a40x/Makefile deleted file mode 100644 index 3aeb2fb1ad..0000000000 --- a/board/lpd7a40x/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := lpd7a40x.o flash.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/lpd7a40x/config.mk b/board/lpd7a40x/config.mk deleted file mode 100644 index 003e70740f..0000000000 --- a/board/lpd7a40x/config.mk +++ /dev/null @@ -1,38 +0,0 @@ -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# Logic ZOOM LH7A400 SDK board w/Logic LH7A400-10 card engine -# w/Sharp LH7A400 SoC (ARM920T) cpu -# - -# -# 32 or 64 MB SDRAM on SDCSC0 @ 0xc0000000 -# -# Linux-Kernel is @ 0xC0008000, entry 0xc0008000 -# params @ 0xc0000100 -# optionally with a ramdisk at 0xc0300000 -# -# we load ourself to 0xc1fc0000 (32M - 256K) -# -# download area is 0xc0f00000 -# - -CONFIG_SYS_TEXT_BASE = 0xc1fc0000 -#CONFIG_SYS_TEXT_BASE = 0x00000000 diff --git a/board/lpd7a40x/flash.c b/board/lpd7a40x/flash.c deleted file mode 100644 index f5c07135dc..0000000000 --- a/board/lpd7a40x/flash.c +++ /dev/null @@ -1,490 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* #define DEBUG */ - -#include <common.h> -#include <environment.h> - -#define FLASH_BANK_SIZE 0x1000000 /* 16MB (2 x 8 MB) */ -#define MAIN_SECT_SIZE 0x40000 /* 256KB (2 x 128kB) */ - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - - -#define CMD_READ_ARRAY 0x00FF00FF -#define CMD_IDENTIFY 0x00900090 -#define CMD_ERASE_SETUP 0x00200020 -#define CMD_ERASE_CONFIRM 0x00D000D0 -#define CMD_PROGRAM 0x00400040 -#define CMD_RESUME 0x00D000D0 -#define CMD_SUSPEND 0x00B000B0 -#define CMD_STATUS_READ 0x00700070 -#define CMD_STATUS_RESET 0x00500050 - -#define BIT_BUSY 0x00800080 -#define BIT_ERASE_SUSPEND 0x00400040 -#define BIT_ERASE_ERROR 0x00200020 -#define BIT_PROGRAM_ERROR 0x00100010 -#define BIT_VPP_RANGE_ERROR 0x00080008 -#define BIT_PROGRAM_SUSPEND 0x00040004 -#define BIT_PROTECT_ERROR 0x00020002 -#define BIT_UNDEFINED 0x00010001 - -#define BIT_SEQUENCE_ERROR 0x00300030 -#define BIT_TIMEOUT 0x80000000 - -/*----------------------------------------------------------------------- - */ - -ulong flash_init (void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - - flash_info[i].flash_id = - (INTEL_MANUFACT & FLASH_VENDMASK) | - (INTEL_ID_28F640J3A & FLASH_TYPEMASK); - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); - if (i == 0) - flashbase = CONFIG_SYS_FLASH_BASE; - else - panic ("configured too many flash banks!\n"); - for (j = 0; j < flash_info[i].sector_count; j++) { - flash_info[i].start[j] = flashbase; - - /* uniform sector size */ - flashbase += MAIN_SECT_SIZE; - } - size += flash_info[i].size; - } - - /* - * Protect monitor and environment sectors - */ - flash_protect ( FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect ( FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, &flash_info[0]); - -#ifdef CONFIG_ENV_ADDR_REDUND - flash_protect ( FLAG_PROTECT_SET, - CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case (INTEL_MANUFACT & FLASH_VENDMASK): - printf ("Intel: "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (INTEL_ID_28F640J3A & FLASH_TYPEMASK): - printf ("2x 28F640J3A (64Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - return; - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - -int flash_error (ulong code) -{ - /* Check bit patterns */ - /* SR.7=0 is busy, SR.7=1 is ready */ - /* all other flags indicate error on 1 */ - /* SR.0 is undefined */ - /* Timeout is our faked flag */ - - /* sequence is described in Intel 290644-005 document */ - - /* check Timeout */ - if (code & BIT_TIMEOUT) { - puts ("Timeout\n"); - return ERR_TIMOUT; - } - - /* check Busy, SR.7 */ - if (~code & BIT_BUSY) { - puts ("Busy\n"); - return ERR_PROG_ERROR; - } - - /* check Vpp low, SR.3 */ - if (code & BIT_VPP_RANGE_ERROR) { - puts ("Vpp range error\n"); - return ERR_PROG_ERROR; - } - - /* check Device Protect Error, SR.1 */ - if (code & BIT_PROTECT_ERROR) { - puts ("Device protect error\n"); - return ERR_PROG_ERROR; - } - - /* check Command Seq Error, SR.4 & SR.5 */ - if (code & BIT_SEQUENCE_ERROR) { - puts ("Command seqence error\n"); - return ERR_PROG_ERROR; - } - - /* check Block Erase Error, SR.5 */ - if (code & BIT_ERASE_ERROR) { - puts ("Block erase error\n"); - return ERR_PROG_ERROR; - } - - /* check Program Error, SR.4 */ - if (code & BIT_PROGRAM_ERROR) { - puts ("Program error\n"); - return ERR_PROG_ERROR; - } - - /* check Block Erase Suspended, SR.6 */ - if (code & BIT_ERASE_SUSPEND) { - puts ("Block erase suspended\n"); - return ERR_PROG_ERROR; - } - - /* check Program Suspended, SR.2 */ - if (code & BIT_PROGRAM_SUSPEND) { - puts ("Program suspended\n"); - return ERR_PROG_ERROR; - } - - /* OK, no error */ - return ERR_OK; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - ulong result, result1; - int iflag, prot, sect; - int rc = ERR_OK; - ulong start; - -#ifdef USE_920T_MMU - int cflag; -#endif - - debug ("flash_erase: s_first %d s_last %d\n", s_first, s_last); - - /* first look for protection bits */ - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (INTEL_MANUFACT & FLASH_VENDMASK)) { - return ERR_UNKNOWN_FLASH_VENDOR; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ -#ifdef USE_920T_MMU - cflag = dcache_status (); - dcache_disable (); -#endif - iflag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { - - debug ("Erasing sector %2d @ %08lX... ", - sect, info->start[sect]); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - if (info->protect[sect] == 0) { /* not protected */ - vu_long *addr = (vu_long *) (info->start[sect]); - ulong bsR7, bsR7_2, bsR5, bsR5_2; - - /* *addr = CMD_STATUS_RESET; */ - *addr = CMD_ERASE_SETUP; - *addr = CMD_ERASE_CONFIRM; - - /* wait until flash is ready */ - do { - /* check timeout */ - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { - *addr = CMD_STATUS_RESET; - result = BIT_TIMEOUT; - break; - } - - *addr = CMD_STATUS_READ; - result = *addr; - bsR7 = result & (1 << 7); - bsR7_2 = result & (1 << 23); - } while (!bsR7 | !bsR7_2); - - *addr = CMD_STATUS_READ; - result1 = *addr; - bsR5 = result1 & (1 << 5); - bsR5_2 = result1 & (1 << 21); -#ifdef SAMSUNG_FLASH_DEBUG - printf ("bsR5 %lx bsR5_2 %lx\n", bsR5, bsR5_2); - if (bsR5 != 0 && bsR5_2 != 0) - printf ("bsR5 %lx bsR5_2 %lx\n", bsR5, bsR5_2); -#endif - - *addr = CMD_READ_ARRAY; - *addr = CMD_RESUME; - - if ((rc = flash_error (result)) != ERR_OK) - goto outahere; -#if 0 - printf ("ok.\n"); - } else { /* it was protected */ - - printf ("protected!\n"); -#endif - } - } - -outahere: - /* allow flash to settle - wait 10 ms */ - udelay_masked (10000); - - if (iflag) - enable_interrupts (); - -#ifdef USE_920T_MMU - if (cflag) - dcache_enable (); -#endif - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash - */ - -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *) dest; - ulong result; - int rc = ERR_OK; - int iflag; - ulong start; - -#ifdef USE_920T_MMU - int cflag; -#endif - - /* - * Check if Flash is (sufficiently) erased - */ - result = *addr; - if ((result & data) != data) - return ERR_NOT_ERASED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ -#ifdef USE_920T_MMU - cflag = dcache_status (); - dcache_disable (); -#endif - iflag = disable_interrupts (); - - /* *addr = CMD_STATUS_RESET; */ - *addr = CMD_PROGRAM; - *addr = data; - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait until flash is ready */ - do { - /* check timeout */ - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { - *addr = CMD_SUSPEND; - result = BIT_TIMEOUT; - break; - } - - *addr = CMD_STATUS_READ; - result = *addr; - } while (~result & BIT_BUSY); - - /* *addr = CMD_READ_ARRAY; */ - *addr = CMD_STATUS_READ; - result = *addr; - - rc = flash_error (result); - - if (iflag) - enable_interrupts (); - -#ifdef USE_920T_MMU - if (cflag) - dcache_enable (); -#endif - *addr = CMD_READ_ARRAY; - *addr = CMD_RESUME; - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash. - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int l; - int i, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 24); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data >> 8) | (*src++ << 24); - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 24); - } - - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = *((vu_long *) src); - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - src += 4; - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return ERR_OK; - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 24); - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 24); - } - - return write_word (info, wp, data); -} diff --git a/board/lpd7a40x/lowlevel_init.S b/board/lpd7a40x/lowlevel_init.S deleted file mode 100644 index de34fc6f04..0000000000 --- a/board/lpd7a40x/lowlevel_init.S +++ /dev/null @@ -1,212 +0,0 @@ -/* - * Memory Setup - initialize memory controller(s) for devices required - * to boot and relocate - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include <config.h> -#include <version.h> - - -/* memory controller */ -#define BCRX_DEFAULT (0x0000fbe0) -#define BCRX_MW_8 (0x00000000) -#define BCRX_MW_16 (0x10000000) -#define BCRX_MW_32 (0x20000000) -#define BCRX_PME (0x08000000) -#define BCRX_WP (0x04000000) -#define BCRX_WST2_SHIFT (11) -#define BCRX_WST1_SHIFT (5) -#define BCRX_IDCY_SHIFT (0) - -/* Bank0 Async Flash */ -#define BCR0 (0x80002000) -#define BCR0_FLASH (BCRX_MW_32 | (0x08<<BCRX_WST2_SHIFT) | (0x0E<<BCRX_WST1_SHIFT)) - -/* Bank1 Open */ -#define BCR1 (0x80002004) - -/* Bank2 Not used (EEPROM?) */ -#define BCR2 (0x80002008) - -/* Bank3 Not used */ -#define BCR3 (0x8000200C) - -/* Bank4 PC Card1 */ - -/* Bank5 PC Card2 */ - -/* Bank6 CPLD IO Controller Peripherals (slow) */ -#define BCR6 (0x80002018) -#define BCR6_CPLD_SLOW (BCRX_DEFAULT | BCRX_MW_16) - -/* Bank7 CPLD IO Controller Peripherals (fast) */ -#define BCR7 (0x8000201C) -#define BCR7_CPLD_FAST (BCRX_MW_16 | (0x16<<BCRX_WST2_SHIFT) | (0x16<<BCRX_WST1_SHIFT) | (0x2<<BCRX_IDCY_SHIFT)) - -/* SDRAM */ -#define GBLCNFG (0x80002404) -#define GC_CKE (0x80000000) -#define GC_CKSD (0x40000000) -#define GC_LCR (0x00000040) -#define GC_SMEMBURST (0x00000020) -#define GC_MRS (0x00000002) -#define GC_INIT (0x00000001) - -#define GC_CMD_NORMAL (GC_CKE) -#define GC_CMD_MODE (GC_CKE | GC_MRS) -#define GC_CMD_SYNCFLASH_LOAD (GC_CKE | GC_MRS | GC_LCR) -#define GC_CMD_PRECHARGEALL (GC_CKE | GC_INIT) -#define GC_CMD_NOP (GC_CKE | GC_INIT | GC_MRS) - -#define RFSHTMR (0x80002408) -#define RFSHTMR_INIT (10) /* period=100 ns, HCLK=100Mhz, (2048+1-15.6*66) */ -#define RFSHTMR_NORMAL (1500) /* period=15.6 us, HCLK=100Mhz, (2048+1-15.6*66) */ - -#define SDCSCX_BASE (0x80002410) -#define SDCSCX_DEFAULT (0x01220008) -#define SDCSCX_AUTOPC (0x01000000) -#define SDCSCX_RAS2CAS_2 (0x00200000) -#define SDCSCX_RAS2CAS_3 (0x00300000) -#define SDCSCX_WBL (0x00080000) -#define SDCSCX_CASLAT_8 (0x00070000) -#define SDCSCX_CASLAT_7 (0x00060000) -#define SDCSCX_CASLAT_6 (0x00050000) -#define SDCSCX_CASLAT_5 (0x00040000) -#define SDCSCX_CASLAT_4 (0x00030000) -#define SDCSCX_CASLAT_3 (0x00020000) -#define SDCSCX_CASLAT_2 (0x00010000) -#define SDCSCX_2KPAGE (0x00000040) -#define SDCSCX_SROMLL (0x00000020) -#define SDCSCX_SROM512 (0x00000010) -#define SDCSCX_4BNK (0x00000008) -#define SDCSCX_2BNK (0x00000000) -#define SDCSCX_EBW_16 (0x00000004) -#define SDCSCX_EBW_32 (0x00000000) - -#define SDRAM_BASE (0xC0000000) -#define SDCSC_BANK_OFFSET (0x10000000) - -/* - * The SDRAM DEVICE MODE PROGRAMMING VALUE - */ -#define BURST_LENGTH_4 (2 << 10) -#define BURST_LENGTH_8 (3 << 10) -#define WBURST_LENGTH_BL (0 << 19) -#define WBURST_LENGTH_SINGLE (1 << 19) -#define CAS_2 (2 << 14) -#define CAS_3 (3 << 14) -#define BAT_SEQUENTIAL (0 << 13) -#define BAT_INTERLEAVED (1 << 13) -#define OPM_NORMAL (0 << 17) -#define SDRAM_DEVICE_MODE (WBURST_LENGTH_BL|OPM_NORMAL|CAS_3|BAT_SEQUENTIAL|BURST_LENGTH_4) - - -#define TIMER1_BASE (0x80000C00) - -/* - * special lookup flags - */ -#define DO_MEM_DELAY 1 -#define DO_MEM_READ 2 - -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE - -.globl lowlevel_init -lowlevel_init: - mov r9, lr @ save return address - - /* memory control configuration */ - /* make r0 relative the current location so that it */ - /* reads INITMEM_DATA out of FLASH rather than memory ! */ - /* r0 = current word pointer */ - /* r1 = end word location, one word past last actual word */ - /* r3 = address for writes, special lookup flags */ - /* r4 = value for writes, delay constants, or read addresses */ - /* r2 = location for mem reads */ - - ldr r0, =INITMEM_DATA - ldr r1, _TEXT_BASE - sub r0, r0, r1 - add r1, r0, #112 - -mem_loop: - cmp r1, r0 - moveq pc, r9 @ Done - - ldr r3, [r0], #4 @ Fetch Destination Register Address, or 1 for delay - ldr r4, [r0], #4 @ value - - cmp r3, #DO_MEM_DELAY - bleq mem_delay - beq mem_loop - cmp r3, #DO_MEM_READ - ldreq r2, [r4] - beq mem_loop - str r4, [r3] @ normal register/ram store - b mem_loop - -mem_delay: - ldr r5, =TIMER1_BASE - mov r6, r4, LSR #1 @ timer resolution is ~2us - str r6, [r5] - mov r6, #0x88 @ using 508.469KHz clock, enable - str r6, [r5, #8] -0: ldr r6, [r5, #4] @ timer value - cmp r6, #0 - bne 0b - mov r6, #0 @ disable timer - str r6, [r5, #8] - mov pc, lr - - .ltorg -/* the literal pools origin */ - -INITMEM_DATA: - .word BCR0 - .word BCR0_FLASH - .word BCR6 - .word BCR6_CPLD_SLOW - .word BCR7 - .word BCR7_CPLD_FAST - .word SDCSCX_BASE - .word (SDCSCX_RAS2CAS_3 | SDCSCX_CASLAT_3 | SDCSCX_SROMLL | SDCSCX_4BNK | SDCSCX_EBW_32) - .word GBLCNFG - .word GC_CMD_NOP - .word DO_MEM_DELAY - .word 200 - .word GBLCNFG - .word GC_CMD_PRECHARGEALL - .word RFSHTMR - .word RFSHTMR_INIT - .word DO_MEM_DELAY - .word 8 - .word RFSHTMR - .word RFSHTMR_NORMAL - .word GBLCNFG - .word GC_CMD_MODE - .word DO_MEM_READ - .word (SDRAM_BASE | SDRAM_DEVICE_MODE) - .word GBLCNFG - .word GC_CMD_NORMAL - .word SDCSCX_BASE - .word (SDCSCX_AUTOPC | SDCSCX_RAS2CAS_3 | SDCSCX_CASLAT_3 | SDCSCX_SROMLL | SDCSCX_4BNK | SDCSCX_EBW_32) diff --git a/board/lpd7a40x/lpd7a40x.c b/board/lpd7a40x/lpd7a40x.c deleted file mode 100644 index 437dad0388..0000000000 --- a/board/lpd7a40x/lpd7a40x.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <netdev.h> -#if defined(CONFIG_LH7A400) -#include <lh7a400.h> -#elif defined(CONFIG_LH7A404) -#include <lh7a404.h> -#else -#error "No CPU defined!" -#endif -#include <asm/mach-types.h> - -#include <lpd7a400_cpld.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Miscellaneous platform dependent initialisations - */ - -int board_init (void) -{ - /* set up the I/O ports */ - - /* enable flash programming */ - *(LPD7A400_CPLD_REGPTR(LPD7A400_CPLD_FLASH_REG)) |= FLASH_FPEN; - - /* Auto wakeup, LCD disable, WLAN enable */ - *(LPD7A400_CPLD_REGPTR(LPD7A400_CPLD_CECTL_REG)) &= - ~(CECTL_AWKP|CECTL_LCDV|CECTL_WLPE); - - /* Status LED 2 on (leds are active low) */ - *(LPD7A400_CPLD_REGPTR(LPD7A400_CPLD_EXTGPIO_REG)) = - (EXTGPIO_STATUS1|EXTGPIO_GPIO1) & ~(EXTGPIO_STATUS2); - -#if defined(CONFIG_LH7A400) - /* arch number of Logic-Board - MACH_TYPE_LPD7A400 */ - gd->bd->bi_arch_number = MACH_TYPE_LPD7A400; -#elif defined(CONFIG_LH7A404) - /* arch number of Logic-Board - MACH_TYPE_LPD7A400 */ - gd->bd->bi_arch_number = MACH_TYPE_LPD7A404; -#endif - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0xc0000100; - - return 0; -} - -int dram_init (void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return 0; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC91111 - rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); -#endif - return rc; -} -#endif diff --git a/board/lubbock/flash.c b/board/lubbock/flash.c index 1ea2893fd0..e1e7807bc1 100644 --- a/board/lubbock/flash.c +++ b/board/lubbock/flash.c @@ -408,7 +408,7 @@ static int write_data (flash_info_t *info, ulong dest, FPW data) /* wait while polling the status register */ while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer(start)) > CONFIG_SYS_FLASH_WRITE_TOUT) { + if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { *addr = (FPW) 0x00FF00FF; /* restore read mode */ return (1); } diff --git a/board/m501sk/Makefile b/board/m501sk/Makefile deleted file mode 100644 index 439e99f673..0000000000 --- a/board/m501sk/Makefile +++ /dev/null @@ -1,50 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := m501sk.o eeprom.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/m501sk/config.mk b/board/m501sk/config.mk deleted file mode 100644 index 207769233e..0000000000 --- a/board/m501sk/config.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x21f00000 diff --git a/board/m501sk/eeprom.c b/board/m501sk/eeprom.c deleted file mode 100644 index d1a46f348b..0000000000 --- a/board/m501sk/eeprom.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Add by Alan Lu, 07-29-2005 - * For ATMEL AT24C16 EEPROM - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <i2c.h> -#ifdef CONFIG_SYS_EEPROM_AT24C16 -#undef DEBUG - -void eeprom_init(void) -{ -#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) - i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); -#endif -} - -int eeprom_read(unsigned dev_addr, unsigned offset, uchar *buffer, - unsigned cnt) -{ - int page, count = 0, i = 0; - page = offset / 0x100; - i = offset % 0x100; - - while (count < cnt) { - if (i2c_read(dev_addr|page, i++, 1, buffer+count++, 1) != 0) - return 1; - if (i > 0xff) { - page++; - i = 0; - } - } - - return 0; -} - -/* - * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is - * 0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM. - * - * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is - * 0x00000nxx for EEPROM address selectors and page number at n. - */ -int eeprom_write(unsigned dev_addr, unsigned offset, uchar *buffer, - unsigned cnt) -{ - int page, i = 0, count = 0; - - page = offset / 0x100; - i = offset % 0x100; - - while (count < cnt) { - if (i2c_write(dev_addr|page, i++, 1, buffer+count++, 1) != 0) - return 1; - if (i > 0xff) { - page++; - i = 0; - } - } - -#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS) - udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000); -#endif - - return 0; -} - -#ifndef CONFIG_SPI -int eeprom_probe(unsigned dev_addr, unsigned offset) -{ - unsigned char chip; - - /* Probe the chip address */ -#if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X) - chip = offset >> 8; /* block number */ -#else - chip = offset >> 16; /* block number */ -#endif /* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */ - - chip |= dev_addr; /* insert device address */ - return (i2c_probe(chip)); -} -#endif -#endif diff --git a/board/m501sk/m501sk.c b/board/m501sk/m501sk.c deleted file mode 100644 index c9957684b1..0000000000 --- a/board/m501sk/m501sk.c +++ /dev/null @@ -1,203 +0,0 @@ -/* - * (C) Copyright 2008 - * Based on modifications by Alan Lu / Artila - * Author : Timo Tuunainen / Sysart - Kimmo Leppala / Sysart - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/io.h> -#include <netdev.h> -#if defined(CONFIG_DRIVER_ETHER) -#include <at91rm9200_net.h> -#include <dm9161.h> -#endif - -#include "m501sk.h" -#include "net.h" - -#ifdef CONFIG_M501SK - -void m501sk_gpio_init(void) -{ - AT91C_BASE_PIOD->PIO_PER = 1 << (M501SK_DEBUG_LED1 - 96) | - 1 << (M501SK_DEBUG_LED2 - 96) | 1 << (M501SK_DEBUG_LED3 - 96) | - 1 << (M501SK_DEBUG_LED4 - 96) | 1 << (M501SK_READY_LED - 96); - - AT91C_BASE_PIOD->PIO_OER = 1 << (M501SK_DEBUG_LED1 - 96) | - 1 << (M501SK_DEBUG_LED2 - 96) | 1 << (M501SK_DEBUG_LED3 - 96) | - 1 << (M501SK_DEBUG_LED4 - 96) | 1 << (M501SK_READY_LED - 96); - - AT91C_BASE_PIOD->PIO_SODR = 1 << (M501SK_READY_LED - 96); - AT91C_BASE_PIOD->PIO_CODR = 1 << (M501SK_DEBUG_LED3 - 96); - AT91C_BASE_PIOB->PIO_PER = 1 << (M501SK_BUZZER - 32); - AT91C_BASE_PIOB->PIO_OER = 1 << (M501SK_BUZZER - 32); - AT91C_BASE_PIOC->PIO_PDR = (1 << 7) | (1 << 8); - - /* Power OFF all USART's LEDs */ - AT91C_BASE_PIOA->PIO_PER = AT91C_PA5_TXD3 | AT91C_PA6_RXD3 | - AT91C_PA17_TXD0 | AT91C_PA18_RXD0 | AT91C_PA22_RXD2 | \ - AT91C_PA23_TXD2; - - AT91C_BASE_PIOA->PIO_OER = AT91C_PA5_TXD3 | AT91C_PA6_RXD3 | - AT91C_PA17_TXD0 | AT91C_PA18_RXD0 | AT91C_PA22_RXD2 | \ - AT91C_PA23_TXD2; - - AT91C_BASE_PIOA->PIO_SODR = AT91C_PA5_TXD3 | AT91C_PA6_RXD3 | - AT91C_PA17_TXD0 | AT91C_PA18_RXD0 | AT91C_PA22_RXD2 | \ - AT91C_PA23_TXD2; - - AT91C_BASE_PIOB->PIO_PER = AT91C_PB20_RXD1 | AT91C_PB21_TXD1; - AT91C_BASE_PIOB->PIO_OER = AT91C_PB20_RXD1 | AT91C_PB21_TXD1; - AT91C_BASE_PIOB->PIO_SODR = AT91C_PB20_RXD1 | AT91C_PB21_TXD1; -} - -uchar m501sk_gpio_set(M501SK_PIO io) -{ - uchar status = 0xff; - switch (io) { - case M501SK_DEBUG_LED1: - case M501SK_DEBUG_LED2: - case M501SK_DEBUG_LED3: - case M501SK_DEBUG_LED4: - case M501SK_READY_LED: - AT91C_BASE_PIOD->PIO_SODR = 1 << (io - 96); - status = AT91C_BASE_PIOD->PIO_ODSR & (1 << (io - 96)); - break; - case M501SK_BUZZER: - AT91C_BASE_PIOB->PIO_SODR = 1 << (io - 32); - status = AT91C_BASE_PIOB->PIO_ODSR & (1 << (io - 32)); - break; - } - return status; -} - -uchar m501sk_gpio_clear(M501SK_PIO io) -{ - uchar status = 0xff; - switch (io) { - case M501SK_DEBUG_LED1: - case M501SK_DEBUG_LED2: - case M501SK_DEBUG_LED3: - case M501SK_DEBUG_LED4: - case M501SK_READY_LED: - AT91C_BASE_PIOD->PIO_CODR = 1 << (io - 96); - status = AT91C_BASE_PIOD->PIO_ODSR & (1 << (io - 96)); - break; - case M501SK_BUZZER: - AT91C_BASE_PIOB->PIO_CODR = 1 << (io - 32); - status = AT91C_BASE_PIOB->PIO_ODSR & (1 << (io - 32)); - break; - } - return status; -} - -/* - * Miscelaneous platform dependent initialisations - */ -DECLARE_GLOBAL_DATA_PTR; - -int board_init(void) -{ - /* Enable Ctrlc */ - console_init_f(); - - /* Correct IRDA resistor problem */ - /* Set PA23_TXD in Output */ - ((AT91PS_PIO)AT91C_BASE_PIOA)->PIO_OER = AT91C_PA23_TXD2; - - /* memory and cpu-speed are setup before relocation */ - /* so we do _nothing_ here */ - gd->bd->bi_arch_number = MACH_TYPE_M501; - /* adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - m501sk_gpio_init(); - - /* Do interrupt init here, because flash needs timers */ - timer_init(); - flash_init(); - - return 0; -} - -int dram_init(void) -{ - int i = 0; - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; - - for (i = 0; i < 500; i++) { - m501sk_gpio_clear(M501SK_DEBUG_LED3); - m501sk_gpio_clear(M501SK_BUZZER); - udelay(250); - m501sk_gpio_set(M501SK_DEBUG_LED3); - m501sk_gpio_set(M501SK_BUZZER); - udelay(80); - } - m501sk_gpio_clear(M501SK_BUZZER); - m501sk_gpio_clear(M501SK_DEBUG_LED3); - - return 0; -} - -int board_late_init(void) -{ -#if defined(CONFIG_CMD_NET) - eth_init(gd->bd); - eth_halt(); -#endif - - /* Protect U-Boot, kernel & ramdisk memory addresses */ - run_command("protect on 10000000 1041ffff", 0); - return 0; -} - -#ifdef CONFIG_DRIVER_ETHER -#if defined(CONFIG_CMD_NET) -/* - * Name: - * at91rm9200_GetPhyInterface - * Description: - * Initialise the interface functions to the PHY - * Arguments: - * None - * Return value: - * None - */ -void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops) -{ - p_phyops->Init = dm9161_InitPhy; - p_phyops->IsPhyConnected = dm9161_IsPhyConnected; - p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed; - p_phyops->AutoNegotiate = dm9161_AutoNegotiate; -} -#endif /* CONFIG_CMD_NET */ -#endif /* CONFIG_DRIVER_ETHER */ - -#ifdef CONFIG_DRIVER_AT91EMAC -int board_eth_init(bd_t *bis) -{ - int rc = 0; - rc = at91emac_register(bis, 0); - return rc; -} -#endif -#endif /* CONFIG_M501SK */ diff --git a/board/m501sk/m501sk.h b/board/m501sk/m501sk.h deleted file mode 100644 index 51d10f58a9..0000000000 --- a/board/m501sk/m501sk.h +++ /dev/null @@ -1,167 +0,0 @@ -/* - * linux/include/asm/arch-at91/hardware.h - * - * Copyright (C) 2003 SAN People - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#ifndef __M501SK_H -#define __M501SK_H - -#ifndef __ASSEMBLY__ -#include <asm/arch-at91rm9200/AT91RM9200.h> -#else -#include <asm/arch-at91rm9200/AT91RM9200_inc.h> -#endif - -#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) /* Pin Controlled by PA22 */ -#define AT91C_PA22_RXD2 ((unsigned int) AT91C_PIO_PA22) /* USART 2 RxD */ -#define AT91C_PA5_TXD3 ((unsigned int) 1 << 5) /* USART 3 TxD */ -#define AT91C_PA6_RXD3 ((unsigned int) 1 << 6) /* USART 3 RxD */ - -/* ========== Register definition for PIOD peripheral ========== */ -#define AT91C_PIOD_PDSR ((AT91_REG *) 0xFFFFFA3C) /* Pin Data stat Reg */ -#define AT91C_PIOD_CODR ((AT91_REG *) 0xFFFFFA34) /* Clear Output Data Reg */ -#define AT91C_PIOD_OWER ((AT91_REG *) 0xFFFFFAA0) /* Output Write Enable Reg */ -#define AT91C_PIOD_MDER ((AT91_REG *) 0xFFFFFA50) /* Multi-driver Enable Reg */ -#define AT91C_PIOD_IMR ((AT91_REG *) 0xFFFFFA48) /* Interrupt Mask Reg */ -#define AT91C_PIOD_IER ((AT91_REG *) 0xFFFFFA40) /* Interrupt Enable Reg */ -#define AT91C_PIOD_ODSR ((AT91_REG *) 0xFFFFFA38) /* Output Data stat Reg */ -#define AT91C_PIOD_SODR ((AT91_REG *) 0xFFFFFA30) /* Set Output Data Reg */ -#define AT91C_PIOD_PER ((AT91_REG *) 0xFFFFFA00) /* PIO Enable Reg */ -#define AT91C_PIOD_OWDR ((AT91_REG *) 0xFFFFFAA4) /* Output Write Disable Reg */ -#define AT91C_PIOD_PPUER ((AT91_REG *) 0xFFFFFA64) /* Pull-up Enable Reg */ -#define AT91C_PIOD_MDDR ((AT91_REG *) 0xFFFFFA54) /* Multi-driver Disable Reg */ -#define AT91C_PIOD_ISR ((AT91_REG *) 0xFFFFFA4C) /* Interrupt stat Reg */ -#define AT91C_PIOD_IDR ((AT91_REG *) 0xFFFFFA44) /* Interrupt Disable Reg */ -#define AT91C_PIOD_PDR ((AT91_REG *) 0xFFFFFA04) /* PIO Disable Reg */ -#define AT91C_PIOD_ODR ((AT91_REG *) 0xFFFFFA14) /* Output Disable Regr */ -#define AT91C_PIOD_OWSR ((AT91_REG *) 0xFFFFFAA8) /* Output Write stat Reg */ -#define AT91C_PIOD_ABSR ((AT91_REG *) 0xFFFFFA78) /* AB Select stat Reg */ -#define AT91C_PIOD_ASR ((AT91_REG *) 0xFFFFFA70) /* Select A Reg */ -#define AT91C_PIOD_PPUSR ((AT91_REG *) 0xFFFFFA68) /* Pad Pull-up stat Reg */ -#define AT91C_PIOD_PPUDR ((AT91_REG *) 0xFFFFFA60) /* Pull-up Disable Reg */ -#define AT91C_PIOD_MDSR ((AT91_REG *) 0xFFFFFA58) /* Multi-driver stat Reg */ -#define AT91C_PIOD_PSR ((AT91_REG *) 0xFFFFFA08) /* PIO stat Reg */ -#define AT91C_PIOD_OER ((AT91_REG *) 0xFFFFFA10) /* Output Enable Reg */ -#define AT91C_PIOD_OSR ((AT91_REG *) 0xFFFFFA18) /* Output stat Reg */ -#define AT91C_PIOD_IFER ((AT91_REG *) 0xFFFFFA20) /* Input Filter Enable Reg */ -#define AT91C_PIOD_BSR ((AT91_REG *) 0xFFFFFA74) /* Select B Reg */ -#define AT91C_PIOD_IFDR ((AT91_REG *) 0xFFFFFA24) /* Input Filter Disable Reg */ -#define AT91C_PIOD_IFSR ((AT91_REG *) 0xFFFFFA28) /* Input Filter stat Reg */ - -#define AT91C_PIO_PD0 ((unsigned int) 1 << 0) /* Pin Controlled by PD0 */ -#define AT91C_PD0_ETX0 ((unsigned int) AT91C_PIO_PD0) /* Enet MAC Tx Data 0*/ -#define AT91C_PIO_PD1 ((unsigned int) 1 << 1) /* Pin Controlled by PD1 */ -#define AT91C_PD1_ETX1 ((unsigned int) AT91C_PIO_PD1) /* Enet MAC Tx Data 1*/ -#define AT91C_PIO_PD10 ((unsigned int) 1 << 10) /* Pin Controlled by PD10 */ -#define AT91C_PD10_PCK3 ((unsigned int) AT91C_PIO_PD10) /* PMC Prog Clk Oput 3*/ -#define AT91C_PD10_TPS1 ((unsigned int) AT91C_PIO_PD10) /* ETMARM9 pl stat1 */ -#define AT91C_PIO_PD11 ((unsigned int) 1 << 11) /* Pin Controlled by PD11 */ -#define AT91C_PD11_ ((unsigned int) AT91C_PIO_PD11) /* */ -#define AT91C_PD11_TPS2 ((unsigned int) AT91C_PIO_PD11) /* ETMARM9 pl stat2 */ -#define AT91C_PIO_PD12 ((unsigned int) 1 << 12) /* Pin Controlled by PD12 */ -#define AT91C_PD12_ ((unsigned int) AT91C_PIO_PD12) /* */ -#define AT91C_PD12_TPK0 ((unsigned int) AT91C_PIO_PD12) /* ETM Trace Pkt 0 */ -#define AT91C_PIO_PD13 ((unsigned int) 1 << 13) /* Pin Controlled by PD13 */ -#define AT91C_PD13_ ((unsigned int) AT91C_PIO_PD13) /* */ -#define AT91C_PD13_TPK1 ((unsigned int) AT91C_PIO_PD13) /* ETM Trace Pkt 1 */ -#define AT91C_PIO_PD14 ((unsigned int) 1 << 14) /* Pin Controlled by PD14 */ -#define AT91C_PD14_ ((unsigned int) AT91C_PIO_PD14) /* */ -#define AT91C_PD14_TPK2 ((unsigned int) AT91C_PIO_PD14) /* ETM Trace Pkt 2 */ -#define AT91C_PIO_PD15 ((unsigned int) 1 << 15) /* Pin Controlled by PD15 */ -#define AT91C_PD15_TD0 ((unsigned int) AT91C_PIO_PD15) /* SSC TxD */ -#define AT91C_PD15_TPK3 ((unsigned int) AT91C_PIO_PD15) /* ETM Trace Pkt 3 */ -#define AT91C_PIO_PD16 ((unsigned int) 1 << 16) /* Pin Controlled by PD16 */ -#define AT91C_PD16_TD1 ((unsigned int) AT91C_PIO_PD16) /* SSC TxD 1 */ -#define AT91C_PD16_TPK4 ((unsigned int) AT91C_PIO_PD16) /* ETM Trace Pkt 4 */ -#define AT91C_PIO_PD17 ((unsigned int) 1 << 17) /* Pin Controlled by PD17 */ -#define AT91C_PD17_TD2 ((unsigned int) AT91C_PIO_PD17) /* SSC TxD 2 */ -#define AT91C_PD17_TPK5 ((unsigned int) AT91C_PIO_PD17) /* ETM Trace Pkt 5 */ -#define AT91C_PIO_PD18 ((unsigned int) 1 << 18) /* Pin Controlled by PD18 */ -#define AT91C_PD18_NPCS1 ((unsigned int) AT91C_PIO_PD18) /* SPI Perip CS 1 */ -#define AT91C_PD18_TPK6 ((unsigned int) AT91C_PIO_PD18) /* ETM Trace Pkt 6 */ -#define AT91C_PIO_PD19 ((unsigned int) 1 << 19) /* Pin Controlled by PD19 */ -#define AT91C_PD19_NPCS2 ((unsigned int) AT91C_PIO_PD19) /* SPI Perip CS 2 */ -#define AT91C_PD19_TPK7 ((unsigned int) AT91C_PIO_PD19) /* ETM Trace Pkt 7 */ -#define AT91C_PIO_PD2 ((unsigned int) 1 << 2) /* Pin Controlled by PD2 */ -#define AT91C_PD2_ETX2 ((unsigned int) AT91C_PIO_PD2) /* Ethernet MAC TxD 2 */ -#define AT91C_PIO_PD20 ((unsigned int) 1 << 20) /* Pin Controlled by PD20 */ -#define AT91C_PD20_NPCS3 ((unsigned int) AT91C_PIO_PD20) /* SPI Perip CS 3 */ -#define AT91C_PD20_TPK8 ((unsigned int) AT91C_PIO_PD20) /* ETM Trace Pkt 8 */ -#define AT91C_PIO_PD21 ((unsigned int) 1 << 21) /* Pin Controlled by PD21 */ -#define AT91C_PD21_RTS0 ((unsigned int) AT91C_PIO_PD21) /* Usart 0 RTS */ -#define AT91C_PD21_TPK9 ((unsigned int) AT91C_PIO_PD21) /* ETM Trace Pkt 9 */ -#define AT91C_PIO_PD22 ((unsigned int) 1 << 22) /* Pin Controlled by PD22 */ -#define AT91C_PD22_RTS1 ((unsigned int) AT91C_PIO_PD22) /* Usart 0 RTS */ -#define AT91C_PD22_TPK10 ((unsigned int) AT91C_PIO_PD22) /* ETM Trace Pkt 10 */ -#define AT91C_PIO_PD23 ((unsigned int) 1 << 23) /* Pin Controlled by PD23 */ -#define AT91C_PD23_RTS2 ((unsigned int) AT91C_PIO_PD23) /* USART 2 RTS */ -#define AT91C_PD23_TPK11 ((unsigned int) AT91C_PIO_PD23) /* ETM Trace Pkt 11 */ -#define AT91C_PIO_PD24 ((unsigned int) 1 << 24) /* Pin Controlled by PD24 */ -#define AT91C_PD24_RTS3 ((unsigned int) AT91C_PIO_PD24) /* USART 3 RTS */ -#define AT91C_PD24_TPK12 ((unsigned int) AT91C_PIO_PD24) /* ETM Trace Pkt 12 */ -#define AT91C_PIO_PD25 ((unsigned int) 1 << 25) /* Pin Controlled by PD25 */ -#define AT91C_PD25_DTR1 ((unsigned int) AT91C_PIO_PD25) /* USART 1 DTR */ -#define AT91C_PD25_TPK13 ((unsigned int) AT91C_PIO_PD25) /* ETM Trace Pkt 13 */ -#define AT91C_PIO_PD26 ((unsigned int) 1 << 26) /* Pin Controlled by PD26 */ -#define AT91C_PD26_TPK14 ((unsigned int) AT91C_PIO_PD26) /* ETM Trace Pkt 14 */ -#define AT91C_PIO_PD27 ((unsigned int) 1 << 27) /* Pin Controlled by PD27 */ -#define AT91C_PD27_TPK15 ((unsigned int) AT91C_PIO_PD27) /* ETM Trace Pkt 15 */ -#define AT91C_PIO_PD3 ((unsigned int) 1 << 3) /* Pin Controlled by PD3 */ -#define AT91C_PD3_ETX3 ((unsigned int) AT91C_PIO_PD3) /* Enet MAC TxD 3 */ -#define AT91C_PIO_PD4 ((unsigned int) 1 << 4) /* Pin Controlled by PD4 */ -#define AT91C_PD4_ETXEN ((unsigned int) AT91C_PIO_PD4) /* Enet MAC TxEn */ -#define AT91C_PIO_PD5 ((unsigned int) 1 << 5) /* Pin Controlled by PD5 */ -#define AT91C_PD5_ETXER ((unsigned int) AT91C_PIO_PD5) /* Enet MAC TxCE */ -#define AT91C_PIO_PD6 ((unsigned int) 1 << 6) /* Pin Controlled by PD6 */ -#define AT91C_PD6_DTXD ((unsigned int) AT91C_PIO_PD6) /* DBGU Debug TxD */ -#define AT91C_PIO_PD7 ((unsigned int) 1 << 7) /* Pin Controlled by PD7 */ -#define AT91C_PD7_PCK0 ((unsigned int) AT91C_PIO_PD7) /* PMC Prog Clk Oput 0*/ -#define AT91C_PD7_TSYNC ((unsigned int) AT91C_PIO_PD7) /* ETM Sync signal */ -#define AT91C_PIO_PD8 ((unsigned int) 1 << 8) /* Pin Controlled by PD8 */ -#define AT91C_PD8_PCK1 ((unsigned int) AT91C_PIO_PD8) /* PMC Prog Clk Oput 1*/ -#define AT91C_PD8_TCLK ((unsigned int) AT91C_PIO_PD8) /* ETM Trace Clk sig */ -#define AT91C_PIO_PD9 ((unsigned int) 1 << 9) /* Pin Controlled by PD9 */ -#define AT91C_PD9_PCK2 ((unsigned int) AT91C_PIO_PD9) /* PMC Prog Clk 2 */ -#define AT91C_PD9_TPS0 ((unsigned int) AT91C_PIO_PD9) /* ETM ARM9 pl stat0 */ -#define AT91C_PIO_PB6 ((unsigned int) 1 << 6) /* Pin Controlled by PB6 */ -#define AT91C_PIO_PC5 ((unsigned int) 1 << 5) -#define AT91C_PIO_PC14 ((unsigned int) 1 << 14) /* Pin Controlled by PC1 */ -#define AT91C_PIO_PC15 ((unsigned int) 1 << 15) /* Pin Controlled by PC1 */ -#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) /* Pin Controlled by PC1 */ -#define AT91C_PIO_PB2 ((unsigned int) 1 << 2) /* Pin Controlled by PC1 */ -#define AT91C_PIO_PB8 ((unsigned int) 1 << 8) -#define AT91C_PIO_PB9 ((unsigned int) 1 << 9) -#define AT91C_PIO_PB10 ((unsigned int) 1 << 10) -#define AT91C_PIO_PB11 ((unsigned int) 1 << 11) -#define AT91C_PIO_PB17 ((unsigned int) 1 << 17) -#define AT91C_PIO_PB28 ((unsigned int) 1 << 28) -#define AT91C_PIO_PB29 ((unsigned int) 1 << 29) - -typedef enum { - M501SK_BUZZER = 38, - M501SK_DEBUG_LED1 = 96, - M501SK_DEBUG_LED2, - M501SK_DEBUG_LED3, - M501SK_DEBUG_LED4, - M501SK_READY_LED = 102, -} M501SK_PIO; - -void m501sk_gpio_init(void); -uchar m501sk_gpio_set(M501SK_PIO io); -uchar m501sk_gpio_clear(M501SK_PIO io); - -#endif diff --git a/board/mx1fs2/Makefile b/board/mx1fs2/Makefile deleted file mode 100644 index c55b695a51..0000000000 --- a/board/mx1fs2/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := mx1fs2.o flash.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/mx1fs2/config.mk b/board/mx1fs2/config.mk deleted file mode 100644 index eb4d046939..0000000000 --- a/board/mx1fs2/config.mk +++ /dev/null @@ -1,10 +0,0 @@ -# -# This config file is used for compilation of IMX sources -# -# You might change location of U-Boot in memory by setting right CONFIG_SYS_TEXT_BASE. -# This allows for example having one copy located at the end of ram and stored -# in flash device and later on while developing use other location to test -# the code in RAM device only. -# - -CONFIG_SYS_TEXT_BASE = 0x08f00000 diff --git a/board/mx1fs2/flash.c b/board/mx1fs2/flash.c deleted file mode 100644 index da4ebe6e75..0000000000 --- a/board/mx1fs2/flash.c +++ /dev/null @@ -1,849 +0,0 @@ -/* - * (C) 2000-2004 Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * (C) 2003 August Hoeraendl, Logotronic GmbH - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#undef CONFIG_FLASH_16BIT - -#include <common.h> - -#define FLASH_BANK_SIZE MX1FS2_FLASH_BANK_SIZE -#define MAIN_SECT_SIZE MX1FS2_FLASH_SECT_SIZE - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* - * NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it - * has nothing to do with the flash chip being 8-bit or 16-bit. - */ -#ifdef CONFIG_FLASH_16BIT -typedef unsigned short FLASH_PORT_WIDTH; -typedef volatile unsigned short FLASH_PORT_WIDTHV; - -#define FLASH_ID_MASK 0xFFFF -#else -typedef unsigned long FLASH_PORT_WIDTH; -typedef volatile unsigned long FLASH_PORT_WIDTHV; - -#define FLASH_ID_MASK 0xFFFFFFFF -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define ORMASK(size) ((-size) & OR_AM_MSK) - -/*----------------------------------------------------------------------- - * Functions - */ -#if 0 -static ulong flash_get_size(FPWV * addr, flash_info_t * info); -static void flash_get_offsets(ulong base, flash_info_t * info); -#endif -static void flash_reset(flash_info_t * info); -static int write_word_intel(flash_info_t * info, FPWV * dest, FPW data); -static int write_word_amd(flash_info_t * info, FPWV * dest, FPW data); -#define write_word(in, de, da) write_word_amd(in, de, da) -#ifdef CONFIG_SYS_FLASH_PROTECTION -static void flash_sync_real_protect(flash_info_t * info); -#endif - -/*----------------------------------------------------------------------- - * flash_init() - * - * sets up flash_info and returns size of FLASH (bytes) - */ -ulong -flash_init(void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - flash_info[i].flash_id = - (FLASH_MAN_AMD & FLASH_VENDMASK) | - (FLASH_AM640U & FLASH_TYPEMASK); - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); - switch (i) { - case 0: - flashbase = MX1FS2_FLASH_BASE; - break; - default: - panic("configured too many flash banks!\n"); - break; - } - for (j = 0; j < flash_info[i].sector_count; j++) { - flash_info[i].start[j] = flashbase + j * MAIN_SECT_SIZE; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + _bss_start - _armboot_start, - &flash_info[0]); - - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void -flash_reset(flash_info_t * info) -{ - FPWV *base = (FPWV *) (info->start[0]); - - /* Put FLASH back in read mode */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) - *base = (FPW) 0x00FF00FF; /* Intel Read Mode */ - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) - *base = (FPW) 0x00F000F0; /* AMD Read Mode */ -} - -/*----------------------------------------------------------------------- - */ -#if 0 -static void -flash_get_offsets(ulong base, flash_info_t * info) -{ - int i; - - /* set up sector start address table */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL - && (info->flash_id & FLASH_BTYPE)) { - int bootsect_size; /* number of bytes/boot sector */ - int sect_size; /* number of bytes/regular sector */ - - bootsect_size = 0x00002000 * (sizeof (FPW) / 2); - sect_size = 0x00010000 * (sizeof (FPW) / 2); - - /* set sector offsets for bottom boot block type */ - for (i = 0; i < 8; ++i) { - info->start[i] = base + (i * bootsect_size); - } - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i - 7) * sect_size); - } - } else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD - && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) { - - int sect_size; /* number of bytes/sector */ - - sect_size = 0x00010000 * (sizeof (FPW) / 2); - - /* set up sector start address table (uniform sector type) */ - for (i = 0; i < info->sector_count; i++) - info->start[i] = base + (i * sect_size); - } -} -#endif /* 0 */ - -/*----------------------------------------------------------------------- - */ - -void -flash_print_info(flash_info_t * info) -{ - int i; - uchar *boottype; - uchar *bootletter; - char *fmt; - uchar botbootletter[] = "B"; - uchar topbootletter[] = "T"; - uchar botboottype[] = "bottom boot sector"; - uchar topboottype[] = "top boot sector"; - - if (info->flash_id == FLASH_UNKNOWN) { - printf("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - printf("AMD "); - break; - case FLASH_MAN_BM: - printf("BRIGHT MICRO "); - break; - case FLASH_MAN_FUJ: - printf("FUJITSU "); - break; - case FLASH_MAN_SST: - printf("SST "); - break; - case FLASH_MAN_STM: - printf("STM "); - break; - case FLASH_MAN_INTEL: - printf("INTEL "); - break; - default: - printf("Unknown Vendor "); - break; - } - - /* check for top or bottom boot, if it applies */ - if (info->flash_id & FLASH_BTYPE) { - boottype = botboottype; - bootletter = botbootletter; - } else { - boottype = topboottype; - bootletter = topbootletter; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM640U: - fmt = "29LV641D (64 Mbit, uniform sectors)\n"; - break; - case FLASH_28F800C3B: - case FLASH_28F800C3T: - fmt = "28F800C3%s (8 Mbit, %s)\n"; - break; - case FLASH_INTEL800B: - case FLASH_INTEL800T: - fmt = "28F800B3%s (8 Mbit, %s)\n"; - break; - case FLASH_28F160C3B: - case FLASH_28F160C3T: - fmt = "28F160C3%s (16 Mbit, %s)\n"; - break; - case FLASH_INTEL160B: - case FLASH_INTEL160T: - fmt = "28F160B3%s (16 Mbit, %s)\n"; - break; - case FLASH_28F320C3B: - case FLASH_28F320C3T: - fmt = "28F320C3%s (32 Mbit, %s)\n"; - break; - case FLASH_INTEL320B: - case FLASH_INTEL320T: - fmt = "28F320B3%s (32 Mbit, %s)\n"; - break; - case FLASH_28F640C3B: - case FLASH_28F640C3T: - fmt = "28F640C3%s (64 Mbit, %s)\n"; - break; - case FLASH_INTEL640B: - case FLASH_INTEL640T: - fmt = "28F640B3%s (64 Mbit, %s)\n"; - break; - default: - fmt = "Unknown Chip Type\n"; - break; - } - - printf(fmt, bootletter, boottype); - - printf(" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf(" Sector Start Addresses:"); - - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) { - printf("\n "); - } - - printf(" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - - printf("\n"); -} - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -#if 0 -ulong -flash_get_size(FPWV * addr, flash_info_t * info) -{ - /* Write auto select command: read Manufacturer ID */ - - /* Write auto select command sequence and test FLASH answer */ - addr[0x0555] = (FPW) 0x00AA00AA; /* for AMD, Intel ignores this */ - addr[0x02AA] = (FPW) 0x00550055; /* for AMD, Intel ignores this */ - addr[0x0555] = (FPW) 0x00900090; /* selects Intel or AMD */ - - /* The manufacturer codes are only 1 byte, so just use 1 byte. - * This works for any bus width and any FLASH device width. - */ - switch (addr[0] & 0xff) { - - case (uchar) AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - - case (uchar) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; - } - - /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ - if (info->flash_id != FLASH_UNKNOWN) - switch (addr[1]) { - - case (FPW) AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */ - info->flash_id += FLASH_AM640U; - info->sector_count = 128; - info->size = 0x00800000 * (sizeof (FPW) / 2); - break; /* => 8 or 16 MB */ - - case (FPW) INTEL_ID_28F800C3B: - info->flash_id += FLASH_28F800C3B; - info->sector_count = 23; - info->size = 0x00100000 * (sizeof (FPW) / 2); - break; /* => 1 or 2 MB */ - - case (FPW) INTEL_ID_28F800B3B: - info->flash_id += FLASH_INTEL800B; - info->sector_count = 23; - info->size = 0x00100000 * (sizeof (FPW) / 2); - break; /* => 1 or 2 MB */ - - case (FPW) INTEL_ID_28F160C3B: - info->flash_id += FLASH_28F160C3B; - info->sector_count = 39; - info->size = 0x00200000 * (sizeof (FPW) / 2); - break; /* => 2 or 4 MB */ - - case (FPW) INTEL_ID_28F160B3B: - info->flash_id += FLASH_INTEL160B; - info->sector_count = 39; - info->size = 0x00200000 * (sizeof (FPW) / 2); - break; /* => 2 or 4 MB */ - - case (FPW) INTEL_ID_28F320C3B: - info->flash_id += FLASH_28F320C3B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof (FPW) / 2); - break; /* => 4 or 8 MB */ - - case (FPW) INTEL_ID_28F320B3B: - info->flash_id += FLASH_INTEL320B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof (FPW) / 2); - break; /* => 4 or 8 MB */ - - case (FPW) INTEL_ID_28F640C3B: - info->flash_id += FLASH_28F640C3B; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof (FPW) / 2); - break; /* => 8 or 16 MB */ - - case (FPW) INTEL_ID_28F640B3B: - info->flash_id += FLASH_INTEL640B; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof (FPW) / 2); - break; /* => 8 or 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* => no or unknown flash */ - } - - flash_get_offsets((ulong) addr, info); - - /* Put FLASH back in read mode */ - flash_reset(info); - - return (info->size); -} -#endif /* 0 */ - -#ifdef CONFIG_SYS_FLASH_PROTECTION -/*----------------------------------------------------------------------- - */ - -static void -flash_sync_real_protect(flash_info_t * info) -{ - FPWV *addr = (FPWV *) (info->start[0]); - FPWV *sect; - int i; - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F800C3B: - case FLASH_28F800C3T: - case FLASH_28F160C3B: - case FLASH_28F160C3T: - case FLASH_28F320C3B: - case FLASH_28F320C3T: - case FLASH_28F640C3B: - case FLASH_28F640C3T: - /* check for protected sectors */ - *addr = (FPW) 0x00900090; - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02. - * D0 = 1 for each device if protected. - * If at least one device is protected the sector is marked - * protected, but mixed protected and unprotected devices - * within a sector should never happen. - */ - sect = (FPWV *) (info->start[i]); - info->protect[i] = - (sect[2] & (FPW) (0x00010001)) ? 1 : 0; - } - - /* Put FLASH back in read mode */ - flash_reset(info); - break; - - case FLASH_AM640U: - default: - /* no hardware protect that we support */ - break; - } -} -#endif - -/*----------------------------------------------------------------------- - */ - -int -flash_erase(flash_info_t * info, int s_first, int s_last) -{ - FPWV *addr; - int flag, prot, sect; - int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL; - ulong start, now, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf("- missing\n"); - } else { - printf("- no sectors to erase\n"); - } - return 1; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_INTEL800B: - case FLASH_INTEL160B: - case FLASH_INTEL320B: - case FLASH_INTEL640B: - case FLASH_28F800C3B: - case FLASH_28F160C3B: - case FLASH_28F320C3B: - case FLASH_28F640C3B: - case FLASH_AM640U: - break; - case FLASH_UNKNOWN: - default: - printf("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf("\n"); - } - - start = get_timer(0); - last = start; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && rcode == 0; sect++) { - - if (info->protect[sect] != 0) /* protected, skip it */ - continue; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr = (FPWV *) (info->start[sect]); - if (intel) { - *addr = (FPW) 0x00500050; /* clear status register */ - *addr = (FPW) 0x00200020; /* erase setup */ - *addr = (FPW) 0x00D000D0; /* erase confirm */ - } else { - /* must be AMD style if not Intel */ - FPWV *base; /* first address in bank */ - - base = (FPWV *) (info->start[0]); - base[0x0555] = (FPW) 0x00AA00AA; /* unlock */ - base[0x02AA] = (FPW) 0x00550055; /* unlock */ - base[0x0555] = (FPW) 0x00800080; /* erase mode */ - base[0x0555] = (FPW) 0x00AA00AA; /* unlock */ - base[0x02AA] = (FPW) 0x00550055; /* unlock */ - *addr = (FPW) 0x00300030; /* erase sector */ - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 50us for AMD, 80us for Intel. - * Let's wait 1 ms. - */ - udelay(1000); - - while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) { - if ((now = get_timer(0)) - start > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf("Timeout\n"); - - if (intel) { - /* suspend erase */ - *addr = (FPW) 0x00B000B0; - } - - flash_reset(info); /* reset to read mode */ - rcode = 1; /* failed */ - break; - } - - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc('.'); - last = now; - } - } - - flash_reset(info); /* reset to read mode */ - } - - printf(" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int -bad_write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ - int bytes; /* number of bytes to program in current word */ - int left; /* number of bytes left to program */ - int i, res; - - for (left = cnt, res = 0; - left > 0 && res == 0; - addr += sizeof (data), left -= sizeof (data) - bytes) { - - bytes = addr & (sizeof (data) - 1); - addr &= ~(sizeof (data) - 1); - - /* combine source and destination data so can program - * an entire word of 16 or 32 bits - */ - for (i = 0; i < sizeof (data); i++) { - data <<= 8; - if (i < bytes || i - bytes >= left) - data += *((uchar *) addr + i); - else - data += *src++; - } - - /* write one word to the flash */ - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - res = write_word_amd(info, (FPWV *) addr, data); - break; - case FLASH_MAN_INTEL: - res = write_word_intel(info, (FPWV *) addr, data); - break; - default: - /* unknown flash type, error! */ - printf("missing or unknown FLASH type\n"); - res = 1; /* not really a timeout, but gives error */ - break; - } - } - - return (res); -} - -/** - * write_buf: - Copy memory to flash. - * - * @param info: - * @param src: source of copy transaction - * @param addr: where to copy to - * @param cnt: number of bytes to copy - * - * @return error code - */ - -int -write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int l; - int i, rc; - - wp = (addr & ~1); /* get lower word aligned address */ - - /* handle unaligned start bytes */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - for (; i < 2 && cnt > 0; ++i) { - data = (data >> 8) | (*src++ << 8); - --cnt; - ++cp; - } - for (; cnt == 0 && i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - - if ((rc = write_word(info, (FPWV *)wp, data)) != 0) { - return (rc); - } - wp += 2; - } - - /* handle word aligned part */ - while (cnt >= 2) { - /* data = *((vushort*)src); */ - data = *((FPW *) src); - if ((rc = write_word(info, (FPWV *)wp, data)) != 0) { - return (rc); - } - src += sizeof (FPW); - wp += sizeof (FPW); - cnt -= sizeof (FPW); - } - - if (cnt == 0) - return ERR_OK; - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 8); - --cnt; - } - for (; i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - - return write_word(info, (FPWV *)wp, data); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for AMD FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int -write_word_amd(flash_info_t * info, FPWV * dest, FPW data) -{ - ulong start; - int flag; - int res = 0; /* result, assume success */ - FPWV *base; /* first address in flash bank */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - base = (FPWV *) (info->start[0]); - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - base[0x0555] = (FPW) 0x00AA00AA; /* unlock */ - base[0x02AA] = (FPW) 0x00550055; /* unlock */ - base[0x0555] = (FPW) 0x00A000A0; /* selects program mode */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer(0); - - /* data polling for D7 */ - while (res == 0 - && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) { - if (get_timer(0) - start > CONFIG_SYS_FLASH_WRITE_TOUT) { - *dest = (FPW) 0x00F000F0; /* reset bank */ - printf("SHA timeout\n"); - res = 1; - } - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for Intel FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int -write_word_intel(flash_info_t * info, FPWV * dest, FPW data) -{ - ulong start; - int flag; - int res = 0; /* result, assume success */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - *dest = (FPW) 0x00500050; /* clear status register */ - *dest = (FPW) 0x00FF00FF; /* make sure in read mode */ - *dest = (FPW) 0x00400040; /* program setup */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer(0); - - while (res == 0 && (*dest & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *dest = (FPW) 0x00B000B0; /* Suspend program */ - res = 1; - } - } - - if (res == 0 && (*dest & (FPW) 0x00100010)) - res = 1; /* write failed, time out error is close enough */ - - *dest = (FPW) 0x00500050; /* clear status register */ - *dest = (FPW) 0x00FF00FF; /* make sure in read mode */ - - return (res); -} - -#ifdef CONFIG_SYS_FLASH_PROTECTION -/*----------------------------------------------------------------------- - */ -int -flash_real_protect(flash_info_t * info, long sector, int prot) -{ - int rcode = 0; /* assume success */ - FPWV *addr; /* address of sector */ - FPW value; - - addr = (FPWV *) (info->start[sector]); - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F800C3B: - case FLASH_28F800C3T: - case FLASH_28F160C3B: - case FLASH_28F160C3T: - case FLASH_28F320C3B: - case FLASH_28F320C3T: - case FLASH_28F640C3B: - case FLASH_28F640C3T: - flash_reset(info); /* make sure in read mode */ - *addr = (FPW) 0x00600060L; /* lock command setup */ - if (prot) - *addr = (FPW) 0x00010001L; /* lock sector */ - else - *addr = (FPW) 0x00D000D0L; /* unlock sector */ - flash_reset(info); /* reset to read mode */ - - /* now see if it really is locked/unlocked as requested */ - *addr = (FPW) 0x00900090; - /* read sector protection at sector address, (A7 .. A0) = 0x02. - * D0 = 1 for each device if protected. - * If at least one device is protected the sector is marked - * protected, but return failure. Mixed protected and - * unprotected devices within a sector should never happen. - */ - value = addr[2] & (FPW) 0x00010001; - if (value == 0) - info->protect[sector] = 0; - else if (value == (FPW) 0x00010001) - info->protect[sector] = 1; - else { - /* error, mixed protected and unprotected */ - rcode = 1; - info->protect[sector] = 1; - } - if (info->protect[sector] != prot) - rcode = 1; /* failed to protect/unprotect as requested */ - - /* reload all protection bits from hardware for now */ - flash_sync_real_protect(info); - break; - - case FLASH_AM640U: - default: - /* no hardware protect that we support */ - info->protect[sector] = prot; - break; - } - - return rcode; -} -#endif diff --git a/board/mx1fs2/intel.h b/board/mx1fs2/intel.h deleted file mode 100644 index 8db5dd4f64..0000000000 --- a/board/mx1fs2/intel.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (C) 2002 ETC s.r.o. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the ETC s.r.o. nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Written by Marcel Telka <marcel@telka.sk>, 2002. - * - * Documentation: - * [1] Intel Corporation, "3 Volt Intel Strata Flash Memory 28F128J3A, 28F640J3A, - * 28F320J3A (x8/x16)", April 2002, Order Number: 290667-011 - * [2] Intel Corporation, "3 Volt Synchronous Intel Strata Flash Memory 28F640K3, 28F640K18, - * 28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)", June 2002, Order Number: 290737-005 - * - * This file is taken from OpenWinCE project hosted by SourceForge.net - * - */ - -#ifndef FLASH_INTEL_H -#define FLASH_INTEL_H - -#include <common.h> - -/* Intel CFI commands - see Table 4. in [1] and Table 3. in [2] */ - -#define CFI_INTEL_CMD_READ_ARRAY 0xFF /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_READ_IDENTIFIER 0x90 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_READ_QUERY 0x98 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_READ_STATUS_REGISTER 0x70 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_CLEAR_STATUS_REGISTER 0x50 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_PROGRAM1 0x40 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_PROGRAM2 0x10 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_WRITE_TO_BUFFER 0xE8 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_CONFIRM 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_BLOCK_ERASE 0x20 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_SUSPEND 0xB0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_RESUME 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_LOCK_SETUP 0x60 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_LOCK_BLOCK 0x01 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_UNLOCK_BLOCK 0xD0 /* 28FxxxJ3A - unlocks all blocks, 28FFxxxK3, 28FxxxK18 */ -#define CFI_INTEL_CMD_LOCK_DOWN_BLOCK 0x2F /* 28FxxxK3, 28FxxxK18 */ - -/* Intel CFI Status Register bits - see Table 6. in [1] and Table 7. in [2] */ - -#define CFI_INTEL_SR_READY 1 << 7 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_SR_ERASE_SUSPEND 1 << 6 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_SR_ERASE_ERROR 1 << 5 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_SR_PROGRAM_ERROR 1 << 4 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_SR_VPEN_ERROR 1 << 3 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_SR_PROGRAM_SUSPEND 1 << 2 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_SR_BLOCK_LOCKED 1 << 1 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */ -#define CFI_INTEL_SR_BEFP 1 << 0 /* 28FxxxK3, 28FxxxK18 */ - -/* Intel flash device ID codes for 28FxxxJ3A - see Table 5. in [1] */ - -#define CFI_CHIP_INTEL_28F320J3A 0x0016 -#define CFI_CHIPN_INTEL_28F320J3A "28F320J3A" -#define CFI_CHIP_INTEL_28F640J3A 0x0017 -#define CFI_CHIPN_INTEL_28F640J3A "28F640J3A" -#define CFI_CHIP_INTEL_28F128J3A 0x0018 -#define CFI_CHIPN_INTEL_28F128J3A "28F128J3A" - -/* Intel flash device ID codes for 28FxxxK3 and 28FxxxK18 - see Table 8. in [2] */ - -#define CFI_CHIP_INTEL_28F640K3 0x8801 -#define CFI_CHIPN_INTEL_28F640K3 "28F640K3" -#define CFI_CHIP_INTEL_28F128K3 0x8802 -#define CFI_CHIPN_INTEL_28F128K3 "28F128K3" -#define CFI_CHIP_INTEL_28F256K3 0x8803 -#define CFI_CHIPN_INTEL_28F256K3 "28F256K3" -#define CFI_CHIP_INTEL_28F640K18 0x8805 -#define CFI_CHIPN_INTEL_28F640K18 "28F640K18" -#define CFI_CHIP_INTEL_28F128K18 0x8806 -#define CFI_CHIPN_INTEL_28F128K18 "28F128K18" -#define CFI_CHIP_INTEL_28F256K18 0x8807 -#define CFI_CHIPN_INTEL_28F256K18 "28F256K18" - -#endif /* FLASH_INTEL_H */ diff --git a/board/mx1fs2/lowlevel_init.S b/board/mx1fs2/lowlevel_init.S deleted file mode 100644 index 56a4819b08..0000000000 --- a/board/mx1fs2/lowlevel_init.S +++ /dev/null @@ -1,188 +0,0 @@ -/* - * Copyright (C) 2004 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version 2 - * of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA - * 02111-1307, USA. - * - */ - -#include <config.h> -#include <version.h> -#include <asm/arch/imx-regs.h> - -.globl lowlevel_init -lowlevel_init: - - mov r10, lr - -/* Change PERCLK1DIV to 14 ie 14+1 */ - ldr r0, =PCDR - ldr r1, =CONFIG_SYS_PCDR_VAL - str r1, [r0] - -/* set MCU PLL Control Register 0 */ - - ldr r0, =MPCTL0 - ldr r1, =CONFIG_SYS_MPCTL0_VAL - str r1, [r0] - -/* set MCU PLL Control Register 1 */ - - ldr r0, =MPCTL1 - ldr r1, =CONFIG_SYS_MPCTL1_VAL - str r1, [r0] - -/* set mpll restart bit */ - ldr r0, =CSCR - ldr r1, [r0] - orr r1,r1,#(1<<21) - str r1, [r0] - - mov r2,#0x10 -1: - mov r3,#0x2000 -2: - subs r3,r3,#1 - bne 2b - - subs r2,r2,#1 - bne 1b - -/* set System PLL Control Register 0 */ - - ldr r0, =SPCTL0 - ldr r1, =CONFIG_SYS_SPCTL0_VAL - str r1, [r0] - -/* set System PLL Control Register 1 */ - - ldr r0, =SPCTL1 - ldr r1, =CONFIG_SYS_SPCTL1_VAL - str r1, [r0] - -/* set spll restart bit */ - ldr r0, =CSCR - ldr r1, [r0] - orr r1,r1,#(1<<22) - str r1, [r0] - - mov r2,#0x10 -1: - mov r3,#0x2000 -2: - subs r3,r3,#1 - bne 2b - - subs r2,r2,#1 - bne 1b - - ldr r0, =CSCR - ldr r1, =CONFIG_SYS_CSCR_VAL - str r1, [r0] - - ldr r0, =GPCR - ldr r1, =CONFIG_SYS_GPCR_VAL - str r1, [r0] - -/* - * I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon - * this..... - * - * It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15 - * register 1, this stops it using the output of the PLL and thus runs at the - * slow rate. Unless you place the Core into "Asynch" mode, the CPU will never - * use the value set in the CM_OSC registers...regardless of what you set it - * too! Thus, although i thought i was running at 140MHz, i'm actually running - * at 40!.. - * - * Slapping this into my bootloader does the trick... - * - * MRC p15,0,r0,c1,c0,0 ; read core configuration register - * ORR r0,r0,#0xC0000000 ; set asynchronous clocks and not fastbus mode - * MCR p15,0,r0,c1,c0,0 ; write modified value to core configuration - * register - * - */ - MRC p15,0,r0,c1,c0,0 -/* ORR r0,r0,#0xC0000000 async mode */ -/* ORR r0,r0,#0x40000000 sync mode */ - ORR r0,r0,#0xC0000000 - MCR p15,0,r0,c1,c0,0 - - ldr r0, =GIUS(0) - ldr r1, =CONFIG_SYS_GIUS_A_VAL - str r1, [r0] - - ldr r0, =FMCR - ldr r1, =CONFIG_SYS_FMCR_VAL - str r1, [r0] - - ldr r0, =CS0U - ldr r1, =CONFIG_SYS_CS0U_VAL - str r1, [r0] - - ldr r0, =CS0L - ldr r1, =CONFIG_SYS_CS0L_VAL - str r1, [r0] - - ldr r0, =CS1U - ldr r1, =CONFIG_SYS_CS1U_VAL - str r1, [r0] - - ldr r0, =CS1L - ldr r1, =CONFIG_SYS_CS1L_VAL - str r1, [r0] - - ldr r0, =CS4U - ldr r1, =CONFIG_SYS_CS4U_VAL - str r1, [r0] - - ldr r0, =CS4L - ldr r1, =CONFIG_SYS_CS4L_VAL - str r1, [r0] - - ldr r0, =CS5U - ldr r1, =CONFIG_SYS_CS5U_VAL - str r1, [r0] - - ldr r0, =CS5L - ldr r1, =CONFIG_SYS_CS5L_VAL - str r1, [r0] - -/* SDRAM Setup */ - - ldr r1,=0x00221000 /* adr of SDCTRL0 */ - ldr r0,=0x92120200 - str r0,[r1,#0] /* put in precharge command mode */ - ldr r2,=0x08200000 /* adr for precharge cmd */ - ldr r0,[r2,#0] /* precharge */ - ldr r0,=0xA2120200 - ldr r2,=0x08000000 /* start of SDRAM */ - str r0,[r1,#0] /* put in auto-refresh mode */ - ldr r0,[r2,#0] /* auto-refresh */ - ldr r0,[r2,#0] /* auto-refresh */ - ldr r0,[r2,#0] /* auto-refresh */ - ldr r0,[r2,#0] /* auto-refresh */ - ldr r0,[r2,#0] /* auto-refresh */ - ldr r0,[r2,#0] /* auto-refresh */ - ldr r0,[r2,#0] /* auto-refresh */ - ldr r0,=0xB2120200 - ldr r2,=0x08111800 - str r0,[r1,#0] /* setup for mode register of SDRAM */ - ldr r0,[r2,#0] /* program mode register */ - ldr r0,=0x82124267 - str r0,[r1,#0] /* back to normal operation */ - - mov pc,r10 diff --git a/board/mx1fs2/mx1fs2.c b/board/mx1fs2/mx1fs2.c deleted file mode 100644 index 90a33c2499..0000000000 --- a/board/mx1fs2/mx1fs2.c +++ /dev/null @@ -1,122 +0,0 @@ -/* - * Copyright (C) 2004 Sascha Hauer, Pengutronix - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#include <common.h> -#include <asm/arch/imx-regs.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) - -extern void imx_gpio_mode(int gpio_mode); - -static void logo_init(void) -{ - imx_gpio_mode(PD15_PF_LD0); - imx_gpio_mode(PD16_PF_LD1); - imx_gpio_mode(PD17_PF_LD2); - imx_gpio_mode(PD18_PF_LD3); - imx_gpio_mode(PD19_PF_LD4); - imx_gpio_mode(PD20_PF_LD5); - imx_gpio_mode(PD21_PF_LD6); - imx_gpio_mode(PD22_PF_LD7); - imx_gpio_mode(PD23_PF_LD8); - imx_gpio_mode(PD24_PF_LD9); - imx_gpio_mode(PD25_PF_LD10); - imx_gpio_mode(PD26_PF_LD11); - imx_gpio_mode(PD27_PF_LD12); - imx_gpio_mode(PD28_PF_LD13); - imx_gpio_mode(PD29_PF_LD14); - imx_gpio_mode(PD30_PF_LD15); - imx_gpio_mode(PD14_PF_FLM_VSYNC); - imx_gpio_mode(PD13_PF_LP_HSYNC); - imx_gpio_mode(PD6_PF_LSCLK); - imx_gpio_mode(GPIO_PORTD | GPIO_OUT | GPIO_DR); - imx_gpio_mode(PD11_PF_CONTRAST); - imx_gpio_mode(PD10_PF_SPL_SPR); - - LCDC_RMCR = 0x00000000; - LCDC_PCR = PCR_COLOR | PCR_PBSIZ_8 | PCR_BPIX_16 | PCR_PCD(5); - LCDC_HCR = HCR_H_WIDTH(2); - LCDC_VCR = VCR_V_WIDTH(2); - - LCDC_PWMR = 0x00000380; /* contrast to 0x80 middle (is best !!!) */ - LCDC_SSA = 0x10040000; /* image in flash */ - - LCDC_SIZE = SIZE_XMAX(320) | SIZE_YMAX(240); /* screen size */ - - LCDC_VPW = 0x000000A0; /* Virtual Page Width Register */ - LCDC_POS = 0x00000000; /* panning offset 0 (0 pixel offset) */ - - /* disable Cursor */ - LCDC_CPOS = 0x00000000; - - /* fixed burst length */ - LCDC_DMACR = DMACR_BURST | DMACR_HM(8) | DMACR_TM(2); - - /* enable LCD */ - DR(3) |= 0x00001000; - LCDC_RMCR = RMCR_LCDC_EN; - -} - -int -board_init(void) -{ - gd->bd->bi_arch_number = MACH_TYPE_MX1FS2; - gd->bd->bi_boot_params = 0x08000100; -serial_init(); - logo_init(); - return 0; -} - -int -dram_init(void) -{ -#if ( CONFIG_NR_DRAM_BANKS > 0 ) - gd->bd->bi_dram[0].start = MX1FS2_SDRAM_1; - gd->bd->bi_dram[0].size = MX1FS2_SDRAM_1_SIZE; -#endif - return 0; -} - -/** - * show_boot_progress: - indicate state of the boot process - * - * @param status: Status number - see README for details. - * - */ - -void -show_boot_progress(int status) -{ - /* We use this as a hook to disable serial ports just before booting - * This way we suppress the "uncompressing linux..." message - */ -#ifdef CONFIG_SILENT_CONSOLE - if( status == 8) { - if( getenv("silent") != NULL ) { - *(volatile unsigned long *)0x206080 &= ~1; - *(volatile unsigned long *)0x207080 &= ~1; - } - } -#endif - return; -} diff --git a/board/netstar/Makefile b/board/netstar/Makefile deleted file mode 100644 index 7230a2f88a..0000000000 --- a/board/netstar/Makefile +++ /dev/null @@ -1,95 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2005 -# Ladislav Michl, 2N Telekomunikace, michl@2n.cz -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := netstar.o -SOBJS := setup.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -LOAD_ADDR = 0x10400000 - -######################################################################### - -all: $(obj).depend $(LIB) $(obj)eeprom.srec $(obj)eeprom.bin \ - $(obj)crcek.srec $(obj)crcek.bin $(obj)crcit - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $^) - -$(obj)eeprom_start.o: - echo "b eeprom" | $(CC) $(AFLAGS) -c -x assembler -o $@ - - -$(obj)eeprom: $(obj)eeprom_start.o $(obj)eeprom.o - $(LD) -Ttext $(LOAD_ADDR) -e eeprom -o $@ $^ \ - -L$(obj)../../examples/standalone -lstubs \ - $(PLATFORM_LIBS) - -$(obj)eeprom.srec: $(obj)eeprom - $(OBJCOPY) -S -O srec $(<:.o=) $@ - -$(obj)eeprom.bin: $(obj)eeprom - $(OBJCOPY) -S -O binary $< $@ - -$(obj)crcek.srec: $(obj)crcek.o - $(LD) -g -Ttext 0x00000000 -e crcek -o $(<:.o=) $^ - $(OBJCOPY) -S -O srec $(<:.o=) $@ - -$(obj)crcek.bin: $(obj)crcek.srec - $(OBJCOPY) -I srec -O binary $< $@ - -$(obj)crcit: $(obj)crcit.o $(obj)crc32.o - $(HOSTCC) $(HOSTCFLAGS) -o $@ $^ - -$(obj)crcit.o: crcit.c - $(HOSTCC) $(HOSTCFLAGS) -o $@ -c $< - -$(obj)crc32.o: $(SRCTREE)/lib/crc32.c - $(HOSTCC) $(HOSTCFLAGS) -DUSE_HOSTCC -I$(TOPDIR)/include \ - -o $@ -c $< - -clean: - rm -f $(SOBJS) $(OBJS) \ - $(obj)eeprom_start.o $(obj)eeprom.o \ - $(obj)eeprom $(obj)eeprom.srec $(obj)eeprom.bin \ - $(obj)crcek.o $(obj)crcek $(obj)crcek.srec $(obj)crcek.bin - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/netstar/config.mk b/board/netstar/config.mk deleted file mode 100644 index 9e1446e4b6..0000000000 --- a/board/netstar/config.mk +++ /dev/null @@ -1,11 +0,0 @@ -# -# Linux-Kernel is expected to be at 1000'8000, -# entry 1000'8000 (mem base + reserved) -# -# We load ourself to internal RAM at 2001'2000 -# Check map file when changing CONFIG_SYS_TEXT_BASE. -# Everything has fit into 192kB internal SRAM! -# - -# XXX CONFIG_SYS_TEXT_BASE = 0x20012000 -CONFIG_SYS_TEXT_BASE = 0x13FC0000 diff --git a/board/netstar/crcek.S b/board/netstar/crcek.S deleted file mode 100644 index af35662187..0000000000 --- a/board/netstar/crcek.S +++ /dev/null @@ -1,241 +0,0 @@ -/** - * (C) Copyright 2005 - * 2N Telekomunikace, Ladislav Michl <michl@2n.cz> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2. - * - * Image layout looks like following: - * u32 - size - * u32 - version - * ... - data - * u32 - crc32 - */ - -#include <config.h> -#include "crcek.h" - -/** - * do_crc32 - calculate CRC32 of given buffer - * r0 - crc - * r1 - pointer to buffer - * r2 - buffer len - */ - .macro do_crc32 - ldr r5, FFFFFFFF - eor r0, r0, r5 - adr r3, CRC32_TABLE -1: - ldrb r4, [r1], #1 - eor r4, r4, r0 - and r4, r4, #0xff - ldr r4, [r3, r4, lsl#2] - eor r0, r4, r0, lsr#8 - subs r2, r2, #0x1 - bne 1b - eor r0, r0, r5 - .endm - - .macro crcuj, offset, size - mov r0, #0 - ldr r1, \offset - ldr r2, [r1], #4 - cmp r2, r0 @ no data, no problem - beq 2f - tst r2, #3 @ unaligned size - bne 2f - ldr r3, \size - cmp r2, r3 @ bogus size - bhi 2f - do_crc32 - ldr r1, [r1] -2: - cmp r0, r1 - .endm - - .macro wait, reg - mov \reg, #0x100000 -3: - subs \reg, \reg, #0x1 - bne 3b - .endm - -.text -.globl crcek -crcek: - /* Enable I-cache */ - mrc p15, 0, r1, c0, c0, 0 @ read C15 ID register - mrc p15, 0, r1, c0, c0, 1 @ read C15 Cache information register - mrc p15, 0, r1, c1, c0, 0 @ read C15 Control register - orr r1, r1, #0x1000 @ enable I-cache, map interrupt vector 0xffff0000 - mcr p15, 0, r1, c1, c0, 0 @ write C15 Control register - mov r1, #0x00 - mcr p15, 0, r1, c7, c5, 0 @ Flush I-cache - nop - nop - nop - nop - - /* Setup clocking mode */ - ldr r0, MPU_CLKM_BASE @ base of CLOCK unit - ldrh r1, [r0, #0x18] @ ARM_SYST - get reset status - bic r1, r1, #(7 << 11) @ clear clock select - orr r1, r1, #(2 << 11) @ set synchronous scalable - mov r2, #0 -loop: - cmp r2, #1 @ this loop will wait for at least 100 cycles - streqh r1, [r0, #0x18] @ before issuing next request from MPU - add r2, r2, #1 @ on the 1st run code is loaded into I-cache - cmp r2, #16 @ and second run will set clocking mode - bne loop - nop - - /* Setup clock dividers */ - ldr r1, CKCTL_VAL - orr r1, r1, #0x2000 @ enable DSP clock - strh r1, [r0] @ setup clock divisors - - /* Setup DPLL to generate requested freq */ - ldr r0, DPLL1_BASE @ base of DPLL1 register - mov r1, #0x0010 @ set PLL_ENABLE - orr r1, r1, #0x2000 @ set IOB to new locking - orr r1, r1, #(OMAP5910_DPLL_MUL << 7) @ setup multiplier CLKREF - orr r1, r1, #(OMAP5910_DPLL_DIV << 5) @ setup divider CLKREF - strh r1, [r0] @ write - -locking: - ldrh r1, [r0] @ get DPLL value - tst r1, #0x01 - beq locking @ while LOCK not set - - /* Enable clock */ - ldr r0, MPU_CLKM_BASE @ base of CLOCK unit - mov r1, #(1 << 10) @ disable idle mode do not check - @ nWAKEUP pin, other remain active - strh r1, [r0, #0x04] - ldr r1, EN_CLK_VAL - strh r1, [r0, #0x08] - mov r1, #0x003f @ FLASH.RP not enabled in idle and - strh r1, [r0, #0x0c] @ max delayed ( 32 x CLKIN ) - - - mov r6, #0 - crcuj _LOADER1_OFFSET, _LOADER_SIZE - bne crc1_bad - orr r6, r6, #1 -crc1_bad: - crcuj _LOADER2_OFFSET, _LOADER_SIZE - bne crc2_bad - orr r6, r6, #2 -crc2_bad: - ldr r3, _LOADER1_OFFSET - ldr r4, _LOADER2_OFFSET - teq r6, #3 - bne one_is_bad @ one of them (or both) has bad crc - ldr r1, [r3, #4] - ldr r2, [r4, #4] - cmp r1, r2 @ boot 2nd loader if versions differ - beq boot_1st - b boot_2nd -one_is_bad: - tst r6, #1 - bne boot_1st - tst r6, #2 - bne boot_2nd -@ We are doomed, so let user know. -hell: - ldr r0, GPIO_BASE @ configure GPIO pins - ldr r1, GPIO_DIRECTION - strh r1, [r0, #0x08] -blink_loop: - mov r1, #0x08 - strh r1, [r0, #0x04] - wait r3 - mov r1, #0x10 - strh r1, [r0, #0x04] - wait r3 - b blink_loop -boot_1st: - add pc, r3, #8 -boot_2nd: - add pc, r4, #8 - -_LOADER_SIZE: - .word LOADER_SIZE - 8 @ minus size and crc32 -_LOADER1_OFFSET: - .word LOADER1_OFFSET -_LOADER2_OFFSET: - .word LOADER2_OFFSET - -FFFFFFFF: - .word 0xffffffff -CRC32_TABLE: - .word 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419 - .word 0x706af48f, 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4 - .word 0xe0d5e91e, 0x97d2d988, 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07 - .word 0x90bf1d91, 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de - .word 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, 0x136c9856 - .word 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9 - .word 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4 - .word 0xa2677172, 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b - .word 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3 - .word 0x45df5c75, 0xdcd60dcf, 0xabd13d59, 0x26d930ac, 0x51de003a - .word 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, 0xcfba9599 - .word 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924 - .word 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190 - .word 0x01db7106, 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f - .word 0x9fbfe4a5, 0xe8b8d433, 0x7807c9a2, 0x0f00f934, 0x9609a88e - .word 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01 - .word 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, 0x6c0695ed - .word 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950 - .word 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3 - .word 0xfbd44c65, 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2 - .word 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a - .word 0x346ed9fc, 0xad678846, 0xda60b8d0, 0x44042d73, 0x33031de5 - .word 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa, 0xbe0b1010 - .word 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f - .word 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17 - .word 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6 - .word 0x03b6e20c, 0x74b1d29a, 0xead54739, 0x9dd277af, 0x04db2615 - .word 0x73dc1683, 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8 - .word 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, 0xf00f9344 - .word 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb - .word 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a - .word 0x67dd4acc, 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5 - .word 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1 - .word 0xa6bc5767, 0x3fb506dd, 0x48b2364b, 0xd80d2bda, 0xaf0a1b4c - .word 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, 0x316e8eef - .word 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236 - .word 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe - .word 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31 - .word 0x2cd99e8b, 0x5bdeae1d, 0x9b64c2b0, 0xec63f226, 0x756aa39c - .word 0x026d930a, 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713 - .word 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, 0x92d28e9b - .word 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242 - .word 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1 - .word 0x18b74777, 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c - .word 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, 0xa00ae278 - .word 0xd70dd2ee, 0x4e048354, 0x3903b3c2, 0xa7672661, 0xd06016f7 - .word 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc, 0x40df0b66 - .word 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9 - .word 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605 - .word 0xcdd70693, 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8 - .word 0x5d681b02, 0x2a6f2b94, 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b - .word 0x2d02ef8d - -GPIO_BASE: - .word 0xfffce000 -MPU_CLKM_BASE: - .word 0xfffece00 -DPLL1_BASE: - .word 0xfffecf00 - -CKCTL_VAL: - .word OMAP5910_ARM_CKCTL -EN_CLK_VAL: - .word OMAP5910_ARM_EN_CLK -GPIO_DIRECTION: - .word 0x0000ffe7 - -.end diff --git a/board/netstar/crcek.h b/board/netstar/crcek.h deleted file mode 100644 index 30c08602f5..0000000000 --- a/board/netstar/crcek.h +++ /dev/null @@ -1,3 +0,0 @@ -#define LOADER_SIZE (448 * 1024) -#define LOADER1_OFFSET (128 * 1024) -#define LOADER2_OFFSET (LOADER1_OFFSET + LOADER_SIZE) diff --git a/board/netstar/crcit.c b/board/netstar/crcit.c deleted file mode 100644 index a16264914c..0000000000 --- a/board/netstar/crcit.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * (C) Copyright 2005 - * 2N Telekomunikace, Ladislav Michl <michl@2n.cz> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <stdio.h> -#include <stdlib.h> -#include <stdint.h> -#include <fcntl.h> -#include <string.h> -#include <unistd.h> -#include <sys/types.h> -#include <sys/stat.h> -#include "crcek.h" - -extern uint32_t crc32(uint32_t, const unsigned char *, uint); - -static uint32_t data[LOADER_SIZE/4 + 3]; - -static int do_crc(char *path, unsigned version) -{ - uint32_t *p; - ssize_t size; - int fd; - - fd = open(path, O_RDONLY); - if (fd == -1) { - perror("Error opening file"); - return EXIT_FAILURE; - } - p = data + 2; - size = read(fd, p, LOADER_SIZE + 4); - if (size == -1) { - perror("Error reading file"); - return EXIT_FAILURE; - } - if (size > LOADER_SIZE) { - fprintf(stderr, "File too large\n"); - return EXIT_FAILURE; - } - size = (size + 3) & ~3; /* round up to 4 bytes */ - size += 4; /* add size of version field */ - data[0] = size; - data[1] = version; - data[size/4 + 1] = crc32(0, (unsigned char *)(data + 1), size); - close(fd); - - if (write(STDOUT_FILENO, data, size + 4 /*size*/ + 4 /*crc*/) == -1) { - perror("Error writing file"); - return EXIT_FAILURE; - } - - return EXIT_SUCCESS; -} - -int main(int argc, char * const *argv) -{ - if (argc == 2) { - return do_crc(argv[1], 0); - } else if ((argc == 4) && (strcmp(argv[1], "-v") == 0)) { - char *endptr, *nptr = argv[2]; - unsigned ver = strtoul(nptr, &endptr, 0); - if (*nptr != '\0' && *endptr == '\0') - return do_crc(argv[3], ver); - } - fprintf(stderr, "Usage: crcit [-v version] <image>\n"); - - return EXIT_FAILURE; -} diff --git a/board/netstar/eeprom.c b/board/netstar/eeprom.c deleted file mode 100644 index aa375a4b1a..0000000000 --- a/board/netstar/eeprom.c +++ /dev/null @@ -1,218 +0,0 @@ -/* - * (C) Copyright 2005 - * Ladislav Michl, 2N Telekomunikace, michl@2n.cz - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Some code shamelessly stolen back from Robin Getz. - */ - -#include <common.h> -#include <exports.h> -#include <timestamp.h> -#include <net.h> -#include "../drivers/net/smc91111.h" - -static struct eth_device dev = { - .iobase = CONFIG_SMC91111_BASE -}; - -static u16 read_eeprom_reg(u16 reg) -{ - int timeout; - - SMC_SELECT_BANK(&dev, 2); - SMC_outw(&dev, reg, PTR_REG); - - SMC_SELECT_BANK(&dev, 1); - SMC_outw(&dev, SMC_inw(&dev, CTL_REG) | CTL_EEPROM_SELECT | - CTL_RELOAD, CTL_REG); - - timeout = 100; - - while ((SMC_inw(&dev, CTL_REG) & CTL_RELOAD) && --timeout) - udelay(100); - if (timeout == 0) { - printf("Timeout reading register %02x\n", reg); - return 0; - } - - return SMC_inw(&dev, GP_REG); -} - -static int write_eeprom_reg(u16 value, u16 reg) -{ - int timeout; - - SMC_SELECT_BANK(&dev, 2); - SMC_outw(&dev, reg, PTR_REG); - - SMC_SELECT_BANK(&dev, 1); - - SMC_outw(&dev, value, GP_REG); - SMC_outw(&dev, SMC_inw(&dev, CTL_REG) | CTL_EEPROM_SELECT | - CTL_STORE, CTL_REG); - - timeout = 100; - - while ((SMC_inw(&dev, CTL_REG) & CTL_STORE) && --timeout) - udelay(100); - if (timeout == 0) { - printf("Timeout writing register %02x\n", reg); - return 0; - } - - return 1; -} - -static int write_data(u16 *buf, int len) -{ - u16 reg = 0x23; - - while (len--) - write_eeprom_reg(*buf++, reg++); - - return 0; -} - -static int verify_macaddr(char *s) -{ - u16 reg; - int i, err = 0; - - puts("HWaddr: "); - for (i = 0; i < 3; i++) { - reg = read_eeprom_reg(0x20 + i); - printf("%02x:%02x%c", reg & 0xff, reg >> 8, i != 2 ? ':' : '\n'); - if (s) - err |= reg != ((u16 *)s)[i]; - } - - return err ? 0 : 1; -} - -static int set_mac(char *s) -{ - int i; - char *e, eaddr[6]; - - /* turn string into mac value */ - for (i = 0; i < 6; i++) { - eaddr[i] = simple_strtoul(s, &e, 16); - s = (*e) ? e+1 : e; - } - - for (i = 0; i < 3; i++) - write_eeprom_reg(*(((u16 *)eaddr) + i), 0x20 + i); - - return 0; -} - -static int parse_element(char *s, unsigned char *buf, int len) -{ - int cnt; - char *p, num[3]; - unsigned char id; - - id = simple_strtoul(s, &p, 16); - if (*p++ != ':') - return -1; - cnt = 2; - num[2] = 0; - for (; *p; p += 2) { - if (p[1] == 0) - return -2; - if (cnt + 3 > len) - return -3; - num[0] = p[0]; - num[1] = p[1]; - buf[cnt++] = simple_strtoul(num, NULL, 16); - } - buf[0] = id; - buf[1] = cnt - 2; - - return cnt; -} - -int eeprom(int argc, char * const argv[]) -{ - int i, len, ret; - unsigned char buf[58], *p; - - app_startup(argv); - i = get_version(); - if (i != XF_VERSION) { - printf("Using ABI version %d, but U-Boot provides %d\n", - XF_VERSION, i); - return 1; - } - - if ((SMC_inw(&dev, BANK_SELECT) & 0xFF00) != 0x3300) { - puts("SMSC91111 not found\n"); - return 2; - } - - /* Called without parameters - print MAC address */ - if (argc < 2) { - verify_macaddr(NULL); - return 0; - } - - /* Print help message */ - if (argv[1][1] == 'h') { - puts("NetStar EEPROM writer\n" - "Built: " U_BOOT_DATE " at " U_BOOT_TIME "\n" - "Usage:\n\t<mac_address> [<element_1>] [<...>]\n"); - return 0; - } - - /* Try to parse information elements */ - len = sizeof(buf); - p = buf; - for (i = 2; i < argc; i++) { - ret = parse_element(argv[i], p, len); - switch (ret) { - case -1: - printf("Element %d: malformed\n", i - 1); - return 3; - case -2: - printf("Element %d: odd character count\n", i - 1); - return 3; - case -3: - puts("Out of EEPROM memory\n"); - return 3; - default: - p += ret; - len -= ret; - } - } - - /* First argument (MAC) is mandatory */ - set_mac(argv[1]); - if (verify_macaddr(argv[1])) { - puts("*** HWaddr does not match! ***\n"); - return 4; - } - - while (len--) - *p++ = 0; - - write_data((u16 *)buf, sizeof(buf) >> 1); - - return 0; -} diff --git a/board/netstar/netstar.c b/board/netstar/netstar.c deleted file mode 100644 index df1704be35..0000000000 --- a/board/netstar/netstar.c +++ /dev/null @@ -1,129 +0,0 @@ -/* - * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <netdev.h> -#include <i2c.h> -#include <flash.h> -#include <nand.h> - -#include <asm/io.h> - -DECLARE_GLOBAL_DATA_PTR; - -int board_init(void) -{ - /* arch number of NetStar board */ - gd->bd->bi_arch_number = MACH_TYPE_NETSTAR; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x10000100; - - return 0; -} - -int dram_init(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - /* Take the Ethernet controller out of reset and wait - * for the EEPROM load to complete. */ - *((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) |= 0x80; - udelay(10); /* doesn't work before timer_init call */ - *((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) &= ~0x80; - udelay(500); - - return 0; -} - -int misc_init_r(void) -{ -#if defined(CONFIG_RTC_DS1307) - /* enable trickle charge */ - i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, 0x10, 0xaa); -#endif - return 0; -} - -int board_late_init(void) -{ - return 0; -} - -#if defined(CONFIG_CMD_FLASH) -ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t * info) -{ - if (banknum == 0) { /* AM29LV800 boot flash */ - info->portwidth = FLASH_CFI_16BIT; - info->chipwidth = FLASH_CFI_BY16; - info->interface = FLASH_CFI_X16; - return 1; - } - - return 0; -} -#endif - -#if defined(CONFIG_CMD_NAND) -/* - * hardware specific access to control-lines - * - * NAND_NCE: bit 0 - don't care - * NAND_CLE: bit 1 -> bit 1 (0x0002) - * NAND_ALE: bit 2 -> bit 2 (0x0004) - */ -static void netstar_nand_hwcontrol(struct mtd_info *mtd, int cmd, - unsigned int ctrl) -{ - struct nand_chip *chip = mtd->priv; - unsigned long mask; - - if (cmd == NAND_CMD_NONE) - return; - - mask = (ctrl & NAND_CLE) ? 0x02 : 0; - if (ctrl & NAND_ALE) - mask |= 0x04; - writeb(cmd, (unsigned long)chip->IO_ADDR_W | mask); -} - -int board_nand_init(struct nand_chip *nand) -{ - nand->options = NAND_SAMSUNG_LP_OPTIONS; - nand->ecc.mode = NAND_ECC_SOFT; - nand->cmd_ctrl = netstar_nand_hwcontrol; - nand->chip_delay = 400; - return 0; -} -#endif - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC91111 - rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); -#endif - return rc; -} -#endif diff --git a/board/netstar/setup.S b/board/netstar/setup.S deleted file mode 100644 index 72e18112f6..0000000000 --- a/board/netstar/setup.S +++ /dev/null @@ -1,284 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2004 Ales Jindra <jindra@2n.cz> - * (C) Copyright 2005 Ladislav Michl <michl@2n.cz> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <version.h> - -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE /* SDRAM load addr from config.mk */ - -OMAP5910_LPG1_BASE: .word 0xfffbd000 -OMAP5910_TIPB_SWITCHES_BASE: .word 0xfffbc800 -OMAP5910_MPU_TC_BASE: .word 0xfffecc00 -OMAP5910_MPU_CLKM_BASE: .word 0xfffece00 -OMAP5910_ULPD_PWR_MNG_BASE: .word 0xfffe0800 -OMAP5910_DPLL1_BASE: .word 0xfffecf00 -OMAP5910_GPIO_BASE: .word 0xfffce000 -OMAP5910_MPU_WD_TIMER_BASE: .word 0xfffec800 -OMAP5910_MPUI_BASE: .word 0xfffec900 - -_OMAP5910_ARM_CKCTL: .word OMAP5910_ARM_CKCTL -_OMAP5910_ARM_EN_CLK: .word OMAP5910_ARM_EN_CLK - -OMAP5910_MPUI_CTRL: .word 0x0000ff1b - -VAL_EMIFS_CS0_CONFIG: .word 0x00009090 -VAL_EMIFS_CS1_CONFIG: .word 0x00003031 -VAL_EMIFS_CS2_CONFIG: .word 0x0000a0a1 -VAL_EMIFS_CS3_CONFIG: .word 0x0000c0c0 -VAL_EMIFS_DYN_WAIT: .word 0x00000000 -/* autorefresh counter 0x246 ((64000000/13.4)-400)/8192) */ - /* SLRF SD_RET ARE SDRAM_TYPE ARCV SDRAM_FREQUENCY PWD CLK */ - -#if (PHYS_SDRAM_1_SIZE == SZ_32M) -VAL_EMIFF_SDRAM_CONFIG: .word ((0 << 0) | (0 << 1) | (3 << 2) | (0xf << 4) | (0x246 << 8) | (0 << 24) | (0 << 26) | (0 << 27)) -#else -VAL_EMIFF_SDRAM_CONFIG: .word ((0 << 0) | (0 << 1) | (3 << 2) | (0xd << 4) | (0x246 << 8) | (0 << 24) | (0 << 26) | (0 << 27)) -#endif - -VAL_EMIFF_SDRAM_CONFIG2: .word 0x00000003 -VAL_EMIFF_MRS: .word 0x00000037 - -/* - * GPIO04 - Green LED (Red LED is connected to LED Pulse Generator) - * GPIO07 - LAN91C111 reset - */ -GPIO_DIRECTION: - .word 0x0000ff6f -/* - * Disable everything (green LED is connected via invertor) - */ -GPIO_OUTPUT: - .word 0x00000010 - -MUX_CONFIG_BASE: - .word 0xfffe1000 - -MUX_CONFIG_VALUES: - .align 4 - .word 0x00000000 @ FUNC_MUX_CTRL_0 - .word 0x00000000 @ FUNC_MUX_CTRL_1 - .word 0x00000000 @ FUNC_MUX_CTRL_2 - .word 0x00000000 @ FUNC_MUX_CTRL_3 - .word 0x00000000 @ FUNC_MUX_CTRL_4 - .word 0x02080480 @ FUNC_MUX_CTRL_5 - .word 0x0100001c @ FUNC_MUX_CTRL_6 - .word 0x0004800b @ FUNC_MUX_CTRL_7 - .word 0x10001200 @ FUNC_MUX_CTRL_8 - .word 0x01201012 @ FUNC_MUX_CTRL_9 - .word 0x02082248 @ FUNC_MUX_CTRL_A - .word 0x00000248 @ FUNC_MUX_CTRL_B - .word 0x12240000 @ FUNC_MUX_CTRL_C - .word 0x00002000 @ FUNC_MUX_CTRL_D - .word 0x00000000 @ PULL_DWN_CTRL_0 - .word 0x00000800 @ PULL_DWN_CTRL_1 - .word 0x01801000 @ PULL_DWN_CTRL_2 - .word 0x00000000 @ PULL_DWN_CTRL_3 - .word 0x00000000 @ GATE_INH_CTRL_0 - .word 0x00000000 @ VOLTAGE_CTRL_0 - .word 0x00000000 @ TEST_DBG_CTRL_0 - .word 0x00000006 @ MOD_CONF_CTRL_0 - .word 0x0000eaef @ COMP_MODE_CTRL_0 - -MUX_CONFIG_OFFSETS: - .align 1 - .byte 0x00 @ FUNC_MUX_CTRL_0 - .byte 0x04 @ FUNC_MUX_CTRL_1 - .byte 0x08 @ FUNC_MUX_CTRL_2 - .byte 0x10 @ FUNC_MUX_CTRL_3 - .byte 0x14 @ FUNC_MUX_CTRL_4 - .byte 0x18 @ FUNC_MUX_CTRL_5 - .byte 0x1c @ FUNC_MUX_CTRL_6 - .byte 0x20 @ FUNC_MUX_CTRL_7 - .byte 0x24 @ FUNC_MUX_CTRL_8 - .byte 0x28 @ FUNC_MUX_CTRL_9 - .byte 0x2c @ FUNC_MUX_CTRL_A - .byte 0x30 @ FUNC_MUX_CTRL_B - .byte 0x34 @ FUNC_MUX_CTRL_C - .byte 0x38 @ FUNC_MUX_CTRL_D - .byte 0x40 @ PULL_DWN_CTRL_0 - .byte 0x44 @ PULL_DWN_CTRL_1 - .byte 0x48 @ PULL_DWN_CTRL_2 - .byte 0x4c @ PULL_DWN_CTRL_3 - .byte 0x50 @ GATE_INH_CTRL_0 - .byte 0x60 @ VOLTAGE_CTRL_0 - .byte 0x70 @ TEST_DBG_CTRL_0 - .byte 0x80 @ MOD_CONF_CTRL_0 - .byte 0x0c @ COMP_MODE_CTRL_0 - .byte 0xff - -.globl lowlevel_init -lowlevel_init: - /* Improve performance a bit... */ - mrc p15, 0, r1, c0, c0, 0 @ read C15 ID register - mrc p15, 0, r1, c0, c0, 1 @ read C15 Cache information register - mrc p15, 0, r1, c1, c0, 0 @ read C15 Control register - orr r1, r1, #0x1000 @ enable I-cache, map interrupt vector 0xffff0000 - mcr p15, 0, r1, c1, c0, 0 @ write C15 Control register - mov r1, #0x00 - mcr p15, 0, r1, c7, c5, 0 @ Flush I-cache - nop - nop - nop - nop - - /* Setup clocking mode */ - ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit - ldrh r1, [r0, #0x18] @ ARM_SYST - get reset status - bic r1, r1, #(7 << 11) @ clear clock select - orr r1, r1, #(2 << 11) @ set synchronous scalable - mov r2, #0 -loop: - cmp r2, #1 @ this loop will wait for at least 100 cycles - streqh r1, [r0, #0x18] @ before issuing next request from MPU - add r2, r2, #1 @ on the 1st run code is loaded into I-cache - cmp r2, #16 @ and second run will set clocking mode - bne loop - nop - - /* Setup clock dividers */ - ldr r1, _OMAP5910_ARM_CKCTL - orr r1, r1, #0x2000 @ enable DSP clock - strh r1, [r0] @ setup clock divisors - - /* Setup DPLL to generate requested freq */ - ldr r0, OMAP5910_DPLL1_BASE @ base of DPLL1 register - mov r1, #0x0010 @ set PLL_ENABLE - orr r1, r1, #0x2000 @ set IOB to new locking - orr r1, r1, #(OMAP5910_DPLL_MUL << 7) @ setup multiplier CLKREF - orr r1, r1, #(OMAP5910_DPLL_DIV << 5) @ setup divider CLKREF - strh r1, [r0] @ write - -locking: - ldrh r1, [r0] @ get DPLL value - tst r1, #0x01 - beq locking @ while LOCK not set - - /* Enable clock */ - ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit - mov r1, #(1 << 10) @ disable idle mode do not check - @ nWAKEUP pin, other remain active - strh r1, [r0, #0x04] - ldr r1, _OMAP5910_ARM_EN_CLK - strh r1, [r0, #0x08] - mov r1, #0x003f @ FLASH.RP not enabled in idle and - strh r1, [r0, #0x0c] @ max delayed ( 32 x CLKIN ) - - /* Configure 5910 pins functions to match our board. */ - ldr r0, MUX_CONFIG_BASE - adr r1, MUX_CONFIG_VALUES - adr r2, MUX_CONFIG_OFFSETS -next_mux_cfg: - ldrb r3, [r2], #1 - ldr r4, [r1], #4 - cmp r3, #0xff - strne r4, [r0, r3] - bne next_mux_cfg - - /* Configure GPIO pins (also disables Green LED) */ - ldr r0, OMAP5910_GPIO_BASE - ldr r1, GPIO_OUTPUT - strh r1, [r0, #0x04] - ldr r1, GPIO_DIRECTION - strh r1, [r0, #0x08] - - /* EnablePeripherals */ - ldr r0, OMAP5910_MPU_CLKM_BASE @ CLOCK unit - mov r1, #0x0001 @ Peripheral enable - strh r1, [r0, #0x14] - - /* Program LED Pulse Generator */ - ldr r0, OMAP5910_LPG1_BASE @ 1st LED Pulse Generator - mov r1, #0x7F @ Set obscure frequency in - strb r1, [r0, #0x00] @ LCR - mov r1, #0x01 @ Enable clock (CLK_EN) in - strb r1, [r0, #0x04] @ PMR - - /* TIPB Lock UART1 */ - ldr r0, OMAP5910_TIPB_SWITCHES_BASE @ prepare base of TIPB switches - mov r1, #1 @ ARM allocated - strh r1, [r0,#0x04] @ clear IRQ line and status bits - strh r1, [r0,#0x00] - ldrh r1, [r0,#0x04] - - /* Disable watchdog */ - ldr r0, OMAP5910_MPU_WD_TIMER_BASE - mov r1, #0xf5 - strh r1, [r0, #0x8] - mov r1, #0xa0 - strh r1, [r0, #0x8] - - /* Enable MCLK */ - ldr r0, OMAP5910_ULPD_PWR_MNG_BASE - mov r1, #0x6 - strh r1, [r0, #0x34] - strh r1, [r0, #0x34] - - /* Setup clock divisors */ - ldr r0, OMAP5910_ULPD_PWR_MNG_BASE @ base of ULDPL DPLL1 register - - mov r1, #0x0010 @ set PLL_ENABLE - orr r1, r1, #0x2000 @ set IOB to new locking - strh r1, [r0] @ write - -ulocking: - ldrh r1, [r0] @ get DPLL value - tst r1, #1 - beq ulocking @ while LOCK not set - - /* EMIF init */ - ldr r0, OMAP5910_MPU_TC_BASE - ldrh r1, [r0, #0x0c] @ EMIFS_CONFIG_REG - bic r1, r1, #0x0c @ pwr down disabled, flash WP - orr r1, r1, #0x01 - str r1, [r0, #0x0c] - - ldr r1, VAL_EMIFS_CS0_CONFIG - str r1, [r0, #0x10] @ EMIFS_CS0_CONFIG - ldr r1, VAL_EMIFS_CS1_CONFIG - str r1, [r0, #0x14] @ EMIFS_CS1_CONFIG - ldr r1, VAL_EMIFS_CS2_CONFIG - str r1, [r0, #0x18] @ EMIFS_CS2_CONFIG - ldr r1, VAL_EMIFS_CS3_CONFIG - str r1, [r0, #0x1c] @ EMIFS_CS3_CONFIG - ldr r1, VAL_EMIFS_DYN_WAIT - str r1, [r0, #0x40] @ EMIFS_CFG_DYN_WAIT - - /* Setup SDRAM */ - ldr r1, VAL_EMIFF_SDRAM_CONFIG - str r1, [r0, #0x20] @ EMIFF_SDRAM_CONFIG - ldr r1, VAL_EMIFF_SDRAM_CONFIG2 - str r1, [r0, #0x3c] @ EMIFF_SDRAM_CONFIG2 - ldr r1, VAL_EMIFF_MRS - str r1, [r0, #0x24] @ EMIFF_MRS - /* SDRAM needs 100us to stabilize */ - mov r0, #0x4000 -sdelay: - subs r0, r0, #0x1 - bne sdelay - - /* back to arch calling code */ - mov pc, lr -.end diff --git a/board/nvidia/common/board.c b/board/nvidia/common/board.c index 8ab94404d1..160dac8e1c 100644 --- a/board/nvidia/common/board.c +++ b/board/nvidia/common/board.c @@ -28,6 +28,7 @@ #include <asm/arch/sys_proto.h> #include <asm/arch/clk_rst.h> +#include <asm/arch/clock.h> #include <asm/arch/pinmux.h> #include <asm/arch/uart.h> #include "board.h" @@ -76,33 +77,28 @@ int timer_init(void) static void clock_init_uart(void) { struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; + struct clk_pll *pll = &clkrst->crc_pll[CLOCK_PLL_ID_PERIPH]; u32 reg; - reg = readl(&clkrst->crc_pllp_base); - if (!(reg & PLL_BASE_OVRRIDE)) { + reg = readl(&pll->pll_base); + if (!(reg & PLL_BASE_OVRRIDE_MASK)) { /* Override pllp setup for 216MHz operation. */ - reg = (PLL_BYPASS | PLL_BASE_OVRRIDE | PLL_DIVP); - reg |= (((NVRM_PLLP_FIXED_FREQ_KHZ/500) << 8) | PLL_DIVM); - writel(reg, &clkrst->crc_pllp_base); + reg = PLL_BYPASS_MASK | PLL_BASE_OVRRIDE_MASK | + (1 << PLL_DIVP_SHIFT) | (0xc << PLL_DIVM_SHIFT); + reg |= (NVRM_PLLP_FIXED_FREQ_KHZ / 500) << PLL_DIVN_SHIFT; + writel(reg, &pll->pll_base); - reg |= PLL_ENABLE; - writel(reg, &clkrst->crc_pllp_base); + reg |= PLL_ENABLE_MASK; + writel(reg, &pll->pll_base); - reg &= ~PLL_BYPASS; - writel(reg, &clkrst->crc_pllp_base); + reg &= ~PLL_BYPASS_MASK; + writel(reg, &pll->pll_base); } - /* Now do the UART reset/clock enable */ #if defined(CONFIG_TEGRA2_ENABLE_UARTA) - /* Assert Reset to UART */ - reg = readl(&clkrst->crc_rst_dev_l); - reg |= SWR_UARTA_RST; /* SWR_UARTA_RST = 1 */ - writel(reg, &clkrst->crc_rst_dev_l); - - /* Enable clk to UART */ - reg = readl(&clkrst->crc_clk_out_enb_l); - reg |= CLK_ENB_UARTA; /* CLK_ENB_UARTA = 1 */ - writel(reg, &clkrst->crc_clk_out_enb_l); + /* Assert UART reset and enable clock */ + reset_set_enable(PERIPH_ID_UART1, 1); + clock_enable(PERIPH_ID_UART1); /* Enable pllp_out0 to UART */ reg = readl(&clkrst->crc_clk_src_uarta); @@ -113,20 +109,12 @@ static void clock_init_uart(void) udelay(2); /* De-assert reset to UART */ - reg = readl(&clkrst->crc_rst_dev_l); - reg &= ~SWR_UARTA_RST; /* SWR_UARTA_RST = 0 */ - writel(reg, &clkrst->crc_rst_dev_l); + reset_set_enable(PERIPH_ID_UART1, 0); #endif /* CONFIG_TEGRA2_ENABLE_UARTA */ #if defined(CONFIG_TEGRA2_ENABLE_UARTD) - /* Assert Reset to UART */ - reg = readl(&clkrst->crc_rst_dev_u); - reg |= SWR_UARTD_RST; /* SWR_UARTD_RST = 1 */ - writel(reg, &clkrst->crc_rst_dev_u); - - /* Enable clk to UART */ - reg = readl(&clkrst->crc_clk_out_enb_u); - reg |= CLK_ENB_UARTD; /* CLK_ENB_UARTD = 1 */ - writel(reg, &clkrst->crc_clk_out_enb_u); + /* Assert UART reset and enable clock */ + reset_set_enable(PERIPH_ID_UART4, 1); + clock_enable(PERIPH_ID_UART4); /* Enable pllp_out0 to UART */ reg = readl(&clkrst->crc_clk_src_uartd); @@ -137,9 +125,7 @@ static void clock_init_uart(void) udelay(2); /* De-assert reset to UART */ - reg = readl(&clkrst->crc_rst_dev_u); - reg &= ~SWR_UARTD_RST; /* SWR_UARTD_RST = 0 */ - writel(reg, &clkrst->crc_rst_dev_u); + reset_set_enable(PERIPH_ID_UART4, 0); #endif /* CONFIG_TEGRA2_ENABLE_UARTD */ } @@ -157,19 +143,15 @@ static void pin_mux_uart(void) reg &= 0xFFF0FFFF; /* IRRX_/IRTX_SEL [19:16] = 00 UARTA */ writel(reg, &pmt->pmt_ctl_c); - reg = readl(&pmt->pmt_tri_a); - reg &= ~Z_IRRX; /* Z_IRRX = normal (0) */ - reg &= ~Z_IRTX; /* Z_IRTX = normal (0) */ - writel(reg, &pmt->pmt_tri_a); + pinmux_tristate_disable(PIN_IRRX); + pinmux_tristate_disable(PIN_IRTX); #endif /* CONFIG_TEGRA2_ENABLE_UARTA */ #if defined(CONFIG_TEGRA2_ENABLE_UARTD) reg = readl(&pmt->pmt_ctl_b); reg &= 0xFFFFFFF3; /* GMC_SEL [3:2] = 00, UARTD */ writel(reg, &pmt->pmt_ctl_b); - reg = readl(&pmt->pmt_tri_a); - reg &= ~Z_GMC; /* Z_GMC = normal (0) */ - writel(reg, &pmt->pmt_tri_a); + pinmux_tristate_disable(PIN_GMC); #endif /* CONFIG_TEGRA2_ENABLE_UARTD */ } @@ -183,16 +165,8 @@ static void clock_init_mmc(void) u32 reg; /* Do the SDMMC resets/clock enables */ - - /* Assert Reset to SDMMC4 */ - reg = readl(&clkrst->crc_rst_dev_l); - reg |= SWR_SDMMC4_RST; /* SWR_SDMMC4_RST = 1 */ - writel(reg, &clkrst->crc_rst_dev_l); - - /* Enable clk to SDMMC4 */ - reg = readl(&clkrst->crc_clk_out_enb_l); - reg |= CLK_ENB_SDMMC4; /* CLK_ENB_SDMMC4 = 1 */ - writel(reg, &clkrst->crc_clk_out_enb_l); + reset_set_enable(PERIPH_ID_SDMMC4, 1); + clock_enable(PERIPH_ID_SDMMC4); /* Enable pllp_out0 to SDMMC4 */ reg = readl(&clkrst->crc_clk_src_sdmmc4); @@ -206,20 +180,10 @@ static void clock_init_mmc(void) */ udelay(2); - /* De-assert reset to SDMMC4 */ - reg = readl(&clkrst->crc_rst_dev_l); - reg &= ~SWR_SDMMC4_RST; /* SWR_SDMMC4_RST = 0 */ - writel(reg, &clkrst->crc_rst_dev_l); - - /* Assert Reset to SDMMC3 */ - reg = readl(&clkrst->crc_rst_dev_u); - reg |= SWR_SDMMC3_RST; /* SWR_SDMMC3_RST = 1 */ - writel(reg, &clkrst->crc_rst_dev_u); + reset_set_enable(PERIPH_ID_SDMMC4, 1); - /* Enable clk to SDMMC3 */ - reg = readl(&clkrst->crc_clk_out_enb_u); - reg |= CLK_ENB_SDMMC3; /* CLK_ENB_SDMMC3 = 1 */ - writel(reg, &clkrst->crc_clk_out_enb_u); + reset_set_enable(PERIPH_ID_SDMMC3, 1); + clock_enable(PERIPH_ID_SDMMC3); /* Enable pllp_out0 to SDMMC4, set divisor to 11 for 20MHz */ reg = readl(&clkrst->crc_clk_src_sdmmc3); @@ -230,10 +194,7 @@ static void clock_init_mmc(void) /* wait for 2us */ udelay(2); - /* De-assert reset to SDMMC3 */ - reg = readl(&clkrst->crc_rst_dev_u); - reg &= ~SWR_SDMMC3_RST; /* SWR_SDMMC3_RST = 0 */ - writel(reg, &clkrst->crc_rst_dev_u); + reset_set_enable(PERIPH_ID_SDMMC3, 0); } /* @@ -257,13 +218,9 @@ static void pin_mux_mmc(void) reg |= (3 << 0); /* GME_SEL [1:0] = 11 SDIO4 */ writel(reg, &pmt->pmt_ctl_d); - reg = readl(&pmt->pmt_tri_a); - reg &= ~Z_ATB; /* Z_ATB = normal (0) */ - reg &= ~Z_GMA; /* Z_GMA = normal (0) */ - writel(reg, &pmt->pmt_tri_a); - reg = readl(&pmt->pmt_tri_b); - reg &= ~Z_GME; /* Z_GME = normal (0) */ - writel(reg, &pmt->pmt_tri_b); + pinmux_tristate_disable(PIN_ATB); + pinmux_tristate_disable(PIN_GMA); + pinmux_tristate_disable(PIN_GME); /* SDMMC3 */ /* SDIO3_CLK, SDIO3_CMD, SDIO3_DAT[3:0] */ @@ -274,13 +231,9 @@ static void pin_mux_mmc(void) reg |= (2 << 14); /* SDD_SEL [15:14] = 01 SDIO3 */ writel(reg, &pmt->pmt_ctl_d); - reg = readl(&pmt->pmt_tri_b); - reg &= ~Z_SDC; /* Z_SDC = normal (0) */ - reg &= ~Z_SDD; /* Z_SDD = normal (0) */ - writel(reg, &pmt->pmt_tri_b); - reg = readl(&pmt->pmt_tri_d); - reg &= ~Z_SDB; /* Z_SDB = normal (0) */ - writel(reg, &pmt->pmt_tri_d); + pinmux_tristate_disable(PIN_SDC); + pinmux_tristate_disable(PIN_SDD); + pinmux_tristate_disable(PIN_SDB); } /* @@ -318,8 +271,6 @@ int board_init(void) { /* boot param addr */ gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100); - /* board id for Linux */ - gd->bd->bi_arch_number = CONFIG_MACH_TYPE; return 0; } diff --git a/board/pandora/pandora.c b/board/pandora/pandora.c index 992e9f7625..58a676d455 100644 --- a/board/pandora/pandora.c +++ b/board/pandora/pandora.c @@ -32,7 +32,9 @@ #include <common.h> #include <twl4030.h> #include <asm/io.h> +#include <asm/arch/mmc_host_def.h> #include <asm/arch/mux.h> +#include <asm/arch/gpio.h> #include <asm/arch/sys_proto.h> #include <asm/mach-types.h> #include "pandora.h" @@ -102,3 +104,11 @@ void set_muxconf_regs(void) { MUX_PANDORA(); } + +#ifdef CONFIG_GENERIC_MMC +int board_mmc_init(bd_t *bis) +{ + omap_mmc_init(0); + return 0; +} +#endif diff --git a/board/ronetix/pm9261/led.c b/board/ronetix/pm9261/led.c index ff21ce667b..f65987035d 100644 --- a/board/ronetix/pm9261/led.c +++ b/board/ronetix/pm9261/led.c @@ -24,17 +24,16 @@ */ #include <common.h> -#include <asm/arch/at91sam9261.h> #include <asm/arch/at91_pmc.h> -#include <asm/arch/at91_pio.h> -#include <asm/arch/io.h> +#include <asm/arch/gpio.h> +#include <asm/io.h> void coloured_LED_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; /* Enable clock */ - writel(1 << AT91SAM9261_ID_PIOC, &pmc->pcer); + writel(1 << ATMEL_ID_PIOC, &pmc->pcer); at91_set_pio_output(CONFIG_RED_LED, 1); at91_set_pio_output(CONFIG_GREEN_LED, 1); diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c index 2c50fe8e6e..871b94ada7 100644 --- a/board/ronetix/pm9261/pm9261.c +++ b/board/ronetix/pm9261/pm9261.c @@ -26,17 +26,15 @@ #include <common.h> #include <asm/sizes.h> -#include <asm/arch/at91sam9261.h> +#include <asm/io.h> #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/at91_rstc.h> #include <asm/arch/at91_matrix.h> -#include <asm/arch/at91_pio.h> #include <asm/arch/clk.h> -#include <asm/arch/at91_pio.h> -#include <asm/arch/io.h> -#include <asm/arch/hardware.h> +#include <asm/arch/gpio.h> + #include <lcd.h> #include <atmel_lcdc.h> #include <dataflash.h> @@ -56,9 +54,9 @@ DECLARE_GLOBAL_DATA_PTR; static void pm9261_nand_hw_init(void) { unsigned long csa; - at91_smc_t *smc = (at91_smc_t *) AT91_SMC_BASE; - at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE; - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; /* Enable CS3 */ csa = readl(&matrix->csa) | AT91_MATRIX_CSA_EBI_CS3A; @@ -86,8 +84,8 @@ static void pm9261_nand_hw_init(void) AT91_SMC_MODE_TDF_CYCLE(2), &smc->cs[3].mode); - writel(1 << AT91SAM9261_ID_PIOA | - 1 << AT91SAM9261_ID_PIOC, + writel(1 << ATMEL_ID_PIOA | + 1 << ATMEL_ID_PIOC, &pmc->pcer); /* Configure RDY/BSY */ @@ -105,8 +103,8 @@ static void pm9261_nand_hw_init(void) #ifdef CONFIG_DRIVER_DM9000 static void pm9261_dm9000_hw_init(void) { - at91_smc_t *smc = (at91_smc_t *) AT91_SMC_BASE; - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; /* Configure SMC CS2 for DM9000 */ writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | @@ -127,7 +125,7 @@ static void pm9261_dm9000_hw_init(void) &smc->cs[2].mode); /* Configure Interrupt pin as input, no pull-up */ - writel(1 << AT91SAM9261_ID_PIOA, &pmc->pcer); + writel(1 << ATMEL_ID_PIOA, &pmc->pcer); at91_set_pio_input(AT91_PIO_PORTA, 24, 0); } #endif @@ -147,7 +145,7 @@ vidinfo_t panel_info = { vl_vsync_len: 1, vl_upper_margin:1, vl_lower_margin:0, - mmio: AT91SAM9261_LCDC_BASE, + mmio: ATMEL_BASE_LCDC, }; void lcd_enable(void) @@ -162,7 +160,7 @@ void lcd_disable(void) static void pm9261_lcd_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* LCDHSYNC */ at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* LCDDOTCK */ @@ -189,7 +187,7 @@ static void pm9261_lcd_hw_init(void) writel(1 << 17, &pmc->scer); /* LCD controller Clock, AT91SAM9261 only */ - gd->fb_base = AT91SAM9261_SRAM_BASE; + gd->fb_base = ATMEL_BASE_SRAM; } #ifdef CONFIG_LCD_INFO @@ -241,13 +239,13 @@ void lcd_show_board_info(void) int board_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; /* Enable Ctrlc */ console_init_f(); - writel(1 << AT91SAM9261_ID_PIOA | - 1 << AT91SAM9261_ID_PIOC, + writel(1 << ATMEL_ID_PIOA | + 1 << ATMEL_ID_PIOC, &pmc->pcer); /* arch number of PM9261-Board */ @@ -256,7 +254,7 @@ int board_init(void) /* adress of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - at91_serial_hw_init(); + at91_seriald_hw_init(); #ifdef CONFIG_CMD_NAND pm9261_nand_hw_init(); #endif diff --git a/board/ronetix/pm9263/led.c b/board/ronetix/pm9263/led.c index 4e585a4751..d6eb69f04a 100644 --- a/board/ronetix/pm9263/led.c +++ b/board/ronetix/pm9263/led.c @@ -24,17 +24,16 @@ */ #include <common.h> -#include <asm/arch/at91sam9263.h> #include <asm/arch/at91_pmc.h> -#include <asm/arch/at91_pio.h> -#include <asm/arch/io.h> +#include <asm/arch/gpio.h> +#include <asm/io.h> void coloured_LED_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; /* Enable clock */ - writel(1 << AT91SAM9263_ID_PIOB, &pmc->pcer); + writel(1 << ATMEL_ID_PIOB, &pmc->pcer); at91_set_pio_output(CONFIG_RED_LED, 1); at91_set_pio_output(CONFIG_GREEN_LED, 1); diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c index 8071600081..cfc9847ccc 100644 --- a/board/ronetix/pm9263/pm9263.c +++ b/board/ronetix/pm9263/pm9263.c @@ -26,16 +26,14 @@ #include <common.h> #include <asm/sizes.h> -#include <asm/arch/at91sam9263.h> +#include <asm/io.h> #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/at91_rstc.h> #include <asm/arch/at91_matrix.h> -#include <asm/arch/at91_pio.h> #include <asm/arch/clk.h> -#include <asm/arch/io.h> -#include <asm/arch/hardware.h> +#include <asm/arch/gpio.h> #include <lcd.h> #include <atmel_lcdc.h> #include <dataflash.h> @@ -55,8 +53,8 @@ DECLARE_GLOBAL_DATA_PTR; static void pm9263_nand_hw_init(void) { unsigned long csa; - at91_smc_t *smc = (at91_smc_t *) AT91_SMC0_BASE; - at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE; + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC0; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; /* Enable CS3 */ csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A; @@ -95,7 +93,7 @@ static void pm9263_nand_hw_init(void) #ifdef CONFIG_MACB static void pm9263_macb_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; /* * PB27 enables the 50MHz oscillator for Ethernet PHY @@ -106,7 +104,7 @@ static void pm9263_macb_hw_init(void) at91_set_pio_value(AT91_PIO_PORTB, 27, 1); /* 1- enable, 0 - disable */ /* Enable clock */ - writel(1 << AT91SAM9263_ID_EMAC, &pmc->pcer); + writel(1 << ATMEL_ID_EMAC, &pmc->pcer); /* * Disable pull-up on: @@ -145,7 +143,7 @@ vidinfo_t panel_info = { vl_vsync_len: 1, vl_upper_margin:1, vl_lower_margin:0, - mmio: AT91SAM9263_LCDC_BASE, + mmio: ATMEL_BASE_LCDC, }; void lcd_enable(void) @@ -168,8 +166,8 @@ static int pm9263_lcd_hw_psram_init(void) { volatile uint16_t x; unsigned long csa; - at91_smc_t *smc = (at91_smc_t *) AT91_SMC1_BASE; - at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE; + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC1; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; /* Enable CS3 3.3v, no pull-ups */ csa = readl(&matrix->csa[1]) | AT91_MATRIX_CSA_DBPUC | @@ -249,7 +247,7 @@ static int pm9263_lcd_hw_psram_init(void) static void pm9263_lcd_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */ at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */ @@ -275,7 +273,7 @@ static void pm9263_lcd_hw_init(void) at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */ at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */ - writel(1 << AT91SAM9263_ID_LCDC, &pmc->pcer); + writel(1 << ATMEL_ID_LCDC, &pmc->pcer); /* Power Control */ at91_set_pio_output(AT91_PIO_PORTA, 22, 1); @@ -285,9 +283,9 @@ static void pm9263_lcd_hw_init(void) /* initialize te PSRAM */ int stat = pm9263_lcd_hw_psram_init(); - gd->fb_base = (stat == 0) ? PHYS_PSRAM : AT91SAM9263_SRAM0_BASE; + gd->fb_base = (stat == 0) ? PHYS_PSRAM : ATMEL_BASE_SRAM0; #else - gd->fb_base = AT91SAM9263_SRAM0_BASE; + gd->fb_base = ATMEL_BASE_SRAM0; #endif } @@ -341,14 +339,14 @@ void lcd_show_board_info(void) int board_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; /* Enable Ctrlc */ console_init_f(); - writel((1 << AT91SAM9263_ID_PIOA) | - (1 << AT91SAM9263_ID_PIOCDE) | - (1 << AT91SAM9263_ID_PIOB), + writel((1 << ATMEL_ID_PIOA) | + (1 << ATMEL_ID_PIOCDE) | + (1 << ATMEL_ID_PIOB), &pmc->pcer); /* arch number of AT91SAM9263EK-Board */ @@ -357,7 +355,7 @@ int board_init(void) /* adress of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - at91_serial_hw_init(); + at91_seriald_hw_init(); #ifdef CONFIG_CMD_NAND pm9263_nand_hw_init(); #endif @@ -400,7 +398,7 @@ int board_eth_init(bd_t *bis) { int rc = 0; #ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)AT91_EMAC_BASE, 0x01); + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x01); #endif return rc; } @@ -417,7 +415,7 @@ int checkboard (void) ss = "(PSRAM)"; break; - case AT91SAM9263_SRAM0_BASE: + case ATMEL_BASE_SRAM0: ss = "(Internal SRAM)"; break; diff --git a/board/ronetix/pm9g45/pm9g45.c b/board/ronetix/pm9g45/pm9g45.c index fa69599e90..f3374a4429 100644 --- a/board/ronetix/pm9g45/pm9g45.c +++ b/board/ronetix/pm9g45/pm9g45.c @@ -29,16 +29,14 @@ #include <common.h> #include <asm/sizes.h> -#include <asm/arch/at91sam9g45.h> +#include <asm/io.h> #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/at91_rstc.h> #include <asm/arch/at91_matrix.h> -#include <asm/arch/at91_pio.h> +#include <asm/arch/gpio.h> #include <asm/arch/clk.h> -#include <asm/arch/io.h> -#include <asm/arch/hardware.h> #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) #include <net.h> #endif @@ -54,9 +52,9 @@ DECLARE_GLOBAL_DATA_PTR; static void pm9g45_nand_hw_init(void) { unsigned long csa; - at91_smc_t *smc = (at91_smc_t *) AT91_SMC_BASE; - at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE; - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; /* Enable CS3 */ csa = readl(&matrix->ccr[6]) | AT91_MATRIX_CSA_EBI_CS3A; @@ -80,7 +78,7 @@ static void pm9g45_nand_hw_init(void) AT91_SMC_MODE_TDF_CYCLE(3), &smc->cs[3].mode); - writel(1 << AT91SAM9G45_ID_PIOC, &pmc->pcer); + writel(1 << ATMEL_ID_PIOC, &pmc->pcer); #ifdef CONFIG_SYS_NAND_READY_PIN /* Configure RDY/BSY */ @@ -95,7 +93,7 @@ static void pm9g45_nand_hw_init(void) #ifdef CONFIG_MACB static void pm9g45_macb_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; /* * PD2 enables the 50MHz oscillator for Ethernet PHY @@ -106,7 +104,7 @@ static void pm9g45_macb_hw_init(void) at91_set_pio_value(AT91_PIO_PORTD, 2, 1); /* 1- enable, 0 - disable */ /* Enable clock */ - writel(1 << AT91SAM9G45_ID_EMAC, &pmc->pcer); + writel(1 << ATMEL_ID_EMAC, &pmc->pcer); /* * Disable pull-up on: @@ -131,22 +129,22 @@ static void pm9g45_macb_hw_init(void) int board_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; /* Enable Ctrlc */ console_init_f(); - writel((1 << AT91SAM9G45_ID_PIOA) | - (1 << AT91SAM9G45_ID_PIOB) | - (1 << AT91SAM9G45_ID_PIOC) | - (1 << AT91SAM9G45_ID_PIODE), &pmc->pcer); + writel((1 << ATMEL_ID_PIOA) | + (1 << ATMEL_ID_PIOB) | + (1 << ATMEL_ID_PIOC) | + (1 << ATMEL_ID_PIODE), &pmc->pcer); /* arch number of AT91SAM9M10G45EK-Board */ gd->bd->bi_arch_number = MACH_TYPE_PM9G45; /* adress of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - at91_serial_hw_init(); + at91_seriald_hw_init(); #ifdef CONFIG_CMD_NAND pm9g45_nand_hw_init(); #endif @@ -188,7 +186,7 @@ int board_eth_init(bd_t *bis) { int rc = 0; #ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)AT91_EMAC_BASE, 0x01); + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x01); #endif return rc; } diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c index 581935d054..e24cd29f37 100644 --- a/board/samsung/goni/goni.c +++ b/board/samsung/goni/goni.c @@ -73,7 +73,7 @@ int board_mmc_init(bd_t *bis) int i; /* MASSMEMORY_EN: XMSMDATA7: GPJ2[7] output high */ - gpio_direction_output(&s5pc110_gpio->j2, 7, 1); + s5p_gpio_direction_output(&s5pc110_gpio->j2, 7, 1); /* * MMC0 GPIO @@ -86,11 +86,11 @@ int board_mmc_init(bd_t *bis) if (i == 2) continue; /* GPG0[0:6] special function 2 */ - gpio_cfg_pin(&s5pc110_gpio->g0, i, 0x2); + s5p_gpio_cfg_pin(&s5pc110_gpio->g0, i, 0x2); /* GPG0[0:6] pull disable */ - gpio_set_pull(&s5pc110_gpio->g0, i, GPIO_PULL_NONE); + s5p_gpio_set_pull(&s5pc110_gpio->g0, i, GPIO_PULL_NONE); /* GPG0[0:6] drv 4x */ - gpio_set_drv(&s5pc110_gpio->g0, i, GPIO_DRV_4X); + s5p_gpio_set_drv(&s5pc110_gpio->g0, i, GPIO_DRV_4X); } return s5p_mmc_init(0, 4); diff --git a/board/armadillo/Makefile b/board/samsung/origen/Makefile index 3b524524f9..f5c6507337 100644 --- a/board/armadillo/Makefile +++ b/board/samsung/origen/Makefile @@ -1,10 +1,5 @@ # -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2002 -# Sysgo Real-Time Solutions, GmbH <www.elinos.com> -# Marius Groeger <mgroeger@sysgo.de> +# Copyright (C) 2011 Samsung Electronics # # See file CREDITS for list of people who contributed to this # project. @@ -29,21 +24,35 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -COBJS := armadillo.o flash.o -SOBJS := lowlevel_init.o +SOBJS := mem_setup.o +SOBJS += lowlevel_init.o + +ifndef CONFIG_SPL_BUILD +COBJS += origen.o +endif + +ifdef CONFIG_SPL_BUILD +COBJS += mmc_boot.o +endif SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) + +ALL +=$(obj).depend $(LIB) + +ifdef CONFIG_SPL_BUILD +ALL += tools/mk$(BOARD)spl.exe +endif -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) +all: $(ALL) -clean: - rm -f $(SOBJS) $(OBJS) +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend +ifdef CONFIG_SPL_BUILD +tools/mk$(BOARD)spl.exe: tools/mkv310_image.c + $(HOSTCC) tools/mkv310_image.c -o tools/mk$(BOARD)spl.exe +endif ######################################################################### diff --git a/board/samsung/origen/lowlevel_init.S b/board/samsung/origen/lowlevel_init.S new file mode 100644 index 0000000000..ddca1e21fc --- /dev/null +++ b/board/samsung/origen/lowlevel_init.S @@ -0,0 +1,357 @@ +/* + * Lowlevel setup for ORIGEN board based on S5PV310 + * + * Copyright (C) 2011 Samsung Electronics + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> +#include <asm/arch/cpu.h> +#include "origen_setup.h" +/* + * Register usages: + * + * r5 has zero always + * r7 has GPIO part1 base 0x11400000 + * r6 has GPIO part2 base 0x11000000 + */ + +_TEXT_BASE: + .word CONFIG_SYS_TEXT_BASE + + .globl lowlevel_init +lowlevel_init: + push {lr} + + /* r5 has always zero */ + mov r5, #0 + ldr r7, =S5PC210_GPIO_PART1_BASE + ldr r6, =S5PC210_GPIO_PART2_BASE + + /* check reset status */ + ldr r0, =(S5PC210_POWER_BASE + INFORM1_OFFSET) + ldr r1, [r0] + + /* AFTR wakeup reset */ + ldr r2, =S5P_CHECK_DIDLE + cmp r1, r2 + beq exit_wakeup + + /* LPA wakeup reset */ + ldr r2, =S5P_CHECK_LPA + cmp r1, r2 + beq exit_wakeup + + /* Sleep wakeup reset */ + ldr r2, =S5P_CHECK_SLEEP + cmp r1, r2 + beq wakeup_reset + + /* + * If U-boot is already running in ram, no need to relocate U-Boot. + * Memory controller must be configured before relocating U-Boot + * in ram. + */ + ldr r0, =0x0ffffff /* r0 <- Mask Bits*/ + bic r1, pc, r0 /* pc <- current addr of code */ + /* r1 <- unmasked bits of pc */ + ldr r2, _TEXT_BASE /* r2 <- original base addr in ram */ + bic r2, r2, r0 /* r2 <- unmasked bits of r2*/ + cmp r1, r2 /* compare r1, r2 */ + beq 1f /* r0 == r1 then skip sdram init */ + + /* init system clock */ + bl system_clock_init + + /* Memory initialize */ + bl mem_ctrl_asm_init + +1: + /* for UART */ + bl uart_asm_init + bl tzpc_init + pop {pc} + +wakeup_reset: + bl system_clock_init + bl mem_ctrl_asm_init + bl tzpc_init + +exit_wakeup: + /* Load return address and jump to kernel */ + ldr r0, =(S5PC210_POWER_BASE + INFORM0_OFFSET) + + /* r1 = physical address of s5pc210_cpu_resume function */ + ldr r1, [r0] + + /* Jump to kernel*/ + mov pc, r1 + nop + nop + +/* + * system_clock_init: Initialize core clock and bus clock. + * void system_clock_init(void) + */ +system_clock_init: + push {lr} + ldr r0, =S5PC210_CLOCK_BASE + + /* APLL(1), MPLL(1), CORE(0), HPM(0) */ + ldr r1, =CLK_SRC_CPU_VAL + ldr r2, =CLK_SRC_CPU_OFFSET + str r1, [r0, r2] + + /* wait ?us */ + mov r1, #0x10000 +2: subs r1, r1, #1 + bne 2b + + ldr r1, =CLK_SRC_TOP0_VAL + ldr r2, =CLK_SRC_TOP0_OFFSET + str r1, [r0, r2] + + ldr r1, =CLK_SRC_TOP1_VAL + ldr r2, =CLK_SRC_TOP1_OFFSET + str r1, [r0, r2] + + /* DMC */ + ldr r1, =CLK_SRC_DMC_VAL + ldr r2, =CLK_SRC_DMC_OFFSET + str r1, [r0, r2] + + /*CLK_SRC_LEFTBUS */ + ldr r1, =CLK_SRC_LEFTBUS_VAL + ldr r2, =CLK_SRC_LEFTBUS_OFFSET + str r1, [r0, r2] + + /*CLK_SRC_RIGHTBUS */ + ldr r1, =CLK_SRC_RIGHTBUS_VAL + ldr r2, =CLK_SRC_RIGHTBUS_OFFSET + str r1, [r0, r2] + + /* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */ + ldr r1, =CLK_SRC_FSYS_VAL + ldr r2, =CLK_SRC_FSYS_OFFSET + str r1, [r0, r2] + + /* UART[0:4] */ + ldr r1, =CLK_SRC_PERIL0_VAL + ldr r2, =CLK_SRC_PERIL0_OFFSET + str r1, [r0, r2] + + /* wait ?us */ + mov r1, #0x10000 +3: subs r1, r1, #1 + bne 3b + + /* CLK_DIV_CPU0 */ + ldr r1, =CLK_DIV_CPU0_VAL + ldr r2, =CLK_DIV_CPU0_OFFSET + str r1, [r0, r2] + + /* CLK_DIV_CPU1 */ + ldr r1, =CLK_DIV_CPU1_VAL + ldr r2, =CLK_DIV_CPU1_OFFSET + str r1, [r0, r2] + + /* CLK_DIV_DMC0 */ + ldr r1, =CLK_DIV_DMC0_VAL + ldr r2, =CLK_DIV_DMC0_OFFSET + str r1, [r0, r2] + + /*CLK_DIV_DMC1 */ + ldr r1, =CLK_DIV_DMC1_VAL + ldr r2, =CLK_DIV_DMC1_OFFSET + str r1, [r0, r2] + + /* CLK_DIV_LEFTBUS */ + ldr r1, =CLK_DIV_LEFTBUS_VAL + ldr r2, =CLK_DIV_LEFTBUS_OFFSET + str r1, [r0, r2] + + /* CLK_DIV_RIGHTBUS */ + ldr r1, =CLK_DIV_RIGHTBUS_VAL + ldr r2, =CLK_DIV_RIGHTBUS_OFFSET + str r1, [r0, r2] + + /* CLK_DIV_TOP */ + ldr r1, =CLK_DIV_TOP_VAL + ldr r2, =CLK_DIV_TOP_OFFSET + str r1, [r0, r2] + + /* MMC[0:1] */ + ldr r1, =CLK_DIV_FSYS1_VAL /* 800(MPLL) / (15 + 1) */ + ldr r2, =CLK_DIV_FSYS1_OFFSET + str r1, [r0, r2] + + /* MMC[2:3] */ + ldr r1, =CLK_DIV_FSYS2_VAL /* 800(MPLL) / (15 + 1) */ + ldr r2, =CLK_DIV_FSYS2_OFFSET + str r1, [r0, r2] + + /* MMC4 */ + ldr r1, =CLK_DIV_FSYS3_VAL /* 800(MPLL) / (15 + 1) */ + ldr r2, =CLK_DIV_FSYS3_OFFSET + str r1, [r0, r2] + + /* CLK_DIV_PERIL0: UART Clock Divisors */ + ldr r1, =CLK_DIV_PERIL0_VAL + ldr r2, =CLK_DIV_PERIL0_OFFSET + str r1, [r0, r2] + + /* Set PLL locktime */ + ldr r1, =PLL_LOCKTIME + ldr r2, =APLL_LOCK_OFFSET + str r1, [r0, r2] + + ldr r1, =PLL_LOCKTIME + ldr r2, =MPLL_LOCK_OFFSET + str r1, [r0, r2] + + ldr r1, =PLL_LOCKTIME + ldr r2, =EPLL_LOCK_OFFSET + str r1, [r0, r2] + + ldr r1, =PLL_LOCKTIME + ldr r2, =VPLL_LOCK_OFFSET + str r1, [r0, r2] + + /* APLL_CON1 */ + ldr r1, =APLL_CON1_VAL + ldr r2, =APLL_CON1_OFFSET + str r1, [r0, r2] + + /* APLL_CON0 */ + ldr r1, =APLL_CON0_VAL + ldr r2, =APLL_CON0_OFFSET + str r1, [r0, r2] + + /* MPLL_CON1 */ + ldr r1, =MPLL_CON1_VAL + ldr r2, =MPLL_CON1_OFFSET + str r1, [r0, r2] + + /* MPLL_CON0 */ + ldr r1, =MPLL_CON0_VAL + ldr r2, =MPLL_CON0_OFFSET + str r1, [r0, r2] + + /* EPLL */ + ldr r1, =EPLL_CON1_VAL + ldr r2, =EPLL_CON1_OFFSET + str r1, [r0, r2] + + /* EPLL_CON0 */ + ldr r1, =EPLL_CON0_VAL + ldr r2, =EPLL_CON0_OFFSET + str r1, [r0, r2] + + /* VPLL_CON1 */ + ldr r1, =VPLL_CON1_VAL + ldr r2, =VPLL_CON1_OFFSET + str r1, [r0, r2] + + /* VPLL_CON0 */ + ldr r1, =VPLL_CON0_VAL + ldr r2, =VPLL_CON0_OFFSET + str r1, [r0, r2] + + /* wait ?us */ + mov r1, #0x30000 +4: subs r1, r1, #1 + bne 4b + + pop {pc} +/* + * uart_asm_init: Initialize UART in asm mode, 115200bps fixed. + * void uart_asm_init(void) + */ + .globl uart_asm_init +uart_asm_init: + + /* setup UART0-UART3 GPIOs (part1) */ + mov r0, r7 + ldr r1, =S5PC210_GPIO_A0_CON_VAL + str r1, [r0, #S5PC210_GPIO_A0_CON_OFFSET] + ldr r1, =S5PC210_GPIO_A1_CON_VAL + str r1, [r0, #S5PC210_GPIO_A1_CON_OFFSET] + + ldr r0, =S5PC210_UART_BASE + add r0, r0, #S5PC210_DEFAULT_UART_OFFSET + + ldr r1, =ULCON_VAL + str r1, [r0, #ULCON_OFFSET] + ldr r1, =UCON_VAL + str r1, [r0, #UCON_OFFSET] + ldr r1, =UFCON_VAL + str r1, [r0, #UFCON_OFFSET] + ldr r1, =UBRDIV_VAL + str r1, [r0, #UBRDIV_OFFSET] + ldr r1, =UFRACVAL_VAL + str r1, [r0, #UFRACVAL_OFFSET] + mov pc, lr + nop + nop + nop + +/* Setting TZPC[TrustZone Protection Controller] */ +tzpc_init: + ldr r0, =TZPC0_BASE + mov r1, #R0SIZE + str r1, [r0] + mov r1, #DECPROTXSET + str r1, [r0, #TZPC_DECPROT0SET_OFFSET] + str r1, [r0, #TZPC_DECPROT1SET_OFFSET] + str r1, [r0, #TZPC_DECPROT2SET_OFFSET] + str r1, [r0, #TZPC_DECPROT3SET_OFFSET] + + ldr r0, =TZPC1_BASE + str r1, [r0, #TZPC_DECPROT0SET_OFFSET] + str r1, [r0, #TZPC_DECPROT1SET_OFFSET] + str r1, [r0, #TZPC_DECPROT2SET_OFFSET] + str r1, [r0, #TZPC_DECPROT3SET_OFFSET] + + ldr r0, =TZPC2_BASE + str r1, [r0, #TZPC_DECPROT0SET_OFFSET] + str r1, [r0, #TZPC_DECPROT1SET_OFFSET] + str r1, [r0, #TZPC_DECPROT2SET_OFFSET] + str r1, [r0, #TZPC_DECPROT3SET_OFFSET] + + ldr r0, =TZPC3_BASE + str r1, [r0, #TZPC_DECPROT0SET_OFFSET] + str r1, [r0, #TZPC_DECPROT1SET_OFFSET] + str r1, [r0, #TZPC_DECPROT2SET_OFFSET] + str r1, [r0, #TZPC_DECPROT3SET_OFFSET] + + ldr r0, =TZPC4_BASE + str r1, [r0, #TZPC_DECPROT0SET_OFFSET] + str r1, [r0, #TZPC_DECPROT1SET_OFFSET] + str r1, [r0, #TZPC_DECPROT2SET_OFFSET] + str r1, [r0, #TZPC_DECPROT3SET_OFFSET] + + ldr r0, =TZPC5_BASE + str r1, [r0, #TZPC_DECPROT0SET_OFFSET] + str r1, [r0, #TZPC_DECPROT1SET_OFFSET] + str r1, [r0, #TZPC_DECPROT2SET_OFFSET] + str r1, [r0, #TZPC_DECPROT3SET_OFFSET] + + mov pc, lr diff --git a/board/samsung/origen/mem_setup.S b/board/samsung/origen/mem_setup.S new file mode 100644 index 0000000000..a798848ba1 --- /dev/null +++ b/board/samsung/origen/mem_setup.S @@ -0,0 +1,421 @@ +/* + * Memory setup for ORIGEN board based on S5PV310 + * + * Copyright (C) 2011 Samsung Electronics + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include "origen_setup.h" +#define SET_MIU + + .globl mem_ctrl_asm_init +mem_ctrl_asm_init: + /* + * Async bridge configuration at CPU_core: + * 1: half_sync + * 0: full_sync + */ + ldr r0, =ASYNC_CONFIG + mov r1, #1 + str r1, [r0] + +#ifdef SET_MIU + ldr r0, =S5PC210_MIU_BASE + /* Interleave: 2Bit, Interleave_bit1: 0x21, Interleave_bit2: 0x7 */ + ldr r1, =0x20001507 + str r1, [r0, #APB_SFR_INTERLEAVE_CONF_OFFSET] + + /* Update MIU Configuration */ + ldr r1, =0x00000001 + str r1, [r0, #APB_SFR_ARBRITATION_CONF_OFFSET] +#endif + /* DREX0 */ + ldr r0, =S5PC210_DMC0_BASE + + /* + * DLL Parameter Setting: + * Termination: Enable R/W + * Phase Delay for DQS Cleaning: 180' Shift + */ + ldr r1, =0xe0000086 + str r1, [r0, #DMC_PHYCONTROL1] + + /* + * ZQ Calibration + * Termination: Disable + * Auto Calibration Start: Enable + */ + ldr r1, =0xE3855703 + str r1, [r0, #DMC_PHYZQCONTROL] + + /* Wait ?us*/ + mov r2, #0x100000 +1: subs r2, r2, #1 + bne 1b + + /* + * Update DLL Information: + * Force DLL Resyncronization + */ + ldr r1, =0xe000008e + str r1, [r0, #DMC_PHYCONTROL1] + + /* Reset Force DLL Resyncronization */ + ldr r1, =0xe0000086 + str r1, [r0, #DMC_PHYCONTROL1] + + /* Enable Differential DQS, DLL Off*/ + ldr r1, =0x71101008 + str r1, [r0, #DMC_PHYCONTROL0] + + /* Activate PHY DLL: DLL On */ + ldr r1, =0x7110100A + str r1, [r0, #DMC_PHYCONTROL0] + + /* Set DLL Parameters */ + ldr r1, =0xe0000086 + str r1, [r0, #DMC_PHYCONTROL1] + + /* DLL Start */ + ldr r1, =0x7110100B + str r1, [r0, #DMC_PHYCONTROL0] + + ldr r1, =0x00000000 + str r1, [r0, #DMC_PHYCONTROL2] + + /* Set Clock Ratio of Bus clock to Memory Clock */ + ldr r1, =0x0FFF301a + str r1, [r0, #DMC_CONCONTROL] + + /* + * Memor Burst length: 8 + * Number of chips: 2 + * Memory Bus width: 32 bit + * Memory Type: DDR3 + * Additional Latancy for PLL: 1 Cycle + */ + ldr r1, =0x00312640 + str r1, [r0, #DMC_MEMCONTROL] + + /* + * Memory Configuration Chip 0 + * Address Mapping: Interleaved + * Number of Column address Bits: 10 bits + * Number of Rows Address Bits: 14 + * Number of Banks: 8 + */ + ldr r1, =0x20e01323 + str r1, [r0, #DMC_MEMCONFIG0] + + /* + * Memory Configuration Chip 1 + * Address Mapping: Interleaved + * Number of Column address Bits: 10 bits + * Number of Rows Address Bits: 14 + * Number of Banks: 8 + */ + ldr r1, =0x40e01323 + str r1, [r0, #DMC_MEMCONFIG1] + + /* Config Precharge Policy */ + ldr r1, =0xff000000 + str r1, [r0, #DMC_PRECHCONFIG] + + /* + * TimingAref, TimingRow, TimingData, TimingPower Setting: + * Values as per Memory AC Parameters + */ + ldr r1, =0x000000BB + str r1, [r0, #DMC_TIMINGAREF] + ldr r1, =0x4046654f + str r1, [r0, #DMC_TIMINGROW] + ldr r1, =0x46400506 + str r1, [r0, #DMC_TIMINGDATA] + ldr r1, =0x52000A3C + str r1, [r0, #DMC_TIMINGPOWER] + + /* Chip0: NOP Command: Assert and Hold CKE to high level */ + ldr r1, =0x07000000 + str r1, [r0, #DMC_DIRECTCMD] + + /* Wait ?us*/ + mov r2, #0x100000 +2: subs r2, r2, #1 + bne 2b + + /* Chip0: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */ + ldr r1, =0x00020000 + str r1, [r0, #DMC_DIRECTCMD] + ldr r1, =0x00030000 + str r1, [r0, #DMC_DIRECTCMD] + ldr r1, =0x00010002 + str r1, [r0, #DMC_DIRECTCMD] + ldr r1, =0x00000328 + str r1, [r0, #DMC_DIRECTCMD] + + /* Wait ?us*/ + mov r2, #0x100000 +3: subs r2, r2, #1 + bne 3b + + /* Chip0: ZQINIT */ + ldr r1, =0x0a000000 + str r1, [r0, #DMC_DIRECTCMD] + + /* Wait ?us*/ + mov r2, #0x100000 +4: subs r2, r2, #1 + bne 4b + + /* Chip1: NOP Command: Assert and Hold CKE to high level */ + ldr r1, =0x07100000 + str r1, [r0, #DMC_DIRECTCMD] + + /* Wait ?us*/ + mov r2, #0x100000 +5: subs r2, r2, #1 + bne 5b + + /* Chip1: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */ + ldr r1, =0x00120000 + str r1, [r0, #DMC_DIRECTCMD] + ldr r1, =0x00130000 + str r1, [r0, #DMC_DIRECTCMD] + ldr r1, =0x00110002 + str r1, [r0, #DMC_DIRECTCMD] + ldr r1, =0x00100328 + str r1, [r0, #DMC_DIRECTCMD] + + /* Wait ?us*/ + mov r2, #0x100000 +6: subs r2, r2, #1 + bne 6b + + /* Chip1: ZQINIT */ + ldr r1, =0x0a100000 + str r1, [r0, #DMC_DIRECTCMD] + + /* Wait ?us*/ + mov r2, #0x100000 +7: subs r2, r2, #1 + bne 7b + + ldr r1, =0xe000008e + str r1, [r0, #DMC_PHYCONTROL1] + ldr r1, =0xe0000086 + str r1, [r0, #DMC_PHYCONTROL1] + + /* Wait ?us*/ + mov r2, #0x100000 +8: subs r2, r2, #1 + bne 8b + + /* DREX1 */ + ldr r0, =S5PC210_DMC1_BASE @0x10410000 + + /* + * DLL Parameter Setting: + * Termination: Enable R/W + * Phase Delay for DQS Cleaning: 180' Shift + */ + ldr r1, =0xe0000086 + str r1, [r0, #DMC_PHYCONTROL1] + + /* + * ZQ Calibration: + * Termination: Disable + * Auto Calibration Start: Enable + */ + ldr r1, =0xE3855703 + str r1, [r0, #DMC_PHYZQCONTROL] + + /* Wait ?us*/ + mov r2, #0x100000 +1: subs r2, r2, #1 + bne 1b + + /* + * Update DLL Information: + * Force DLL Resyncronization + */ + ldr r1, =0xe000008e + str r1, [r0, #DMC_PHYCONTROL1] + + /* Reset Force DLL Resyncronization */ + ldr r1, =0xe0000086 + str r1, [r0, #DMC_PHYCONTROL1] + + /* Enable Differential DQS, DLL Off*/ + ldr r1, =0x71101008 + str r1, [r0, #DMC_PHYCONTROL0] + + /* Activate PHY DLL: DLL On */ + ldr r1, =0x7110100A + str r1, [r0, #DMC_PHYCONTROL0] + + /* Set DLL Parameters */ + ldr r1, =0xe0000086 + str r1, [r0, #DMC_PHYCONTROL1] + + /* DLL Start */ + ldr r1, =0x7110100B + str r1, [r0, #DMC_PHYCONTROL0] + + ldr r1, =0x00000000 + str r1, [r0, #DMC_PHYCONTROL2] + + /* Set Clock Ratio of Bus clock to Memory Clock */ + ldr r1, =0x0FFF301a + str r1, [r0, #DMC_CONCONTROL] + + /* + * Memor Burst length: 8 + * Number of chips: 2 + * Memory Bus width: 32 bit + * Memory Type: DDR3 + * Additional Latancy for PLL: 1 Cycle + */ + ldr r1, =0x00312640 + str r1, [r0, #DMC_MEMCONTROL] + + /* + * Memory Configuration Chip 0 + * Address Mapping: Interleaved + * Number of Column address Bits: 10 bits + * Number of Rows Address Bits: 14 + * Number of Banks: 8 + */ + ldr r1, =0x20e01323 + str r1, [r0, #DMC_MEMCONFIG0] + + /* + * Memory Configuration Chip 1 + * Address Mapping: Interleaved + * Number of Column address Bits: 10 bits + * Number of Rows Address Bits: 14 + * Number of Banks: 8 + */ + ldr r1, =0x40e01323 + str r1, [r0, #DMC_MEMCONFIG1] + + /* Config Precharge Policy */ + ldr r1, =0xff000000 + str r1, [r0, #DMC_PRECHCONFIG] + + /* + * TimingAref, TimingRow, TimingData, TimingPower Setting: + * Values as per Memory AC Parameters + */ + ldr r1, =0x000000BB + str r1, [r0, #DMC_TIMINGAREF] + ldr r1, =0x4046654f + str r1, [r0, #DMC_TIMINGROW] + ldr r1, =0x46400506 + str r1, [r0, #DMC_TIMINGDATA] + ldr r1, =0x52000A3C + str r1, [r0, #DMC_TIMINGPOWER] + + /* Chip0: NOP Command: Assert and Hold CKE to high level */ + ldr r1, =0x07000000 + str r1, [r0, #DMC_DIRECTCMD] + + /* Wait ?us*/ + mov r2, #0x100000 +2: subs r2, r2, #1 + bne 2b + + /* Chip0: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */ + ldr r1, =0x00020000 + str r1, [r0, #DMC_DIRECTCMD] + ldr r1, =0x00030000 + str r1, [r0, #DMC_DIRECTCMD] + ldr r1, =0x00010002 + str r1, [r0, #DMC_DIRECTCMD] + ldr r1, =0x00000328 + str r1, [r0, #DMC_DIRECTCMD] + + /* Wait ?us*/ + mov r2, #0x100000 +3: subs r2, r2, #1 + bne 3b + + /* Chip 0: ZQINIT */ + ldr r1, =0x0a000000 + str r1, [r0, #DMC_DIRECTCMD] + + /* Wait ?us*/ + mov r2, #0x100000 +4: subs r2, r2, #1 + bne 4b + + /* Chip1: NOP Command: Assert and Hold CKE to high level */ + ldr r1, =0x07100000 + str r1, [r0, #DMC_DIRECTCMD] + + /* Wait ?us*/ + mov r2, #0x100000 +5: subs r2, r2, #1 + bne 5b + + /* Chip1: EMRS2, EMRS3, EMRS, MRS Commands Using Direct Command */ + ldr r1, =0x00120000 + str r1, [r0, #DMC_DIRECTCMD] + ldr r1, =0x00130000 + str r1, [r0, #DMC_DIRECTCMD] + ldr r1, =0x00110002 + str r1, [r0, #DMC_DIRECTCMD] + ldr r1, =0x00100328 + str r1, [r0, #DMC_DIRECTCMD] + + /* Wait ?us*/ + mov r2, #0x100000 +6: subs r2, r2, #1 + bne 6b + + /* Chip1: ZQINIT */ + ldr r1, =0x0a100000 + str r1, [r0, #DMC_DIRECTCMD] + + /* Wait ?us*/ + mov r2, #0x100000 +7: subs r2, r2, #1 + bne 7b + + ldr r1, =0xe000008e + str r1, [r0, #DMC_PHYCONTROL1] + ldr r1, =0xe0000086 + str r1, [r0, #DMC_PHYCONTROL1] + + /* Wait ?us*/ + mov r2, #0x100000 +8: subs r2, r2, #1 + bne 8b + + /* turn on DREX0, DREX1 */ + ldr r0, =S5PC210_DMC0_BASE + ldr r1, =0x0FFF303a + str r1, [r0, #DMC_CONCONTROL] + + ldr r0, =S5PC210_DMC1_BASE + ldr r1, =0x0FFF303a + str r1, [r0, #DMC_CONCONTROL] + + mov pc, lr diff --git a/board/samsung/origen/mmc_boot.c b/board/samsung/origen/mmc_boot.c new file mode 100644 index 0000000000..072f16146c --- /dev/null +++ b/board/samsung/origen/mmc_boot.c @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2011 Samsung Electronics + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include<common.h> +#include<config.h> + +/* +* Copy U-boot from mmc to RAM: +* COPY_BL2_FNPTR_ADDR: Address in iRAM, which Contains +* Pointer to API (Data transfer from mmc to ram) +*/ +void copy_uboot_to_ram(void) +{ + u32 (*copy_bl2)(u32, u32, u32) = (void *) *(u32 *)COPY_BL2_FNPTR_ADDR; + + copy_bl2(BL2_START_OFFSET, BL2_SIZE_BLOC_COUNT, CONFIG_SYS_TEXT_BASE); +} + +void board_init_f(unsigned long bootflag) +{ + __attribute__((noreturn)) void (*uboot)(void); + copy_uboot_to_ram(); + + /* Jump to U-Boot image */ + uboot = (void *)CONFIG_SYS_TEXT_BASE; + (*uboot)(); + /* Never returns Here */ +} + +/* Place Holders */ +void board_init_r(gd_t *id, ulong dest_addr) +{ + /* Function attribute is no-return */ + /* This Function never executes */ + while (1) + ; +} + +void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3) {} diff --git a/board/samsung/origen/origen.c b/board/samsung/origen/origen.c new file mode 100644 index 0000000000..8882646eca --- /dev/null +++ b/board/samsung/origen/origen.c @@ -0,0 +1,109 @@ +/* + * Copyright (C) 2011 Samsung Electronics + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/gpio.h> +#include <asm/arch/mmc.h> + +DECLARE_GLOBAL_DATA_PTR; +struct s5pc210_gpio_part1 *gpio1; +struct s5pc210_gpio_part2 *gpio2; + +int board_init(void) +{ + gpio1 = (struct s5pc210_gpio_part1 *) S5PC210_GPIO_PART1_BASE; + gpio2 = (struct s5pc210_gpio_part2 *) S5PC210_GPIO_PART2_BASE; + + gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL); + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) + + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) + + get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) + + get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE); + + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1, \ + PHYS_SDRAM_1_SIZE); + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2, \ + PHYS_SDRAM_2_SIZE); + gd->bd->bi_dram[2].start = PHYS_SDRAM_3; + gd->bd->bi_dram[2].size = get_ram_size((long *)PHYS_SDRAM_3, \ + PHYS_SDRAM_3_SIZE); + gd->bd->bi_dram[3].start = PHYS_SDRAM_4; + gd->bd->bi_dram[3].size = get_ram_size((long *)PHYS_SDRAM_4, \ + PHYS_SDRAM_4_SIZE); +} + +#ifdef CONFIG_DISPLAY_BOARDINFO +int checkboard(void) +{ + printf("\nBoard: ORIGEN\n"); + return 0; +} +#endif + +#ifdef CONFIG_GENERIC_MMC +int board_mmc_init(bd_t *bis) +{ + int i, err; + + /* + * MMC2 SD card GPIO: + * + * GPK2[0] SD_2_CLK(2) + * GPK2[1] SD_2_CMD(2) + * GPK2[2] SD_2_CDn + * GPK2[3:6] SD_2_DATA[0:3](2) + */ + for (i = 0; i < 7; i++) { + /* GPK2[0:6] special function 2 */ + s5p_gpio_cfg_pin(&gpio2->k2, i, GPIO_FUNC(0x2)); + + /* GPK2[0:6] drv 4x */ + s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X); + + /* GPK2[0:1] pull disable */ + if (i == 0 || i == 1) { + s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE); + continue; + } + + /* GPK2[2:6] pull up */ + s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_UP); + } + + err = s5p_mmc_init(2, 4); + return err; +} +#endif diff --git a/board/samsung/origen/origen_setup.h b/board/samsung/origen/origen_setup.h new file mode 100644 index 0000000000..63d85d8a8c --- /dev/null +++ b/board/samsung/origen/origen_setup.h @@ -0,0 +1,546 @@ +/* + * Machine Specific Values for ORIGEN board based on S5PV310 + * + * Copyright (C) 2011 Samsung Electronics + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ORIGEN_SETUP_H +#define _ORIGEN_SETUP_H + +#include <config.h> +#include <version.h> +#include <asm/arch/cpu.h> + +/* Offsets of clock registers (sources and dividers) */ +#define CLK_SRC_CPU_OFFSET 0x14200 +#define CLK_DIV_CPU0_OFFSET 0x14500 +#define CLK_DIV_CPU1_OFFSET 0x14504 + +#define CLK_SRC_DMC_OFFSET 0x10200 +#define CLK_DIV_DMC0_OFFSET 0x10500 +#define CLK_DIV_DMC1_OFFSET 0x10504 + +#define CLK_SRC_TOP0_OFFSET 0xC210 +#define CLK_SRC_TOP1_OFFSET 0xC214 +#define CLK_DIV_TOP_OFFSET 0xC510 + +#define CLK_SRC_LEFTBUS_OFFSET 0x4200 +#define CLK_DIV_LEFTBUS_OFFSET 0x4500 + +#define CLK_SRC_RIGHTBUS_OFFSET 0x8200 +#define CLK_DIV_RIGHTBUS_OFFSET 0x8500 + +#define CLK_SRC_FSYS_OFFSET 0xC240 +#define CLK_DIV_FSYS1_OFFSET 0xC544 +#define CLK_DIV_FSYS2_OFFSET 0xC548 +#define CLK_DIV_FSYS3_OFFSET 0xC54C + +#define CLK_SRC_PERIL0_OFFSET 0xC250 +#define CLK_DIV_PERIL0_OFFSET 0xC550 + +#define APLL_LOCK_OFFSET 0x14000 +#define MPLL_LOCK_OFFSET 0x14008 +#define APLL_CON0_OFFSET 0x14100 +#define APLL_CON1_OFFSET 0x14104 +#define MPLL_CON0_OFFSET 0x14108 +#define MPLL_CON1_OFFSET 0x1410C + +#define EPLL_LOCK_OFFSET 0xC010 +#define VPLL_LOCK_OFFSET 0xC020 +#define EPLL_CON0_OFFSET 0xC110 +#define EPLL_CON1_OFFSET 0xC114 +#define VPLL_CON0_OFFSET 0xC120 +#define VPLL_CON1_OFFSET 0xC124 + +/* DMC: DRAM Controllor Register offsets */ +#define DMC_CONCONTROL 0x00 +#define DMC_MEMCONTROL 0x04 +#define DMC_MEMCONFIG0 0x08 +#define DMC_MEMCONFIG1 0x0C +#define DMC_DIRECTCMD 0x10 +#define DMC_PRECHCONFIG 0x14 +#define DMC_PHYCONTROL0 0x18 +#define DMC_PHYCONTROL1 0x1C +#define DMC_PHYCONTROL2 0x20 +#define DMC_TIMINGAREF 0x30 +#define DMC_TIMINGROW 0x34 +#define DMC_TIMINGDATA 0x38 +#define DMC_TIMINGPOWER 0x3C +#define DMC_PHYZQCONTROL 0x44 + +/* Bus Configuration Register Address */ +#define ASYNC_CONFIG 0x10010350 + +/* MIU Config Register Offsets*/ +#define APB_SFR_INTERLEAVE_CONF_OFFSET 0x400 +#define APB_SFR_ARBRITATION_CONF_OFFSET 0xC00 + +/* Offset for inform registers */ +#define INFORM0_OFFSET 0x800 +#define INFORM1_OFFSET 0x804 + +/* GPIO Offsets for UART: GPIO Contol Register */ +#define S5PC210_GPIO_A0_CON_OFFSET 0x00 +#define S5PC210_GPIO_A1_CON_OFFSET 0x20 + +/* UART Register offsets */ +#define ULCON_OFFSET 0x00 +#define UCON_OFFSET 0x04 +#define UFCON_OFFSET 0x08 +#define UBRDIV_OFFSET 0x28 +#define UFRACVAL_OFFSET 0x2C + +/* TZPC : Register Offsets */ +#define TZPC0_BASE 0x10110000 +#define TZPC1_BASE 0x10120000 +#define TZPC2_BASE 0x10130000 +#define TZPC3_BASE 0x10140000 +#define TZPC4_BASE 0x10150000 +#define TZPC5_BASE 0x10160000 + +#define TZPC_DECPROT0SET_OFFSET 0x804 +#define TZPC_DECPROT1SET_OFFSET 0x810 +#define TZPC_DECPROT2SET_OFFSET 0x81C +#define TZPC_DECPROT3SET_OFFSET 0x828 + +/* CLK_SRC_CPU */ +#define MUX_HPM_SEL_MOUTAPLL 0x0 +#define MUX_HPM_SEL_SCLKMPLL 0x1 +#define MUX_CORE_SEL_MOUTAPLL 0x0 +#define MUX_CORE_SEL_SCLKMPLL 0x1 +#define MUX_MPLL_SEL_FILPLL 0x0 +#define MUX_MPLL_SEL_MOUTMPLLFOUT 0x1 +#define MUX_APLL_SEL_FILPLL 0x0 +#define MUX_APLL_SEL_MOUTMPLLFOUT 0x1 +#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL_MOUTAPLL << 20) \ + | (MUX_CORE_SEL_MOUTAPLL << 16) \ + | (MUX_MPLL_SEL_MOUTMPLLFOUT << 8)\ + | (MUX_APLL_SEL_MOUTMPLLFOUT << 0)) + +/* CLK_DIV_CPU0 */ +#define APLL_RATIO 0x0 +#define PCLK_DBG_RATIO 0x1 +#define ATB_RATIO 0x3 +#define PERIPH_RATIO 0x3 +#define COREM1_RATIO 0x7 +#define COREM0_RATIO 0x3 +#define CORE_RATIO 0x0 +#define CLK_DIV_CPU0_VAL ((APLL_RATIO << 24) \ + | (PCLK_DBG_RATIO << 20) \ + | (ATB_RATIO << 16) \ + | (PERIPH_RATIO << 12) \ + | (COREM1_RATIO << 8) \ + | (COREM0_RATIO << 4) \ + | (CORE_RATIO << 0)) + +/* CLK_DIV_CPU1 */ +#define HPM_RATIO 0x0 +#define COPY_RATIO 0x3 +#define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) | (COPY_RATIO)) + +/* CLK_SRC_DMC */ +#define MUX_PWI_SEL_XXTI 0x0 +#define MUX_PWI_SEL_XUSBXTI 0x1 +#define MUX_PWI_SEL_SCLK_HDMI24M 0x2 +#define MUX_PWI_SEL_SCLK_USBPHY0 0x3 +#define MUX_PWI_SEL_SCLK_USBPHY1 0x4 +#define MUX_PWI_SEL_SCLK_HDMIPHY 0x5 +#define MUX_PWI_SEL_SCLKMPLL 0x6 +#define MUX_PWI_SEL_SCLKEPLL 0x7 +#define MUX_PWI_SEL_SCLKVPLL 0x8 +#define MUX_DPHY_SEL_SCLKMPLL 0x0 +#define MUX_DPHY_SEL_SCLKAPLL 0x1 +#define MUX_DMC_BUS_SEL_SCLKMPLL 0x0 +#define MUX_DMC_BUS_SEL_SCLKAPLL 0x1 +#define CLK_SRC_DMC_VAL ((MUX_PWI_SEL_XUSBXTI << 16) \ + | (MUX_DPHY_SEL_SCLKMPLL << 8) \ + | (MUX_DMC_BUS_SEL_SCLKMPLL << 4)) + +/* CLK_DIV_DMC0 */ +#define CORE_TIMERS_RATIO 0x1 +#define COPY2_RATIO 0x3 +#define DMCP_RATIO 0x1 +#define DMCD_RATIO 0x1 +#define DMC_RATIO 0x1 +#define DPHY_RATIO 0x1 +#define ACP_PCLK_RATIO 0x1 +#define ACP_RATIO 0x3 +#define CLK_DIV_DMC0_VAL ((CORE_TIMERS_RATIO << 28) \ + | (COPY2_RATIO << 24) \ + | (DMCP_RATIO << 20) \ + | (DMCD_RATIO << 16) \ + | (DMC_RATIO << 12) \ + | (DPHY_RATIO << 8) \ + | (ACP_PCLK_RATIO << 4) \ + | (ACP_RATIO << 0)) + +/* CLK_DIV_DMC1 */ +#define DPM_RATIO 0x1 +#define DVSEM_RATIO 0x1 +#define PWI_RATIO 0x1 +#define CLK_DIV_DMC1_VAL ((DPM_RATIO << 24) \ + | (DVSEM_RATIO << 16) \ + | (PWI_RATIO << 8)) + +/* CLK_SRC_TOP0 */ +#define MUX_ONENAND_SEL_ACLK_133 0x0 +#define MUX_ONENAND_SEL_ACLK_160 0x1 +#define MUX_ACLK_133_SEL_SCLKMPLL 0x0 +#define MUX_ACLK_133_SEL_SCLKAPLL 0x1 +#define MUX_ACLK_160_SEL_SCLKMPLL 0x0 +#define MUX_ACLK_160_SEL_SCLKAPLL 0x1 +#define MUX_ACLK_100_SEL_SCLKMPLL 0x0 +#define MUX_ACLK_100_SEL_SCLKAPLL 0x1 +#define MUX_ACLK_200_SEL_SCLKMPLL 0x0 +#define MUX_ACLK_200_SEL_SCLKAPLL 0x1 +#define MUX_VPLL_SEL_FINPLL 0x0 +#define MUX_VPLL_SEL_FOUTVPLL 0x1 +#define MUX_EPLL_SEL_FINPLL 0x0 +#define MUX_EPLL_SEL_FOUTEPLL 0x1 +#define MUX_ONENAND_1_SEL_MOUTONENAND 0x0 +#define MUX_ONENAND_1_SEL_SCLKVPLL 0x1 +#define CLK_SRC_TOP0_VAL ((MUX_ONENAND_SEL_ACLK_133 << 28) \ + | (MUX_ACLK_133_SEL_SCLKMPLL << 24) \ + | (MUX_ACLK_160_SEL_SCLKMPLL << 20) \ + | (MUX_ACLK_100_SEL_SCLKMPLL << 16) \ + | (MUX_ACLK_200_SEL_SCLKMPLL << 12) \ + | (MUX_VPLL_SEL_FINPLL << 8) \ + | (MUX_EPLL_SEL_FINPLL << 4)\ + | (MUX_ONENAND_1_SEL_MOUTONENAND << 0)) + +/* CLK_SRC_TOP1 */ +#define VPLLSRC_SEL_FINPLL 0x0 +#define VPLLSRC_SEL_SCLKHDMI24M 0x1 +#define CLK_SRC_TOP1_VAL (VPLLSRC_SEL_FINPLL) + +/* CLK_DIV_TOP */ +#define ONENAND_RATIO 0x0 +#define ACLK_133_RATIO 0x5 +#define ACLK_160_RATIO 0x4 +#define ACLK_100_RATIO 0x7 +#define ACLK_200_RATIO 0x3 +#define CLK_DIV_TOP_VAL ((ONENAND_RATIO << 16) \ + | (ACLK_133_RATIO << 12)\ + | (ACLK_160_RATIO << 8) \ + | (ACLK_100_RATIO << 4) \ + | (ACLK_200_RATIO << 0)) + +/* CLK_SRC_LEFTBUS */ +#define MUX_GDL_SEL_SCLKMPLL 0x0 +#define MUX_GDL_SEL_SCLKAPLL 0x1 +#define CLK_SRC_LEFTBUS_VAL (MUX_GDL_SEL_SCLKMPLL) + +/* CLK_DIV_LEFTBUS */ +#define GPL_RATIO 0x1 +#define GDL_RATIO 0x3 +#define CLK_DIV_LEFTBUS_VAL ((GPL_RATIO << 4) | (GDL_RATIO)) + +/* CLK_SRC_RIGHTBUS */ +#define MUX_GDR_SEL_SCLKMPLL 0x0 +#define MUX_GDR_SEL_SCLKAPLL 0x1 +#define CLK_SRC_RIGHTBUS_VAL (MUX_GDR_SEL_SCLKMPLL) + +/* CLK_DIV_RIGHTBUS */ +#define GPR_RATIO 0x1 +#define GDR_RATIO 0x3 +#define CLK_DIV_RIGHTBUS_VAL ((GPR_RATIO << 4) | (GDR_RATIO)) + +/* CLK_SRS_FSYS: 6 = SCLKMPLL */ +#define SATA_SEL_SCLKMPLL 0 +#define SATA_SEL_SCLKAPLL 1 + +#define MMC_SEL_XXTI 0 +#define MMC_SEL_XUSBXTI 1 +#define MMC_SEL_SCLK_HDMI24M 2 +#define MMC_SEL_SCLK_USBPHY0 3 +#define MMC_SEL_SCLK_USBPHY1 4 +#define MMC_SEL_SCLK_HDMIPHY 5 +#define MMC_SEL_SCLKMPLL 6 +#define MMC_SEL_SCLKEPLL 7 +#define MMC_SEL_SCLKVPLL 8 + +#define MMCC0_SEL MMC_SEL_SCLKMPLL +#define MMCC1_SEL MMC_SEL_SCLKMPLL +#define MMCC2_SEL MMC_SEL_SCLKMPLL +#define MMCC3_SEL MMC_SEL_SCLKMPLL +#define MMCC4_SEL MMC_SEL_SCLKMPLL +#define CLK_SRC_FSYS_VAL ((SATA_SEL_SCLKMPLL << 24) \ + | (MMCC4_SEL << 16) \ + | (MMCC3_SEL << 12) \ + | (MMCC2_SEL << 8) \ + | (MMCC1_SEL << 4) \ + | (MMCC0_SEL << 0)) + +/* SCLK_MMC[0-4] = MOUTMMC[0-4]/(MMC[0-4]_RATIO + 1)/(MMC[0-4]_PRE_RATIO +1) */ +/* CLK_DIV_FSYS1 */ +#define MMC0_RATIO 0xF +#define MMC0_PRE_RATIO 0x0 +#define MMC1_RATIO 0xF +#define MMC1_PRE_RATIO 0x0 +#define CLK_DIV_FSYS1_VAL ((MMC1_PRE_RATIO << 24) \ + | (MMC1_RATIO << 16) \ + | (MMC0_PRE_RATIO << 8) \ + | (MMC0_RATIO << 0)) + +/* CLK_DIV_FSYS2 */ +#define MMC2_RATIO 0xF +#define MMC2_PRE_RATIO 0x0 +#define MMC3_RATIO 0xF +#define MMC3_PRE_RATIO 0x0 +#define CLK_DIV_FSYS2_VAL ((MMC3_PRE_RATIO << 24) \ + | (MMC3_RATIO << 16) \ + | (MMC2_PRE_RATIO << 8) \ + | (MMC2_RATIO << 0)) + +/* CLK_DIV_FSYS3 */ +#define MMC4_RATIO 0xF +#define MMC4_PRE_RATIO 0x0 +#define CLK_DIV_FSYS3_VAL ((MMC4_PRE_RATIO << 8) \ + | (MMC4_RATIO << 0)) + +/* CLK_SRC_PERIL0 */ +#define UART_SEL_XXTI 0 +#define UART_SEL_XUSBXTI 1 +#define UART_SEL_SCLK_HDMI24M 2 +#define UART_SEL_SCLK_USBPHY0 3 +#define UART_SEL_SCLK_USBPHY1 4 +#define UART_SEL_SCLK_HDMIPHY 5 +#define UART_SEL_SCLKMPLL 6 +#define UART_SEL_SCLKEPLL 7 +#define UART_SEL_SCLKVPLL 8 + +#define UART0_SEL UART_SEL_SCLKMPLL +#define UART1_SEL UART_SEL_SCLKMPLL +#define UART2_SEL UART_SEL_SCLKMPLL +#define UART3_SEL UART_SEL_SCLKMPLL +#define UART4_SEL UART_SEL_SCLKMPLL +#define CLK_SRC_PERIL0_VAL ((UART4_SEL << 16) \ + | (UART3_SEL << 12) \ + | (UART2_SEL << 8) \ + | (UART1_SEL << 4) \ + | (UART0_SEL << 0)) + +/* SCLK_UART[0-4] = MOUTUART[0-4]/(UART[0-4]_RATIO + 1) */ +/* CLK_DIV_PERIL0 */ +#define UART0_RATIO 7 +#define UART1_RATIO 7 +#define UART2_RATIO 7 +#define UART3_RATIO 7 +#define UART4_RATIO 7 +#define CLK_DIV_PERIL0_VAL ((UART4_RATIO << 16) \ + | (UART3_RATIO << 12) \ + | (UART2_RATIO << 8) \ + | (UART1_RATIO << 4) \ + | (UART0_RATIO << 0)) + +/* Required period to generate a stable clock output */ +/* PLL_LOCK_TIME */ +#define PLL_LOCKTIME 0x1C20 + +/* PLL Values */ +#define DISABLE 0 +#define ENABLE 1 +#define SET_PLL(mdiv, pdiv, sdiv) ((ENABLE << 31)\ + | (mdiv << 16) \ + | (pdiv << 8) \ + | (sdiv << 0)) + +/* APLL_CON0 */ +#define APLL_MDIV 0xFA +#define APLL_PDIV 0x6 +#define APLL_SDIV 0x1 +#define APLL_CON0_VAL SET_PLL(APLL_MDIV, APLL_PDIV, APLL_SDIV) + +/* APLL_CON1 */ +#define APLL_AFC_ENB 0x1 +#define APLL_AFC 0xC +#define APLL_CON1_VAL ((APLL_AFC_ENB << 31) | (APLL_AFC << 0)) + +/* MPLL_CON0 */ +#define MPLL_MDIV 0xC8 +#define MPLL_PDIV 0x6 +#define MPLL_SDIV 0x1 +#define MPLL_CON0_VAL SET_PLL(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV) + +/* MPLL_CON1 */ +#define MPLL_AFC_ENB 0x0 +#define MPLL_AFC 0x1C +#define MPLL_CON1_VAL ((MPLL_AFC_ENB << 31) | (MPLL_AFC << 0)) + +/* EPLL_CON0 */ +#define EPLL_MDIV 0x30 +#define EPLL_PDIV 0x3 +#define EPLL_SDIV 0x2 +#define EPLL_CON0_VAL SET_PLL(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV) + +/* EPLL_CON1 */ +#define EPLL_K 0x0 +#define EPLL_CON1_VAL (EPLL_K >> 0) + +/* VPLL_CON0 */ +#define VPLL_MDIV 0x35 +#define VPLL_PDIV 0x3 +#define VPLL_SDIV 0x2 +#define VPLL_CON0_VAL SET_PLL(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV) + +/* VPLL_CON1 */ +#define VPLL_SSCG_EN DISABLE +#define VPLL_SEL_PF_DN_SPREAD 0x0 +#define VPLL_MRR 0x11 +#define VPLL_MFR 0x0 +#define VPLL_K 0x400 +#define VPLL_CON1_VAL ((VPLL_SSCG_EN << 31)\ + | (VPLL_SEL_PF_DN_SPREAD << 29) \ + | (VPLL_MRR << 24) \ + | (VPLL_MFR << 16) \ + | (VPLL_K << 0)) +/* + * UART GPIO_A0/GPIO_A1 Control Register Value + * 0x2: UART Function + */ +#define S5PC210_GPIO_A0_CON_VAL 0x22222222 +#define S5PC210_GPIO_A1_CON_VAL 0x222222 + +/* ULCON: UART Line Control Value 8N1 */ +#define WORD_LEN_5_BIT 0x00 +#define WORD_LEN_6_BIT 0x01 +#define WORD_LEN_7_BIT 0x02 +#define WORD_LEN_8_BIT 0x03 + +#define STOP_BIT_1 0x00 +#define STOP_BIT_2 0x01 + +#define NO_PARITY 0x00 +#define ODD_PARITY 0x4 +#define EVEN_PARITY 0x5 +#define FORCED_PARITY_CHECK_AS_1 0x6 +#define FORCED_PARITY_CHECK_AS_0 0x7 + +#define INFRAMODE_NORMAL 0x00 +#define INFRAMODE_INFRARED 0x01 + +#define ULCON_VAL ((INFRAMODE_NORMAL << 6) \ + | (NO_PARITY << 3) \ + | (STOP_BIT_1 << 2) \ + | (WORD_LEN_8_BIT << 0)) + +/* + * UCON: UART Control Value + * Tx_interrupt Type: Level + * Rx_interrupt Type: Level + * Rx Timeout Enabled: Yes + * Rx-Error Atatus_Int Enable: Yes + * Loop_Back: No + * Break Signal: No + * Transmit mode : Interrupt request/polling + * Receive mode : Interrupt request/polling + */ +#define TX_PULSE_INTERRUPT 0 +#define TX_LEVEL_INTERRUPT 1 +#define RX_PULSE_INTERRUPT 0 +#define RX_LEVEL_INTERRUPT 1 + +#define RX_TIME_OUT ENABLE +#define RX_ERROR_STATE_INT_ENB ENABLE +#define LOOP_BACK DISABLE +#define BREAK_SIGNAL DISABLE + +#define TX_MODE_DISABLED 0X00 +#define TX_MODE_IRQ_OR_POLL 0X01 +#define TX_MODE_DMA 0X02 + +#define RX_MODE_DISABLED 0X00 +#define RX_MODE_IRQ_OR_POLL 0X01 +#define RX_MODE_DMA 0X02 + +#define UCON_VAL ((TX_LEVEL_INTERRUPT << 9) \ + | (RX_LEVEL_INTERRUPT << 8) \ + | (RX_TIME_OUT << 7) \ + | (RX_ERROR_STATE_INT_ENB << 6) \ + | (LOOP_BACK << 5) \ + | (BREAK_SIGNAL << 4) \ + | (TX_MODE_IRQ_OR_POLL << 2) \ + | (RX_MODE_IRQ_OR_POLL << 0)) + +/* + * UFCON: UART FIFO Control Value + * Tx FIFO Trigger LEVEL: 2 Bytes (001) + * Rx FIFO Trigger LEVEL: 2 Bytes (001) + * Tx Fifo Reset: No + * Rx Fifo Reset: No + * FIFO Enable: Yes + */ +#define TX_FIFO_TRIGGER_LEVEL_0_BYTES 0x00 +#define TX_FIFO_TRIGGER_LEVEL_2_BYTES 0x1 +#define TX_FIFO_TRIGGER_LEVEL_4_BYTES 0x2 +#define TX_FIFO_TRIGGER_LEVEL_6_BYTES 0x3 +#define TX_FIFO_TRIGGER_LEVEL_8_BYTES 0x4 +#define TX_FIFO_TRIGGER_LEVEL_10_BYTES 0x5 +#define TX_FIFO_TRIGGER_LEVEL_12_BYTES 0x6 +#define TX_FIFO_TRIGGER_LEVEL_14_BYTES 0x7 + +#define RX_FIFO_TRIGGER_LEVEL_2_BYTES 0x0 +#define RX_FIFO_TRIGGER_LEVEL_4_BYTES 0x1 +#define RX_FIFO_TRIGGER_LEVEL_6_BYTES 0x2 +#define RX_FIFO_TRIGGER_LEVEL_8_BYTES 0x3 +#define RX_FIFO_TRIGGER_LEVEL_10_BYTES 0x4 +#define RX_FIFO_TRIGGER_LEVEL_12_BYTES 0x5 +#define RX_FIFO_TRIGGER_LEVEL_14_BYTES 0x6 +#define RX_FIFO_TRIGGER_LEVEL_16_BYTES 0x7 + +#define TX_FIFO_TRIGGER_LEVEL TX_FIFO_TRIGGER_LEVEL_2_BYTES +#define RX_FIFO_TRIGGER_LEVEL RX_FIFO_TRIGGER_LEVEL_4_BYTES +#define TX_FIFO_RESET DISABLE +#define RX_FIFO_RESET DISABLE +#define FIFO_ENABLE ENABLE +#define UFCON_VAL ((TX_FIFO_TRIGGER_LEVEL << 8) \ + | (RX_FIFO_TRIGGER_LEVEL << 4) \ + | (TX_FIFO_RESET << 2) \ + | (RX_FIFO_RESET << 1) \ + | (FIFO_ENABLE << 0)) +/* + * Baud Rate Division Value + * 115200 BAUD: + * UBRDIV_VAL = SCLK_UART/((115200 * 16) - 1) + * UBRDIV_VAL = (800 MHz)/((115200 * 16) - 1) + */ +#define UBRDIV_VAL 0x35 + +/* + * Fractional Part of Baud Rate Divisor: + * 115200 BAUD: + * UBRFRACVAL = ((((SCLK_UART*10/(115200*16) -10))%10)*16/10) + * UBRFRACVAL = ((((800MHz*10/(115200*16) -10))%10)*16/10) + */ +#define UFRACVAL_VAL 0x4 + +/* + * TZPC Register Value : + * R0SIZE: 0x0 : Size of secured ram + */ +#define R0SIZE 0x0 + +/* + * TZPC Decode Protection Register Value : + * DECPROTXSET: 0xFF : Set Decode region to non-secure + */ +#define DECPROTXSET 0xFF +#endif diff --git a/board/samsung/origen/tools/mkv310_image.c b/board/samsung/origen/tools/mkv310_image.c new file mode 100644 index 0000000000..158aab5cf9 --- /dev/null +++ b/board/samsung/origen/tools/mkv310_image.c @@ -0,0 +1,126 @@ +/* + * Copyright (C) 2011 Samsung Electronics + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <stdio.h> +#include <stdlib.h> +#include <unistd.h> +#include <fcntl.h> +#include <errno.h> +#include <string.h> +#include <sys/stat.h> + +#define BUFSIZE (16*1024) +#define IMG_SIZE (16*1024) +#define SPL_HEADER_SIZE 16 +#define FILE_PERM (S_IRUSR | S_IWUSR | S_IRGRP \ + | S_IWGRP | S_IROTH | S_IWOTH) +#define SPL_HEADER "S5PC210 HEADER " +/* +* Requirement: +* IROM code reads first 14K bytes from boot device. +* It then calculates the checksum of 14K-4 bytes and compare with data at +* 14K-4 offset. +* +* This function takes two filenames: +* IN "u-boot-spl.bin" and +* OUT "$(BOARD)-spl.bin as filenames. +* It reads the "u-boot-spl.bin" in 16K buffer. +* It calculates checksum of 14K-4 Bytes and stores at 14K-4 offset in buffer. +* It writes the buffer to "$(BOARD)-spl.bin" file. +*/ + +int main(int argc, char **argv) +{ + int i, len; + unsigned char buffer[BUFSIZE] = {0}; + int ifd, ofd; + unsigned int checksum = 0, count; + + if (argc != 3) { + printf(" %d Wrong number of arguments\n", argc); + exit(EXIT_FAILURE); + } + + ifd = open(argv[1], O_RDONLY); + if (ifd < 0) { + fprintf(stderr, "%s: Can't open %s: %s\n", + argv[0], argv[1], strerror(errno)); + exit(EXIT_FAILURE); + } + + ofd = open(argv[2], O_WRONLY | O_CREAT | O_TRUNC, FILE_PERM); + if (ifd < 0) { + fprintf(stderr, "%s: Can't open %s: %s\n", + argv[0], argv[2], strerror(errno)); + if (ifd) + close(ifd); + exit(EXIT_FAILURE); + } + + len = lseek(ifd, 0, SEEK_END); + lseek(ifd, 0, SEEK_SET); + + memcpy(&buffer[0], SPL_HEADER, SPL_HEADER_SIZE); + + count = (len < (IMG_SIZE - SPL_HEADER_SIZE)) + ? len : (IMG_SIZE - SPL_HEADER_SIZE); + + if (read(ifd, buffer + SPL_HEADER_SIZE, count) != count) { + fprintf(stderr, "%s: Can't read %s: %s\n", + argv[0], argv[1], strerror(errno)); + + if (ifd) + close(ifd); + if (ofd) + close(ofd); + + exit(EXIT_FAILURE); + } + + for (i = 0; i < IMG_SIZE - SPL_HEADER_SIZE; i++) + checksum += buffer[i+16]; + + *(ulong *)buffer ^= 0x1f; + *(ulong *)(buffer+4) ^= checksum; + + for (i = 1; i < SPL_HEADER_SIZE; i++) + buffer[i] ^= buffer[i-1]; + + if (write(ofd, buffer, BUFSIZE) != BUFSIZE) { + fprintf(stderr, "%s: Can't write %s: %s\n", + argv[0], argv[2], strerror(errno)); + + if (ifd) + close(ifd); + if (ofd) + close(ofd); + + exit(EXIT_FAILURE); + } + + if (ifd) + close(ifd); + if (ofd) + close(ofd); + + return EXIT_SUCCESS; +} diff --git a/board/samsung/smdk2400/Makefile b/board/samsung/smdk2400/Makefile deleted file mode 100644 index 0c45d02a65..0000000000 --- a/board/samsung/smdk2400/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := smdk2400.o flash.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/samsung/smdk2400/config.mk b/board/samsung/smdk2400/config.mk deleted file mode 100644 index 4c27dc3044..0000000000 --- a/board/samsung/smdk2400/config.mk +++ /dev/null @@ -1,25 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> -# -# SAMSUNG board with S3C2400X (ARM920T) CPU -# -# see http://www.samsung.com/ for more information on SAMSUNG -# - -# -# SAMSUNG has 1 bank of 32 MB DRAM -# -# 0C00'0000 to 0E00'0000 -# -# Linux-Kernel is expected to be at 0cf0'0000, entry 0cf0'0000 -# optionally with a ramdisk at 0c80'0000 -# -# we load ourself to 0CF80000 (must be high enough not to be -# overwritten by the uncompessing Linux kernel) -# -# download area is 0C80'0000 -# - - -CONFIG_SYS_TEXT_BASE = 0x0CF80000 diff --git a/board/samsung/smdk2400/flash.c b/board/samsung/smdk2400/flash.c deleted file mode 100644 index 47382fe8f2..0000000000 --- a/board/samsung/smdk2400/flash.c +++ /dev/null @@ -1,492 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* #define DEBUG */ - -#include <common.h> -#include <environment.h> - -#define FLASH_BANK_SIZE 0x1000000 /* 2 x 8 MB */ -#define MAIN_SECT_SIZE 0x40000 /* 2 x 128 kB */ - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - - -#define CMD_READ_ARRAY 0x00FF00FF -#define CMD_IDENTIFY 0x00900090 -#define CMD_ERASE_SETUP 0x00200020 -#define CMD_ERASE_CONFIRM 0x00D000D0 -#define CMD_PROGRAM 0x00400040 -#define CMD_RESUME 0x00D000D0 -#define CMD_SUSPEND 0x00B000B0 -#define CMD_STATUS_READ 0x00700070 -#define CMD_STATUS_RESET 0x00500050 - -#define BIT_BUSY 0x00800080 -#define BIT_ERASE_SUSPEND 0x00400040 -#define BIT_ERASE_ERROR 0x00200020 -#define BIT_PROGRAM_ERROR 0x00100010 -#define BIT_VPP_RANGE_ERROR 0x00080008 -#define BIT_PROGRAM_SUSPEND 0x00040004 -#define BIT_PROTECT_ERROR 0x00020002 -#define BIT_UNDEFINED 0x00010001 - -#define BIT_SEQUENCE_ERROR 0x00300030 -#define BIT_TIMEOUT 0x80000000 - -/*----------------------------------------------------------------------- - */ - -ulong flash_init (void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - - flash_info[i].flash_id = - (INTEL_MANUFACT & FLASH_VENDMASK) | - (INTEL_ID_28F640J3A & FLASH_TYPEMASK); - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); - if (i == 0) - flashbase = CONFIG_SYS_FLASH_BASE; - else - panic ("configured too many flash banks!\n"); - for (j = 0; j < flash_info[i].sector_count; j++) { - flash_info[i].start[j] = flashbase; - - /* uniform sector size */ - flashbase += MAIN_SECT_SIZE; - } - size += flash_info[i].size; - } - - /* - * Protect monitor and environment sectors - */ - flash_protect ( FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect ( FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, &flash_info[0]); - -#ifdef CONFIG_ENV_ADDR_REDUND - flash_protect ( FLAG_PROTECT_SET, - CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case (INTEL_MANUFACT & FLASH_VENDMASK): - printf ("Intel: "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (INTEL_ID_28F640J3A & FLASH_TYPEMASK): - printf ("2x 28F640J3A (64Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - goto Done; - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - -Done: ; -} - -/*----------------------------------------------------------------------- - */ - -int flash_error (ulong code) -{ - /* Check bit patterns */ - /* SR.7=0 is busy, SR.7=1 is ready */ - /* all other flags indicate error on 1 */ - /* SR.0 is undefined */ - /* Timeout is our faked flag */ - - /* sequence is described in Intel 290644-005 document */ - - /* check Timeout */ - if (code & BIT_TIMEOUT) { - puts ("Timeout\n"); - return ERR_TIMOUT; - } - - /* check Busy, SR.7 */ - if (~code & BIT_BUSY) { - puts ("Busy\n"); - return ERR_PROG_ERROR; - } - - /* check Vpp low, SR.3 */ - if (code & BIT_VPP_RANGE_ERROR) { - puts ("Vpp range error\n"); - return ERR_PROG_ERROR; - } - - /* check Device Protect Error, SR.1 */ - if (code & BIT_PROTECT_ERROR) { - puts ("Device protect error\n"); - return ERR_PROG_ERROR; - } - - /* check Command Seq Error, SR.4 & SR.5 */ - if (code & BIT_SEQUENCE_ERROR) { - puts ("Command seqence error\n"); - return ERR_PROG_ERROR; - } - - /* check Block Erase Error, SR.5 */ - if (code & BIT_ERASE_ERROR) { - puts ("Block erase error\n"); - return ERR_PROG_ERROR; - } - - /* check Program Error, SR.4 */ - if (code & BIT_PROGRAM_ERROR) { - puts ("Program error\n"); - return ERR_PROG_ERROR; - } - - /* check Block Erase Suspended, SR.6 */ - if (code & BIT_ERASE_SUSPEND) { - puts ("Block erase suspended\n"); - return ERR_PROG_ERROR; - } - - /* check Program Suspended, SR.2 */ - if (code & BIT_PROGRAM_SUSPEND) { - puts ("Program suspended\n"); - return ERR_PROG_ERROR; - } - - /* OK, no error */ - return ERR_OK; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - ulong result, result1; - int iflag, prot, sect; - int rc = ERR_OK; - ulong start; - -#ifdef USE_920T_MMU - int cflag; -#endif - - debug ("flash_erase: s_first %d s_last %d\n", s_first, s_last); - - /* first look for protection bits */ - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (INTEL_MANUFACT & FLASH_VENDMASK)) { - return ERR_UNKNOWN_FLASH_VENDOR; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ -#ifdef USE_920T_MMU - cflag = dcache_status (); - dcache_disable (); -#endif - iflag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { - - debug ("Erasing sector %2d @ %08lX... ", - sect, info->start[sect]); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - if (info->protect[sect] == 0) { /* not protected */ - vu_long *addr = (vu_long *) (info->start[sect]); - ulong bsR7, bsR7_2, bsR5, bsR5_2; - - /* *addr = CMD_STATUS_RESET; */ - *addr = CMD_ERASE_SETUP; - *addr = CMD_ERASE_CONFIRM; - - /* wait until flash is ready */ - do { - /* check timeout */ - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { - *addr = CMD_STATUS_RESET; - result = BIT_TIMEOUT; - break; - } - - *addr = CMD_STATUS_READ; - result = *addr; - bsR7 = result & (1 << 7); - bsR7_2 = result & (1 << 23); - } while (!bsR7 | !bsR7_2); - - *addr = CMD_STATUS_READ; - result1 = *addr; - bsR5 = result1 & (1 << 5); - bsR5_2 = result1 & (1 << 21); -#ifdef SAMSUNG_FLASH_DEBUG - printf ("bsR5 %lx bsR5_2 %lx\n", bsR5, bsR5_2); - if (bsR5 != 0 && bsR5_2 != 0) - printf ("bsR5 %lx bsR5_2 %lx\n", bsR5, bsR5_2); -#endif - - *addr = CMD_READ_ARRAY; - *addr = CMD_RESUME; - - if ((rc = flash_error (result)) != ERR_OK) - goto outahere; -#if 0 - printf ("ok.\n"); - } else { /* it was protected */ - - printf ("protected!\n"); -#endif - } - } - -outahere: - /* allow flash to settle - wait 10 ms */ - udelay_masked (10000); - - if (iflag) - enable_interrupts (); - -#ifdef USE_920T_MMU - if (cflag) - dcache_enable (); -#endif - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash - */ - -static int write_word (flash_info_t * info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *) dest; - ulong result; - int rc = ERR_OK; - int iflag; - ulong start; - -#ifdef USE_920T_MMU - int cflag; -#endif - - /* - * Check if Flash is (sufficiently) erased - */ - result = *addr; - if ((result & data) != data) - return ERR_NOT_ERASED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ -#ifdef USE_920T_MMU - cflag = dcache_status (); - dcache_disable (); -#endif - iflag = disable_interrupts (); - - /* *addr = CMD_STATUS_RESET; */ - *addr = CMD_PROGRAM; - *addr = data; - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait until flash is ready */ - do { - /* check timeout */ - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { - *addr = CMD_SUSPEND; - result = BIT_TIMEOUT; - break; - } - - *addr = CMD_STATUS_READ; - result = *addr; - } while (~result & BIT_BUSY); - - /* *addr = CMD_READ_ARRAY; */ - *addr = CMD_STATUS_READ; - result = *addr; - - rc = flash_error (result); - - if (iflag) - enable_interrupts (); - -#ifdef USE_920T_MMU - if (cflag) - dcache_enable (); -#endif - *addr = CMD_READ_ARRAY; - *addr = CMD_RESUME; - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash. - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int l; - int i, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 24); - } - for (; i < 4 && cnt > 0; ++i) { - data = (data >> 8) | (*src++ << 24); - --cnt; - ++cp; - } - for (; cnt == 0 && i < 4; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 24); - } - - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = *((vu_long *) src); - if ((rc = write_word (info, wp, data)) != 0) { - return (rc); - } - src += 4; - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return ERR_OK; - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 24); - --cnt; - } - for (; i < 4; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 24); - } - - return write_word (info, wp, data); -} diff --git a/board/samsung/smdk2400/lowlevel_init.S b/board/samsung/smdk2400/lowlevel_init.S deleted file mode 100644 index c275c07e7c..0000000000 --- a/board/samsung/smdk2400/lowlevel_init.S +++ /dev/null @@ -1,163 +0,0 @@ -/* - * Memory Setup stuff - taken from blob memsetup.S - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and - * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) - * - * Modified for the Samsung development board by - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include <config.h> -#include <version.h> - - -/* some parameters for the board */ - -/* - * - * Taken from linux/arch/arm/boot/compressed/head-s3c2400.S - * - * Copyright (C) 2001 Samsung Electronics by chc, 010406 - * - * S3C2400 specific tweaks. - * - */ - -/* memory controller */ -#define BWSCON 0x14000000 -#define BANKCON3 0x14000010 /* for cs8900, ethernet */ - -/* Bank0 */ -#define B0_Tacs 0x0 /* 0 clk */ -#define B0_Tcos 0x0 /* 0 clk */ -#define B0_Tacc 0x7 /* 14 clk */ -#define B0_Tcoh 0x0 /* 0 clk */ -#define B0_Tah 0x0 /* 0 clk */ -#define B0_Tacp 0x0 -#define B0_PMC 0x0 /* normal */ - -/* Bank1 */ -#define B1_Tacs 0x0 /* 0 clk */ -#define B1_Tcos 0x0 /* 0 clk */ -#define B1_Tacc 0x7 /* 14 clk */ -#define B1_Tcoh 0x0 /* 0 clk */ -#define B1_Tah 0x0 /* 0 clk */ -#define B1_Tacp 0x0 -#define B1_PMC 0x0 /* normal */ - -/* Bank2 */ -#define B2_Tacs 0x0 /* 0 clk */ -#define B2_Tcos 0x0 /* 0 clk */ -#define B2_Tacc 0x7 /* 14 clk */ -#define B2_Tcoh 0x0 /* 0 clk */ -#define B2_Tah 0x0 /* 0 clk */ -#define B2_Tacp 0x0 -#define B2_PMC 0x0 /* normal */ - -/* Bank3 - setup for the cs8900 */ -#define B3_Tacs 0x0 /* 0 clk */ -#define B3_Tcos 0x3 /* 4 clk */ -#define B3_Tacc 0x7 /* 14 clk */ -#define B3_Tcoh 0x1 /* 1 clk */ -#define B3_Tah 0x0 /* 0 clk */ -#define B3_Tacp 0x3 /* 6 clk */ -#define B3_PMC 0x0 /* normal */ - -/* Bank4 */ -#define B4_Tacs 0x0 /* 0 clk */ -#define B4_Tcos 0x0 /* 0 clk */ -#define B4_Tacc 0x7 /* 14 clk */ -#define B4_Tcoh 0x0 /* 0 clk */ -#define B4_Tah 0x0 /* 0 clk */ -#define B4_Tacp 0x0 -#define B4_PMC 0x0 /* normal */ - -/* Bank5 */ -#define B5_Tacs 0x0 /* 0 clk */ -#define B5_Tcos 0x0 /* 0 clk */ -#define B5_Tacc 0x7 /* 14 clk */ -#define B5_Tcoh 0x0 /* 0 clk */ -#define B5_Tah 0x0 /* 0 clk */ -#define B5_Tacp 0x0 -#define B5_PMC 0x0 /* normal */ - -/* Bank6 */ -#define B6_MT 0x3 /* SDRAM */ -#define B6_Trcd 0x1 /* 3clk */ -#define B6_SCAN 0x1 /* 9 bit */ - -/* Bank7 */ -#define B7_MT 0x3 /* SDRAM */ -#define B7_Trcd 0x1 /* 3clk */ -#define B7_SCAN 0x1 /* 9 bit */ - -/* refresh parameter */ -#define REFEN 0x1 /* enable refresh */ -#define TREFMD 0x0 /* CBR(CAS before RAS)/auto refresh */ -#define Trp 0x0 /* 2 clk */ -#define Trc 0x3 /* 7 clk */ -#define Tchr 0x2 /* 3 clk */ - -#define REFCNT 1113 /* period=15.6 us, HCLK=60Mhz, (2048+1-15.6*66) */ - - -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE - -.globl lowlevel_init -lowlevel_init: - /* memory control configuration */ - /* make r0 relative the current location so that it */ - /* reads SMRDATA out of FLASH rather than memory ! */ - ldr r0, =SMRDATA - ldr r1, _TEXT_BASE - sub r0, r0, r1 - ldr r1, =BWSCON /* Bus Width Status Controller */ - add r2, r0, #52 -0: - ldr r3, [r0], #4 - str r3, [r1], #4 - cmp r2, r0 - bne 0b - - /* everything is fine now */ - mov pc, lr - - .ltorg -/* the literal pools origin */ - -SMRDATA: - .word 0x2211d114 /* d->Ethernet, BUSWIDTH=32 */ - .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) /* GCS0 */ - .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) /* GCS1 */ - .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) /* GCS2 */ - .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) /* GCS3 */ - .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) /* GCS4 */ - .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) /* GCS5 */ - .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) /* GCS6 */ - .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) /* GCS7 */ - .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) - .word 0x10 /* BUSWIDTH=32, SCLK power saving mode, BANKSIZE 32M/32M */ - .word 0x30 /* MRSR6, CL=3clk */ - .word 0x30 /* MRSR7 */ diff --git a/board/samsung/smdk2400/smdk2400.c b/board/samsung/smdk2400/smdk2400.c deleted file mode 100644 index 895bd7789a..0000000000 --- a/board/samsung/smdk2400/smdk2400.c +++ /dev/null @@ -1,125 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <netdev.h> -#include <asm/arch/s3c24x0_cpu.h> - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_MODEM_SUPPORT -static int key_pressed(void); -int mdm_init (bd_t *); -extern void disable_putc(void); -extern void enable_putc(void); -extern int hwflow_onoff(int); -extern int do_mdm_init; /* defined in common/main.c */ -#endif /* CONFIG_MODEM_SUPPORT */ - -/* - * Miscellaneous platform dependent initialisations - */ - -int board_init (void) -{ - struct s3c24x0_clock_power * const clk_power = - s3c24x0_get_base_clock_power(); - struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - - /* memory and cpu-speed are setup before relocation */ - /* change the clock to be 50 MHz 1:1:1 */ - clk_power->mpllcon = 0x5c042; - clk_power->clkdivn = 0; - /* set up the I/O ports */ - gpio->pacon = 0x3ffff; - gpio->pbcon = 0xaaaaaaaa; - gpio->pbup = 0xffff; - gpio->pecon = 0x0; - gpio->peup = 0x0; -#ifdef CONFIG_HWFLOW - /*CTS[0] RTS[0] INPUT INPUT TXD[0] INPUT RXD[0] */ - /* 10, 10, 00, 00, 10, 00, 10 */ - gpio->pfcon = 0xa22; - /* Disable pull-up on Rx, Tx, CTS and RTS pins */ - gpio->pfup = 0x35; -#else - /*INPUT INPUT INPUT INPUT TXD[0] INPUT RXD[0] */ - /* 00, 00, 00, 00, 10, 00, 10 */ - gpio->pfcon = 0x22; - /* Disable pull-up on Rx and Tx pins */ - gpio->pfup = 0x5; -#endif /* CONFIG_HWFLOW */ - gpio->pgcon = 0x0; - gpio->pgup = 0x0; - gpio->opencr = 0x0; - - /* arch number of SAMSUNG-Board to MACH_TYPE_SMDK2400 */ - gd->bd->bi_arch_number = MACH_TYPE_SMDK2400; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x0C000100; - -#ifdef CONFIG_MODEM_SUPPORT - if (key_pressed()) { - disable_putc(); /* modem doesn't understand banner etc */ - do_mdm_init = 1; - } -#endif /* CONFIG_MODEM_SUPPORT */ - - return 0; -} - -int dram_init (void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return 0; -} - -#ifdef CONFIG_MODEM_SUPPORT -static int key_pressed(void) -{ - int rc; - if (1) { /* check for button push here, now just return 1 */ - rc = 1; - } - - return rc; -} -#endif /* CONFIG_MODEM_SUPPORT */ - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_CS8900 - rc = cs8900_initialize(0, CONFIG_CS8900_BASE); -#endif - return rc; -} -#endif diff --git a/board/samsung/smdk6400/smdk6400.c b/board/samsung/smdk6400/smdk6400.c index 13c7ed5189..c40d1f9b49 100644 --- a/board/samsung/smdk6400/smdk6400.c +++ b/board/samsung/smdk6400/smdk6400.c @@ -72,7 +72,6 @@ int board_init(void) /* Enable WAIT */ SROM_BW_REG |= 4 | 8 | 1; - gd->bd->bi_arch_number = MACH_TYPE; gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; return 0; diff --git a/board/samsung/smdkc100/smdkc100.c b/board/samsung/smdkc100/smdkc100.c index 1ad68b9c07..c41e610a43 100644 --- a/board/samsung/smdkc100/smdkc100.c +++ b/board/samsung/smdkc100/smdkc100.c @@ -41,7 +41,7 @@ static void smc9115_pre_init(void) (struct s5pc100_gpio *)samsung_get_base_gpio(); /* gpio configuration GPK0CON */ - gpio_cfg_pin(&gpio->k0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2)); + s5p_gpio_cfg_pin(&gpio->k0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2)); /* Ethernet needs bus width of 16 bits */ smc_bw_conf = SMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK); diff --git a/board/samsung/smdkv310/smdkv310.c b/board/samsung/smdkv310/smdkv310.c index acf9ee7b87..e0b89dd55b 100644 --- a/board/samsung/smdkv310/smdkv310.c +++ b/board/samsung/smdkv310/smdkv310.c @@ -37,7 +37,7 @@ static void smc9115_pre_init(void) u32 smc_bw_conf, smc_bc_conf; /* gpio configuration GPK0CON */ - gpio_cfg_pin(&gpio2->y0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2)); + s5p_gpio_cfg_pin(&gpio2->y0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2)); /* Ethernet needs bus width of 16 bits */ smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK); @@ -116,19 +116,19 @@ int board_mmc_init(bd_t *bis) */ for (i = 0; i < 7; i++) { /* GPK2[0:6] special function 2 */ - gpio_cfg_pin(&gpio2->k2, i, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(&gpio2->k2, i, GPIO_FUNC(0x2)); /* GPK2[0:6] drv 4x */ - gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X); + s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X); /* GPK2[0:1] pull disable */ if (i == 0 || i == 1) { - gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE); + s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE); continue; } /* GPK2[2:6] pull up */ - gpio_set_pull(&gpio2->k2, i, GPIO_PULL_UP); + s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_UP); } err = s5p_mmc_init(2, 4); return err; diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index b65bc6ecb7..1b27e8b428 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -160,7 +160,7 @@ int board_mmc_init(bd_t *bis) * you should set it HIGH since it removes the inverter */ /* MASSMEMORY_EN: XMDMDATA_6: GPE3[6] */ - gpio_direction_output(&gpio1->e3, 6, 0); + s5p_gpio_direction_output(&gpio1->e3, 6, 0); break; default: /* @@ -168,7 +168,7 @@ int board_mmc_init(bd_t *bis) * But set it as HIGH to ensure */ /* MASSMEMORY_EN: XMDMADDR_3: GPE1[3] */ - gpio_direction_output(&gpio1->e1, 3, 1); + s5p_gpio_direction_output(&gpio1->e1, 3, 1); break; } @@ -192,25 +192,25 @@ int board_mmc_init(bd_t *bis) if (i == 2) continue; /* GPK0[0:6] special function 2 */ - gpio_cfg_pin(&gpio2->k0, i, 0x2); + s5p_gpio_cfg_pin(&gpio2->k0, i, 0x2); /* GPK0[0:6] pull disable */ - gpio_set_pull(&gpio2->k0, i, GPIO_PULL_NONE); + s5p_gpio_set_pull(&gpio2->k0, i, GPIO_PULL_NONE); /* GPK0[0:6] drv 4x */ - gpio_set_drv(&gpio2->k0, i, GPIO_DRV_4X); + s5p_gpio_set_drv(&gpio2->k0, i, GPIO_DRV_4X); } for (i = 3; i < 7; i++) { /* GPK1[3:6] special function 3 */ - gpio_cfg_pin(&gpio2->k1, i, 0x3); + s5p_gpio_cfg_pin(&gpio2->k1, i, 0x3); /* GPK1[3:6] pull disable */ - gpio_set_pull(&gpio2->k1, i, GPIO_PULL_NONE); + s5p_gpio_set_pull(&gpio2->k1, i, GPIO_PULL_NONE); /* GPK1[3:6] drv 4x */ - gpio_set_drv(&gpio2->k1, i, GPIO_DRV_4X); + s5p_gpio_set_drv(&gpio2->k1, i, GPIO_DRV_4X); } /* T-flash detect */ - gpio_cfg_pin(&gpio2->x3, 4, 0xf); - gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP); + s5p_gpio_cfg_pin(&gpio2->x3, 4, 0xf); + s5p_gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP); /* * MMC device init @@ -223,7 +223,7 @@ int board_mmc_init(bd_t *bis) * Check the T-flash detect pin * GPX3[4] T-flash detect pin */ - if (!gpio_get_value(&gpio2->x3, 4)) { + if (!s5p_gpio_get_value(&gpio2->x3, 4)) { /* * SD card GPIO: * GPK2[0] SD_2_CLK(2) @@ -235,11 +235,11 @@ int board_mmc_init(bd_t *bis) if (i == 2) continue; /* GPK2[0:6] special function 2 */ - gpio_cfg_pin(&gpio2->k2, i, 0x2); + s5p_gpio_cfg_pin(&gpio2->k2, i, 0x2); /* GPK2[0:6] pull disable */ - gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE); + s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE); /* GPK2[0:6] drv 4x */ - gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X); + s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X); } err = s5p_mmc_init(2, 4); } diff --git a/board/sbc2410x/Makefile b/board/sbc2410x/Makefile deleted file mode 100644 index 2b3b781eea..0000000000 --- a/board/sbc2410x/Makefile +++ /dev/null @@ -1,51 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := sbc2410x.o flash.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/sbc2410x/config.mk b/board/sbc2410x/config.mk deleted file mode 100644 index bc01a2d9f2..0000000000 --- a/board/sbc2410x/config.mk +++ /dev/null @@ -1,23 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> -# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> -# -# SAMSUNG SMDK2410 board with S3C2410X (ARM920T) cpu -# -# see http://www.samsung.com/ for more information on SAMSUNG -# - -# -# SMDK2410 has 1 bank of 64 MB DRAM -# -# 3000'0000 to 3400'0000 -# -# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000 -# optionally with a ramdisk at 3080'0000 -# -# we load ourself to 33F8'0000 -# -# download area is 3300'0000 - -CONFIG_SYS_TEXT_BASE = 0x33F80000 diff --git a/board/sbc2410x/flash.c b/board/sbc2410x/flash.c deleted file mode 100644 index d209a6f9ac..0000000000 --- a/board/sbc2410x/flash.c +++ /dev/null @@ -1,433 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke <azu@sysgo.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -ulong myflush (void); - -#define FLASH_BANK_SIZE PHYS_FLASH_SIZE -#define MAIN_SECT_SIZE 0x10000 /* 64 KB */ - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -#define CMD_READ_ARRAY 0x000000F0 -#define CMD_UNLOCK1 0x000000AA -#define CMD_UNLOCK2 0x00000055 -#define CMD_ERASE_SETUP 0x00000080 -#define CMD_ERASE_CONFIRM 0x00000030 -#define CMD_PROGRAM 0x000000A0 -#define CMD_UNLOCK_BYPASS 0x00000020 - -#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555 << 1))) -#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA << 1))) - -#define BIT_ERASE_DONE 0x00000080 -#define BIT_RDY_MASK 0x00000080 -#define BIT_PROGRAM_ERROR 0x00000020 -#define BIT_TIMEOUT 0x80000000 /* our flag */ - -#define READY 1 -#define ERR 2 -#define TMO 4 - -/*----------------------------------------------------------------------- - */ - -ulong flash_init (void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - - flash_info[i].flash_id = -#if defined(CONFIG_AMD_LV400) - (AMD_MANUFACT & FLASH_VENDMASK) | - (AMD_ID_LV400B & FLASH_TYPEMASK); -#elif defined(CONFIG_AMD_LV800) - (AMD_MANUFACT & FLASH_VENDMASK) | - (AMD_ID_LV800B & FLASH_TYPEMASK); -#else -#error "Unknown flash configured" -#endif - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); - if (i == 0) - flashbase = PHYS_FLASH_1; - else - panic ("configured too many flash banks!\n"); - for (j = 0; j < flash_info[i].sector_count; j++) { - if (j <= 3) { - /* 1st one is 16 KB */ - if (j == 0) { - flash_info[i].start[j] = - flashbase + 0; - } - - /* 2nd and 3rd are both 8 KB */ - if ((j == 1) || (j == 2)) { - flash_info[i].start[j] = - flashbase + 0x4000 + (j - - 1) * - 0x2000; - } - - /* 4th 32 KB */ - if (j == 3) { - flash_info[i].start[j] = - flashbase + 0x8000; - } - } else { - flash_info[i].start[j] = - flashbase + (j - 3) * MAIN_SECT_SIZE; - } - } - size += flash_info[i].size; - } - - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case (AMD_MANUFACT & FLASH_VENDMASK): - printf ("AMD: "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (AMD_ID_LV400B & FLASH_TYPEMASK): - printf ("1x Amd29LV400BB (4Mbit)\n"); - break; - case (AMD_ID_LV800B & FLASH_TYPEMASK): - printf ("1x Amd29LV800BB (8Mbit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - goto Done; - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - printf ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - - Done:; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - ushort result; - int iflag, cflag, prot, sect; - int rc = ERR_OK; - int chip; - ulong start; - - /* first look for protection bits */ - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (AMD_MANUFACT & FLASH_VENDMASK)) { - return ERR_UNKNOWN_FLASH_VENDOR; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) - return ERR_PROTECTED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - cflag = icache_status (); - icache_disable (); - iflag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - if (info->protect[sect] == 0) { /* not protected */ - vu_short *addr = (vu_short *) (info->start[sect]); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - *addr = CMD_ERASE_CONFIRM; - - /* wait until flash is ready */ - chip = 0; - - do { - result = *addr; - - /* check timeout */ - if (get_timer(start) > - CONFIG_SYS_FLASH_ERASE_TOUT) { - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - chip = TMO; - break; - } - - if (!chip - && (result & 0xFFFF) & BIT_ERASE_DONE) - chip = READY; - - if (!chip - && (result & 0xFFFF) & BIT_PROGRAM_ERROR) - chip = ERR; - - } while (!chip); - - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - - if (chip == ERR) { - rc = ERR_PROG_ERROR; - goto outahere; - } - if (chip == TMO) { - rc = ERR_TIMOUT; - goto outahere; - } - - printf ("ok.\n"); - } else { /* it was protected */ - - printf ("protected!\n"); - } - } - - if (ctrlc ()) - printf ("User Interrupt!\n"); - - outahere: - /* allow flash to settle - wait 10 ms */ - udelay_masked (10000); - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash - */ - -static int write_hword (flash_info_t * info, ulong dest, ushort data) -{ - vu_short *addr = (vu_short *) dest; - ushort result; - int rc = ERR_OK; - int cflag, iflag; - int chip; - ulong start; - - /* - * Check if Flash is (sufficiently) erased - */ - result = *addr; - if ((result & data) != data) - return ERR_NOT_ERASED; - - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - cflag = icache_status (); - icache_disable (); - iflag = disable_interrupts (); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS; - *addr = CMD_PROGRAM; - *addr = data; - - /* arm simple, non interrupt dependent timer */ - get_timer(start); - - /* wait until flash is ready */ - chip = 0; - do { - result = *addr; - - /* check timeout */ - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { - chip = ERR | TMO; - break; - } - if (!chip && ((result & 0x80) == (data & 0x80))) - chip = READY; - - if (!chip && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) { - result = *addr; - - if ((result & 0x80) == (data & 0x80)) - chip = READY; - else - chip = ERR; - } - - } while (!chip); - - *addr = CMD_READ_ARRAY; - - if (chip == ERR || *addr != data) - rc = ERR_PROG_ERROR; - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash. - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - int l; - int i, rc; - ushort data; - - wp = (addr & ~1); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - for (; i < 2 && cnt > 0; ++i) { - data = (data >> 8) | (*src++ << 8); - --cnt; - ++cp; - } - for (; cnt == 0 && i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - - if ((rc = write_hword (info, wp, data)) != 0) { - return (rc); - } - wp += 2; - } - - /* - * handle word aligned part - */ - while (cnt >= 2) { - data = *((vu_short *) src); - if ((rc = write_hword (info, wp, data)) != 0) { - return (rc); - } - src += 2; - wp += 2; - cnt -= 2; - } - - if (cnt == 0) { - return ERR_OK; - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 8); - --cnt; - } - for (; i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - - return write_hword (info, wp, data); -} diff --git a/board/sbc2410x/lowlevel_init.S b/board/sbc2410x/lowlevel_init.S deleted file mode 100644 index 3de91661d4..0000000000 --- a/board/sbc2410x/lowlevel_init.S +++ /dev/null @@ -1,163 +0,0 @@ -/* - * Memory Setup stuff - taken from blob memsetup.S - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and - * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) - * - * Modified for the Samsung SMDK2410 by - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> - * - * Modified for the friendly-arm SBC-2410X by - * (C) Copyright 2005 - * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <version.h> - -/* - * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S - * - * Copyright (C) 2002 Samsung Electronics SW.LEE <hitchcar@sec.samsung.com> - */ - -#define BWSCON 0x48000000 - -/* BWSCON */ -#define DW8 (0x0) -#define DW16 (0x1) -#define DW32 (0x2) -#define WAIT (0x1<<2) -#define UBLB (0x1<<3) - -#define B1_BWSCON (DW16) -#define B2_BWSCON (DW16) -#define B3_BWSCON (DW16 + WAIT + UBLB) -#define B4_BWSCON (DW16) -#define B5_BWSCON (DW16) -#define B6_BWSCON (DW32) -#define B7_BWSCON (DW32) - -#define B0_Tacs 0x0 -#define B0_Tcos 0x0 -#define B0_Tacc 0x7 -#define B0_Tcoh 0x0 -#define B0_Tah 0x0 -#define B0_Tacp 0x0 -#define B0_PMC 0x0 - -#define B1_Tacs 0x0 -#define B1_Tcos 0x0 -#define B1_Tacc 0x7 -#define B1_Tcoh 0x0 -#define B1_Tah 0x0 -#define B1_Tacp 0x0 -#define B1_PMC 0x0 - -#define B2_Tacs 0x0 -#define B2_Tcos 0x0 -#define B2_Tacc 0x7 -#define B2_Tcoh 0x0 -#define B2_Tah 0x0 -#define B2_Tacp 0x0 -#define B2_PMC 0x0 - -#define B3_Tacs 0xc -#define B3_Tcos 0x7 -#define B3_Tacc 0xf -#define B3_Tcoh 0x1 -#define B3_Tah 0x0 -#define B3_Tacp 0x0 -#define B3_PMC 0x0 - -#define B4_Tacs 0x0 -#define B4_Tcos 0x0 -#define B4_Tacc 0x7 -#define B4_Tcoh 0x0 -#define B4_Tah 0x0 -#define B4_Tacp 0x0 -#define B4_PMC 0x0 - -#define B5_Tacs 0xc -#define B5_Tcos 0x7 -#define B5_Tacc 0xf -#define B5_Tcoh 0x1 -#define B5_Tah 0x0 -#define B5_Tacp 0x0 -#define B5_PMC 0x0 - -#define B6_MT 0x3 /* SDRAM */ -#define B6_Trcd 0x1 -#define B6_SCAN 0x1 /* 9bit */ - -#define B7_MT 0x3 /* SDRAM */ -#define B7_Trcd 0x1 /* 3clk */ -#define B7_SCAN 0x1 /* 9bit */ - -/* REFRESH parameter */ -#define REFEN 0x1 /* Refresh enable */ -#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ -#define Trp 0x0 /* 2clk */ -#define Trc 0x3 /* 7clk */ -#define Tchr 0x2 /* 3clk */ -#define REFCNT 0x0459 -/**************************************/ - -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE - -.globl lowlevel_init -lowlevel_init: - /* memory control configuration */ - /* make r0 relative the current location so that it */ - /* reads SMRDATA out of FLASH rather than memory ! */ - ldr r0, =SMRDATA - ldr r1, _TEXT_BASE - sub r0, r0, r1 - ldr r1, =BWSCON /* Bus Width Status Controller */ - add r2, r0, #13*4 -0: - ldr r3, [r0], #4 - str r3, [r1], #4 - cmp r2, r0 - bne 0b - - /* everything is fine now */ - mov pc, lr - - .ltorg -/* the literal pools origin */ - -SMRDATA: - .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28)) - .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) - .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) - .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) - .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) - .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) - .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) - .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) - .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) - .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) - .word 0xb2 - .word 0x30 - .word 0x30 diff --git a/board/sbc2410x/sbc2410x.c b/board/sbc2410x/sbc2410x.c deleted file mode 100644 index c82382dc82..0000000000 --- a/board/sbc2410x/sbc2410x.c +++ /dev/null @@ -1,193 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Marius Groeger <mgroeger@sysgo.de> - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> - * - * (C) Copyright 2005 - * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <netdev.h> -#include <asm/arch/s3c24x0_cpu.h> - -#if defined(CONFIG_CMD_NAND) -#include <linux/mtd/nand.h> -#endif - -DECLARE_GLOBAL_DATA_PTR; - -#define FCLK_SPEED 1 - -#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */ -#define M_MDIV 0xC3 -#define M_PDIV 0x4 -#define M_SDIV 0x1 -#elif FCLK_SPEED==1 /* Fout = 202.8MHz */ -#define M_MDIV 0x5c -#define M_PDIV 0x4 -#define M_SDIV 0x0 -#endif - -#define USB_CLOCK 1 - -#if USB_CLOCK==0 -#define U_M_MDIV 0xA1 -#define U_M_PDIV 0x3 -#define U_M_SDIV 0x1 -#elif USB_CLOCK==1 -#define U_M_MDIV 0x48 -#define U_M_PDIV 0x3 -#define U_M_SDIV 0x2 -#endif - -static inline void delay (unsigned long loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - -/* - * Miscellaneous platform dependent initialisations - */ - -int board_init (void) -{ - struct s3c24x0_clock_power * const clk_power = - s3c24x0_get_base_clock_power(); - struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); - - /* to reduce PLL lock time, adjust the LOCKTIME register */ - clk_power->locktime = 0xFFFFFF; - - /* configure MPLL */ - clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); - - /* some delay between MPLL and UPLL */ - delay (4000); - - /* configure UPLL */ - clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); - - /* some delay between MPLL and UPLL */ - delay (8000); - - /* set up the I/O ports */ - gpio->gpacon = 0x007FFFFF; - gpio->gpbcon = 0x00044556; - gpio->gpbup = 0x000007FF; - gpio->gpccon = 0xAAAAAAAA; - gpio->gpcup = 0x0000FFFF; - gpio->gpdcon = 0xAAAAAAAA; - gpio->gpdup = 0x0000FFFF; - gpio->gpecon = 0xAAAAAAAA; - gpio->gpeup = 0x0000FFFF; - gpio->gpfcon = 0x000055AA; - gpio->gpfup = 0x000000FF; - gpio->gpgcon = 0xFF95FF3A; - gpio->gpgup = 0x0000FFFF; - gpio->gphcon = 0x0016FAAA; - gpio->gphup = 0x000007FF; - - gpio->extint0 = 0x22222222; - gpio->extint1 = 0x22222222; - gpio->extint2 = 0x22222222; - - /* arch number of SMDK2410-Board */ - gd->bd->bi_arch_number = MACH_TYPE_SMDK2410; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x30000100; - - icache_enable(); - dcache_enable(); - - return 0; -} - -int dram_init (void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return 0; -} - -#if defined(CONFIG_CMD_NAND) -extern ulong nand_probe(ulong physadr); - -static inline void NF_Reset(void) -{ - int i; - - NF_SetCE(NFCE_LOW); - NF_Cmd(0xFF); /* reset command */ - for(i = 0; i < 10; i++); /* tWB = 100ns. */ - NF_WaitRB(); /* wait 200~500us; */ - NF_SetCE(NFCE_HIGH); -} - -static inline void NF_Init(void) -{ -#if 1 -#define TACLS 0 -#define TWRPH0 3 -#define TWRPH1 0 -#else -#define TACLS 0 -#define TWRPH0 4 -#define TWRPH1 2 -#endif - - NF_Conf((1<<15)|(0<<14)|(0<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0)); - /*nand->NFCONF = (1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0); */ - /* 1 1 1 1, 1 xxx, r xxx, r xxx */ - /* En 512B 4step ECCR nFCE=H tACLS tWRPH0 tWRPH1 */ - - NF_Reset(); -} - -void nand_init(void) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - NF_Init(); -#ifdef DEBUG - printf("NAND flash probing at 0x%.8lX\n", (ulong)nand); -#endif - printf ("%4lu MB\n", nand_probe((ulong)nand) >> 20); -} -#endif - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_CS8900 - rc = cs8900_initialize(0, CONFIG_CS8900_BASE); -#endif - return rc; -} -#endif diff --git a/board/scb9328/scb9328.c b/board/scb9328/scb9328.c index 2e31e8c7b3..076c046ced 100644 --- a/board/scb9328/scb9328.c +++ b/board/scb9328/scb9328.c @@ -40,7 +40,7 @@ int board_init (void) int dram_init (void) { /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((volatile void *)SCB9328_SDRAM_1, + gd->ram_size = get_ram_size((void *)SCB9328_SDRAM_1, SCB9328_SDRAM_1_SIZE); return 0; diff --git a/board/syteco/zmx25/zmx25.c b/board/syteco/zmx25/zmx25.c index f0550389eb..893adc6bd5 100644 --- a/board/syteco/zmx25/zmx25.c +++ b/board/syteco/zmx25/zmx25.c @@ -29,7 +29,7 @@ * */ #include <common.h> -#include <mxc_gpio.h> +#include <asm/gpio.h> #include <asm/io.h> #include <asm/arch/imx-regs.h> #include <asm/arch/imx25-pinmux.h> @@ -56,8 +56,7 @@ int board_init() /* Setup of core volatage selection pin to run at 1.4V */ writel(gpio_mux_mode5, &muxctl->pad_ext_armclk); /* VCORE GPIO3[15] */ - mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(3, 15), MXC_GPIO_DIRECTION_OUT); - mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(3, 15), 1); + gpio_direction_output(MXC_GPIO_PORT_TO_NUM(3, 15), 1); /* Setup of input daisy chains for SD card pins*/ writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_cmd); @@ -69,11 +68,10 @@ int board_init() /* Setup of digital output for USB power and OC */ writel(gpio_mux_mode5, &muxctl->pad_csi_d3); /* USB Power GPIO1[28] */ - mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 28), MXC_GPIO_DIRECTION_OUT); - mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 28), 1); + gpio_direction_output(MXC_GPIO_PORT_TO_NUM(1, 28), 1); writel(gpio_mux_mode5, &muxctl->pad_csi_d2); /* USB OC GPIO1[27] */ - mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 18), MXC_GPIO_DIRECTION_IN); + gpio_direction_input(MXC_GPIO_PORT_TO_NUM(1, 18)); /* Setup of digital output control pins */ writel(gpio_mux_mode5, &muxctl->pad_csi_d8); /* Ouput 1 Ctrl GPIO1[7] */ @@ -85,25 +83,21 @@ int board_init() writel(0, &padctl->pad_csi_d5); /* Ouput 2 Stat pull up off */ /* Switch both output drivers off */ - mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 7), 0); - mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 7), MXC_GPIO_DIRECTION_OUT); - mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 6), 0); - mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 6), MXC_GPIO_DIRECTION_OUT); + gpio_direction_output(MXC_GPIO_PORT_TO_NUM(1, 7), 0); + gpio_direction_output(MXC_GPIO_PORT_TO_NUM(1, 6), 0); /* Setup of key input pin GPIO2[29]*/ writel(gpio_mux_mode5 | MX25_PIN_MUX_SION, &muxctl->pad_kpp_row0); writel(0, &padctl->pad_kpp_row0); /* Key pull up off */ - mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(2, 29), MXC_GPIO_DIRECTION_IN); + gpio_direction_input(MXC_GPIO_PORT_TO_NUM(2, 29)); /* Setup of status LED outputs */ writel(gpio_mux_mode5, &muxctl->pad_csi_d9); /* GPIO4[21] */ writel(gpio_mux_mode5, &muxctl->pad_csi_d4); /* GPIO1[29] */ /* Switch both LEDs off */ - mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(4, 21), 0); - mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(4, 21), MXC_GPIO_DIRECTION_OUT); - mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 29), 0); - mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 29), MXC_GPIO_DIRECTION_OUT); + gpio_direction_output(MXC_GPIO_PORT_TO_NUM(4, 21), 0); + gpio_direction_output(MXC_GPIO_PORT_TO_NUM(1, 29), 0); /* Setup of CAN1 and CAN2 signals */ writel(gpio_mux_mode6, &muxctl->pad_gpio_a); /* CAN1 TX */ @@ -158,13 +152,12 @@ int board_late_init(void) writel(gpio_mux_mode2, &muxctl->pad_uart2_cts); /* assert PHY reset (low) */ - mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(3, 16), 0); - mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(3, 16), MXC_GPIO_DIRECTION_OUT); + gpio_direction_output(MXC_GPIO_PORT_TO_NUM(3, 16), 0); udelay(5000); /* deassert PHY reset */ - mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(3, 16), 1); + gpio_set_value(MXC_GPIO_PORT_TO_NUM(3, 16), 1); udelay(5000); #endif @@ -172,12 +165,12 @@ int board_late_init(void) e = getenv("gs_base_board"); if (e != NULL) { if (strcmp(e, "G283") == 0) { - int key = mxc_gpio_get(MXC_GPIO_PORT_TO_NUM(2, 29)); + int key = gpio_get_value(MXC_GPIO_PORT_TO_NUM(2, 29)); if (key) { /* Switch on both LEDs to inidcate boot mode */ - mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 29), 0); - mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(4, 21), 0); + gpio_set_value(MXC_GPIO_PORT_TO_NUM(1, 29), 0); + gpio_set_value(MXC_GPIO_PORT_TO_NUM(4, 21), 0); setenv("preboot", "run gs_slow_boot"); } else diff --git a/board/ti/am3517crane/am3517crane.c b/board/ti/am3517crane/am3517crane.c index d007044b2d..cd5683d9be 100644 --- a/board/ti/am3517crane/am3517crane.c +++ b/board/ti/am3517crane/am3517crane.c @@ -24,6 +24,7 @@ #include <common.h> #include <asm/io.h> +#include <asm/arch/mmc_host_def.h> #include <asm/arch/mem.h> #include <asm/arch/mux.h> #include <asm/arch/sys_proto.h> @@ -73,3 +74,11 @@ void set_muxconf_regs(void) { MUX_AM3517CRANE(); } + +#ifdef CONFIG_GENERIC_MMC +int board_mmc_init(bd_t *bis) +{ + omap_mmc_init(0); + return 0; +} +#endif diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index ab50514f25..e07f1b8f82 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -50,6 +50,7 @@ extern struct ehci_hccr *hccr; extern volatile struct ehci_hcor *hcor; #endif #include "beagle.h" +#include <command.h> #define pr_debug(fmt, args...) debug(fmt, ##args) @@ -164,6 +165,28 @@ unsigned int get_expansion_id(void) } /* + * Configure DSS to display background color on DVID + * Configure VENC to display color bar on S-Video + */ +void beagle_display_init(void) +{ + omap3_dss_venc_config(&venc_config_std_tv, VENC_HEIGHT, VENC_WIDTH); + switch (get_board_revision()) { + case REVISION_AXBX: + case REVISION_CX: + case REVISION_C4: + omap3_dss_panel_config(&dvid_cfg); + break; + case REVISION_XM_A: + case REVISION_XM_B: + case REVISION_XM_C: + default: + omap3_dss_panel_config(&dvid_cfg_xm); + break; + } +} + +/* * Routine: misc_init_r * Description: Configure board specific parts */ @@ -216,6 +239,16 @@ int misc_init_r(void) TWL4030_PM_RECEIVER_VAUX2_DEV_GRP, TWL4030_PM_RECEIVER_DEV_GRP_P1); break; + case REVISION_XM_C: + printf("Beagle xM Rev C\n"); + setenv("beaglerev", "xMC"); + MUX_BEAGLE_XM(); + /* Set VAUX2 to 1.8V for EHCI PHY */ + twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED, + TWL4030_PM_RECEIVER_VAUX2_VSEL_18, + TWL4030_PM_RECEIVER_VAUX2_DEV_GRP, + TWL4030_PM_RECEIVER_DEV_GRP_P1); + break; default: printf("Beagle unknown 0x%02x\n", get_board_revision()); MUX_BEAGLE_XM(); @@ -299,20 +332,30 @@ int misc_init_r(void) setenv(expansion_config.env_var, expansion_config.env_setting); twl4030_power_init(); - twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); - - /* Configure GPIOs to output */ - writel(~(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe); - writel(~(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 | - GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe); + switch (get_board_revision()) { + case REVISION_XM_A: + case REVISION_XM_B: + twl4030_led_init(TWL4030_LED_LEDEN_LEDBON); + break; + default: + twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); + break; + } - /* Set GPIOs */ + /* Set GPIO states before they are made outputs */ writel(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1, &gpio6_base->setdataout); writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 | GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout); + /* Configure GPIOs to output */ + writel(~(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe); + writel(~(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 | + GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe); + dieid_num_r(); + beagle_display_init(); + omap3_dss_enable(); return 0; } @@ -346,6 +389,12 @@ int ehci_hcd_stop(void) pr_debug("Resetting OMAP3 EHCI\n"); omap_set_gpio_dataout(GPIO_PHY_RESET, 0); writel(OMAP_UHH_SYSCONFIG_SOFTRESET, OMAP3_UHH_BASE + OMAP_UHH_SYSCONFIG); + /* disable USB clocks */ + struct prcm *prcm_base = (struct prcm *)PRCM_BASE; + sr32(&prcm_base->iclken_usbhost, 0, 1, 0); + sr32(&prcm_base->fclken_usbhost, 0, 2, 0); + sr32(&prcm_base->iclken3_core, 2, 1, 0); + sr32(&prcm_base->fclken3_core, 2, 1, 0); return 0; } @@ -430,3 +479,58 @@ int ehci_hcd_init(void) } #endif /* CONFIG_USB_EHCI */ + +/* + * This command returns the status of the user button on beagle xM + * Input - none + * Returns - 1 if button is held down + * 0 if button is not held down + */ +int do_userbutton (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + int button = 0; + int gpio; + + /* + * pass address parameter as argv[0] (aka command name), + * and all remaining args + */ + switch (get_board_revision()) { + case REVISION_AXBX: + case REVISION_CX: + case REVISION_C4: + gpio = 7; + break; + case REVISION_XM_A: + case REVISION_XM_B: + case REVISION_XM_C: + default: + gpio = 4; + break; + } + omap_request_gpio(gpio); + omap_set_gpio_direction(gpio, 1); + printf("The user button is currently "); + if(omap_get_gpio_datain(gpio)) + { + button = 1; + printf("PRESSED.\n"); + } + else + { + button = 0; + printf("NOT pressed.\n"); + } + + omap_free_gpio(gpio); + + return !button; +} + +/* -------------------------------------------------------------------- */ + +U_BOOT_CMD( + userbutton, CONFIG_SYS_MAXARGS, 1, do_userbutton, + "Return the status of the BeagleBoard USER button", + "" +); diff --git a/board/ti/beagle/beagle.h b/board/ti/beagle/beagle.h index a7401b1e7c..18bfaa8dec 100644 --- a/board/ti/beagle/beagle.h +++ b/board/ti/beagle/beagle.h @@ -23,6 +23,8 @@ #ifndef _BEAGLE_H_ #define _BEAGLE_H_ +#include <asm/arch/dss.h> + const omap3_sysinfo sysinfo = { DDR_STACKED, "OMAP3 Beagle board", @@ -39,6 +41,7 @@ const omap3_sysinfo sysinfo = { #define REVISION_C4 0x5 #define REVISION_XM_A 0x0 #define REVISION_XM_B 0x1 +#define REVISION_XM_C 0x2 /* * IEN - Input Enable @@ -471,4 +474,88 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(MMC2_DAT6), (IDIS | PTU | EN | M4)) /*GPIO_138 BT_EN*/\ MUX_VAL(CP(MMC2_DAT7), (IDIS | PTU | EN | M4)) /*GPIO_139 WLAN_EN*/ +/* + * Display Configuration + */ + +#define DVI_BEAGLE_ORANGE_COL 0x00FF8000 +#define VENC_HEIGHT 0x00ef +#define VENC_WIDTH 0x027f + +/* + * Configure VENC in DSS for Beagle to generate Color Bar + * + * Kindly refer to OMAP TRM for definition of these values. + */ +static const struct venc_regs venc_config_std_tv = { + .status = 0x0000001B, + .f_control = 0x00000040, + .vidout_ctrl = 0x00000000, + .sync_ctrl = 0x00008000, + .llen = 0x00008359, + .flens = 0x0000020C, + .hfltr_ctrl = 0x00000000, + .cc_carr_wss_carr = 0x043F2631, + .c_phase = 0x00000024, + .gain_u = 0x00000130, + .gain_v = 0x00000198, + .gain_y = 0x000001C0, + .black_level = 0x0000006A, + .blank_level = 0x0000005C, + .x_color = 0x00000000, + .m_control = 0x00000001, + .bstamp_wss_data = 0x0000003F, + .s_carr = 0x21F07C1F, + .line21 = 0x00000000, + .ln_sel = 0x00000015, + .l21__wc_ctl = 0x00001400, + .htrigger_vtrigger = 0x00000000, + .savid__eavid = 0x069300F4, + .flen__fal = 0x0016020C, + .lal__phase_reset = 0x00060107, + .hs_int_start_stop_x = 0x008D034E, + .hs_ext_start_stop_x = 0x000F0359, + .vs_int_start_x = 0x01A00000, + .vs_int_stop_x__vs_int_start_y = 0x020501A0, + .vs_int_stop_y__vs_ext_start_x = 0x01AC0024, + .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC, + .vs_ext_stop_y = 0x00000006, + .avid_start_stop_x = 0x03480079, + .avid_start_stop_y = 0x02040024, + .fid_int_start_x__fid_int_start_y = 0x0001008A, + .fid_int_offset_y__fid_ext_start_x = 0x01AC0106, + .fid_ext_start_y__fid_ext_offset_y = 0x01060006, + .tvdetgp_int_start_stop_x = 0x00140001, + .tvdetgp_int_start_stop_y = 0x00010001, + .gen_ctrl = 0x00FF0000, + .output_control = 0x0000000D, + .dac_b__dac_c = 0x00000000 +}; + +/* + * Configure Timings for DVI D + */ +static const struct panel_config dvid_cfg = { + .timing_h = 0x0ff03f31, /* Horizantal timing */ + .timing_v = 0x01400504, /* Vertical timing */ + .pol_freq = 0x00007028, /* Pol Freq */ + .divisor = 0x00010006, /* 72Mhz Pixel Clock */ + .lcd_size = 0x02ff03ff, /* 1024x768 */ + .panel_type = 0x01, /* TFT */ + .data_lines = 0x03, /* 24 Bit RGB */ + .load_mode = 0x02, /* Frame Mode */ + .panel_color = DVI_BEAGLE_ORANGE_COL /* ORANGE */ +}; + +static const struct panel_config dvid_cfg_xm = { + .timing_h = 0x1a4024c9, /* Horizantal timing */ + .timing_v = 0x02c00509, /* Vertical timing */ + .pol_freq = 0x00007028, /* Pol Freq */ + .divisor = 0x00010001, /* 96MHz Pixel Clock */ + .lcd_size = 0x02ff03ff, /* 1024x768 */ + .panel_type = 0x01, /* TFT */ + .data_lines = 0x03, /* 24 Bit RGB */ + .load_mode = 0x02, /* Frame Mode */ + .panel_color = DVI_BEAGLE_ORANGE_COL /* ORANGE */ +}; #endif diff --git a/board/ti/beagle/led.c b/board/ti/beagle/led.c index 08f95a0a16..f08c08ad88 100644 --- a/board/ti/beagle/led.c +++ b/board/ti/beagle/led.c @@ -24,11 +24,9 @@ #include <asm/arch/sys_proto.h> #include <asm/arch/gpio.h> -static unsigned int saved_state[2] = {STATUS_LED_OFF, STATUS_LED_OFF}; - /* GPIO pins for the LEDs */ -#define BEAGLE_LED_USR0 149 -#define BEAGLE_LED_USR1 150 +#define BEAGLE_LED_USR0 150 +#define BEAGLE_LED_USR1 149 #ifdef STATUS_LED_GREEN void green_LED_off (void) @@ -49,22 +47,22 @@ void __led_init (led_id_t mask, int state) void __led_toggle (led_id_t mask) { + int state, toggle_gpio = 0; #ifdef STATUS_LED_BIT - if (STATUS_LED_BIT & mask) { - if (STATUS_LED_ON == saved_state[0]) - __led_set(STATUS_LED_BIT, 0); - else - __led_set(STATUS_LED_BIT, 1); - } + if (!toggle_gpio && STATUS_LED_BIT & mask) + toggle_gpio = BEAGLE_LED_USR0; #endif #ifdef STATUS_LED_BIT1 - if (STATUS_LED_BIT1 & mask) { - if (STATUS_LED_ON == saved_state[1]) - __led_set(STATUS_LED_BIT1, 0); - else - __led_set(STATUS_LED_BIT1, 1); - } + if (!toggle_gpio && STATUS_LED_BIT1 & mask) + toggle_gpio = BEAGLE_LED_USR1; #endif + if (toggle_gpio) { + if (!omap_request_gpio(toggle_gpio)) { + omap_set_gpio_direction(toggle_gpio, 0); + state = omap_get_gpio_dataout(toggle_gpio); + omap_set_gpio_dataout(toggle_gpio, !state); + } + } } void __led_set (led_id_t mask, int state) @@ -75,7 +73,6 @@ void __led_set (led_id_t mask, int state) omap_set_gpio_direction(BEAGLE_LED_USR0, 0); omap_set_gpio_dataout(BEAGLE_LED_USR0, state); } - saved_state[0] = state; } #endif #ifdef STATUS_LED_BIT1 @@ -84,7 +81,6 @@ void __led_set (led_id_t mask, int state) omap_set_gpio_direction(BEAGLE_LED_USR1, 0); omap_set_gpio_dataout(BEAGLE_LED_USR1, state); } - saved_state[1] = state; } #endif } diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c index 30c1c570f1..e8360df960 100644 --- a/board/ti/evm/evm.c +++ b/board/ti/evm/evm.c @@ -33,6 +33,7 @@ #include <asm/arch/mem.h> #include <asm/arch/mux.h> #include <asm/arch/sys_proto.h> +#include <asm/arch/mmc_host_def.h> #include <asm/arch/gpio.h> #include <i2c.h> #include <asm/mach-types.h> @@ -221,3 +222,11 @@ int board_eth_init(bd_t *bis) return rc; } #endif /* CONFIG_CMD_NET */ + +#ifdef CONFIG_GENERIC_MMC +int board_mmc_init(bd_t *bis) +{ + omap_mmc_init(0); + return 0; +} +#endif diff --git a/board/ti/omap1610inn/omap1610innovator.c b/board/ti/omap1610inn/omap1610innovator.c index 44818bbdae..16e823766a 100644 --- a/board/ti/omap1610inn/omap1610innovator.c +++ b/board/ti/omap1610inn/omap1610innovator.c @@ -63,13 +63,6 @@ static inline void delay (unsigned long loops) int board_init (void) { - if (machine_is_omap_h2()) - gd->bd->bi_arch_number = MACH_TYPE_OMAP_H2; - else if (machine_is_omap_innovator()) - gd->bd->bi_arch_number = MACH_TYPE_OMAP_INNOVATOR; - else - gd->bd->bi_arch_number = MACH_TYPE_OMAP_GENERIC; - /* adress of boot parameters */ gd->bd->bi_boot_params = 0x10000100; diff --git a/board/ti/sdp3430/sdp.c b/board/ti/sdp3430/sdp.c index 72f0984d67..d73f501819 100644 --- a/board/ti/sdp3430/sdp.c +++ b/board/ti/sdp3430/sdp.c @@ -25,6 +25,7 @@ #include <netdev.h> #include <twl4030.h> #include <asm/io.h> +#include <asm/arch/mmc_host_def.h> #include <asm/arch/mux.h> #include <asm/arch/mem.h> #include <asm/arch/sys_proto.h> @@ -204,3 +205,11 @@ void set_muxconf_regs(void) /* platform specific muxes */ MUX_SDP3430(); } + +#ifdef CONFIG_GENERIC_MMC +int board_mmc_init(bd_t *bis) +{ + omap_mmc_init(0); + return 0; +} +#endif diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c index 95afaaaaa4..533af5a60a 100644 --- a/board/timll/devkit8000/devkit8000.c +++ b/board/timll/devkit8000/devkit8000.c @@ -35,6 +35,7 @@ #include <common.h> #include <twl4030.h> #include <asm/io.h> +#include <asm/arch/mmc_host_def.h> #include <asm/arch/mux.h> #include <asm/arch/sys_proto.h> #include <asm/arch/mem.h> @@ -119,6 +120,14 @@ void set_muxconf_regs(void) MUX_DEVKIT8000(); } +#ifdef CONFIG_GENERIC_MMC +int board_mmc_init(bd_t *bis) +{ + omap_mmc_init(0); + return 0; +} +#endif + #ifdef CONFIG_DRIVER_DM9000 /* * Routine: board_eth_init diff --git a/board/ttcontrol/vision2/vision2.c b/board/ttcontrol/vision2/vision2.c index 565c4d05ba..17a25587d6 100644 --- a/board/ttcontrol/vision2/vision2.c +++ b/board/ttcontrol/vision2/vision2.c @@ -29,7 +29,7 @@ #include <asm/arch/mx5x_pins.h> #include <asm/arch/crm_regs.h> #include <asm/arch/iomux.h> -#include <mxc_gpio.h> +#include <asm/gpio.h> #include <asm/arch/sys_proto.h> #include <asm/errno.h> #include <i2c.h> @@ -69,9 +69,9 @@ void hw_watchdog_reset(void) int val; /* toggle watchdog trigger pin */ - val = mxc_gpio_get(66); + val = gpio_get_value(66); val = val ? 0 : 1; - mxc_gpio_set(66, val); + gpio_set_value(66, val); } #endif @@ -233,30 +233,22 @@ static void reset_peripherals(int reset) if (reset) { /* reset_n is on NANDF_D15 */ - mxc_gpio_set(89, 0); - mxc_gpio_direction(89, MXC_GPIO_DIRECTION_OUT); + gpio_direction_output(89, 0); #ifdef CONFIG_VISION2_HW_1_0 /* * set FEC Configuration lines * set levels of FEC config lines */ - mxc_gpio_set(75, 0); - mxc_gpio_set(74, 1); - mxc_gpio_set(95, 1); - mxc_gpio_direction(75, MXC_GPIO_DIRECTION_OUT); - mxc_gpio_direction(74, MXC_GPIO_DIRECTION_OUT); - mxc_gpio_direction(95, MXC_GPIO_DIRECTION_OUT); + gpio_direction_output(75, 0); + gpio_direction_output(74, 1); + gpio_direction_output(95, 1); /* set direction of FEC config lines */ - mxc_gpio_set(59, 0); - mxc_gpio_set(60, 0); - mxc_gpio_set(61, 0); - mxc_gpio_set(55, 1); - mxc_gpio_direction(59, MXC_GPIO_DIRECTION_OUT); - mxc_gpio_direction(60, MXC_GPIO_DIRECTION_OUT); - mxc_gpio_direction(61, MXC_GPIO_DIRECTION_OUT); - mxc_gpio_direction(55, MXC_GPIO_DIRECTION_OUT); + gpio_direction_output(59, 0); + gpio_direction_output(60, 0); + gpio_direction_output(61, 0); + gpio_direction_output(55, 1); /* FEC_RXD1 - sel GPIO (2-23) for configuration -> 1 */ mxc_request_iomux(MX51_PIN_EIM_EB3, IOMUX_CONFIG_ALT1); @@ -283,7 +275,7 @@ static void reset_peripherals(int reset) PAD_CTL_DRV_VOT_HIGH | PAD_CTL_DRV_MAX); } else { /* set FEC Control lines */ - mxc_gpio_direction(89, MXC_GPIO_DIRECTION_IN); + gpio_direction_input(89); udelay(500); #ifdef CONFIG_VISION2_HW_1_0 @@ -438,31 +430,23 @@ static void setup_gpios(void) * Set GPIO1_4 to high and output; it is used to reset * the system on reboot */ - mxc_gpio_set(4, 1); - mxc_gpio_direction(4, MXC_GPIO_DIRECTION_OUT); + gpio_direction_output(4, 1); - mxc_gpio_set(7, 0); - mxc_gpio_direction(7, MXC_GPIO_DIRECTION_OUT); + gpio_direction_output(7, 0); for (i = 65; i < 71; i++) { - mxc_gpio_set(i, 0); - mxc_gpio_direction(i, MXC_GPIO_DIRECTION_OUT); + gpio_direction_output(i, 0); } - mxc_gpio_set(94, 0); - mxc_gpio_direction(94, MXC_GPIO_DIRECTION_OUT); + gpio_direction_output(94, 0); /* Set POWER_OFF high */ - mxc_gpio_set(91, 1); - mxc_gpio_direction(91, MXC_GPIO_DIRECTION_OUT); + gpio_direction_output(91, 1); - mxc_gpio_set(90, 0); - mxc_gpio_direction(90, MXC_GPIO_DIRECTION_OUT); + gpio_direction_output(90, 0); - mxc_gpio_set(122, 0); - mxc_gpio_direction(122, MXC_GPIO_DIRECTION_OUT); + gpio_direction_output(122, 0); - mxc_gpio_set(121, 1); - mxc_gpio_direction(121, MXC_GPIO_DIRECTION_OUT); + gpio_direction_output(121, 1); WATCHDOG_RESET(); } @@ -551,7 +535,7 @@ int get_mmc_getcd(u8 *cd, struct mmc *mmc) struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) - *cd = mxc_gpio_get(0); + *cd = gpio_get_value(0); else *cd = 0; @@ -623,8 +607,7 @@ int board_early_init_f(void) init_drive_strength(); /* Setup debug led */ - mxc_gpio_set(6, 0); - mxc_gpio_direction(6, MXC_GPIO_DIRECTION_OUT); + gpio_direction_output(6, 0); mxc_request_iomux(MX51_PIN_GPIO1_6, IOMUX_CONFIG_ALT0); mxc_iomux_set_pad(MX51_PIN_GPIO1_6, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST); @@ -644,12 +627,12 @@ int board_early_init_f(void) static void backlight(int on) { if (on) { - mxc_gpio_set(65, 1); + gpio_set_value(65, 1); udelay(10000); - mxc_gpio_set(68, 1); + gpio_set_value(68, 1); } else { - mxc_gpio_set(65, 0); - mxc_gpio_set(68, 0); + gpio_set_value(65, 0); + gpio_set_value(68, 0); } } @@ -660,7 +643,7 @@ void lcd_enable(void) mxc_request_iomux(MX51_PIN_DI1_PIN2, IOMUX_CONFIG_ALT0); mxc_request_iomux(MX51_PIN_DI1_PIN3, IOMUX_CONFIG_ALT0); - mxc_gpio_set(2, 1); + gpio_set_value(2, 1); mxc_request_iomux(MX51_PIN_GPIO1_2, IOMUX_CONFIG_ALT0); ret = mx51_fb_init(&nec_nl6448bc26_09c); diff --git a/board/voiceblue/Makefile b/board/voiceblue/Makefile deleted file mode 100644 index e16b195c3c..0000000000 --- a/board/voiceblue/Makefile +++ /dev/null @@ -1,74 +0,0 @@ -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de -# -# (C) Copyright 2005 -# Ladislav Michl, 2N Telekomunikace, michl@2n.cz -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License version 2 as -# published by the Free Software Foundation. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := voiceblue.o -SOBJS := setup.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -LOAD_ADDR = 0x10400000 - -######################################################################### - -all: $(obj).depend $(LIB) $(obj)eeprom.srec $(obj)eeprom.bin - -$(LIB): $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $^) - -$(obj)eeprom_start.o: - echo "b eeprom" | $(CC) $(AFLAGS) -c -x assembler -o $@ - - -$(obj)eeprom: $(obj)eeprom_start.o $(obj)eeprom.o - $(LD) -Ttext $(LOAD_ADDR) -e eeprom -o $@ $^ \ - -L$(obj)../../examples/standalone -lstubs \ - $(PLATFORM_LIBS) - -$(obj)eeprom.srec: $(obj)eeprom - $(OBJCOPY) -S -O srec $(<:.o=) $@ - -$(obj)eeprom.bin: $(obj)eeprom - $(OBJCOPY) -S -O binary $< $@ - -clean: - rm -f $(SOBJS) $(OBJS) $(obj)eeprom \ - $(obj)eeprom.srec $(obj)eeprom.bin \ - $(obj)eeprom.o $(obj)eeprom_start.o - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/voiceblue/config.mk b/board/voiceblue/config.mk deleted file mode 100644 index 412b57d27e..0000000000 --- a/board/voiceblue/config.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x13FD0000 diff --git a/board/voiceblue/eeprom.c b/board/voiceblue/eeprom.c deleted file mode 100644 index aa6baca645..0000000000 --- a/board/voiceblue/eeprom.c +++ /dev/null @@ -1,218 +0,0 @@ -/* - * (C) Copyright 2005 - * Ladislav Michl, 2N Telekomunikace, michl@2n.cz - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - * Some code shamelessly stolen back from Robin Getz. - */ - -#include <common.h> -#include <exports.h> -#include <timestamp.h> -#include <net.h> -#include "../drivers/net/smc91111.h" - -static struct eth_device dev = { - .iobase = CONFIG_SMC91111_BASE -}; - -static u16 read_eeprom_reg(u16 reg) -{ - int timeout; - - SMC_SELECT_BANK(&dev, 2); - SMC_outw(&dev, reg, PTR_REG); - - SMC_SELECT_BANK(&dev, 1); - SMC_outw(&dev, SMC_inw(&dev, CTL_REG) | CTL_EEPROM_SELECT | - CTL_RELOAD, CTL_REG); - - timeout = 100; - - while ((SMC_inw(&dev, CTL_REG) & CTL_RELOAD) && --timeout) - udelay(100); - if (timeout == 0) { - printf("Timeout reading register %02x\n", reg); - return 0; - } - - return SMC_inw(&dev, GP_REG); -} - -static int write_eeprom_reg(u16 value, u16 reg) -{ - int timeout; - - SMC_SELECT_BANK(&dev, 2); - SMC_outw(&dev, reg, PTR_REG); - - SMC_SELECT_BANK(&dev, 1); - - SMC_outw(&dev, value, GP_REG); - SMC_outw(&dev, SMC_inw(&dev, CTL_REG) | CTL_EEPROM_SELECT | - CTL_STORE, CTL_REG); - - timeout = 100; - - while ((SMC_inw(&dev, CTL_REG) & CTL_STORE) && --timeout) - udelay(100); - if (timeout == 0) { - printf("Timeout writing register %02x\n", reg); - return 0; - } - - return 1; -} - -static int write_data(u16 *buf, int len) -{ - u16 reg = 0x23; - - while (len--) - write_eeprom_reg(*buf++, reg++); - - return 0; -} - -static int verify_macaddr(char *s) -{ - u16 reg; - int i, err = 0; - - puts("HWaddr: "); - for (i = 0; i < 3; i++) { - reg = read_eeprom_reg(0x20 + i); - printf("%02x:%02x%c", reg & 0xff, reg >> 8, i != 2 ? ':' : '\n'); - if (s) - err |= reg != ((u16 *)s)[i]; - } - - return err ? 0 : 1; -} - -static int set_mac(char *s) -{ - int i; - char *e, eaddr[6]; - - /* turn string into mac value */ - for (i = 0; i < 6; i++) { - eaddr[i] = simple_strtoul(s, &e, 16); - s = (*e) ? e+1 : e; - } - - for (i = 0; i < 3; i++) - write_eeprom_reg(*(((u16 *)eaddr) + i), 0x20 + i); - - return 0; -} - -static int parse_element(char *s, unsigned char *buf, int len) -{ - int cnt; - char *p, num[3]; - unsigned char id; - - id = simple_strtoul(s, &p, 16); - if (*p++ != ':') - return -1; - cnt = 2; - num[2] = 0; - for (; *p; p += 2) { - if (p[1] == 0) - return -2; - if (cnt + 3 > len) - return -3; - num[0] = p[0]; - num[1] = p[1]; - buf[cnt++] = simple_strtoul(num, NULL, 16); - } - buf[0] = id; - buf[1] = cnt - 2; - - return cnt; -} - -int eeprom(int argc, char * const argv[]) -{ - int i, len, ret; - unsigned char buf[58], *p; - - app_startup(argv); - i = get_version(); - if (i != XF_VERSION) { - printf("Using ABI version %d, but U-Boot provides %d\n", - XF_VERSION, i); - return 1; - } - - if ((SMC_inw(&dev, BANK_SELECT) & 0xFF00) != 0x3300) { - puts("SMSC91111 not found\n"); - return 2; - } - - /* Called without parameters - print MAC address */ - if (argc < 2) { - verify_macaddr(NULL); - return 0; - } - - /* Print help message */ - if (argv[1][1] == 'h') { - puts("VoiceBlue EEPROM writer\n" - "Built: " U_BOOT_DATE " at " U_BOOT_TIME "\n" - "Usage:\n\t<mac_address> [<element_1>] [<...>]\n"); - return 0; - } - - /* Try to parse information elements */ - len = sizeof(buf); - p = buf; - for (i = 2; i < argc; i++) { - ret = parse_element(argv[i], p, len); - switch (ret) { - case -1: - printf("Element %d: malformed\n", i - 1); - return 3; - case -2: - printf("Element %d: odd character count\n", i - 1); - return 3; - case -3: - puts("Out of EEPROM memory\n"); - return 3; - default: - p += ret; - len -= ret; - } - } - - /* First argument (MAC) is mandatory */ - set_mac(argv[1]); - if (verify_macaddr(argv[1])) { - puts("*** HWaddr does not match! ***\n"); - return 4; - } - - while (len--) - *p++ = 0; - - write_data((u16 *)buf, sizeof(buf) >> 1); - - return 0; -} diff --git a/board/voiceblue/setup.S b/board/voiceblue/setup.S deleted file mode 100644 index 6dddd6bdcf..0000000000 --- a/board/voiceblue/setup.S +++ /dev/null @@ -1,280 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2004 Ales Jindra <jindra@2n.cz> - * (C) Copyright 2005 Ladislav Michl <michl@2n.cz> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <version.h> - -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE /* SDRAM load addr from config.mk */ - -OMAP5910_LPG1_BASE: .word 0xfffbd000 -OMAP5910_TIPB_SWITCHES_BASE: .word 0xfffbc800 -OMAP5910_MPU_TC_BASE: .word 0xfffecc00 -OMAP5910_MPU_CLKM_BASE: .word 0xfffece00 -OMAP5910_ULPD_PWR_MNG_BASE: .word 0xfffe0800 -OMAP5910_DPLL1_BASE: .word 0xfffecf00 -OMAP5910_GPIO_BASE: .word 0xfffce000 -OMAP5910_MPU_WD_TIMER_BASE: .word 0xfffec800 -OMAP5910_MPUI_BASE: .word 0xfffec900 - -_OMAP5910_ARM_CKCTL: .word OMAP5910_ARM_CKCTL -_OMAP5910_ARM_EN_CLK: .word OMAP5910_ARM_EN_CLK - -OMAP5910_MPUI_CTRL: .word 0x0000ff1b - -VAL_EMIFS_CS0_CONFIG: .word 0x00009090 -VAL_EMIFS_CS1_CONFIG: .word 0x00003031 -VAL_EMIFS_CS2_CONFIG: .word 0x00003031 -VAL_EMIFS_CS3_CONFIG: .word 0x0000c0c0 -VAL_EMIFS_DYN_WAIT: .word 0x00000000 -/* autorefresh counter 0x246 ((64000000/13.4)-400)/8192) */ - /* SLRF SD_RET ARE SDRAM_TYPE ARCV SDRAM_FREQUENCY PWD CLK */ -VAL_EMIFF_SDRAM_CONFIG: .word ((0 << 0) | (0 << 1) | (3 << 2) | (0xd << 4) | (0x246 << 8) | (0 << 24) | (0 << 26) | (0 << 27)) -VAL_EMIFF_SDRAM_CONFIG2: .word 0x00000003 -VAL_EMIFF_MRS: .word 0x00000037 - -/* - * GPIO04 - D4 (Onboard LED) - * GPIO07 - LAN91C111 reset - */ -GPIO_DIRECTION: - .word 0x0000ff6f -/* - * Disable everything, but D4 LED (connected through invertor) - */ -GPIO_OUTPUT: - .word 0x00000010 - -MUX_CONFIG_BASE: - .word 0xfffe1000 - -MUX_CONFIG_VALUES: - .align 4 - .word 0x00000000 @ FUNC_MUX_CTRL_0 - .word 0x00000000 @ FUNC_MUX_CTRL_1 - .word 0x00000000 @ FUNC_MUX_CTRL_2 - .word 0x00000000 @ FUNC_MUX_CTRL_3 - .word 0x00000000 @ FUNC_MUX_CTRL_4 - .word 0x12082480 @ FUNC_MUX_CTRL_5 - .word 0x0000001c @ FUNC_MUX_CTRL_6 - .word 0x00000003 @ FUNC_MUX_CTRL_7 - .word 0x10001200 @ FUNC_MUX_CTRL_8 - .word 0x01201012 @ FUNC_MUX_CTRL_9 - .word 0x02081248 @ FUNC_MUX_CTRL_A - .word 0x00001248 @ FUNC_MUX_CTRL_B - .word 0x12240000 @ FUNC_MUX_CTRL_C - .word 0x00002000 @ FUNC_MUX_CTRL_D - .word 0x00000000 @ PULL_DWN_CTRL_0 - .word 0x0000085f @ PULL_DWN_CTRL_1 - .word 0x01001000 @ PULL_DWN_CTRL_2 - .word 0x00000000 @ PULL_DWN_CTRL_3 - .word 0x00000000 @ GATE_INH_CTRL_0 - .word 0x00000000 @ VOLTAGE_CTRL_0 - .word 0x00000000 @ TEST_DBG_CTRL_0 - .word 0x00000006 @ MOD_CONF_CTRL_0 - .word 0x0000eaef @ COMP_MODE_CTRL_0 - -MUX_CONFIG_OFFSETS: - .align 1 - .byte 0x00 @ FUNC_MUX_CTRL_0 - .byte 0x04 @ FUNC_MUX_CTRL_1 - .byte 0x08 @ FUNC_MUX_CTRL_2 - .byte 0x10 @ FUNC_MUX_CTRL_3 - .byte 0x14 @ FUNC_MUX_CTRL_4 - .byte 0x18 @ FUNC_MUX_CTRL_5 - .byte 0x1c @ FUNC_MUX_CTRL_6 - .byte 0x20 @ FUNC_MUX_CTRL_7 - .byte 0x24 @ FUNC_MUX_CTRL_8 - .byte 0x28 @ FUNC_MUX_CTRL_9 - .byte 0x2c @ FUNC_MUX_CTRL_A - .byte 0x30 @ FUNC_MUX_CTRL_B - .byte 0x34 @ FUNC_MUX_CTRL_C - .byte 0x38 @ FUNC_MUX_CTRL_D - .byte 0x40 @ PULL_DWN_CTRL_0 - .byte 0x44 @ PULL_DWN_CTRL_1 - .byte 0x48 @ PULL_DWN_CTRL_2 - .byte 0x4c @ PULL_DWN_CTRL_3 - .byte 0x50 @ GATE_INH_CTRL_0 - .byte 0x60 @ VOLTAGE_CTRL_0 - .byte 0x70 @ TEST_DBG_CTRL_0 - .byte 0x80 @ MOD_CONF_CTRL_0 - .byte 0x0c @ COMP_MODE_CTRL_0 - .byte 0xff - -.globl lowlevel_init -lowlevel_init: - /* Improve performance a bit... */ - mrc p15, 0, r1, c0, c0, 0 @ read C15 ID register - mrc p15, 0, r1, c0, c0, 1 @ read C15 Cache information register - mrc p15, 0, r1, c1, c0, 0 @ read C15 Control register - orr r1, r1, #0x1000 @ enable I-cache, map interrupt vector 0xffff0000 - mcr p15, 0, r1, c1, c0, 0 @ write C15 Control register - mov r1, #0x00 - mcr p15, 0, r1, c7, c5, 0 @ Flush I-cache - nop - nop - nop - nop - - /* Setup clocking mode */ - ldr r0, OMAP5910_MPU_CLKM_BASE @ prepare base of CLOCK unit - ldrh r1, [r0, #0x18] @ get reset status - bic r1, r1, #(7 << 11) @ clear clock select - orr r1, r1, #(2 << 11) @ set synchronous scalable - mov r2, #0 @ set wait counter to 100 clock cycles - -icache_loop: - cmp r2, #0x01 - streqh r1, [r0, #0x18] - add r2, r2, #0x01 - cmp r2, #0x10 - bne icache_loop - nop - - /* Setup clock divisors */ - ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit - ldr r1, _OMAP5910_ARM_CKCTL - orr r1, r1, #0x2000 @ enable DSP clock - strh r1, [r0, #0x00] @ setup clock divisors - - /* Setup DPLL to generate requested freq */ - ldr r0, OMAP5910_DPLL1_BASE @ base of DPLL1 register - mov r1, #0x0010 @ set PLL_ENABLE - orr r1, r1, #0x2000 @ set IOB to new locking - orr r1, r1, #(OMAP5910_DPLL_MUL << 7) @ setup multiplier CLKREF - orr r1, r1, #(OMAP5910_DPLL_DIV << 5) @ setup divider CLKREF - strh r1, [r0] @ write - -locking: - ldrh r1, [r0] @ get DPLL value - tst r1, #0x01 - beq locking @ while LOCK not set - - /* Enable clock */ - ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit - mov r1, #(1 << 10) @ disable idle mode do not check - @ nWAKEUP pin, other remain active - strh r1, [r0, #0x04] - ldr r1, _OMAP5910_ARM_EN_CLK - strh r1, [r0, #0x08] - mov r1, #0x003f @ FLASH.RP not enabled in idle and - @ max delayed ( 32 x CLKIN ) - strh r1, [r0, #0x0c] - - /* Configure 5910 pins functions to match our board. */ - ldr r0, MUX_CONFIG_BASE - adr r1, MUX_CONFIG_VALUES - adr r2, MUX_CONFIG_OFFSETS -next_mux_cfg: - ldrb r3, [r2], #1 - ldr r4, [r1], #4 - cmp r3, #0xff - strne r4, [r0, r3] - bne next_mux_cfg - - /* Configure GPIO pins (also enables onboard LED) */ - ldr r0, OMAP5910_GPIO_BASE - ldr r1, GPIO_OUTPUT - strh r1, [r0, #0x04] - ldr r1, GPIO_DIRECTION - strh r1, [r0, #0x08] - - /* EnablePeripherals */ - ldr r0, OMAP5910_MPU_CLKM_BASE @ CLOCK unit - mov r1, #0x0001 @ Peripheral enable - strh r1, [r0, #0x14] - - /* Program LED Pulse Generator */ - ldr r0, OMAP5910_LPG1_BASE @ 1st LED Pulse Generator - mov r1, #0x7F @ Set obscure frequency in - strb r1, [r0, #0x00] @ LCR - mov r1, #0x01 @ Enable clock (CLK_EN) in - strb r1, [r0, #0x04] @ PMR - - /* TIPB Lock UART1 */ - ldr r0, OMAP5910_TIPB_SWITCHES_BASE @ prepare base of TIPB switches - mov r1, #1 @ ARM allocated - strh r1, [r0,#0x04] @ clear IRQ line and status bits - strh r1, [r0,#0x00] - ldrh r1, [r0,#0x04] - - /* Disable watchdog */ - ldr r0, OMAP5910_MPU_WD_TIMER_BASE - mov r1, #0xf5 - strh r1, [r0, #0x8] - mov r1, #0xa0 - strh r1, [r0, #0x8] - - /* Enable MCLK */ - ldr r0, OMAP5910_ULPD_PWR_MNG_BASE - mov r1, #0x6 - strh r1, [r0, #0x34] - strh r1, [r0, #0x34] - - /* Setup clock divisors */ - ldr r0, OMAP5910_ULPD_PWR_MNG_BASE @ base of ULDPL DPLL1 register - - mov r1, #0x0010 @ set PLL_ENABLE - orr r1, r1, #0x2000 @ set IOB to new locking - strh r1, [r0] @ write - -ulocking: - ldrh r1, [r0] @ get DPLL value - tst r1, #1 - beq ulocking @ while LOCK not set - - /* EMIF init */ - ldr r0, OMAP5910_MPU_TC_BASE - ldrh r1, [r0, #0x0c] @ EMIFS_CONFIG_REG - bic r1, r1, #0x0c @ pwr down disabled, flash WP - orr r1, r1, #0x01 - str r1, [r0, #0x0c] - - ldr r1, VAL_EMIFS_CS0_CONFIG - str r1, [r0, #0x10] @ EMIFS_CS0_CONFIG - ldr r1, VAL_EMIFS_CS1_CONFIG - str r1, [r0, #0x14] @ EMIFS_CS1_CONFIG - ldr r1, VAL_EMIFS_CS2_CONFIG - str r1, [r0, #0x18] @ EMIFS_CS2_CONFIG - ldr r1, VAL_EMIFS_CS3_CONFIG - str r1, [r0, #0x1c] @ EMIFS_CS3_CONFIG - ldr r1, VAL_EMIFS_DYN_WAIT - str r1, [r0, #0x40] @ EMIFS_CFG_DYN_WAIT - - /* Setup SDRAM */ - ldr r1, VAL_EMIFF_SDRAM_CONFIG - str r1, [r0, #0x20] @ EMIFF_SDRAM_CONFIG - ldr r1, VAL_EMIFF_SDRAM_CONFIG2 - str r1, [r0, #0x3c] @ EMIFF_SDRAM_CONFIG2 - ldr r1, VAL_EMIFF_MRS - str r1, [r0, #0x24] @ EMIFF_MRS - /* SDRAM needs 100us to stabilize */ - mov r0, #0x4000 -sdelay: - subs r0, r0, #0x1 - bne sdelay - - /* back to arch calling code */ - mov pc, lr -.end diff --git a/board/voiceblue/voiceblue.c b/board/voiceblue/voiceblue.c deleted file mode 100644 index 5f8af2bd24..0000000000 --- a/board/voiceblue/voiceblue.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <netdev.h> - -DECLARE_GLOBAL_DATA_PTR; - -int board_init(void) -{ - *((volatile unsigned char *) VOICEBLUE_LED_REG) = 0xaa; - - /* arch number of VoiceBlue board */ - gd->bd->bi_arch_number = MACH_TYPE_VOICEBLUE; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x10000100; - - return 0; -} - -int dram_init(void) -{ - *((volatile unsigned short *) VOICEBLUE_LED_REG) = 0xff; - - /* Take the Ethernet controller out of reset and wait - * for the EEPROM load to complete. */ - *((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) |= 0x80; - udelay(10); /* doesn't work before timer_init call */ - *((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) &= ~0x80; - udelay(500); - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return 0; -} - -int misc_init_r(void) -{ - *((volatile unsigned short *) VOICEBLUE_LED_REG) = 0x55; - - return 0; -} - -int board_late_init(void) -{ - *((volatile unsigned char *) VOICEBLUE_LED_REG) = 0x00; - - return 0; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC91111 - rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); -#endif - return rc; -} -#endif |