diff options
Diffstat (limited to 'board')
169 files changed, 5136 insertions, 661 deletions
diff --git a/board/Barix/ipam390/README.ipam390 b/board/Barix/ipam390/README.ipam390 index 5c45fca59f9..be09280dd81 100644 --- a/board/Barix/ipam390/README.ipam390 +++ b/board/Barix/ipam390/README.ipam390 @@ -31,9 +31,9 @@ loading the next image from a different media, etc). Compilation =========== -run "./MAKEALL ipam390" in the u-boot source tree. -Once this build completes you will have a u-boot.ais file that needs to -be written to the nand flash. +run "tools/buildman/buildman -k ipam390" in the u-boot source tree. +Once this build completes you will have a ../current/ipam390/u-boot.ais file +that needs to be written to the nand flash. Flashing the images to NAND ========================== @@ -71,13 +71,13 @@ here[1] to create an uboot-uart-ais.bin file - cd to the u-boot source tree - compile the u-boot for the ipam390 board: -$ ./MAKEALL ipam390 +$ tools/buildman/buildman -k ipam390 -> Now we shall have u-boot.bin - Create u-boot-uart-ais.bin -$ mono HexAIS_OMAP-L138.exe -entrypoint 0xC1080000 -ini -ipam390-ais-uart.cfg -o ./uboot-uart-ais.bin ./u-boot.bin@0xC1080000; +$ mono HexAIS_OMAP-L138.exe -entrypoint 0xC1080000 -ini ipam390-ais-uart.cfg \ + -o ../current/ipam390/uboot-uart-ais.bin ./u-boot.bin@0xC1080000; Note: The ipam390-ais-uart.cfg is found in the board directory for the ipam390 board, u-boot:/board/Barix/ipam390/ipam390-ais-uart.cfg diff --git a/board/advantech/Kconfig b/board/advantech/Kconfig new file mode 100644 index 00000000000..a8d49691f7f --- /dev/null +++ b/board/advantech/Kconfig @@ -0,0 +1,28 @@ +if VENDOR_ADVANTECH + +choice + prompt "Mainboard model" + optional + +config TARGET_SOM_DB5800_SOM_6867 + bool "Advantech SOM-DB5800 & SOM-6867" + help + Advantech SOM-DB5800 COM Express development board with SOM-6867 + installed. + + SOM-6867 is a COM Express Type 6 Compact Module with either an Intel + Atom E3845 or Celeron N2920 processor. + + SOM-DB5800 is a COM Express Development board with: + 10/100/1000 Ethernet + PCIe slots + 4x USB ports + HDMI/DisplayPort/DVI, LVDS, VGA + SATA ports + ALC892 HD Audio Codec + +endchoice + +source "board/advantech/som-db5800-som-6867/Kconfig" + +endif diff --git a/board/advantech/som-db5800-som-6867/.gitignore b/board/advantech/som-db5800-som-6867/.gitignore new file mode 100644 index 00000000000..6eb8a5481ab --- /dev/null +++ b/board/advantech/som-db5800-som-6867/.gitignore @@ -0,0 +1,3 @@ +dsdt.aml +dsdt.asl.tmp +dsdt.c diff --git a/board/advantech/som-db5800-som-6867/Kconfig b/board/advantech/som-db5800-som-6867/Kconfig new file mode 100644 index 00000000000..f6f3748fc35 --- /dev/null +++ b/board/advantech/som-db5800-som-6867/Kconfig @@ -0,0 +1,28 @@ +if TARGET_SOM_DB5800_SOM_6867 + +config SYS_BOARD + default "som-db5800-som-6867" + +config SYS_VENDOR + default "advantech" + +config SYS_SOC + default "baytrail" + +config SYS_CONFIG_NAME + default "som-db5800-som-6867" + +config SYS_TEXT_BASE + default 0xfff00000 if !EFI_STUB + default 0x01110000 if EFI_STUB + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select X86_RESET_VECTOR if !EFI_STUB + select INTEL_BAYTRAIL + select BOARD_ROMSIZE_KB_8192 + +config PCIE_ECAM_BASE + default 0xe0000000 + +endif diff --git a/board/advantech/som-db5800-som-6867/MAINTAINERS b/board/advantech/som-db5800-som-6867/MAINTAINERS new file mode 100644 index 00000000000..92989bfba09 --- /dev/null +++ b/board/advantech/som-db5800-som-6867/MAINTAINERS @@ -0,0 +1,7 @@ +Advantech SOM-DB5800-SOM-6867 +M: George McCollister <george.mccollister@gmail.com> +S: Maintained +F: board/advantech/som-db5800-som-6867 +F: include/configs/som-db5800-som-6867.h +F: configs/som-db5800-som-6867_defconfig +F: arch/x86/dts/baytrail_som-db5800-som-6867.dts diff --git a/board/advantech/som-db5800-som-6867/Makefile b/board/advantech/som-db5800-som-6867/Makefile new file mode 100644 index 00000000000..9837aa0c798 --- /dev/null +++ b/board/advantech/som-db5800-som-6867/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2015, Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += som-db5800-som-6867.o start.o +obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o diff --git a/board/advantech/som-db5800-som-6867/acpi/mainboard.asl b/board/advantech/som-db5800-som-6867/acpi/mainboard.asl new file mode 100644 index 00000000000..21785ea73b1 --- /dev/null +++ b/board/advantech/som-db5800-som-6867/acpi/mainboard.asl @@ -0,0 +1,11 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Power Button */ +Device (PWRB) +{ + Name(_HID, EISAID("PNP0C0C")) +} diff --git a/board/advantech/som-db5800-som-6867/dsdt.asl b/board/advantech/som-db5800-som-6867/dsdt.asl new file mode 100644 index 00000000000..6042011acf3 --- /dev/null +++ b/board/advantech/som-db5800-som-6867/dsdt.asl @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000) +{ + /* platform specific */ + #include <asm/arch/acpi/platform.asl> + + /* board specific */ + #include "acpi/mainboard.asl" +} diff --git a/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c b/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c new file mode 100644 index 00000000000..5bed2c11460 --- /dev/null +++ b/board/advantech/som-db5800-som-6867/som-db5800-som-6867.c @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2016 Stefan Roese <sr@denx.de> + * Copyright (C) 2016 George McCollister <george.mccollister@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> + +int board_early_init_f(void) +{ + /* + * The FSP enables the BayTrail internal legacy UART (again). + * Disable it again, so that the one on the EC can be used. + */ + setup_internal_uart(0); + + return 0; +} + +int arch_early_init_r(void) +{ + return 0; +} diff --git a/board/advantech/som-db5800-som-6867/start.S b/board/advantech/som-db5800-som-6867/start.S new file mode 100644 index 00000000000..2c941a4a510 --- /dev/null +++ b/board/advantech/som-db5800-som-6867/start.S @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2015, Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +.globl early_board_init +early_board_init: + jmp early_board_init_ret diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index e95ec81760f..d1e6850636a 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -102,7 +102,7 @@ iomux_v3_cfg_t const usdhc1_pads[] = { int dram_init(void) { - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + gd->ram_size = imx_ddr_size(); return 0; } diff --git a/board/armltd/vexpress/Makefile b/board/armltd/vexpress/Makefile index 1dd6780708c..95f4ec0cbd8 100644 --- a/board/armltd/vexpress/Makefile +++ b/board/armltd/vexpress/Makefile @@ -6,3 +6,4 @@ # obj-y := vexpress_common.o +obj-$(CONFIG_TARGET_VEXPRESS_CA15_TC2) += vexpress_tc2.o diff --git a/board/armltd/vexpress/vexpress_tc2.c b/board/armltd/vexpress/vexpress_tc2.c new file mode 100644 index 00000000000..ebb41a8833a --- /dev/null +++ b/board/armltd/vexpress/vexpress_tc2.c @@ -0,0 +1,33 @@ +/* + * (C) Copyright 2016 Linaro + * Jon Medhurst <tixy@linaro.org> + * + * TC2 specific code for Versatile Express. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/io.h> + +#define SCC_BASE 0x7fff0000 + +bool armv7_boot_nonsec_default(void) +{ +#ifdef CONFIG_ARMV7_BOOT_SEC_DEFAULT + return false +#else + /* + * The Serial Configuration Controller (SCC) register at address 0x700 + * contains flags for configuring the behaviour of the Boot Monitor + * (which CPUs execute from reset). Two of these bits are of interest: + * + * bit 12 = Use per-cpu mailboxes for power management + * bit 13 = Power down the non-boot cluster + * + * It is only when both of these are false that U-Boot's current + * implementation of 'nonsec' mode can work as expected because we + * rely on getting all CPUs to execute _nonsec_init, so let's check that. + */ + return (readl((u32 *)(SCC_BASE + 0x700)) & ((1 << 12) | (1 << 13))) == 0; +#endif +} diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index 973b57969f8..e34af6c4d93 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -31,13 +31,15 @@ U_BOOT_DEVICE(vexpress_serials) = { static struct mm_region vexpress64_mem_map[] = { { - .base = 0x0UL, + .virt = 0x0UL, + .phys = 0x0UL, .size = 0x80000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { - .base = 0x80000000UL, + .virt = 0x80000000UL, + .phys = 0x80000000UL, .size = 0xff80000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE diff --git a/board/cadence/xtfpga/Kconfig b/board/cadence/xtfpga/Kconfig new file mode 100644 index 00000000000..69296be49c7 --- /dev/null +++ b/board/cadence/xtfpga/Kconfig @@ -0,0 +1,39 @@ +if TARGET_XTFPGA + +choice + prompt "XTFPGA board type select" + +config XTFPGA_LX60 + bool "Support Avnet LX60" +config XTFPGA_LX110 + bool "Support Avnet LX110" +config XTFPGA_LX200 + bool "Support Avnet LX200" +config XTFPGA_ML605 + bool "Support Xilinx ML605" +config XTFPGA_KC705 + bool "Support Xilinx KC705" + +endchoice + +config SYS_BOARD + string + default "xtfpga" + +config SYS_VENDOR + string + default "cadence" + +config SYS_CONFIG_NAME + string + default "xtfpga" + +config BOARD_SDRAM_SIZE + hex + default 0x04000000 if XTFPGA_LX60 + default 0x03000000 if XTFPGA_LX110 + default 0x06000000 if XTFPGA_LX200 + default 0x18000000 if XTFPGA_ML605 + default 0x38000000 if XTFPGA_KC705 + +endif diff --git a/board/cadence/xtfpga/MAINTAINERS b/board/cadence/xtfpga/MAINTAINERS new file mode 100644 index 00000000000..f4a2b942d9e --- /dev/null +++ b/board/cadence/xtfpga/MAINTAINERS @@ -0,0 +1,7 @@ +XTFPGA BOARD +M: Max Filippov <jcmvbkbc@gmail.com> +S: Maintained +F: board/cadence/xtfpga/ +F: include/configs/xtfpga.h +F: configs/xtfpga_defconfig +F: drivers/sysreset/sysreset_xtfpga.c diff --git a/board/cadence/xtfpga/Makefile b/board/cadence/xtfpga/Makefile new file mode 100644 index 00000000000..fd8f720d68f --- /dev/null +++ b/board/cadence/xtfpga/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2007 - 2013, Tensilica Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ${BOARD}.o diff --git a/board/cadence/xtfpga/README b/board/cadence/xtfpga/README new file mode 100644 index 00000000000..5f29e2592f5 --- /dev/null +++ b/board/cadence/xtfpga/README @@ -0,0 +1,125 @@ + Tensilica 'xtfpga' Evaluation Boards + ==================================== + +Tensilica's 'xtfpga' evaluation boards are actually a set of different +boards that share configurations. The following is a list of supported +hardware by this board type: + +- XT-AV60 / LX60 +- XT-AV110 / LX110 +- XT-AV200 / LX200 +- ML605 +- KC705 + +All boards provide the following common configurations: + +- An Xtensa or Diamond processor core. +- An on-chip-debug (OCD) JTAG interface. +- A 16550 compatible UART and serial port. +- An OpenCores Wishbone 10/100-base-T ethernet interface. +- A 32 char two line LCD display. (except for the LX200) + +LX60/LX110/LX200: + +- Virtex-4 (XC4VLX60 / XCV4LX200) / Virtext-5 (XC5VLX110) +- 128MB / 64MB (LX60) memory +- 16MB / 4MB (LX60) Linear Flash + +ML605 + +- Virtex-6 (XC6VLX240T) +- 512MB DDR3 memory +- 16MB Linear BPI Flash + +KC705 (Xilinx) + +- Kintex-7 XC7K325T FPGA +- 1GB DDR3 memory +- 128MB Linear BPI Flash + + +Setting up the Board +-------------------- + +The serial port defaults to 115200 baud, no parity and 1 stop bit. +A terminal emulator must be set accordingly to see the U-Boot prompt. + + +Board Configurations LX60/LX110/LX200/ML605/KC705 +------------------------------------------------- + +The LX60/LX110/LX200/ML605 contain an 8-way DIP switch that controls +the boot mapping and selects from a range of default ethernet MAC +addresses. + +Boot Mapping (DIP switch 8): + + DIP switch 8 maps the system ROM address space (in which the + reset vector resides) to either SRAM (off, 0, down) or Flash + (on, 1, up). This mapping is implemented in the FPGA bitstream + and cannot be disabled by software, therefore DIP switch 8 is no + available for application use. Note DIP switch 7 is reserved by + Tensilica for future possible hardware use. + + Mapping to SRAM allows U-Boot to be debugged with an OCD/JTAG + tool such as the Xtensa OCD Daemon connected via a suppored probe. + See the tools documentation for supported probes and how to + connect them. Be aware that the board has only 128 KB of SRAM, + therefore U-Boot must fit within this space to debug an image + intended for the Flash. This issues is discussed in a separate + section toward the end. + + Mapping to flash allows U-Boot to start on reset, provided it + has been programmed into the first two 64 KB sectors of the Flash. + + The Flash is always mapped at a device (memory mapped I/O) address + (the address is board specific and is expressed as CFG_FLASH_BASE). + The device address is used by U-Boot to program the flash, and may + be used to specify an application to run or U-Boot image to boot. + +Default MAC Address (DIP switches 1-6): + + When the board is first powered on, or after the environment has + been reinitialized, the ethernet MAC address receives a default + value whose least significant 6 bits come from DIP switches 1-6. + The default is 00:50:C2:13:6F:xx where xx ranges from 0..3F + according to the DIP switches, where "on"==1 and "off"==0, and + switch 1 is the least-significant bit. + + After initial startup, the MAC address is stored in the U-Boot + environment variable 'ethaddr'. The user may change this to any + other address with the "setenv" comamnd. After the environment + has been saved to Flash by the "saveenv" command, this will be + used and the DIP switches no longer consulted. DIP swithes 1-6 + may then be used for application purposes. + +The KC705 board contains 4-way DIP switch, way 1 is the boot mapping +switch and ways 2-4 control the low three bits of the MAC address. + + +Limitation of SDRAM Size for OCD Debugging on the LX60 +------------------------------------------------------ + +The XT-AV60 board has only 128 KB of SDRAM that can be mapped +to the system ROM address space for debugging a ROM image under +OCD/JTAG. This limits the useful size of U-Boot to 128 KB (0x20000) +or the first 2 sectors of the flash. + +This can pose a problem if all the sources are compiled with -O0 +for debugging. The code size is then too large, in which case it +would be necessary to temporarily alter the linker script to place +the load addresses (LMA) in the RAM (VMA) so that OCD loads U-Boot +directly there and does not unpack. In practice this is not really +necessary as long as only a limited set of sources need to be +debugged, because the image can still fit into the 128 KB SRAM. + +The recommended procedure for debugging is to first build U-Boot +with the default optimization level (-Os), and then touch and +rebuild incrementally with -O0 so that only the touched sources +are recompiled with -O0. To build with -O0, pass it in the KCFLAGS +variable to make. + +Because this problem is easy to fall into and difficult to debug +if one doesn't expect it, the linker script provides a link-time +check and fatal error message if the image size exceeds 128 KB. + diff --git a/board/cadence/xtfpga/xtfpga.c b/board/cadence/xtfpga/xtfpga.c new file mode 100644 index 00000000000..5899aa63629 --- /dev/null +++ b/board/cadence/xtfpga/xtfpga.c @@ -0,0 +1,115 @@ +/* + * (C) Copyright 2007 - 2013 Tensilica Inc. + * (C) Copyright 2014 - 2016 Cadence Design Systems Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <dm/platdata.h> +#include <dm/platform_data/net_ethoc.h> +#include <linux/ctype.h> +#include <linux/string.h> +#include <linux/stringify.h> +#include <asm/global_data.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Check board idendity. + * (Print information about the board to stdout.) + */ + + +#if defined(CONFIG_XTFPGA_LX60) +const char *board = "XT_AV60"; +const char *description = "Avnet Xilinx LX60 FPGA Evaluation Board / "; +#elif defined(CONFIG_XTFPGA_LX110) +const char *board = "XT_AV110"; +const char *description = "Avnet Xilinx Virtex-5 LX110 Evaluation Kit / "; +#elif defined(CONFIG_XTFPGA_LX200) +const char *board = "XT_AV200"; +const char *description = "Avnet Xilinx Virtex-4 LX200 Evaluation Kit / "; +#elif defined(CONFIG_XTFPGA_ML605) +const char *board = "XT_ML605"; +const char *description = "Xilinx Virtex-6 FPGA ML605 Evaluation Kit / "; +#elif defined(CONFIG_XTFPGA_KC705) +const char *board = "XT_KC705"; +const char *description = "Xilinx Kintex-7 FPGA KC705 Evaluation Kit / "; +#else +const char *board = "<unknown>"; +const char *description = ""; +#endif + +int checkboard(void) +{ + printf("Board: %s: %sTensilica bitstream\n", board, description); + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_memstart = PHYSADDR(CONFIG_SYS_SDRAM_BASE); + gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; +} + +int board_postclk_init(void) +{ + /* + * Obtain CPU clock frequency from board and cache in global + * data structure (Hz). Return 0 on success (OK to continue), + * else non-zero (hang). + */ + +#ifdef CONFIG_SYS_FPGAREG_FREQ + gd->cpu_clk = (*(volatile unsigned long *)CONFIG_SYS_FPGAREG_FREQ); +#else + /* early Tensilica bitstreams lack this reg, but most run at 50 MHz */ + gd->cpu_clk = 50000000UL; +#endif + return 0; +} + +/* + * Miscellaneous late initializations. + * The environment has been set up, so we can set the Ethernet address. + */ + +int misc_init_r(void) +{ +#ifdef CONFIG_CMD_NET + /* + * Initialize ethernet environment variables and board info. + * Default MAC address comes from CONFIG_ETHADDR + DIP switches 1-6. + */ + + char *s = getenv("ethaddr"); + if (s == 0) { + unsigned int x; + char s[] = __stringify(CONFIG_ETHBASE); + x = (*(volatile u32 *)CONFIG_SYS_FPGAREG_DIPSW) + & FPGAREG_MAC_MASK; + sprintf(&s[15], "%02x", x); + setenv("ethaddr", s); + } +#endif /* CONFIG_CMD_NET */ + + return 0; +} + +U_BOOT_DEVICE(sysreset) = { + .name = "xtfpga_sysreset", +}; + +static struct ethoc_eth_pdata ethoc_pdata = { + .eth_pdata = { + .iobase = CONFIG_SYS_ETHOC_BASE, + }, + .packet_base = CONFIG_SYS_ETHOC_BUFFER_ADDR, +}; + +U_BOOT_DEVICE(ethoc) = { + .name = "ethoc", + .platdata = ðoc_pdata, +}; diff --git a/board/cavium/thunderx/thunderx.c b/board/cavium/thunderx/thunderx.c index 9131a385fd0..960ca53b021 100644 --- a/board/cavium/thunderx/thunderx.c +++ b/board/cavium/thunderx/thunderx.c @@ -45,16 +45,19 @@ DECLARE_GLOBAL_DATA_PTR; static struct mm_region thunderx_mem_map[] = { { - .base = 0x000000000000UL, + .virt = 0x000000000000UL, + .phys = 0x000000000000UL, .size = 0x40000000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE, }, { - .base = 0x800000000000UL, + .virt = 0x800000000000UL, + .phys = 0x800000000000UL, .size = 0x40000000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE, }, { - .base = 0x840000000000UL, + .virt = 0x840000000000UL, + .phys = 0x840000000000UL, .size = 0x40000000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE, diff --git a/board/chipspark/popmetal_rk3288/Kconfig b/board/chipspark/popmetal_rk3288/Kconfig new file mode 100644 index 00000000000..a5f404306a8 --- /dev/null +++ b/board/chipspark/popmetal_rk3288/Kconfig @@ -0,0 +1,15 @@ +if TARGET_POPMETAL_RK3288 + +config SYS_BOARD + default "popmetal_rk3288" + +config SYS_VENDOR + default "chipspark" + +config SYS_CONFIG_NAME + default "popmetal_rk3288" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/chipspark/popmetal_rk3288/MAINTAINERS b/board/chipspark/popmetal_rk3288/MAINTAINERS new file mode 100644 index 00000000000..1a6a1bb2c61 --- /dev/null +++ b/board/chipspark/popmetal_rk3288/MAINTAINERS @@ -0,0 +1,6 @@ +POPMETAL-RK3288 +M: Lin Huang <hl@rock-chips.com> +S: Maintained +F: board/chipspark/popmetal_rk3288 +F: include/configs/popmetal_rk3288.h +F: configs/popmetal-rk3288_defconfig diff --git a/board/chipspark/popmetal_rk3288/Makefile b/board/chipspark/popmetal_rk3288/Makefile new file mode 100644 index 00000000000..86d66b0bfe4 --- /dev/null +++ b/board/chipspark/popmetal_rk3288/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2016 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += popmetal-rk3288.o diff --git a/board/chipspark/popmetal_rk3288/popmetal-rk3288.c b/board/chipspark/popmetal_rk3288/popmetal-rk3288.c new file mode 100644 index 00000000000..aad74ef1095 --- /dev/null +++ b/board/chipspark/popmetal_rk3288/popmetal-rk3288.c @@ -0,0 +1,15 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spl.h> + +void board_boot_order(u32 *spl_boot_list) +{ + /* eMMC prior to sdcard */ + spl_boot_list[0] = BOOT_DEVICE_MMC2; + spl_boot_list[1] = BOOT_DEVICE_MMC1; +} diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c index a21e7b00e1f..566c19b4c99 100644 --- a/board/compulab/cm_fx6/cm_fx6.c +++ b/board/compulab/cm_fx6/cm_fx6.c @@ -12,6 +12,7 @@ #include <dm.h> #include <fsl_esdhc.h> #include <miiphy.h> +#include <mtd_node.h> #include <netdev.h> #include <errno.h> #include <usb.h> @@ -28,6 +29,7 @@ #include <asm/io.h> #include <asm/gpio.h> #include <dm/platform_data/serial_mxc.h> +#include <jffs2/load_kernel.h> #include "common.h" #include "../common/eeprom.h" #include "../common/common.h" @@ -581,6 +583,17 @@ int cm_fx6_setup_ecspi(void) { return 0; } #ifdef CONFIG_OF_BOARD_SETUP #define USDHC3_PATH "/soc/aips-bus@02100000/usdhc@02198000/" + +struct node_info nodes[] = { + /* + * Both entries target the same flash chip. The st,m25p compatible + * is used in the vendor device trees, while upstream uses (the + * documented) jedec,spi-nor comptatible. + */ + { "st,m25p", MTD_DEV_TYPE_NOR, }, + { "jedec,spi-nor", MTD_DEV_TYPE_NOR, }, +}; + int ft_board_setup(void *blob, bd_t *bd) { u32 baseboard_rev; @@ -589,6 +602,8 @@ int ft_board_setup(void *blob, bd_t *bd) char baseboard_name[16]; int err; + fdt_shrink_to_minimum(blob); /* Make room for new properties */ + /* MAC addr */ if (eth_getenv_enetaddr("ethaddr", enetaddr)) { fdt_find_and_setprop(blob, @@ -607,15 +622,16 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; /* Assume not an early revision SB-FX6m baseboard */ if (!strncmp("SB-FX6m", baseboard_name, 7) && baseboard_rev <= 120) { - fdt_shrink_to_minimum(blob); /* Make room for new properties */ nodeoffset = fdt_path_offset(blob, USDHC3_PATH); fdt_delprop(blob, nodeoffset, "cd-gpios"); - fdt_find_and_setprop(blob, USDHC3_PATH, "non-removable", + fdt_find_and_setprop(blob, USDHC3_PATH, "broken-cd", NULL, 0, 1); fdt_find_and_setprop(blob, USDHC3_PATH, "keep-power-in-suspend", NULL, 0, 1); } + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); + return 0; } #endif diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c index 225de7c543f..3fbd3d2aaaa 100644 --- a/board/congatec/cgtqmx6eval/cgtqmx6eval.c +++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c @@ -678,14 +678,6 @@ int overwrite_console(void) return 1; } -static bool is_mx6q(void) -{ - if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) - return true; - else - return false; -} - int board_early_init_f(void) { setup_iomux_uart(); @@ -703,7 +695,7 @@ int board_init(void) gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; - if (is_mx6q()) + if (is_mx6dq()) setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1); else setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1); @@ -760,7 +752,7 @@ int misc_init_r(void) int board_late_init(void) { #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - if (is_mx6q()) + if (is_mx6dq()) setenv("board_rev", "MX6Q"); else setenv("board_rev", "MX6DL"); @@ -1053,7 +1045,7 @@ static void spl_dram_init(int width) return; } - if (is_mx6q()) { + if (is_mx6dq()) { mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs); mx6_dram_cfg(&sysinfo, &mx6q_mmcd_calib, &mem_ddr_2g); } else if (is_cpu_type(MXC_CPU_MX6SOLO)) { diff --git a/board/congatec/conga-qeval20-qa3-e3845/MAINTAINERS b/board/congatec/conga-qeval20-qa3-e3845/MAINTAINERS index 5a4d4dcdd38..3d7e8e2d619 100644 --- a/board/congatec/conga-qeval20-qa3-e3845/MAINTAINERS +++ b/board/congatec/conga-qeval20-qa3-e3845/MAINTAINERS @@ -4,4 +4,5 @@ S: Maintained F: board/congatec/conga-qeval20-qa3-e3845 F: include/configs/conga-qeval20-qa3-e3845.h F: configs/conga-qeval20-qa3-e3845_defconfig +F: configs/conga-qeval20-qa3-e3845-internal-uart_defconfig F: arch/x86/dts/conga-qeval20-qa3-e3845.dts diff --git a/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c b/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c index 6a946d57585..7a5b7659ef6 100644 --- a/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c +++ b/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c @@ -5,6 +5,7 @@ */ #include <common.h> +#include <i2c.h> #include <winbond_w83627.h> #include <asm/gpio.h> #include <asm/ibmpc.h> @@ -12,6 +13,7 @@ int board_early_init_f(void) { +#ifndef CONFIG_INTERNAL_UART /* * The FSP enables the BayTrail internal legacy UART (again). * Disable it again, so that the Winbond one can be used. @@ -21,6 +23,7 @@ int board_early_init_f(void) /* Enable the legacy UART in the Winbond W83627 Super IO chip */ winbond_enable_serial(PNP_DEV(WINBOND_IO_PORT, W83627DHG_SP1), UART0_BASE, UART0_IRQ); +#endif return 0; } @@ -29,3 +32,42 @@ int arch_early_init_r(void) { return 0; } + +int board_late_init(void) +{ + struct udevice *dev; + u8 buf[8]; + int ret; + + /* Configure SMSC USB2513 USB Hub: 7bit address 0x2c */ + ret = i2c_get_chip_for_busnum(0, 0x2c, 1, &dev); + if (ret) { + printf("Cannot find USB2513: %d\n", ret); + return 0; + } + + /* + * The first access to the USB Hub fails sometimes, so lets read + * a dummy byte to be sure here + */ + dm_i2c_read(dev, 0x00, buf, 1); + + /* + * The SMSC hub is not visible on the I2C bus after the first + * configuration at power-up. The following code deliberately + * does not report upon failure of these I2C write calls. + */ + buf[0] = 0x93; + dm_i2c_write(dev, 0x06, buf, 1); + + buf[0] = 0xaa; + dm_i2c_write(dev, 0xf8, buf, 1); + + buf[0] = 0x0f; + dm_i2c_write(dev, 0xfa, buf, 1); + + buf[0] = 0x01; + dm_i2c_write(dev, 0xff, buf, 1); + + return 0; +} diff --git a/board/dfi/Kconfig b/board/dfi/Kconfig new file mode 100644 index 00000000000..25d0a11ce15 --- /dev/null +++ b/board/dfi/Kconfig @@ -0,0 +1,29 @@ +# +# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +if VENDOR_DFI + +choice + prompt "Mainboard model" + optional + +config TARGET_DFI_BT700 + bool "DFI BT700 BayTrail" + help + This is the DFI Q7X-151 baseboard equipped with the + DFI BayTrail Bt700 SoM. It contains an Atom E3845 with + Ethernet (in non-PCIe-x4 configuration), micro-SD, USB 2, + USB 3, SATA, serial console and DisplayPort video out. + It requires some binary blobs - see README.x86 for details. + + Note that PCIE_ECAM_BASE is set up by the FSP so the value used + by U-Boot matches that value. + +endchoice + +source "board/dfi/dfi-bt700/Kconfig" + +endif diff --git a/board/dfi/dfi-bt700/Kconfig b/board/dfi/dfi-bt700/Kconfig new file mode 100644 index 00000000000..3f0acb39f7d --- /dev/null +++ b/board/dfi/dfi-bt700/Kconfig @@ -0,0 +1,28 @@ +if TARGET_DFI_BT700 + +config SYS_BOARD + default "dfi-bt700" + +config SYS_VENDOR + default "dfi" + +config SYS_SOC + default "baytrail" + +config SYS_CONFIG_NAME + default "dfi-bt700" + +config SYS_TEXT_BASE + default 0xfff00000 if !EFI_STUB + default 0x01110000 if EFI_STUB + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select X86_RESET_VECTOR if !EFI_STUB + select INTEL_BAYTRAIL + select BOARD_ROMSIZE_KB_8192 + +config PCIE_ECAM_BASE + default 0xe0000000 + +endif diff --git a/board/dfi/dfi-bt700/MAINTAINERS b/board/dfi/dfi-bt700/MAINTAINERS new file mode 100644 index 00000000000..6639787814e --- /dev/null +++ b/board/dfi/dfi-bt700/MAINTAINERS @@ -0,0 +1,10 @@ +congatec DFI-BT700 +M: Stefan Roese <sr@denx.de> +S: Maintained +F: board/dfi/dfi-bt700 +F: include/configs/dfi-bt700.h +F: configs/dfi-bt700-q7x-151_defconfig +F: configs/theadorable-x86-dfi-bt700_defconfig +F: arch/x86/dts/dfi-bt700.dtsi +F: arch/x86/dts/dfi-bt700-q7x-151.dts +F: arch/x86/dts/theadorable-x86-dfi-bt700.dts diff --git a/board/dfi/dfi-bt700/Makefile b/board/dfi/dfi-bt700/Makefile new file mode 100644 index 00000000000..8052f5e02fd --- /dev/null +++ b/board/dfi/dfi-bt700/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2015, Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += dfi-bt700.o start.o +obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o diff --git a/board/dfi/dfi-bt700/acpi/mainboard.asl b/board/dfi/dfi-bt700/acpi/mainboard.asl new file mode 100644 index 00000000000..544a04915e1 --- /dev/null +++ b/board/dfi/dfi-bt700/acpi/mainboard.asl @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Power Button */ +Device (PWRB) +{ + Name(_HID, EISAID("PNP0C0C")) +} + +/* TODO: Need add Nuvoton SuperIO chipset NCT6102D ASL codes */ diff --git a/board/dfi/dfi-bt700/dfi-bt700.c b/board/dfi/dfi-bt700/dfi-bt700.c new file mode 100644 index 00000000000..8645bdc795b --- /dev/null +++ b/board/dfi/dfi-bt700/dfi-bt700.c @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2016 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <nuvoton_nct6102d.h> +#include <asm/gpio.h> +#include <asm/ibmpc.h> +#include <asm/pnp_def.h> + +int board_early_init_f(void) +{ +#ifdef CONFIG_INTERNAL_UART + /* Disable the legacy UART which is enabled per default */ + nct6102d_uarta_disable(); +#else + /* + * The FSP enables the BayTrail internal legacy UART (again). + * Disable it again, so that the Nuvoton one can be used. + */ + setup_internal_uart(0); +#endif + + /* Disable the watchdog which is enabled per default */ + nct6102d_wdt_disable(); + + return 0; +} diff --git a/board/dfi/dfi-bt700/dsdt.asl b/board/dfi/dfi-bt700/dsdt.asl new file mode 100644 index 00000000000..6042011acf3 --- /dev/null +++ b/board/dfi/dfi-bt700/dsdt.asl @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000) +{ + /* platform specific */ + #include <asm/arch/acpi/platform.asl> + + /* board specific */ + #include "acpi/mainboard.asl" +} diff --git a/board/dfi/dfi-bt700/start.S b/board/dfi/dfi-bt700/start.S new file mode 100644 index 00000000000..2c941a4a510 --- /dev/null +++ b/board/dfi/dfi-bt700/start.S @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2015, Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +.globl early_board_init +early_board_init: + jmp early_board_init_ret diff --git a/board/el/el6x/Kconfig b/board/el/el6x/Kconfig new file mode 100644 index 00000000000..aa9bf25fb47 --- /dev/null +++ b/board/el/el6x/Kconfig @@ -0,0 +1,25 @@ +if TARGET_ZC5202 + +config SYS_BOARD + default "el6x" + +config SYS_VENDOR + default "el" + +config SYS_CONFIG_NAME + default "zc5202" + +endif + +if TARGET_ZC5601 + +config SYS_BOARD + default "el6x" + +config SYS_VENDOR + default "el" + +config SYS_CONFIG_NAME + default "zc5601" + +endif diff --git a/board/el/el6x/MAINTAINERS b/board/el/el6x/MAINTAINERS new file mode 100644 index 00000000000..9a40010f50e --- /dev/null +++ b/board/el/el6x/MAINTAINERS @@ -0,0 +1,8 @@ +EL6X BOARD +M: Stefano Babic <sbabic@denx.de> +S: Maintained +F: board/el/el6x/ +F: include/configs/zc5202.h +F: include/configs/zc5601.h +F: configs/zc5202_defconfig +F: configs/zc5601_defconfig diff --git a/board/el/el6x/Makefile b/board/el/el6x/Makefile new file mode 100644 index 00000000000..48d5ad9440b --- /dev/null +++ b/board/el/el6x/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) Stefano Babic <sbabic@denx.de> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := el6x.o diff --git a/board/el/el6x/el6x.c b/board/el/el6x/el6x.c new file mode 100644 index 00000000000..3b0fb323bdd --- /dev/null +++ b/board/el/el6x/el6x.c @@ -0,0 +1,640 @@ +/* + * Copyright (C) Stefano Babic <sbabic@denx.de> + * + * Based on other i.MX6 boards + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <asm/errno.h> +#include <asm/gpio.h> +#include <asm/imx-common/mxc_i2c.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/boot_mode.h> +#include <asm/imx-common/video.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/arch/mxc_hdmi.h> +#include <asm/arch/crm_regs.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +#include <i2c.h> +#include <power/pmic.h> +#include <power/pfuze100_pmic.h> +#include <asm/arch/mx6-ddr.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define OPEN_PAD_CTRL (PAD_CTL_ODE | PAD_CTL_DSE_DISABLE | (0 << 12)) + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +#define I2C_PMIC 1 + +#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL) + +#define ETH_PHY_RESET IMX_GPIO_NR(2, 4) + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + + return 0; +} + +iomux_v3_cfg_t const uart2_pads[] = { + MX6_PAD_SD3_DAT5__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD3_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); +} + +#ifdef CONFIG_TARGET_ZC5202 +iomux_v3_cfg_t const enet_pads[] = { + MX6_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_KEY_COL2__ENET_RX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_KEY_COL0__ENET_RX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK), + MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_GPIO_19__ENET_TX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_KEY_ROW2__ENET_TX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_KEY_ROW0__ENET_TX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), + /* Switch Reset */ + MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD), + /* Switch Interrupt */ + MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* use CRS and COL pads as GPIOs */ + MX6_PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(OPEN_PAD_CTRL), + MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(OPEN_PAD_CTRL), + +}; + +#define BOARD_NAME "EL6x-ZC5202" +#else +iomux_v3_cfg_t const enet_pads[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK), + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; +#define BOARD_NAME "EL6x-ZC5601" +#endif + +static void setup_iomux_enet(void) +{ + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); + +#ifdef CONFIG_TARGET_ZC5202 + /* set CRS and COL to input */ + gpio_direction_input(IMX_GPIO_NR(4, 9)); + gpio_direction_input(IMX_GPIO_NR(4, 12)); + + /* Reset Switch */ + gpio_direction_output(ETH_PHY_RESET , 0); + mdelay(2); + gpio_set_value(ETH_PHY_RESET, 1); +#endif +} + +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +#ifdef CONFIG_MXC_SPI +#ifdef CONFIG_TARGET_ZC5202 +iomux_v3_cfg_t const ecspi1_pads[] = { + MX6_PAD_DISP0_DAT20__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_DISP0_DAT21__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_DISP0_DAT22__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_DISP0_DAT15__GPIO5_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +iomux_v3_cfg_t const ecspi3_pads[] = { + MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_DISP0_DAT7__GPIO4_IO28 | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_DISP0_DAT8__GPIO4_IO29 | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_DISP0_DAT9__GPIO4_IO30 | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_DISP0_DAT10__GPIO4_IO31 | MUX_PAD_CTRL(SPI_PAD_CTRL), +}; +#endif + +iomux_v3_cfg_t const ecspi4_pads[] = { + MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS) + ? (IMX_GPIO_NR(3, 20)) : -1; +} + +static void setup_spi(void) +{ +#ifdef CONFIG_TARGET_ZC5202 + gpio_request(IMX_GPIO_NR(5, 17), "spi_cs0"); + gpio_request(IMX_GPIO_NR(5, 9), "spi_cs1"); + gpio_direction_output(IMX_GPIO_NR(5, 17), 1); + gpio_direction_output(IMX_GPIO_NR(5, 9), 1); + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); +#endif + + gpio_request(IMX_GPIO_NR(3, 20), "spi4_cs0"); + gpio_direction_output(IMX_GPIO_NR(3, 20), 1); + imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads)); + + enable_spi_clk(true, 3); +} +#endif + +static struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | I2C_PAD, + .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | I2C_PAD, + .gp = IMX_GPIO_NR(2, 30) + }, + .sda = { + .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD, + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD, + .gp = IMX_GPIO_NR(4, 13) + } +}; + +static struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | I2C_PAD, + .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | I2C_PAD, + .gp = IMX_GPIO_NR(1, 5) + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | I2C_PAD, + .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | I2C_PAD, + .gp = IMX_GPIO_NR(7, 11) + } +}; + +iomux_v3_cfg_t const usdhc2_pads[] = { + MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_GPIO_4__SD2_CD_B | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +}; + +iomux_v3_cfg_t const usdhc4_pads[] = { + MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC2_BASE_ADDR}, + {USDHC4_BASE_ADDR}, +}; + +#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + break; + case USDHC4_BASE_ADDR: + ret = 1; /* eMMC/uSDHC4 is always present */ + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ +#ifndef CONFIG_SPL_BUILD + int ret; + int i; + + /* + * According to the board_mmc_init() the following map is done: + * (U-boot device node) (Physical Port) + * mmc0 SD2 + * mmc1 SD3 + * mmc2 eMMC + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + gpio_direction_input(USDHC2_CD_GPIO); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + break; + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) then supported by the board (%d)\n", + i + 1, CONFIG_SYS_FSL_USDHC_NUM); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; +#else + struct src *psrc = (struct src *)SRC_BASE_ADDR; + unsigned reg = readl(&psrc->sbmr1) >> 11; + + /* + * Upon reading BOOT_CFG register the following map is done: + * Bit 11 and 12 of BOOT_CFG register can determine the current + * mmc port + * 0x1 SD1 + * 0x2 SD2 + * 0x3 SD4 + */ + + switch (reg & 0x3) { + case 0x1: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + break; + case 0x3: + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + break; + } + + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +#endif + +} +#endif + + +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + +int board_eth_init(bd_t *bis) +{ + setup_iomux_enet(); + enable_enet_clk(1); + + return cpu_eth_init(bis); +} + +int board_early_init_f(void) +{ + + setup_iomux_uart(); + setup_spi(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); + + return 0; +} + +int power_init_board(void) +{ + struct pmic *p; + int ret; + unsigned int reg; + + ret = power_pfuze100_init(I2C_PMIC); + if (ret) + return ret; + + p = pmic_get("PFUZE100"); + ret = pmic_probe(p); + if (ret) + return ret; + + pmic_reg_read(p, PFUZE100_DEVICEID, ®); + printf("PMIC: PFUZE100 ID=0x%02x\n", reg); + + /* Increase VGEN3 from 2.5 to 2.8V */ + pmic_reg_read(p, PFUZE100_VGEN3VOL, ®); + reg &= ~LDO_VOL_MASK; + reg |= LDOB_2_80V; + pmic_reg_write(p, PFUZE100_VGEN3VOL, reg); + + /* Increase VGEN5 from 2.8 to 3V */ + pmic_reg_read(p, PFUZE100_VGEN5VOL, ®); + reg &= ~LDO_VOL_MASK; + reg |= LDOB_3_00V; + pmic_reg_write(p, PFUZE100_VGEN5VOL, reg); + + /* Set SW1AB stanby volage to 0.975V */ + pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®); + reg &= ~SW1x_STBY_MASK; + reg |= SW1x_0_975V; + pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg); + + /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */ + pmic_reg_read(p, PFUZE100_SW1ABCONF, ®); + reg &= ~SW1xCONF_DVSSPEED_MASK; + reg |= SW1xCONF_DVSSPEED_4US; + pmic_reg_write(p, PFUZE100_SW1ABCONF, reg); + + /* Set SW1C standby voltage to 0.975V */ + pmic_reg_read(p, PFUZE100_SW1CSTBY, ®); + reg &= ~SW1x_STBY_MASK; + reg |= SW1x_0_975V; + pmic_reg_write(p, PFUZE100_SW1CSTBY, reg); + + /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */ + pmic_reg_read(p, PFUZE100_SW1CCONF, ®); + reg &= ~SW1xCONF_DVSSPEED_MASK; + reg |= SW1xCONF_DVSSPEED_4US; + pmic_reg_write(p, PFUZE100_SW1CCONF, reg); + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, + /* 8 bit bus width */ + {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + + setenv("board_name", BOARD_NAME); + return 0; +} + +int checkboard(void) +{ + puts("Board: "); + puts(BOARD_NAME "\n"); + + return 0; +} + +#ifdef CONFIG_SPL_BUILD +#include <spl.h> +#include <libfdt.h> + +const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_sdclk_0 = 0x00020030, + .dram_sdclk_1 = 0x00020030, + .dram_cas = 0x00020030, + .dram_ras = 0x00020030, + .dram_reset = 0x00020030, + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + .dram_sdba2 = 0x00000000, + .dram_sdodt0 = 0x00003030, + .dram_sdodt1 = 0x00003030, + .dram_sdqs0 = 0x00000030, + .dram_sdqs1 = 0x00000030, + .dram_sdqs2 = 0x00000030, + .dram_sdqs3 = 0x00000030, + .dram_sdqs4 = 0x00000030, + .dram_sdqs5 = 0x00000030, + .dram_sdqs6 = 0x00000030, + .dram_sdqs7 = 0x00000030, + .dram_dqm0 = 0x00020030, + .dram_dqm1 = 0x00020030, + .dram_dqm2 = 0x00020030, + .dram_dqm3 = 0x00020030, + .dram_dqm4 = 0x00020030, + .dram_dqm5 = 0x00020030, + .dram_dqm6 = 0x00020030, + .dram_dqm7 = 0x00020030, +}; + +const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = { + .grp_ddr_type = 0x000C0000, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, + .grp_addds = 0x00000030, + .grp_ctlds = 0x00000030, + .grp_ddrmode = 0x00020000, + .grp_b0ds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_b2ds = 0x00000030, + .grp_b3ds = 0x00000030, + .grp_b4ds = 0x00000030, + .grp_b5ds = 0x00000030, + .grp_b6ds = 0x00000030, + .grp_b7ds = 0x00000030, +}; + +const struct mx6_mmdc_calibration mx6_mmcd_calib = { + .p0_mpwldectrl0 = 0x001F001F, + .p0_mpwldectrl1 = 0x001F001F, + .p1_mpwldectrl0 = 0x00440044, + .p1_mpwldectrl1 = 0x00440044, + .p0_mpdgctrl0 = 0x434B0350, + .p0_mpdgctrl1 = 0x034C0359, + .p1_mpdgctrl0 = 0x434B0350, + .p1_mpdgctrl1 = 0x03650348, + .p0_mprddlctl = 0x4436383B, + .p1_mprddlctl = 0x39393341, + .p0_mpwrdlctl = 0x35373933, + .p1_mpwrdlctl = 0x48254A36, +}; + +/* MT41K128M16JT-125 */ +static struct mx6_ddr3_cfg mem_ddr = { + .mem_speed = 1600, + .density = 2, + .width = 16, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0x00C03F3F, &ccm->CCGR0); + writel(0x0030FC03, &ccm->CCGR1); + writel(0x0FFFC000, &ccm->CCGR2); + writel(0x3FF00000, &ccm->CCGR3); + writel(0x00FFF300, &ccm->CCGR4); + writel(0x0F0000C3, &ccm->CCGR5); + writel(0x000003FF, &ccm->CCGR6); +} + +static void gpr_init(void) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* enable AXI cache for VDOA/VPU/IPU */ + writel(0xF00000CF, &iomux->gpr[4]); + /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ + writel(0x007F007F, &iomux->gpr[6]); + writel(0x007F007F, &iomux->gpr[7]); +} + +/* + * This section requires the differentiation between iMX6 Sabre boards, but + * for now, it will configure only for the mx6q variant. + */ +static void spl_dram_init(void) +{ + struct mx6_ddr_sysinfo sysinfo = { + /* width of data bus:0=16,1=32,2=64 */ + .dsize = 2, + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, /* 32Gb per CS */ + /* single chip select */ + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ + .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .ddr_type = DDR_TYPE_DDR3, + }; + + mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs); + mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); +} + +void board_init_f(ulong dummy) +{ + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + ccgr_init(); + gpr_init(); + + /* iomux and setup of i2c */ + board_early_init_f(); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} + +#endif diff --git a/board/evb_rk3036/evb_rk3036/evb_rk3036.c b/board/evb_rk3036/evb_rk3036/evb_rk3036.c deleted file mode 100644 index f5758b1e9a7..00000000000 --- a/board/evb_rk3036/evb_rk3036/evb_rk3036.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * (C) Copyright 2015 Rockchip Electronics Co., Ltd - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <dm.h> -#include <asm/io.h> -#include <asm/arch/uart.h> -#include <asm/arch/sdram_rk3036.h> - -DECLARE_GLOBAL_DATA_PTR; - -void get_ddr_config(struct rk3036_ddr_config *config) -{ - /* K4B4G1646Q config */ - config->ddr_type = 3; - config->rank = 2; - config->cs0_row = 15; - config->cs1_row = 15; - - /* 8bank */ - config->bank = 3; - config->col = 10; - - /* 16bit bw */ - config->bw = 1; -} - -int board_init(void) -{ - return 0; -} - -int dram_init(void) -{ - gd->ram_size = sdram_size(); - - return 0; -} - -#ifndef CONFIG_SYS_DCACHE_OFF -void enable_caches(void) -{ - /* Enable D-cache. I-cache is already enabled in start.S */ - dcache_enable(); -} -#endif diff --git a/board/freescale/b4860qds/MAINTAINERS b/board/freescale/b4860qds/MAINTAINERS index ac02bb7e481..97304c53254 100644 --- a/board/freescale/b4860qds/MAINTAINERS +++ b/board/freescale/b4860qds/MAINTAINERS @@ -12,6 +12,6 @@ F: configs/B4860QDS_SPIFLASH_defconfig F: configs/B4860QDS_SRIO_PCIE_BOOT_defconfig B4860QDS_SECURE_BOOT BOARD -M: Aneesh Bansal <aneesh.bansal@freescale.com> +M: Ruchika Gupta <ruchika.gupta@nxp.com> S: Maintained F: configs/B4860QDS_SECURE_BOOT_defconfig diff --git a/board/freescale/bsc9132qds/MAINTAINERS b/board/freescale/bsc9132qds/MAINTAINERS index 3de62d3f46e..c58fc503497 100644 --- a/board/freescale/bsc9132qds/MAINTAINERS +++ b/board/freescale/bsc9132qds/MAINTAINERS @@ -13,7 +13,7 @@ F: configs/BSC9132QDS_SPIFLASH_DDRCLK100_defconfig F: configs/BSC9132QDS_SPIFLASH_DDRCLK133_defconfig BSC9132QDS_NAND_DDRCLK100_SECURE BOARD -M: Aneesh Bansal <aneesh.bansal@freescale.com> +M: Ruchika Gupta <ruchika.gupta@nxp.com> S: Maintained F: configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig F: configs/BSC9132QDS_NAND_DDRCLK133_SECURE_defconfig diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c index ecfcc8253a8..dea231b866f 100644 --- a/board/freescale/common/fsl_chain_of_trust.c +++ b/board/freescale/common/fsl_chain_of_trust.c @@ -6,7 +6,21 @@ #include <common.h> #include <fsl_validate.h> +#include <fsl_secboot_err.h> #include <fsl_sfp.h> +#include <dm/root.h> + +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_FRAMEWORK) +#include <spl.h> +#endif + +#ifdef CONFIG_ADDR_MAP +#include <asm/mmu.h> +#endif + +#ifdef CONFIG_FSL_CORENET +#include <asm/fsl_pamu.h> +#endif #ifdef CONFIG_LS102XA #include <asm/arch/immap_ls102xa.h> @@ -52,6 +66,7 @@ int fsl_check_boot_mode_secure(void) return 0; } +#ifndef CONFIG_SPL_BUILD int fsl_setenv_chain_of_trust(void) { /* Check Boot Mode @@ -68,3 +83,76 @@ int fsl_setenv_chain_of_trust(void) setenv("bootcmd", CONFIG_CHAIN_BOOT_CMD); return 0; } +#endif + +#ifdef CONFIG_SPL_BUILD +void spl_validate_uboot(uint32_t hdr_addr, uintptr_t img_addr) +{ + int res; + + /* + * Check Boot Mode + * If Boot Mode is Non-Secure, skip validation + */ + if (fsl_check_boot_mode_secure() == 0) + return; + + printf("SPL: Validating U-Boot image\n"); + +#ifdef CONFIG_ADDR_MAP + init_addr_map(); +#endif + +#ifdef CONFIG_FSL_CORENET + if (pamu_init() < 0) + fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT); +#endif + +#ifdef CONFIG_FSL_CAAM + if (sec_init() < 0) + fsl_secboot_handle_error(ERROR_ESBC_SEC_INIT); +#endif + +/* + * dm_init_and_scan() is called as part of common SPL framework, so no + * need to call it again but in case of powerpc platforms which currently + * do not use common SPL framework, so need to call this function here. + */ +#if defined(CONFIG_SPL_DM) && (!defined(CONFIG_SPL_FRAMEWORK)) + dm_init_and_scan(true); +#endif + res = fsl_secboot_validate(hdr_addr, CONFIG_SPL_UBOOT_KEY_HASH, + &img_addr); + + if (res == 0) + printf("SPL: Validation of U-boot successful\n"); +} + +#ifdef CONFIG_SPL_FRAMEWORK +/* Override weak funtion defined in SPL framework to enable validation + * of main u-boot image before jumping to u-boot image. + */ +void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +{ + typedef void __noreturn (*image_entry_noargs_t)(void); + uint32_t hdr_addr; + + image_entry_noargs_t image_entry = + (image_entry_noargs_t)(unsigned long)spl_image->entry_point; + + hdr_addr = (spl_image->entry_point + spl_image->size - + CONFIG_U_BOOT_HDR_SIZE); + spl_validate_uboot(hdr_addr, (uintptr_t)spl_image->entry_point); + /* + * In case of failure in validation, spl_validate_uboot would + * not return back in case of Production environment with ITS=1. + * Thus U-Boot will not start. + * In Development environment (ITS=0 and SB_EN=1), the function + * may return back in case of non-fatal failures. + */ + + debug("image entry point: 0x%X\n", spl_image->entry_point); + image_entry(); +} +#endif /* ifdef CONFIG_SPL_FRAMEWORK */ +#endif /* ifdef CONFIG_SPL_BUILD */ diff --git a/board/freescale/corenet_ds/MAINTAINERS b/board/freescale/corenet_ds/MAINTAINERS index 73b0553184e..708e812e8e1 100644 --- a/board/freescale/corenet_ds/MAINTAINERS +++ b/board/freescale/corenet_ds/MAINTAINERS @@ -30,7 +30,7 @@ F: configs/P5040DS_SPIFLASH_defconfig F: configs/P5040DS_SECURE_BOOT_defconfig CORENET_DS_SECURE_BOOT BOARD -M: Aneesh Bansal <aneesh.bansal@freescale.com> +M: Ruchika Gupta <ruchika.gupta@nxp.com> S: Maintained F: configs/P3041DS_NAND_SECURE_BOOT_defconfig F: configs/P5020DS_NAND_SECURE_BOOT_defconfig diff --git a/board/freescale/ls1021aqds/Makefile b/board/freescale/ls1021aqds/Makefile index ab0234412cb..f0390c129f8 100644 --- a/board/freescale/ls1021aqds/Makefile +++ b/board/freescale/ls1021aqds/Makefile @@ -8,3 +8,4 @@ obj-y += ls1021aqds.o obj-y += ddr.o obj-y += eth.o obj-$(CONFIG_FSL_DCU_FB) += dcu.o +obj-$(CONFIG_ARMV7_PSCI) += psci.o diff --git a/board/freescale/ls1021aqds/psci.S b/board/freescale/ls1021aqds/psci.S new file mode 100644 index 00000000000..598168c7b07 --- /dev/null +++ b/board/freescale/ls1021aqds/psci.S @@ -0,0 +1,33 @@ +/* + * Copyright 2016 NXP Semiconductor. + * Author: Wang Dongsheng <dongsheng.wang@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <linux/linkage.h> + +#include <asm/armv7.h> +#include <asm/psci.h> + + .pushsection ._secure.text, "ax" + + .arch_extension sec + + .align 5 + +.globl psci_system_off +psci_system_off: + @ Get QIXIS base address + movw r1, #(QIXIS_BASE & 0xffff) + movt r1, #(QIXIS_BASE >> 16) + + ldrb r2, [r1, #QIXIS_PWR_CTL] + orr r2, r2, #QIXIS_PWR_CTL_POWEROFF + strb r2, [r1, #QIXIS_PWR_CTL] + +1: wfi + b 1b + + .popsection diff --git a/board/freescale/ls1021atwr/MAINTAINERS b/board/freescale/ls1021atwr/MAINTAINERS index b997bb00ece..06d888f65ce 100644 --- a/board/freescale/ls1021atwr/MAINTAINERS +++ b/board/freescale/ls1021atwr/MAINTAINERS @@ -9,3 +9,7 @@ F: configs/ls1021atwr_nor_lpuart_defconfig F: configs/ls1021atwr_sdcard_ifc_defconfig F: configs/ls1021atwr_sdcard_qspi_defconfig F: configs/ls1021atwr_qspi_defconfig + +M: Sumit Garg <sumit.garg@nxp.com> +S: Maintained +F: configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig diff --git a/board/freescale/ls1021atwr/Makefile b/board/freescale/ls1021atwr/Makefile index 01296c04b29..5238b158d7c 100644 --- a/board/freescale/ls1021atwr/Makefile +++ b/board/freescale/ls1021atwr/Makefile @@ -6,3 +6,4 @@ obj-y += ls1021atwr.o obj-$(CONFIG_FSL_DCU_FB) += dcu.o +obj-$(CONFIG_ARMV7_PSCI) += psci.o diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index c69c9cba42e..77482a947bf 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -503,6 +503,13 @@ int board_init(void) return 0; } +#if defined(CONFIG_SPL_BUILD) +void spl_board_init(void) +{ + ls102xa_smmu_stream_id_init(); +} +#endif + #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { diff --git a/board/freescale/ls1021atwr/psci.S b/board/freescale/ls1021atwr/psci.S new file mode 100644 index 00000000000..bec73568d3c --- /dev/null +++ b/board/freescale/ls1021atwr/psci.S @@ -0,0 +1,25 @@ +/* + * Copyright 2016 NXP Semiconductor. + * Author: Wang Dongsheng <dongsheng.wang@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <linux/linkage.h> + +#include <asm/armv7.h> +#include <asm/psci.h> + + .pushsection ._secure.text, "ax" + + .arch_extension sec + + .align 5 + +.globl psci_system_off +psci_system_off: +1: wfi + b 1b + + .popsection diff --git a/board/freescale/ls1043aqds/MAINTAINERS b/board/freescale/ls1043aqds/MAINTAINERS index 65a0af19309..992c54c95fa 100644 --- a/board/freescale/ls1043aqds/MAINTAINERS +++ b/board/freescale/ls1043aqds/MAINTAINERS @@ -9,3 +9,4 @@ F: configs/ls1043aqds_nand_defconfig F: configs/ls1043aqds_sdcard_ifc_defconfig F: configs/ls1043aqds_sdcard_qspi_defconfig F: configs/ls1043aqds_qspi_defconfig +F: configs/ls1043aqds_lpuart_defconfig diff --git a/board/freescale/ls1043aqds/ddr.c b/board/freescale/ls1043aqds/ddr.c index 0fd835d74fb..d4540d0a9a0 100644 --- a/board/freescale/ls1043aqds/ddr.c +++ b/board/freescale/ls1043aqds/ddr.c @@ -128,7 +128,7 @@ phys_size_t initdram(int board_type) void dram_init_banksize(void) { /* - * gd->secure_ram tracks the location of secure memory. + * gd->arch.secure_ram tracks the location of secure memory. * It was set as if the memory starts from 0. * The address needs to add the offset of its bank. */ @@ -139,16 +139,17 @@ void dram_init_banksize(void) gd->bd->bi_dram[1].size = gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE; #ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->secure_ram = gd->bd->bi_dram[1].start + - gd->secure_ram - - CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; + gd->arch.secure_ram = gd->bd->bi_dram[1].start + + gd->arch.secure_ram - + CONFIG_SYS_DDR_BLOCK1_SIZE; + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; #endif } else { gd->bd->bi_dram[0].size = gd->ram_size; #ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram; - gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; + gd->arch.secure_ram = gd->bd->bi_dram[0].start + + gd->arch.secure_ram; + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; #endif } } diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index b7e9c217277..941dfbc447e 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -327,6 +327,7 @@ int ft_board_setup(void *blob, bd_t *bd) { u64 base[CONFIG_NR_DRAM_BANKS]; u64 size[CONFIG_NR_DRAM_BANKS]; + u8 reg; /* fixup DT for the two DDR banks */ base[0] = gd->bd->bi_dram[0].start; @@ -341,6 +342,15 @@ int ft_board_setup(void *blob, bd_t *bd) fdt_fixup_fman_ethernet(blob); fdt_fixup_board_enet(blob); #endif + + reg = QIXIS_READ(brdcfg[0]); + reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; + + /* Disable IFC if QSPI is enabled */ + if (reg == 0xF) + do_fixup_by_compat(blob, "fsl,ifc", + "status", "disabled", 8 + 1, 1); + return 0; } #endif diff --git a/board/freescale/ls1043ardb/MAINTAINERS b/board/freescale/ls1043ardb/MAINTAINERS index 84ffb638d8e..0503a3fcc96 100644 --- a/board/freescale/ls1043ardb/MAINTAINERS +++ b/board/freescale/ls1043ardb/MAINTAINERS @@ -9,6 +9,6 @@ F: configs/ls1043ardb_nand_defconfig F: configs/ls1043ardb_sdcard_defconfig LS1043A_SECURE_BOOT BOARD -M: Aneesh Bansal <aneesh.bansal@freescale.com> +M: Ruchika Gupta <ruchika.gupta@nxp.com> S: Maintained F: configs/ls1043ardb_SECURE_BOOT_defconfig diff --git a/board/freescale/ls1043ardb/ddr.c b/board/freescale/ls1043ardb/ddr.c index 1e2fd2ed0c1..61b1cc4f30e 100644 --- a/board/freescale/ls1043ardb/ddr.c +++ b/board/freescale/ls1043ardb/ddr.c @@ -189,7 +189,7 @@ phys_size_t initdram(int board_type) void dram_init_banksize(void) { /* - * gd->secure_ram tracks the location of secure memory. + * gd->arch.secure_ram tracks the location of secure memory. * It was set as if the memory starts from 0. * The address needs to add the offset of its bank. */ @@ -200,16 +200,17 @@ void dram_init_banksize(void) gd->bd->bi_dram[1].size = gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE; #ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->secure_ram = gd->bd->bi_dram[1].start + - gd->secure_ram - - CONFIG_SYS_DDR_BLOCK1_SIZE; - gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; + gd->arch.secure_ram = gd->bd->bi_dram[1].start + + gd->arch.secure_ram - + CONFIG_SYS_DDR_BLOCK1_SIZE; + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; #endif } else { gd->bd->bi_dram[0].size = gd->ram_size; #ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram; - gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; + gd->arch.secure_ram = gd->bd->bi_dram[0].start + + gd->arch.secure_ram; + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; #endif } } diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index 14365207da1..d3e37b4996a 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -24,7 +24,9 @@ #ifdef CONFIG_U_QE #include <fsl_qe.h> #endif - +#ifdef CONFIG_FSL_LS_PPA +#include <asm/arch/ppa.h> +#endif DECLARE_GLOBAL_DATA_PTR; @@ -92,6 +94,10 @@ int board_init(void) enable_layerscape_ns_access(); #endif +#ifdef CONFIG_FSL_LS_PPA + ppa_init(); +#endif + #ifdef CONFIG_U_QE u_qe_init(); #endif diff --git a/board/freescale/ls2080a/ddr.c b/board/freescale/ls2080a/ddr.c index 1827ddca695..e6130ec7093 100644 --- a/board/freescale/ls2080a/ddr.c +++ b/board/freescale/ls2080a/ddr.c @@ -177,7 +177,7 @@ void dram_init_banksize(void) #endif /* - * gd->secure_ram tracks the location of secure memory. + * gd->arch.secure_ram tracks the location of secure memory. * It was set as if the memory starts from 0. * The address needs to add the offset of its bank. */ @@ -188,16 +188,17 @@ void dram_init_banksize(void) gd->bd->bi_dram[1].size = gd->ram_size - CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; #ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->secure_ram = gd->bd->bi_dram[1].start + - gd->secure_ram - - CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; - gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; + gd->arch.secure_ram = gd->bd->bi_dram[1].start + + gd->arch.secure_ram - + CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; #endif } else { gd->bd->bi_dram[0].size = gd->ram_size; #ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram; - gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; + gd->arch.secure_ram = gd->bd->bi_dram[0].start + + gd->arch.secure_ram; + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; #endif } diff --git a/board/freescale/ls2080aqds/MAINTAINERS b/board/freescale/ls2080aqds/MAINTAINERS index 076532622f4..8f78b67baae 100644 --- a/board/freescale/ls2080aqds/MAINTAINERS +++ b/board/freescale/ls2080aqds/MAINTAINERS @@ -6,6 +6,7 @@ F: board/freescale/ls2080a/ls2080aqds.c F: include/configs/ls2080aqds.h F: configs/ls2080aqds_defconfig F: configs/ls2080aqds_nand_defconfig +F: configs/ls2080aqds_qspi_defconfig LS2080A_SECURE_BOOT BOARD M: Saksham Jain <saksham.jain@nxp.freescale.com> diff --git a/board/freescale/ls2080aqds/ddr.c b/board/freescale/ls2080aqds/ddr.c index fcb03665bf9..9c6f477c7f4 100644 --- a/board/freescale/ls2080aqds/ddr.c +++ b/board/freescale/ls2080aqds/ddr.c @@ -177,7 +177,7 @@ void dram_init_banksize(void) #endif /* - * gd->secure_ram tracks the location of secure memory. + * gd->arch.secure_ram tracks the location of secure memory. * It was set as if the memory starts from 0. * The address needs to add the offset of its bank. */ @@ -188,16 +188,17 @@ void dram_init_banksize(void) gd->bd->bi_dram[1].size = gd->ram_size - CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; #ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->secure_ram = gd->bd->bi_dram[1].start + - gd->secure_ram - - CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; - gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; + gd->arch.secure_ram = gd->bd->bi_dram[1].start + + gd->arch.secure_ram - + CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; #endif } else { gd->bd->bi_dram[0].size = gd->ram_size; #ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram; - gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; + gd->arch.secure_ram = gd->bd->bi_dram[0].start + + gd->arch.secure_ram; + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; #endif } diff --git a/board/freescale/ls2080ardb/ddr.c b/board/freescale/ls2080ardb/ddr.c index a04d21be130..ecd1e71ad8f 100644 --- a/board/freescale/ls2080ardb/ddr.c +++ b/board/freescale/ls2080ardb/ddr.c @@ -177,7 +177,7 @@ void dram_init_banksize(void) #endif /* - * gd->secure_ram tracks the location of secure memory. + * gd->arch.secure_ram tracks the location of secure memory. * It was set as if the memory starts from 0. * The address needs to add the offset of its bank. */ @@ -188,16 +188,17 @@ void dram_init_banksize(void) gd->bd->bi_dram[1].size = gd->ram_size - CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; #ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->secure_ram = gd->bd->bi_dram[1].start + - gd->secure_ram - - CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; - gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; + gd->arch.secure_ram = gd->bd->bi_dram[1].start + + gd->arch.secure_ram - + CONFIG_SYS_LS2_DDR_BLOCK1_SIZE; + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; #endif } else { gd->bd->bi_dram[0].size = gd->ram_size; #ifdef CONFIG_SYS_MEM_RESERVE_SECURE - gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram; - gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; + gd->arch.secure_ram = gd->bd->bi_dram[0].start + + gd->arch.secure_ram; + gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED; #endif } diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index d63a979be58..a3ed4cd466c 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -64,7 +64,7 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + gd->ram_size = imx_ddr_size(); return 0; } diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c index 256d6029b4e..f978e5044e9 100644 --- a/board/freescale/mx6slevk/mx6slevk.c +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -61,7 +61,7 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + gd->ram_size = imx_ddr_size(); return 0; } diff --git a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c index 886373c901a..44e6a7d1411 100644 --- a/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c +++ b/board/freescale/mx6sxsabreauto/mx6sxsabreauto.c @@ -106,7 +106,7 @@ static int port_exp_direction_output(unsigned gpio, int value) int dram_init(void) { - gd->ram_size = PHYS_SDRAM_SIZE; + gd->ram_size = imx_ddr_size(); return 0; } diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index 25e009ee9bc..8d95c51aaf8 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -64,7 +64,7 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { - gd->ram_size = PHYS_SDRAM_SIZE; + gd->ram_size = imx_ddr_size(); return 0; } diff --git a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c index 92c92117cd9..66d679556b4 100644 --- a/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c +++ b/board/freescale/mx6ul_14x14_evk/mx6ul_14x14_evk.c @@ -60,9 +60,6 @@ DECLARE_GLOBAL_DATA_PTR; #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) -#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ - PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST) - #define IOX_SDI IMX_GPIO_NR(5, 10) #define IOX_STCP IMX_GPIO_NR(5, 7) #define IOX_SHCP IMX_GPIO_NR(5, 11) diff --git a/board/freescale/mx7dsabresd/MAINTAINERS b/board/freescale/mx7dsabresd/MAINTAINERS index b96642a568f..c7a22fc0d3e 100644 --- a/board/freescale/mx7dsabresd/MAINTAINERS +++ b/board/freescale/mx7dsabresd/MAINTAINERS @@ -4,3 +4,4 @@ S: Maintained F: board/freescale/mx7dsabresd F: include/configs/mx7dsabresd.h F: configs/mx7dsabresd_defconfig +F: configs/mx7dsabresd_secure_defconfig diff --git a/board/freescale/t1040qds/MAINTAINERS b/board/freescale/t1040qds/MAINTAINERS index 640538ff61c..fb3565a7fd1 100644 --- a/board/freescale/t1040qds/MAINTAINERS +++ b/board/freescale/t1040qds/MAINTAINERS @@ -7,6 +7,6 @@ F: configs/T1040QDS_defconfig F: configs/T1040QDS_DDR4_defconfig T1040QDS_SECURE_BOOT BOARD -M: Aneesh Bansal <aneesh.bansal@freescale.com> +M: Ruchika Gupta <ruchika.gupta@nxp.com> S: Maintained F: configs/T1040QDS_SECURE_BOOT_defconfig diff --git a/board/freescale/t104xrdb/MAINTAINERS b/board/freescale/t104xrdb/MAINTAINERS index 7597800252d..05789890f64 100644 --- a/board/freescale/t104xrdb/MAINTAINERS +++ b/board/freescale/t104xrdb/MAINTAINERS @@ -26,9 +26,13 @@ F: configs/T1042D4RDB_SDCARD_defconfig F: configs/T1042RDB_PI_SDCARD_defconfig T1040RDB_SECURE_BOOT BOARD -M: Aneesh Bansal <aneesh.bansal@freescale.com> +M: Ruchika Gupta <ruchika.gupta@nxp.com> S: Maintained F: configs/T1040RDB_SECURE_BOOT_defconfig F: configs/T1040D4RDB_SECURE_BOOT_defconfig F: configs/T1042RDB_SECURE_BOOT_defconfig F: configs/T1042D4RDB_SECURE_BOOT_defconfig + +M: Sumit Garg <sumit.garg@nxp.com> +S: Maintained +F: configs/T1042RDB_PI_NAND_SECURE_BOOT_defconfig diff --git a/board/freescale/t104xrdb/t104x_pbi_sb.cfg b/board/freescale/t104xrdb/t104x_pbi_sb.cfg new file mode 100644 index 00000000000..98dc8e4c240 --- /dev/null +++ b/board/freescale/t104xrdb/t104x_pbi_sb.cfg @@ -0,0 +1,38 @@ +#PBI commands +#Software Workaround for errata A-007662 to train PCIe2 controller in Gen2 speed +09250100 00000400 +09250108 00002000 +#Software Workaround for errata A-008007 to reset PVR register +09000010 0000000b +09000014 c0000000 +09000018 81d00017 +89020400 a1000000 +091380c0 000f0000 +89020400 00000000 +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +#Configure CPC1 as 256KB SRAM +09010100 00000000 +09010104 bffc0007 +09010f00 081e000d +09010000 80000000 +#Configure LAW for CPC1 +09000cd0 00000000 +09000cd4 bffc0000 +09000cd8 81000011 +#Configure alternate space +09000010 00000000 +09000014 bf000000 +09000018 81000000 +#Configure SPI controller +09110000 80000403 +09110020 2d170008 +09110024 00100008 +09110028 00100008 +0911002c 00100008 +#Flush PBL data +091380c0 000FFFFF +090e0200 bffd0000 +091380c0 000FFFFF diff --git a/board/freescale/t104xrdb/tlb.c b/board/freescale/t104xrdb/tlb.c index 95c15aa5965..7c0511e268b 100644 --- a/board/freescale/t104xrdb/tlb.c +++ b/board/freescale/t104xrdb/tlb.c @@ -28,7 +28,8 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB 1 */ /* *I*** - Covers boot page */ -#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) && \ + !defined(CONFIG_SECURE_BOOT) /* * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the * SRAM is at 0xfffc0000, it covered the 0xfffff000. @@ -36,6 +37,18 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 0, BOOKE_PAGESZ_256K, 1), + +#elif defined(CONFIG_SECURE_BOOT) && defined(CONFIG_SPL_BUILD) + /* + * *I*G - L3SRAM. When L3 is used as 256K SRAM, in case of Secure Boot + * the physical address of the SRAM is at 0xbffc0000, + * and virtual address is 0xfffc0000 + */ + + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_VADDR, + CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_256K, 1), #else SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, diff --git a/board/freescale/t208xqds/MAINTAINERS b/board/freescale/t208xqds/MAINTAINERS index d747de3f347..790b009c516 100644 --- a/board/freescale/t208xqds/MAINTAINERS +++ b/board/freescale/t208xqds/MAINTAINERS @@ -15,6 +15,6 @@ F: configs/T2081QDS_SPIFLASH_defconfig F: configs/T2081QDS_SRIO_PCIE_BOOT_defconfig T2080QDS_SECURE_BOOT BOARD -M: Aneesh Bansal <aneesh.bansal@freescale.com> +M: Ruchika Gupta <ruchika.gupta@nxp.com> S: Maintained F: configs/T2080QDS_SECURE_BOOT_defconfig diff --git a/board/freescale/t208xrdb/MAINTAINERS b/board/freescale/t208xrdb/MAINTAINERS index ccbfbab1426..f894f77b735 100644 --- a/board/freescale/t208xrdb/MAINTAINERS +++ b/board/freescale/t208xrdb/MAINTAINERS @@ -10,6 +10,6 @@ F: configs/T2080RDB_SPIFLASH_defconfig F: configs/T2080RDB_SRIO_PCIE_BOOT_defconfig T2080RDB_SECURE_BOOT BOARD -M: Aneesh Bansal <aneesh.bansal@freescale.com> +M: Ruchika Gupta <ruchika.gupta@nxp.com> S: Maintained F: configs/T2080RDB_SECURE_BOOT_defconfig diff --git a/board/freescale/t4qds/MAINTAINERS b/board/freescale/t4qds/MAINTAINERS index b1591136421..b288571c7a7 100644 --- a/board/freescale/t4qds/MAINTAINERS +++ b/board/freescale/t4qds/MAINTAINERS @@ -12,7 +12,7 @@ F: configs/T4240QDS_SDCARD_defconfig F: configs/T4240QDS_SRIO_PCIE_BOOT_defconfig T4160QDS_SECURE_BOOT BOARD -M: Aneesh Bansal <aneesh.bansal@freescale.com> +M: Ruchika Gupta <ruchika.gupta@nxp.com> S: Maintained F: configs/T4160QDS_SECURE_BOOT_defconfig F: configs/T4240QDS_SECURE_BOOT_defconfig diff --git a/board/gateworks/gw_ventana/common.c b/board/gateworks/gw_ventana/common.c index 929dde9880a..4065c5655a4 100644 --- a/board/gateworks/gw_ventana/common.c +++ b/board/gateworks/gw_ventana/common.c @@ -132,14 +132,14 @@ void setup_ventana_i2c(void) /* common to add baseboards */ static iomux_v3_cfg_t const gw_gpio_pads[] = { - /* RS232_EN# */ - IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG), /* SD3_VSELECT */ IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG), }; /* prototype */ static iomux_v3_cfg_t const gwproto_gpio_pads[] = { + /* RS232_EN# */ + IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG), /* PANLEDG# */ IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), /* PANLEDR# */ @@ -183,6 +183,8 @@ static iomux_v3_cfg_t const gw51xx_gpio_pads[] = { }; static iomux_v3_cfg_t const gw52xx_gpio_pads[] = { + /* RS232_EN# */ + IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG), /* MSATA_EN */ IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG), /* PANLEDG# */ @@ -214,6 +216,8 @@ static iomux_v3_cfg_t const gw52xx_gpio_pads[] = { }; static iomux_v3_cfg_t const gw53xx_gpio_pads[] = { + /* RS232_EN# */ + IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG), /* MSATA_EN */ IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG), /* CAN_STBY */ @@ -245,6 +249,8 @@ static iomux_v3_cfg_t const gw53xx_gpio_pads[] = { }; static iomux_v3_cfg_t const gw54xx_gpio_pads[] = { + /* RS232_EN# */ + IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG), /* MSATA_EN */ IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG), /* CAN_STBY */ @@ -332,6 +338,219 @@ static iomux_v3_cfg_t const gw553x_gpio_pads[] = { IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), }; +/* Digital I/O */ +struct dio_cfg gw51xx_dio[] = { + { + { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, + IMX_GPIO_NR(1, 16), + { 0, 0 }, + 0 + }, + { + { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, + IMX_GPIO_NR(1, 19), + { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, + 2 + }, + { + { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, + IMX_GPIO_NR(1, 17), + { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, + 3 + }, + { + { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) }, + IMX_GPIO_NR(1, 18), + { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) }, + 4 + }, +}; + +struct dio_cfg gw52xx_dio[] = { + { + { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, + IMX_GPIO_NR(1, 16), + { 0, 0 }, + 0 + }, + { + { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, + IMX_GPIO_NR(1, 19), + { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, + 2 + }, + { + { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, + IMX_GPIO_NR(1, 17), + { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, + 3 + }, + { + { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, + IMX_GPIO_NR(1, 20), + { 0, 0 }, + 0 + }, +}; + +struct dio_cfg gw53xx_dio[] = { + { + { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, + IMX_GPIO_NR(1, 16), + { 0, 0 }, + 0 + }, + { + { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, + IMX_GPIO_NR(1, 19), + { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, + 2 + }, + { + { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, + IMX_GPIO_NR(1, 17), + { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, + 3 + }, + { + {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, + IMX_GPIO_NR(1, 20), + { 0, 0 }, + 0 + }, +}; + +struct dio_cfg gw54xx_dio[] = { + { + { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) }, + IMX_GPIO_NR(1, 9), + { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) }, + 1 + }, + { + { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, + IMX_GPIO_NR(1, 19), + { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, + 2 + }, + { + { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) }, + IMX_GPIO_NR(2, 9), + { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) }, + 3 + }, + { + { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) }, + IMX_GPIO_NR(2, 10), + { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) }, + 4 + }, +}; + +struct dio_cfg gw551x_dio[] = { + { + { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, + IMX_GPIO_NR(1, 19), + { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, + 2 + }, + { + { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, + IMX_GPIO_NR(1, 17), + { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, + 3 + }, +}; + +struct dio_cfg gw552x_dio[] = { + { + { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, + IMX_GPIO_NR(1, 16), + { 0, 0 }, + 0 + }, + { + { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, + IMX_GPIO_NR(1, 19), + { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, + 2 + }, + { + { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, + IMX_GPIO_NR(1, 17), + { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, + 3 + }, + { + {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, + IMX_GPIO_NR(1, 20), + { 0, 0 }, + 0 + }, + { + {IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18) }, + IMX_GPIO_NR(5, 18), + { 0, 0 }, + 0 + }, + { + {IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20) }, + IMX_GPIO_NR(5, 20), + { 0, 0 }, + 0 + }, + { + {IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21) }, + IMX_GPIO_NR(5, 21), + { 0, 0 }, + 0 + }, + { + {IOMUX_PADS(PAD_CSI0_DAT4__GPIO5_IO22) }, + IMX_GPIO_NR(5, 22), + { 0, 0 }, + 0 + }, + { + {IOMUX_PADS(PAD_CSI0_DAT5__GPIO5_IO23) }, + IMX_GPIO_NR(5, 23), + { 0, 0 }, + 0 + }, + { + {IOMUX_PADS(PAD_CSI0_DAT7__GPIO5_IO25) }, + IMX_GPIO_NR(5, 25), + { 0, 0 }, + 0 + }, +}; + +struct dio_cfg gw553x_dio[] = { + { + { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, + IMX_GPIO_NR(1, 16), + { 0, 0 }, + 0 + }, + { + { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, + IMX_GPIO_NR(1, 19), + { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, + 2 + }, + { + { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, + IMX_GPIO_NR(1, 17), + { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, + 3 + }, + { + { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) }, + IMX_GPIO_NR(1, 18), + { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) }, + 4 + }, +}; /* * Board Specific GPIO @@ -341,33 +560,8 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { { .gpio_pads = gw54xx_gpio_pads, .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2, - .dio_cfg = { - { - { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) }, - IMX_GPIO_NR(1, 9), - { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) }, - 1 - }, - { - { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, - IMX_GPIO_NR(1, 19), - { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, - 2 - }, - { - { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) }, - IMX_GPIO_NR(2, 9), - { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) }, - 3 - }, - { - { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) }, - IMX_GPIO_NR(2, 10), - { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) }, - 4 - }, - }, - .num_gpios = 4, + .dio_cfg = gw54xx_dio, + .dio_num = ARRAY_SIZE(gw54xx_dio), .leds = { IMX_GPIO_NR(4, 6), IMX_GPIO_NR(4, 10), @@ -385,33 +579,8 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { { .gpio_pads = gw51xx_gpio_pads, .num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2, - .dio_cfg = { - { - { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, - IMX_GPIO_NR(1, 16), - { 0, 0 }, - 0 - }, - { - { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, - IMX_GPIO_NR(1, 19), - { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, - 2 - }, - { - { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, - IMX_GPIO_NR(1, 17), - { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, - 3 - }, - { - { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) }, - IMX_GPIO_NR(1, 18), - { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) }, - 4 - }, - }, - .num_gpios = 4, + .dio_cfg = gw51xx_dio, + .dio_num = ARRAY_SIZE(gw51xx_dio), .leds = { IMX_GPIO_NR(4, 6), IMX_GPIO_NR(4, 10), @@ -428,33 +597,8 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { { .gpio_pads = gw52xx_gpio_pads, .num_pads = ARRAY_SIZE(gw52xx_gpio_pads)/2, - .dio_cfg = { - { - { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, - IMX_GPIO_NR(1, 16), - { 0, 0 }, - 0 - }, - { - { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, - IMX_GPIO_NR(1, 19), - { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, - 2 - }, - { - { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, - IMX_GPIO_NR(1, 17), - { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, - 3 - }, - { - { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, - IMX_GPIO_NR(1, 20), - { 0, 0 }, - 0 - }, - }, - .num_gpios = 4, + .dio_cfg = gw52xx_dio, + .dio_num = ARRAY_SIZE(gw52xx_dio), .leds = { IMX_GPIO_NR(4, 6), IMX_GPIO_NR(4, 7), @@ -468,39 +612,15 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .usb_sel = IMX_GPIO_NR(1, 2), .wdis = IMX_GPIO_NR(7, 12), .msata_en = GP_MSATA_SEL, + .rs232_en = GP_RS232_EN, }, /* GW53xx */ { .gpio_pads = gw53xx_gpio_pads, .num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2, - .dio_cfg = { - { - { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, - IMX_GPIO_NR(1, 16), - { 0, 0 }, - 0 - }, - { - { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, - IMX_GPIO_NR(1, 19), - { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, - 2 - }, - { - { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, - IMX_GPIO_NR(1, 17), - { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, - 3 - }, - { - {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, - IMX_GPIO_NR(1, 20), - { 0, 0 }, - 0 - }, - }, - .num_gpios = 4, + .dio_cfg = gw53xx_dio, + .dio_num = ARRAY_SIZE(gw53xx_dio), .leds = { IMX_GPIO_NR(4, 6), IMX_GPIO_NR(4, 7), @@ -513,39 +633,15 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .vidin_en = IMX_GPIO_NR(3, 31), .wdis = IMX_GPIO_NR(7, 12), .msata_en = GP_MSATA_SEL, + .rs232_en = GP_RS232_EN, }, /* GW54xx */ { .gpio_pads = gw54xx_gpio_pads, .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2, - .dio_cfg = { - { - { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) }, - IMX_GPIO_NR(1, 9), - { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) }, - 1 - }, - { - { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, - IMX_GPIO_NR(1, 19), - { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, - 2 - }, - { - { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) }, - IMX_GPIO_NR(2, 9), - { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) }, - 3 - }, - { - { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) }, - IMX_GPIO_NR(2, 10), - { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) }, - 4 - }, - }, - .num_gpios = 4, + .dio_cfg = gw54xx_dio, + .dio_num = ARRAY_SIZE(gw54xx_dio), .leds = { IMX_GPIO_NR(4, 6), IMX_GPIO_NR(4, 7), @@ -560,27 +656,15 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { .pcie_sson = IMX_GPIO_NR(1, 20), .wdis = IMX_GPIO_NR(5, 17), .msata_en = GP_MSATA_SEL, + .rs232_en = GP_RS232_EN, }, /* GW551x */ { .gpio_pads = gw551x_gpio_pads, .num_pads = ARRAY_SIZE(gw551x_gpio_pads)/2, - .dio_cfg = { - { - { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, - IMX_GPIO_NR(1, 19), - { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, - 2 - }, - { - { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, - IMX_GPIO_NR(1, 17), - { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, - 3 - }, - }, - .num_gpios = 2, + .dio_cfg = gw551x_dio, + .dio_num = ARRAY_SIZE(gw551x_dio), .leds = { IMX_GPIO_NR(4, 7), }, @@ -592,33 +676,8 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { { .gpio_pads = gw552x_gpio_pads, .num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2, - .dio_cfg = { - { - { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, - IMX_GPIO_NR(1, 16), - { 0, 0 }, - 0 - }, - { - { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, - IMX_GPIO_NR(1, 19), - { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, - 2 - }, - { - { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, - IMX_GPIO_NR(1, 17), - { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, - 3 - }, - { - {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, - IMX_GPIO_NR(1, 20), - { 0, 0 }, - 0 - }, - }, - .num_gpios = 4, + .dio_cfg = gw552x_dio, + .dio_num = ARRAY_SIZE(gw552x_dio), .leds = { IMX_GPIO_NR(4, 6), IMX_GPIO_NR(4, 7), @@ -634,33 +693,8 @@ struct ventana gpio_cfg[GW_UNKNOWN] = { { .gpio_pads = gw553x_gpio_pads, .num_pads = ARRAY_SIZE(gw553x_gpio_pads)/2, - .dio_cfg = { - { - { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, - IMX_GPIO_NR(1, 16), - { 0, 0 }, - 0 - }, - { - { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, - IMX_GPIO_NR(1, 19), - { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, - 2 - }, - { - { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, - IMX_GPIO_NR(1, 17), - { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, - 3 - }, - { - { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) }, - IMX_GPIO_NR(1, 18), - { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) }, - 4 - }, - }, - .num_gpios = 4, + .dio_cfg = gw553x_dio, + .dio_num = ARRAY_SIZE(gw553x_dio), .leds = { IMX_GPIO_NR(4, 10), IMX_GPIO_NR(4, 11), @@ -682,10 +716,6 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info) gpio_request(GP_USB_OTG_PWR, "usbotg_pwr"); gpio_direction_output(GP_USB_OTG_PWR, 0); - /* RS232_EN# */ - gpio_request(GP_RS232_EN, "rs232_en"); - gpio_direction_output(GP_RS232_EN, 0); - if (board >= GW_UNKNOWN) return; @@ -693,6 +723,12 @@ void setup_iomux_gpio(int board, struct ventana_board_info *info) imx_iomux_v3_setup_multiple_pads(gpio_cfg[board].gpio_pads, gpio_cfg[board].num_pads); + /* RS232_EN# */ + if (gpio_cfg[board].rs232_en) { + gpio_request(gpio_cfg[board].rs232_en, "rs232_en"); + gpio_direction_output(gpio_cfg[board].rs232_en, 0); + } + /* GW522x Uses GPIO3_IO23 for PCIE_RST# */ if (board == GW52xx && info->model[4] == '2') gpio_cfg[board].pcie_rst = IMX_GPIO_NR(3, 23); @@ -788,7 +824,10 @@ void setup_board_gpio(int board, struct ventana_board_info *info) return; /* RS232_EN# */ - gpio_direction_output(GP_RS232_EN, (hwconfig("rs232")) ? 0 : 1); + if (gpio_cfg[board].rs232_en) { + gpio_direction_output(gpio_cfg[board].rs232_en, + (hwconfig("rs232")) ? 0 : 1); + } /* MSATA Enable */ if (gpio_cfg[board].msata_en && is_cpu_type(MXC_CPU_MX6Q)) { @@ -806,7 +845,7 @@ void setup_board_gpio(int board, struct ventana_board_info *info) * Configure DIO pinmux/padctl registers * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions */ - for (i = 0; i < gpio_cfg[board].num_gpios; i++) { + for (i = 0; i < gpio_cfg[board].dio_num; i++) { struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i]; iomux_v3_cfg_t ctrl = DIO_PAD_CFG; unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1; @@ -851,8 +890,10 @@ void setup_board_gpio(int board, struct ventana_board_info *info) printf("MSATA: %s\n", (hwconfig("msata") ? "enabled" : "disabled")); } - printf("RS232: %s\n", (hwconfig("rs232")) ? - "enabled" : "disabled"); + if (gpio_cfg[board].rs232_en) { + printf("RS232: %s\n", (hwconfig("rs232")) ? + "enabled" : "disabled"); + } } } diff --git a/board/gateworks/gw_ventana/common.h b/board/gateworks/gw_ventana/common.h index d037767ecc8..3d7aff1077c 100644 --- a/board/gateworks/gw_ventana/common.h +++ b/board/gateworks/gw_ventana/common.h @@ -48,8 +48,8 @@ #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) /* - * each baseboard has 4 user configurable Digital IO lines which can - * be pinmuxed as a GPIO or in some cases a PWM + * each baseboard has an optional set user configurable Digital IO lines which + * can be pinmuxed as a GPIO or in some cases a PWM */ struct dio_cfg { iomux_v3_cfg_t gpio_padmux[2]; @@ -63,8 +63,8 @@ struct ventana { iomux_v3_cfg_t const *gpio_pads; int num_pads; /* DIO pinmux/val */ - struct dio_cfg dio_cfg[4]; - int num_gpios; + struct dio_cfg *dio_cfg; + int dio_num; /* various gpios (0 if non-existent) */ int leds[3]; int pcie_rst; @@ -78,6 +78,8 @@ struct ventana { int usb_sel; int wdis; int msata_en; + int rs232_en; + /* various features */ bool usd_vsel; }; diff --git a/board/gateworks/gw_ventana/gw_ventana.c b/board/gateworks/gw_ventana/gw_ventana.c index 70395ac91db..5d871ceed91 100644 --- a/board/gateworks/gw_ventana/gw_ventana.c +++ b/board/gateworks/gw_ventana/gw_ventana.c @@ -491,14 +491,54 @@ int imx6_pcie_toggle_reset(void) * GPIO's as PERST# signals for its downstream ports - configure the GPIO's * properly and assert reset for 100ms. */ +#define MAX_PCI_DEVS 32 +struct pci_dev { + pci_dev_t devfn; + unsigned short vendor; + unsigned short device; + unsigned short class; + unsigned short busno; /* subbordinate busno */ + struct pci_dev *ppar; +}; +struct pci_dev pci_devs[MAX_PCI_DEVS]; +int pci_devno; +int pci_bridgeno; + void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev, unsigned short vendor, unsigned short device, unsigned short class) { + int i; u32 dw; + struct pci_dev *pdev = &pci_devs[pci_devno++]; debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__, PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device); + + /* store array of devs for later use in device-tree fixup */ + pdev->devfn = dev; + pdev->vendor = vendor; + pdev->device = device; + pdev->class = class; + pdev->ppar = NULL; + if (class == PCI_CLASS_BRIDGE_PCI) + pdev->busno = ++pci_bridgeno; + else + pdev->busno = 0; + + /* fixup RC - it should be 00:00.0 not 00:01.0 */ + if (PCI_BUS(dev) == 0) + pdev->devfn = 0; + + /* find dev's parent */ + for (i = 0; i < pci_devno; i++) { + if (pci_devs[i].busno == PCI_BUS(pdev->devfn)) { + pdev->ppar = &pci_devs[i]; + break; + } + } + + /* assert downstream PERST# */ if (vendor == PCI_VENDOR_ID_PLX && (device & 0xfff0) == 0x8600 && PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) { @@ -660,13 +700,14 @@ static const struct boot_mode board_boot_modes[] = { int misc_init_r(void) { struct ventana_board_info *info = &ventana_info; + char buf[256]; + int i; /* set env vars based on EEPROM data */ if (ventana_info.model[0]) { char str[16], fdt[36]; char *p; const char *cputype = ""; - int i; /* * FDT name will be prefixed with CPU type. Three versions @@ -729,6 +770,19 @@ int misc_init_r(void) setenv("mem_mb", str); } + /* Set a non-initialized hwconfig based on board configuration */ + if (!strcmp(getenv("hwconfig"), "_UNKNOWN_")) { + sprintf(buf, "hwconfig="); + if (gpio_cfg[board_type].rs232_en) + strcat(buf, "rs232;"); + for (i = 0; i < gpio_cfg[board_type].dio_num; i++) { + char buf1[32]; + sprintf(buf1, "dio%d:mode=gpio;", i); + if (strlen(buf) + strlen(buf1) < sizeof(buf)) + strcat(buf, buf1); + } + setenv("hwconfig", buf); + } /* setup baseboard specific GPIO based on board and env */ setup_board_gpio(board_type, info); @@ -802,6 +856,224 @@ static inline void ft_delprop_path(void *blob, const char *path, } } +#if defined(CONFIG_CMD_PCI) +#define PCI_ID(x) ( \ + (PCI_BUS(x->devfn)<<16)| \ + (PCI_DEV(x->devfn)<<11)| \ + (PCI_FUNC(x->devfn)<<8) \ + ) +#define PCIE_PATH "/soc/pcie@0x01000000" +int fdt_add_pci_node(void *blob, int par, struct pci_dev *dev) +{ + uint32_t reg[5]; + char node[32]; + int np; + + sprintf(node, "pcie@%d,%d,%d", PCI_BUS(dev->devfn), + PCI_DEV(dev->devfn), PCI_FUNC(dev->devfn)); + + np = fdt_subnode_offset(blob, par, node); + if (np >= 0) + return np; + np = fdt_add_subnode(blob, par, node); + if (np < 0) { + printf(" %s failed: no space\n", __func__); + return np; + } + + memset(reg, 0, sizeof(reg)); + reg[0] = cpu_to_fdt32(PCI_ID(dev)); + fdt_setprop(blob, np, "reg", reg, sizeof(reg)); + + return np; +} + +/* build a path of nested PCI devs for all bridges passed through */ +int fdt_add_pci_path(void *blob, struct pci_dev *dev) +{ + struct pci_dev *bridges[MAX_PCI_DEVS]; + int k, np; + + /* build list of parents */ + np = fdt_path_offset(blob, PCIE_PATH); + if (np < 0) + return np; + + k = 0; + while (dev) { + bridges[k++] = dev; + dev = dev->ppar; + }; + + /* now add them the to DT in reverse order */ + while (k--) { + np = fdt_add_pci_node(blob, np, bridges[k]); + if (np < 0) + break; + } + + return np; +} + +/* + * The GW16082 has a hardware errata errata such that it's + * INTA/B/C/D are mis-mapped to its four slots (slot12-15). Because + * of this normal PCI interrupt swizzling will not work so we will + * provide an irq-map via device-tree. + */ +int fdt_fixup_gw16082(void *blob, int np, struct pci_dev *dev) +{ + int len; + int host; + uint32_t imap_new[8*4*4]; + const uint32_t *imap; + uint32_t irq[4]; + uint32_t reg[4]; + int i; + + /* build irq-map based on host controllers map */ + host = fdt_path_offset(blob, PCIE_PATH); + if (host < 0) { + printf(" %s failed: missing host\n", __func__); + return host; + } + + /* use interrupt data from root complex's node */ + imap = fdt_getprop(blob, host, "interrupt-map", &len); + if (!imap || len != 128) { + printf(" %s failed: invalid interrupt-map\n", + __func__); + return -FDT_ERR_NOTFOUND; + } + + /* obtain irq's of host controller in pin order */ + for (i = 0; i < 4; i++) + irq[(fdt32_to_cpu(imap[(i*8)+3])-1)%4] = imap[(i*8)+6]; + + /* + * determine number of swizzles necessary: + * For each bridge we pass through we need to swizzle + * the number of the slot we are on. + */ + struct pci_dev *d; + int b; + b = 0; + d = dev->ppar; + while(d && d->ppar) { + b += PCI_DEV(d->devfn); + d = d->ppar; + } + + /* create new irq mappings for slots12-15 + * <skt> <idsel> <slot> <skt-inta> <skt-intb> + * J3 AD28 12 INTD INTA + * J4 AD29 13 INTC INTD + * J5 AD30 14 INTB INTC + * J2 AD31 15 INTA INTB + */ + for (i = 0; i < 4; i++) { + /* addr matches bus:dev:func */ + u32 addr = dev->busno << 16 | (12+i) << 11; + + /* default cells from root complex */ + memcpy(&imap_new[i*32], imap, 128); + /* first cell is PCI device address (BDF) */ + imap_new[(i*32)+(0*8)+0] = cpu_to_fdt32(addr); + imap_new[(i*32)+(1*8)+0] = cpu_to_fdt32(addr); + imap_new[(i*32)+(2*8)+0] = cpu_to_fdt32(addr); + imap_new[(i*32)+(3*8)+0] = cpu_to_fdt32(addr); + /* third cell is pin */ + imap_new[(i*32)+(0*8)+3] = cpu_to_fdt32(1); + imap_new[(i*32)+(1*8)+3] = cpu_to_fdt32(2); + imap_new[(i*32)+(2*8)+3] = cpu_to_fdt32(3); + imap_new[(i*32)+(3*8)+3] = cpu_to_fdt32(4); + /* sixth cell is relative interrupt */ + imap_new[(i*32)+(0*8)+6] = irq[(15-(12+i)+b+0)%4]; + imap_new[(i*32)+(1*8)+6] = irq[(15-(12+i)+b+1)%4]; + imap_new[(i*32)+(2*8)+6] = irq[(15-(12+i)+b+2)%4]; + imap_new[(i*32)+(3*8)+6] = irq[(15-(12+i)+b+3)%4]; + } + fdt_setprop(blob, np, "interrupt-map", imap_new, + sizeof(imap_new)); + reg[0] = cpu_to_fdt32(0xfff00); + reg[1] = 0; + reg[2] = 0; + reg[3] = cpu_to_fdt32(0x7); + fdt_setprop(blob, np, "interrupt-map-mask", reg, sizeof(reg)); + fdt_setprop_cell(blob, np, "#interrupt-cells", 1); + fdt_setprop_string(blob, np, "device_type", "pci"); + fdt_setprop_cell(blob, np, "#address-cells", 3); + fdt_setprop_cell(blob, np, "#size-cells", 2); + printf(" Added custom interrupt-map for GW16082\n"); + + return 0; +} + +/* The sky2 GigE MAC obtains it's MAC addr from device-tree by default */ +int fdt_fixup_sky2(void *blob, int np, struct pci_dev *dev) +{ + char *tmp, *end; + char mac[16]; + unsigned char mac_addr[6]; + int j; + + sprintf(mac, "eth1addr"); + tmp = getenv(mac); + if (tmp) { + for (j = 0; j < 6; j++) { + mac_addr[j] = tmp ? + simple_strtoul(tmp, &end,16) : 0; + if (tmp) + tmp = (*end) ? end+1 : end; + } + fdt_setprop(blob, np, "local-mac-address", mac_addr, + sizeof(mac_addr)); + printf(" Added mac addr for eth1\n"); + return 0; + } + + return -1; +} + +/* + * PCI DT nodes must be nested therefore if we need to apply a DT fixup + * we will walk the PCI bus and add bridge nodes up to the device receiving + * the fixup. + */ +void ft_board_pci_fixup(void *blob, bd_t *bd) +{ + int i, np; + struct pci_dev *dev; + + for (i = 0; i < pci_devno; i++) { + dev = &pci_devs[i]; + + /* + * The GW16082 consists of a TI XIO2001 PCIe-to-PCI bridge and + * an EEPROM at i2c1-0x50. + */ + if ((dev->vendor == PCI_VENDOR_ID_TI) && + (dev->device == 0x8240) && + (i2c_set_bus_num(1) == 0) && + (i2c_probe(0x50) == 0)) + { + np = fdt_add_pci_path(blob, dev); + if (np > 0) + fdt_fixup_gw16082(blob, np, dev); + } + + /* ethernet1 mac address */ + else if ((dev->vendor == PCI_VENDOR_ID_MARVELL) && + (dev->device == 0x4380)) + { + np = fdt_add_pci_path(blob, dev); + if (np > 0) + fdt_fixup_sky2(blob, np, dev); + } + } +} +#endif /* if defined(CONFIG_CMD_PCI) */ + /* * called prior to booting kernel or by 'fdt boardsetup' command * @@ -811,6 +1083,10 @@ static inline void ft_delprop_path(void *blob, const char *path, * - board (full model from EEPROM) * - peripherals removed from DTB if not loaded on board (per EEPROM config) */ +#define UART1_PATH "/soc/aips-bus@02100000/serial@021ec000" +#define WDOG1_PATH "/soc/aips-bus@02000000/wdog@020bc000" +#define WDOG2_PATH "/soc/aips-bus@02000000/wdog@020c0000" +#define GPIO3_PATH "/soc/aips-bus@02000000/gpio@020a4000" int ft_board_setup(void *blob, bd_t *bd) { struct ventana_board_info *info = &ventana_info; @@ -864,94 +1140,140 @@ int ft_board_setup(void *blob, bd_t *bd) ft_sethdmiinfmt(blob, getenv("hdmiinfmt")); /* - * disable serial2 node for GW54xx for compatibility with older - * 3.10.x kernel that improperly had this node enabled in the DT + * Board model specific fixups */ - if (board_type == GW54xx) { - i = fdt_path_offset(blob, - "/soc/aips-bus@02100000/serial@021ec000"); - if (i) - fdt_del_node(blob, i); - } - - /* - * disable wdog1/wdog2 nodes for GW51xx below revC to work around - * errata causing wdog timer to be unreliable. - */ - if (board_type == GW51xx && rev >= 'A' && rev < 'C') { - i = fdt_path_offset(blob, - "/soc/aips-bus@02000000/wdog@020bc000"); - if (i) - fdt_status_disabled(blob, i); - } + switch (board_type) { + case GW51xx: + /* + * disable wdog node for GW51xx-A/B to work around + * errata causing wdog timer to be unreliable. + */ + if (rev >= 'A' && rev < 'C') { + i = fdt_path_offset(blob, WDOG1_PATH); + if (i) + fdt_status_disabled(blob, i); + } - /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */ - else if (board_type == GW52xx && info->model[4] == '2') { - u32 handle = 0; - u32 *range = NULL; + /* GW51xx-E adds WDOG1_B external reset */ + if (rev < 'E') + ft_delprop_path(blob, WDOG1_PATH, + "fsl,ext-reset-output"); + break; - i = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie"); - if (i) - range = (u32 *)fdt_getprop(blob, i, "reset-gpio", - NULL); + case GW52xx: + /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */ + if (info->model[4] == '2') { + u32 handle = 0; + u32 *range = NULL; - if (range) { - i = fdt_path_offset(blob, - "/soc/aips-bus@02000000/gpio@020a4000"); + i = fdt_node_offset_by_compatible(blob, -1, + "fsl,imx6q-pcie"); if (i) - handle = fdt_get_phandle(blob, i); - if (handle) { - range[0] = cpu_to_fdt32(handle); - range[1] = cpu_to_fdt32(23); + range = (u32 *)fdt_getprop(blob, i, + "reset-gpio", NULL); + + if (range) { + i = fdt_path_offset(blob, GPIO3_PATH); + if (i) + handle = fdt_get_phandle(blob, i); + if (handle) { + range[0] = cpu_to_fdt32(handle); + range[1] = cpu_to_fdt32(23); + } } - } - /* these have broken usd_vsel */ - if (strstr((const char *)info->model, "SP318-B") || - strstr((const char *)info->model, "SP331-B")) - gpio_cfg[board_type].usd_vsel = 0; - } + /* these have broken usd_vsel */ + if (strstr((const char *)info->model, "SP318-B") || + strstr((const char *)info->model, "SP331-B")) + gpio_cfg[board_type].usd_vsel = 0; - /* - * isolate CSI0_DATA_EN for GW551x below revB to work around - * errata causing non functional digital video in (it is not hooked up) - */ - else if (board_type == GW551x && rev == 'A') { - u32 *range = NULL; - int len; - const u32 *handle = NULL; + /* GW520x-E adds WDOG1_B external reset */ + if (info->model[4] == '0' && rev < 'E') + ft_delprop_path(blob, WDOG1_PATH, + "fsl,ext-reset-output"); - i = fdt_node_offset_by_compatible(blob, -1, - "fsl,imx-tda1997x-video"); - if (i) - handle = fdt_getprop(blob, i, "pinctrl-0", NULL); - if (handle) - i = fdt_node_offset_by_phandle(blob, - fdt32_to_cpu(*handle)); + /* GW522x-B adds WDOG1_B external reset */ + if (info->model[4] == '2' && rev < 'B') + ft_delprop_path(blob, WDOG1_PATH, + "fsl,ext-reset-output"); + } + break; + + case GW53xx: + /* GW53xx-E adds WDOG1_B external reset */ + if (rev < 'E') + ft_delprop_path(blob, WDOG1_PATH, + "fsl,ext-reset-output"); + break; + + case GW54xx: + /* + * disable serial2 node for GW54xx for compatibility with older + * 3.10.x kernel that improperly had this node enabled in the DT + */ + i = fdt_path_offset(blob, UART1_PATH); if (i) - range = (u32 *)fdt_getprop(blob, i, "fsl,pins", &len); - if (range) { - len /= sizeof(u32); - for (i = 0; i < len; i += 6) { - u32 mux_reg = fdt32_to_cpu(range[i+0]); - u32 conf_reg = fdt32_to_cpu(range[i+1]); - /* mux PAD_CSI0_DATA_EN to GPIO */ - if (is_cpu_type(MXC_CPU_MX6Q) && - mux_reg == 0x260 && conf_reg == 0x630) - range[i+3] = cpu_to_fdt32(0x5); - else if (!is_cpu_type(MXC_CPU_MX6Q) && - mux_reg == 0x08c && conf_reg == 0x3a0) - range[i+3] = cpu_to_fdt32(0x5); + fdt_del_node(blob, i); + + /* GW54xx-E adds WDOG2_B external reset */ + if (rev < 'E') + ft_delprop_path(blob, WDOG2_PATH, + "fsl,ext-reset-output"); + break; + + case GW551x: + /* + * isolate CSI0_DATA_EN for GW551x-A to work around errata + * causing non functional digital video in (it is not hooked up) + */ + if (rev == 'A') { + u32 *range = NULL; + int len; + const u32 *handle = NULL; + + i = fdt_node_offset_by_compatible(blob, -1, + "fsl,imx-tda1997x-video"); + if (i) + handle = fdt_getprop(blob, i, "pinctrl-0", + NULL); + if (handle) + i = fdt_node_offset_by_phandle(blob, + fdt32_to_cpu(*handle)); + if (i) + range = (u32 *)fdt_getprop(blob, i, "fsl,pins", + &len); + if (range) { + len /= sizeof(u32); + for (i = 0; i < len; i += 6) { + u32 mux_reg = fdt32_to_cpu(range[i+0]); + u32 conf_reg = fdt32_to_cpu(range[i+1]); + /* mux PAD_CSI0_DATA_EN to GPIO */ + if (is_cpu_type(MXC_CPU_MX6Q) && + mux_reg == 0x260 && + conf_reg == 0x630) + range[i+3] = cpu_to_fdt32(0x5); + else if (!is_cpu_type(MXC_CPU_MX6Q) && + mux_reg == 0x08c && + conf_reg == 0x3a0) + range[i+3] = cpu_to_fdt32(0x5); + } + fdt_setprop_inplace(blob, i, "fsl,pins", range, + len); } - fdt_setprop_inplace(blob, i, "fsl,pins", range, len); + + /* set BT656 video format */ + ft_sethdmiinfmt(blob, "yuv422bt656"); } - /* set BT656 video format */ - ft_sethdmiinfmt(blob, "yuv422bt656"); + /* GW551x-C adds WDOG1_B external reset */ + if (rev < 'C') + ft_delprop_path(blob, WDOG1_PATH, + "fsl,ext-reset-output"); + break; } /* Configure DIO */ - for (i = 0; i < gpio_cfg[board_type].num_gpios; i++) { + for (i = 0; i < gpio_cfg[board_type].dio_num; i++) { struct dio_cfg *cfg = &gpio_cfg[board_type].dio_cfg[i]; char arg[10]; @@ -976,6 +1298,11 @@ int ft_board_setup(void *blob, bd_t *bd) "no-1-8-v"); } +#if defined(CONFIG_CMD_PCI) + if (!getenv("nopcifixup")) + ft_board_pci_fixup(blob, bd); +#endif + /* * Peripheral Config: * remove nodes by alias path if EEPROM config tells us the diff --git a/board/gdsys/405ep/405ep.c b/board/gdsys/405ep/405ep.c index 426dc05c7d3..35fa06a2ee9 100644 --- a/board/gdsys/405ep/405ep.c +++ b/board/gdsys/405ep/405ep.c @@ -31,14 +31,6 @@ int get_fpga_state(unsigned dev) return gd->arch.fpga_state[dev]; } -void print_fpga_state(unsigned dev) -{ - if (gd->arch.fpga_state[dev] & FPGA_STATE_DONE_FAILED) - puts(" Waiting for FPGA-DONE timed out.\n"); - if (gd->arch.fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED) - puts(" FPGA reflection test failed.\n"); -} - int board_early_init_f(void) { unsigned k; diff --git a/board/gdsys/405ep/dlvision-10g.c b/board/gdsys/405ep/dlvision-10g.c index 54c7eb3a12a..e400d1945a7 100644 --- a/board/gdsys/405ep/dlvision-10g.c +++ b/board/gdsys/405ep/dlvision-10g.c @@ -109,7 +109,10 @@ static void print_fpga_info(unsigned dev) && !((hardware_version == HWVER_101) && (fpga_state == FPGA_STATE_DONE_FAILED))) { puts("not available\n"); - print_fpga_state(dev); + if (fpga_state & FPGA_STATE_DONE_FAILED) + puts(" Waiting for FPGA-DONE timed out.\n"); + if (fpga_state & FPGA_STATE_REFLECTION_FAILED) + puts(" FPGA reflection test failed.\n"); return; } diff --git a/board/gdsys/405ep/io.c b/board/gdsys/405ep/io.c index 03d796cdb89..81b49659ff8 100644 --- a/board/gdsys/405ep/io.c +++ b/board/gdsys/405ep/io.c @@ -172,8 +172,17 @@ int last_stage_init(void) print_fpga_info(); - miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME, - bb_miiphy_read, bb_miiphy_write); + int retval; + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; + strncpy(mdiodev->name, CONFIG_SYS_GBIT_MII_BUSNAME, MDIO_NAME_LEN); + mdiodev->read = bb_miiphy_read; + mdiodev->write = bb_miiphy_write; + + retval = mdio_register(mdiodev); + if (retval < 0) + return retval; for (k = 0; k < 32; ++k) configure_gbit_phy(k); diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c index 7484624d13e..7db0e29ea6c 100644 --- a/board/gdsys/405ep/iocon.c +++ b/board/gdsys/405ep/iocon.c @@ -405,8 +405,17 @@ int last_stage_init(void) } if (!legacy && (feature_carrier_speed == CARRIER_SPEED_1G)) { - miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read, - bb_miiphy_write); + int retval; + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; + strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN); + mdiodev->read = bb_miiphy_read; + mdiodev->write = bb_miiphy_write; + + retval = mdio_register(mdiodev); + if (retval < 0) + return retval; for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) { if ((mux_ch == 1) && !ch0_rgmii2_present) continue; @@ -437,8 +446,18 @@ int last_stage_init(void) print_fpga_info(k, false); osd_probe(k); if (feature_carrier_speed == CARRIER_SPEED_1G) { - miiphy_register(bb_miiphy_buses[k].name, - bb_miiphy_read, bb_miiphy_write); + int retval; + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; + strncpy(mdiodev->name, bb_miiphy_buses[k].name, + MDIO_NAME_LEN); + mdiodev->read = bb_miiphy_read; + mdiodev->write = bb_miiphy_write; + + retval = mdio_register(mdiodev); + if (retval < 0) + return retval; setup_88e1518(bb_miiphy_buses[k].name, 0); } } diff --git a/board/gdsys/405ex/405ex.c b/board/gdsys/405ex/405ex.c index c1a583ffbe0..9e1c57f8085 100644 --- a/board/gdsys/405ex/405ex.c +++ b/board/gdsys/405ex/405ex.c @@ -24,14 +24,6 @@ int get_fpga_state(unsigned dev) return gd->arch.fpga_state[dev]; } -void print_fpga_state(unsigned dev) -{ - if (gd->arch.fpga_state[dev] & FPGA_STATE_DONE_FAILED) - puts(" Waiting for FPGA-DONE timed out.\n"); - if (gd->arch.fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED) - puts(" FPGA reflection test failed.\n"); -} - int board_early_init_f(void) { u32 val; diff --git a/board/gdsys/405ex/io64.c b/board/gdsys/405ex/io64.c index 3a075c471f8..848cdde5e6b 100644 --- a/board/gdsys/405ex/io64.c +++ b/board/gdsys/405ex/io64.c @@ -246,8 +246,17 @@ int last_stage_init(void) /* setup Gbit PHYs */ puts("TRANS: "); puts(str_phys); - miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME, - bb_miiphy_read, bb_miiphy_write); + int retval; + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; + strncpy(mdiodev->name, CONFIG_SYS_GBIT_MII_BUSNAME, MDIO_NAME_LEN); + mdiodev->read = bb_miiphy_read; + mdiodev->write = bb_miiphy_write; + + retval = mdio_register(mdiodev); + if (retval < 0) + return retval; for (k = 0; k < 32; ++k) { configure_gbit_phy(CONFIG_SYS_GBIT_MII_BUSNAME, k); @@ -255,8 +264,16 @@ int last_stage_init(void) putc(slash[k % 8]); } - miiphy_register(CONFIG_SYS_GBIT_MII1_BUSNAME, - bb_miiphy_read, bb_miiphy_write); + mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; + strncpy(mdiodev->name, CONFIG_SYS_GBIT_MII1_BUSNAME, MDIO_NAME_LEN); + mdiodev->read = bb_miiphy_read; + mdiodev->write = bb_miiphy_write; + + retval = mdio_register(mdiodev); + if (retval < 0) + return retval; for (k = 0; k < 32; ++k) { configure_gbit_phy(CONFIG_SYS_GBIT_MII1_BUSNAME, k); diff --git a/board/gdsys/mpc8308/hrcon.c b/board/gdsys/mpc8308/hrcon.c index 880b6387de2..f55893f79c9 100644 --- a/board/gdsys/mpc8308/hrcon.c +++ b/board/gdsys/mpc8308/hrcon.c @@ -162,8 +162,17 @@ int last_stage_init(void) } if (hw_type_cat) { - miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read, - bb_miiphy_write); + int retval; + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; + strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN); + mdiodev->read = bb_miiphy_read; + mdiodev->write = bb_miiphy_write; + + retval = mdio_register(mdiodev); + if (retval < 0) + return retval; for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) { if ((mux_ch == 1) && !ch0_rgmii2_present) continue; @@ -199,8 +208,18 @@ int last_stage_init(void) osd_probe(k + 4); #endif if (hw_type_cat) { - miiphy_register(bb_miiphy_buses[k].name, - bb_miiphy_read, bb_miiphy_write); + int retval; + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; + strncpy(mdiodev->name, bb_miiphy_buses[k].name, + MDIO_NAME_LEN); + mdiodev->read = bb_miiphy_read; + mdiodev->write = bb_miiphy_write; + + retval = mdio_register(mdiodev); + if (retval < 0) + return retval; setup_88e1514(bb_miiphy_buses[k].name, 0); } } diff --git a/board/gdsys/mpc8308/mpc8308.c b/board/gdsys/mpc8308/mpc8308.c index 4338a331268..1b8e035b4b2 100644 --- a/board/gdsys/mpc8308/mpc8308.c +++ b/board/gdsys/mpc8308/mpc8308.c @@ -31,14 +31,6 @@ int get_fpga_state(unsigned dev) return gd->arch.fpga_state[dev]; } -void print_fpga_state(unsigned dev) -{ - if (gd->arch.fpga_state[dev] & FPGA_STATE_DONE_FAILED) - puts(" Waiting for FPGA-DONE timed out.\n"); - if (gd->arch.fpga_state[dev] & FPGA_STATE_REFLECTION_FAILED) - puts(" FPGA reflection test failed.\n"); -} - int board_early_init_f(void) { unsigned k; diff --git a/board/gdsys/mpc8308/strider.c b/board/gdsys/mpc8308/strider.c index 121977d315f..b8dde5f1bad 100644 --- a/board/gdsys/mpc8308/strider.c +++ b/board/gdsys/mpc8308/strider.c @@ -179,8 +179,17 @@ int last_stage_init(void) } if (hw_type_cat) { - miiphy_register(bb_miiphy_buses[0].name, bb_miiphy_read, - bb_miiphy_write); + int retval; + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; + strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN); + mdiodev->read = bb_miiphy_read; + mdiodev->write = bb_miiphy_write; + + retval = mdio_register(mdiodev); + if (retval < 0) + return retval; for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) { if ((mux_ch == 1) && !ch0_sgmii2_present) continue; @@ -252,8 +261,18 @@ int last_stage_init(void) dp501_probe(k, false); #endif if (hw_type_cat) { - miiphy_register(bb_miiphy_buses[k].name, - bb_miiphy_read, bb_miiphy_write); + int retval; + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; + strncpy(mdiodev->name, bb_miiphy_buses[k].name, + MDIO_NAME_LEN); + mdiodev->read = bb_miiphy_read; + mdiodev->write = bb_miiphy_write; + + retval = mdio_register(mdiodev); + if (retval < 0) + return retval; setup_88e1514(bb_miiphy_buses[k].name, 0); } } diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index d45ed44c684..e9729f88e5c 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -60,7 +60,7 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + gd->ram_size = imx_ddr_size(); return 0; } diff --git a/board/gumstix/duovero/duovero.c b/board/gumstix/duovero/duovero.c index 9671c5aa54b..3786842d365 100644 --- a/board/gumstix/duovero/duovero.c +++ b/board/gumstix/duovero/duovero.c @@ -128,7 +128,7 @@ void board_mmc_power_init(void) #define GPMC_BASEADDR_MASK 0x3F #define GPMC_CS_ENABLE 0x1 -static void enable_gpmc_net_config(const u32 *gpmc_config, struct gpmc_cs *cs, +static void enable_gpmc_net_config(const u32 *gpmc_config, const struct gpmc_cs *cs, u32 base, u32 size) { writel(0, &cs->config7); diff --git a/board/hisilicon/hikey/hikey.c b/board/hisilicon/hikey/hikey.c index 7abc67874ab..72d6334b5f6 100644 --- a/board/hisilicon/hikey/hikey.c +++ b/board/hisilicon/hikey/hikey.c @@ -93,12 +93,14 @@ U_BOOT_DEVICE(hikey_seriala) = { static struct mm_region hikey_mem_map[] = { { - .base = 0x0UL, + .virt = 0x0UL, + .phys = 0x0UL, .size = 0x80000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { - .base = 0x80000000UL, + .virt = 0x80000000UL, + .phys = 0x80000000UL, .size = 0x80000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | diff --git a/board/intel/bayleybay/acpi/mainboard.asl b/board/intel/bayleybay/acpi/mainboard.asl index 21785ea73b1..8b7ee3fba22 100644 --- a/board/intel/bayleybay/acpi/mainboard.asl +++ b/board/intel/bayleybay/acpi/mainboard.asl @@ -9,3 +9,41 @@ Device (PWRB) { Name(_HID, EISAID("PNP0C0C")) } + +/* PS/2 keyboard and mouse */ +Scope (\_SB.PCI0.LPCB) +{ + /* 8042 Keyboard */ + Device (PS2K) + { + Name(_HID, EISAID("PNP0303")) + Name(_CRS, ResourceTemplate() + { + IO(Decode16, 0x60, 0x60, 0x00, 0x01) + IO(Decode16, 0x64, 0x64, 0x00, 0x01) + IRQNoFlags() { 1 } + }) + + Method(_STA, 0, Serialized) + { + Return (STA_VISIBLE) + } + } + + /* 8042 Mouse */ + Device (PS2M) + { + Name(_HID, EISAID("PNP0F03")) + Name(_CRS, ResourceTemplate() + { + IO(Decode16, 0x60, 0x60, 0x00, 0x01) + IO(Decode16, 0x64, 0x64, 0x00, 0x01) + IRQNoFlags() { 12 } + }) + + Method(_STA, 0, Serialized) + { + Return (STA_VISIBLE) + } + } +} diff --git a/board/inversepath/usbarmory/usbarmory.c b/board/inversepath/usbarmory/usbarmory.c index a809039ac58..c875e786a49 100644 --- a/board/inversepath/usbarmory/usbarmory.c +++ b/board/inversepath/usbarmory/usbarmory.c @@ -415,3 +415,34 @@ int checkboard(void) puts("Board: Inverse Path USB armory MkI\n"); return 0; } + +#ifndef CONFIG_CMDLINE +static char *ext2_argv[] = { + "ext2load", + "mmc", + "0:1", + USBARMORY_FIT_ADDR, + USBARMORY_FIT_PATH +}; + +static char *bootm_argv[] = { + "bootm", + USBARMORY_FIT_ADDR +}; + +int board_run_command(const char *cmdline) +{ + printf("%s %s %s %s %s\n", ext2_argv[0], ext2_argv[1], ext2_argv[2], + ext2_argv[3], ext2_argv[4]); + + if (do_ext2load(NULL, 0, 5, ext2_argv) != 0) { + udelay(5*1000*1000); + return 1; + } + + printf("%s %s\n", bootm_argv[0], bootm_argv[1]); + do_bootm(NULL, 0, 2, bootm_argv); + + return 1; +} +#endif diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index d1a6a6f56f0..808955e69e7 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -10,6 +10,7 @@ #include <ns16550.h> #include <twl4030.h> #include <netdev.h> +#include <spl.h> #include <asm/gpio.h> #include <asm/io.h> #include <asm/arch/mem.h> @@ -17,21 +18,32 @@ #include <asm/arch/mux.h> #include <asm/arch/sys_proto.h> #include <asm/mach-types.h> +#include <linux/mtd/mtd.h> +#include <linux/mtd/nand.h> +#include <linux/mtd/nand.h> +#include <linux/mtd/onenand.h> +#include <jffs2/load_kernel.h> #include "igep00x0.h" DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_CMD_NET) -/* GPMC definitions for LAN9221 chips */ -static const u32 gpmc_lan_config[] = { - NET_LAN9221_GPMC_CONFIG1, - NET_LAN9221_GPMC_CONFIG2, - NET_LAN9221_GPMC_CONFIG3, - NET_LAN9221_GPMC_CONFIG4, - NET_LAN9221_GPMC_CONFIG5, - NET_LAN9221_GPMC_CONFIG6, -}; +const omap3_sysinfo sysinfo = { + DDR_STACKED, +#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) + "IGEPv2", +#endif +#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030) + "IGEP COM MODULE/ELECTRON", +#endif +#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0032) + "IGEP COM PROTON", +#endif +#if defined(CONFIG_ENV_IS_IN_ONENAND) + "ONENAND", +#else + "NAND", #endif +}; static const struct ns16550_platdata igep_serial = { .base = OMAP34XX_UART3, @@ -50,7 +62,25 @@ U_BOOT_DEVICE(igep_uart) = { */ int board_init(void) { - gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + int loops = 100; + + /* find out flash memory type, assume NAND first */ + gpmc_cs0_flash = MTD_DEV_TYPE_NAND; + gpmc_init(); + + /* Issue a RESET and then READID */ + writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd); + writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd); + while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY) + != NAND_STATUS_READY) { + udelay(1); + if (--loops == 0) { + gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND; + gpmc_init(); /* reinitialize for OneNAND */ + break; + } + } + /* boot param addr */ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); @@ -63,45 +93,60 @@ int board_init(void) #ifdef CONFIG_SPL_BUILD /* - * Routine: omap_rev_string - * Description: For SPL builds output board rev - */ -void omap_rev_string(void) -{ -} - -/* * Routine: get_board_mem_timings * Description: If we use SPL then there is no x-loader nor config header * so we have to setup the DDR timings ourself on both banks. */ void get_board_mem_timings(struct board_sdrc_timings *timings) { - timings->mr = MICRON_V_MR_165; -#ifdef CONFIG_BOOT_NAND - timings->mcfg = MICRON_V_MCFG_200(256 << 20); - timings->ctrla = MICRON_V_ACTIMA_200; - timings->ctrlb = MICRON_V_ACTIMB_200; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; -#else - if (get_cpu_family() == CPU_OMAP34XX) { - timings->mcfg = NUMONYX_V_MCFG_165(256 << 20); - timings->ctrla = NUMONYX_V_ACTIMA_165; - timings->ctrlb = NUMONYX_V_ACTIMB_165; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + int mfr, id, err = identify_nand_chip(&mfr, &id); - } else { - timings->mcfg = NUMONYX_V_MCFG_200(256 << 20); - timings->ctrla = NUMONYX_V_ACTIMA_200; - timings->ctrlb = NUMONYX_V_ACTIMB_200; + timings->mr = MICRON_V_MR_165; + if (!err && mfr == NAND_MFR_MICRON) { + timings->mcfg = MICRON_V_MCFG_200(256 << 20); + timings->ctrla = MICRON_V_ACTIMA_200; + timings->ctrlb = MICRON_V_ACTIMB_200; timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + gpmc_cs0_flash = MTD_DEV_TYPE_NAND; + } else { + if (get_cpu_family() == CPU_OMAP34XX) { + timings->mcfg = NUMONYX_V_MCFG_165(256 << 20); + timings->ctrla = NUMONYX_V_ACTIMA_165; + timings->ctrlb = NUMONYX_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + } else { + timings->mcfg = NUMONYX_V_MCFG_200(256 << 20); + timings->ctrla = NUMONYX_V_ACTIMA_200; + timings->ctrlb = NUMONYX_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + } + gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND; } -#endif +} + +#ifdef CONFIG_SPL_OS_BOOT +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + if (serial_tstc() && serial_getc() == 'c') + return 1; + + return 0; } #endif +#endif -#if defined(CONFIG_CMD_NET) +int onenand_board_init(struct mtd_info *mtd) +{ + if (gpmc_cs0_flash == MTD_DEV_TYPE_ONENAND) { + struct onenand_chip *this = mtd->priv; + this->base = (void *)CONFIG_SYS_ONENAND_BASE; + return 0; + } + return 1; +} +#if defined(CONFIG_CMD_NET) static void reset_net_chip(int gpio) { if (!gpio_request(gpio, "eth nrst")) { @@ -122,6 +167,14 @@ static void reset_net_chip(int gpio) static void setup_net_chip(void) { struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; + static const u32 gpmc_lan_config[] = { + NET_LAN9221_GPMC_CONFIG1, + NET_LAN9221_GPMC_CONFIG2, + NET_LAN9221_GPMC_CONFIG3, + NET_LAN9221_GPMC_CONFIG4, + NET_LAN9221_GPMC_CONFIG5, + NET_LAN9221_GPMC_CONFIG6, + }; enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], CONFIG_SMC911X_BASE, GPMC_SIZE_16M); @@ -136,6 +189,15 @@ static void setup_net_chip(void) reset_net_chip(64); } + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_SMC911X + return smc911x_initialize(0, CONFIG_SMC911X_BASE); +#else + return 0; +#endif +} #else static inline void setup_net_chip(void) {} #endif @@ -183,6 +245,23 @@ int misc_init_r(void) return 0; } +void board_mtdparts_default(const char **mtdids, const char **mtdparts) +{ + struct mtd_info *mtd = get_mtd_device(NULL, 0); + if (mtd) { + static char ids[24]; + static char parts[48]; + const char *linux_name = "omap2-nand"; + if (strncmp(mtd->name, "onenand0", 8) == 0) + linux_name = "omap2-onenand"; + snprintf(ids, sizeof(ids), "%s=%s", mtd->name, linux_name); + snprintf(parts, sizeof(parts), "mtdparts=%s:%dk(SPL),-(UBI)", + linux_name, 4 * mtd->erasesize >> 10); + *mtdids = ids; + *mtdparts = parts; + } +} + /* * Routine: set_muxconf_regs * Description: Setting up the configuration Mux registers specific to the @@ -201,14 +280,3 @@ void set_muxconf_regs(void) MUX_IGEP0030(); #endif } - -#if defined(CONFIG_CMD_NET) -int board_eth_init(bd_t *bis) -{ -#ifdef CONFIG_SMC911X - return smc911x_initialize(0, CONFIG_SMC911X_BASE); -#else - return 0; -#endif -} -#endif diff --git a/board/isee/igep00x0/igep00x0.h b/board/isee/igep00x0/igep00x0.h index 3c7ff9b1488..5698efab5d7 100644 --- a/board/isee/igep00x0/igep00x0.h +++ b/board/isee/igep00x0/igep00x0.h @@ -7,26 +7,6 @@ #ifndef _IGEP00X0_H_ #define _IGEP00X0_H_ -const omap3_sysinfo sysinfo = { - DDR_STACKED, -#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) - "IGEPv2", -#endif -#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030) - "IGEP COM MODULE/ELECTRON", -#endif -#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0032) - "IGEP COM PROTON", -#endif -#if defined(CONFIG_ENV_IS_IN_ONENAND) - "ONENAND", -#else - "NAND", -#endif -}; - -static void setup_net_chip(void); - /* * IEN - Input Enable * IDIS - Input Disable diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c index a42f3eca33b..0829b7fa066 100644 --- a/board/keymile/common/common.c +++ b/board/keymile/common/common.c @@ -53,7 +53,7 @@ int set_km_env(void) sprintf((char *)buf, "0x%x", pnvramaddr); setenv("pnvramaddr", (char *)buf); - /* try to read rootfssize (ram image) from envrionment */ + /* try to read rootfssize (ram image) from environment */ p = getenv("rootfssize"); if (p != NULL) strict_strtoul(p, 16, &rootfssize); diff --git a/board/keymile/kmp204x/ddr.c b/board/keymile/kmp204x/ddr.c index 34ac6979bd7..77af184c82b 100644 --- a/board/keymile/kmp204x/ddr.c +++ b/board/keymile/kmp204x/ddr.c @@ -36,7 +36,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, /* we have only one module, half str should be OK */ popts->half_strength_driver_enable = 1; - /* wrlvl values overriden as recommended by ddr init func */ + /* wrlvl values overridden as recommended by ddr init func */ popts->wrlvl_override = 1; popts->wrlvl_sample = 0xf; popts->wrlvl_start = 0x6; diff --git a/board/kylin/kylin_rk3036/MAINTAINERS b/board/kylin/kylin_rk3036/MAINTAINERS deleted file mode 100644 index e69de29bb2d..00000000000 --- a/board/kylin/kylin_rk3036/MAINTAINERS +++ /dev/null diff --git a/board/logicpd/zoom1/zoom1.c b/board/logicpd/zoom1/zoom1.c index 982619cd7bc..2821ee22674 100644 --- a/board/logicpd/zoom1/zoom1.c +++ b/board/logicpd/zoom1/zoom1.c @@ -19,6 +19,7 @@ #include <ns16550.h> #include <netdev.h> #include <twl4030.h> +#include <linux/mtd/omap_gpmc.h> #include <asm/io.h> #include <asm/arch/mem.h> #include <asm/arch/mmc_host_def.h> @@ -29,10 +30,10 @@ DECLARE_GLOBAL_DATA_PTR; -/* gpmc_cfg is initialized by gpmc_init and we use it here */ -extern struct gpmc *gpmc_cfg; - -/* GPMC definitions for Ethenet Controller LAN9211 */ +/* + * gpmc_cfg is initialized by gpmc_init and we use it here. + * GPMC definitions for Ethenet Controller LAN9211 + */ static const u32 gpmc_lab_enet[] = { ZOOM1_ENET_GPMC_CONF1, ZOOM1_ENET_GPMC_CONF2, diff --git a/board/micronas/vct/ebi_onenand.c b/board/micronas/vct/ebi_onenand.c index 62eb6489be2..ef892cae15b 100644 --- a/board/micronas/vct/ebi_onenand.c +++ b/board/micronas/vct/ebi_onenand.c @@ -169,7 +169,7 @@ static int ebi_write_bufferram(struct mtd_info *mtd, loff_t addr, int area, return 0; } -void onenand_board_init(struct mtd_info *mtd) +int onenand_board_init(struct mtd_info *mtd) { struct onenand_chip *chip = mtd->priv; @@ -181,4 +181,6 @@ void onenand_board_init(struct mtd_info *mtd) chip->read_bufferram = ebi_read_bufferram; chip->write_bufferram = ebi_write_bufferram; + + return 0; } diff --git a/board/nvidia/p2371-2180/p2371-2180.c b/board/nvidia/p2371-2180/p2371-2180.c index 0f587eaaa79..dbdc1b65e68 100644 --- a/board/nvidia/p2371-2180/p2371-2180.c +++ b/board/nvidia/p2371-2180/p2371-2180.c @@ -30,6 +30,28 @@ void pin_mux_mmc(void) ret = dm_i2c_write(dev, MAX77620_CNFG1_L2_REG, &val, 1); if (ret) printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret); + + /* Disable LDO4 discharge */ + ret = dm_i2c_read(dev, MAX77620_CNFG2_L4_REG, &val, 1); + if (ret) { + printf("i2c_read 0 0x3c 0x2c failed: %d\n", ret); + } else { + val &= ~BIT(1); /* ADE */ + ret = dm_i2c_write(dev, MAX77620_CNFG2_L4_REG, &val, 1); + if (ret) + printf("i2c_write 0 0x3c 0x2c failed: %d\n", ret); + } + + /* Set MBLPD */ + ret = dm_i2c_read(dev, MAX77620_CNFGGLBL1_REG, &val, 1); + if (ret) { + printf("i2c_write 0 0x3c 0x00 failed: %d\n", ret); + } else { + val |= BIT(6); /* MBLPD */ + ret = dm_i2c_write(dev, MAX77620_CNFGGLBL1_REG, &val, 1); + if (ret) + printf("i2c_write 0 0x3c 0x00 failed: %d\n", ret); + } } /* diff --git a/board/nvidia/p2571/max77620_init.h b/board/nvidia/p2571/max77620_init.h index 92c3719112a..39e550149aa 100644 --- a/board/nvidia/p2571/max77620_init.h +++ b/board/nvidia/p2571/max77620_init.h @@ -13,6 +13,8 @@ #define MAX77620_I2C_ADDR 0x78 #define MAX77620_I2C_ADDR_7BIT 0x3C +#define MAX77620_CNFGGLBL1_REG 0x00 + #define MAX77620_SD0_REG 0x16 #define MAX77620_SD1_REG 0x17 #define MAX77620_SD2_REG 0x18 diff --git a/board/nvidia/p2771-0000/p2771-0000.c b/board/nvidia/p2771-0000/p2771-0000.c index 4ba8ebc0dce..529ed9d4547 100644 --- a/board/nvidia/p2771-0000/p2771-0000.c +++ b/board/nvidia/p2771-0000/p2771-0000.c @@ -5,3 +5,51 @@ */ #include <common.h> +#include <i2c.h> +#include "../p2571/max77620_init.h" + +int tegra_board_init(void) +{ + struct udevice *dev; + uchar val; + int ret; + + /* Turn on MAX77620 LDO3 to 3.3V for SD card power */ + debug("%s: Set LDO3 for VDDIO_SDMMC_AP power to 3.3V\n", __func__); + ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev); + if (ret) { + printf("%s: Cannot find MAX77620 I2C chip\n", __func__); + return ret; + } + /* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ + val = 0xF2; + ret = dm_i2c_write(dev, MAX77620_CNFG1_L3_REG, &val, 1); + if (ret) { + printf("i2c_write 0 0x3c 0x27 failed: %d\n", ret); + return ret; + } + + return 0; +} + +int tegra_pcie_board_init(void) +{ + struct udevice *dev; + uchar val; + int ret; + + /* Turn on MAX77620 LDO7 to 1.05V for PEX power */ + debug("%s: Set LDO7 for PEX power to 1.05V\n", __func__); + ret = i2c_get_chip_for_busnum(0, MAX77620_I2C_ADDR_7BIT, 1, &dev); + if (ret) { + printf("%s: Cannot find MAX77620 I2C chip\n", __func__); + return -1; + } + /* 0xC5 for 1.05v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */ + val = 0xC5; + ret = dm_i2c_write(dev, MAX77620_CNFG1_L7_REG, &val, 1); + if (ret) + printf("i2c_write 0 0x3c 0x31 failed: %d\n", ret); + + return 0; +} diff --git a/board/nvidia/venice2/as3722_init.c b/board/nvidia/venice2/as3722_init.c index 960fea7ee7e..1770ec2468d 100644 --- a/board/nvidia/venice2/as3722_init.c +++ b/board/nvidia/venice2/as3722_init.c @@ -32,7 +32,18 @@ void pmic_enable_cpu_vdd(void) { debug("%s entry\n", __func__); - /* Don't need to set up VDD_CORE - already done - by OTP */ +#ifdef AS3722_SD1VOLTAGE_DATA + /* Set up VDD_CORE, for boards where OTP is incorrect*/ + debug("%s: Setting VDD_CORE via AS3722 reg 1\n", __func__); + /* Configure VDD_CORE via the AS3722 PMIC on the PWR I2C bus */ + tegra_i2c_ll_write_addr(AS3722_I2C_ADDR, 2); + tegra_i2c_ll_write_data(AS3722_SD1VOLTAGE_DATA, I2C_SEND_2_BYTES); + /* + * Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled. + * tegra_i2c_ll_write_data(AS3722_SD1CONTROL_DATA, I2C_SEND_2_BYTES); + */ + udelay(10 * 1000); +#endif debug("%s: Setting VDD_CPU to 1.0V via AS3722 reg 0/4D\n", __func__); /* diff --git a/board/nvidia/venice2/as3722_init.h b/board/nvidia/venice2/as3722_init.h index 992b11f6435..c6b1247149e 100644 --- a/board/nvidia/venice2/as3722_init.h +++ b/board/nvidia/venice2/as3722_init.h @@ -25,8 +25,10 @@ #endif #define AS3722_SD0CONTROL_DATA (0x0100 | AS3722_SDCONTROL_REG) -#define AS3722_SD1VOLTAGE_DATA (0x3200 | AS3722_SD1VOLTAGE_REG) +#ifdef CONFIG_TARGET_JETSON_TK1 +#define AS3722_SD1VOLTAGE_DATA (0x2800 | AS3722_SD1VOLTAGE_REG) #define AS3722_SD1CONTROL_DATA (0x0200 | AS3722_SDCONTROL_REG) +#endif #define AS3722_SD6CONTROL_DATA (0x4000 | AS3722_SDCONTROL_REG) #define AS3722_SD6VOLTAGE_DATA (0x2800 | AS3722_SD6VOLTAGE_REG) diff --git a/board/phytec/pcm058/Kconfig b/board/phytec/pcm058/Kconfig new file mode 100644 index 00000000000..d099275d48e --- /dev/null +++ b/board/phytec/pcm058/Kconfig @@ -0,0 +1,12 @@ +if TARGET_PCM058 + +config SYS_BOARD + default "pcm058" + +config SYS_VENDOR + default "phytec" + +config SYS_CONFIG_NAME + default "pcm058" + +endif diff --git a/board/phytec/pcm058/MAINTAINERS b/board/phytec/pcm058/MAINTAINERS new file mode 100644 index 00000000000..b0ca40277f0 --- /dev/null +++ b/board/phytec/pcm058/MAINTAINERS @@ -0,0 +1,6 @@ +PHYTEC PHYBOARD MIRA +M: Stefano Babic <sbabic@denx.de> +S: Maintained +F: board/phytec/pcm058/ +F: include/configs/pcm058.h +F: configs/pcm058_defconfig diff --git a/board/phytec/pcm058/Makefile b/board/phytec/pcm058/Makefile new file mode 100644 index 00000000000..97733b110cd --- /dev/null +++ b/board/phytec/pcm058/Makefile @@ -0,0 +1,9 @@ +# +# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de> +# +# (C) Copyright 2011 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := pcm058.o diff --git a/board/phytec/pcm058/README b/board/phytec/pcm058/README new file mode 100644 index 00000000000..33271356451 --- /dev/null +++ b/board/phytec/pcm058/README @@ -0,0 +1,35 @@ +Board information +----------------- + +The SBC produced by Phytec has a SOM based on a i.MX6Q. +The SOM is sold in two versions, with eMMC or with NAND. Support +here is for the SOM with NAND. +The evaluation board "phyBoard-Mira" is thought to be used +together with the SOM. + +More information on the board can be found on manufacturer's +website: + +http://www.phytec.de/produkt/single-board-computer/phyboard-mira/ +http://www.phytec.de/fileadmin/user_upload/images/content/1.Products/SOMs/phyCORE-i.MX6/L-808e_1.pdf + +Building U-Boot +------------------------------- + +$ make pcm058_defconfig +$ make + +This generates the artifacts SPL and u-boot.img. +The SOM can boot from NAND or from SD-Card, having the SPI-NOR +as second option. +The dip switch "DIP-1" on the board let choose between +NAND and SD. + +DIP-1 set to off: Boot first from NAND, then try SPI +DIP-1 set to on: Boot first from SD, then try SPI + +The bootloader was tested with DIP-1 set to on. If a SD-card +is present, then the RBL tries to load SPL from the SD Card, if not, +RBL loads from SPI-NOR. The SPL tries then to load from the same +device where SPL was loaded (SD or SPI). Booting from NAND is +not supported. diff --git a/board/phytec/pcm058/pcm058.c b/board/phytec/pcm058/pcm058.c new file mode 100644 index 00000000000..0ba4a2e2680 --- /dev/null +++ b/board/phytec/pcm058/pcm058.c @@ -0,0 +1,582 @@ +/* + * Copyright (C) 2016 Stefano Babic <sbabic@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Please note: there are two version of the board + * one with NAND and the other with eMMC. + * Both NAND and eMMC cannot be set because they share the + * same pins (SD4) + */ +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/mx6-ddr.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/boot_mode.h> +#include <asm/imx-common/mxc_i2c.h> +#include <asm/imx-common/spi.h> +#include <asm/errno.h> +#include <asm/gpio.h> +#include <mmc.h> +#include <i2c.h> +#include <fsl_esdhc.h> +#include <nand.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/arch/sys_proto.h> +#include <asm/sections.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL) + +#define ASRC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define NAND_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 14) +#define USDHC1_CD_GPIO IMX_GPIO_NR(6, 31) +#define USER_LED IMX_GPIO_NR(1, 4) +#define IMX6Q_DRIVE_STRENGTH 0x30 + +int dram_init(void) +{ + gd->ram_size = imx_ddr_size(); + return 0; +} + +void board_turn_off_led(void) +{ + gpio_direction_output(USER_LED, 0); +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const enet_pads[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_SD2_DAT1__GPIO1_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const ecspi1_pads[] = { + MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +/* NAND */ +static iomux_v3_cfg_t const nfc_pads[] = { + MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NAND_PAD_CTRL), +}; + + +/* GPIOS */ +static iomux_v3_cfg_t const gpios_pads[] = { +}; + +static struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | I2C_PAD, + .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | I2C_PAD, + .gp = IMX_GPIO_NR(1, 5) + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD, + .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD, + .gp = IMX_GPIO_NR(1, 6) + } +}; + +static struct fsl_esdhc_cfg usdhc_cfg[] = { + {.esdhc_base = USDHC1_BASE_ADDR, + .max_bus_width = 4}, +#ifndef CONFIG_CMD_NAND + {USDHC4_BASE_ADDR}, +#endif +}; + +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +}; + +#ifndef CONFIG_CMD_NAND +static iomux_v3_cfg_t const usdhc4_pads[] = { + MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; +#endif + +int board_mmc_get_env_dev(int devno) +{ + return devno - 1; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + case USDHC4_BASE_ADDR: + ret = 1; /* eMMC/uSDHC4 is always present */ + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ +#ifndef CONFIG_SPL_BUILD + int ret; + int i; + + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + gpio_direction_input(USDHC1_CD_GPIO); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; +#ifndef CONFIG_CMD_NAND + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + break; +#endif + default: + printf("Warning: you configured more USDHC controllers" + "(%d) then supported by the board (%d)\n", + i + 1, CONFIG_SYS_FSL_USDHC_NUM); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; +#else + struct src *psrc = (struct src *)SRC_BASE_ADDR; + unsigned reg = readl(&psrc->sbmr1) >> 11; + /* + * Upon reading BOOT_CFG register the following map is done: + * Bit 11 and 12 of BOOT_CFG register can determine the current + * mmc port + * 0x1 SD1 + * 0x2 SD2 + * 0x3 SD4 + */ + + switch (reg & 0x3) { + case 0x0: + imx_iomux_v3_setup_multiple_pads( + usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + gpio_direction_input(USDHC1_CD_GPIO); + usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + usdhc_cfg[0].max_bus_width = 4; + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + break; + } + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +#endif +} + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +static void setup_iomux_enet(void) +{ + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); + + gpio_direction_output(ENET_PHY_RESET_GPIO, 0); + mdelay(10); + gpio_set_value(ENET_PHY_RESET_GPIO, 1); + mdelay(30); +} + +static void setup_spi(void) +{ + gpio_request(IMX_GPIO_NR(3, 19), "spi_cs0"); + gpio_direction_output(IMX_GPIO_NR(3, 19), 1); + + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); + + enable_spi_clk(true, 0); +} + +#ifdef CONFIG_CMD_NAND +static void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads)); + + /* gate ENFC_CLK_ROOT clock first,before clk source switch */ + clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); + + /* config gpmi and bch clock to 100 MHz */ + clrsetbits_le32(&mxc_ccm->cs2cdr, + MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, + MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | + MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | + MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); + + /* enable ENFC_CLK_ROOT clock */ + setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); + + /* enable gpmi and bch clock gating */ + setbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} +#endif + +int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + if (bus != 0 || (cs != 0)) + return -EINVAL; + + return IMX_GPIO_NR(3, 19); +} + +int board_eth_init(bd_t *bis) +{ + setup_iomux_enet(); + + return cpu_eth_init(bis); +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_SYS_I2C_MXC + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); +#endif + +#ifdef CONFIG_MXC_SPI + setup_spi(); +#endif + +#ifdef CONFIG_CMD_NAND + setup_gpmi_nand(); +#endif + return 0; +} + + +#ifdef CONFIG_CMD_BMODE +/* + * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4 + * see Table 8-11 and Table 5-9 + * BOOT_CFG1[7] = 1 (boot from NAND) + * BOOT_CFG1[5] = 0 - raw NAND + * BOOT_CFG1[4] = 0 - default pad settings + * BOOT_CFG1[3:2] = 00 - devices = 1 + * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3 + * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2 + * BOOT_CFG2[2:1] = 01 - Pages In Block = 64 + * BOOT_CFG2[0] = 0 - Reset time 12ms + */ +static const struct boot_mode board_boot_modes[] = { + /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */ + {"nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00)}, + {"mmc0", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + + return 0; +} + +#ifdef CONFIG_SPL_BUILD +#include <spl.h> +#include <libfdt.h> + +static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_sdclk_0 = 0x00000030, + .dram_sdclk_1 = 0x00000030, + .dram_cas = 0x00000030, + .dram_ras = 0x00000030, + .dram_reset = 0x00000030, + .dram_sdcke0 = 0x00000030, + .dram_sdcke1 = 0x00000030, + .dram_sdba2 = 0x00000000, + .dram_sdodt0 = 0x00000030, + .dram_sdodt1 = 0x00000030, + .dram_sdqs0 = 0x00000030, + .dram_sdqs1 = 0x00000030, + .dram_sdqs2 = 0x00000030, + .dram_sdqs3 = 0x00000030, + .dram_sdqs4 = 0x00000030, + .dram_sdqs5 = 0x00000030, + .dram_sdqs6 = 0x00000030, + .dram_sdqs7 = 0x00000030, + .dram_dqm0 = 0x00000030, + .dram_dqm1 = 0x00000030, + .dram_dqm2 = 0x00000030, + .dram_dqm3 = 0x00000030, + .dram_dqm4 = 0x00000030, + .dram_dqm5 = 0x00000030, + .dram_dqm6 = 0x00000030, + .dram_dqm7 = 0x00000030, +}; + +static const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = { + .grp_ddr_type = 0x000C0000, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, + .grp_addds = IMX6Q_DRIVE_STRENGTH, + .grp_ctlds = IMX6Q_DRIVE_STRENGTH, + .grp_ddrmode = 0x00020000, + .grp_b0ds = IMX6Q_DRIVE_STRENGTH, + .grp_b1ds = IMX6Q_DRIVE_STRENGTH, + .grp_b2ds = IMX6Q_DRIVE_STRENGTH, + .grp_b3ds = IMX6Q_DRIVE_STRENGTH, + .grp_b4ds = IMX6Q_DRIVE_STRENGTH, + .grp_b5ds = IMX6Q_DRIVE_STRENGTH, + .grp_b6ds = IMX6Q_DRIVE_STRENGTH, + .grp_b7ds = IMX6Q_DRIVE_STRENGTH, +}; + +static const struct mx6_mmdc_calibration mx6_mmcd_calib = { + .p0_mpwldectrl0 = 0x00140014, + .p0_mpwldectrl1 = 0x000A0015, + .p1_mpwldectrl0 = 0x000A001E, + .p1_mpwldectrl1 = 0x000A0015, + .p0_mpdgctrl0 = 0x43080314, + .p0_mpdgctrl1 = 0x02680300, + .p1_mpdgctrl0 = 0x430C0318, + .p1_mpdgctrl1 = 0x03000254, + .p0_mprddlctl = 0x3A323234, + .p1_mprddlctl = 0x3E3C3242, + .p0_mpwrdlctl = 0x2A2E3632, + .p1_mpwrdlctl = 0x3C323E34, +}; + +static struct mx6_ddr3_cfg mem_ddr = { + .mem_speed = 1600, + .density = 2, + .width = 16, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, + .SRT = 1, +}; + +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0x00C03F3F, &ccm->CCGR0); + writel(0x0030FC03, &ccm->CCGR1); + writel(0x0FFFC000, &ccm->CCGR2); + writel(0x3FF00000, &ccm->CCGR3); + writel(0x00FFF300, &ccm->CCGR4); + writel(0x0F0000C3, &ccm->CCGR5); + writel(0x000003FF, &ccm->CCGR6); +} + +static void gpr_init(void) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* enable AXI cache for VDOA/VPU/IPU */ + writel(0xF00000CF, &iomux->gpr[4]); + /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ + writel(0x007F007F, &iomux->gpr[6]); + writel(0x007F007F, &iomux->gpr[7]); +} + + +static void spl_dram_init(void) +{ + struct mx6_ddr_sysinfo sysinfo = { + /* width of data bus:0=16,1=32,2=64 */ + .dsize = 2, + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, /* 32Gb per CS */ + /* single chip select */ + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ + .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + .ddr_type = DDR_TYPE_DDR3, + }; + + mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs); + mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); +} + +void board_boot_order(u32 *spl_boot_list) +{ + spl_boot_list[0] = spl_boot_device(); + printf("Boot device %x\n", spl_boot_list[0]); + switch (spl_boot_list[0]) { + case BOOT_DEVICE_SPI: + spl_boot_list[1] = BOOT_DEVICE_UART; + break; + case BOOT_DEVICE_MMC1: + spl_boot_list[1] = BOOT_DEVICE_SPI; + spl_boot_list[2] = BOOT_DEVICE_UART; + break; + default: + printf("Boot device %x\n", spl_boot_list[0]); + } +} + +void board_init_f(ulong dummy) +{ +#ifdef CONFIG_CMD_NAND + /* Enable NAND */ + setup_gpmi_nand(); +#endif + + /* setup clock gating */ + ccgr_init(); + + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + /* setup AXI */ + gpr_init(); + + board_early_init_f(); + + /* setup GP timer */ + timer_init(); + + setup_spi(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} +#endif diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index c45ddb14aa3..fbfbf6cbbc6 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -234,12 +234,14 @@ static const struct rpi_model *model; #ifdef CONFIG_ARM64 static struct mm_region bcm2837_mem_map[] = { { - .base = 0x00000000UL, + .virt = 0x00000000UL, + .phys = 0x00000000UL, .size = 0x3f000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { - .base = 0x3f000000UL, + .virt = 0x3f000000UL, + .phys = 0x3f000000UL, .size = 0x01000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | diff --git a/board/evb_rk3036/evb_rk3036/Kconfig b/board/rockchip/evb_rk3036/Kconfig index ae2a9ebe479..ef45f629252 100644 --- a/board/evb_rk3036/evb_rk3036/Kconfig +++ b/board/rockchip/evb_rk3036/Kconfig @@ -4,7 +4,7 @@ config SYS_BOARD default "evb_rk3036" config SYS_VENDOR - default "evb_rk3036" + default "rockchip" config SYS_CONFIG_NAME default "evb_rk3036" diff --git a/board/rockchip/evb_rk3036/MAINTAINERS b/board/rockchip/evb_rk3036/MAINTAINERS new file mode 100644 index 00000000000..91f8a839cd4 --- /dev/null +++ b/board/rockchip/evb_rk3036/MAINTAINERS @@ -0,0 +1,6 @@ +EVB-RK3036 +M: huang lin <hl@rock-chips.com> +S: Maintained +F: board/rockchip/evb_rk3036 +F: include/configs/evb_rk3036.h +F: configs/evb-rk3036_defconfig diff --git a/board/evb_rk3036/evb_rk3036/Makefile b/board/rockchip/evb_rk3036/Makefile index 0403836e131..0403836e131 100644 --- a/board/evb_rk3036/evb_rk3036/Makefile +++ b/board/rockchip/evb_rk3036/Makefile diff --git a/board/rockchip/evb_rk3036/evb_rk3036.c b/board/rockchip/evb_rk3036/evb_rk3036.c new file mode 100644 index 00000000000..e5582b47d9f --- /dev/null +++ b/board/rockchip/evb_rk3036/evb_rk3036.c @@ -0,0 +1,95 @@ +/* + * (C) Copyright 2015 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <asm/io.h> +#include <asm/arch/uart.h> +#include <asm/arch/sdram_rk3036.h> + +DECLARE_GLOBAL_DATA_PTR; + +void get_ddr_config(struct rk3036_ddr_config *config) +{ + /* K4B4G1646Q config */ + config->ddr_type = 3; + config->rank = 2; + config->cs0_row = 15; + config->cs1_row = 15; + + /* 8bank */ + config->bank = 3; + config->col = 10; + + /* 16bit bw */ + config->bw = 1; +} + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = sdram_size(); + + return 0; +} + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif + +#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) +#include <usb.h> +#include <usb/dwc2_udc.h> + +static struct dwc2_plat_otg_data rk3036_otg_data = { + .rx_fifo_sz = 512, + .np_tx_fifo_sz = 16, + .tx_fifo_sz = 128, +}; + +int board_usb_init(int index, enum usb_init_type init) +{ + int node; + const char *mode; + bool matched = false; + const void *blob = gd->fdt_blob; + + /* find the usb_otg node */ + node = fdt_node_offset_by_compatible(blob, -1, + "rockchip,rk3288-usb"); + + while (node > 0) { + mode = fdt_getprop(blob, node, "dr_mode", NULL); + if (mode && strcmp(mode, "otg") == 0) { + matched = true; + break; + } + + node = fdt_node_offset_by_compatible(blob, node, + "rockchip,rk3288-usb"); + } + if (!matched) { + debug("Not found usb_otg device\n"); + return -ENODEV; + } + rk3036_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg"); + + return dwc2_udc_probe(&rk3036_otg_data); +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + return 0; +} +#endif diff --git a/board/rockchip/evb_rk3288/Kconfig b/board/rockchip/evb_rk3288/Kconfig new file mode 100644 index 00000000000..8ab07f41fa6 --- /dev/null +++ b/board/rockchip/evb_rk3288/Kconfig @@ -0,0 +1,15 @@ +if TARGET_EVB_RK3288 + +config SYS_BOARD + default "evb_rk3288" + +config SYS_VENDOR + default "rockchip" + +config SYS_CONFIG_NAME + default "evb_rk3288" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/rockchip/evb_rk3288/MAINTAINERS b/board/rockchip/evb_rk3288/MAINTAINERS new file mode 100644 index 00000000000..8a4f127f886 --- /dev/null +++ b/board/rockchip/evb_rk3288/MAINTAINERS @@ -0,0 +1,6 @@ +EVB-RK3288 +M: Lin Huang <hl@rock-chips.com> +S: Maintained +F: board/rockchip/evb_rk3288 +F: include/configs/evb_rk3288.h +F: configs/evb-rk3288_defconfig diff --git a/board/rockchip/evb_rk3288/Makefile b/board/rockchip/evb_rk3288/Makefile new file mode 100644 index 00000000000..c11b657601a --- /dev/null +++ b/board/rockchip/evb_rk3288/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2016 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += evb-rk3288.o diff --git a/board/rockchip/evb_rk3288/evb-rk3288.c b/board/rockchip/evb_rk3288/evb-rk3288.c new file mode 100644 index 00000000000..a82f0ae283b --- /dev/null +++ b/board/rockchip/evb_rk3288/evb-rk3288.c @@ -0,0 +1,15 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spl.h> + +void board_boot_order(u32 *spl_boot_list) +{ + /* eMMC prior to sdcard. */ + spl_boot_list[0] = BOOT_DEVICE_MMC2; + spl_boot_list[1] = BOOT_DEVICE_MMC1; +} diff --git a/board/rockchip/evb_rk3399/Kconfig b/board/rockchip/evb_rk3399/Kconfig new file mode 100644 index 00000000000..412b81cbee9 --- /dev/null +++ b/board/rockchip/evb_rk3399/Kconfig @@ -0,0 +1,15 @@ +if TARGET_EVB_RK3399 + +config SYS_BOARD + default "evb_rk3399" + +config SYS_VENDOR + default "rockchip" + +config SYS_CONFIG_NAME + default "evb_rk3399" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/evb_rk3036/evb_rk3036/MAINTAINERS b/board/rockchip/evb_rk3399/MAINTAINERS index e69de29bb2d..e69de29bb2d 100644 --- a/board/evb_rk3036/evb_rk3036/MAINTAINERS +++ b/board/rockchip/evb_rk3399/MAINTAINERS diff --git a/board/rockchip/evb_rk3399/Makefile b/board/rockchip/evb_rk3399/Makefile new file mode 100644 index 00000000000..aaa51c212e5 --- /dev/null +++ b/board/rockchip/evb_rk3399/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2016 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += evb-rk3399.o diff --git a/board/rockchip/evb_rk3399/README b/board/rockchip/evb_rk3399/README new file mode 100644 index 00000000000..fb8bb197634 --- /dev/null +++ b/board/rockchip/evb_rk3399/README @@ -0,0 +1,73 @@ +Introduction +============ + +RK3399 key features we might use in U-Boot: +* CPU: ARMv8 64bit Big-Little architecture, +* Big: dual-core Cortex-A72 +* Little: quad-core Cortex-A53 +* IRAM: 200KB +* DRAM: 4GB-128MB dual-channel +* eMMC: support eMMC 5.0/5.1, suport HS400, HS200, DDR50 +* SD/MMC: support SD 3.0, MMC 4.51 +* USB: USB3.0 typc-C port *2 with dwc3 controller +* USB2.0 EHCI host port *2 +* Display: RGB/HDMI/DP/MIPI/EDP + +evb key features: +* regulator: pwm regulator for CPU B/L +* PMIC: rk808 +* debug console: UART2 + +In order to support Arm Trust Firmware(ATF), we need to use the +miniloader from rockchip which: +* do DRAM init +* load and verify ATF image +* load and verify U-Boot image + +Here is the step-by-step to boot to U-Boot on rk3399. + +Get the Source and prebuild binary +================================== + + > mkdir ~/evb_rk3399 + > cd ~/evb_rk3399 + > git clone https://github.com/ARM-software/arm-trusted-firmware.git + > git clone https://github.com/rockchip-linux/rkbin + > git clone https://github.com/rockchip-linux/rkflashtool + +Compile the ATF +=============== + + > cd arm-trusted-firmware + > make realclean + > make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 bl31 + +Compile the U-Boot +================== + + > cd ../u-boot + > make CROSS_COMPILE=aarch64-linux-gnu- evb-rk3399_defconfig all + +Compile the rkflashtool +======================= + + > cd ../rkflashtool + > make + +Package the image for miniloader +================================ + > cd .. + > cp arm-trusted-firmware/build/rk3399/release/bl31.bin rkbin/rk33 + > ./rkbin/tools/trust_merger rkbin/tools/RK3399TRUST.ini + > ./rkbin/tools/loaderimage --pack --uboot u-boot/u-boot-dtb.bin uboot.img + > mkdir image + > mv trust.img ./image/ + > mv uboot.img ./image/rk3399evb-uboot.bin + +Flash the image +=============== +Power on(or reset with RESET KEY) with MASKROM KEY preesed, and then: + + > ./rkflashtool/rkflashloader rk3399evb + +You should be able to get U-Boot log message in console/UART2 now. diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c b/board/rockchip/evb_rk3399/evb-rk3399.c new file mode 100644 index 00000000000..cb2d97dfb92 --- /dev/null +++ b/board/rockchip/evb_rk3399/evb-rk3399.c @@ -0,0 +1,27 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <asm/armv8/mmu.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = 0x80000000; + return 0; +} + +void dram_init_banksize(void) +{ + /* Reserve 0x200000 for ATF bl31 */ + gd->bd->bi_dram[0].start = 0x200000; + gd->bd->bi_dram[0].size = 0x80000000; +} diff --git a/board/rockchip/fennec_rk3288/Kconfig b/board/rockchip/fennec_rk3288/Kconfig new file mode 100644 index 00000000000..1dcfcf0317d --- /dev/null +++ b/board/rockchip/fennec_rk3288/Kconfig @@ -0,0 +1,15 @@ +if TARGET_FENNEC_RK3288 + +config SYS_BOARD + default "fennec_rk3288" + +config SYS_VENDOR + default "rockchip" + +config SYS_CONFIG_NAME + default "fennec_rk3288" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/rockchip/fennec_rk3288/MAINTAINERS b/board/rockchip/fennec_rk3288/MAINTAINERS new file mode 100644 index 00000000000..78a389b0605 --- /dev/null +++ b/board/rockchip/fennec_rk3288/MAINTAINERS @@ -0,0 +1,6 @@ +FENNEC-RK3288 +M: Lin Huang <hl@rock-chips.com> +S: Maintained +F: board/rockchip/fennec_rk3288 +F: include/configs/fennec_rk3288.h +F: configs/fennec-rk3288_defconfig diff --git a/board/rockchip/fennec_rk3288/Makefile b/board/rockchip/fennec_rk3288/Makefile new file mode 100644 index 00000000000..b287db699e0 --- /dev/null +++ b/board/rockchip/fennec_rk3288/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2016 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += fennec-rk3288.o diff --git a/board/rockchip/fennec_rk3288/fennec-rk3288.c b/board/rockchip/fennec_rk3288/fennec-rk3288.c new file mode 100644 index 00000000000..aad74ef1095 --- /dev/null +++ b/board/rockchip/fennec_rk3288/fennec-rk3288.c @@ -0,0 +1,15 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spl.h> + +void board_boot_order(u32 *spl_boot_list) +{ + /* eMMC prior to sdcard */ + spl_boot_list[0] = BOOT_DEVICE_MMC2; + spl_boot_list[1] = BOOT_DEVICE_MMC1; +} diff --git a/board/kylin/kylin_rk3036/Kconfig b/board/rockchip/kylin_rk3036/Kconfig index 5d75c1fc0f6..8d35b4e62bd 100644 --- a/board/kylin/kylin_rk3036/Kconfig +++ b/board/rockchip/kylin_rk3036/Kconfig @@ -4,7 +4,7 @@ config SYS_BOARD default "kylin_rk3036" config SYS_VENDOR - default "kylin" + default "rockchip" config SYS_CONFIG_NAME default "kylin_rk3036" diff --git a/board/rockchip/kylin_rk3036/MAINTAINERS b/board/rockchip/kylin_rk3036/MAINTAINERS new file mode 100644 index 00000000000..5453e7d987a --- /dev/null +++ b/board/rockchip/kylin_rk3036/MAINTAINERS @@ -0,0 +1,6 @@ +KYLIN-RK3036 +M: huang lin <hl@rock-chips.com> +S: Maintained +F: board/rockchip/kylin_rk3036 +F: include/configs/kylin_rk3036.h +F: configs/kylin-rk3036_defconfig diff --git a/board/kylin/kylin_rk3036/Makefile b/board/rockchip/kylin_rk3036/Makefile index 0663270506c..0663270506c 100644 --- a/board/kylin/kylin_rk3036/Makefile +++ b/board/rockchip/kylin_rk3036/Makefile diff --git a/board/kylin/kylin_rk3036/kylin_rk3036.c b/board/rockchip/kylin_rk3036/kylin_rk3036.c index 2a258710ac5..5ade6956165 100644 --- a/board/kylin/kylin_rk3036/kylin_rk3036.c +++ b/board/rockchip/kylin_rk3036/kylin_rk3036.c @@ -79,3 +79,49 @@ void enable_caches(void) dcache_enable(); } #endif + +#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) +#include <usb.h> +#include <usb/dwc2_udc.h> + +static struct dwc2_plat_otg_data rk3036_otg_data = { + .rx_fifo_sz = 512, + .np_tx_fifo_sz = 16, + .tx_fifo_sz = 128, +}; + +int board_usb_init(int index, enum usb_init_type init) +{ + int node; + const char *mode; + bool matched = false; + const void *blob = gd->fdt_blob; + + /* find the usb_otg node */ + node = fdt_node_offset_by_compatible(blob, -1, + "rockchip,rk3288-usb"); + + while (node > 0) { + mode = fdt_getprop(blob, node, "dr_mode", NULL); + if (mode && strcmp(mode, "otg") == 0) { + matched = true; + break; + } + + node = fdt_node_offset_by_compatible(blob, node, + "rockchip,rk3288-usb"); + } + if (!matched) { + debug("Not found usb_otg device\n"); + return -ENODEV; + } + rk3036_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg"); + + return dwc2_udc_probe(&rk3036_otg_data); +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + return 0; +} +#endif diff --git a/board/rockchip/miniarm_rk3288/Kconfig b/board/rockchip/miniarm_rk3288/Kconfig new file mode 100644 index 00000000000..529c09f2c8f --- /dev/null +++ b/board/rockchip/miniarm_rk3288/Kconfig @@ -0,0 +1,15 @@ +if TARGET_MINIARM_RK3288 + +config SYS_BOARD + default "miniarm_rk3288" + +config SYS_VENDOR + default "rockchip" + +config SYS_CONFIG_NAME + default "miniarm_rk3288" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/rockchip/miniarm_rk3288/MAINTAINERS b/board/rockchip/miniarm_rk3288/MAINTAINERS new file mode 100644 index 00000000000..7537b8fbf9a --- /dev/null +++ b/board/rockchip/miniarm_rk3288/MAINTAINERS @@ -0,0 +1,6 @@ +MINIARM-RK3288 +M: Lin Huang <hl@rock-chips.com> +S: Maintained +F: board/rockchip/miniarm_rk3288 +F: include/configs/miniarm_rk3288.h +F: configs/miniarm-rk3288_defconfig diff --git a/board/rockchip/miniarm_rk3288/Makefile b/board/rockchip/miniarm_rk3288/Makefile new file mode 100644 index 00000000000..9419b91ea06 --- /dev/null +++ b/board/rockchip/miniarm_rk3288/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2016 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += miniarm-rk3288.o diff --git a/board/rockchip/miniarm_rk3288/miniarm-rk3288.c b/board/rockchip/miniarm_rk3288/miniarm-rk3288.c new file mode 100644 index 00000000000..aad74ef1095 --- /dev/null +++ b/board/rockchip/miniarm_rk3288/miniarm-rk3288.c @@ -0,0 +1,15 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spl.h> + +void board_boot_order(u32 *spl_boot_list) +{ + /* eMMC prior to sdcard */ + spl_boot_list[0] = BOOT_DEVICE_MMC2; + spl_boot_list[1] = BOOT_DEVICE_MMC1; +} diff --git a/board/samsung/goni/onenand.c b/board/samsung/goni/onenand.c index b74d8e8ac9e..cbe1d12fdaa 100644 --- a/board/samsung/goni/onenand.c +++ b/board/samsung/goni/onenand.c @@ -11,11 +11,13 @@ #include <linux/mtd/samsung_onenand.h> #include <onenand_uboot.h> -void onenand_board_init(struct mtd_info *mtd) +int onenand_board_init(struct mtd_info *mtd) { struct onenand_chip *this = mtd->priv; this->base = (void *)CONFIG_SYS_ONENAND_BASE; this->options |= ONENAND_RUNTIME_BADBLOCK_CHECK; this->chip_probe = s5pc110_chip_probe; + + return 0; } diff --git a/board/samsung/smdkc100/onenand.c b/board/samsung/smdkc100/onenand.c index 577c1a546f0..994d91d999f 100644 --- a/board/samsung/smdkc100/onenand.c +++ b/board/samsung/smdkc100/onenand.c @@ -16,7 +16,7 @@ #include <asm/io.h> #include <asm/arch/clock.h> -void onenand_board_init(struct mtd_info *mtd) +int onenand_board_init(struct mtd_info *mtd) { struct onenand_chip *this = mtd->priv; struct s5pc100_clock *clk = @@ -65,4 +65,6 @@ void onenand_board_init(struct mtd_info *mtd) writel(value, &onenand->int_err_mask); s3c_onenand_init(mtd); + + return 0; } diff --git a/board/samsung/universal_c210/onenand.c b/board/samsung/universal_c210/onenand.c index 28bc8114f4a..147a95e2907 100644 --- a/board/samsung/universal_c210/onenand.c +++ b/board/samsung/universal_c210/onenand.c @@ -10,11 +10,13 @@ #include <linux/mtd/onenand.h> #include <linux/mtd/samsung_onenand.h> -void onenand_board_init(struct mtd_info *mtd) +int onenand_board_init(struct mtd_info *mtd) { struct onenand_chip *this = mtd->priv; this->base = (void *)CONFIG_SYS_ONENAND_BASE; this->options |= ONENAND_RUNTIME_BADBLOCK_CHECK; this->chip_probe = s5pc210_chip_probe; + + return 0; } diff --git a/board/sandbox/MAINTAINERS b/board/sandbox/MAINTAINERS index f5db773a478..4dcbf4ba03c 100644 --- a/board/sandbox/MAINTAINERS +++ b/board/sandbox/MAINTAINERS @@ -11,3 +11,10 @@ S: Maintained F: board/sandbox/ F: include/configs/sandbox.h F: configs/sandbox_noblk_defconfig + +SANDBOX SPL BOARD +M: Simon Glass <sjg@chromium.org> +S: Maintained +F: board/sandbox/ +F: include/configs/sandbox_spl.h +F: configs/sandbox_spl_defconfig diff --git a/board/sandbox/README.sandbox b/board/sandbox/README.sandbox index 9fe3bf171a2..ed820d338e5 100644 --- a/board/sandbox/README.sandbox +++ b/board/sandbox/README.sandbox @@ -44,6 +44,9 @@ Note: make sandbox_defconfig all NO_SDL=1 ./u-boot + If you are building on a 32-bit machine you may get errors from __ffs.h + about shifting more than the machine word size. Edit the config file + include/configs/sandbox.h and change CONFIG_SANDBOX_BITS_PER_LONG to 32. U-Boot will start on your computer, showing a sandbox emulation of the serial console: diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c index bcc9729129c..cafa3481508 100644 --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c @@ -367,14 +367,6 @@ int checkboard(void) return 0; } -static bool is_mx6q(void) -{ - if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) - return true; - else - return false; -} - int board_late_init(void) { #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG @@ -383,7 +375,7 @@ int board_late_init(void) else setenv("board_name", "CUBOXI"); - if (is_mx6q()) + if (is_mx6dq()) setenv("board_rev", "MX6Q"); else setenv("board_rev", "MX6DL"); @@ -615,7 +607,7 @@ static void spl_dram_init(int width) .ddr_type = DDR_TYPE_DDR3, }; - if (is_cpu_type(MXC_CPU_MX6D) || is_cpu_type(MXC_CPU_MX6Q)) + if (is_mx6dq()) mx6dq_dram_iocfg(width, &mx6q_ddr_ioregs, &mx6q_grp_ioregs); else mx6sdl_dram_iocfg(width, &mx6dl_ddr_ioregs, &mx6sdl_grp_ioregs); diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c index 0e04d141480..404fdfa2a71 100644 --- a/board/st/stm32f746-disco/stm32f746-disco.c +++ b/board/st/stm32f746-disco/stm32f746-disco.c @@ -10,6 +10,8 @@ #include <asm/armv7m.h> #include <asm/arch/stm32.h> #include <asm/arch/gpio.h> +#include <asm/arch/rcc.h> +#include <asm/arch/fmc.h> #include <dm/platdata.h> #include <dm/platform_data/serial_stm32x7.h> #include <asm/arch/stm32_periph.h> @@ -33,6 +35,221 @@ const struct stm32_gpio_ctl gpio_ctl_usart = { .af = STM32_GPIO_AF7 }; +const struct stm32_gpio_ctl gpio_ctl_fmc = { + .mode = STM32_GPIO_MODE_AF, + .otype = STM32_GPIO_OTYPE_PP, + .speed = STM32_GPIO_SPEED_100M, + .pupd = STM32_GPIO_PUPD_NO, + .af = STM32_GPIO_AF12 +}; + +static const struct stm32_gpio_dsc ext_ram_fmc_gpio[] = { + /* Chip is LQFP144, see DM00077036.pdf for details */ + {STM32_GPIO_PORT_D, STM32_GPIO_PIN_10}, /* 79, FMC_D15 */ + {STM32_GPIO_PORT_D, STM32_GPIO_PIN_9}, /* 78, FMC_D14 */ + {STM32_GPIO_PORT_D, STM32_GPIO_PIN_8}, /* 77, FMC_D13 */ + {STM32_GPIO_PORT_E, STM32_GPIO_PIN_15}, /* 68, FMC_D12 */ + {STM32_GPIO_PORT_E, STM32_GPIO_PIN_14}, /* 67, FMC_D11 */ + {STM32_GPIO_PORT_E, STM32_GPIO_PIN_13}, /* 66, FMC_D10 */ + {STM32_GPIO_PORT_E, STM32_GPIO_PIN_12}, /* 65, FMC_D9 */ + {STM32_GPIO_PORT_E, STM32_GPIO_PIN_11}, /* 64, FMC_D8 */ + {STM32_GPIO_PORT_E, STM32_GPIO_PIN_10}, /* 63, FMC_D7 */ + {STM32_GPIO_PORT_E, STM32_GPIO_PIN_9}, /* 60, FMC_D6 */ + {STM32_GPIO_PORT_E, STM32_GPIO_PIN_8}, /* 59, FMC_D5 */ + {STM32_GPIO_PORT_E, STM32_GPIO_PIN_7}, /* 58, FMC_D4 */ + {STM32_GPIO_PORT_D, STM32_GPIO_PIN_1}, /* 115, FMC_D3 */ + {STM32_GPIO_PORT_D, STM32_GPIO_PIN_0}, /* 114, FMC_D2 */ + {STM32_GPIO_PORT_D, STM32_GPIO_PIN_15}, /* 86, FMC_D1 */ + {STM32_GPIO_PORT_D, STM32_GPIO_PIN_14}, /* 85, FMC_D0 */ + + {STM32_GPIO_PORT_E, STM32_GPIO_PIN_1}, /* 142, FMC_NBL1 */ + {STM32_GPIO_PORT_E, STM32_GPIO_PIN_0}, /* 141, FMC_NBL0 */ + + {STM32_GPIO_PORT_G, STM32_GPIO_PIN_5}, /* 90, FMC_A15, BA1 */ + {STM32_GPIO_PORT_G, STM32_GPIO_PIN_4}, /* 89, FMC_A14, BA0 */ + + {STM32_GPIO_PORT_G, STM32_GPIO_PIN_1}, /* 57, FMC_A11 */ + {STM32_GPIO_PORT_G, STM32_GPIO_PIN_0}, /* 56, FMC_A10 */ + {STM32_GPIO_PORT_F, STM32_GPIO_PIN_15}, /* 55, FMC_A9 */ + {STM32_GPIO_PORT_F, STM32_GPIO_PIN_14}, /* 54, FMC_A8 */ + {STM32_GPIO_PORT_F, STM32_GPIO_PIN_13}, /* 53, FMC_A7 */ + {STM32_GPIO_PORT_F, STM32_GPIO_PIN_12}, /* 50, FMC_A6 */ + {STM32_GPIO_PORT_F, STM32_GPIO_PIN_5}, /* 15, FMC_A5 */ + {STM32_GPIO_PORT_F, STM32_GPIO_PIN_4}, /* 14, FMC_A4 */ + {STM32_GPIO_PORT_F, STM32_GPIO_PIN_3}, /* 13, FMC_A3 */ + {STM32_GPIO_PORT_F, STM32_GPIO_PIN_2}, /* 12, FMC_A2 */ + {STM32_GPIO_PORT_F, STM32_GPIO_PIN_1}, /* 11, FMC_A1 */ + {STM32_GPIO_PORT_F, STM32_GPIO_PIN_0}, /* 10, FMC_A0 */ + + {STM32_GPIO_PORT_H, STM32_GPIO_PIN_3}, /* 136, SDRAM_NE */ + {STM32_GPIO_PORT_F, STM32_GPIO_PIN_11}, /* 49, SDRAM_NRAS */ + {STM32_GPIO_PORT_G, STM32_GPIO_PIN_15}, /* 132, SDRAM_NCAS */ + {STM32_GPIO_PORT_H, STM32_GPIO_PIN_5}, /* 26, SDRAM_NWE */ + {STM32_GPIO_PORT_C, STM32_GPIO_PIN_3}, /* 135, SDRAM_CKE */ + + {STM32_GPIO_PORT_G, STM32_GPIO_PIN_8}, /* 93, SDRAM_CLK */ +}; + +static int fmc_setup_gpio(void) +{ + int rv = 0; + int i; + + clock_setup(GPIO_B_CLOCK_CFG); + clock_setup(GPIO_C_CLOCK_CFG); + clock_setup(GPIO_D_CLOCK_CFG); + clock_setup(GPIO_E_CLOCK_CFG); + clock_setup(GPIO_F_CLOCK_CFG); + clock_setup(GPIO_G_CLOCK_CFG); + clock_setup(GPIO_H_CLOCK_CFG); + + for (i = 0; i < ARRAY_SIZE(ext_ram_fmc_gpio); i++) { + rv = stm32_gpio_config(&ext_ram_fmc_gpio[i], + &gpio_ctl_fmc); + if (rv) + goto out; + } + +out: + return rv; +} + +/* + * STM32 RCC FMC specific definitions + */ +#define RCC_ENR_FMC (1 << 0) /* FMC module clock */ + +static inline u32 _ns2clk(u32 ns, u32 freq) +{ + u32 tmp = freq/1000000; + return (tmp * ns) / 1000; +} + +#define NS2CLK(ns) (_ns2clk(ns, freq)) + +/* + * Following are timings for IS42S16400J, from corresponding datasheet + */ +#define SDRAM_CAS 3 /* 3 cycles */ +#define SDRAM_NB 1 /* Number of banks */ +#define SDRAM_MWID 1 /* 16 bit memory */ + +#define SDRAM_NR 0x1 /* 12-bit row */ +#define SDRAM_NC 0x0 /* 8-bit col */ +#define SDRAM_RBURST 0x1 /* Single read requests always as bursts */ +#define SDRAM_RPIPE 0x0 /* No HCLK clock cycle delay */ + +#define SDRAM_TRRD NS2CLK(12) +#define SDRAM_TRCD NS2CLK(18) +#define SDRAM_TRP NS2CLK(18) +#define SDRAM_TRAS NS2CLK(42) +#define SDRAM_TRC NS2CLK(60) +#define SDRAM_TRFC NS2CLK(60) +#define SDRAM_TCDL (1 - 1) +#define SDRAM_TRDL NS2CLK(12) +#define SDRAM_TBDL (1 - 1) +#define SDRAM_TREF (NS2CLK(64000000 / 8192) - 20) +#define SDRAM_TCCD (1 - 1) + +#define SDRAM_TXSR SDRAM_TRFC /* Row cycle time after precharge */ +#define SDRAM_TMRD 1 /* Page 10, Mode Register Set */ + + +/* Last data in to row precharge, need also comply ineq on page 1648 */ +#define SDRAM_TWR max(\ + (int)max((int)SDRAM_TRDL, (int)(SDRAM_TRAS - SDRAM_TRCD)), \ + (int)(SDRAM_TRC - SDRAM_TRCD - SDRAM_TRP)\ +) + + +#define SDRAM_MODE_BL_SHIFT 0 +#define SDRAM_MODE_CAS_SHIFT 4 +#define SDRAM_MODE_BL 0 +#define SDRAM_MODE_CAS SDRAM_CAS + +int dram_init(void) +{ + u32 freq; + int rv; + + rv = fmc_setup_gpio(); + if (rv) + return rv; + + setbits_le32(RCC_BASE + RCC_AHB3ENR, RCC_ENR_FMC); + + /* + * Get frequency for NS2CLK calculation. + */ + freq = clock_get(CLOCK_AHB) / CONFIG_SYS_RAM_FREQ_DIV; + + writel( + CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT + | SDRAM_CAS << FMC_SDCR_CAS_SHIFT + | SDRAM_NB << FMC_SDCR_NB_SHIFT + | SDRAM_MWID << FMC_SDCR_MWID_SHIFT + | SDRAM_NR << FMC_SDCR_NR_SHIFT + | SDRAM_NC << FMC_SDCR_NC_SHIFT + | SDRAM_RPIPE << FMC_SDCR_RPIPE_SHIFT + | SDRAM_RBURST << FMC_SDCR_RBURST_SHIFT, + &STM32_SDRAM_FMC->sdcr1); + + writel( + SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT + | SDRAM_TRP << FMC_SDTR_TRP_SHIFT + | SDRAM_TWR << FMC_SDTR_TWR_SHIFT + | SDRAM_TRC << FMC_SDTR_TRC_SHIFT + | SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT + | SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT + | SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT, + &STM32_SDRAM_FMC->sdtr1); + + writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK, + &STM32_SDRAM_FMC->sdcmr); + + udelay(200); /* 200 us delay, page 10, "Power-Up" */ + FMC_BUSY_WAIT(); + + writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_PRECHARGE, + &STM32_SDRAM_FMC->sdcmr); + + udelay(100); + FMC_BUSY_WAIT(); + + writel((FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_AUTOREFRESH + | 7 << FMC_SDCMR_NRFS_SHIFT), &STM32_SDRAM_FMC->sdcmr); + + udelay(100); + FMC_BUSY_WAIT(); + + writel(FMC_SDCMR_BANK_1 | (SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT + | SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT) + << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE, + &STM32_SDRAM_FMC->sdcmr); + + udelay(100); + + FMC_BUSY_WAIT(); + + writel(FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_NORMAL, + &STM32_SDRAM_FMC->sdcmr); + + FMC_BUSY_WAIT(); + + /* Refresh timer */ + writel(SDRAM_TREF, &STM32_SDRAM_FMC->sdrtr); + + /* + * Fill in global info with description of SRAM configuration + */ + gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE; + gd->bd->bi_dram[0].size = CONFIG_SYS_RAM_SIZE; + + gd->ram_size = CONFIG_SYS_RAM_SIZE; + + return rv; +} + static const struct stm32_gpio_dsc usart_gpio[] = { {STM32_GPIO_PORT_A, STM32_GPIO_PIN_9}, /* TX */ {STM32_GPIO_PORT_B, STM32_GPIO_PIN_7}, /* RX */ @@ -88,12 +305,3 @@ int board_init(void) return 0; } - -int dram_init(void) -{ - gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE; - gd->bd->bi_dram[0].size = CONFIG_SYS_RAM_SIZE; - - gd->ram_size = CONFIG_SYS_RAM_SIZE; - return 0; -} diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 323e972932c..1b30669230a 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -249,7 +249,7 @@ config UART0_PORT_F Only enable this if you really know what you are doing. config OLD_SUNXI_KERNEL_COMPAT - boolean "Enable workarounds for booting old kernels" + bool "Enable workarounds for booting old kernels" default n ---help--- Set this to enable various workarounds for old kernels, this results in @@ -419,13 +419,13 @@ config I2C4_ENABLE endif config AXP_GPIO - boolean "Enable support for gpio-s on axp PMICs" + bool "Enable support for gpio-s on axp PMICs" default n ---help--- Say Y here to enable support for the gpio pins of the axp PMIC ICs. config VIDEO - boolean "Enable graphical uboot console on HDMI, LCD or VGA" + bool "Enable graphical uboot console on HDMI, LCD or VGA" depends on !MACH_SUN8I_A83T && !MACH_SUN8I_H3 && !MACH_SUN9I && !MACH_SUN50I_A64 default y ---help--- @@ -434,21 +434,21 @@ config VIDEO info on how to select the video output and mode. config VIDEO_HDMI - boolean "HDMI output support" + bool "HDMI output support" depends on VIDEO && !MACH_SUN8I default y ---help--- Say Y here to add support for outputting video over HDMI. config VIDEO_VGA - boolean "VGA output support" + bool "VGA output support" depends on VIDEO && (MACH_SUN4I || MACH_SUN7I) default n ---help--- Say Y here to add support for outputting video over VGA. config VIDEO_VGA_VIA_LCD - boolean "VGA via LCD controller support" + bool "VGA via LCD controller support" depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I) default n ---help--- @@ -457,7 +457,7 @@ config VIDEO_VGA_VIA_LCD Olimex A13 boards. config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH - boolean "Force sync active high for VGA via LCD controller support" + bool "Force sync active high for VGA via LCD controller support" depends on VIDEO_VGA_VIA_LCD default n ---help--- @@ -475,7 +475,7 @@ config VIDEO_VGA_EXTERNAL_DAC_EN format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. config VIDEO_COMPOSITE - boolean "Composite video output support" + bool "Composite video output support" depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I) default n ---help--- diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index d2dfebef46b..de719cd1f90 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -56,8 +56,10 @@ F: configs/ga10h_v1_1_defconfig F: configs/gt90h_v4_defconfig F: configs/inet86dz_defconfig F: configs/orangepi_2_defconfig +F: configs/orangepi_lite_defconfig F: configs/orangepi_one_defconfig F: configs/orangepi_pc_defconfig +F: configs/orangepi_pc_plus_defconfig F: configs/orangepi_plus_defconfig F: configs/polaroid_mid2407pxe03_defconfig F: configs/polaroid_mid2809pxe04_defconfig diff --git a/board/sunxi/README.pine64 b/board/sunxi/README.pine64 new file mode 100644 index 00000000000..55534152708 --- /dev/null +++ b/board/sunxi/README.pine64 @@ -0,0 +1,98 @@ +Pine64 board README +==================== + +The Pine64(+) is a single board computer equipped with an AArch64 capable ARMv8 +compliant Allwinner A64 SoC. +This chip has ARM Cortex A-53 cores and thus can run both in AArch32 +(compatible to 32-bit ARMv7) and AArch64 modes. Upon reset the SoC starts +in AArch32 mode and executes 32-bit code from the Boot ROM (BROM). +This has some implications on U-Boot. + +Quick start +============ +- Get hold of a boot0.img file (see below for more details). +- Get the boot0img tool source from the tools directory in [1] and compile + that on your host. +- Build U-Boot: +$ export CROSS_COMPILE=aarch64-linux-gnu- +$ make pine64_plus_defconfig +$ make +- You also need a compiled ARM Trusted Firmware (ATF) binary. Checkout the + "allwinner" branch from the github repository [2] and build it: +$ export CROSS_COMPILE=aarch64-linux-gnu- +$ make PLAT=sun50iw1p1 DEBUG=1 bl31 + The resulting binary is build/sun50iw1p1/debug/bl31.bin. + +Now put an empty (or disposable) micro SD card in your card reader and learn +its device file name, replacing /dev/sd<x> below with the result (that could +be /dev/mmcblk<x> as well): + +$ ./boot0img --device /dev/sd<x> -e -u u-boot.bin -B boot0.img \ + -d trampoline64:0x44000 -s bl31.bin -a 0x44008 -p 100 +(either copying the respective files to the working directory or specifying +the paths directly) + +This will create a new partition table (with a 100 MB FAT boot partition), +copies boot0.img, ATF and U-Boot to the proper locations on the SD card and +will fill in the magic Allwinner header to be recognized by boot0. +Prefix the above call with "sudo" if you don't have write access to the +uSD card. You can also use "-o output.img" instead of "--device /dev/sd<x>" +to create an image file and "dd" that to the uSD card. +Omitting the "-p" option will skip the partition table. + +Now put this uSD card in the board and power it on. You should be greeted by +the U-Boot prompt. + + +Main U-Boot +============ +The main U-Boot proper is a real 64-bit ARMv8 port and runs entirely in the +64-bit AArch64 mode. It can load any AArch64 code, EFI applications or arm64 +Linux kernel images (often named "Image") using the booti command. +Launching 32-bit code and kernels is technically possible, though not without +drawbacks (or hacks to avoid them) and currently not implemented. + +SPL support +============ +The main task of the SPL support is to bring up the DRAM controller and make +DRAM actually accessible. At the moment there is no documentation or source +code available which would do this. +There are currently two ways to overcome this situation: using a tainted 32-bit +SPL (involving some hacks and resulting in a non-redistributable binary, thus +not described here) or using the Allwinner boot0 blob. + +boot0 method +------------- +boot0 is Allwiner's secondary program loader and it can be used as some kind +of SPL replacement to get U-Boot up and running. +The binary is a 32 KByte blob and contained on every Pine64 image distributed +so far. It can be easily extracted from a micro SD card or an image file: +# dd if=/dev/sd<x> of=boot0.bin bs=8k skip=1 count=4 +where /dev/sd<x> is the device name of the uSD card or the name of the image +file. Apparently Allwinner allows re-distribution of this proprietary code +as-is. +For the time being this boot0 blob is the only redistributable way of making +U-Boot work on the Pine64. Beside loading the various parts of the (original) +firmware it also switches the core into AArch64 mode. +The original boot0 code looks for U-Boot at a certain place on an uSD card +(at 19096 KB), also it expects a header with magic bytes and a checksum. +There is a tool called boot0img[1] which takes a boot0.bin image and a compiled +U-Boot binary (plus other binaries) and will populate that header accordingly. +To make space for the magic header, the pine64_plus_defconfig will make sure +there is sufficient space at the beginning of the U-Boot binary. +boot0img will also take care of putting the different binaries at the right +places on the uSD card and works around unused, but mandatory parts by using +trampoline code. See the output of "boot0img -h" for more information. +boot0img can also patch boot0 to avoid loading U-Boot from 19MB, instead +fetching it from just behind the boot0 binary (-B option). + +FEL boot +========= +FEL is the name of the Allwinner defined USB boot protocol built-in the +mask ROM of most Allwinner SoCs. It allows to bootstrap a board solely +by using the USB-OTG interface and a host port on another computer. +Since FEL boot does not work with boot0, it requires the libdram hack, which +is not described here. + +[1] https://github.com/apritzel/pine64/ +[2] https://github.com/apritzel/arm-trusted-firmware.git diff --git a/board/sunxi/board.c b/board/sunxi/board.c index c8bf3169d12..209fb1cfd80 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -20,12 +20,16 @@ #include <asm/arch/dram.h> #include <asm/arch/gpio.h> #include <asm/arch/mmc.h> +#include <asm/arch/spl.h> #include <asm/arch/usb_phy.h> #ifndef CONFIG_ARM64 #include <asm/armv7.h> #endif #include <asm/gpio.h> #include <asm/io.h> +#include <crc.h> +#include <environment.h> +#include <libfdt.h> #include <nand.h> #include <net.h> #include <sy8106a.h> @@ -133,7 +137,7 @@ int dram_init(void) return 0; } -#if defined(CONFIG_NAND_SUNXI) && defined(CONFIG_SPL_BUILD) +#if defined(CONFIG_NAND_SUNXI) static void nand_pinmux_setup(void) { unsigned int pin; @@ -170,6 +174,9 @@ void board_nand_init(void) { nand_pinmux_setup(); nand_clock_setup(); +#ifndef CONFIG_SPL_BUILD + sunxi_nand_init(); +#endif } #endif @@ -366,8 +373,7 @@ int board_mmc_init(bd_t *bis) * are searched there first. Note we only do this for u-boot proper, * not for the SPL, see spl_boot_device(). */ - if (!sunxi_mmc_has_egon_boot_signature(mmc0) && - sunxi_mmc_has_egon_boot_signature(mmc1)) { + if (readb(SPL_ADDR + 0x28) == SUNXI_BOOTED_FROM_MMC2) { /* Booting from emmc / mmc2, swap */ mmc0->block_dev.devnum = 1; mmc1->block_dev.devnum = 0; @@ -571,9 +577,6 @@ void get_board_serial(struct tag_serialnr *serialnr) } #endif -#if !defined(CONFIG_SPL_BUILD) -#include <asm/arch/spl.h> - /* * Check the SPL header for the "sunxi" variant. If found: parse values * that might have been passed by the loader ("fel" utility), and update @@ -582,50 +585,88 @@ void get_board_serial(struct tag_serialnr *serialnr) static void parse_spl_header(const uint32_t spl_addr) { struct boot_file_head *spl = (void *)(ulong)spl_addr; - if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) == 0) { - uint8_t spl_header_version = spl->spl_signature[3]; - if (spl_header_version == SPL_HEADER_VERSION) { - if (spl->fel_script_address) - setenv_hex("fel_scriptaddr", - spl->fel_script_address); - return; - } + if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0) + return; /* signature mismatch, no usable header */ + + uint8_t spl_header_version = spl->spl_signature[3]; + if (spl_header_version != SPL_HEADER_VERSION) { printf("sunxi SPL version mismatch: expected %u, got %u\n", SPL_HEADER_VERSION, spl_header_version); + return; } + if (!spl->fel_script_address) + return; + + if (spl->fel_uEnv_length != 0) { + /* + * data is expected in uEnv.txt compatible format, so "env + * import -t" the string(s) at fel_script_address right away. + */ + himport_r(&env_htab, (char *)spl->fel_script_address, + spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL); + return; + } + /* otherwise assume .scr format (mkimage-type script) */ + setenv_hex("fel_scriptaddr", spl->fel_script_address); } -#endif -#ifdef CONFIG_MISC_INIT_R -int misc_init_r(void) +/* + * Note this function gets called multiple times. + * It must not make any changes to env variables which already exist. + */ +static void setup_environment(const void *fdt) { char serial_string[17] = { 0 }; unsigned int sid[4]; uint8_t mac_addr[6]; - int ret; + char ethaddr[16]; + int i, ret; -#if !defined(CONFIG_SPL_BUILD) - setenv("fel_booted", NULL); - setenv("fel_scriptaddr", NULL); - /* determine if we are running in FEL mode */ - if (!is_boot0_magic(SPL_ADDR + 4)) { /* eGON.BT0 */ - setenv("fel_booted", "1"); - parse_spl_header(SPL_ADDR); - } + ret = sunxi_get_sid(sid); + if (ret == 0 && sid[0] != 0) { + /* + * The single words 1 - 3 of the SID have quite a few bits + * which are the same on many models, so we take a crc32 + * of all 3 words, to get a more unique value. + * + * Note we only do this on newer SoCs as we cannot change + * the algorithm on older SoCs since those have been using + * fixed mac-addresses based on only using word 3 for a + * long time and changing a fixed mac-address with an + * u-boot update is not good. + */ +#if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \ + !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \ + !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33) + sid[3] = crc32(0, (unsigned char *)&sid[1], 12); #endif - ret = sunxi_get_sid(sid); - if (ret == 0 && sid[0] != 0 && sid[3] != 0) { - if (!getenv("ethaddr")) { + /* Ensure the NIC specific bytes of the mac are not all 0 */ + if ((sid[3] & 0xffffff) == 0) + sid[3] |= 0x800000; + + for (i = 0; i < 4; i++) { + sprintf(ethaddr, "ethernet%d", i); + if (!fdt_get_alias(fdt, ethaddr)) + continue; + + if (i == 0) + strcpy(ethaddr, "ethaddr"); + else + sprintf(ethaddr, "eth%daddr", i); + + if (getenv(ethaddr)) + continue; + /* Non OUI / registered MAC address */ - mac_addr[0] = 0x02; + mac_addr[0] = (i << 4) | 0x02; mac_addr[1] = (sid[0] >> 0) & 0xff; mac_addr[2] = (sid[3] >> 24) & 0xff; mac_addr[3] = (sid[3] >> 16) & 0xff; mac_addr[4] = (sid[3] >> 8) & 0xff; mac_addr[5] = (sid[3] >> 0) & 0xff; - eth_setenv_enetaddr("ethaddr", mac_addr); + eth_setenv_enetaddr(ethaddr, mac_addr); } if (!getenv("serial#")) { @@ -635,6 +676,21 @@ int misc_init_r(void) setenv("serial#", serial_string); } } +} + +int misc_init_r(void) +{ + __maybe_unused int ret; + + setenv("fel_booted", NULL); + setenv("fel_scriptaddr", NULL); + /* determine if we are running in FEL mode */ + if (!is_boot0_magic(SPL_ADDR + 4)) { /* eGON.BT0 */ + setenv("fel_booted", "1"); + parse_spl_header(SPL_ADDR); + } + + setup_environment(gd->fdt_blob); #ifndef CONFIG_MACH_SUN9I ret = sunxi_usb_phy_probe(); @@ -645,12 +701,17 @@ int misc_init_r(void) return 0; } -#endif int ft_board_setup(void *blob, bd_t *bd) { int __maybe_unused r; + /* + * Call setup_environment again in case the boot fdt has + * ethernet aliases the u-boot copy does not have. + */ + setup_environment(blob); + #ifdef CONFIG_VIDEO_DT_SIMPLEFB r = sunxi_simplefb_setup(blob); if (r) diff --git a/board/synopsys/Kconfig b/board/synopsys/Kconfig index 8ab48cd91c4..27e5509b26e 100644 --- a/board/synopsys/Kconfig +++ b/board/synopsys/Kconfig @@ -1,9 +1,9 @@ -if TARGET_ARCANGEL4 +if TARGET_NSIM config SYS_VENDOR default "synopsys" config SYS_CONFIG_NAME - default "arcangel4" + default "nsim" endif diff --git a/board/synopsys/MAINTAINERS b/board/synopsys/MAINTAINERS index 43114cea5ec..b9bfd3c2e8a 100644 --- a/board/synopsys/MAINTAINERS +++ b/board/synopsys/MAINTAINERS @@ -1,6 +1,8 @@ - BOARD M: Alexey Brodkin <abrodkin@synopsys.com> S: Maintained -F: include/configs/arcangel4.h -F: configs/arcangel4_defconfig -F: configs/arcangel4-be_defconfig +F: include/configs/nsim.h +F: configs/nsim_700_defconfig +F: configs/nsim_700be_defconfig +F: configs/nsim_hs38_defconfig +F: configs/nsim_hs38be_defconfig diff --git a/board/synopsys/axs101/Makefile b/board/synopsys/axs101/Makefile deleted file mode 100644 index f0965f78416..00000000000 --- a/board/synopsys/axs101/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += axs101.o -obj-$(CONFIG_CMD_NAND) += nand.o diff --git a/board/synopsys/axs101/Kconfig b/board/synopsys/axs10x/Kconfig index 79e5400ea86..c60b6a20473 100644 --- a/board/synopsys/axs101/Kconfig +++ b/board/synopsys/axs10x/Kconfig @@ -1,12 +1,12 @@ -if TARGET_AXS101 +if TARGET_AXS10X config SYS_BOARD - default "axs101" + default "axs10x" config SYS_VENDOR default "synopsys" config SYS_CONFIG_NAME - default "axs101" + default "axs10x" endif diff --git a/board/synopsys/axs101/MAINTAINERS b/board/synopsys/axs10x/MAINTAINERS index 79fff8eb3e2..abb890b714c 100644 --- a/board/synopsys/axs101/MAINTAINERS +++ b/board/synopsys/axs10x/MAINTAINERS @@ -1,7 +1,7 @@ -AXS101 BOARD +AXS10X BOARD M: Alexey Brodkin <abrodkin@synopsys.com> S: Maintained -F: board/synopsys/axs101/ -F: include/configs/axs101.h +F: board/synopsys/axs10x/ +F: include/configs/axs10x.h F: configs/axs101_defconfig F: configs/axs103_defconfig diff --git a/board/synopsys/axs10x/Makefile b/board/synopsys/axs10x/Makefile new file mode 100644 index 00000000000..e29d52046f5 --- /dev/null +++ b/board/synopsys/axs10x/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2013-2016 Synopsys, Inc. All rights reserved. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += axs10x.o +obj-$(CONFIG_CMD_NAND) += nand.o diff --git a/board/synopsys/axs101/axs101.c b/board/synopsys/axs10x/axs10x.c index a5e774b2cf7..a5e774b2cf7 100644 --- a/board/synopsys/axs101/axs101.c +++ b/board/synopsys/axs10x/axs10x.c diff --git a/board/synopsys/axs101/axs10x.h b/board/synopsys/axs10x/axs10x.h index 8e8c41f865d..8e8c41f865d 100644 --- a/board/synopsys/axs101/axs10x.h +++ b/board/synopsys/axs10x/axs10x.h diff --git a/board/synopsys/axs101/nand.c b/board/synopsys/axs10x/nand.c index 4be52e22c0b..4be52e22c0b 100644 --- a/board/synopsys/axs101/nand.c +++ b/board/synopsys/axs10x/nand.c diff --git a/board/technexion/pico-imx6ul/README b/board/technexion/pico-imx6ul/README new file mode 100644 index 00000000000..2f660950976 --- /dev/null +++ b/board/technexion/pico-imx6ul/README @@ -0,0 +1,57 @@ +How to Update U-Boot on Pico-imx6ul board +----------------------------------------- + +Required software on the host PC: + +- imx_usb_loader: https://github.com/boundarydevices/imx_usb_loader + +- dfu-util: http://dfu-util.sourceforge.net/releases/ + +Build U-Boot for Pico: + +$ make mrproper +$ make pico-imx6ul_defconfig +$ make + +This will generate the U-Boot binary called u-boot.imx. + +Put pico board in USB download mode (refer to the document +http://www.wandboard.org/images/hobbit/hobbitboard-imx6ul-reva1.pdf page 15) + +Connect a USB to serial adapter between the host PC and pico + +Connect a USB cable between the OTG pico port and the host PC + +Open a terminal program such as minicom + +Copy u-boot.imx to the imx_usb_loader folder. + +Load u-boot.imx via USB: + +$ sudo ./imx_usb u-boot.imx + +Then U-Boot should start and its messages will appear in the console program. + +Use the default environment variables: + +=> env default -f -a +=> saveenv + +Run the DFU command: +=> dfu 0 mmc 0 + +Transfer u-boot.imx that will be flashed into the eMMC: + +$ sudo dfu-util -D u-boot.imx -a boot + +Then on the U-Boot prompt the following message should be seen after a +successful upgrade: + +#DOWNLOAD ... OK +Ctrl+C to exit ... + +Remove power from the pico board. + +Put pico board into normal boot mode + +Power up the board and the new updated U-Boot should boot from eMMC. diff --git a/board/technexion/pico-imx6ul/pico-imx6ul.c b/board/technexion/pico-imx6ul/pico-imx6ul.c index c038d4326ee..5cbf803e7e6 100644 --- a/board/technexion/pico-imx6ul/pico-imx6ul.c +++ b/board/technexion/pico-imx6ul/pico-imx6ul.c @@ -14,11 +14,18 @@ #include <asm/arch/sys_proto.h> #include <asm/gpio.h> #include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/mxc_i2c.h> #include <asm/io.h> #include <common.h> +#include <miiphy.h> +#include <netdev.h> #include <fsl_esdhc.h> +#include <i2c.h> #include <linux/sizes.h> #include <usb.h> +#include <power/pmic.h> +#include <power/pfuze3000_pmic.h> +#include "../../freescale/common/pfuze.h" DECLARE_GLOBAL_DATA_PTR; @@ -30,10 +37,113 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE) + #define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) +#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ + PAD_CTL_SPEED_HIGH | \ + PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST) + +#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#define RMII_PHY_RESET IMX_GPIO_NR(1, 28) + +#ifdef CONFIG_SYS_I2C_MXC +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C2 for PMIC */ +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO1_IO02__I2C1_SCL | PC, + .gpio_mode = MX6_PAD_GPIO1_IO02__GPIO1_IO02 | PC, + .gp = IMX_GPIO_NR(1, 2), + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO1_IO03__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_GPIO1_IO03__GPIO1_IO03 | PC, + .gp = IMX_GPIO_NR(1, 3), + }, +}; +#endif + +static iomux_v3_cfg_t const fec_pads[] = { + MX6_PAD_ENET1_TX_EN__ENET2_MDC | MUX_PAD_CTRL(MDIO_PAD_CTRL), + MX6_PAD_ENET1_TX_DATA1__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL), + MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL), + MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static void setup_iomux_fec(void) +{ + imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); +} + +int board_eth_init(bd_t *bis) +{ + setup_iomux_fec(); + + gpio_direction_output(RMII_PHY_RESET, 0); + /* + * According to KSZ8081MNX-RNB manual: + * For warm reset, the reset (RST#) pin should be asserted low for a + * minimum of 500μs. The strap-in pin values are read and updated + * at the de-assertion of reset. + */ + udelay(500); + + gpio_direction_output(RMII_PHY_RESET, 1); + /* + * According to KSZ8081MNX-RNB manual: + * After the de-assertion of reset, wait a minimum of 100μs before + * starting programming on the MIIM (MDC/MDIO) interface. + */ + udelay(100); + + return fecmxc_initialize(bis); +} + +static int setup_fec(void) +{ + struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + int ret; + + clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, + IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); + + ret = enable_fec_anatop_clock(1, ENET_50MHZ); + if (ret) + return ret; + + enable_enet_clk(1); + + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + int dram_init(void) { gd->ram_size = imx_ddr_size(); @@ -59,6 +169,9 @@ static iomux_v3_cfg_t const usdhc1_pads[] = { MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), }; +#define USB_OTHERREGS_OFFSET 0x800 +#define UCTRL_PWR_POL (1 << 9) + static iomux_v3_cfg_t const usb_otg_pad[] = { MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL), }; @@ -96,9 +209,67 @@ int board_early_init_f(void) return 0; } +#ifdef CONFIG_POWER +#define I2C_PMIC 0 +static struct pmic *pfuze; +int power_init_board(void) +{ + int ret; + unsigned int reg, rev_id; + + ret = power_pfuze3000_init(I2C_PMIC); + if (ret) + return ret; + + pfuze = pmic_get("PFUZE3000"); + ret = pmic_probe(pfuze); + if (ret) + return ret; + + pmic_reg_read(pfuze, PFUZE3000_DEVICEID, ®); + pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id); + printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id); + + /* disable Low Power Mode during standby mode */ + pmic_reg_read(pfuze, PFUZE3000_LDOGCTL, ®); + reg |= 0x1; + pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, reg); + + /* SW1B step ramp up time from 2us to 4us/25mV */ + pmic_reg_write(pfuze, PFUZE3000_SW1BCONF, 0x40); + + /* SW1B mode to APS/PFM */ + pmic_reg_write(pfuze, PFUZE3000_SW1BMODE, 0xc); + + /* SW1B standby voltage set to 0.975V */ + pmic_reg_write(pfuze, PFUZE3000_SW1BSTBY, 0xb); + + return 0; +} +#endif + int board_usb_phy_mode(int port) { - return USB_INIT_DEVICE; + if (port == 1) + return USB_INIT_HOST; + else + return USB_INIT_DEVICE; +} + +int board_ehci_hcd_init(int port) +{ + u32 *usbnc_usb_ctrl; + + if (port > 1) + return -EINVAL; + + usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET + + port * 4); + + /* Set Power polarity */ + setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL); + + return 0; } int board_init(void) @@ -106,6 +277,11 @@ int board_init(void) /* Address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + #ifdef CONFIG_SYS_I2C_MXC + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + #endif + + setup_fec(); setup_usb(); return 0; diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index f005762edad..27c311ee9d2 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -13,6 +13,7 @@ #include <asm/errno.h> #include <spl.h> #include <usb.h> +#include <asm/omap_sec_common.h> #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> #include <asm/arch/mux.h> @@ -862,3 +863,10 @@ int board_fit_config_name_match(const char *name) return -1; } #endif + +#ifdef CONFIG_TI_SECURE_DEVICE +void board_fit_image_post_process(void **p_image, size_t *p_size) +{ + secure_boot_verify_image(p_image, p_size); +} +#endif diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c index 08cf14d5e73..927d1364fe4 100644 --- a/board/ti/am57xx/board.c +++ b/board/ti/am57xx/board.c @@ -13,6 +13,7 @@ #include <sata.h> #include <usb.h> #include <asm/omap_common.h> +#include <asm/omap_sec_common.h> #include <asm/emif.h> #include <asm/gpio.h> #include <asm/arch/gpio.h> @@ -750,3 +751,10 @@ int board_fit_config_name_match(const char *name) return -1; } #endif + +#ifdef CONFIG_TI_SECURE_DEVICE +void board_fit_image_post_process(void **p_image, size_t *p_size) +{ + secure_boot_verify_image(p_image, p_size); +} +#endif diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 6a4d02769e5..99e82542f72 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -17,6 +17,8 @@ #include <asm/gpio.h> #include <usb.h> #include <linux/usb/gadget.h> +#include <asm/omap_common.h> +#include <asm/omap_sec_common.h> #include <asm/arch/gpio.h> #include <asm/arch/dra7xx_iodelay.h> #include <asm/emif.h> @@ -834,3 +836,10 @@ int board_fit_config_name_match(const char *name) return -1; } #endif + +#ifdef CONFIG_TI_SECURE_DEVICE +void board_fit_image_post_process(void **p_image, size_t *p_size) +{ + secure_boot_verify_image(p_image, p_size); +} +#endif diff --git a/board/ti/evm/Kconfig b/board/ti/evm/Kconfig index f02aa31a91e..4f490ddd9d5 100644 --- a/board/ti/evm/Kconfig +++ b/board/ti/evm/Kconfig @@ -10,29 +10,3 @@ config SYS_CONFIG_NAME default "omap3_evm" endif - -if TARGET_OMAP3_EVM_QUICK_MMC - -config SYS_BOARD - default "evm" - -config SYS_VENDOR - default "ti" - -config SYS_CONFIG_NAME - default "omap3_evm_quick_mmc" - -endif - -if TARGET_OMAP3_EVM_QUICK_NAND - -config SYS_BOARD - default "evm" - -config SYS_VENDOR - default "ti" - -config SYS_CONFIG_NAME - default "omap3_evm_quick_nand" - -endif diff --git a/board/ti/evm/MAINTAINERS b/board/ti/evm/MAINTAINERS index 90c3f6b9a74..612a08ace0e 100644 --- a/board/ti/evm/MAINTAINERS +++ b/board/ti/evm/MAINTAINERS @@ -3,8 +3,4 @@ M: Tom Rini <trini@konsulko.com> S: Maintained F: board/ti/evm/ F: include/configs/omap3_evm.h -F: include/configs/omap3_evm_quick_mmc.h -F: include/configs/omap3_evm_quick_nand.h F: configs/omap3_evm_defconfig -F: configs/omap3_evm_quick_mmc_defconfig -F: configs/omap3_evm_quick_nand_defconfig diff --git a/board/toradex/colibri_imx7/Kconfig b/board/toradex/colibri_imx7/Kconfig new file mode 100644 index 00000000000..7bba26b90dd --- /dev/null +++ b/board/toradex/colibri_imx7/Kconfig @@ -0,0 +1,20 @@ +if TARGET_COLIBRI_IMX7 + +config SYS_BOARD + default "colibri_imx7" + +config SYS_VENDOR + default "toradex" + +config SYS_CONFIG_NAME + default "colibri_imx7" + +config COLIBRI_IMX7_EXT_PHYCLK + bool "External oscillator for Ethernet PHY clock provided" + help + Select this if your module provides a external Ethernet PHY + clock source. + default y + + +endif diff --git a/board/toradex/colibri_imx7/MAINTAINERS b/board/toradex/colibri_imx7/MAINTAINERS new file mode 100644 index 00000000000..5ffb2417aab --- /dev/null +++ b/board/toradex/colibri_imx7/MAINTAINERS @@ -0,0 +1,6 @@ +Colibri iMX7 +M: Stefan Agner <stefan.agner@toradex.com> +S: Maintained +F: board/toradex/colibri_imx7/ +F: include/configs/colibri_imx7.h +F: configs/colibri_imx7_defconfig diff --git a/board/toradex/colibri_imx7/Makefile b/board/toradex/colibri_imx7/Makefile new file mode 100644 index 00000000000..ea597dec28f --- /dev/null +++ b/board/toradex/colibri_imx7/Makefile @@ -0,0 +1,6 @@ +# Copyright (C) 2016 Toradex AG +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := colibri_imx7.o diff --git a/board/toradex/colibri_imx7/colibri_imx7.c b/board/toradex/colibri_imx7/colibri_imx7.c new file mode 100644 index 00000000000..8eedd65bf07 --- /dev/null +++ b/board/toradex/colibri_imx7/colibri_imx7.c @@ -0,0 +1,420 @@ +/* + * Copyright (C) 2016 Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/clock.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/mx7-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/imx-common/boot_mode.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/mxc_i2c.h> +#include <asm/io.h> +#include <common.h> +#include <dm.h> +#include <dm/platform_data/serial_mxc.h> +#include <fsl_esdhc.h> +#include <i2c.h> +#include <linux/sizes.h> +#include <mmc.h> +#include <miiphy.h> +#include <netdev.h> +#include <usb/ehci-ci.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ + PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) +#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM) + +#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) + +#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM) + +#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \ + PAD_CTL_DSE_3P3V_49OHM) + +#define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) + +#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM) + +#ifdef CONFIG_SYS_I2C_MXC +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +/* I2C1 for PMIC */ +static struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX7D_PAD_GPIO1_IO04__I2C1_SCL | PC, + .gpio_mode = MX7D_PAD_GPIO1_IO04__GPIO1_IO4 | PC, + .gp = IMX_GPIO_NR(1, 4), + }, + .sda = { + .i2c_mode = MX7D_PAD_GPIO1_IO05__I2C1_SDA | PC, + .gpio_mode = MX7D_PAD_GPIO1_IO05__GPIO1_IO5 | PC, + .gp = IMX_GPIO_NR(1, 5), + }, +}; +/* I2C4 for Colibri I2C */ +static struct i2c_pads_info i2c_pad_info4 = { + .scl = { + .i2c_mode = MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL | PC, + .gpio_mode = MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 | PC, + .gp = IMX_GPIO_NR(7, 8), + }, + .sda = { + .i2c_mode = MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA | PC, + .gpio_mode = MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 | PC, + .gp = IMX_GPIO_NR(7, 9), + }, +}; +#endif + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + + return 0; +} + +static iomux_v3_cfg_t const uart1_pads[] = { + MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL), + MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc1_pads[] = { + MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + MX7D_PAD_GPIO1_IO00__GPIO1_IO0 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#ifdef CONFIG_NAND_MXS +static iomux_v3_cfg_t const gpmi_pads[] = { + MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), + MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL), +}; + +static void setup_gpmi_nand(void) +{ + imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); + + /* NAND_USDHC_BUS_CLK is set in rom */ + set_clk_nand(); +} +#endif + +static iomux_v3_cfg_t const usdhc3_emmc_pads[] = { + MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX7D_PAD_SD3_STROBE__SD3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL), + + MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +#ifdef CONFIG_VIDEO_MXS +static iomux_v3_cfg_t const lcd_pads[] = { + MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), + MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), +}; + +static iomux_v3_cfg_t const backlight_pads[] = { + /* Backlight On */ + MX7D_PAD_SD1_WP__GPIO5_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* Backlight PWM<A> (multiplexed pin) */ + MX7D_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +#define GPIO_BL_ON IMX_GPIO_NR(5, 1) +#define GPIO_PWM_A IMX_GPIO_NR(1, 8) + +static int setup_lcd(void) +{ + imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); + + imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads)); + + /* Set BL_ON */ + gpio_request(GPIO_BL_ON, "BL_ON"); + gpio_direction_output(GPIO_BL_ON, 1); + + /* Set PWM<A> to full brightness (assuming inversed polarity) */ + gpio_request(GPIO_PWM_A, "PWM<A>"); + gpio_direction_output(GPIO_PWM_A, 0); + + return 0; +} +#endif + +#ifdef CONFIG_FEC_MXC +static iomux_v3_cfg_t const fec1_pads[] = { +#ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK + MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL) | MUX_MODE_SION, +#else + MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL), +#endif + MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), + MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static void setup_iomux_fec(void) +{ + imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); +} +#endif + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); +} + +#ifdef CONFIG_FSL_ESDHC + +#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 0) + +static struct fsl_esdhc_cfg usdhc_cfg[] = { + {USDHC1_BASE_ADDR, 0, 4}, +}; + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = !gpio_get_value(USDHC1_CD_GPIO); + break; + } + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + int i, ret; + /* USDHC1 is mmc0 */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + imx_iomux_v3_setup_multiple_pads( + usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); + gpio_request(USDHC1_CD_GPIO, "usdhc1_cd"); + gpio_direction_input(USDHC1_CD_GPIO); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + break; + default: + printf("Warning: you configured more USDHC controllers" + "(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; +} +#endif + +#ifdef CONFIG_FEC_MXC +int board_eth_init(bd_t *bis) +{ + int ret; + + setup_iomux_fec(); + + ret = fecmxc_initialize_multi(bis, 0, + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); + if (ret) + printf("FEC1 MXC: %s:failed\n", __func__); + + return ret; +} + +static int setup_fec(void) +{ + struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs + = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + +#ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK + /* + * Use 50M anatop REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17] + * and output it on the pin + */ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK, + IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK); +#else + /* Use 50M external CLK for ENET1, set gpr1[13], clear gpr1[17] */ + clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], + IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK, + IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK); +#endif + + return set_clk_enet(ENET_50MHz); +} + +int board_phy_config(struct phy_device *phydev) +{ + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; +} +#endif + +int board_early_init_f(void) +{ + setup_iomux_uart(); + +#ifdef CONFIG_SYS_I2C_MXC + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info4); +#endif + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + +#ifdef CONFIG_NAND_MXS + setup_gpmi_nand(); +#endif + +#ifdef CONFIG_VIDEO_MXS + setup_lcd(); +#endif + + return 0; +} + +#ifdef CONFIG_CMD_BMODE +static const struct boot_mode board_boot_modes[] = { + /* 4 bit bus width */ + {"nand", MAKE_CFGVAL(0x40, 0x34, 0x00, 0x00)}, + {"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)}, + {NULL, 0}, +}; +#endif + +int board_late_init(void) +{ +#ifdef CONFIG_CMD_BMODE + add_board_boot_modes(board_boot_modes); +#endif + + return 0; +} + +int checkboard(void) +{ + printf("Model: Toradex Colibri iMX7%c\n", + is_cpu_type(MXC_CPU_MX7D) ? 'D' : 'S'); + + return 0; +} + +#ifdef CONFIG_USB_EHCI_MX7 +static iomux_v3_cfg_t const usb_otg2_pads[] = { + MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +int board_ehci_hcd_init(int port) +{ + switch (port) { + case 0: + break; + case 1: + if (is_cpu_type(MXC_CPU_MX7S)) + return -ENODEV; + + imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, + ARRAY_SIZE(usb_otg2_pads)); + break; + default: + return -EINVAL; + } + return 0; +} +#endif + +static struct mxc_serial_platdata mxc_serial_plat = { + .reg = (struct mxc_uart *)UART1_IPS_BASE_ADDR, + .use_dte = true, +}; + +U_BOOT_DEVICE(mxc_serial) = { + .name = "serial_mxc", + .platdata = &mxc_serial_plat, +}; diff --git a/board/toradex/colibri_imx7/imximage.cfg b/board/toradex/colibri_imx7/imximage.cfg new file mode 100644 index 00000000000..d891e82ae43 --- /dev/null +++ b/board/toradex/colibri_imx7/imximage.cfg @@ -0,0 +1,150 @@ +/* + * Copyright (C) 2015 Freescale Semiconductor, Inc. + * 2015 Toradex AG + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer docs/README.imxmage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +#define __ASSEMBLY__ +#include <config.h> + +/* image version */ + +IMAGE_VERSION 2 + +/* + * Boot Device : sd + */ + +BOOT_FROM sd + +/* + * Secure boot support + */ +#ifdef CONFIG_SECURE_BOOT +CSF CONFIG_CSF_SIZE +#endif + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* IOMUXC_GPR_GPR1 */ +DATA 4 0x30340004 0x4F400005 + +/* DDR3L */ +/* assuming MEMC_FREQ_RATIO = 2 */ +/* SRC_DDRC_RCR */ +DATA 4 0x30391000 0x00000002 +/* DDRC_MSTR */ +DATA 4 0x307a0000 0x01040001 +/* DDRC_DFIUPD0 */ +DATA 4 0x307a01a0 0x80400003 +/* DDRC_DFIUPD1 */ +DATA 4 0x307a01a4 0x00100020 +/* DDRC_DFIUPD2 */ +DATA 4 0x307a01a8 0x80100004 +/* DDRC_RFSHTMG */ +DATA 4 0x307a0064 0x00400045 +/* DDRC_MP_PCTRL_0 */ +DATA 4 0x307a0490 0x00000001 +/* DDRC_INIT0 */ +DATA 4 0x307a00d0 0x00020083 +/* DDRC_INIT1 */ +DATA 4 0x307a00d4 0x00690000 +/* DDRC_INIT3 MR0/MR1 */ +DATA 4 0x307a00dc 0x09300004 +/* DDRC_INIT4 MR2/MR3 */ +DATA 4 0x307a00e0 0x04480000 +/* DDRC_INIT5 */ +DATA 4 0x307a00e4 0x00100004 +/* DDRC_RANKCTL */ +DATA 4 0x307a00f4 0x0000033f +/* DDRC_DRAMTMG0 */ +DATA 4 0x307a0100 0x090b090a +/* DDRC_DRAMTMG1 */ +DATA 4 0x307a0104 0x000d020d +/* DDRC_DRAMTMG2 */ +DATA 4 0x307a0108 0x03040307 +/* DDRC_DRAMTMG3 */ +DATA 4 0x307a010c 0x00002006 +/* DDRC_DRAMTMG4 */ +DATA 4 0x307a0110 0x04020205 +/* DDRC_DRAMTMG5 */ +DATA 4 0x307a0114 0x03030202 +/* DDRC_DRAMTMG8 */ +DATA 4 0x307a0120 0x00000803 +/* DDRC_ZQCTL0 */ +DATA 4 0x307a0180 0x00800020 +/* DDRC_ZQCTL1 */ +DATA 4 0x307a0184 0x02001000 +/* DDRC_DFITMG0 */ +DATA 4 0x307a0190 0x02098204 +/* DDRC_DFITMG1 */ +DATA 4 0x307a0194 0x00030303 +/* DDRC_ADDRMAP0 */ +DATA 4 0x307a0200 0x0000001f +/* DDRC_ADDRMAP1 */ +DATA 4 0x307a0204 0x00080808 +/* DDRC_ADDRMAP5 */ +DATA 4 0x307a0214 0x07070707 +/* DDRC_ADDRMAP6 */ +DATA 4 0x307a0218 0x07070707 +/* DDRC_ODTCFG */ +DATA 4 0x307a0240 0x06000601 +/* DDRC_ODTMAP */ +DATA 4 0x307a0244 0x00000011 +/* SRC_DDRC_RCR */ +DATA 4 0x30391000 0x00000000 +/* DDR_PHY_PHY_CON0 */ +DATA 4 0x30790000 0x17420f40 +/* DDR_PHY_PHY_CON1 */ +DATA 4 0x30790004 0x10210100 +/* DDR_PHY_PHY_CON4 */ +DATA 4 0x30790010 0x00060807 +/* DDR_PHY_MDLL_CON0 */ +DATA 4 0x307900b0 0x1010007e +/* DDR_PHY_DRVDS_CON0 */ +DATA 4 0x3079009c 0x00000d6e +/* DDR_PHY_OFFSET_RD_CON0 */ +DATA 4 0x30790020 0x08080808 +/* DDR_PHY_OFFSET_WR_CON0 */ +DATA 4 0x30790030 0x08080808 +/* DDR_PHY_CMD_SDLL_CON0 */ +DATA 4 0x30790050 0x01000010 +DATA 4 0x30790050 0x00000010 + +/* DDR_PHY_ZQ_CON0 */ +DATA 4 0x307900c0 0x0e407304 +DATA 4 0x307900c0 0x0e447304 +DATA 4 0x307900c0 0x0e447306 +/* DDR_PHY_ZQ_CON1 */ +CHECK_BITS_SET 4 0x307900c4 0x1 +/* DDR_PHY_ZQ_CON0 */ +DATA 4 0x307900c0 0x0e447304 +DATA 4 0x307900c0 0x0e407304 + +/* CCM_CCGRn */ +DATA 4 0x30384130 0x00000000 +/* IOMUXC_GPR_GPR8 */ +DATA 4 0x30340020 0x00000178 +/* CCM_CCGRn */ +DATA 4 0x30384130 0x00000002 +/* DDR_PHY_LP_CON0 */ +DATA 4 0x30790018 0x0000000f + +/* DDRC_STAT */ +CHECK_BITS_SET 4 0x307a0004 0x1 diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c index 4ce74cd9715..1de1e0b2578 100644 --- a/board/wandboard/wandboard.c +++ b/board/wandboard/wandboard.c @@ -19,6 +19,7 @@ #include <asm/imx-common/mxc_i2c.h> #include <asm/imx-common/boot_mode.h> #include <asm/imx-common/video.h> +#include <asm/imx-common/sata.h> #include <asm/io.h> #include <linux/sizes.h> #include <common.h> @@ -345,6 +346,12 @@ int board_early_init_f(void) #if defined(CONFIG_VIDEO_IPUV3) setup_display(); #endif +#ifdef CONFIG_CMD_SATA + /* Only mx6q wandboard has SATA */ + if (is_cpu_type(MXC_CPU_MX6Q)) + setup_sata(); +#endif + return 0; } @@ -384,7 +391,7 @@ int board_late_init(void) #endif #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) + if (is_mx6dq()) setenv("board_rev", "MX6Q"); else setenv("board_rev", "MX6DL"); @@ -403,7 +410,7 @@ int board_init(void) gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info); - if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) + if (is_mx6dq()) setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info); else setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info); diff --git a/board/warp/warp.c b/board/warp/warp.c index 49dfdb67174..0bc0a6a92e6 100644 --- a/board/warp/warp.c +++ b/board/warp/warp.c @@ -46,7 +46,7 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + gd->ram_size = imx_ddr_size(); return 0; } diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index f15dc5d7152..0c5d9979316 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -307,3 +307,8 @@ int board_usb_cleanup(int index, enum usb_init_type init) return 0; } #endif + +void reset_misc(void) +{ + psci_system_reset(true); +} |