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-rw-r--r--board/LEOX/elpt860/u-boot.lds8
-rw-r--r--board/LaCie/edminiv2/Makefile4
-rw-r--r--board/LaCie/net2big_v2/Makefile4
-rw-r--r--board/LaCie/netspace_v2/Makefile4
-rw-r--r--board/LaCie/wireless_space/Makefile4
-rw-r--r--board/Marvell/db64360/Makefile4
-rw-r--r--board/Marvell/db64460/Makefile4
-rw-r--r--board/actux1/u-boot.lds8
-rw-r--r--board/actux2/u-boot.lds8
-rw-r--r--board/actux3/u-boot.lds8
-rw-r--r--board/altera/nios2-generic/Makefile4
-rw-r--r--board/altera/nios2-generic/config.mk4
-rw-r--r--board/atmel/sama5d3xek/sama5d3xek.c5
-rw-r--r--board/avionic-design/medcom-wide/Makefile2
-rw-r--r--board/avionic-design/plutux/Makefile2
-rw-r--r--board/avionic-design/tec/Makefile2
-rw-r--r--board/cogent/config.mk12
-rw-r--r--board/cogent/dipsw.c2
-rw-r--r--board/cogent/flash.c2
-rw-r--r--board/cogent/lcd.c2
-rw-r--r--board/cogent/mb.c10
-rw-r--r--board/cogent/serial.c2
-rw-r--r--board/compal/paz00/Makefile2
-rw-r--r--board/compulab/cm_t335/u-boot.lds2
-rw-r--r--board/compulab/cm_t35/cm_t35.c14
-rw-r--r--board/compulab/common/Makefile2
-rw-r--r--board/compulab/common/eeprom.h2
-rw-r--r--board/compulab/common/omap3_display.c46
-rw-r--r--board/compulab/trimslice/Makefile2
-rw-r--r--board/davinci/da8xxevm/u-boot-spl-hawk.lds4
-rw-r--r--board/dvlhost/u-boot.lds8
-rw-r--r--board/emk/top5200/Makefile4
-rw-r--r--board/emk/top860/Makefile3
-rw-r--r--board/esd/adciop/Makefile4
-rw-r--r--board/esd/apc405/Makefile4
-rw-r--r--board/esd/ar405/Makefile4
-rw-r--r--board/esd/ash405/Makefile4
-rw-r--r--board/esd/cms700/Makefile4
-rw-r--r--board/esd/cpci2dp/Makefile4
-rw-r--r--board/esd/cpci405/Makefile4
-rw-r--r--board/esd/cpci5200/Makefile4
-rw-r--r--board/esd/cpci750/Makefile4
-rw-r--r--board/esd/cpciiser4/Makefile4
-rw-r--r--board/esd/dasa_sim/Makefile4
-rw-r--r--board/esd/dp405/Makefile4
-rw-r--r--board/esd/du405/Makefile4
-rw-r--r--board/esd/hh405/Makefile4
-rw-r--r--board/esd/hub405/Makefile4
-rw-r--r--board/esd/ocrtc/Makefile4
-rw-r--r--board/esd/pci405/Makefile4
-rw-r--r--board/esd/pf5200/Makefile4
-rw-r--r--board/esd/plu405/Makefile4
-rw-r--r--board/esd/pmc405/Makefile4
-rw-r--r--board/esd/pmc405de/Makefile4
-rw-r--r--board/esd/pmc440/Makefile4
-rw-r--r--board/esd/voh405/Makefile4
-rw-r--r--board/esd/vom405/Makefile4
-rw-r--r--board/esd/wuh405/Makefile4
-rw-r--r--board/esteem192e/u-boot.lds4
-rw-r--r--board/exmeritus/hww1u1a/ddr.c4
-rw-r--r--board/exmeritus/hww1u1a/hww1u1a.c5
-rw-r--r--board/freescale/b4860qds/ddr.c6
-rw-r--r--board/freescale/bsc9131rdb/ddr.c4
-rw-r--r--board/freescale/bsc9131rdb/spl_minimal.c5
-rw-r--r--board/freescale/bsc9132qds/bsc9132qds.c18
-rw-r--r--board/freescale/bsc9132qds/ddr.c4
-rw-r--r--board/freescale/bsc9132qds/spl_minimal.c5
-rw-r--r--board/freescale/c29xpcie/c29xpcie.c2
-rw-r--r--board/freescale/c29xpcie/ddr.c4
-rw-r--r--board/freescale/corenet_ds/ddr.c4
-rw-r--r--board/freescale/corenet_ds/eth_p4080.c2
-rw-r--r--board/freescale/corenet_ds/p3041ds_ddr.c2
-rw-r--r--board/freescale/corenet_ds/p4080ds_ddr.c2
-rw-r--r--board/freescale/corenet_ds/p5020ds_ddr.c2
-rw-r--r--board/freescale/corenet_ds/p5040ds_ddr.c2
-rw-r--r--board/freescale/m52277evb/config.mk11
-rw-r--r--board/freescale/m52277evb/u-boot.lds4
-rw-r--r--board/freescale/m5235evb/config.mk12
-rw-r--r--board/freescale/m53017evb/u-boot.lds6
-rw-r--r--board/freescale/m54451evb/config.mk11
-rw-r--r--board/freescale/m54455evb/config.mk11
-rw-r--r--board/freescale/mpc8349emds/Makefile2
-rw-r--r--board/freescale/mpc8349emds/ddr.c4
-rw-r--r--board/freescale/mpc8349emds/mpc8349emds.c6
-rw-r--r--board/freescale/mpc8536ds/ddr.c4
-rw-r--r--board/freescale/mpc8536ds/mpc8536ds.c4
-rw-r--r--board/freescale/mpc8540ads/ddr.c4
-rw-r--r--board/freescale/mpc8540ads/mpc8540ads.c5
-rw-r--r--board/freescale/mpc8541cds/ddr.c4
-rw-r--r--board/freescale/mpc8541cds/mpc8541cds.c2
-rw-r--r--board/freescale/mpc8544ds/ddr.c4
-rw-r--r--board/freescale/mpc8544ds/mpc8544ds.c2
-rw-r--r--board/freescale/mpc8548cds/ddr.c4
-rw-r--r--board/freescale/mpc8548cds/mpc8548cds.c2
-rw-r--r--board/freescale/mpc8555cds/ddr.c4
-rw-r--r--board/freescale/mpc8555cds/mpc8555cds.c2
-rw-r--r--board/freescale/mpc8560ads/ddr.c4
-rw-r--r--board/freescale/mpc8560ads/mpc8560ads.c4
-rw-r--r--board/freescale/mpc8568mds/ddr.c4
-rw-r--r--board/freescale/mpc8568mds/mpc8568mds.c2
-rw-r--r--board/freescale/mpc8569mds/ddr.c4
-rw-r--r--board/freescale/mpc8569mds/mpc8569mds.c5
-rw-r--r--board/freescale/mpc8572ds/ddr.c4
-rw-r--r--board/freescale/mpc8572ds/mpc8572ds.c4
-rw-r--r--board/freescale/mpc8610hpcd/Makefile2
-rw-r--r--board/freescale/mpc8610hpcd/ddr.c4
-rw-r--r--board/freescale/mpc8610hpcd/mpc8610hpcd.c4
-rw-r--r--board/freescale/mpc8641hpcn/Makefile2
-rw-r--r--board/freescale/mpc8641hpcn/ddr.c4
-rw-r--r--board/freescale/mpc8641hpcn/mpc8641hpcn.c4
-rw-r--r--board/freescale/mx31ads/u-boot.lds10
-rw-r--r--board/freescale/p1010rdb/README.P1010RDB-PA (renamed from board/freescale/p1010rdb/README)4
-rw-r--r--board/freescale/p1010rdb/README.P1010RDB-PB188
-rw-r--r--board/freescale/p1010rdb/ddr.c4
-rw-r--r--board/freescale/p1010rdb/p1010rdb.c2
-rw-r--r--board/freescale/p1010rdb/spl_minimal.c5
-rw-r--r--board/freescale/p1022ds/ddr.c4
-rw-r--r--board/freescale/p1022ds/p1022ds.c2
-rw-r--r--board/freescale/p1022ds/spl_minimal.c2
-rw-r--r--board/freescale/p1023rdb/ddr.c4
-rw-r--r--board/freescale/p1023rdb/p1023rdb.c2
-rw-r--r--board/freescale/p1023rds/p1023rds.c5
-rw-r--r--board/freescale/p1_p2_rdb/ddr.c2
-rw-r--r--board/freescale/p1_p2_rdb_pc/ddr.c4
-rw-r--r--board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c2
-rw-r--r--board/freescale/p1_p2_rdb_pc/spl_minimal.c2
-rw-r--r--board/freescale/p1_twr/ddr.c4
-rw-r--r--board/freescale/p1_twr/p1_twr.c2
-rw-r--r--board/freescale/p2020come/ddr.c4
-rw-r--r--board/freescale/p2020ds/ddr.c6
-rw-r--r--board/freescale/p2020ds/p2020ds.c5
-rw-r--r--board/freescale/p2041rdb/ddr.c4
-rw-r--r--board/freescale/t1040qds/Makefile2
-rw-r--r--board/freescale/t1040qds/ddr.c4
-rw-r--r--board/freescale/t1040qds/t1040_pbi.cfg27
-rw-r--r--board/freescale/t1040qds/t1040_rcw.cfg7
-rw-r--r--board/freescale/t104xrdb/Makefile12
-rw-r--r--board/freescale/t104xrdb/README200
-rw-r--r--board/freescale/t104xrdb/ddr.c132
-rw-r--r--board/freescale/t104xrdb/ddr.h76
-rw-r--r--board/freescale/t104xrdb/law.c32
-rw-r--r--board/freescale/t104xrdb/pci.c23
-rw-r--r--board/freescale/t104xrdb/t104xrdb.c93
-rw-r--r--board/freescale/t104xrdb/t104xrdb.h13
-rw-r--r--board/freescale/t104xrdb/tlb.c107
-rw-r--r--board/freescale/t2080qds/Makefile12
-rw-r--r--board/freescale/t2080qds/ddr.c127
-rw-r--r--board/freescale/t2080qds/ddr.h85
-rw-r--r--board/freescale/t2080qds/eth_t2080qds.c511
-rw-r--r--board/freescale/t2080qds/law.c34
-rw-r--r--board/freescale/t2080qds/pci.c23
-rw-r--r--board/freescale/t2080qds/t2080_pbi.cfg41
-rw-r--r--board/freescale/t2080qds/t2080_rcw.cfg8
-rw-r--r--board/freescale/t2080qds/t2080qds.c324
-rw-r--r--board/freescale/t2080qds/t2080qds.h13
-rw-r--r--board/freescale/t2080qds/t2080qds_qixis.h47
-rw-r--r--board/freescale/t2080qds/tlb.c146
-rw-r--r--board/freescale/t4qds/ddr.c4
-rw-r--r--board/freescale/t4qds/eth.c2
-rw-r--r--board/gaisler/gr_cpci_ax2000/config.mk3
-rw-r--r--board/gaisler/gr_ep2s60/config.mk3
-rw-r--r--board/gaisler/gr_xc3s_1500/config.mk3
-rw-r--r--board/gaisler/grsim/config.mk3
-rw-r--r--board/gaisler/grsim_leon2/config.mk3
-rw-r--r--board/gdsys/p1022/controlcenterd.c2
-rw-r--r--board/gdsys/p1022/ddr.c4
-rw-r--r--board/genietv/u-boot.lds10
-rw-r--r--board/h2200/Makefile3
-rw-r--r--board/hermes/u-boot.lds2
-rw-r--r--board/imgtec/malta/Makefile (renamed from board/qemu-malta/Makefile)3
-rw-r--r--board/imgtec/malta/flash-malta-boot.tcl40
-rw-r--r--board/imgtec/malta/lowlevel_init.S238
-rw-r--r--board/imgtec/malta/malta.c220
-rw-r--r--board/imgtec/malta/superio.c63
-rw-r--r--board/imgtec/malta/superio.h15
-rw-r--r--board/keymile/km82xx/Makefile3
-rw-r--r--board/keymile/km83xx/Makefile4
-rw-r--r--board/keymile/km_arm/Makefile4
-rw-r--r--board/keymile/kmp204x/Makefile6
-rw-r--r--board/keymile/kmp204x/ddr.c4
-rw-r--r--board/kmc/kzm9g/kzm9g.c1
-rw-r--r--board/kup/kup4k/Makefile4
-rw-r--r--board/kup/kup4x/Makefile4
-rw-r--r--board/logicpd/am3517evm/am3517evm.c4
-rw-r--r--board/matrix_vision/mvsmr/u-boot.lds2
-rw-r--r--board/mpl/mip405/Makefile4
-rw-r--r--board/mpl/pati/Makefile4
-rw-r--r--board/mpl/pip405/Makefile4
-rw-r--r--board/mpl/vcma9/Makefile4
-rw-r--r--board/mvblue/u-boot.lds12
-rw-r--r--board/nvidia/beaver/Makefile2
-rw-r--r--board/nvidia/ventana/Makefile2
-rw-r--r--board/overo/overo.c2
-rw-r--r--board/phytec/pcm051/board.c4
-rw-r--r--board/pn62/Makefile8
-rw-r--r--board/pn62/cmd_pn62.c146
-rw-r--r--board/pn62/misc.c219
-rw-r--r--board/pn62/pn62.c171
-rw-r--r--board/pn62/pn62.h145
-rw-r--r--board/prodrive/p3mx/Makefile4
-rw-r--r--board/psyent/pci5441/Makefile4
-rw-r--r--board/psyent/pci5441/config.mk1
-rw-r--r--board/psyent/pk1c20/Makefile4
-rw-r--r--board/psyent/pk1c20/config.mk1
-rw-r--r--board/qemu-malta/lowlevel_init.S69
-rw-r--r--board/qemu-malta/qemu-malta.c47
-rw-r--r--board/rbc823/u-boot.lds8
-rw-r--r--board/renesas/ecovec/ecovec.c3
-rw-r--r--board/sandburst/karef/Makefile4
-rw-r--r--board/sandburst/metrobox/Makefile4
-rw-r--r--board/sbc8548/Makefile2
-rw-r--r--board/sbc8548/ddr.c7
-rw-r--r--board/sbc8548/sbc8548.c2
-rw-r--r--board/sbc8641d/Makefile2
-rw-r--r--board/sbc8641d/ddr.c4
-rw-r--r--board/sbc8641d/sbc8641d.c8
-rw-r--r--board/siemens/common/board.c4
-rw-r--r--board/siemens/dxr2/Makefile4
-rw-r--r--board/siemens/pxm2/Makefile4
-rw-r--r--board/siemens/rut/Makefile4
-rw-r--r--board/socrates/Makefile2
-rw-r--r--board/socrates/ddr.c4
-rw-r--r--board/socrates/sdram.c5
-rw-r--r--board/spd8xx/u-boot.lds4
-rw-r--r--board/stx/stxgp3/Makefile2
-rw-r--r--board/stx/stxgp3/ddr.c4
-rw-r--r--board/stx/stxgp3/stxgp3.c2
-rw-r--r--board/stx/stxssa/Makefile2
-rw-r--r--board/stx/stxssa/ddr.c4
-rw-r--r--board/stx/stxssa/stxssa.c2
-rw-r--r--board/svm_sc8xx/u-boot.lds10
-rw-r--r--board/ti/am335x/board.c16
-rw-r--r--board/ti/am335x/u-boot.lds2
-rw-r--r--board/ti/am3517crane/am3517crane.c4
-rw-r--r--board/ti/beagle/Makefile2
-rw-r--r--board/ti/evm/evm.c4
-rw-r--r--board/toradex/colibri_t20_iris/Makefile3
-rw-r--r--board/tqc/tqm5200/Makefile3
-rw-r--r--board/tqc/tqm8260/Makefile4
-rw-r--r--board/tqc/tqm8272/Makefile4
-rw-r--r--board/tqc/tqm8xx/u-boot.lds14
-rw-r--r--board/vpac270/u-boot-spl.lds4
-rw-r--r--board/xes/xpedite517x/ddr.c4
-rw-r--r--board/xes/xpedite517x/xpedite517x.c2
-rw-r--r--board/xes/xpedite520x/ddr.c4
-rw-r--r--board/xes/xpedite537x/ddr.c4
-rw-r--r--board/xes/xpedite550x/ddr.c4
-rw-r--r--board/xilinx/ppc405-generic/Makefile4
-rw-r--r--board/xilinx/ppc440-generic/Makefile4
249 files changed, 3193 insertions, 1402 deletions
diff --git a/board/LEOX/elpt860/u-boot.lds b/board/LEOX/elpt860/u-boot.lds
index b30b667eb9..c5e57ec03b 100644
--- a/board/LEOX/elpt860/u-boot.lds
+++ b/board/LEOX/elpt860/u-boot.lds
@@ -30,10 +30,10 @@ SECTIONS
arch/powerpc/cpu/mpc8xx/start.o (.text*)
arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- common/libcommon.o (.text*)
- arch/powerpc/cpu/mpc8xx/libmpc8xx.o (.text*)
- board/LEOX/elpt860/libelpt860.o (.text*)
- arch/powerpc/lib/libpowerpc.o (.text*)
+ common/built-in.o (.text*)
+ arch/powerpc/cpu/mpc8xx/built-in.o (.text*)
+ board/LEOX/elpt860/built-in.o (.text*)
+ arch/powerpc/lib/built-in.o (.text*)
. = env_offset;
common/env_embedded.o (.text*)
diff --git a/board/LaCie/edminiv2/Makefile b/board/LaCie/edminiv2/Makefile
index 7ca06f5a79..035f6865d9 100644
--- a/board/LaCie/edminiv2/Makefile
+++ b/board/LaCie/edminiv2/Makefile
@@ -9,8 +9,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y := edminiv2.o ../common/common.o
diff --git a/board/LaCie/net2big_v2/Makefile b/board/LaCie/net2big_v2/Makefile
index 4fa08c5138..f3074af256 100644
--- a/board/LaCie/net2big_v2/Makefile
+++ b/board/LaCie/net2big_v2/Makefile
@@ -9,10 +9,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y := net2big_v2.o ../common/common.o
ifneq ($(and $(CONFIG_KIRKWOOD_GPIO),$(CONFIG_NET2BIG_V2)),)
obj-y += ../common/cpld-gpio-bus.o
diff --git a/board/LaCie/netspace_v2/Makefile b/board/LaCie/netspace_v2/Makefile
index e5357e4bc3..47778d8472 100644
--- a/board/LaCie/netspace_v2/Makefile
+++ b/board/LaCie/netspace_v2/Makefile
@@ -9,8 +9,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y := netspace_v2.o ../common/common.o
diff --git a/board/LaCie/wireless_space/Makefile b/board/LaCie/wireless_space/Makefile
index 11c535e99a..90a84f4892 100644
--- a/board/LaCie/wireless_space/Makefile
+++ b/board/LaCie/wireless_space/Makefile
@@ -9,8 +9,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y := wireless_space.o ../common/common.o
diff --git a/board/Marvell/db64360/Makefile b/board/Marvell/db64360/Makefile
index aad4776b88..aefe0a789a 100644
--- a/board/Marvell/db64360/Makefile
+++ b/board/Marvell/db64360/Makefile
@@ -8,10 +8,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y = db64360.o ../common/flash.o ../common/serial.o ../common/memory.o pci.o \
mv_eth.o ../common/ns16550.o mpsc.o ../common/i2c.o \
sdram_init.o ../common/intel_flash.o ../common/misc.o
diff --git a/board/Marvell/db64460/Makefile b/board/Marvell/db64460/Makefile
index ea9e57086e..a970f9afde 100644
--- a/board/Marvell/db64460/Makefile
+++ b/board/Marvell/db64460/Makefile
@@ -8,10 +8,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y += db64460.o ../common/flash.o ../common/serial.o ../common/memory.o pci.o \
mv_eth.o ../common/ns16550.o mpsc.o ../common/i2c.o \
sdram_init.o ../common/intel_flash.o ../common/misc.o
diff --git a/board/actux1/u-boot.lds b/board/actux1/u-boot.lds
index 12e018f316..4716e4f0e0 100644
--- a/board/actux1/u-boot.lds
+++ b/board/actux1/u-boot.lds
@@ -16,10 +16,10 @@ SECTIONS
.text : {
*(.__image_copy_start)
arch/arm/cpu/ixp/start.o(.text*)
- net/libnet.o(.text*)
- board/actux1/libactux1.o(.text*)
- arch/arm/cpu/ixp/libixp.o(.text*)
- drivers/input/libinput.o(.text*)
+ net/built-in.o(.text*)
+ board/actux1/built-in.o(.text*)
+ arch/arm/cpu/ixp/built-in.o(.text*)
+ drivers/input/built-in.o(.text*)
. = env_offset;
common/env_embedded.o(.ppcenv)
diff --git a/board/actux2/u-boot.lds b/board/actux2/u-boot.lds
index 300273bf7a..f00d7c72b1 100644
--- a/board/actux2/u-boot.lds
+++ b/board/actux2/u-boot.lds
@@ -16,10 +16,10 @@ SECTIONS
.text : {
*(.__image_copy_start)
arch/arm/cpu/ixp/start.o(.text*)
- net/libnet.o(.text*)
- board/actux2/libactux2.o(.text*)
- arch/arm/cpu/ixp/libixp.o(.text*)
- drivers/input/libinput.o(.text*)
+ net/built-in.o(.text*)
+ board/actux2/built-in.o(.text*)
+ arch/arm/cpu/ixp/built-in.o(.text*)
+ drivers/input/built-in.o(.text*)
. = env_offset;
common/env_embedded.o(.ppcenv)
diff --git a/board/actux3/u-boot.lds b/board/actux3/u-boot.lds
index 9c97c533dc..2de3ca60b5 100644
--- a/board/actux3/u-boot.lds
+++ b/board/actux3/u-boot.lds
@@ -16,10 +16,10 @@ SECTIONS
.text : {
*(.__image_copy_start)
arch/arm/cpu/ixp/start.o(.text*)
- net/libnet.o(.text*)
- board/actux3/libactux3.o(.text*)
- arch/arm/cpu/ixp/libixp.o(.text*)
- drivers/input/libinput.o(.text*)
+ net/built-in.o(.text*)
+ board/actux3/built-in.o(.text*)
+ arch/arm/cpu/ixp/built-in.o(.text*)
+ drivers/input/built-in.o(.text*)
. = env_offset;
common/env_embedded.o(.ppcenv)
diff --git a/board/altera/nios2-generic/Makefile b/board/altera/nios2-generic/Makefile
index 84c7bff80f..84690fe04d 100644
--- a/board/altera/nios2-generic/Makefile
+++ b/board/altera/nios2-generic/Makefile
@@ -6,10 +6,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y := nios2-generic.o
obj-$(CONFIG_CMD_IDE) += ../common/cfide.o
obj-$(CONFIG_EPLED) += ../common/epled.o
diff --git a/board/altera/nios2-generic/config.mk b/board/altera/nios2-generic/config.mk
index f9f317c440..a673525195 100644
--- a/board/altera/nios2-generic/config.mk
+++ b/board/altera/nios2-generic/config.mk
@@ -5,11 +5,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
-# we get text_base from board config header, so do not use this
-#CONFIG_SYS_TEXT_BASE = do-not-use-me
-
PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
-PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c
index 0ab8020126..eff94a48b2 100644
--- a/board/atmel/sama5d3xek/sama5d3xek.c
+++ b/board/atmel/sama5d3xek/sama5d3xek.c
@@ -134,7 +134,8 @@ static void sama5d3xek_lcd_hw_init(void)
void lcd_show_board_info(void)
{
- ulong dram_size, nand_size;
+ ulong dram_size;
+ uint64_t nand_size;
int i;
char temp[32];
@@ -153,7 +154,7 @@ void lcd_show_board_info(void)
for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
nand_size += nand_info[i].size;
#endif
- lcd_printf("%ld MB SDRAM, %ld MB NAND\n",
+ lcd_printf("%ld MB SDRAM, %lld MB NAND\n",
dram_size >> 20, nand_size >> 20);
}
#endif /* CONFIG_LCD_INFO */
diff --git a/board/avionic-design/medcom-wide/Makefile b/board/avionic-design/medcom-wide/Makefile
index 6c4ab643ef..87e19123b0 100644
--- a/board/avionic-design/medcom-wide/Makefile
+++ b/board/avionic-design/medcom-wide/Makefile
@@ -7,8 +7,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-$(shell mkdir -p $(obj)../common $(obj)../../nvidia/common)
-
obj-y := ../common/tamonten.o
include ../../nvidia/common/common.mk
diff --git a/board/avionic-design/plutux/Makefile b/board/avionic-design/plutux/Makefile
index 6c4ab643ef..87e19123b0 100644
--- a/board/avionic-design/plutux/Makefile
+++ b/board/avionic-design/plutux/Makefile
@@ -7,8 +7,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-$(shell mkdir -p $(obj)../common $(obj)../../nvidia/common)
-
obj-y := ../common/tamonten.o
include ../../nvidia/common/common.mk
diff --git a/board/avionic-design/tec/Makefile b/board/avionic-design/tec/Makefile
index 6c4ab643ef..87e19123b0 100644
--- a/board/avionic-design/tec/Makefile
+++ b/board/avionic-design/tec/Makefile
@@ -7,8 +7,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-$(shell mkdir -p $(obj)../common $(obj)../../nvidia/common)
-
obj-y := ../common/tamonten.o
include ../../nvidia/common/common.mk
diff --git a/board/cogent/config.mk b/board/cogent/config.mk
deleted file mode 100644
index 1452d46a9f..0000000000
--- a/board/cogent/config.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# (C) Copyright 2000
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-#
-# Cogent Modular Architecture
-#
-
-PLATFORM_CPPFLAGS += -I$(TOPDIR)
diff --git a/board/cogent/dipsw.c b/board/cogent/dipsw.c
index d2027c9758..ecfbc25981 100644
--- a/board/cogent/dipsw.c
+++ b/board/cogent/dipsw.c
@@ -1,5 +1,5 @@
#include <common.h>
-#include <board/cogent/dipsw.h>
+#include "dipsw.h"
unsigned char
dipsw_raw(void)
diff --git a/board/cogent/flash.c b/board/cogent/flash.c
index d4ae4d0a3c..1da8f10a1f 100644
--- a/board/cogent/flash.c
+++ b/board/cogent/flash.c
@@ -6,7 +6,7 @@
*/
#include <common.h>
-#include <board/cogent/flash.h>
+#include "flash.h"
#include <linux/compiler.h>
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
diff --git a/board/cogent/lcd.c b/board/cogent/lcd.c
index 76f5ad103f..8e90f9853a 100644
--- a/board/cogent/lcd.c
+++ b/board/cogent/lcd.c
@@ -48,7 +48,7 @@
#include <common.h>
#include <stdarg.h>
-#include <board/cogent/lcd.h>
+#include "lcd.h"
static char lines[2][LCD_LINE_LENGTH+1];
static int curline;
diff --git a/board/cogent/mb.c b/board/cogent/mb.c
index 603f1235a4..3eea47d3e8 100644
--- a/board/cogent/mb.c
+++ b/board/cogent/mb.c
@@ -6,11 +6,11 @@
*/
#include <common.h>
-#include <board/cogent/dipsw.h>
-#include <board/cogent/lcd.h>
-#include <board/cogent/rtc.h>
-#include <board/cogent/par.h>
-#include <board/cogent/pci.h>
+#include "dipsw.h"
+#include "lcd.h"
+#include "rtc.h"
+#include "par.h"
+#include "pci.h"
/* ------------------------------------------------------------------------- */
diff --git a/board/cogent/serial.c b/board/cogent/serial.c
index 20631d162d..f0d6b22cfd 100644
--- a/board/cogent/serial.c
+++ b/board/cogent/serial.c
@@ -4,7 +4,7 @@
*/
#include <common.h>
-#include <board/cogent/serial.h>
+#include "serial.h"
#include <serial.h>
#include <linux/compiler.h>
diff --git a/board/compal/paz00/Makefile b/board/compal/paz00/Makefile
index 824cd2ea1f..b2d3b6b4b2 100644
--- a/board/compal/paz00/Makefile
+++ b/board/compal/paz00/Makefile
@@ -14,8 +14,6 @@
# more details.
#
-$(shell mkdir -p $(obj)../../nvidia/common)
-
obj-y := paz00.o
include ../../nvidia/common/common.mk
diff --git a/board/compulab/cm_t335/u-boot.lds b/board/compulab/cm_t335/u-boot.lds
index 3bd96e9c1b..1b609a249a 100644
--- a/board/compulab/cm_t335/u-boot.lds
+++ b/board/compulab/cm_t335/u-boot.lds
@@ -19,7 +19,7 @@ SECTIONS
{
*(.__image_copy_start)
CPUDIR/start.o (.text*)
- board/compulab/cm_t335/libcm_t335.o (.text*)
+ board/compulab/cm_t335/built-in.o (.text*)
*(.text*)
}
diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c
index b9a996594f..bc8e0cad94 100644
--- a/board/compulab/cm_t35/cm_t35.c
+++ b/board/compulab/cm_t35/cm_t35.c
@@ -268,6 +268,9 @@ static void cm_t3x_set_common_muxconf(void)
/* DVI enable */
MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M4));/*GPMC_nCS3*/
+ /* DataImage backlight */
+ MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | DIS | M4));/*GPIO_58*/
+
/* CM-T3x Ethernet */
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M0)); /*GPMC_nCS5*/
MUX_VAL(CP(GPMC_CLK), (IEN | PTD | DIS | M4)); /*GPIO_59*/
@@ -374,6 +377,15 @@ static void cm_t3x_set_common_muxconf(void)
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /*MMC1_DAT1*/
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /*MMC1_DAT2*/
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /*MMC1_DAT3*/
+
+ /* SPI */
+ MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M1)); /*MCSPI4_CLK*/
+ MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M1)); /*MCSPI4_SIMO*/
+ MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)); /*MCSPI4_SOMI*/
+ MUX_VAL(CP(MCBSP1_FSX), (IEN | PTU | EN | M1)); /*MCSPI4_CS0*/
+
+ /* display controls */
+ MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | DIS | M4)); /*GPIO_157*/
}
static void cm_t35_set_muxconf(void)
@@ -470,7 +482,7 @@ static void setup_net_chip_gmpc(void)
&ctrl_base->gpmc_nadv_ale);
}
-#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+#ifdef CONFIG_SYS_I2C_OMAP34XX
/*
* Routine: reset_net_chip
* Description: reset the Ethernet controller via TPS65930 GPIO
diff --git a/board/compulab/common/Makefile b/board/compulab/common/Makefile
index 831be2e0e7..6d7d06815c 100644
--- a/board/compulab/common/Makefile
+++ b/board/compulab/common/Makefile
@@ -6,5 +6,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_DRIVER_OMAP34XX_I2C) += eeprom.o
+obj-$(CONFIG_SYS_I2C_OMAP34XX) += eeprom.o
obj-$(CONFIG_LCD) += omap3_display.o
diff --git a/board/compulab/common/eeprom.h b/board/compulab/common/eeprom.h
index cf8c302b2e..e87162930d 100644
--- a/board/compulab/common/eeprom.h
+++ b/board/compulab/common/eeprom.h
@@ -10,7 +10,7 @@
#ifndef _EEPROM_
#define _EEPROM_
-#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+#ifdef CONFIG_SYS_I2C_OMAP34XX
int cl_eeprom_read_mac_addr(uchar *buf);
u32 cl_eeprom_get_board_rev(void);
#else
diff --git a/board/compulab/common/omap3_display.c b/board/compulab/common/omap3_display.c
index ead821eeb7..61707f5b90 100644
--- a/board/compulab/common/omap3_display.c
+++ b/board/compulab/common/omap3_display.c
@@ -14,6 +14,7 @@
#include <stdio_dev.h>
#include <asm/arch/dss.h>
#include <lcd.h>
+#include <scf0403_lcd.h>
#include <asm/arch-omap3/dss.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -22,6 +23,7 @@ enum display_type {
NONE,
DVI,
DVI_CUSTOM,
+ DATA_IMAGE, /* #define CONFIG_SCF0403_LCD to use */
};
#define CMAP_ADDR 0x80100000
@@ -119,6 +121,18 @@ static const struct panel_config preset_dvi_1280X1024 = {
.gfx_format = GFXFORMAT_RGB16,
};
+static const struct panel_config preset_dataimage_480X800 = {
+ .lcd_size = PANEL_LCD_SIZE(480, 800),
+ .timing_h = DSS_HBP(2) | DSS_HFP(2) | DSS_HSW(2),
+ .timing_v = DSS_VBP(17) | DSS_VFP(20) | DSS_VSW(3),
+ .pol_freq = DSS_IVS | DSS_IHS | DSS_IPC | DSS_ONOFF,
+ .divisor = 10 | (1 << 10),
+ .data_lines = LCD_INTERFACE_18_BIT,
+ .panel_type = ACTIVE_DISPLAY,
+ .load_mode = 2,
+ .gfx_format = GFXFORMAT_RGB16,
+};
+
/*
* set_resolution_params()
*
@@ -146,6 +160,13 @@ static enum display_type set_dvi_preset(const struct panel_config preset,
return DVI;
}
+static enum display_type set_dataimage_preset(const struct panel_config preset,
+ int x_res, int y_res)
+{
+ set_preset(preset, x_res, y_res);
+ return DATA_IMAGE;
+}
+
/*
* parse_mode() - parse the mode parameter of custom lcd settings
*
@@ -369,6 +390,8 @@ static enum display_type env_parse_displaytype(char *displaytype)
return set_dvi_preset(preset_dvi_1280X960, 1280, 960);
else if (!strncmp(displaytype, "dvi1280x1024", 12))
return set_dvi_preset(preset_dvi_1280X1024, 1280, 1024);
+ else if (!strncmp(displaytype, "dataimage480x800", 16))
+ return set_dataimage_preset(preset_dataimage_480X800, 480, 800);
return NONE;
}
@@ -401,12 +424,31 @@ void lcd_ctrl_init(void *lcdbase)
clrsetbits_le32(&prcm->clksel_dss, 0xF, 3);
}
+#ifdef CONFIG_SCF0403_LCD
+static void scf0403_enable(void)
+{
+ gpio_direction_output(58, 1);
+ scf0403_init(157);
+}
+#else
+static inline void scf0403_enable(void) {}
+#endif
+
void lcd_enable(void)
{
- if (lcd_def == DVI || lcd_def == DVI_CUSTOM) {
+ switch (lcd_def) {
+ case NONE:
+ return;
+ case DVI:
+ case DVI_CUSTOM:
gpio_direction_output(54, 0); /* Turn on DVI */
- omap3_dss_enable();
+ break;
+ case DATA_IMAGE:
+ scf0403_enable();
+ break;
}
+
+ omap3_dss_enable();
}
void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) {}
diff --git a/board/compulab/trimslice/Makefile b/board/compulab/trimslice/Makefile
index 0818673cbd..f3bd00dbf1 100644
--- a/board/compulab/trimslice/Makefile
+++ b/board/compulab/trimslice/Makefile
@@ -5,8 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-$(shell mkdir -p $(obj)../../nvidia/common)
-
obj-y := trimslice.o
include ../../nvidia/common/common.mk
diff --git a/board/davinci/da8xxevm/u-boot-spl-hawk.lds b/board/davinci/da8xxevm/u-boot-spl-hawk.lds
index e43130aa67..d49c314490 100644
--- a/board/davinci/da8xxevm/u-boot-spl-hawk.lds
+++ b/board/davinci/da8xxevm/u-boot-spl-hawk.lds
@@ -19,8 +19,8 @@ SECTIONS
.text :
{
arch/arm/cpu/arm926ejs/start.o (.text*)
- arch/arm/cpu/arm926ejs/davinci/libdavinci.o (.text*)
- drivers/mtd/nand/libnand.o (.text*)
+ arch/arm/cpu/arm926ejs/davinci/built-in.o (.text*)
+ drivers/mtd/nand/built-in.o (.text*)
*(.text*)
}
diff --git a/board/dvlhost/u-boot.lds b/board/dvlhost/u-boot.lds
index 057d94b62a..ebcaf447b8 100644
--- a/board/dvlhost/u-boot.lds
+++ b/board/dvlhost/u-boot.lds
@@ -16,10 +16,10 @@ SECTIONS
.text : {
*(.__image_copy_start)
arch/arm/cpu/ixp/start.o(.text*)
- net/libnet.o(.text*)
- board/dvlhost/libdvlhost.o(.text*)
- arch/arm/cpu/ixp/libixp.o(.text*)
- drivers/serial/libserial.o(.text*)
+ net/built-in.o(.text*)
+ board/dvlhost/built-in.o(.text*)
+ arch/arm/cpu/ixp/built-in.o(.text*)
+ drivers/serial/built-in.o(.text*)
. = env_offset;
common/env_embedded.o(.ppcenv)
diff --git a/board/emk/top5200/Makefile b/board/emk/top5200/Makefile
index 0930d484fb..b455c26e17 100644
--- a/board/emk/top5200/Makefile
+++ b/board/emk/top5200/Makefile
@@ -5,8 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y := top5200.o ../common/flash.o ../common/vpd.o ../common/am79c874.o
diff --git a/board/emk/top860/Makefile b/board/emk/top860/Makefile
index b2645f6347..0401639ce3 100644
--- a/board/emk/top860/Makefile
+++ b/board/emk/top860/Makefile
@@ -5,7 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
obj-y = top860.o ../common/flash.o ../common/vpd.o ../common/am79c874.o
diff --git a/board/esd/adciop/Makefile b/board/esd/adciop/Makefile
index a096e44418..d0e264de92 100644
--- a/board/esd/adciop/Makefile
+++ b/board/esd/adciop/Makefile
@@ -5,8 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y = adciop.o flash.o ../common/misc.o ../common/pci.o
diff --git a/board/esd/apc405/Makefile b/board/esd/apc405/Makefile
index c6ab1a5e21..ada8bfd3d3 100644
--- a/board/esd/apc405/Makefile
+++ b/board/esd/apc405/Makefile
@@ -5,10 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y = apc405.o \
../common/misc.o \
../common/auto_update.o
diff --git a/board/esd/ar405/Makefile b/board/esd/ar405/Makefile
index 2d16313e8d..dd54f546a6 100644
--- a/board/esd/ar405/Makefile
+++ b/board/esd/ar405/Makefile
@@ -5,8 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y = ar405.o flash.o ../common/misc.o
diff --git a/board/esd/ash405/Makefile b/board/esd/ash405/Makefile
index 4c866ee0aa..aab8de44bc 100644
--- a/board/esd/ash405/Makefile
+++ b/board/esd/ash405/Makefile
@@ -5,10 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y = ash405.o flash.o \
../common/misc.o \
../common/esd405ep_nand.o \
diff --git a/board/esd/cms700/Makefile b/board/esd/cms700/Makefile
index 8cfe3baf79..2bf50066c4 100644
--- a/board/esd/cms700/Makefile
+++ b/board/esd/cms700/Makefile
@@ -5,10 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common/xilinx_jtag)
-endif
-
# Objects for Xilinx JTAG programming (CPLD)
CPLD = ../common/xilinx_jtag/lenval.o \
../common/xilinx_jtag/micro.o \
diff --git a/board/esd/cpci2dp/Makefile b/board/esd/cpci2dp/Makefile
index 1d1502071e..ce2c6dd912 100644
--- a/board/esd/cpci2dp/Makefile
+++ b/board/esd/cpci2dp/Makefile
@@ -5,8 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y = cpci2dp.o flash.o ../common/misc.o ../common/cmd_loadpci.o
diff --git a/board/esd/cpci405/Makefile b/board/esd/cpci405/Makefile
index 1af7e9454d..b140571796 100644
--- a/board/esd/cpci405/Makefile
+++ b/board/esd/cpci405/Makefile
@@ -5,9 +5,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y = cpci405.o flash.o ../common/misc.o ../common/auto_update.o
obj-y += ../common/cmd_loadpci.o
diff --git a/board/esd/cpci5200/Makefile b/board/esd/cpci5200/Makefile
index fb6c0e20e4..8421f54869 100644
--- a/board/esd/cpci5200/Makefile
+++ b/board/esd/cpci5200/Makefile
@@ -5,10 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-# ifneq ($(OBJTREE),$(SRCTREE))
-# $(shell mkdir -p $(obj)../common/xilinx_jtag)
-# endif
-
# Objects for Xilinx JTAG programming (CPLD)
# CPLD = ../common/xilinx_jtag/lenval.o \
# ../common/xilinx_jtag/micro.o \
diff --git a/board/esd/cpci750/Makefile b/board/esd/cpci750/Makefile
index 8b3dc33704..a3300c9f4a 100644
--- a/board/esd/cpci750/Makefile
+++ b/board/esd/cpci750/Makefile
@@ -8,10 +8,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../../Marvell/common)
-endif
-
obj-y = misc.o
obj-y += cpci750.o serial.o ../../Marvell/common/memory.o pci.o \
mv_eth.o mpsc.o i2c.o \
diff --git a/board/esd/cpciiser4/Makefile b/board/esd/cpciiser4/Makefile
index 4d3c34ae42..b8d6bea6dc 100644
--- a/board/esd/cpciiser4/Makefile
+++ b/board/esd/cpciiser4/Makefile
@@ -5,8 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y = cpciiser4.o flash.o ../common/misc.o
diff --git a/board/esd/dasa_sim/Makefile b/board/esd/dasa_sim/Makefile
index f0a5a8f09b..eb9f5f86d0 100644
--- a/board/esd/dasa_sim/Makefile
+++ b/board/esd/dasa_sim/Makefile
@@ -5,8 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y = dasa_sim.o flash.o cmd_dasa_sim.o eeprom.o ../common/pci.o
diff --git a/board/esd/dp405/Makefile b/board/esd/dp405/Makefile
index 6809c673ce..cfcfb66a15 100644
--- a/board/esd/dp405/Makefile
+++ b/board/esd/dp405/Makefile
@@ -5,10 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common/xilinx_jtag)
-endif
-
# Objects for Xilinx JTAG programming (CPLD)
CPLD = ../common/xilinx_jtag/lenval.o \
../common/xilinx_jtag/micro.o \
diff --git a/board/esd/du405/Makefile b/board/esd/du405/Makefile
index 12ce41a9a8..7914eab355 100644
--- a/board/esd/du405/Makefile
+++ b/board/esd/du405/Makefile
@@ -5,8 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y = du405.o flash.o ../common/misc.o
diff --git a/board/esd/hh405/Makefile b/board/esd/hh405/Makefile
index 0507f1b4dd..fba21a3ae2 100644
--- a/board/esd/hh405/Makefile
+++ b/board/esd/hh405/Makefile
@@ -5,10 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y = hh405.o flash.o \
../common/misc.o \
../common/esd405ep_nand.o \
diff --git a/board/esd/hub405/Makefile b/board/esd/hub405/Makefile
index 5447a959c0..99e18b567f 100644
--- a/board/esd/hub405/Makefile
+++ b/board/esd/hub405/Makefile
@@ -5,10 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y = hub405.o flash.o \
../common/misc.o \
../common/esd405ep_nand.o \
diff --git a/board/esd/ocrtc/Makefile b/board/esd/ocrtc/Makefile
index 0d9a6fdc43..44b7d5d072 100644
--- a/board/esd/ocrtc/Makefile
+++ b/board/esd/ocrtc/Makefile
@@ -5,8 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y = ocrtc.o flash.o ../common/misc.o cmd_ocrtc.o
diff --git a/board/esd/pci405/Makefile b/board/esd/pci405/Makefile
index 2f8706bd6e..9e659c796c 100644
--- a/board/esd/pci405/Makefile
+++ b/board/esd/pci405/Makefile
@@ -5,9 +5,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y = pci405.o flash.o ../common/misc.o cmd_pci405.o
obj-y += writeibm.o
diff --git a/board/esd/pf5200/Makefile b/board/esd/pf5200/Makefile
index a9d20c90b1..a54289c073 100644
--- a/board/esd/pf5200/Makefile
+++ b/board/esd/pf5200/Makefile
@@ -5,10 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-# ifneq ($(OBJTREE),$(SRCTREE))
-# $(shell mkdir -p $(obj)../common/xilinx_jtag)
-# endif
-
# Objects for Xilinx JTAG programming (CPLD)
# CPLD = ../common/xilinx_jtag/lenval.o \
# ../common/xilinx_jtag/micro.o \
diff --git a/board/esd/plu405/Makefile b/board/esd/plu405/Makefile
index 45b962f69a..6ffae677b1 100644
--- a/board/esd/plu405/Makefile
+++ b/board/esd/plu405/Makefile
@@ -5,10 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y = plu405.o flash.o \
../common/misc.o \
../common/esd405ep_nand.o \
diff --git a/board/esd/pmc405/Makefile b/board/esd/pmc405/Makefile
index f4aa1c9eea..ad98207f3e 100644
--- a/board/esd/pmc405/Makefile
+++ b/board/esd/pmc405/Makefile
@@ -5,10 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common/xilinx_jtag)
-endif
-
# Objects for Xilinx JTAG programming (CPLD)
CPLD = ../common/xilinx_jtag/lenval.o \
../common/xilinx_jtag/micro.o \
diff --git a/board/esd/pmc405de/Makefile b/board/esd/pmc405de/Makefile
index 7d5b273c0f..b3f6dcd1e7 100644
--- a/board/esd/pmc405de/Makefile
+++ b/board/esd/pmc405de/Makefile
@@ -5,10 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y = pmc405de.o
obj-$(CONFIG_CMD_CHIP_CONFIG) += chip_config.o
obj-y += ../common/cmd_loadpci.o
diff --git a/board/esd/pmc440/Makefile b/board/esd/pmc440/Makefile
index b1318c7429..708e9d138e 100644
--- a/board/esd/pmc440/Makefile
+++ b/board/esd/pmc440/Makefile
@@ -5,10 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y = pmc440.o cmd_pmc440.o sdram.o fpga.o \
../common/cmd_loadpci.o
extra-y += init.o
diff --git a/board/esd/voh405/Makefile b/board/esd/voh405/Makefile
index 8fcfa37dc0..3d82399ed1 100644
--- a/board/esd/voh405/Makefile
+++ b/board/esd/voh405/Makefile
@@ -5,10 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y = voh405.o flash.o \
../common/misc.o \
../common/esd405ep_nand.o \
diff --git a/board/esd/vom405/Makefile b/board/esd/vom405/Makefile
index c8a4a4e4c7..7cf5c0224c 100644
--- a/board/esd/vom405/Makefile
+++ b/board/esd/vom405/Makefile
@@ -5,10 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common/xilinx_jtag)
-endif
-
# Objects for Xilinx JTAG programming (CPLD)
CPLD = ../common/xilinx_jtag/lenval.o \
../common/xilinx_jtag/micro.o \
diff --git a/board/esd/wuh405/Makefile b/board/esd/wuh405/Makefile
index 046ebad301..b9beeffc57 100644
--- a/board/esd/wuh405/Makefile
+++ b/board/esd/wuh405/Makefile
@@ -5,10 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y = wuh405.o flash.o \
../common/misc.o \
../common/esd405ep_nand.o \
diff --git a/board/esteem192e/u-boot.lds b/board/esteem192e/u-boot.lds
index 87642d6b40..59a86bfdc0 100644
--- a/board/esteem192e/u-boot.lds
+++ b/board/esteem192e/u-boot.lds
@@ -18,8 +18,8 @@ SECTIONS
arch/powerpc/cpu/mpc8xx/start.o (.text*)
arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- net/libnet.o (.text*)
- board/esteem192e/libesteem192e.o (.text*)
+ net/built-in.o (.text*)
+ board/esteem192e/built-in.o (.text*)
. = env_offset;
common/env_embedded.o (.text*)
diff --git a/board/exmeritus/hww1u1a/ddr.c b/board/exmeritus/hww1u1a/ddr.c
index 23a71d5af5..e1f6865f42 100644
--- a/board/exmeritus/hww1u1a/ddr.c
+++ b/board/exmeritus/hww1u1a/ddr.c
@@ -9,8 +9,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/exmeritus/hww1u1a/hww1u1a.c b/board/exmeritus/hww1u1a/hww1u1a.c
index 7c11e38d1c..97b84b3224 100644
--- a/board/exmeritus/hww1u1a/hww1u1a.c
+++ b/board/exmeritus/hww1u1a/hww1u1a.c
@@ -13,7 +13,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/io.h>
#include <miiphy.h>
#include <libfdt.h>
@@ -37,6 +37,7 @@ int checkboard(void)
unsigned int gpio_low = 0;
unsigned int gpio_in = 0;
unsigned int i;
+ struct ccsr_ddr __iomem *ddr;
puts("Board: HWW-1U-1A ");
@@ -89,7 +90,7 @@ int checkboard(void)
* and delay a while before we continue.
*/
if (mpc85xx_gpio_get(GPIO_RESETS)) {
- ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+ ddr = (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
puts("Debugger detected... extra device reset enabled!\n");
diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c
index 2d14923139..187c3b3ebc 100644
--- a/board/freescale/b4860qds/ddr.c
+++ b/board/freescale/b4860qds/ddr.c
@@ -9,11 +9,11 @@
#include <common.h>
#include <i2c.h>
#include <hwconfig.h>
+#include <fsl_ddr.h>
#include <asm/mmu.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
-#include <../arch/powerpc/cpu/mpc8xxx/ddr/ddr.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/freescale/bsc9131rdb/ddr.c b/board/freescale/bsc9131rdb/ddr.c
index a9e92f2ae0..339c576256 100644
--- a/board/freescale/bsc9131rdb/ddr.c
+++ b/board/freescale/bsc9131rdb/ddr.c
@@ -8,8 +8,8 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
#include <asm/io.h>
#include <asm/fsl_law.h>
diff --git a/board/freescale/bsc9131rdb/spl_minimal.c b/board/freescale/bsc9131rdb/spl_minimal.c
index dd5ea95e33..bd8560b555 100644
--- a/board/freescale/bsc9131rdb/spl_minimal.c
+++ b/board/freescale/bsc9131rdb/spl_minimal.c
@@ -10,7 +10,7 @@
#include <nand.h>
#include <linux/compiler.h>
#include <asm/fsl_law.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -20,7 +20,8 @@ DECLARE_GLOBAL_DATA_PTR;
*/
static void sdram_init(void)
{
- ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+ struct ccsr_ddr __iomem *ddr =
+ (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
diff --git a/board/freescale/bsc9132qds/bsc9132qds.c b/board/freescale/bsc9132qds/bsc9132qds.c
index a895e4e297..9377280063 100644
--- a/board/freescale/bsc9132qds/bsc9132qds.c
+++ b/board/freescale/bsc9132qds/bsc9132qds.c
@@ -17,10 +17,10 @@
#include <tsec.h>
#include <mmc.h>
#include <netdev.h>
-#include <asm/fsl_ifc.h>
+#include <fsl_ifc.h>
#include <hwconfig.h>
#include <i2c.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#ifdef CONFIG_PCI
#include <pci.h>
@@ -133,16 +133,16 @@ void dsp_ddr_configure(void)
*copy the ddr controller settings from PowerPC side DDR controller
*to the DSP DDR controller as connected DDR memories are similar.
*/
- ccsr_ddr_t __iomem *pa_ddr =
- (ccsr_ddr_t __iomem *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
- ccsr_ddr_t temp_ddr;
- ccsr_ddr_t __iomem *dsp_ddr =
- (ccsr_ddr_t __iomem *)CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR;
+ struct ccsr_ddr __iomem *pa_ddr =
+ (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
+ struct ccsr_ddr temp_ddr;
+ struct ccsr_ddr __iomem *dsp_ddr =
+ (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR;
- memcpy(&temp_ddr, pa_ddr, sizeof(ccsr_ddr_t));
+ memcpy(&temp_ddr, pa_ddr, sizeof(struct ccsr_ddr));
temp_ddr.cs0_bnds = CONFIG_SYS_DDR1_CS0_BNDS;
temp_ddr.sdram_cfg &= ~SDRAM_CFG_MEM_EN;
- memcpy(dsp_ddr, &temp_ddr, sizeof(ccsr_ddr_t));
+ memcpy(dsp_ddr, &temp_ddr, sizeof(struct ccsr_ddr));
dsp_ddr->sdram_cfg |= SDRAM_CFG_MEM_EN;
}
diff --git a/board/freescale/bsc9132qds/ddr.c b/board/freescale/bsc9132qds/ddr.c
index b3130be86d..43f163a2c6 100644
--- a/board/freescale/bsc9132qds/ddr.c
+++ b/board/freescale/bsc9132qds/ddr.c
@@ -8,8 +8,8 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
#include <asm/io.h>
#include <asm/fsl_law.h>
diff --git a/board/freescale/bsc9132qds/spl_minimal.c b/board/freescale/bsc9132qds/spl_minimal.c
index 2bf0a0cfa8..8f71431926 100644
--- a/board/freescale/bsc9132qds/spl_minimal.c
+++ b/board/freescale/bsc9132qds/spl_minimal.c
@@ -10,14 +10,15 @@
#include <nand.h>
#include <linux/compiler.h>
#include <asm/fsl_law.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
static void sdram_init(void)
{
- ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+ struct ccsr_ddr __iomem *ddr =
+ (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
#if CONFIG_DDR_CLK_FREQ == 100000000
__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
diff --git a/board/freescale/c29xpcie/c29xpcie.c b/board/freescale/c29xpcie/c29xpcie.c
index 48c4b308be..f964d6185a 100644
--- a/board/freescale/c29xpcie/c29xpcie.c
+++ b/board/freescale/c29xpcie/c29xpcie.c
@@ -18,7 +18,7 @@
#include <mmc.h>
#include <netdev.h>
#include <pci.h>
-#include <asm/fsl_ifc.h>
+#include <fsl_ifc.h>
#include <asm/fsl_pci.h>
#include "cpld.h"
diff --git a/board/freescale/c29xpcie/ddr.c b/board/freescale/c29xpcie/ddr.c
index 57a9b610ea..968655c1b3 100644
--- a/board/freescale/c29xpcie/ddr.c
+++ b/board/freescale/c29xpcie/ddr.c
@@ -6,8 +6,8 @@
#include <common.h>
#include <asm/fsl_law.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
#include "cpld.h"
diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c
index 18e2ff617b..e7e893a1ae 100644
--- a/board/freescale/corenet_ds/ddr.c
+++ b/board/freescale/corenet_ds/ddr.c
@@ -10,8 +10,8 @@
#include <i2c.h>
#include <hwconfig.h>
#include <asm/mmu.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/freescale/corenet_ds/eth_p4080.c b/board/freescale/corenet_ds/eth_p4080.c
index e5beb55177..5cbec7f5f2 100644
--- a/board/freescale/corenet_ds/eth_p4080.c
+++ b/board/freescale/corenet_ds/eth_p4080.c
@@ -12,7 +12,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
diff --git a/board/freescale/corenet_ds/p3041ds_ddr.c b/board/freescale/corenet_ds/p3041ds_ddr.c
index 5a8ed94b04..4dead9c045 100644
--- a/board/freescale/corenet_ds/p3041ds_ddr.c
+++ b/board/freescale/corenet_ds/p3041ds_ddr.c
@@ -7,7 +7,7 @@
*/
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
fixed_ddr_parm_t fixed_ddr_parm_0[] = {
{0, 0, NULL}
diff --git a/board/freescale/corenet_ds/p4080ds_ddr.c b/board/freescale/corenet_ds/p4080ds_ddr.c
index 844e1d736a..d572a5fbed 100644
--- a/board/freescale/corenet_ds/p4080ds_ddr.c
+++ b/board/freescale/corenet_ds/p4080ds_ddr.c
@@ -7,7 +7,7 @@
*/
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#define CONFIG_SYS_DDR_TIMING_3_1200 0x01030000
#define CONFIG_SYS_DDR_TIMING_0_1200 0xCC550104
diff --git a/board/freescale/corenet_ds/p5020ds_ddr.c b/board/freescale/corenet_ds/p5020ds_ddr.c
index e65de364d7..9aaf6db997 100644
--- a/board/freescale/corenet_ds/p5020ds_ddr.c
+++ b/board/freescale/corenet_ds/p5020ds_ddr.c
@@ -7,7 +7,7 @@
*/
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
fixed_ddr_parm_t fixed_ddr_parm_0[] = {
{0, 0, NULL}
diff --git a/board/freescale/corenet_ds/p5040ds_ddr.c b/board/freescale/corenet_ds/p5040ds_ddr.c
index e65de364d7..9aaf6db997 100644
--- a/board/freescale/corenet_ds/p5040ds_ddr.c
+++ b/board/freescale/corenet_ds/p5040ds_ddr.c
@@ -7,7 +7,7 @@
*/
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
fixed_ddr_parm_t fixed_ddr_parm_0[] = {
{0, 0, NULL}
diff --git a/board/freescale/m52277evb/config.mk b/board/freescale/m52277evb/config.mk
deleted file mode 100644
index 0ffb0a204b..0000000000
--- a/board/freescale/m52277evb/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE)
diff --git a/board/freescale/m52277evb/u-boot.lds b/board/freescale/m52277evb/u-boot.lds
index f3337a3845..70121d9248 100644
--- a/board/freescale/m52277evb/u-boot.lds
+++ b/board/freescale/m52277evb/u-boot.lds
@@ -13,8 +13,8 @@ SECTIONS
.text :
{
arch/m68k/cpu/mcf5227x/start.o (.text*)
- arch/m68k/cpu/mcf5227x/libmcf5227x.o (.text*)
- arch/m68k/lib/libm68k.o (.text*)
+ arch/m68k/cpu/mcf5227x/built-in.o (.text*)
+ arch/m68k/lib/built-in.o (.text*)
*(.text*)
}
diff --git a/board/freescale/m5235evb/config.mk b/board/freescale/m5235evb/config.mk
deleted file mode 100644
index 9ab4582bf8..0000000000
--- a/board/freescale/m5235evb/config.mk
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-/*CONFIG_SYS_TEXT_BASE = 0xFFC00000*/
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE)
diff --git a/board/freescale/m53017evb/u-boot.lds b/board/freescale/m53017evb/u-boot.lds
index ef21299ea9..de8d09bf66 100644
--- a/board/freescale/m53017evb/u-boot.lds
+++ b/board/freescale/m53017evb/u-boot.lds
@@ -12,9 +12,9 @@ SECTIONS
/* Read-only sections, merged into text segment: */
.text :
{
- arch/m68k/cpu/mcf532x/start.o (.text*)
- arch/m68k/cpu/mcf532x/libmcf532x.o (.text*)
- arch/m68k/lib/libm68k.o (.text*)
+ arch/m68k/cpu/mcf532x/start.o (.text*)
+ arch/m68k/cpu/mcf532x/built-in.o (.text*)
+ arch/m68k/lib/built-in.o (.text*)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.text*)
diff --git a/board/freescale/m54451evb/config.mk b/board/freescale/m54451evb/config.mk
deleted file mode 100644
index 0ffb0a204b..0000000000
--- a/board/freescale/m54451evb/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE)
diff --git a/board/freescale/m54455evb/config.mk b/board/freescale/m54455evb/config.mk
deleted file mode 100644
index 0ffb0a204b..0000000000
--- a/board/freescale/m54455evb/config.mk
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
-
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE)
diff --git a/board/freescale/mpc8349emds/Makefile b/board/freescale/mpc8349emds/Makefile
index 23880f52f5..5c315f9f68 100644
--- a/board/freescale/mpc8349emds/Makefile
+++ b/board/freescale/mpc8349emds/Makefile
@@ -7,4 +7,4 @@
obj-y += mpc8349emds.o
obj-$(CONFIG_PCI) += pci.o
-obj-$(CONFIG_FSL_DDR2) += ddr.o
+obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
diff --git a/board/freescale/mpc8349emds/ddr.c b/board/freescale/mpc8349emds/ddr.c
index 3d257d0fbf..aae003d121 100644
--- a/board/freescale/mpc8349emds/ddr.c
+++ b/board/freescale/mpc8349emds/ddr.c
@@ -6,8 +6,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
struct board_specific_parameters {
u32 n_ranks;
diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c
index ec48487294..d9092201aa 100644
--- a/board/freescale/mpc8349emds/mpc8349emds.c
+++ b/board/freescale/mpc8349emds/mpc8349emds.c
@@ -12,8 +12,8 @@
#include <i2c.h>
#include <spi.h>
#include <miiphy.h>
-#ifdef CONFIG_FSL_DDR2
-#include <asm/fsl_ddr_sdram.h>
+#ifdef CONFIG_SYS_FSL_DDR2
+#include <fsl_ddr_sdram.h>
#else
#include <spd_sdram.h>
#endif
@@ -57,7 +57,7 @@ phys_size_t initdram (int board_type)
/* DDR SDRAM - Main SODIMM */
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
#if defined(CONFIG_SPD_EEPROM)
-#ifndef CONFIG_FSL_DDR2
+#ifndef CONFIG_SYS_FSL_DDR2
msize = spd_sdram() * 1024 * 1024;
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
ddr_enable_ecc(msize);
diff --git a/board/freescale/mpc8536ds/ddr.c b/board/freescale/mpc8536ds/ddr.c
index d10370c9f2..ebe3ba460c 100644
--- a/board/freescale/mpc8536ds/ddr.c
+++ b/board/freescale/mpc8536ds/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c
index 5daab692c6..467f4f2013 100644
--- a/board/freescale/mpc8536ds/mpc8536ds.c
+++ b/board/freescale/mpc8536ds/mpc8536ds.c
@@ -12,7 +12,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/io.h>
#include <asm/fsl_serdes.h>
#include <spd.h>
@@ -90,7 +90,7 @@ int checkboard (void)
phys_size_t fixed_sdram (void)
{
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+ struct ccsr_ddr __iomem *ddr = &immap->im_ddr;
uint d_init;
ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
diff --git a/board/freescale/mpc8540ads/ddr.c b/board/freescale/mpc8540ads/ddr.c
index 9e79815278..41d4cfe738 100644
--- a/board/freescale/mpc8540ads/ddr.c
+++ b/board/freescale/mpc8540ads/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c
index 175eefcc6b..93288c7e9c 100644
--- a/board/freescale/mpc8540ads/mpc8540ads.c
+++ b/board/freescale/mpc8540ads/mpc8540ads.c
@@ -14,7 +14,7 @@
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <libfdt.h>
#include <fdt_support.h>
@@ -168,7 +168,8 @@ void lbc_sdram_init(void)
phys_size_t fixed_sdram(void)
{
#ifndef CONFIG_SYS_RAMBOOT
- volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
+ struct ccsr_ddr __iomem *ddr =
+ (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
diff --git a/board/freescale/mpc8541cds/ddr.c b/board/freescale/mpc8541cds/ddr.c
index 78d73b0ea8..d2ac6c4ad4 100644
--- a/board/freescale/mpc8541cds/ddr.c
+++ b/board/freescale/mpc8541cds/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c
index 8115e5c69b..7b264dddd1 100644
--- a/board/freescale/mpc8541cds/mpc8541cds.c
+++ b/board/freescale/mpc8541cds/mpc8541cds.c
@@ -11,7 +11,7 @@
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <ioports.h>
#include <spd_sdram.h>
#include <libfdt.h>
diff --git a/board/freescale/mpc8544ds/ddr.c b/board/freescale/mpc8544ds/ddr.c
index 6cf9bc1d75..aa30cabb03 100644
--- a/board/freescale/mpc8544ds/ddr.c
+++ b/board/freescale/mpc8544ds/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c
index dfd8fa6522..1b33db6f31 100644
--- a/board/freescale/mpc8544ds/mpc8544ds.c
+++ b/board/freescale/mpc8544ds/mpc8544ds.c
@@ -11,7 +11,7 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/io.h>
#include <miiphy.h>
diff --git a/board/freescale/mpc8548cds/ddr.c b/board/freescale/mpc8548cds/ddr.c
index 996ffe206d..b31ea3432e 100644
--- a/board/freescale/mpc8548cds/ddr.c
+++ b/board/freescale/mpc8548cds/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c
index 51e4bb5dcb..ca9b43c6b6 100644
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -12,7 +12,7 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <miiphy.h>
#include <libfdt.h>
diff --git a/board/freescale/mpc8555cds/ddr.c b/board/freescale/mpc8555cds/ddr.c
index 78d73b0ea8..d2ac6c4ad4 100644
--- a/board/freescale/mpc8555cds/ddr.c
+++ b/board/freescale/mpc8555cds/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c
index e2093d1bbc..de5f5669e6 100644
--- a/board/freescale/mpc8555cds/mpc8555cds.c
+++ b/board/freescale/mpc8555cds/mpc8555cds.c
@@ -9,7 +9,7 @@
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <ioports.h>
#include <spd_sdram.h>
#include <libfdt.h>
diff --git a/board/freescale/mpc8560ads/ddr.c b/board/freescale/mpc8560ads/ddr.c
index 9e79815278..41d4cfe738 100644
--- a/board/freescale/mpc8560ads/ddr.c
+++ b/board/freescale/mpc8560ads/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c
index 90a2522cb9..7104e33156 100644
--- a/board/freescale/mpc8560ads/mpc8560ads.c
+++ b/board/freescale/mpc8560ads/mpc8560ads.c
@@ -14,7 +14,7 @@
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <ioports.h>
#include <spd_sdram.h>
#include <miiphy.h>
@@ -373,7 +373,7 @@ void lbc_sdram_init(void)
phys_size_t fixed_sdram(void)
{
#ifndef CONFIG_SYS_RAMBOOT
- volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
+ volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_FSL_DDR_ADDR);
ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
diff --git a/board/freescale/mpc8568mds/ddr.c b/board/freescale/mpc8568mds/ddr.c
index b1f4f1f848..6db92ef2da 100644
--- a/board/freescale/mpc8568mds/ddr.c
+++ b/board/freescale/mpc8568mds/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c
index ae80697b38..a8fdcb5f91 100644
--- a/board/freescale/mpc8568mds/mpc8568mds.c
+++ b/board/freescale/mpc8568mds/mpc8568mds.c
@@ -12,7 +12,7 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <spd_sdram.h>
#include <i2c.h>
diff --git a/board/freescale/mpc8569mds/ddr.c b/board/freescale/mpc8569mds/ddr.c
index 68f686b7e6..ef404b1d6f 100644
--- a/board/freescale/mpc8569mds/ddr.c
+++ b/board/freescale/mpc8569mds/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c
index c928a964f9..cb55e1c98c 100644
--- a/board/freescale/mpc8569mds/mpc8569mds.c
+++ b/board/freescale/mpc8569mds/mpc8569mds.c
@@ -14,7 +14,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/io.h>
#include <spd_sdram.h>
@@ -231,7 +231,8 @@ int checkboard (void)
#if !defined(CONFIG_SPD_EEPROM)
phys_size_t fixed_sdram(void)
{
- volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+ struct ccsr_ddr __iomem *ddr =
+ (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
uint d_init;
out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
diff --git a/board/freescale/mpc8572ds/ddr.c b/board/freescale/mpc8572ds/ddr.c
index 52e4f4224c..2bfc1a170c 100644
--- a/board/freescale/mpc8572ds/ddr.c
+++ b/board/freescale/mpc8572ds/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
struct board_specific_parameters {
u32 n_ranks;
diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c
index 657df6a718..56863222c8 100644
--- a/board/freescale/mpc8572ds/mpc8572ds.c
+++ b/board/freescale/mpc8572ds/mpc8572ds.c
@@ -12,7 +12,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/io.h>
#include <asm/fsl_serdes.h>
#include <miiphy.h>
@@ -62,7 +62,7 @@ int checkboard (void)
phys_size_t fixed_sdram (void)
{
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile ccsr_ddr_t *ddr= &immap->im_ddr;
+ struct ccsr_ddr __iomem *ddr = &immap->im_ddr;
uint d_init;
ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
diff --git a/board/freescale/mpc8610hpcd/Makefile b/board/freescale/mpc8610hpcd/Makefile
index 933ea179ba..2613004f89 100644
--- a/board/freescale/mpc8610hpcd/Makefile
+++ b/board/freescale/mpc8610hpcd/Makefile
@@ -4,6 +4,6 @@
#
obj-y += mpc8610hpcd.o
-obj-$(CONFIG_FSL_DDR2) += ddr.o
+obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
obj-y += law.o
obj-$(CONFIG_FSL_DIU_FB) += mpc8610hpcd_diu.o
diff --git a/board/freescale/mpc8610hpcd/ddr.c b/board/freescale/mpc8610hpcd/ddr.c
index 6cf9bc1d75..aa30cabb03 100644
--- a/board/freescale/mpc8610hpcd/ddr.c
+++ b/board/freescale/mpc8610hpcd/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
index ffdcf2444c..d8740ddacc 100644
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
@@ -10,7 +10,7 @@
#include <asm/processor.h>
#include <asm/immap_86xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <i2c.h>
#include <asm/io.h>
@@ -143,7 +143,7 @@ phys_size_t fixed_sdram(void)
{
#if !defined(CONFIG_SYS_RAMBOOT)
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
+ struct ccsr_ddr __iomem *ddr = &immap->im_ddr1;
uint d_init;
ddr->cs0_bnds = 0x0000001f;
diff --git a/board/freescale/mpc8641hpcn/Makefile b/board/freescale/mpc8641hpcn/Makefile
index 8d53af8227..86c70bcb9d 100644
--- a/board/freescale/mpc8641hpcn/Makefile
+++ b/board/freescale/mpc8641hpcn/Makefile
@@ -7,4 +7,4 @@
obj-y += mpc8641hpcn.o
obj-y += law.o
-obj-$(CONFIG_FSL_DDR2) += ddr.o
+obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
diff --git a/board/freescale/mpc8641hpcn/ddr.c b/board/freescale/mpc8641hpcn/ddr.c
index 651652a77d..7cd0395651 100644
--- a/board/freescale/mpc8641hpcn/ddr.c
+++ b/board/freescale/mpc8641hpcn/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
struct board_specific_parameters {
u32 n_ranks;
diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
index 46a543ebcc..a58b5f9cd4 100644
--- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -9,7 +9,7 @@
#include <asm/processor.h>
#include <asm/immap_86xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/io.h>
#include <libfdt.h>
@@ -64,7 +64,7 @@ fixed_sdram(void)
{
#if !defined(CONFIG_SYS_RAMBOOT)
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
+ struct ccsr_ddr __iomem *ddr = &immap->im_ddr1;
ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
diff --git a/board/freescale/mx31ads/u-boot.lds b/board/freescale/mx31ads/u-boot.lds
index 6cfca2dab6..1cca176c38 100644
--- a/board/freescale/mx31ads/u-boot.lds
+++ b/board/freescale/mx31ads/u-boot.lds
@@ -22,11 +22,11 @@ SECTIONS
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
- arch/arm/cpu/arm1136/start.o (.text*)
- board/freescale/mx31ads/libmx31ads.o (.text*)
- arch/arm/lib/libarm.o (.text*)
- net/libnet.o (.text*)
- drivers/mtd/libmtd.o (.text*)
+ arch/arm/cpu/arm1136/start.o (.text*)
+ board/freescale/mx31ads/built-in.o (.text*)
+ arch/arm/lib/built-in.o (.text*)
+ net/built-in.o (.text*)
+ drivers/mtd/built-in.o (.text*)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o(.text*)
diff --git a/board/freescale/p1010rdb/README b/board/freescale/p1010rdb/README.P1010RDB-PA
index 7f18aaa1b2..158a1b3152 100644
--- a/board/freescale/p1010rdb/README
+++ b/board/freescale/p1010rdb/README.P1010RDB-PA
@@ -204,5 +204,5 @@ Place uImage, p1010rdb.dtb and rootfs files in the TFTP disk area.
=> bootm 1000000 3000000 2000000
-Please contact your local field applications engineer or sales representative
-to obtain related documents, such as P1010-RDB User Guide for details.
+For more details, please refer to P1010RDB User Guide and access website
+www.freescale.com
diff --git a/board/freescale/p1010rdb/README.P1010RDB-PB b/board/freescale/p1010rdb/README.P1010RDB-PB
new file mode 100644
index 0000000000..cf459b339e
--- /dev/null
+++ b/board/freescale/p1010rdb/README.P1010RDB-PB
@@ -0,0 +1,188 @@
+Overview
+=========
+The P1010RDB-PB is a Freescale Reference Design Board that hosts the P1010 SoC.
+P1010RDB-PB is a variation of previous P1010RDB-PA board.
+
+The P1010 is a cost-effective, low-power, highly integrated host processor
+based on a Power Architecture e500v2 core (maximum core frequency 1GHz),that
+addresses the requirements of several routing, gateways, storage, consumer,
+and industrial applications. Applications of interest include the main CPUs and
+I/O processors in network attached storage (NAS), the voice over IP (VoIP)
+router/gateway, and wireless LAN (WLAN) and industrial controllers.
+
+The P1010RDB-PB board features are as following:
+Memory subsystem:
+ - 1G bytes unbuffered DDR3 SDRAM discrete devices (32-bit bus)
+ - 32M bytes NOR flash single-chip memory
+ - 2G bytes NAND flash memory
+ - 16M bytes SPI memory
+ - 256K bit M24256 I2C EEPROM
+ - I2C Board EEPROM 128x8 bit memory
+ - SD/MMC connector to interface with the SD memory card
+Interfaces:
+ - Three 10/100/1000 BaseT Ethernet ports (One RGMII and two SGMII)
+ - PCIe 2.0: two x1 mini-PCIe slots
+ - SATA 2.0: two SATA interfaces
+ - USB 2.0: one USB interface
+ - FlexCAN: two FlexCAN interfaces (revision 2.0B)
+ - UART: one USB-to-Serial interface
+ - TDM: 2 FXS ports connected via an external SLIC to the TDM interface.
+ 1 FXO port connected via a relay to FXS for switchover to POTS
+
+Board connectors:
+ - Mini-ITX power supply connector
+ - JTAG/COP for debugging
+
+POR: support critical POR setting changed via switch on board
+PCB: 6-layer routing (4-layer signals, 2-layer power and ground)
+
+Physical Memory Map on P1010RDB
+===============================
+Address Start Address End Memory type Attributes
+0x0000_0000 0x3fff_ffff DDR 1G Cacheable
+0xa000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable
+0xee00_0000 0xefff_ffff NOR Flash 32M non-cacheable
+0xffc2_0000 0xffc5_ffff PCI IO range 256K non-cacheable
+0xffa0_0000 0xffaf_ffff NAND Flash 1M cacheable
+0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable
+0xffd0_0000 0xffd0_3fff L1 for Stack 16K Cacheable TLB0
+0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
+
+
+Serial Port Configuration on P1010RDB
+=====================================
+Configure the serial port of the attached computer with the following values:
+ -Data rate: 115200 bps
+ -Number of data bits: 8
+ -Parity: None
+ -Number of Stop bits: 1
+ -Flow Control: Hardware/None
+
+
+P1010RDB-PB default DIP-switch settings
+=======================================
+SW1[1:8]= 10101010
+SW2[1:8]= 11011000
+SW3[1:8]= 10010000
+SW4[1:4]= 1010
+SW5[1:8]= 11111010
+
+
+P1010RDB-PB boot mode settings via DIP-switch
+=============================================
+SW4[1:4]= 1111 and SW3[3:4]= 00 for 16bit NOR boot
+SW4[1:4]= 1010 and SW3[3:4]= 01 for 8bit NAND boot
+SW4[1:4]= 0110 and SW3[3:4]= 00 for SPI boot
+SW4[1:4]= 0111 and SW3[3:4]= 10 for SD boot
+Note: 1 stands for 'on', 0 stands for 'off'
+
+
+Switch P1010RDB-PB boot mode via software without setting DIP-switch
+====================================================================
+=> run boot_bank0 (boot from NOR bank0)
+=> run boot_bank1 (boot from NOR bank1)
+=> run boot_nand (boot from NAND flash)
+=> run boot_spi (boot from SPI flash)
+=> run boot_sd (boot from SD card)
+
+
+Frequency combination support on P1010RDB-PB
+=============================================
+SW1[4:7] SW5[1] SW5[5:8] SW2[2] Core(MHz) Platform(MHz) DDR(MT/s)
+0101 1 1010 0 800 400 800
+1001 1 1010 0 800 400 667
+1010 1 1100 0 667 333 667
+1000 0 1010 0 533 266 667
+0101 1 1010 1 1000 400 800
+1001 1 1010 1 1000 400 667
+
+
+Setting of pin mux
+==================
+Since pins multiplexing, TDM and CAN are muxed with SPI flash.
+SDHC is muxed with IFC. IFC and SPI flash are enabled by default.
+
+To enable TDM:
+=> setenv hwconfig fsl_p1010mux:tdm_can=tdm
+=> save;reset
+
+To enable FlexCAN:
+=> setenv hwconfig fsl_p1010mux:tdm_can=can
+=> save;reset
+
+To enable SDHC in case of NOR/NAND/SPI boot
+ a) For temporary use case in runtime without reboot system
+ run 'mux sdhc' in u-boot to validate SDHC with invalidating IFC.
+
+ b) For long-term use case
+ set 'esdhc' in hwconfig and save it.
+
+To enable IFC in case of SD boot
+ a) For temporary use case in runtime without reboot system
+ run 'mux ifc' in u-boot to validate IFC with invalidating SDHC.
+
+ b) For long-term use case
+ set 'ifc' in hwconfig and save it.
+
+
+Build images for different boot mode
+====================================
+First setup cross compile environment on build host
+ $ export ARCH=powerpc
+ $ export CROSS_COMPILE=<your-compiler-path>/powerpc-linux-gnu-
+
+1. For NOR boot
+ $ make P1010RDB-PB_NOR
+
+2. For NAND boot
+ $ make P1010RDB-PB_NAND
+
+3. For SPI boot
+ $ make P1010RDB-PB_SPIFLASH
+
+4. For SD boot
+ $ make P1010RDB-PB_SDCARD
+
+
+Steps to program images to flash for different boot mode
+========================================================
+1. NOR boot
+ => tftp 1000000 u-boot.bin
+ For bank0
+ => pro off all;era eff80000 efffffff;cp.b 1000000 eff80000 $filesize
+ set SW1[8]=0, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board
+
+ For bank1
+ => pro off all;era eef80000 eeffffff;cp.b 1000000 eef80000 $filesize
+ set SW1[8]=1, SW4[1:4]= 1111 and SW3[3:4]= 00, then power on the board
+
+2. NAND boot
+ => tftp 1000000 u-boot-nand.bin
+ => nand erase 0 $filesize; nand write $loadaddr 0 $filesize
+ Set SW4[1:4]= 1010 and SW3[3:4]= 01, then power on the board
+
+3. SPI boot
+ 1) cat p1010rdb-config-header.bin u-boot.bin > u-boot-spi-combined.bin
+ 2) => tftp 1000000 u-boot-spi-combined.bin
+ 3) => sf probe 0; sf erase 0 100000; sf write 1000000 0 100000
+ set SW4[1:4]= 0110 and SW3[3:4]= 00, then power on the board
+
+4. SD boot
+ 1) cat p1010rdb-config-header.bin u-boot.bin > u-boot-sd-combined.bin
+ 2) => tftp 1000000 u-boot-sd-combined.bin
+ 3) => mux sdhc
+ 4) => mmc write 1000000 0 1050
+ set SW4[1:4]= 0111 and SW3[3:4]= 10, then power on the board
+
+
+Boot Linux from network using TFTP on P1010RDB-PB
+=================================================
+Place uImage, p1010rdb.dtb and rootfs files in the TFTP download path.
+ => tftp 1000000 uImage
+ => tftp 2000000 p1010rdb.dtb
+ => tftp 3000000 rootfs.ext2.gz.uboot.p1010rdb
+ => bootm 1000000 3000000 2000000
+
+
+For more details, please refer to P1010RDB-PB User Guide and access website
+www.freescale.com and Freescale QorIQ SDK Infocenter document.
diff --git a/board/freescale/p1010rdb/ddr.c b/board/freescale/p1010rdb/ddr.c
index ab1b41d832..b0d95ea006 100644
--- a/board/freescale/p1010rdb/ddr.c
+++ b/board/freescale/p1010rdb/ddr.c
@@ -8,8 +8,8 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
#include <asm/io.h>
#include <asm/fsl_law.h>
diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c
index e940d2275e..62caf676c6 100644
--- a/board/freescale/p1010rdb/p1010rdb.c
+++ b/board/freescale/p1010rdb/p1010rdb.c
@@ -19,7 +19,7 @@
#include <netdev.h>
#include <pci.h>
#include <asm/fsl_serdes.h>
-#include <asm/fsl_ifc.h>
+#include <fsl_ifc.h>
#include <asm/fsl_pci.h>
#include <hwconfig.h>
#include <i2c.h>
diff --git a/board/freescale/p1010rdb/spl_minimal.c b/board/freescale/p1010rdb/spl_minimal.c
index d0e712eb30..39a5a0f37b 100644
--- a/board/freescale/p1010rdb/spl_minimal.c
+++ b/board/freescale/p1010rdb/spl_minimal.c
@@ -10,7 +10,7 @@
#include <nand.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_law.h>
#include <asm/global_data.h>
@@ -19,7 +19,8 @@ DECLARE_GLOBAL_DATA_PTR;
void sdram_init(void)
{
- ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+ struct ccsr_ddr __iomem *ddr =
+ (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
u32 ddr_ratio;
unsigned long ddr_freq_mhz;
diff --git a/board/freescale/p1022ds/ddr.c b/board/freescale/p1022ds/ddr.c
index 94d2c2b0db..09212bcee8 100644
--- a/board/freescale/p1022ds/ddr.c
+++ b/board/freescale/p1022ds/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
struct board_specific_parameters {
u32 n_ranks;
diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c
index 3d1951cdba..ba789a4daf 100644
--- a/board/freescale/p1022ds/p1022ds.c
+++ b/board/freescale/p1022ds/p1022ds.c
@@ -14,7 +14,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/io.h>
#include <libfdt.h>
diff --git a/board/freescale/p1022ds/spl_minimal.c b/board/freescale/p1022ds/spl_minimal.c
index 8b34396843..6c7e1ac3cb 100644
--- a/board/freescale/p1022ds/spl_minimal.c
+++ b/board/freescale/p1022ds/spl_minimal.c
@@ -9,7 +9,7 @@
#include <asm/io.h>
#include <nand.h>
#include <asm/fsl_law.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
const static u32 sysclk_tbl[] = {
diff --git a/board/freescale/p1023rdb/ddr.c b/board/freescale/p1023rdb/ddr.c
index 9fb61fdab3..d587df527a 100644
--- a/board/freescale/p1023rdb/ddr.c
+++ b/board/freescale/p1023rdb/ddr.c
@@ -8,8 +8,8 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
#include <asm/io.h>
#include <asm/fsl_law.h>
diff --git a/board/freescale/p1023rdb/p1023rdb.c b/board/freescale/p1023rdb/p1023rdb.c
index b52b092069..d2d4f8390a 100644
--- a/board/freescale/p1023rdb/p1023rdb.c
+++ b/board/freescale/p1023rdb/p1023rdb.c
@@ -16,7 +16,7 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_portals.h>
#include <libfdt.h>
#include <fdt_support.h>
diff --git a/board/freescale/p1023rds/p1023rds.c b/board/freescale/p1023rds/p1023rds.c
index 7c54b65c1d..d8c87458e8 100644
--- a/board/freescale/p1023rds/p1023rds.c
+++ b/board/freescale/p1023rds/p1023rds.c
@@ -16,7 +16,7 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_portals.h>
#include <libfdt.h>
#include <fdt_support.h>
@@ -58,7 +58,8 @@ int checkboard(void)
phys_size_t fixed_sdram(void)
{
#ifndef CONFIG_SYS_RAMBOOT
- ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+ struct ccsr_ddr __iomem *ddr =
+ (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1);
diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c
index 5bee22e638..17d3beac39 100644
--- a/board/freescale/p1_p2_rdb/ddr.c
+++ b/board/freescale/p1_p2_rdb/ddr.c
@@ -8,7 +8,7 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/io.h>
#include <asm/fsl_law.h>
diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c
index 81cc0930bc..946d5032e7 100644
--- a/board/freescale/p1_p2_rdb_pc/ddr.c
+++ b/board/freescale/p1_p2_rdb_pc/ddr.c
@@ -10,8 +10,8 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
#include <asm/io.h>
#include <asm/fsl_law.h>
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index 50553dacd9..966abb24a6 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -14,7 +14,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/io.h>
#include <asm/fsl_law.h>
#include <asm/fsl_lbc.h>
diff --git a/board/freescale/p1_p2_rdb_pc/spl_minimal.c b/board/freescale/p1_p2_rdb_pc/spl_minimal.c
index adfa7b1e0f..92437bc787 100644
--- a/board/freescale/p1_p2_rdb_pc/spl_minimal.c
+++ b/board/freescale/p1_p2_rdb_pc/spl_minimal.c
@@ -10,7 +10,7 @@
#include <nand.h>
#include <linux/compiler.h>
#include <asm/fsl_law.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/freescale/p1_twr/ddr.c b/board/freescale/p1_twr/ddr.c
index 67f69d79bd..a2ce75a40d 100644
--- a/board/freescale/p1_twr/ddr.c
+++ b/board/freescale/p1_twr/ddr.c
@@ -8,8 +8,8 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/processor.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
#include <asm/io.h>
#include <asm/fsl_law.h>
diff --git a/board/freescale/p1_twr/p1_twr.c b/board/freescale/p1_twr/p1_twr.c
index ea8db6fc07..0e0d0587d7 100644
--- a/board/freescale/p1_twr/p1_twr.c
+++ b/board/freescale/p1_twr/p1_twr.c
@@ -14,7 +14,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/io.h>
#include <asm/fsl_law.h>
#include <asm/fsl_lbc.h>
diff --git a/board/freescale/p2020come/ddr.c b/board/freescale/p2020come/ddr.c
index da804771fb..b642e1255c 100644
--- a/board/freescale/p2020come/ddr.c
+++ b/board/freescale/p2020come/ddr.c
@@ -5,8 +5,8 @@
*/
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/freescale/p2020ds/ddr.c b/board/freescale/p2020ds/ddr.c
index b12141f296..debe70b18b 100644
--- a/board/freescale/p2020ds/ddr.c
+++ b/board/freescale/p2020ds/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
struct board_specific_parameters {
u32 n_ranks;
@@ -37,7 +37,7 @@ static const struct board_specific_parameters dimm0[] = {
* num| hi| clk| cpo|wrdata|2T
* ranks| mhz|adjst| | delay|
*/
-#ifdef CONFIG_FSL_DDR2
+#ifdef CONFIG_SYS_FSL_DDR2
{2, 549, 4, 0x1f, 2, 0},
{2, 680, 4, 0x1f, 3, 0},
{2, 850, 4, 0x1f, 4, 0},
diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c
index 58a42231a9..a0cf927038 100644
--- a/board/freescale/p2020ds/p2020ds.c
+++ b/board/freescale/p2020ds/p2020ds.c
@@ -12,7 +12,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/io.h>
#include <asm/fsl_serdes.h>
#include <miiphy.h>
@@ -68,7 +68,8 @@ int checkboard(void)
phys_size_t fixed_sdram(void)
{
- volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+ struct ccsr_ddr __iomem *ddr =
+ (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
uint d_init;
ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
diff --git a/board/freescale/p2041rdb/ddr.c b/board/freescale/p2041rdb/ddr.c
index cc1bfae394..b8bbcdf2a8 100644
--- a/board/freescale/p2041rdb/ddr.c
+++ b/board/freescale/p2041rdb/ddr.c
@@ -10,8 +10,8 @@
#include <i2c.h>
#include <hwconfig.h>
#include <asm/mmu.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
struct board_specific_parameters {
diff --git a/board/freescale/t1040qds/Makefile b/board/freescale/t1040qds/Makefile
index a2dba6ff1c..93af9eb6a0 100644
--- a/board/freescale/t1040qds/Makefile
+++ b/board/freescale/t1040qds/Makefile
@@ -4,7 +4,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y += $(BOARD).o
+obj-y += t1040qds.o
obj-y += ddr.o
obj-$(CONFIG_PCI) += pci.o
obj-y += law.o
diff --git a/board/freescale/t1040qds/ddr.c b/board/freescale/t1040qds/ddr.c
index 4fd17da160..da89a36b96 100644
--- a/board/freescale/t1040qds/ddr.c
+++ b/board/freescale/t1040qds/ddr.c
@@ -8,8 +8,8 @@
#include <i2c.h>
#include <hwconfig.h>
#include <asm/mmu.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
#include "ddr.h"
diff --git a/board/freescale/t1040qds/t1040_pbi.cfg b/board/freescale/t1040qds/t1040_pbi.cfg
new file mode 100644
index 0000000000..624398a25d
--- /dev/null
+++ b/board/freescale/t1040qds/t1040_pbi.cfg
@@ -0,0 +1,27 @@
+#PBI commands
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#Configure CPC1 as 512KB SRAM
+09010100 00000000
+09010104 fffc0007
+09010f00 08000000
+09010000 80000000
+#Configure LAW for CPC1
+09000cf0 00000000
+09000cf4 fffc0000
+09000cf8 81000011
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Configure SPI controller
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Flush PBL data
+09138000 00000000
+091380c0 00000000
diff --git a/board/freescale/t1040qds/t1040_rcw.cfg b/board/freescale/t1040qds/t1040_rcw.cfg
new file mode 100644
index 0000000000..0d0dfa5a46
--- /dev/null
+++ b/board/freescale/t1040qds/t1040_rcw.cfg
@@ -0,0 +1,7 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+# serdes protocol 0x66
+0a10000c 0c000000 00000000 00000000
+66000002 00000000 fc027000 01000000
+00000000 00000000 00000000 00030810
+00000000 03fc500f 00000000 00000000
diff --git a/board/freescale/t104xrdb/Makefile b/board/freescale/t104xrdb/Makefile
new file mode 100644
index 0000000000..76c0c94b0e
--- /dev/null
+++ b/board/freescale/t104xrdb/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+
+obj-y += t104xrdb.o
+obj-y += ddr.o
+obj-$(CONFIG_PCI) += pci.o
+obj-y += law.o
+obj-y += tlb.o
diff --git a/board/freescale/t104xrdb/README b/board/freescale/t104xrdb/README
new file mode 100644
index 0000000000..2cd8219c84
--- /dev/null
+++ b/board/freescale/t104xrdb/README
@@ -0,0 +1,200 @@
+Overview
+--------
+The T1040RDB is a Freescale reference board that hosts the T1040 SoC
+(and variants). Variants inclued T1042 presonality of T1040, in which
+case T1040RDB can also be called T1042RDB.
+
+The T1042RDB_PI is a Freescale reference board that hosts the T1042 SoC.
+(a personality of T1040 SoC). The board is similar to T1040RDB but is
+designed specially with low power features targeted for Printing Image Market.
+
+T1040 SoC Overview
+------------------
+The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
+processor cores with high-performance data path acceleration architecture
+and network peripheral interfaces required for networking & telecommunications.
+
+The T1040/T1042 SoC includes the following function and features:
+
+ - Four e5500 cores, each with a private 256 KB L2 cache
+ - 256 KB shared L3 CoreNet platform cache (CPC)
+ - Interconnect CoreNet platform
+ - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
+ support
+ - Data Path Acceleration Architecture (DPAA) incorporating acceleration
+ for the following functions:
+ - Packet parsing, classification, and distribution
+ - Queue management for scheduling, packet sequencing, and congestion
+ management
+ - Cryptography Acceleration (SEC 5.0)
+ - RegEx Pattern Matching Acceleration (PME 2.2)
+ - IEEE Std 1588 support
+ - Hardware buffer management for buffer allocation and deallocation
+ - Ethernet interfaces
+ - Integrated 8-port Gigabit Ethernet switch (T1040 only)
+ - Four 1 Gbps Ethernet controllers
+ - Two RGMII interfaces or one RGMII and one MII interfaces
+ - High speed peripheral interfaces
+ - Four PCI Express 2.0 controllers running at up to 5 GHz
+ - Two SATA controllers supporting 1.5 and 3.0 Gb/s operation
+ - Upto two QSGMII interface
+ - Upto six SGMII interface supporting 1000 Mbps
+ - One SGMII interface supporting upto 2500 Mbps
+ - Additional peripheral interfaces
+ - Two USB 2.0 controllers with integrated PHY
+ - SD/eSDHC/eMMC
+ - eSPI controller
+ - Four I2C controllers
+ - Four UARTs
+ - Four GPIO controllers
+ - Integrated flash controller (IFC)
+ - LCD and HDMI interface (DIU) with 12 bit dual data rate
+ - TDM interface
+ - Multicore programmable interrupt controller (PIC)
+ - Two 8-channel DMA engines
+ - Single source clocking implementation
+ - Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
+
+T1040 SoC Personalities
+-------------------------
+
+T1022 Personality:
+T1022 is a reduced personality of T1040 with less core/clusters.
+
+T1042 Personality:
+T1042 is a reduced personality of T1040 without Integrated 8-port Gigabit
+Ethernet switch. Rest of the blocks are same as T1040
+
+
+T1040RDB board Overview
+-------------------------
+ - SERDES Connections, 8 lanes information:
+ 1: None
+ 2: SGMII
+ 3: QSGMII
+ 4: QSGMII
+ 5: PCIe1 x1 slot
+ 6: mini PCIe connector
+ 7: mini PCIe connector
+ 8: SATA connector
+ - DDR Controller
+ - Supports rates of up to 1600 MHz data-rate
+ - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types.
+ - IFC/Local Bus
+ - NAND flash: 1GB 8-bit NAND flash
+ - NOR: 128MB 16-bit NOR Flash
+ - Ethernet
+ - Two on-board RGMII 10/100/1G ethernet ports.
+ - CPLD
+ - Clocks
+ - System and DDR clock (SYSCLK, “DDRCLK”)
+ - SERDES clocks
+ - Power Supplies
+ - USB
+ - Supports two USB 2.0 ports with integrated PHYs
+ - Two type A ports with 5V@1.5A per port.
+ - SDHC
+ - SDHC/SDXC connector
+ - SPI
+ - On-board 64MB SPI flash
+ - Other IO
+ - Two Serial ports
+ - Four I2C ports
+
+T1042RDB_PI board Overview
+-------------------------
+ - SERDES Connections, 8 lanes information:
+ 1, 2, 3, 4 : PCIe x4 slot
+ 5: mini PCIe connector
+ 6: mini PCIe connector
+ 7: NA
+ 8: SATA connector
+ - DDR Controller
+ - Supports rates of up to 1600 MHz data-rate
+ - Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types.
+ - IFC/Local Bus
+ - NAND flash: 1GB 8-bit NAND flash
+ - NOR: 128MB 16-bit NOR Flash
+ - Ethernet
+ - Two on-board RGMII 10/100/1G ethernet ports.
+ - CPLD
+ - Clocks
+ - System and DDR clock (SYSCLK, “DDRCLK”)
+ - SERDES clocks
+ - Video
+ - DIU supports video at up to 1280x1024x32bpp
+ - Power Supplies
+ - USB
+ - Supports two USB 2.0 ports with integrated PHYs
+ - Two type A ports with 5V@1.5A per port.
+ - SDHC
+ - SDHC/SDXC connector
+ - SPI
+ - On-board 64MB SPI flash
+ - Other IO
+ - Two Serial ports
+ - Four I2C ports
+
+Memory map
+-----------
+The addresses in brackets are physical addresses.
+
+Start Address End Address Description Size
+0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB
+0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
+0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
+0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB
+0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
+0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
+0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
+0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
+0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
+0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
+0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
+0xC_3000_0000 0xC_3FFF_FFFF PCI Express 4 Mem Space 256MB
+0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB
+0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB
+0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB
+0x0_0000_0000 0x0_ffff_ffff DDR 2GB
+
+
+NOR Flash memory Map
+---------------------
+ Start End Definition Size
+0xEFF80000 0xEFFFFFFF u-boot (current bank) 512KB
+0xEFF60000 0xEFF7FFFF u-boot env (current bank) 128KB
+0xEFF40000 0xEFF5FFFF FMAN Ucode (current bank) 128KB
+0xED300000 0xEFF3FFFF rootfs (alt bank) 44MB + 256KB
+0xEC800000 0xEC8FFFF Hardware device tree (alt bank) 1MB
+0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
+0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
+0xEBF80000 0xEBFFFFFF u-boot (alt bank) 512KB
+0xEBF60000 0xEBF7FFFF u-boot env (alt bank) 128KB
+0xEBF40000 0xEBF5FFFF FMAN ucode (alt bank) 128KB
+0xE9300000 0xEBF3FFFF rootfs (current bank) 44MB + 256KB
+0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB
+0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
+0xE8000000 0xE801FFFF RCW (current bank) 128KB
+
+
+Various Software configurations/environment variables/commands
+--------------------------------------------------------------
+The below commands apply to the board
+
+1. U-boot environment variable hwconfig
+ The default hwconfig is:
+ hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1:
+ dr_mode=host,phy_type=utmi
+ Note: For USB gadget set "dr_mode=peripheral"
+
+2. FMAN Ucode versions
+ fsl_fman_ucode_t1040.bin
+
+3. Switching to alternate bank
+ Commands for switching to alternate bank.
+
+ 1. To change from vbank0 to vbank4
+ => qixis_reset altbank (it will boot using vbank4)
+
+ 2.To change from vbank4 to vbank0
+ => qixis reset (it will boot using vbank0)
diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c
new file mode 100644
index 0000000000..9009afa3ad
--- /dev/null
+++ b/board/freescale/t104xrdb/ddr.c
@@ -0,0 +1,132 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+ unsigned int controller_number,
+ unsigned int dimm_number)
+{
+ const char dimm_model[] = "RAW timing DDR";
+
+ if ((controller_number == 0) && (dimm_number == 0)) {
+ memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+ memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+ memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+ }
+
+ return 0;
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ ulong ddr_freq;
+
+ if (ctrl_num > 1) {
+ printf("Not supported controller number %d\n", ctrl_num);
+ return;
+ }
+ if (!pdimm->n_ranks)
+ return;
+
+ pbsp = udimms[0];
+
+ /* Get clk_adjust, cpo, write_data_delay,2t, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm->n_ranks &&
+ (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->cpo_override = pbsp->cpo;
+ popts->write_data_delay =
+ pbsp->write_data_delay;
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->wrlvl_start = pbsp->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ popts->twot_en = pbsp->force_2t;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+ }
+
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found\n");
+ printf("for data rate %lu MT/s\n", ddr_freq);
+ printf("Trying to use the highest speed (%u) parameters\n",
+ pbsp_highest->datarate_mhz_high);
+ popts->cpo_override = pbsp_highest->cpo;
+ popts->write_data_delay = pbsp_highest->write_data_delay;
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->wrlvl_start = pbsp_highest->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ popts->twot_en = pbsp_highest->force_2t;
+ } else {
+ panic("DIMM is not supported by this board");
+ }
+found:
+ debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
+ "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
+ "wrlvl_ctrl_3 0x%x\n",
+ pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
+ pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
+ pbsp->wrlvl_ctl_3);
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+ /*
+ * Write leveling override
+ */
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+
+ /*
+ * rtt and rtt_wr override
+ */
+ popts->rtt_override = 0;
+
+ /* Enable ZQ calibration */
+ popts->zq_en = 1;
+
+ /* DHC_EN =1, ODT = 75 Ohm */
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+}
+
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size;
+
+ puts("Initializing....using SPD\n");
+
+ dram_size = fsl_ddr_sdram();
+
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+
+ puts(" DDR: ");
+ return dram_size;
+}
diff --git a/board/freescale/t104xrdb/ddr.h b/board/freescale/t104xrdb/ddr.h
new file mode 100644
index 0000000000..9276b596ac
--- /dev/null
+++ b/board/freescale/t104xrdb/ddr.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+
+dimm_params_t ddr_raw_timing = {
+ .n_ranks = 2,
+ .rank_density = 2147483648u,
+ .capacity = 4294967296u,
+ .primary_sdram_width = 64,
+ .ec_sdram_width = 8,
+ .registered_dimm = 0,
+ .mirrored_dimm = 1,
+ .n_row_addr = 15,
+ .n_col_addr = 10,
+ .n_banks_per_sdram_device = 8,
+ .edc_config = 2, /* ECC */
+ .burst_lengths_bitmask = 0x0c,
+
+ .tckmin_x_ps = 1071,
+ .caslat_x = 0x2fe << 4, /* 5,6,7,8,9,10,11,13 */
+ .taa_ps = 13910,
+ .twr_ps = 15000,
+ .trcd_ps = 13910,
+ .trrd_ps = 6000,
+ .trp_ps = 13910,
+ .tras_ps = 34000,
+ .trc_ps = 48910,
+ .trfc_ps = 260000,
+ .twtr_ps = 7500,
+ .trtp_ps = 7500,
+ .refresh_rate_ps = 7800000,
+ .tfaw_ps = 35000,
+};
+
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 rank_gb;
+ u32 clk_adjust;
+ u32 wrlvl_start;
+ u32 wrlvl_ctl_2;
+ u32 wrlvl_ctl_3;
+ u32 cpo;
+ u32 write_data_delay;
+ u32 force_2t;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+
+static const struct board_specific_parameters udimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
+ */
+ {2, 1066, 4, 8, 4, 0x05070609, 0x08090a08, 0xff, 2, 0},
+ {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
+ {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0},
+ {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0},
+ {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0},
+ {}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+ udimm0,
+};
+#endif
diff --git a/board/freescale/t104xrdb/law.c b/board/freescale/t104xrdb/law.c
new file mode 100644
index 0000000000..2362d4324b
--- /dev/null
+++ b/board/freescale/t104xrdb/law.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+#ifndef CONFIG_SYS_NO_FLASH
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#endif
+#ifdef CONFIG_SYS_CPLD_BASE_PHYS
+ SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/t104xrdb/pci.c b/board/freescale/t104xrdb/pci.c
new file mode 100644
index 0000000000..c53e3b76a4
--- /dev/null
+++ b/board/freescale/t104xrdb/pci.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, bd_t *bd)
+{
+ FT_FSL_PCI_SETUP;
+}
diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c
new file mode 100644
index 0000000000..6e29d64107
--- /dev/null
+++ b/board/freescale/t104xrdb/t104xrdb.c
@@ -0,0 +1,93 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+
+#include "t104xrdb.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ struct cpu_type *cpu = gd->arch.cpu;
+
+ printf("Board: %sRDB\n", cpu->name);
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+#ifdef CONFIG_SYS_FLASH_BASE
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+ /*
+ * Remap Boot flash region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ /* invalidate existing TLB entry for flash */
+ disable_tlb(flash_esel);
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_256M, 1);
+#endif
+ set_liodns();
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ setup_portals();
+#endif
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ return 0;
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+ pci_of_setup(blob, bd);
+#endif
+
+ fdt_fixup_liodn(blob);
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+ fdt_fixup_dr_usb(blob, bd);
+#endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+ fdt_fixup_fman_ethernet(blob);
+#endif
+}
diff --git a/board/freescale/t104xrdb/t104xrdb.h b/board/freescale/t104xrdb/t104xrdb.h
new file mode 100644
index 0000000000..e7cc0c7b5e
--- /dev/null
+++ b/board/freescale/t104xrdb/t104xrdb.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __T104x_RDB_H__
+#define __T104x_RDB_H__
+
+void fdt_fixup_board_enet(void *blob);
+void pci_of_setup(void *blob, bd_t *bd);
+
+#endif
diff --git a/board/freescale/t104xrdb/tlb.c b/board/freescale/t104xrdb/tlb.c
new file mode 100644
index 0000000000..84f97a41e3
--- /dev/null
+++ b/board/freescale/t104xrdb/tlb.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+ /*
+ * *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
+ * SRAM is at 0xfffc0000, it covered the 0xfffff000.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_256K, 1),
+#else
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_16M, 1),
+
+ /* *I*G* - Flash, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_1G, 1),
+
+ /* *I*G* - PCI I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256K, 1),
+
+ /* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 5, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 7, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 8, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 9, BOOKE_PAGESZ_4M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+ /*
+ * *I*G - NAND
+ * entry 14 and 15 has been used hard coded, they will be disabled
+ * in cpu_init_f, so we use entry 16 for nand.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_64K, 1),
+#endif
+#ifdef CONFIG_SYS_CPLD_BASE
+ SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 11, BOOKE_PAGESZ_256K, 1),
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/t2080qds/Makefile b/board/freescale/t2080qds/Makefile
new file mode 100644
index 0000000000..0b8747b877
--- /dev/null
+++ b/board/freescale/t2080qds/Makefile
@@ -0,0 +1,12 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_T2080QDS) += t2080qds.o
+obj-$(CONFIG_T2080QDS) += eth_t2080qds.o
+obj-$(CONFIG_PCI) += pci.o
+obj-y += ddr.o
+obj-y += law.o
+obj-y += tlb.o
diff --git a/board/freescale/t2080qds/ddr.c b/board/freescale/t2080qds/ddr.c
new file mode 100644
index 0000000000..5db5d21622
--- /dev/null
+++ b/board/freescale/t2080qds/ddr.c
@@ -0,0 +1,127 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 or later as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+ dimm_params_t *pdimm,
+ unsigned int ctrl_num)
+{
+ const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+ ulong ddr_freq;
+
+ if (ctrl_num > 2) {
+ printf("Not supported controller number %d\n", ctrl_num);
+ return;
+ }
+ if (!pdimm->n_ranks)
+ return;
+
+ /*
+ * we use identical timing for all slots. If needed, change the code
+ * to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
+ */
+ if (popts->registered_dimm_en)
+ pbsp = rdimms[0];
+ else
+ pbsp = udimms[0];
+
+
+ /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+ * freqency and n_banks specified in board_specific_parameters table.
+ */
+ ddr_freq = get_ddr_freq(0) / 1000000;
+ while (pbsp->datarate_mhz_high) {
+ if (pbsp->n_ranks == pdimm->n_ranks &&
+ (pdimm->rank_density >> 30) >= pbsp->rank_gb) {
+ if (ddr_freq <= pbsp->datarate_mhz_high) {
+ popts->cpo_override = pbsp->cpo;
+ popts->write_data_delay =
+ pbsp->write_data_delay;
+ popts->clk_adjust = pbsp->clk_adjust;
+ popts->wrlvl_start = pbsp->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ popts->twot_en = pbsp->force_2t;
+ goto found;
+ }
+ pbsp_highest = pbsp;
+ }
+ pbsp++;
+ }
+
+ if (pbsp_highest) {
+ printf("Error: board specific timing not found");
+ printf("for data rate %lu MT/s\n", ddr_freq);
+ printf("Trying to use the highest speed (%u) parameters\n",
+ pbsp_highest->datarate_mhz_high);
+ popts->cpo_override = pbsp_highest->cpo;
+ popts->write_data_delay = pbsp_highest->write_data_delay;
+ popts->clk_adjust = pbsp_highest->clk_adjust;
+ popts->wrlvl_start = pbsp_highest->wrlvl_start;
+ popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+ popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+ popts->twot_en = pbsp_highest->force_2t;
+ } else {
+ panic("DIMM is not supported by this board");
+ }
+found:
+ debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
+ "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
+ "wrlvl_ctrl_3 0x%x\n",
+ pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
+ pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
+ pbsp->wrlvl_ctl_3);
+
+ /*
+ * Factors to consider for half-strength driver enable:
+ * - number of DIMMs installed
+ */
+ popts->half_strength_driver_enable = 0;
+ /*
+ * Write leveling override
+ */
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xf;
+
+ /*
+ * Rtt and Rtt_WR override
+ */
+ popts->rtt_override = 0;
+
+ /* Enable ZQ calibration */
+ popts->zq_en = 1;
+
+ /* DHC_EN =1, ODT = 75 Ohm */
+ popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+ popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+}
+
+phys_size_t initdram(int board_type)
+{
+ phys_size_t dram_size;
+
+ puts("Initializing....using SPD\n");
+
+ dram_size = fsl_ddr_sdram();
+
+ dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+ dram_size *= 0x100000;
+
+ puts(" DDR: ");
+ return dram_size;
+}
diff --git a/board/freescale/t2080qds/ddr.h b/board/freescale/t2080qds/ddr.h
new file mode 100644
index 0000000000..964eaada18
--- /dev/null
+++ b/board/freescale/t2080qds/ddr.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+struct board_specific_parameters {
+ u32 n_ranks;
+ u32 datarate_mhz_high;
+ u32 rank_gb;
+ u32 clk_adjust;
+ u32 wrlvl_start;
+ u32 wrlvl_ctl_2;
+ u32 wrlvl_ctl_3;
+ u32 cpo;
+ u32 write_data_delay;
+ u32 force_2t;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+
+static const struct board_specific_parameters udimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
+ */
+ {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
+ {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0},
+ {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0},
+ {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0},
+ {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
+ {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0},
+ {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
+ {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0},
+ {1, 1800, 2, 5, 6, 0x06070709, 0x110a0b08, 0xff, 2, 0},
+ {1, 1866, 2, 4, 6, 0x06060708, 0x09090a07, 0xff, 2, 0},
+ {1, 1900, 2, 4, 6, 0x06060708, 0x09090a07, 0xff, 2, 0},
+ {1, 2000, 2, 4, 8, 0x090a0b0d, 0x0e0f110b, 0xff, 2, 0},
+ {1, 2133, 2, 4, 8, 0x090a0b0d, 0x0e0f110b, 0xff, 2, 0},
+ {}
+};
+
+static const struct board_specific_parameters rdimm0[] = {
+ /*
+ * memory controller 0
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
+ */
+ {4, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
+ {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906, 0xff, 2, 0},
+ {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
+ {2, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
+ {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0},
+ {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
+ {1, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0},
+ {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0},
+ {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0},
+ {}
+};
+
+/*
+ * The three slots have slightly different timing. The center values are good
+ * for all slots. We use identical speed tables for them. In future use, if
+ * DIMMs require separated tables, make more entries as needed.
+ */
+static const struct board_specific_parameters *udimms[] = {
+ udimm0,
+};
+
+/*
+ * The three slots have slightly different timing. See comments above.
+ */
+static const struct board_specific_parameters *rdimms[] = {
+ rdimm0,
+};
+
+
+#endif
diff --git a/board/freescale/t2080qds/eth_t2080qds.c b/board/freescale/t2080qds/eth_t2080qds.c
new file mode 100644
index 0000000000..3613f93981
--- /dev/null
+++ b/board/freescale/t2080qds/eth_t2080qds.c
@@ -0,0 +1,511 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * Shengzhou Liu <Shengzhou.Liu@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <malloc.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <asm/fsl_dtsec.h>
+#include <asm/fsl_serdes.h>
+#include "../common/qixis.h"
+#include "../common/fman.h"
+#include "t2080qds_qixis.h"
+
+#define EMI_NONE 0xFFFFFFFF
+#define EMI1_RGMII1 0
+#define EMI1_RGMII2 1
+#define EMI1_SLOT1 2
+#define EMI1_SLOT2 6
+#define EMI1_SLOT3 3
+#define EMI1_SLOT4 4
+#define EMI1_SLOT5 5
+#define EMI2 7
+
+static int mdio_mux[NUM_FM_PORTS];
+
+static const char * const mdio_names[] = {
+ "T2080QDS_MDIO_RGMII1",
+ "T2080QDS_MDIO_RGMII2",
+ "T2080QDS_MDIO_SLOT1",
+ "T2080QDS_MDIO_SLOT3",
+ "T2080QDS_MDIO_SLOT4",
+ "T2080QDS_MDIO_SLOT5",
+ "T2080QDS_MDIO_SLOT2",
+ "T2080QDS_MDIO_10GC",
+};
+
+/* Map SerDes1 8 lanes to default slot, will be initialized dynamically */
+static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1};
+
+static const char *T2080qds_mdio_name_for_muxval(u8 muxval)
+{
+ return mdio_names[muxval];
+}
+
+struct mii_dev *mii_dev_for_muxval(u8 muxval)
+{
+ struct mii_dev *bus;
+ const char *name = T2080qds_mdio_name_for_muxval(muxval);
+
+ if (!name) {
+ printf("No bus for muxval %x\n", muxval);
+ return NULL;
+ }
+
+ bus = miiphy_get_dev_by_name(name);
+
+ if (!bus) {
+ printf("No bus by name %s\n", name);
+ return NULL;
+ }
+
+ return bus;
+}
+
+struct T2080qds_mdio {
+ u8 muxval;
+ struct mii_dev *realbus;
+};
+
+static void T2080qds_mux_mdio(u8 muxval)
+{
+ u8 brdcfg4;
+ if (muxval < 7) {
+ brdcfg4 = QIXIS_READ(brdcfg[4]);
+ brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
+ brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
+ QIXIS_WRITE(brdcfg[4], brdcfg4);
+ }
+}
+
+static int T2080qds_mdio_read(struct mii_dev *bus, int addr, int devad,
+ int regnum)
+{
+ struct T2080qds_mdio *priv = bus->priv;
+
+ T2080qds_mux_mdio(priv->muxval);
+
+ return priv->realbus->read(priv->realbus, addr, devad, regnum);
+}
+
+static int T2080qds_mdio_write(struct mii_dev *bus, int addr, int devad,
+ int regnum, u16 value)
+{
+ struct T2080qds_mdio *priv = bus->priv;
+
+ T2080qds_mux_mdio(priv->muxval);
+
+ return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
+}
+
+static int T2080qds_mdio_reset(struct mii_dev *bus)
+{
+ struct T2080qds_mdio *priv = bus->priv;
+
+ return priv->realbus->reset(priv->realbus);
+}
+
+static int T2080qds_mdio_init(char *realbusname, u8 muxval)
+{
+ struct T2080qds_mdio *pmdio;
+ struct mii_dev *bus = mdio_alloc();
+
+ if (!bus) {
+ printf("Failed to allocate T2080QDS MDIO bus\n");
+ return -1;
+ }
+
+ pmdio = malloc(sizeof(*pmdio));
+ if (!pmdio) {
+ printf("Failed to allocate T2080QDS private data\n");
+ free(bus);
+ return -1;
+ }
+
+ bus->read = T2080qds_mdio_read;
+ bus->write = T2080qds_mdio_write;
+ bus->reset = T2080qds_mdio_reset;
+ sprintf(bus->name, T2080qds_mdio_name_for_muxval(muxval));
+
+ pmdio->realbus = miiphy_get_dev_by_name(realbusname);
+
+ if (!pmdio->realbus) {
+ printf("No bus with name %s\n", realbusname);
+ free(bus);
+ free(pmdio);
+ return -1;
+ }
+
+ pmdio->muxval = muxval;
+ bus->priv = pmdio;
+
+ return mdio_register(bus);
+}
+
+void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
+ enum fm_port port, int offset)
+{
+ int phy;
+ char alias[20];
+ struct fixed_link f_link;
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+
+ srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+ if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
+ phy = fm_info_get_phy_address(port);
+ switch (port) {
+ case FM1_DTSEC1:
+ case FM1_DTSEC2:
+ case FM1_DTSEC9:
+ case FM1_DTSEC10:
+ sprintf(alias, "phy_sgmii_s3_%x", phy);
+ fdt_set_phy_handle(fdt, compat, addr, alias);
+ fdt_status_okay_by_alias(fdt, "emi1_slot3");
+ break;
+ case FM1_DTSEC5:
+ case FM1_DTSEC6:
+ if (mdio_mux[port] == EMI1_SLOT1) {
+ sprintf(alias, "phy_sgmii_s1_%x", phy);
+ fdt_set_phy_handle(fdt, compat, addr, alias);
+ fdt_status_okay_by_alias(fdt, "emi1_slot1");
+ } else if (mdio_mux[port] == EMI1_SLOT2) {
+ sprintf(alias, "phy_sgmii_s2_%x", phy);
+ fdt_set_phy_handle(fdt, compat, addr, alias);
+ fdt_status_okay_by_alias(fdt, "emi1_slot2");
+ }
+ break;
+ default:
+ break;
+ }
+
+ } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
+ switch (srds_s1) {
+ case 0x66: /* XFI interface */
+ case 0x6b:
+ case 0x6c:
+ case 0x6d:
+ case 0x71:
+ f_link.phy_id = port;
+ f_link.duplex = 1;
+ f_link.link_speed = 10000;
+ f_link.pause = 0;
+ f_link.asym_pause = 0;
+ /* no PHY for XFI */
+ fdt_delprop(fdt, offset, "phy-handle");
+ fdt_setprop(fdt, offset, "fixed-link", &f_link,
+ sizeof(f_link));
+ break;
+ default:
+ break;
+ }
+ }
+}
+
+void fdt_fixup_board_enet(void *fdt)
+{
+ return;
+}
+
+/*
+ * This function reads RCW to check if Serdes1{E,F,G,H} is configured
+ * as slot 1/2/3 and update the lane_to_slot[] array accordingly
+ */
+static void initialize_lane_to_slot(void)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+
+ srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+ switch (srds_s1) {
+ case 0x51:
+ case 0x5f:
+ case 0x65:
+ case 0x6b:
+ case 0x71:
+ lane_to_slot[5] = 2;
+ lane_to_slot[6] = 2;
+ lane_to_slot[7] = 2;
+ break;
+ case 0xa6:
+ case 0x8e:
+ case 0x8f:
+ case 0x82:
+ case 0x83:
+ case 0xd3:
+ case 0xd9:
+ case 0xcb:
+ lane_to_slot[6] = 2;
+ lane_to_slot[7] = 2;
+ break;
+ case 0xda:
+ lane_to_slot[4] = 3;
+ lane_to_slot[5] = 3;
+ lane_to_slot[6] = 3;
+ lane_to_slot[7] = 3;
+ break;
+ default:
+ break;
+ }
+}
+
+int board_eth_init(bd_t *bis)
+{
+#if defined(CONFIG_FMAN_ENET)
+ int i, idx, lane, slot, interface;
+ struct memac_mdio_info dtsec_mdio_info;
+ struct memac_mdio_info tgec_mdio_info;
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
+ u32 srds_s1;
+
+ srds_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+ srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+
+ initialize_lane_to_slot();
+
+ /* Initialize the mdio_mux array so we can recognize empty elements */
+ for (i = 0; i < NUM_FM_PORTS; i++)
+ mdio_mux[i] = EMI_NONE;
+
+ dtsec_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+
+ dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+ /* Register the 1G MDIO bus */
+ fm_memac_mdio_init(bis, &dtsec_mdio_info);
+
+ tgec_mdio_info.regs =
+ (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+ tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+ /* Register the 10G MDIO bus */
+ fm_memac_mdio_init(bis, &tgec_mdio_info);
+
+ /* Register the muxing front-ends to the MDIO buses */
+ T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
+ T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
+ T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
+ T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
+ T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
+ T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
+ T2080qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
+ T2080qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
+
+ /* Set the two on-board RGMII PHY address */
+ fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
+ if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
+ FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII)
+ fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
+ else
+ fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR);
+
+ switch (srds_s1) {
+ case 0x1c:
+ case 0x95:
+ case 0xa2:
+ case 0x94:
+ /* SGMII in Slot3 */
+ fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
+ /* SGMII in Slot2 */
+ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
+ break;
+ case 0x51:
+ case 0x5f:
+ case 0x65:
+ /* XAUI/HiGig in Slot3 */
+ fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
+ /* SGMII in Slot2 */
+ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
+ break;
+ case 0x66:
+ /*
+ * XFI does not need a PHY to work, but to avoid U-boot use
+ * default PHY address which is zero to a MAC when it found
+ * a MAC has no PHY address, we give a PHY address to XFI
+ * MAC, and should not use a real XAUI PHY address, since
+ * MDIO can access it successfully, and then MDIO thinks
+ * the XAUI card is used for the XFI MAC, which will cause
+ * error.
+ */
+ fm_info_set_phy_address(FM1_10GEC1, 4);
+ fm_info_set_phy_address(FM1_10GEC2, 5);
+ fm_info_set_phy_address(FM1_10GEC3, 6);
+ fm_info_set_phy_address(FM1_10GEC4, 7);
+ break;
+ case 0x6b:
+ fm_info_set_phy_address(FM1_10GEC1, 4);
+ fm_info_set_phy_address(FM1_10GEC2, 5);
+ fm_info_set_phy_address(FM1_10GEC3, 6);
+ fm_info_set_phy_address(FM1_10GEC4, 7);
+ /* SGMII in Slot2 */
+ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+ break;
+ case 0x6c:
+ case 0x6d:
+ /* SGMII in Slot3 */
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
+ break;
+ case 0x71:
+ /* SGMII in Slot3 */
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
+ /* SGMII in Slot2 */
+ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+ break;
+ case 0xa6:
+ case 0x8e:
+ case 0x8f:
+ case 0x82:
+ case 0x83:
+ /* SGMII in Slot3 */
+ fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
+ /* SGMII in Slot2 */
+ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+ break;
+ case 0xa4:
+ case 0x96:
+ case 0x8a:
+ /* SGMII in Slot3 */
+ fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
+ break;
+ case 0xd9:
+ case 0xd3:
+ case 0xcb:
+ /* SGMII in Slot3 */
+ fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
+ /* SGMII in Slot2 */
+ fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
+ break;
+ default:
+ puts("Invalid SerDes1 protocol for T2080QDS\n");
+ break;
+ }
+
+ for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+ idx = i - FM1_DTSEC1;
+ interface = fm_info_get_enet_if(i);
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ SGMII_FM1_DTSEC1 + idx);
+ if (lane < 0)
+ break;
+ slot = lane_to_slot[lane];
+ debug("FM1@DTSEC%u expects SGMII in slot %u\n",
+ idx + 1, slot);
+ if (QIXIS_READ(present2) & (1 << (slot - 1)))
+ fm_disable_port(i);
+
+ switch (slot) {
+ case 1:
+ mdio_mux[i] = EMI1_SLOT1;
+ fm_info_set_mdio(i, mii_dev_for_muxval(
+ mdio_mux[i]));
+ break;
+ case 2:
+ mdio_mux[i] = EMI1_SLOT2;
+ fm_info_set_mdio(i, mii_dev_for_muxval(
+ mdio_mux[i]));
+ break;
+ };
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ if (i == FM1_DTSEC3)
+ mdio_mux[i] = EMI1_RGMII1;
+ else if (i == FM1_DTSEC4 || FM1_DTSEC10)
+ mdio_mux[i] = EMI1_RGMII2;
+ fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+ break;
+ default:
+ break;
+ }
+ }
+
+ for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
+ idx = i - FM1_10GEC1;
+ switch (fm_info_get_enet_if(i)) {
+ case PHY_INTERFACE_MODE_XGMII:
+ if (srds_s1 == 0x51) {
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ XAUI_FM1_MAC9 + idx);
+ } else if ((srds_s1 == 0x5f) || (srds_s1 == 0x65)) {
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ HIGIG_FM1_MAC9 + idx);
+ } else {
+ if (i == FM1_10GEC1 || i == FM1_10GEC2)
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ XFI_FM1_MAC9 + idx);
+ else
+ lane = serdes_get_first_lane(FSL_SRDS_1,
+ XFI_FM1_MAC1 + idx);
+ }
+
+ if (lane < 0)
+ break;
+ mdio_mux[i] = EMI2;
+ fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
+
+ if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) ||
+ (srds_s1 == 0x6c) || (srds_s1 == 0x6d) ||
+ (srds_s1 == 0x71)) {
+ /* As XFI is in cage intead of a slot, so
+ * ensure doesn't disable the corresponding port
+ */
+ break;
+ }
+
+ slot = lane_to_slot[lane];
+ if (QIXIS_READ(present2) & (1 << (slot - 1)))
+ fm_disable_port(i);
+ break;
+ default:
+ break;
+ }
+ }
+
+ cpu_eth_init(bis);
+#endif /* CONFIG_FMAN_ENET */
+
+ return pci_eth_init(bis);
+}
diff --git a/board/freescale/t2080qds/law.c b/board/freescale/t2080qds/law.c
new file mode 100644
index 0000000000..74e2a53a8f
--- /dev/null
+++ b/board/freescale/t2080qds/law.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2008-2012 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#endif
+#ifdef QIXIS_BASE_PHYS
+ SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ /* Limit DCSR to 32M to access NPC Trace Buffer */
+ SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/t2080qds/pci.c b/board/freescale/t2080qds/pci.c
new file mode 100644
index 0000000000..84a89dad4f
--- /dev/null
+++ b/board/freescale/t2080qds/pci.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2007-2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+void pci_init_board(void)
+{
+ fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, bd_t *bd)
+{
+ FT_FSL_PCI_SETUP;
+}
diff --git a/board/freescale/t2080qds/t2080_pbi.cfg b/board/freescale/t2080qds/t2080_pbi.cfg
new file mode 100644
index 0000000000..e200d926fb
--- /dev/null
+++ b/board/freescale/t2080qds/t2080_pbi.cfg
@@ -0,0 +1,41 @@
+#
+# Copyright 2013 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Refer doc/README.pblimage for more details about how-to configure
+# and create PBL boot image
+#
+
+#PBI commands
+#Initialize CPC1
+09010000 00200400
+09138000 00000000
+091380c0 00000100
+#512KB SRAM
+09010100 00000000
+09010104 fff80009
+09010f00 08000000
+#enable CPC1
+09010000 80000000
+#Configure LAW for CPC1
+09000d00 00000000
+09000d04 fff80000
+09000d08 81000012
+#Initialize eSPI controller, default configuration is slow for eSPI to
+#load data, this configuration comes from u-boot eSPI driver.
+09110000 80000403
+09110020 2d170008
+09110024 00100008
+09110028 00100008
+0911002c 00100008
+#Errata for slowing down the MDC clock to make it <= 2.5 MHZ
+094fc030 00008148
+094fd030 00008148
+#Configure alternate space
+09000010 00000000
+09000014 ff000000
+09000018 81000000
+#Flush PBL data
+09138000 00000000
+091380c0 00000000
diff --git a/board/freescale/t2080qds/t2080_rcw.cfg b/board/freescale/t2080qds/t2080_rcw.cfg
new file mode 100644
index 0000000000..c2ad0fda55
--- /dev/null
+++ b/board/freescale/t2080qds/t2080_rcw.cfg
@@ -0,0 +1,8 @@
+#PBL preamble and RCW header
+aa55aa55 010e0100
+#SerDes Protocol: 0x66_0x16
+#Core/DDR: 1533Mhz/2133MT/s
+12100017 15000000 00000000 00000000
+66160002 00008400 e8104000 c1000000
+00000000 00000000 00000000 000307fc
+00000000 00000000 00000000 00000004
diff --git a/board/freescale/t2080qds/t2080qds.c b/board/freescale/t2080qds/t2080qds.c
new file mode 100644
index 0000000000..cac32fe73c
--- /dev/null
+++ b/board/freescale/t2080qds/t2080qds.c
@@ -0,0 +1,324 @@
+/*
+ * Copyright 2009-2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+
+#include "../common/qixis.h"
+#include "../common/vsc3316_3308.h"
+#include "t2080qds.h"
+#include "t2080qds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+ char buf[64];
+ u8 sw;
+ struct cpu_type *cpu = gd->arch.cpu;
+ static const char *freq[4] = {
+ "100.00MHZ(from 8T49N222A)", "125.00MHz",
+ "156.25MHZ", "100.00MHz"
+ };
+
+ printf("Board: %sQDS, ", cpu->name);
+ sw = QIXIS_READ(arch);
+ printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
+ printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
+
+ sw = QIXIS_READ(brdcfg[0]);
+ sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+ if (sw < 0x8)
+ printf("vBank%d\n", sw);
+ else if (sw == 0x8)
+ puts("Promjet\n");
+ else if (sw == 0x9)
+ puts("NAND\n");
+ else
+ printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+
+ printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver),
+ qixis_read_tag(buf), (int)qixis_read_minor());
+ /* the timestamp string contains "\n" at the end */
+ printf(" on %s", qixis_read_time(buf));
+
+ puts("SERDES Reference Clocks:\n");
+ sw = QIXIS_READ(brdcfg[2]);
+ printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[sw >> 6],
+ freq[(sw >> 4) & 0x3]);
+ printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[(sw & 0xf) >> 2],
+ freq[sw & 0x3]);
+
+ return 0;
+}
+
+int select_i2c_ch_pca9547(u8 ch)
+{
+ int ret;
+
+ ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+ if (ret) {
+ puts("PCA: failed to select proper channel\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+int brd_mux_lane_to_slot(void)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 srds_prtcl_s1, srds_prtcl_s2;
+
+ srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+ srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+ srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+ srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+
+ switch (srds_prtcl_s1) {
+ case 0:
+ /* SerDes1 is not enabled */
+ break;
+ case 0x1c:
+ case 0x95:
+ case 0xa2:
+ case 0x94:
+ /* SD1(A:D) => SLOT3 SGMII
+ * SD1(G:H) => SLOT1 SGMII
+ */
+ QIXIS_WRITE(brdcfg[12], 0x58);
+ break;
+ case 0x51:
+ /* SD1(A:D) => SLOT3 XAUI
+ * SD1(E) => SLOT1 PCIe4
+ * SD1(F:H) => SLOT2 SGMII
+ */
+ QIXIS_WRITE(brdcfg[12], 0x15);
+ break;
+ case 0x66:
+ case 0x67:
+ /* SD1(A:D) => XFI cage
+ * SD1(E:H) => SLOT1 PCIe4
+ */
+ QIXIS_WRITE(brdcfg[12], 0xfe);
+ break;
+ case 0x6b:
+ /* SD1(A:D) => XFI cage
+ * SD1(E) => SLOT1 PCIe4
+ * SD1(F:H) => SLOT2 SGMII
+ */
+ QIXIS_WRITE(brdcfg[12], 0xf1);
+ break;
+ case 0x6c:
+ case 0x6d:
+ /* SD1(A:B) => XFI cage
+ * SD1(C:D) => SLOT3 SGMII
+ * SD1(E:H) => SLOT1 PCIe4
+ */
+ QIXIS_WRITE(brdcfg[12], 0xda);
+ break;
+ default:
+ printf("WARNING: unsupported for SerDes1 Protocol %d\n",
+ srds_prtcl_s1);
+ return -1;
+ }
+
+ switch (srds_prtcl_s2) {
+ case 0:
+ /* SerDes2 is not enabled */
+ break;
+ case 0x01:
+ case 0x02:
+ /* SD2(A:H) => SLOT4 PCIe1 */
+ QIXIS_WRITE(brdcfg[13], 0x20);
+ break;
+ case 0x15:
+ case 0x16:
+ /*
+ * SD2(A:D) => SLOT4 PCIe1
+ * SD2(E:F) => SLOT5 PCIe2
+ * SD2(G:H) => SATA1,SATA2
+ */
+ QIXIS_WRITE(brdcfg[13], 0xb0);
+ break;
+ case 0x18:
+ /*
+ * SD2(A:D) => SLOT4 PCIe1
+ * SD2(E:F) => SLOT5 Aurora
+ * SD2(G:H) => SATA1,SATA2
+ */
+ QIXIS_WRITE(brdcfg[13], 0x70);
+ break;
+ case 0x1f:
+ /*
+ * SD2(A:D) => SLOT4 PCIe1
+ * SD2(E:H) => SLOT5 PCIe2
+ */
+ QIXIS_WRITE(brdcfg[13], 0xa0);
+ break;
+ case 0x29:
+ case 0x2d:
+ case 0x2e:
+ /*
+ * SD2(A:D) => SLOT4 SRIO2
+ * SD2(E:H) => SLOT5 SRIO1
+ */
+ QIXIS_WRITE(brdcfg[13], 0x50);
+ break;
+ default:
+ printf("WARNING: unsupported for SerDes2 Protocol %d\n",
+ srds_prtcl_s2);
+ return -1;
+ }
+ return 0;
+}
+
+int board_early_init_r(void)
+{
+ const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+ const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+ /*
+ * Remap Boot flash + PROMJET region to caching-inhibited
+ * so that flash can be erased properly.
+ */
+
+ /* Flush d-cache and invalidate i-cache of any FLASH data */
+ flush_dcache();
+ invalidate_icache();
+
+ /* invalidate existing TLB entry for flash + promjet */
+ disable_tlb(flash_esel);
+
+ set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+ set_liodns();
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ setup_portals();
+#endif
+
+ /* Disable remote I2C connection to qixis fpga */
+ QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
+
+ brd_mux_lane_to_slot();
+ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+
+ return 0;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+ u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
+ /* use accurate clock measurement */
+ int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
+ int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
+ u32 val;
+
+ val = freq * base;
+ if (val) {
+ debug("SYS Clock measurement is: %d\n", val);
+ return val;
+ } else {
+ printf("Warning: SYS clock measurement is invalid, ");
+ printf("using value from brdcfg1.\n");
+ }
+#endif
+
+ switch (sysclk_conf & 0x0F) {
+ case QIXIS_SYSCLK_83:
+ return 83333333;
+ case QIXIS_SYSCLK_100:
+ return 100000000;
+ case QIXIS_SYSCLK_125:
+ return 125000000;
+ case QIXIS_SYSCLK_133:
+ return 133333333;
+ case QIXIS_SYSCLK_150:
+ return 150000000;
+ case QIXIS_SYSCLK_160:
+ return 160000000;
+ case QIXIS_SYSCLK_166:
+ return 166666666;
+ }
+ return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+ u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
+ /* use accurate clock measurement */
+ int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
+ int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
+ u32 val;
+
+ val = freq * base;
+ if (val) {
+ debug("DDR Clock measurement is: %d\n", val);
+ return val;
+ } else {
+ printf("Warning: DDR clock measurement is invalid, ");
+ printf("using value from brdcfg1.\n");
+ }
+#endif
+
+ switch ((ddrclk_conf & 0x30) >> 4) {
+ case QIXIS_DDRCLK_100:
+ return 100000000;
+ case QIXIS_DDRCLK_125:
+ return 125000000;
+ case QIXIS_DDRCLK_133:
+ return 133333333;
+ }
+ return 66666666;
+}
+
+int misc_init_r(void)
+{
+ return 0;
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+ phys_addr_t base;
+ phys_size_t size;
+
+ ft_cpu_setup(blob, bd);
+
+ base = getenv_bootm_low();
+ size = getenv_bootm_size();
+
+ fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+ pci_of_setup(blob, bd);
+#endif
+
+ fdt_fixup_liodn(blob);
+ fdt_fixup_dr_usb(blob, bd);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+ fdt_fixup_fman_ethernet(blob);
+ fdt_fixup_board_enet(blob);
+#endif
+}
diff --git a/board/freescale/t2080qds/t2080qds.h b/board/freescale/t2080qds/t2080qds.h
new file mode 100644
index 0000000000..39fcef28c3
--- /dev/null
+++ b/board/freescale/t2080qds/t2080qds.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2011-2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CORENET_DS_H__
+#define __CORENET_DS_H__
+
+void fdt_fixup_board_enet(void *blob);
+void pci_of_setup(void *blob, bd_t *bd);
+
+#endif
diff --git a/board/freescale/t2080qds/t2080qds_qixis.h b/board/freescale/t2080qds/t2080qds_qixis.h
new file mode 100644
index 0000000000..fc83da707f
--- /dev/null
+++ b/board/freescale/t2080qds/t2080qds_qixis.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __T2080QDS_QIXIS_H__
+#define __T2080QDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for T2080QDS */
+
+#define QIXIS_SRDS1CLK_122 0x5a
+#define QIXIS_SRDS1CLK_125 0x5e
+
+
+/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
+#define BRDCFG4_EMISEL_MASK 0xE0
+#define BRDCFG4_EMISEL_SHIFT 5
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66 0x0
+#define QIXIS_SYSCLK_83 0x1
+#define QIXIS_SYSCLK_100 0x2
+#define QIXIS_SYSCLK_125 0x3
+#define QIXIS_SYSCLK_133 0x4
+#define QIXIS_SYSCLK_150 0x5
+#define QIXIS_SYSCLK_160 0x6
+#define QIXIS_SYSCLK_166 0x7
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66 0x0
+#define QIXIS_DDRCLK_100 0x1
+#define QIXIS_DDRCLK_125 0x2
+#define QIXIS_DDRCLK_133 0x3
+
+#define BRDCFG5_IRE 0x20 /* i2c Remote i2c1 enable */
+
+#define BRDCFG12_SD3EN_MASK 0x20
+#define BRDCFG12_SD3MX_MASK 0x08
+#define BRDCFG12_SD3MX_SLOT5 0x08
+#define BRDCFG12_SD3MX_SLOT6 0x00
+#define BRDCFG12_SD4EN_MASK 0x04
+#define BRDCFG12_SD4MX_MASK 0x03
+#define BRDCFG12_SD4MX_SLOT7 0x02
+#define BRDCFG12_SD4MX_SLOT8 0x01
+#define BRDCFG12_SD4MX_AURO_SATA 0x00
+#endif
diff --git a/board/freescale/t2080qds/tlb.c b/board/freescale/t2080qds/tlb.c
new file mode 100644
index 0000000000..62cd11033a
--- /dev/null
+++ b/board/freescale/t2080qds/tlb.c
@@ -0,0 +1,146 @@
+/*
+ * Copyright 2008-2013 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+ /* TLB 0 - for temp stack in cache */
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+ SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+ CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 0, BOOKE_PAGESZ_4K, 0),
+
+ /* TLB 1 */
+ /* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+ /*
+ * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
+ * SRAM is at 0xfff00000, it covered the 0xfffff000.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
+#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
+ /*
+ * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
+ * space is at 0xfff00000, it covered the 0xfffff000.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
+ CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_1M, 1),
+#else
+ SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
+
+ /* *I*G* - CCSRBAR */
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 1, BOOKE_PAGESZ_16M, 1),
+
+ /* *I*G* - Flash, localbus */
+ /* This will be changed to *I*G* after relocation to RAM. */
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCIe 1, 0x80000000 */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 3, BOOKE_PAGESZ_512M, 1),
+
+ /* *I*G* - PCIe 2, 0xa0000000 */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 4, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCIe 3, 0xb0000000 */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_256M, 1),
+
+
+ /* *I*G* - PCIe 4, 0xc0000000 */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_256M, 1),
+
+ /* *I*G* - PCI I/O */
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 7, BOOKE_PAGESZ_256K, 1),
+
+ /* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 9, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 10, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 11, BOOKE_PAGESZ_16M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
+ CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 12, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+ SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 13, BOOKE_PAGESZ_32M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+ /*
+ * *I*G - NAND
+ * entry 14 and 15 has been used hard coded, they will be disabled
+ * in cpu_init_f, so we use entry 16 for nand.
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 16, BOOKE_PAGESZ_64K, 1),
+#endif
+#ifdef QIXIS_BASE_PHYS
+ SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 17, BOOKE_PAGESZ_4K, 1),
+#endif
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+ /*
+ * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
+ * fetching ucode and ENV from master
+ */
+ SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
+ CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+ 0, 18, BOOKE_PAGESZ_1M, 1),
+#endif
+
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c
index d70c31051d..7586cc3c4b 100644
--- a/board/freescale/t4qds/ddr.c
+++ b/board/freescale/t4qds/ddr.c
@@ -10,8 +10,8 @@
#include <i2c.h>
#include <hwconfig.h>
#include <asm/mmu.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
#include "ddr.h"
diff --git a/board/freescale/t4qds/eth.c b/board/freescale/t4qds/eth.c
index b5f488bcba..24cf907430 100644
--- a/board/freescale/t4qds/eth.c
+++ b/board/freescale/t4qds/eth.c
@@ -12,7 +12,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
diff --git a/board/gaisler/gr_cpci_ax2000/config.mk b/board/gaisler/gr_cpci_ax2000/config.mk
index e9c60286ce..309c879489 100644
--- a/board/gaisler/gr_cpci_ax2000/config.mk
+++ b/board/gaisler/gr_cpci_ax2000/config.mk
@@ -18,5 +18,4 @@ CONFIG_SYS_TEXT_BASE = 0x00000000
# U-BOOT IN SDRAM
#CONFIG_SYS_TEXT_BASE = 0x60000000
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) \
- -I$(TOPDIR)/board
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board
diff --git a/board/gaisler/gr_ep2s60/config.mk b/board/gaisler/gr_ep2s60/config.mk
index 6c31a17f8c..d57efae158 100644
--- a/board/gaisler/gr_ep2s60/config.mk
+++ b/board/gaisler/gr_ep2s60/config.mk
@@ -16,5 +16,4 @@ CONFIG_SYS_TEXT_BASE = 0x00000000
# U-BOOT IN SDRAM
#CONFIG_SYS_TEXT_BASE = 0x40000000
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) \
- -I$(TOPDIR)/board
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board
diff --git a/board/gaisler/gr_xc3s_1500/config.mk b/board/gaisler/gr_xc3s_1500/config.mk
index 3b59cca5e6..e87320be99 100644
--- a/board/gaisler/gr_xc3s_1500/config.mk
+++ b/board/gaisler/gr_xc3s_1500/config.mk
@@ -15,5 +15,4 @@ CONFIG_SYS_TEXT_BASE = 0x00000000
# U-BOOT IN RAM
#CONFIG_SYS_TEXT_BASE = 0x40000000
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) \
- -I$(TOPDIR)/board
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board
diff --git a/board/gaisler/grsim/config.mk b/board/gaisler/grsim/config.mk
index d98ed54c07..df26f82c9c 100644
--- a/board/gaisler/grsim/config.mk
+++ b/board/gaisler/grsim/config.mk
@@ -15,5 +15,4 @@ CONFIG_SYS_TEXT_BASE = 0x00000000
# U-BOOT IN RAM
#CONFIG_SYS_TEXT_BASE = 0x40000000
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) \
- -I$(TOPDIR)/board
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board
diff --git a/board/gaisler/grsim_leon2/config.mk b/board/gaisler/grsim_leon2/config.mk
index 59e4e31690..99f9a68725 100644
--- a/board/gaisler/grsim_leon2/config.mk
+++ b/board/gaisler/grsim_leon2/config.mk
@@ -15,5 +15,4 @@ CONFIG_SYS_TEXT_BASE = 0x00000000
# RUN U-BOOT FROM RAM
#CONFIG_SYS_TEXT_BASE = 0x40000000
-PLATFORM_CPPFLAGS += -DCONFIG_SYS_TEXT_BASE=$(CONFIG_SYS_TEXT_BASE) \
- -I$(TOPDIR)/board
+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board
diff --git a/board/gdsys/p1022/controlcenterd.c b/board/gdsys/p1022/controlcenterd.c
index 81c22bc94c..8ccd9ce6ba 100644
--- a/board/gdsys/p1022/controlcenterd.c
+++ b/board/gdsys/p1022/controlcenterd.c
@@ -29,7 +29,7 @@
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <asm/io.h>
#include <libfdt.h>
diff --git a/board/gdsys/p1022/ddr.c b/board/gdsys/p1022/ddr.c
index 4a652de430..7596736bfd 100644
--- a/board/gdsys/p1022/ddr.c
+++ b/board/gdsys/p1022/ddr.c
@@ -12,8 +12,8 @@
#include <common.h>
#include <i2c.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm,
unsigned int ctrl_num)
diff --git a/board/genietv/u-boot.lds b/board/genietv/u-boot.lds
index e217f06819..70ab702fd9 100644
--- a/board/genietv/u-boot.lds
+++ b/board/genietv/u-boot.lds
@@ -18,11 +18,11 @@ SECTIONS
arch/powerpc/cpu/mpc8xx/start.o (.text*)
arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- lib/libgeneric.o (.text*)
- net/libnet.o (.text*)
- arch/powerpc/cpu/mpc8xx/libmpc8xx.o (.text*)
- board/genietv/libgenietv.o (.text*)
- arch/powerpc/lib/libpowerpc.o (.text*)
+ lib/built-in.o (.text*)
+ net/built-in.o (.text*)
+ arch/powerpc/cpu/mpc8xx/built-in.o (.text*)
+ board/genietv/built-in.o (.text*)
+ arch/powerpc/lib/built-in.o (.text*)
*(.text.do_load_serial*)
*(.text.do_mem_*)
*(.text.do_bootm*)
diff --git a/board/h2200/Makefile b/board/h2200/Makefile
index b654a96e0b..d4fa15344c 100644
--- a/board/h2200/Makefile
+++ b/board/h2200/Makefile
@@ -10,8 +10,5 @@ obj-y := h2200.o
extra-y := h2200-header.bin
-$(obj)h2200-header.o: h2200-header.S
- $(CC) $(CFLAGS) -c -o $@ $<
-
$(obj)h2200-header.bin: $(obj)h2200-header.o
$(OBJCOPY) -O binary $< $@
diff --git a/board/hermes/u-boot.lds b/board/hermes/u-boot.lds
index 9419f83a70..0309860391 100644
--- a/board/hermes/u-boot.lds
+++ b/board/hermes/u-boot.lds
@@ -17,7 +17,7 @@ SECTIONS
/* the sector layout of our flash chips! XXX FIXME XXX */
arch/powerpc/cpu/mpc8xx/start.o (.text*)
arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- board/hermes/libhermes.o (.text*)
+ board/hermes/built-in.o (.text*)
. = env_offset;
common/env_embedded.o (.text*)
diff --git a/board/qemu-malta/Makefile b/board/imgtec/malta/Makefile
index 5d727f6f52..19dd3a3c3b 100644
--- a/board/qemu-malta/Makefile
+++ b/board/imgtec/malta/Makefile
@@ -5,5 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y = qemu-malta.o
+obj-y = malta.o
obj-y += lowlevel_init.o
+obj-y += superio.o
diff --git a/board/imgtec/malta/flash-malta-boot.tcl b/board/imgtec/malta/flash-malta-boot.tcl
new file mode 100644
index 0000000000..0eedf07ace
--- /dev/null
+++ b/board/imgtec/malta/flash-malta-boot.tcl
@@ -0,0 +1,40 @@
+#
+# Copyright (C) 2013 Imagination Technologies
+#
+# Programs a MIPS Malta boot flash with a flat binary image.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+proc flash-boot { binfile } {
+ puts "flash monitor binary $binfile"
+ config Coherent on
+ config CoherencyDuringLoad on
+
+ if {[endian]=="big"} {
+ puts "CPU in BE mode"
+ flash device sharp_16x32_be;
+ } else {
+ puts "CPU in LE mode"
+ flash device sharp_16x32;
+ }
+
+ flash clear all;
+ flash set 0xBE000000..0xBE0FFFFF
+ flash erase sector 0xbe000000;
+ flash erase sector 0xbe020000;
+ flash erase sector 0xbe040000;
+ flash erase sector 0xbe060000;
+ flash erase sector 0xbe080000;
+ flash erase sector 0xbe0a0000;
+ flash erase sector 0xbe0c0000;
+ flash erase sector 0xbe0e0000;
+ puts "finished erasing boot flash";
+
+ puts "programming flash, please be patient"
+ load bin 0xbe000000 $binfile size4
+
+ flash clear all
+ config CoherencyDuringLoad off
+ puts "finished programming boot flash";
+}
diff --git a/board/imgtec/malta/lowlevel_init.S b/board/imgtec/malta/lowlevel_init.S
new file mode 100644
index 0000000000..ae09c27d07
--- /dev/null
+++ b/board/imgtec/malta/lowlevel_init.S
@@ -0,0 +1,238 @@
+/*
+ * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <config.h>
+#include <gt64120.h>
+#include <msc01.h>
+#include <pci.h>
+
+#include <asm/addrspace.h>
+#include <asm/regdef.h>
+#include <asm/malta.h>
+#include <asm/mipsregs.h>
+
+#ifdef CONFIG_SYS_BIG_ENDIAN
+#define CPU_TO_GT32(_x) ((_x))
+#else
+#define CPU_TO_GT32(_x) ( \
+ (((_x) & 0xff) << 24) | (((_x) & 0xff00) << 8) | \
+ (((_x) & 0xff0000) >> 8) | (((_x) & 0xff000000) >> 24))
+#endif
+
+ .text
+ .set noreorder
+ .set mips32
+
+ .globl lowlevel_init
+lowlevel_init:
+ /* disable any L2 cache for now */
+ sync
+ mfc0 t0, CP0_CONFIG, 2
+ ori t0, t0, 0x1 << 12
+ mtc0 t0, CP0_CONFIG, 2
+
+ /* detect the core card */
+ li t0, KSEG1ADDR(MALTA_REVISION)
+ lw t0, 0(t0)
+ srl t0, t0, MALTA_REVISION_CORID_SHF
+ andi t0, t0, (MALTA_REVISION_CORID_MSK >> \
+ MALTA_REVISION_CORID_SHF)
+
+ /* core cards using the gt64120 system controller */
+ li t1, MALTA_REVISION_CORID_CORE_LV
+ beq t0, t1, _gt64120
+
+ /* core cards using the MSC01 system controller */
+ li t1, MALTA_REVISION_CORID_CORE_FPGA6
+ beq t0, t1, _msc01
+ nop
+
+ /* unknown system controller */
+ b .
+ nop
+
+ /*
+ * Load BAR registers of GT64120 as done by YAMON
+ *
+ * based on a patch sent by Antony Pavlov <antonynpavlov@gmail.com>
+ * to the barebox mailing list.
+ * The subject of the original patch:
+ * 'MIPS: qemu-malta: add YAMON-style GT64120 memory map'
+ * URL:
+ * http://www.mail-archive.com/barebox@lists.infradead.org/msg06128.html
+ *
+ * based on write_bootloader() in qemu.git/hw/mips_malta.c
+ * see GT64120 manual and qemu.git/hw/gt64xxx.c for details
+ */
+_gt64120:
+ /* move GT64120 registers from 0x14000000 to 0x1be00000 */
+ li t1, KSEG1ADDR(GT_DEF_BASE)
+ li t0, CPU_TO_GT32(0xdf000000)
+ sw t0, GT_ISD_OFS(t1)
+
+ /* setup MEM-to-PCI0 mapping */
+ li t1, KSEG1ADDR(MALTA_GT_BASE)
+
+ /* setup PCI0 io window to 0x18000000-0x181fffff */
+ li t0, CPU_TO_GT32(0xc0000000)
+ sw t0, GT_PCI0IOLD_OFS(t1)
+ li t0, CPU_TO_GT32(0x40000000)
+ sw t0, GT_PCI0IOHD_OFS(t1)
+
+ /* setup PCI0 mem windows */
+ li t0, CPU_TO_GT32(0x80000000)
+ sw t0, GT_PCI0M0LD_OFS(t1)
+ li t0, CPU_TO_GT32(0x3f000000)
+ sw t0, GT_PCI0M0HD_OFS(t1)
+
+ li t0, CPU_TO_GT32(0xc1000000)
+ sw t0, GT_PCI0M1LD_OFS(t1)
+ li t0, CPU_TO_GT32(0x5e000000)
+ sw t0, GT_PCI0M1HD_OFS(t1)
+
+ jr ra
+ nop
+
+ /*
+ *
+ */
+_msc01:
+ /* setup peripheral bus controller clock divide */
+ li t0, KSEG1ADDR(MALTA_MSC01_PBC_BASE)
+ li t1, 0x1 << MSC01_PBC_CLKCFG_SHF
+ sw t1, MSC01_PBC_CLKCFG_OFS(t0)
+
+ /* tweak peripheral bus controller timings */
+ li t1, (0x1 << MSC01_PBC_CS0TIM_CDT_SHF) | \
+ (0x1 << MSC01_PBC_CS0TIM_CAT_SHF)
+ sw t1, MSC01_PBC_CS0TIM_OFS(t0)
+ li t1, (0x0 << MSC01_PBC_CS0RW_RDT_SHF) | \
+ (0x2 << MSC01_PBC_CS0RW_RAT_SHF) | \
+ (0x0 << MSC01_PBC_CS0RW_WDT_SHF) | \
+ (0x2 << MSC01_PBC_CS0RW_WAT_SHF)
+ sw t1, MSC01_PBC_CS0RW_OFS(t0)
+ lw t1, MSC01_PBC_CS0CFG_OFS(t0)
+ li t2, MSC01_PBC_CS0CFG_DTYP_MSK
+ and t1, t2
+ ori t1, (0x0 << MSC01_PBC_CS0CFG_ADM_SHF) | \
+ (0x3 << MSC01_PBC_CS0CFG_WSIDLE_SHF) | \
+ (0x10 << MSC01_PBC_CS0CFG_WS_SHF)
+ sw t1, MSC01_PBC_CS0CFG_OFS(t0)
+
+ /* setup basic address decode */
+ li t0, KSEG1ADDR(MALTA_MSC01_BIU_BASE)
+ li t1, 0x0
+ li t2, -CONFIG_SYS_MEM_SIZE
+ sw t1, MSC01_BIU_MCBAS1L_OFS(t0)
+ sw t2, MSC01_BIU_MCMSK1L_OFS(t0)
+ sw t1, MSC01_BIU_MCBAS2L_OFS(t0)
+ sw t2, MSC01_BIU_MCMSK2L_OFS(t0)
+
+ /* initialise IP1 - unused */
+ li t1, MALTA_MSC01_IP1_BASE
+ li t2, -MALTA_MSC01_IP1_SIZE
+ sw t1, MSC01_BIU_IP1BAS1L_OFS(t0)
+ sw t2, MSC01_BIU_IP1MSK1L_OFS(t0)
+ sw t1, MSC01_BIU_IP1BAS2L_OFS(t0)
+ sw t2, MSC01_BIU_IP1MSK2L_OFS(t0)
+
+ /* initialise IP2 - PCI */
+ li t1, MALTA_MSC01_IP2_BASE1
+ li t2, -MALTA_MSC01_IP2_SIZE1
+ sw t1, MSC01_BIU_IP2BAS1L_OFS(t0)
+ sw t2, MSC01_BIU_IP2MSK1L_OFS(t0)
+ li t1, MALTA_MSC01_IP2_BASE2
+ li t2, -MALTA_MSC01_IP2_SIZE2
+ sw t1, MSC01_BIU_IP2BAS2L_OFS(t0)
+ sw t2, MSC01_BIU_IP2MSK2L_OFS(t0)
+
+ /* initialise IP3 - peripheral bus controller */
+ li t1, MALTA_MSC01_IP3_BASE
+ li t2, -MALTA_MSC01_IP3_SIZE
+ sw t1, MSC01_BIU_IP3BAS1L_OFS(t0)
+ sw t2, MSC01_BIU_IP3MSK1L_OFS(t0)
+ sw t1, MSC01_BIU_IP3BAS2L_OFS(t0)
+ sw t2, MSC01_BIU_IP3MSK2L_OFS(t0)
+
+ /* setup PCI memory */
+ li t0, KSEG1ADDR(MALTA_MSC01_PCI_BASE)
+ li t1, MALTA_MSC01_PCIMEM_BASE
+ li t2, (-MALTA_MSC01_PCIMEM_SIZE) & MSC01_PCI_SC2PMMSKL_MSK_MSK
+ li t3, MALTA_MSC01_PCIMEM_MAP
+ sw t1, MSC01_PCI_SC2PMBASL_OFS(t0)
+ sw t2, MSC01_PCI_SC2PMMSKL_OFS(t0)
+ sw t3, MSC01_PCI_SC2PMMAPL_OFS(t0)
+
+ /* setup PCI I/O */
+ li t1, MALTA_MSC01_PCIIO_BASE
+ li t2, (-MALTA_MSC01_PCIIO_SIZE) & MSC01_PCI_SC2PIOMSKL_MSK_MSK
+ li t3, MALTA_MSC01_PCIIO_MAP
+ sw t1, MSC01_PCI_SC2PIOBASL_OFS(t0)
+ sw t2, MSC01_PCI_SC2PIOMSKL_OFS(t0)
+ sw t3, MSC01_PCI_SC2PIOMAPL_OFS(t0)
+
+ /* setup PCI_BAR0 memory window */
+ li t1, -CONFIG_SYS_MEM_SIZE
+ sw t1, MSC01_PCI_BAR0_OFS(t0)
+
+ /* setup PCI to SysCon/CPU translation */
+ sw t1, MSC01_PCI_P2SCMSKL_OFS(t0)
+ sw zero, MSC01_PCI_P2SCMAPL_OFS(t0)
+
+ /* setup PCI vendor & device IDs */
+ li t1, (PCI_VENDOR_ID_MIPS << MSC01_PCI_HEAD0_VENDORID_SHF) | \
+ (PCI_DEVICE_ID_MIPS_MSC01 << MSC01_PCI_HEAD0_DEVICEID_SHF)
+ sw t1, MSC01_PCI_HEAD0_OFS(t0)
+
+ /* setup PCI subsystem vendor & device IDs */
+ sw t1, MSC01_PCI_HEAD11_OFS(t0)
+
+ /* setup PCI class, revision */
+ li t1, (PCI_CLASS_BRIDGE_HOST << MSC01_PCI_HEAD2_CLASS_SHF) | \
+ (0x1 << MSC01_PCI_HEAD2_REV_SHF)
+ sw t1, MSC01_PCI_HEAD2_OFS(t0)
+
+ /* ensure a sane setup */
+ sw zero, MSC01_PCI_HEAD3_OFS(t0)
+ sw zero, MSC01_PCI_HEAD4_OFS(t0)
+ sw zero, MSC01_PCI_HEAD5_OFS(t0)
+ sw zero, MSC01_PCI_HEAD6_OFS(t0)
+ sw zero, MSC01_PCI_HEAD7_OFS(t0)
+ sw zero, MSC01_PCI_HEAD8_OFS(t0)
+ sw zero, MSC01_PCI_HEAD9_OFS(t0)
+ sw zero, MSC01_PCI_HEAD10_OFS(t0)
+ sw zero, MSC01_PCI_HEAD12_OFS(t0)
+ sw zero, MSC01_PCI_HEAD13_OFS(t0)
+ sw zero, MSC01_PCI_HEAD14_OFS(t0)
+ sw zero, MSC01_PCI_HEAD15_OFS(t0)
+
+ /* setup PCI command register */
+ li t1, (PCI_COMMAND_FAST_BACK | \
+ PCI_COMMAND_SERR | \
+ PCI_COMMAND_PARITY | \
+ PCI_COMMAND_MASTER | \
+ PCI_COMMAND_MEMORY)
+ sw t1, MSC01_PCI_HEAD1_OFS(t0)
+
+ /* setup PCI byte swapping */
+#ifdef CONFIG_SYS_BIG_ENDIAN
+ li t1, (0x1 << MSC01_PCI_SWAP_BAR0_BSWAP_SHF) | \
+ (0x1 << MSC01_PCI_SWAP_IO_BSWAP_SHF)
+ sw t1, MSC01_PCI_SWAP_OFS(t0)
+#else
+ sw zero, MSC01_PCI_SWAP_OFS(t0)
+#endif
+
+ /* enable PCI host configuration cycles */
+ lw t1, MSC01_PCI_CFG_OFS(t0)
+ li t2, MSC01_PCI_CFG_RA_MSK | \
+ MSC01_PCI_CFG_G_MSK | \
+ MSC01_PCI_CFG_EN_MSK
+ or t1, t1, t2
+ sw t1, MSC01_PCI_CFG_OFS(t0)
+
+ jr ra
+ nop
diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c
new file mode 100644
index 0000000000..d363e49919
--- /dev/null
+++ b/board/imgtec/malta/malta.c
@@ -0,0 +1,220 @@
+/*
+ * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2013 Imagination Technologies
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <pci.h>
+#include <pci_gt64120.h>
+#include <pci_msc01.h>
+#include <rtc.h>
+#include <serial.h>
+
+#include <asm/addrspace.h>
+#include <asm/io.h>
+#include <asm/malta.h>
+
+#include "superio.h"
+
+enum core_card {
+ CORE_UNKNOWN,
+ CORE_LV,
+ CORE_FPGA6,
+};
+
+enum sys_con {
+ SYSCON_UNKNOWN,
+ SYSCON_GT64120,
+ SYSCON_MSC01,
+};
+
+static void malta_lcd_puts(const char *str)
+{
+ int i;
+ void *reg = (void *)CKSEG1ADDR(MALTA_ASCIIPOS0);
+
+ /* print up to 8 characters of the string */
+ for (i = 0; i < min(strlen(str), 8); i++) {
+ __raw_writel(str[i], reg);
+ reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
+ }
+
+ /* fill the rest of the display with spaces */
+ for (; i < 8; i++) {
+ __raw_writel(' ', reg);
+ reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
+ }
+}
+
+static enum core_card malta_core_card(void)
+{
+ u32 corid, rev;
+
+ rev = __raw_readl(CKSEG1ADDR(MALTA_REVISION));
+ corid = (rev & MALTA_REVISION_CORID_MSK) >> MALTA_REVISION_CORID_SHF;
+
+ switch (corid) {
+ case MALTA_REVISION_CORID_CORE_LV:
+ return CORE_LV;
+
+ case MALTA_REVISION_CORID_CORE_FPGA6:
+ return CORE_FPGA6;
+
+ default:
+ return CORE_UNKNOWN;
+ }
+}
+
+static enum sys_con malta_sys_con(void)
+{
+ switch (malta_core_card()) {
+ case CORE_LV:
+ return SYSCON_GT64120;
+
+ case CORE_FPGA6:
+ return SYSCON_MSC01;
+
+ default:
+ return SYSCON_UNKNOWN;
+ }
+}
+
+phys_size_t initdram(int board_type)
+{
+ return CONFIG_SYS_MEM_SIZE;
+}
+
+int checkboard(void)
+{
+ enum core_card core;
+
+ malta_lcd_puts("U-boot");
+ puts("Board: MIPS Malta");
+
+ core = malta_core_card();
+ switch (core) {
+ case CORE_LV:
+ puts(" CoreLV");
+ break;
+
+ case CORE_FPGA6:
+ puts(" CoreFPGA6");
+ break;
+
+ default:
+ puts(" CoreUnknown");
+ }
+
+ putc('\n');
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return pci_eth_init(bis);
+}
+
+void _machine_restart(void)
+{
+ void __iomem *reset_base;
+
+ reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE);
+ __raw_writel(GORESET, reset_base);
+}
+
+int board_early_init_f(void)
+{
+ void *io_base;
+
+ /* choose correct PCI I/O base */
+ switch (malta_sys_con()) {
+ case SYSCON_GT64120:
+ io_base = (void *)CKSEG1ADDR(MALTA_GT_PCIIO_BASE);
+ break;
+
+ case SYSCON_MSC01:
+ io_base = (void *)CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE);
+ break;
+
+ default:
+ return -1;
+ }
+
+ /* setup FDC37M817 super I/O controller */
+ malta_superio_init(io_base);
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ rtc_reset();
+
+ return 0;
+}
+
+struct serial_device *default_serial_console(void)
+{
+ switch (malta_sys_con()) {
+ case SYSCON_GT64120:
+ return &eserial1_device;
+
+ default:
+ case SYSCON_MSC01:
+ return &eserial2_device;
+ }
+}
+
+void pci_init_board(void)
+{
+ pci_dev_t bdf;
+ u32 val32;
+ u8 val8;
+
+ switch (malta_sys_con()) {
+ case SYSCON_GT64120:
+ set_io_port_base(CKSEG1ADDR(MALTA_GT_PCIIO_BASE));
+
+ gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE),
+ 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
+ 0x10000000, 0x10000000, 128 * 1024 * 1024,
+ 0x00000000, 0x00000000, 0x20000);
+ break;
+
+ default:
+ case SYSCON_MSC01:
+ set_io_port_base(CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE));
+
+ msc01_pci_init((void *)CKSEG1ADDR(MALTA_MSC01_PCI_BASE),
+ 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
+ MALTA_MSC01_PCIMEM_MAP,
+ CKSEG1ADDR(MALTA_MSC01_PCIMEM_BASE),
+ MALTA_MSC01_PCIMEM_SIZE, MALTA_MSC01_PCIIO_MAP,
+ 0x00000000, MALTA_MSC01_PCIIO_SIZE);
+ break;
+ }
+
+ bdf = pci_find_device(PCI_VENDOR_ID_INTEL,
+ PCI_DEVICE_ID_INTEL_82371AB_0, 0);
+ if (bdf == -1)
+ panic("Failed to find PIIX4 PCI bridge\n");
+
+ /* setup PCI interrupt routing */
+ pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCA, 10);
+ pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCB, 10);
+ pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCC, 11);
+ pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCD, 11);
+
+ /* mux SERIRQ onto SERIRQ pin */
+ pci_read_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, &val32);
+ val32 |= PCI_CFG_PIIX4_GENCFG_SERIRQ;
+ pci_write_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, val32);
+
+ /* enable SERIRQ - Linux currently depends upon this */
+ pci_read_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, &val8);
+ val8 |= PCI_CFG_PIIX4_SERIRQC_EN | PCI_CFG_PIIX4_SERIRQC_CONT;
+ pci_write_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, val8);
+}
diff --git a/board/imgtec/malta/superio.c b/board/imgtec/malta/superio.c
new file mode 100644
index 0000000000..eaa14df39e
--- /dev/null
+++ b/board/imgtec/malta/superio.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2013 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * Setup code for the FDC37M817 super I/O controller
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+#define SIO_CONF_PORT 0x3f0
+#define SIO_DATA_PORT 0x3f1
+
+enum sio_conf_key {
+ SIOCONF_DEVNUM = 0x07,
+ SIOCONF_ACTIVATE = 0x30,
+ SIOCONF_ENTER_SETUP = 0x55,
+ SIOCONF_BASE_HIGH = 0x60,
+ SIOCONF_BASE_LOW = 0x61,
+ SIOCONF_PRIMARY_INT = 0x70,
+ SIOCONF_EXIT_SETUP = 0xaa,
+ SIOCONF_MODE = 0xf0,
+};
+
+static struct {
+ u8 key;
+ u8 data;
+} sio_config[] = {
+ /* tty0 */
+ { SIOCONF_DEVNUM, 0x04 },
+ { SIOCONF_BASE_HIGH, 0x03 },
+ { SIOCONF_BASE_LOW, 0xf8 },
+ { SIOCONF_MODE, 0x02 },
+ { SIOCONF_PRIMARY_INT, 0x04 },
+ { SIOCONF_ACTIVATE, 0x01 },
+
+ /* tty1 */
+ { SIOCONF_DEVNUM, 0x05 },
+ { SIOCONF_BASE_HIGH, 0x02 },
+ { SIOCONF_BASE_LOW, 0xf8 },
+ { SIOCONF_MODE, 0x02 },
+ { SIOCONF_PRIMARY_INT, 0x03 },
+ { SIOCONF_ACTIVATE, 0x01 },
+};
+
+void malta_superio_init(void *io_base)
+{
+ unsigned i;
+
+ /* enter config state */
+ writeb(SIOCONF_ENTER_SETUP, io_base + SIO_CONF_PORT);
+
+ /* configure peripherals */
+ for (i = 0; i < ARRAY_SIZE(sio_config); i++) {
+ writeb(sio_config[i].key, io_base + SIO_CONF_PORT);
+ writeb(sio_config[i].data, io_base + SIO_DATA_PORT);
+ }
+
+ /* exit config state */
+ writeb(SIOCONF_EXIT_SETUP, io_base + SIO_CONF_PORT);
+}
diff --git a/board/imgtec/malta/superio.h b/board/imgtec/malta/superio.h
new file mode 100644
index 0000000000..1450da56dd
--- /dev/null
+++ b/board/imgtec/malta/superio.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2013 Imagination Technologies
+ * Author: Paul Burton <paul.burton@imgtec.com>
+ *
+ * Setup code for the FDC37M817 super I/O controller
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __BOARD_MALTA_SUPERIO_H__
+#define __BOARD_MALTA_SUPERIO_H__
+
+extern void malta_superio_init(void *io_base);
+
+#endif /* __BOARD_MALTA_SUPERIO_H__ */
diff --git a/board/keymile/km82xx/Makefile b/board/keymile/km82xx/Makefile
index b44582fbea..20f193ab1d 100644
--- a/board/keymile/km82xx/Makefile
+++ b/board/keymile/km82xx/Makefile
@@ -5,7 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
obj-y := km82xx.o ../common/common.o ../common/ivm.o
diff --git a/board/keymile/km83xx/Makefile b/board/keymile/km83xx/Makefile
index 7bdddf3bc3..6c3268853e 100644
--- a/board/keymile/km83xx/Makefile
+++ b/board/keymile/km83xx/Makefile
@@ -5,8 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y += km83xx.o ../common/common.o ../common/ivm.o km83xx_i2c.o
diff --git a/board/keymile/km_arm/Makefile b/board/keymile/km_arm/Makefile
index 32eaa9357f..a17d8d963a 100644
--- a/board/keymile/km_arm/Makefile
+++ b/board/keymile/km_arm/Makefile
@@ -6,10 +6,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y := km_arm.o ../common/common.o ../common/ivm.o
ifdef CONFIG_KM_FPGA_CONFIG
diff --git a/board/keymile/kmp204x/Makefile b/board/keymile/kmp204x/Makefile
index 64eb37c9d7..3e69ee2f15 100644
--- a/board/keymile/kmp204x/Makefile
+++ b/board/keymile/kmp204x/Makefile
@@ -8,9 +8,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-obj-y := $(BOARD).o ddr.o eth.o tlb.o pci.o law.o \
+obj-y := kmp204x.o ddr.o eth.o tlb.o pci.o law.o \
../common/common.o ../common/ivm.o
diff --git a/board/keymile/kmp204x/ddr.c b/board/keymile/kmp204x/ddr.c
index bd425aab1a..34ac6979bd 100644
--- a/board/keymile/kmp204x/ddr.c
+++ b/board/keymile/kmp204x/ddr.c
@@ -11,8 +11,8 @@
#include <i2c.h>
#include <hwconfig.h>
#include <asm/mmu.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/kmc/kzm9g/kzm9g.c b/board/kmc/kzm9g/kzm9g.c
index b669ffefec..ea36fa4e19 100644
--- a/board/kmc/kzm9g/kzm9g.c
+++ b/board/kmc/kzm9g/kzm9g.c
@@ -289,7 +289,6 @@ void adjust_core_voltage(void)
{
u8 data;
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
data = 0x35;
i2c_set_bus_num(0);
i2c_write(0x40, 3, 1, &data, 1);
diff --git a/board/kup/kup4k/Makefile b/board/kup/kup4k/Makefile
index b3ad86ce18..c896fcd64d 100644
--- a/board/kup/kup4k/Makefile
+++ b/board/kup/kup4k/Makefile
@@ -5,8 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y = kup4k.o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o ../common/pcmcia.o
diff --git a/board/kup/kup4x/Makefile b/board/kup/kup4x/Makefile
index 05a1afc3a9..6945943d09 100644
--- a/board/kup/kup4x/Makefile
+++ b/board/kup/kup4x/Makefile
@@ -5,8 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y = kup4x.o ../common/flash.o ../common/kup.o ../common/load_sernum_ethaddr.o ../common/pcmcia.o
diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c
index b6c68da7a8..1569905460 100644
--- a/board/logicpd/am3517evm/am3517evm.c
+++ b/board/logicpd/am3517evm/am3517evm.c
@@ -98,8 +98,8 @@ static void am3517_evm_musb_init(void)
*/
int misc_init_r(void)
{
-#ifdef CONFIG_DRIVER_OMAP34XX_I2C
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#ifdef CONFIG_SYS_I2C_OMAP34XX
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
#endif
dieid_num_r();
diff --git a/board/matrix_vision/mvsmr/u-boot.lds b/board/matrix_vision/mvsmr/u-boot.lds
index 08ce014aac..e885b7c160 100644
--- a/board/matrix_vision/mvsmr/u-boot.lds
+++ b/board/matrix_vision/mvsmr/u-boot.lds
@@ -18,7 +18,7 @@ SECTIONS
/* the first two sectors (=8KB) of our S29GL flash chip */
arch/powerpc/cpu/mpc5xxx/start.o (.text*)
arch/powerpc/cpu/mpc5xxx/traps.o (.text*)
- board/matrix_vision/common/libmatrix_vision.o (.text*)
+ board/matrix_vision/common/built-in.o (.text*)
/* This is only needed to force failure if size of above code will ever */
/* increase and grow into reserved space. */
diff --git a/board/mpl/mip405/Makefile b/board/mpl/mip405/Makefile
index 509eb591b3..5bcf130501 100644
--- a/board/mpl/mip405/Makefile
+++ b/board/mpl/mip405/Makefile
@@ -5,10 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y = mip405.o cmd_mip405.o \
../common/pci.o \
../common/usb_uhci.o \
diff --git a/board/mpl/pati/Makefile b/board/mpl/pati/Makefile
index 67381c108a..9822082612 100644
--- a/board/mpl/pati/Makefile
+++ b/board/mpl/pati/Makefile
@@ -5,9 +5,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y := pati.o cmd_pati.o \
../common/common_util.o
diff --git a/board/mpl/pip405/Makefile b/board/mpl/pip405/Makefile
index 3d73cc3f8d..0a3d059e9c 100644
--- a/board/mpl/pip405/Makefile
+++ b/board/mpl/pip405/Makefile
@@ -5,10 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y = pip405.o cmd_pip405.o \
../common/pci.o \
../common/isa.o \
diff --git a/board/mpl/vcma9/Makefile b/board/mpl/vcma9/Makefile
index e0e96691c5..175a19fa36 100644
--- a/board/mpl/vcma9/Makefile
+++ b/board/mpl/vcma9/Makefile
@@ -5,10 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y := ../common/common_util.o
obj-y += vcma9.o cmd_vcma9.o
diff --git a/board/mvblue/u-boot.lds b/board/mvblue/u-boot.lds
index 121354bfeb..5034a9675a 100644
--- a/board/mvblue/u-boot.lds
+++ b/board/mvblue/u-boot.lds
@@ -14,12 +14,12 @@ SECTIONS
.text :
{
arch/powerpc/cpu/mpc824x/start.o (.text*)
- lib/libgeneric.o (.text*)
- net/libnet.o (.text*)
- drivers/pci/libpci.o (.text*)
- arch/powerpc/cpu/mpc824x/libmpc824x.o (.text*)
- board/mvblue/libmvblue.o (.text*)
- arch/powerpc/lib/libpowerpc.o (.text*)
+ lib/built-in.o (.text*)
+ net/built-in.o (.text*)
+ drivers/pci/built-in.o (.text*)
+ arch/powerpc/cpu/mpc824x/built-in.o (.text*)
+ board/mvblue/built-in.o (.text*)
+ arch/powerpc/lib/built-in.o (.text*)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.ppcenv*)
diff --git a/board/nvidia/beaver/Makefile b/board/nvidia/beaver/Makefile
index f828f52c25..1f7c31d64b 100644
--- a/board/nvidia/beaver/Makefile
+++ b/board/nvidia/beaver/Makefile
@@ -14,6 +14,4 @@
# along with this program. If not, see <http://www.gnu.org/licenses/>.
#
-$(shell mkdir -p $(obj)../cardhu)
-
obj-y = ../cardhu/cardhu.o
diff --git a/board/nvidia/ventana/Makefile b/board/nvidia/ventana/Makefile
index 7265cfcccc..f67044f2cf 100644
--- a/board/nvidia/ventana/Makefile
+++ b/board/nvidia/ventana/Makefile
@@ -5,6 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-$(shell mkdir -p $(obj)../seaboard)
-
obj-y = ../seaboard/seaboard.o
diff --git a/board/overo/overo.c b/board/overo/overo.c
index aace42a8be..9ac35d2f4e 100644
--- a/board/overo/overo.c
+++ b/board/overo/overo.c
@@ -92,7 +92,7 @@ int get_board_revision(void)
{
int revision;
-#ifdef CONFIG_DRIVER_OMAP34XX_I2C
+#ifdef CONFIG_SYS_I2C_OMAP34XX
unsigned char data;
/* board revisions <= R2410 connect 4030 irq_1 to gpio112 */
diff --git a/board/phytec/pcm051/board.c b/board/phytec/pcm051/board.c
index 6a27e56d11..68463e78db 100644
--- a/board/phytec/pcm051/board.c
+++ b/board/phytec/pcm051/board.c
@@ -130,7 +130,7 @@ void set_mux_conf_regs(void)
{
/* Initalize the board header */
enable_i2c0_pin_mux();
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
enable_board_pin_mux();
}
@@ -141,7 +141,7 @@ void set_mux_conf_regs(void)
*/
int board_init(void)
{
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
diff --git a/board/pn62/Makefile b/board/pn62/Makefile
deleted file mode 100644
index 7572ed8610..0000000000
--- a/board/pn62/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = pn62.o cmd_pn62.o misc.o
diff --git a/board/pn62/cmd_pn62.c b/board/pn62/cmd_pn62.c
deleted file mode 100644
index a0326b40d6..0000000000
--- a/board/pn62/cmd_pn62.c
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * (C) Copyright 2002
- * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <net.h>
-#include <asm/io.h>
-#include <pci.h>
-#include <command.h>
-#include "pn62.h"
-
-#if defined(CONFIG_CMD_BSP)
-
-/*
- * Command led: controls the various LEDs 0..11 on the PN62 card.
- */
-int do_led(cmd_tbl_t * cmdtp, int flag, int argc, char *const argv[])
-{
- unsigned int number, function;
-
- if (argc != 3)
- return cmd_usage(cmdtp);
-
- number = simple_strtoul(argv[1], NULL, 10);
- if (number > PN62_LED_MAX)
- return 1;
-
- function = simple_strtoul(argv[2], NULL, 16);
- set_led(number, function);
- return 0;
-}
-U_BOOT_CMD(
- led , 3, 1, do_led,
- "set LED 0..11 on the PN62 board",
- "i fun"
- " - set 'i'th LED to function 'fun'"
-);
-
-/*
- * Command loadpci: loads a image over PCI.
- */
-#define CMD_MOVE_WINDOW 0x1
-#define CMD_BOOT_IMAGE 0x2
-
-int do_loadpci (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- char *s;
- ulong addr = 0, count = 0;
- u32 off;
- int cmd, rcode = 0;
-
- /* pre-set load_addr */
- if ((s = getenv("loadaddr")) != NULL) {
- addr = simple_strtoul(s, NULL, 16);
- }
-
- switch (argc) {
- case 1:
- break;
- case 2:
- addr = simple_strtoul(argv[1], NULL, 16);
- break;
- default:
- return cmd_usage(cmdtp);
- }
-
- printf ("## Ready for image download ...\n");
-
- show_startup_phase(12);
-
- while (1) {
- /* Alive indicator */
- i2155x_write_scrapad(BOOT_PROTO, BOOT_PROTO_READY);
-
- /* Toggle status LEDs */
- cmd = (count / 200) % 4; /* downscale */
- set_led(4, cmd == 0 ? LED_1 : LED_0);
- set_led(5, cmd == 1 ? LED_1 : LED_0);
- set_led(6, cmd == 2 ? LED_1 : LED_0);
- set_led(7, cmd == 3 ? LED_1 : LED_0);
- udelay(1000);
- count++;
-
- cmd = i2155x_read_scrapad(BOOT_CMD);
-
- if (cmd == BOOT_CMD_MOVE) {
- off = i2155x_read_scrapad(BOOT_DATA);
- off += addr;
- i2155x_set_bar_base(3, off);
- printf ("## BAR3 Addr moved = 0x%08x\n", off);
- i2155x_write_scrapad(BOOT_CMD, ~cmd);
- show_startup_phase(13);
- }
- else if (cmd == BOOT_CMD_BOOT) {
- set_led(4, LED_1);
- set_led(5, LED_1);
- set_led(6, LED_1);
- set_led(7, LED_1);
-
- i2155x_write_scrapad(BOOT_CMD, ~cmd);
- show_startup_phase(14);
- break;
- }
-
- /* Abort if ctrl-c was pressed */
- if (ctrlc()) {
- printf("\nAbort\n");
- return 0;
- }
-
- }
-
- /* Repoint to the default shared memory */
- i2155x_set_bar_base(3, PN62_SMEM_DEFAULT);
-
- load_addr = addr;
- printf ("## Start Addr = 0x%08lx\n", addr);
-
- show_startup_phase(15);
-
- /* Loading ok, check if we should attempt an auto-start */
- if (((s = getenv("autostart")) != NULL) && (strcmp(s,"yes") == 0)) {
- char *local_args[2];
- local_args[0] = argv[0];
- local_args[1] = NULL;
-
- printf ("Automatic boot of image at addr 0x%08lX ...\n",
- load_addr);
- rcode = do_bootm (cmdtp, 0, 1, local_args);
- }
-
- return rcode;
-}
-
-U_BOOT_CMD(
- loadpci, 2, 1, do_loadpci,
- "load binary file over PCI",
- "[addr]\n"
- " - load binary file over PCI to address 'addr'"
-);
-
-#endif
diff --git a/board/pn62/misc.c b/board/pn62/misc.c
deleted file mode 100644
index 98e0dfa518..0000000000
--- a/board/pn62/misc.c
+++ /dev/null
@@ -1,219 +0,0 @@
-/*
- * (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc824x.h>
-#include <asm/io.h>
-#include <pci.h>
-
-#include "pn62.h"
-
-typedef struct {
- pci_dev_t devno;
- volatile u32 *csr;
-
-} i2155x_t;
-
-static i2155x_t i2155x = { 0, NULL };
-
-static struct pci_device_id i2155x_ids[] = {
- { 0x1011, 0x0046 }, /* i21554 */
- { 0x8086, 0xb555 } /* i21555 */
-};
-
-int i2155x_init(void)
-{
- pci_dev_t devno;
- u32 val;
- int i;
-
- /*
- * Find the Intel bridge.
- */
- if ((devno = pci_find_devices(i2155x_ids, 0)) < 0) {
- printf("Error: Intel bridge 2155x not found!\n");
- return -1;
- }
- i2155x.devno = devno;
-
- /*
- * Get auto-configured base address for CSR access.
- */
- pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &val);
- if (val & PCI_BASE_ADDRESS_SPACE_IO) {
- val &= PCI_BASE_ADDRESS_IO_MASK;
- i2155x.csr = (volatile u32 *)(_IO_BASE + val);
- } else {
- val &= PCI_BASE_ADDRESS_MEM_MASK;
- i2155x.csr = (volatile u32 *)val;
- }
-
- /*
- * Translate downstream memory 2 (bar3) to base of shared memory.
- */
- i2155x_set_bar_base(3, PN62_SMEM_DEFAULT);
-
- /*
- * Enable memory space, I/O space and bus master bits
- * in both Primary and Secondary command registers.
- */
- val = PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER|PCI_COMMAND_IO;
- pci_write_config_word(devno, 0x44, val);
- pci_write_config_word(devno, 0x04, val);
-
- /*
- * Clear scratchpad registers.
- */
- for (i = 0; i < (I2155X_SCRAPAD_MAX - 1); i++) {
- i2155x_write_scrapad(i, 0x0);
- }
-
- /*
- * Set interrupt line for Linux.
- */
- pci_write_config_byte(devno, PCI_INTERRUPT_LINE, 3);
-
- return 0;
-}
-
-/*
- * Access the Scratchpad registers 0..7 of the Intel bridge.
- */
-void i2155x_write_scrapad(int idx, u32 val)
-{
- if (idx >= 0 && idx < I2155X_SCRAPAD_MAX)
- out_le32(i2155x.csr + (I2155X_SCRAPAD_ADDR/4) + idx, val);
- else
- printf("i2155x_write_scrapad: invalid index\n");
-}
-
-u32 i2155x_read_scrapad(int idx)
-{
- if (idx >= 0 && idx < I2155X_SCRAPAD_MAX)
- return in_le32(i2155x.csr + (I2155X_SCRAPAD_ADDR/4) + idx);
- else
- printf("i2155x_read_scrapad: invalid index\n");
- return -1;
-}
-
-void i2155x_set_bar_base(int bar, u32 base)
-{
- if (bar >= 2 && bar <= 4) {
- pci_write_config_dword(i2155x.devno,
- I2155X_BAR2_BASE + (bar - 2) * 4,
- base);
- }
-}
-
-/*
- * Read Vital Product Data (VPD) from the Serial EPROM attached
- * to the Intel bridge.
- */
-int i2155x_read_vpd(int offset, int size, unsigned char *data)
-{
- int i, n;
- u16 val16;
-
- for (i = 0; i < size; i++) {
- pci_write_config_word(i2155x.devno, I2155X_VPD_ADDR,
- offset + i - I2155X_VPD_START);
- for (n = 10000; n > 0; n--) {
- pci_read_config_word(i2155x.devno, I2155X_VPD_ADDR, &val16);
- if ((val16 & 0x8000) != 0) /* wait for completion */
- break;
- udelay(100);
- }
- if (n == 0) {
- printf("i2155x_read_vpd: TIMEOUT\n");
- return -1;
- }
-
- pci_read_config_byte(i2155x.devno, I2155X_VPD_DATA, &data[i]);
- }
-
- return i;
-}
-
-static struct pci_device_id am79c95x_ids [] = {
- { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE },
- { }
-};
-
-
-/*
- * Initialize the AMD ethernet controllers.
- */
-int am79c95x_init(void)
-{
- pci_dev_t devno;
- int i;
-
- /*
- * Set interrupt line for Linux.
- */
- for (i = 0; i < 2; i++) {
- if ((devno = pci_find_devices(am79c95x_ids, i)) < 0)
- break;
- pci_write_config_byte(devno, PCI_INTERRUPT_LINE, 2+i);
- }
- if (i < 2)
- printf("Error: Only %d AMD Ethernet Controller found!\n", i);
-
- return 0;
-}
-
-
-void set_led(unsigned int number, unsigned int function)
-{
- volatile u8 *addr;
-
- if ((number >= 0) && (number < PN62_LED_MAX) &&
- (function >= 0) && (function <= LED_LAST_FUNCTION)) {
- addr = (volatile u8 *)(PN62_LED_BASE + number * 8);
- out_8(addr, function&0xff);
- }
-}
-
-/*
- * Show fatal error indicated by Kinght Rider(tm) effect
- * in LEDS 0-7. LEDS 8-11 contain 4 bit error code.
- * Note: this function will not terminate.
- */
-void fatal_error(unsigned int error_code)
-{
- int i, d;
-
- for (i = 0; i < 12; i++) {
- set_led(i, LED_0);
- }
-
- /*
- * Write error code.
- */
- set_led(8, (error_code & 0x01) ? LED_1 : LED_0);
- set_led(9, (error_code & 0x02) ? LED_1 : LED_0);
- set_led(10, (error_code & 0x04) ? LED_1 : LED_0);
- set_led(11, (error_code & 0x08) ? LED_1 : LED_0);
-
- /*
- * Yay - Knight Rider effect!
- */
- while(1) {
- unsigned int delay = 2000;
-
- for (i = 0; i < 8; i++) {
- set_led(i, LED_1);
- for (d = 0; d < delay; d++);
- set_led(i, LED_0);
- }
-
- for (i = 7; i > 0; i--) {
- set_led(i, LED_1);
- for (d = 0; d < delay; d++);
- set_led(i, LED_0);
- }
- }
-}
diff --git a/board/pn62/pn62.c b/board/pn62/pn62.c
deleted file mode 100644
index 81829dd75f..0000000000
--- a/board/pn62/pn62.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc824x.h>
-#include <net.h>
-#include <pci.h>
-#include <netdev.h>
-
-#include "pn62.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static int get_serial_number (char *string, int size);
-static void get_mac_address(int id, u8 *mac);
-
-#ifdef CONFIG_SHOW_BOOT_PROGRESS
-void show_boot_progress (int phase)
-{
- /*
- * Show phases of the bootm command on the front panel
- * LEDs and the scratchpad register #3 as well. We use
- * blinking LEDs for logical "1".
- */
- if (phase > 0) {
- set_led (8, (phase & 0x1) ? LED_SLOW_CLOCK : LED_0);
- set_led (9, (phase & 0x2) ? LED_SLOW_CLOCK : LED_0);
- set_led (10, (phase & 0x4) ? LED_SLOW_CLOCK : LED_0);
- set_led (11, (phase & 0x8) ? LED_SLOW_CLOCK : LED_0);
- }
- i2155x_write_scrapad (BOOT_STATUS, phase);
- if (phase < 0)
- i2155x_write_scrapad (BOOT_DONE, BOOT_DONE_ERROR);
-}
-#endif
-
-void show_startup_phase (int phase)
-{
- /*
- * Show the phase of U-Boot startup on the front panel
- * LEDs and the scratchpad register #3 as well.
- */
- if (phase > 0) {
- set_led (8, (phase & 0x1) ? LED_1 : LED_0);
- set_led (9, (phase & 0x2) ? LED_1 : LED_0);
- set_led (10, (phase & 0x4) ? LED_1 : LED_0);
- set_led (11, (phase & 0x8) ? LED_1 : LED_0);
- }
- i2155x_write_scrapad (BOOT_STATUS, phase);
- if (phase < 0)
- i2155x_write_scrapad (BOOT_DONE, BOOT_DONE_ERROR);
-}
-
-int checkboard (void)
-{
- show_startup_phase (1);
- puts ("Board: PN62\n");
- return 0;
-}
-
-phys_size_t initdram (int board_type)
-{
- long size;
- long new_bank0_end;
- long mear1;
- long emear1;
-
- show_startup_phase (2);
-
- size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
-
- new_bank0_end = size - 1;
- mear1 = mpc824x_mpc107_getreg (MEAR1);
- emear1 = mpc824x_mpc107_getreg (EMEAR1);
- mear1 = (mear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
- emear1 = (emear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
- mpc824x_mpc107_setreg (MEAR1, mear1);
- mpc824x_mpc107_setreg (EMEAR1, emear1);
-
- return (size);
-}
-
-/*
- * Initialize PCI Devices. We rely on auto-configuration.
- */
-#ifndef CONFIG_PCI_PNP
-#error "CONFIG_PCI_PNP is not defined, please correct!"
-#endif
-
-struct pci_controller hose = {
-};
-
-void pci_init_board (void)
-{
- show_startup_phase (4);
- pci_mpc824x_init (&hose);
-
- show_startup_phase (5);
- i2155x_init ();
- show_startup_phase (6);
- am79c95x_init ();
- show_startup_phase (7);
-}
-
-int misc_init_r (void)
-{
- char str[20];
- u8 mac[6];
-
- show_startup_phase (8);
- /*
- * Get serial number and ethernet addresses if not already defined
- * and update the board info structure and the environment.
- */
- if (getenv ("serial#") == NULL &&
- get_serial_number (str, strlen (str)) > 0) {
- setenv ("serial#", str);
- }
- show_startup_phase (9);
-
- if (!eth_getenv_enetaddr("ethaddr", mac)) {
- get_mac_address(0, mac);
- eth_setenv_enetaddr("ethaddr", mac);
- }
- show_startup_phase (10);
-
-#ifdef CONFIG_HAS_ETH1
- if (!eth_getenv_enetaddr("eth1addr", mac)) {
- get_mac_address(1, mac);
- eth_setenv_enetaddr("eth1addr", mac);
- }
-#endif /* CONFIG_HAS_ETH1 */
- show_startup_phase (11);
-
- /* Tell everybody that U-Boot is up and runnig */
- i2155x_write_scrapad (0, 0x12345678);
- return (0);
-}
-
-static int get_serial_number (char *string, int size)
-{
- int i;
- char c;
-
- if (size < I2155X_VPD_SN_SIZE)
- size = I2155X_VPD_SN_SIZE;
- for (i = 0; i < (size - 1); i++) {
- i2155x_read_vpd (I2155X_VPD_SN_START + i, 1, (uchar *)&c);
- if (c == '\0')
- break;
- string[i] = c;
- }
- string[i] = '\0'; /* make sure it's terminated */
-
- return i;
-}
-
-static void get_mac_address(int id, u8 *mac)
-{
- i2155x_read_vpd (I2155X_VPD_MAC0_START + 6 * id, 6, mac);
-}
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
diff --git a/board/pn62/pn62.h b/board/pn62/pn62.h
deleted file mode 100644
index 10290c3142..0000000000
--- a/board/pn62/pn62.h
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _PN62_H_
-#define _PN62_H_
-
-/*
- * Definitions for the Intel Bridge 21554 or 21555.
- */
-#define I2155X_VPD_ADDR 0xe6
-#define I2155X_VPD_DATA 0xe8
-
-#define I2155X_VPD_START 0x80
-#define I2155X_VPD_SN_START 0x80
-#define I2155X_VPD_SN_SIZE 0x10
-#define I2155X_VPD_MAC0_START 0x90
-#define I2155X_VPD_MAC1_START 0x96
-
-#define I2155X_SCRAPAD_ADDR 0xa8
-#define I2155X_SCRAPAD_MAX 8
-
-#define I2155X_BAR2_BASE 0x98
-#define I2155X_BAR3_BASE 0x9c
-#define I2155X_BAR4_BASE 0xa0
-
-#define I2155X_BAR2_SETUP 0xb0
-#define I2155X_BAR3_SETUP 0xb4
-#define I2155X_BAR4_SETUP 0xb8
-
-/*
- * Interrupt request numbers
- */
-#define PN62_IRQ_HOST 0x0
-#define PN62_IRQ_PLX9054 0x1
-#define PN62_IRQ_ETH0 0x2
-#define PN62_IRQ_ETH1 0x3
-#define PN62_IRQ_COM1 0x4
-#define PN62_IRQ_COM2 0x4
-
-/*
- * Miscellaneous definitons.
- */
-#define PN62_SMEM_DEFAULT 0x1f00000
-
-/*
- * Definitions for boot protocol using Scratchpad registers.
- */
-#define BOOT_DONE 0
-#define BOOT_DONE_CLEAR 0x00dead00
-#define BOOT_DONE_ERROR 0xbad0dead
-#define BOOT_DONE_U_BOOT 0x12345678
-#define BOOT_DONE_LINUX 0x87654321
-#define BOOT_CMD 1
-#define BOOT_CMD_MOVE 0x1
-#define BOOT_CMD_BOOT 0x2
-#define BOOT_DATA 2
-#define BOOT_PROTO 3
-#define BOOT_PROTO_READY 0x23456789
-#define BOOT_PROTO_CLEAR 0x00000000
-#define BOOT_STATUS 4
-
-/*
- * LED Definitions:
- */
-#define PN62_LED_BASE 0xff800300
-#define PN62_LED_MAX 12
-
-/*
- * LED0 - 7 mounted on top of board, D1 - D8
- * LED8 - 11 upper four LEDs on the front panel of the board.
- */
-#define LED_0 0x00 /* OFF */
-#define LED_1 0x01 /* ON */
-#define LED_SLOW_CLOCK 0x02 /* SLOW 1Hz ish */
-#define LED_nSLOW_CLOCK 0x03 /* inverse of above */
-#define LED_WATCHDOG_OUT 0x06 /* Reset Watchdog level */
-#define LED_WATCHDOG_CLOCK 0x07 /* clock to watchdog */
-
-/*
- * LED's currently setup in AMD79C973 device as the following:
- * LED0 100Mbit
- * LED1 LNKSE
- * LED2 TX Activity
- * LED3 RX Activity
- */
-#define LED_E0_LED0 0x08 /* Ethernet Port 0 LED 0 */
-#define LED_E0_LED1 0x09 /* Ethernet Port 0 LED 1 */
-#define LED_E0_LED2 0x0A /* Ethernet Port 0 LED 2 */
-#define LED_E0_LED3 0x0B /* Ethernet Port 0 LED 3 */
-#define LED_E1_LED0 0x0C /* Ethernet Port 1 LED 0 */
-#define LED_E1_LED1 0x0D /* Ethernet Port 1 LED 1 */
-#define LED_E1_LED2 0x0E /* Ethernet Port 1 LED 2 */
-#define LED_E1_LED3 0x0F /* Ethernet Port 1 LED 3 */
-#define LED_STROBE0 0x10 /* Processor Strobe 0 */
-#define LED_STROBE1 0x11 /* Processor Strobe 1 */
-#define LED_STROBE2 0x12 /* Processor Strobe 2 */
-#define LED_STROBE3 0x13 /* Processor Strobe 3 */
-#define LED_STROBE4 0x14 /* Processor Strobe 4 */
-#define LED_STROBE5 0x15 /* Processor Strobe 5 */
-#define LED_STROBE6 0x16 /* Processor Strobe 6 */
-#define LED_STROBE7 0x17 /* Processor Strobe 7 */
-#define LED_HOST_STROBE0 0x18 /* Host strobe 0 */
-#define LED_HOST_STROBE1 0x19 /* Host strobe 1 */
-#define LED_HOST_STROBE2 0x1A /* Host strobe 2 */
-#define LED_HOST_STROBE3 0x1B /* Host strobe 3 */
-#define LED_HOST_STROBE4 0x1C /* Host strobe 4 */
-#define LED_HOST_STROBE5 0x1D /* Host strobe 5 */
-#define LED_HOST_STROBE6 0x1E /* Host strobe 6 */
-#define LED_HOST_STROBE7 0x1F /* Host strobe 7 */
-#define LED_MPC_INT0 0x20 /* MPC8240 INT 0 */
-#define LED_MPC_INT1 0x21 /* MPC8240 INT 1 */
-#define LED_MPC_INT2 0x22 /* MPC8240 INT 2 */
-#define LED_MPC_INT3 0x23 /* MPC8240 INT 3 */
-#define LED_MPC_INT4 0x24 /* MPC8240 INT 4 */
-#define LED_UART0_CS 0x25 /* UART 0 Chip Select */
-#define LED_UART1_CS 0x26 /* UART 1 Chip Select */
-#define LED_SRAM_CS 0x27 /* SRAM Chip Select */
-#define LED_SRAM_WR 0x28 /* SRAM WR Signal */
-#define LED_SRAM_RD 0x29 /* SRAM RD Signal */
-#define LED_MPC_RCS0 0x2A /* MPC8240 RCS0 Signal */
-#define LED_S_PCI_FRAME 0x2B /* Secondary PCI Frame Signal */
-#define LED_MPC_CS0 0x2C /* MPC8240 CS0 Signal */
-#define LED_HOST_INT 0x2D /* MPC8240 to Host Interrupt signal */
-#define LED_LAST_FUNCTION LED_HOST_INT /* last function */
-
-/*
- * Forward declarations
- */
-int i2155x_init (void);
-void i2155x_write_scrapad(int idx, u32 val);
-u32 i2155x_read_scrapad (int idx);
-void i2155x_set_bar_base (int bar, u32 addr);
-int i2155x_read_vpd (int offset, int size, unsigned char *data);
-
-int am79c95x_init (void);
-
-void set_led (unsigned int number, unsigned int function);
-void fatal_error (unsigned int error_code);
-void show_startup_phase (int phase);
-
-
-#endif /* _PN62_H_ */
diff --git a/board/prodrive/p3mx/Makefile b/board/prodrive/p3mx/Makefile
index 43caffbc22..6ddda2296d 100644
--- a/board/prodrive/p3mx/Makefile
+++ b/board/prodrive/p3mx/Makefile
@@ -5,10 +5,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../../Marvell/common)
-endif
-
obj-y = misc.o
obj-y += p3mx.o mpsc.o mv_eth.o pci.o sdram_init.o serial.o \
../../Marvell/common/i2c.o ../../Marvell/common/memory.o
diff --git a/board/psyent/pci5441/Makefile b/board/psyent/pci5441/Makefile
index 9a66cfdfe8..364f163e4f 100644
--- a/board/psyent/pci5441/Makefile
+++ b/board/psyent/pci5441/Makefile
@@ -5,8 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y := pci5441.o ../common/AMDLV065D.o
diff --git a/board/psyent/pci5441/config.mk b/board/psyent/pci5441/config.mk
index 00ff743c96..776fa8ab40 100644
--- a/board/psyent/pci5441/config.mk
+++ b/board/psyent/pci5441/config.mk
@@ -8,7 +8,6 @@
CONFIG_SYS_TEXT_BASE = 0x018e0000
PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
-PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
diff --git a/board/psyent/pk1c20/Makefile b/board/psyent/pk1c20/Makefile
index 286db94aef..5450f93ac3 100644
--- a/board/psyent/pk1c20/Makefile
+++ b/board/psyent/pk1c20/Makefile
@@ -5,8 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
obj-y := pk1c20.o led.o ../common/AMDLV065D.o
diff --git a/board/psyent/pk1c20/config.mk b/board/psyent/pk1c20/config.mk
index 7b0810a302..83cfadc113 100644
--- a/board/psyent/pk1c20/config.mk
+++ b/board/psyent/pk1c20/config.mk
@@ -8,7 +8,6 @@
CONFIG_SYS_TEXT_BASE = 0x01fc0000
PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
-PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
diff --git a/board/qemu-malta/lowlevel_init.S b/board/qemu-malta/lowlevel_init.S
deleted file mode 100644
index fa0b6a7d13..0000000000
--- a/board/qemu-malta/lowlevel_init.S
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#include <config.h>
-#include <gt64120.h>
-
-#include <asm/addrspace.h>
-#include <asm/regdef.h>
-#include <asm/malta.h>
-
-#ifdef CONFIG_SYS_BIG_ENDIAN
-#define CPU_TO_GT32(_x) ((_x))
-#else
-#define CPU_TO_GT32(_x) ( \
- (((_x) & 0xff) << 24) | (((_x) & 0xff00) << 8) | \
- (((_x) & 0xff0000) >> 8) | (((_x) & 0xff000000) >> 24))
-#endif
-
- .text
- .set noreorder
- .set mips32
-
- .globl lowlevel_init
-lowlevel_init:
-
- /*
- * Load BAR registers of GT64120 as done by YAMON
- *
- * based on a patch sent by Antony Pavlov <antonynpavlov@gmail.com>
- * to the barebox mailing list.
- * The subject of the original patch:
- * 'MIPS: qemu-malta: add YAMON-style GT64120 memory map'
- * URL:
- * http://www.mail-archive.com/barebox@lists.infradead.org/msg06128.html
- *
- * based on write_bootloader() in qemu.git/hw/mips_malta.c
- * see GT64120 manual and qemu.git/hw/gt64xxx.c for details
- */
-
- /* move GT64120 registers from 0x14000000 to 0x1be00000 */
- li t1, KSEG1ADDR(GT_DEF_BASE)
- li t0, CPU_TO_GT32(0xdf000000)
- sw t0, GT_ISD_OFS(t1)
-
- /* setup MEM-to-PCI0 mapping */
- li t1, KSEG1ADDR(MALTA_GT_BASE)
-
- /* setup PCI0 io window to 0x18000000-0x181fffff */
- li t0, CPU_TO_GT32(0xc0000000)
- sw t0, GT_PCI0IOLD_OFS(t1)
- li t0, CPU_TO_GT32(0x40000000)
- sw t0, GT_PCI0IOHD_OFS(t1)
-
- /* setup PCI0 mem windows */
- li t0, CPU_TO_GT32(0x80000000)
- sw t0, GT_PCI0M0LD_OFS(t1)
- li t0, CPU_TO_GT32(0x3f000000)
- sw t0, GT_PCI0M0HD_OFS(t1)
-
- li t0, CPU_TO_GT32(0xc1000000)
- sw t0, GT_PCI0M1LD_OFS(t1)
- li t0, CPU_TO_GT32(0x5e000000)
- sw t0, GT_PCI0M1HD_OFS(t1)
-
- jr ra
- nop
diff --git a/board/qemu-malta/qemu-malta.c b/board/qemu-malta/qemu-malta.c
deleted file mode 100644
index 7eddf1ce66..0000000000
--- a/board/qemu-malta/qemu-malta.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
- *
- * SPDX-License-Identifier: GPL-2.0
- */
-
-#include <common.h>
-#include <netdev.h>
-
-#include <asm/addrspace.h>
-#include <asm/io.h>
-#include <asm/malta.h>
-#include <pci_gt64120.h>
-
-phys_size_t initdram(int board_type)
-{
- return CONFIG_SYS_MEM_SIZE;
-}
-
-int checkboard(void)
-{
- puts("Board: MIPS Malta CoreLV (Qemu)\n");
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
-
-void _machine_restart(void)
-{
- void __iomem *reset_base;
-
- reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE);
- __raw_writel(GORESET, reset_base);
-}
-
-void pci_init_board(void)
-{
- set_io_port_base(CKSEG1ADDR(MALTA_IO_PORT_BASE));
-
- gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE),
- 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
- 0x10000000, 0x10000000, 128 * 1024 * 1024,
- 0x00000000, 0x00000000, 0x20000);
-}
diff --git a/board/rbc823/u-boot.lds b/board/rbc823/u-boot.lds
index 191f9eb837..7676cf43b1 100644
--- a/board/rbc823/u-boot.lds
+++ b/board/rbc823/u-boot.lds
@@ -19,10 +19,10 @@ SECTIONS
arch/powerpc/cpu/mpc8xx/start.o (.text*)
arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- lib/libgeneric.o (.text*)
- net/libnet.o (.text*)
- arch/powerpc/cpu/mpc8xx/libmpc8xx.o (.text*)
- arch/powerpc/lib/libpowerpc.o (.text*)
+ lib/built-in.o (.text*)
+ net/built-in.o (.text*)
+ arch/powerpc/cpu/mpc8xx/built-in.o (.text*)
+ arch/powerpc/lib/built-in.o (.text*)
. = env_offset;
common/env_embedded.o (.text*)
diff --git a/board/renesas/ecovec/ecovec.c b/board/renesas/ecovec/ecovec.c
index e2d365a187..fb4acf3641 100644
--- a/board/renesas/ecovec/ecovec.c
+++ b/board/renesas/ecovec/ecovec.c
@@ -57,8 +57,7 @@ int board_late_init(void)
outl(inl(MSTPCR2) & ~0x10000000, MSTPCR2);
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
- i2c_set_bus_num(CONFIG_SYS_I2C_MODULE); /* Use I2C 1 */
+ i2c_set_bus_num(1); /* Use I2C 1 */
/* Read MAC address */
i2c_read(0x50, 0x10, 0, mac, 6);
diff --git a/board/sandburst/karef/Makefile b/board/sandburst/karef/Makefile
index 05c818791c..f890008be2 100644
--- a/board/sandburst/karef/Makefile
+++ b/board/sandburst/karef/Makefile
@@ -9,10 +9,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
# TBS: add for debugging purposes
BUILDUSER := $(shell whoami)
FORCEBUILD := $(shell rm -f karef.o)
diff --git a/board/sandburst/metrobox/Makefile b/board/sandburst/metrobox/Makefile
index 76dfffc9c7..37d91a51a3 100644
--- a/board/sandburst/metrobox/Makefile
+++ b/board/sandburst/metrobox/Makefile
@@ -8,10 +8,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
# TBS: add for debugging purposes
BUILDUSER := $(shell whoami)
FORCEBUILD := $(shell rm -f metrobox.o)
diff --git a/board/sbc8548/Makefile b/board/sbc8548/Makefile
index b1e32a668b..4c9b6cd60c 100644
--- a/board/sbc8548/Makefile
+++ b/board/sbc8548/Makefile
@@ -11,4 +11,4 @@
obj-y += sbc8548.o
obj-y += law.o
obj-y += tlb.o
-obj-$(CONFIG_FSL_DDR2) += ddr.o
+obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
diff --git a/board/sbc8548/ddr.c b/board/sbc8548/ddr.c
index 9508561133..24cc776a25 100644
--- a/board/sbc8548/ddr.c
+++ b/board/sbc8548/ddr.c
@@ -9,8 +9,8 @@
#include <common.h>
#include <i2c.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
@@ -91,7 +91,8 @@ void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
*/
phys_size_t fixed_sdram(void)
{
- volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
+ struct ccsr_ddr __iomem *ddr =
+ (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
out_be32(&ddr->cs0_bnds, 0x0000007f);
out_be32(&ddr->cs1_bnds, 0x008000ff);
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index 3cd945f2c2..d584276253 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -15,7 +15,7 @@
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <spd_sdram.h>
#include <netdev.h>
diff --git a/board/sbc8641d/Makefile b/board/sbc8641d/Makefile
index 9626b06a5a..a9b20266bc 100644
--- a/board/sbc8641d/Makefile
+++ b/board/sbc8641d/Makefile
@@ -7,4 +7,4 @@
obj-y += sbc8641d.o
obj-y += law.o
-obj-$(CONFIG_FSL_DDR2) += ddr.o
+obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
diff --git a/board/sbc8641d/ddr.c b/board/sbc8641d/ddr.c
index 996ffe206d..b31ea3432e 100644
--- a/board/sbc8641d/ddr.c
+++ b/board/sbc8641d/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c
index 0b5e8dc17e..4906be4889 100644
--- a/board/sbc8641d/sbc8641d.c
+++ b/board/sbc8641d/sbc8641d.c
@@ -18,7 +18,7 @@
#include <asm/processor.h>
#include <asm/immap_86xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/fsl_serdes.h>
#include <libfdt.h>
#include <fdt_support.h>
@@ -93,7 +93,7 @@ long int fixed_sdram (void)
{
#if !defined(CONFIG_SYS_RAMBOOT)
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
+ volatile struct ccsr_ddr *ddr = &immap->im_ddr1;
ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
@@ -111,7 +111,7 @@ long int fixed_sdram (void)
ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2;
ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
- ddr->sdram_mode_cntl = CONFIG_SYS_DDR_MODE_CTL;
+ ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTL;
ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
@@ -142,7 +142,7 @@ long int fixed_sdram (void)
ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2;
ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1;
ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2;
- ddr->sdram_mode_cntl = CONFIG_SYS_DDR2_MODE_CTL;
+ ddr->sdram_md_cntl = CONFIG_SYS_DDR2_MODE_CTL;
ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL;
ddr->sdram_data_init = CONFIG_SYS_DDR2_DATA_INIT;
ddr->sdram_clk_cntl = CONFIG_SYS_DDR2_CLK_CTRL;
diff --git a/board/siemens/common/board.c b/board/siemens/common/board.c
index 6279c3281c..32d2ee4de9 100644
--- a/board/siemens/common/board.c
+++ b/board/siemens/common/board.c
@@ -42,7 +42,7 @@ void set_mux_conf_regs(void)
{
/* Initalize the board header */
enable_i2c0_pin_mux();
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ i2c_set_bus_num(0);
if (read_eeprom() < 0)
puts("Could not get board ID.\n");
@@ -67,7 +67,7 @@ int board_init(void)
#if defined(CONFIG_HW_WATCHDOG)
hw_watchdog_init();
#endif /* defined(CONFIG_HW_WATCHDOG) */
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ i2c_set_bus_num(0);
if (read_eeprom() < 0)
puts("Could not get board ID.\n");
diff --git a/board/siemens/dxr2/Makefile b/board/siemens/dxr2/Makefile
index 5129c6e3b1..f15993216b 100644
--- a/board/siemens/dxr2/Makefile
+++ b/board/siemens/dxr2/Makefile
@@ -11,10 +11,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
ifdef CONFIG_SPL_BUILD
obj-y := mux.o
endif
diff --git a/board/siemens/pxm2/Makefile b/board/siemens/pxm2/Makefile
index 5129c6e3b1..f15993216b 100644
--- a/board/siemens/pxm2/Makefile
+++ b/board/siemens/pxm2/Makefile
@@ -11,10 +11,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
ifdef CONFIG_SPL_BUILD
obj-y := mux.o
endif
diff --git a/board/siemens/rut/Makefile b/board/siemens/rut/Makefile
index 5129c6e3b1..f15993216b 100644
--- a/board/siemens/rut/Makefile
+++ b/board/siemens/rut/Makefile
@@ -11,10 +11,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
ifdef CONFIG_SPL_BUILD
obj-y := mux.o
endif
diff --git a/board/socrates/Makefile b/board/socrates/Makefile
index 0a088100e8..79bda718d5 100644
--- a/board/socrates/Makefile
+++ b/board/socrates/Makefile
@@ -12,4 +12,4 @@ obj-y += law.o
obj-y += tlb.o
obj-y += nand.o
obj-y += sdram.o
-obj-$(CONFIG_FSL_DDR2) += ddr.o
+obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o
diff --git a/board/socrates/ddr.c b/board/socrates/ddr.c
index e9db476f48..6bad4da394 100644
--- a/board/socrates/ddr.c
+++ b/board/socrates/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c
index 313efae90f..aebd02f76c 100644
--- a/board/socrates/sdram.c
+++ b/board/socrates/sdram.c
@@ -8,7 +8,7 @@
#include <common.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <spd_sdram.h>
@@ -24,7 +24,8 @@
*/
phys_size_t fixed_sdram(void)
{
- volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
+ struct ccsr_ddr __iomem *ddr =
+ (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
/*
* Disable memory controller.
diff --git a/board/spd8xx/u-boot.lds b/board/spd8xx/u-boot.lds
index 2a68934c32..463af7eaa4 100644
--- a/board/spd8xx/u-boot.lds
+++ b/board/spd8xx/u-boot.lds
@@ -18,8 +18,8 @@ SECTIONS
arch/powerpc/cpu/mpc8xx/start.o (.text*)
arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- net/libnet.o (.text*)
- arch/powerpc/cpu/mpc8xx/libmpc8xx.o (.text*)
+ net/built-in.o (.text*)
+ arch/powerpc/cpu/mpc8xx/built-in.o (.text*)
*(.text.v*printf)
. = DEFINED(env_offset) ? env_offset : .;
diff --git a/board/stx/stxgp3/Makefile b/board/stx/stxgp3/Makefile
index 9b724347de..78e2d6c96f 100644
--- a/board/stx/stxgp3/Makefile
+++ b/board/stx/stxgp3/Makefile
@@ -9,4 +9,4 @@ obj-y += stxgp3.o
obj-y += law.o
obj-y += tlb.o
obj-y += flash.o
-obj-$(CONFIG_FSL_DDR1) += ddr.o
+obj-$(CONFIG_SYS_FSL_DDR1) += ddr.o
diff --git a/board/stx/stxgp3/ddr.c b/board/stx/stxgp3/ddr.c
index 9e79815278..41d4cfe738 100644
--- a/board/stx/stxgp3/ddr.c
+++ b/board/stx/stxgp3/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/stx/stxgp3/stxgp3.c b/board/stx/stxgp3/stxgp3.c
index bd683f6af8..c80d5259ce 100644
--- a/board/stx/stxgp3/stxgp3.c
+++ b/board/stx/stxgp3/stxgp3.c
@@ -18,7 +18,7 @@
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <ioports.h>
#include <asm/io.h>
#include <spd_sdram.h>
diff --git a/board/stx/stxssa/Makefile b/board/stx/stxssa/Makefile
index 17e0aaea7e..b1d4b0a270 100644
--- a/board/stx/stxssa/Makefile
+++ b/board/stx/stxssa/Makefile
@@ -8,4 +8,4 @@
obj-y += stxssa.o
obj-y += law.o
obj-y += tlb.o
-obj-$(CONFIG_FSL_DDR1) += ddr.o
+obj-$(CONFIG_SYS_FSL_DDR1) += ddr.o
diff --git a/board/stx/stxssa/ddr.c b/board/stx/stxssa/ddr.c
index 71be3bf636..1ccd4c5183 100644
--- a/board/stx/stxssa/ddr.c
+++ b/board/stx/stxssa/ddr.c
@@ -9,8 +9,8 @@
#include <common.h>
#include <i2c.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
diff --git a/board/stx/stxssa/stxssa.c b/board/stx/stxssa/stxssa.c
index c08a18bffe..f5c3d750ce 100644
--- a/board/stx/stxssa/stxssa.c
+++ b/board/stx/stxssa/stxssa.c
@@ -19,7 +19,7 @@
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <ioports.h>
#include <asm/io.h>
#include <spd_sdram.h>
diff --git a/board/svm_sc8xx/u-boot.lds b/board/svm_sc8xx/u-boot.lds
index 49226251b2..df564e9395 100644
--- a/board/svm_sc8xx/u-boot.lds
+++ b/board/svm_sc8xx/u-boot.lds
@@ -17,11 +17,11 @@ SECTIONS
/* the sector layout of our flash chips! XXX FIXME XXX */
arch/powerpc/cpu/mpc8xx/start.o (.text*)
arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- lib/libgeneric.o (.text*)
- net/libnet.o (.text*)
- arch/powerpc/cpu/mpc8xx/libmpc8xx.o (.text*)
- arch/powerpc/lib/libpowerpc.o (.text*)
- board/svm_sc8xx/libsvm_sc8xx.o (.text*)
+ lib/built-in.o (.text*)
+ net/built-in.o (.text*)
+ arch/powerpc/cpu/mpc8xx/built-in.o (.text*)
+ arch/powerpc/lib/built-in.o (.text*)
+ board/svm_sc8xx/built-in.o (.text*)
*(.text.*printf)
*(.text.do_mem_*)
*(.text.flash*)
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 1459fae253..33693e4ead 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -380,7 +380,7 @@ const struct dpll_params *get_dpll_ddr_params(void)
struct am335x_baseboard_id header;
enable_i2c0_pin_mux();
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
if (read_eeprom(&header) < 0)
puts("Could not get board ID.\n");
@@ -464,26 +464,14 @@ void sdram_init(void)
*/
int board_init(void)
{
-#ifdef CONFIG_NOR
- const u32 gpmc_nor[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1,
- STNOR_GPMC_CONFIG2, STNOR_GPMC_CONFIG3, STNOR_GPMC_CONFIG4,
- STNOR_GPMC_CONFIG5, STNOR_GPMC_CONFIG6, STNOR_GPMC_CONFIG7 };
-#endif
-
#if defined(CONFIG_HW_WATCHDOG)
hw_watchdog_init();
#endif
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
-
+#if defined(CONFIG_NOR) || defined(CONFIG_NAND)
gpmc_init();
-
-#ifdef CONFIG_NOR
- /* Reconfigure CS0 for NOR instead of NAND. */
- enable_gpmc_cs_config(gpmc_nor, &gpmc_cfg->cs[0],
- CONFIG_SYS_FLASH_BASE, GPMC_SIZE_16M);
#endif
-
return 0;
}
diff --git a/board/ti/am335x/u-boot.lds b/board/ti/am335x/u-boot.lds
index 9f96a43898..6a734b30ac 100644
--- a/board/ti/am335x/u-boot.lds
+++ b/board/ti/am335x/u-boot.lds
@@ -35,7 +35,7 @@ SECTIONS
{
*(.__image_copy_start)
CPUDIR/start.o (.text*)
- board/ti/am335x/libam335x.o (.text*)
+ board/ti/am335x/built-in.o (.text*)
*(.text*)
}
diff --git a/board/ti/am3517crane/am3517crane.c b/board/ti/am3517crane/am3517crane.c
index 5eb97ff378..a649697257 100644
--- a/board/ti/am3517crane/am3517crane.c
+++ b/board/ti/am3517crane/am3517crane.c
@@ -43,8 +43,8 @@ int board_init(void)
*/
int misc_init_r(void)
{
-#ifdef CONFIG_DRIVER_OMAP34XX_I2C
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#ifdef CONFIG_SYS_I2C_OMAP34XX
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
#endif
dieid_num_r();
diff --git a/board/ti/beagle/Makefile b/board/ti/beagle/Makefile
index 9f55e8f358..7a858be5e4 100644
--- a/board/ti/beagle/Makefile
+++ b/board/ti/beagle/Makefile
@@ -5,5 +5,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y := $(BOARD).o
+obj-y := beagle.o
obj-$(CONFIG_STATUS_LED) += led.o
diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c
index c71c218529..81dd081d76 100644
--- a/board/ti/evm/evm.c
+++ b/board/ti/evm/evm.c
@@ -146,8 +146,8 @@ void get_board_mem_timings(struct board_sdrc_timings *timings)
int misc_init_r(void)
{
-#ifdef CONFIG_DRIVER_OMAP34XX_I2C
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#ifdef CONFIG_SYS_I2C_OMAP34XX
+ i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
#endif
#if defined(CONFIG_CMD_NET)
diff --git a/board/toradex/colibri_t20_iris/Makefile b/board/toradex/colibri_t20_iris/Makefile
index 7ca3fe596f..ebeac70ea1 100644
--- a/board/toradex/colibri_t20_iris/Makefile
+++ b/board/toradex/colibri_t20_iris/Makefile
@@ -4,9 +4,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
-$(shell mkdir -p $(obj)../../nvidia/common)
-$(shell mkdir -p $(obj)../colibri_t20-common)
-
obj-y := ../../nvidia/common/board.o
obj-y += ../colibri_t20-common/colibri_t20-common.o
obj-y += colibri_t20_iris.o
diff --git a/board/tqc/tqm5200/Makefile b/board/tqc/tqm5200/Makefile
index 757f4729ab..80c1eba87c 100644
--- a/board/tqc/tqm5200/Makefile
+++ b/board/tqc/tqm5200/Makefile
@@ -6,6 +6,3 @@
#
obj-y := tqm5200.o cmd_stk52xx.o cmd_tb5200.o cam5200_flash.o
-
-$(obj)cam5200_flash.o: cam5200_flash.c
- $(CC) $(CFLAGS) -c -o $@ $<
diff --git a/board/tqc/tqm8260/Makefile b/board/tqc/tqm8260/Makefile
index dc4a528083..6b8573d9ab 100644
--- a/board/tqc/tqm8260/Makefile
+++ b/board/tqc/tqm8260/Makefile
@@ -5,8 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../tqm8xx/)
-endif
-
obj-y = tqm8260.o ../tqm8xx/load_sernum_ethaddr.o
diff --git a/board/tqc/tqm8272/Makefile b/board/tqc/tqm8272/Makefile
index 09af765f05..8bf02414e3 100644
--- a/board/tqc/tqm8272/Makefile
+++ b/board/tqc/tqm8272/Makefile
@@ -5,8 +5,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../tqm8xx/)
-endif
-
obj-y = tqm8272.o ../tqm8xx/load_sernum_ethaddr.o nand.o
diff --git a/board/tqc/tqm8xx/u-boot.lds b/board/tqc/tqm8xx/u-boot.lds
index cbfc94f57e..b77ae56c51 100644
--- a/board/tqc/tqm8xx/u-boot.lds
+++ b/board/tqc/tqm8xx/u-boot.lds
@@ -18,13 +18,13 @@ SECTIONS
arch/powerpc/cpu/mpc8xx/start.o (.text*)
arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- arch/powerpc/cpu/mpc8xx/libmpc8xx.o (.text*)
- arch/powerpc/lib/libpowerpc.o (.text*)
- board/tqc/tqm8xx/libtqm8xx.o (.text*)
- disk/libdisk.o (.text*)
- drivers/net/libnet.o (.text*)
- drivers/libdrivers.o (.text.pcmcia_on)
- drivers/libdrivers.o (.text.pcmcia_hardware_enable)
+ arch/powerpc/cpu/mpc8xx/built-in.o (.text*)
+ arch/powerpc/lib/built-in.o (.text*)
+ board/tqc/tqm8xx/built-in.o (.text*)
+ disk/built-in.o (.text*)
+ drivers/net/built-in.o (.text*)
+ drivers/built-in.o (.text.pcmcia_on)
+ drivers/built-in.o (.text.pcmcia_hardware_enable)
. = DEFINED(env_offset) ? env_offset : .;
common/env_embedded.o (.ppcenv*)
diff --git a/board/vpac270/u-boot-spl.lds b/board/vpac270/u-boot-spl.lds
index 08c78b3dbb..02d107c4b9 100644
--- a/board/vpac270/u-boot-spl.lds
+++ b/board/vpac270/u-boot-spl.lds
@@ -20,8 +20,8 @@ SECTIONS
.text.0 :
{
arch/arm/cpu/pxa/start.o (.text*)
- board/vpac270/libvpac270.o (.text*)
- drivers/mtd/onenand/libonenand.o (.text*)
+ board/vpac270/built-in.o (.text*)
+ drivers/mtd/onenand/built-in.o (.text*)
}
diff --git a/board/xes/xpedite517x/ddr.c b/board/xes/xpedite517x/ddr.c
index f48c02fdae..fd602ea7e0 100644
--- a/board/xes/xpedite517x/ddr.c
+++ b/board/xes/xpedite517x/ddr.c
@@ -7,8 +7,8 @@
#include <common.h>
#include <i2c.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void get_spd(ddr2_spd_eeprom_t *spd, u8 i2c_address)
{
diff --git a/board/xes/xpedite517x/xpedite517x.c b/board/xes/xpedite517x/xpedite517x.c
index 1782042510..b7ad349502 100644
--- a/board/xes/xpedite517x/xpedite517x.c
+++ b/board/xes/xpedite517x/xpedite517x.c
@@ -6,7 +6,7 @@
#include <common.h>
#include <asm/processor.h>
-#include <asm/fsl_ddr_sdram.h>
+#include <fsl_ddr_sdram.h>
#include <asm/mmu.h>
#include <asm/io.h>
#include <fdt_support.h>
diff --git a/board/xes/xpedite520x/ddr.c b/board/xes/xpedite520x/ddr.c
index 3671cb8af9..5c5eadc93f 100644
--- a/board/xes/xpedite520x/ddr.c
+++ b/board/xes/xpedite520x/ddr.c
@@ -9,8 +9,8 @@
#include <common.h>
#include <i2c.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address)
{
diff --git a/board/xes/xpedite537x/ddr.c b/board/xes/xpedite537x/ddr.c
index f41ae73755..56b5a187d8 100644
--- a/board/xes/xpedite537x/ddr.c
+++ b/board/xes/xpedite537x/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
#include <i2c.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void get_spd(ddr2_spd_eeprom_t *spd, u8 i2c_address)
{
diff --git a/board/xes/xpedite550x/ddr.c b/board/xes/xpedite550x/ddr.c
index 9fc6f048c4..0c0605e3a9 100644
--- a/board/xes/xpedite550x/ddr.c
+++ b/board/xes/xpedite550x/ddr.c
@@ -8,8 +8,8 @@
#include <common.h>
#include <i2c.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
void get_spd(ddr3_spd_eeprom_t *spd, u8 i2c_address)
{
diff --git a/board/xilinx/ppc405-generic/Makefile b/board/xilinx/ppc405-generic/Makefile
index 1562f1775e..c9da870657 100644
--- a/board/xilinx/ppc405-generic/Makefile
+++ b/board/xilinx/ppc405-generic/Makefile
@@ -9,8 +9,4 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../../xilinx/ppc405-generic)
-endif
-
obj-y += ../../xilinx/ppc405-generic/xilinx_ppc405_generic.o
diff --git a/board/xilinx/ppc440-generic/Makefile b/board/xilinx/ppc440-generic/Makefile
index b2227c58a5..0acd95d6e4 100644
--- a/board/xilinx/ppc440-generic/Makefile
+++ b/board/xilinx/ppc440-generic/Makefile
@@ -9,9 +9,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../../xilinx/ppc440-generic)
-endif
-
obj-y += ../../xilinx/ppc440-generic/xilinx_ppc440_generic.o
extra-y += ../../xilinx/ppc440-generic/init.o