diff options
Diffstat (limited to 'board')
106 files changed, 1659 insertions, 824 deletions
diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c index ce4acc13e0..e947e54c39 100644 --- a/board/BuR/common/common.c +++ b/board/BuR/common/common.c @@ -259,7 +259,7 @@ static int load_devicetree(void) } #ifdef CONFIG_NAND dtbsize = 0x20000; - rc = nand_read_skip_bad(&nand_info[0], 0x40000, (size_t *)&dtbsize, + rc = nand_read_skip_bad(nand_info[0], 0x40000, (size_t *)&dtbsize, NULL, 0x20000, (u_char *)dtbaddr); #else char *dtbname = getenv("dtb"); diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c index 7b7cd2c426..6398bcbc9e 100644 --- a/board/atmel/at91sam9261ek/at91sam9261ek.c +++ b/board/atmel/at91sam9261ek/at91sam9261ek.c @@ -212,7 +212,7 @@ void lcd_show_board_info(void) dram_size += gd->bd->bi_dram[i].size; nand_size = 0; for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) - nand_size += nand_info[i].size; + nand_size += nand_info[i]->size; lcd_printf (" %ld MB SDRAM, %ld MB NAND\n", dram_size >> 20, nand_size >> 20 ); diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c index af68e10390..04e5812db3 100644 --- a/board/atmel/at91sam9263ek/at91sam9263ek.c +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -191,7 +191,7 @@ void lcd_show_board_info(void) dram_size += gd->bd->bi_dram[i].size; nand_size = 0; for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) - nand_size += nand_info[i].size; + nand_size += nand_info[i]->size; #ifndef CONFIG_SYS_NO_FLASH flash_size = 0; for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c index 4c6431266f..6871916865 100644 --- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c +++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c @@ -272,7 +272,7 @@ void lcd_show_board_info(void) dram_size += gd->bd->bi_dram[i].size; nand_size = 0; for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) - nand_size += nand_info[i].size; + nand_size += nand_info[i]->size; lcd_printf (" %ld MB SDRAM, %ld MB NAND\n", dram_size >> 20, nand_size >> 20 ); diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c index d3555bbdf6..fc4f50d219 100644 --- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c +++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c @@ -124,7 +124,7 @@ void lcd_show_board_info(void) dram_size += gd->bd->bi_dram[i].size; nand_size = 0; for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) - nand_size += nand_info[i].size; + nand_size += nand_info[i]->size; lcd_printf(" %ld MB SDRAM, %ld MB NAND\n", dram_size >> 20, nand_size >> 20); diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c index 9ef2864bb1..994f246078 100644 --- a/board/atmel/at91sam9rlek/at91sam9rlek.c +++ b/board/atmel/at91sam9rlek/at91sam9rlek.c @@ -151,7 +151,7 @@ void lcd_show_board_info(void) dram_size += gd->bd->bi_dram[i].size; nand_size = 0; for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) - nand_size += nand_info[i].size; + nand_size += nand_info[i]->size; lcd_printf (" %ld MB SDRAM, %ld MB NAND\n", dram_size >> 20, nand_size >> 20 ); diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c index c14df303b2..b0d440d728 100644 --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c @@ -196,7 +196,7 @@ void lcd_show_board_info(void) dram_size += gd->bd->bi_dram[i].size; nand_size = 0; for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) - nand_size += nand_info[i].size; + nand_size += nand_info[i]->size; lcd_printf(" %ld MB SDRAM, %ld MB NAND\n", dram_size >> 20, nand_size >> 20); diff --git a/board/atmel/sama5d3xek/sama5d3xek.c b/board/atmel/sama5d3xek/sama5d3xek.c index e8ee612036..fa90270b86 100644 --- a/board/atmel/sama5d3xek/sama5d3xek.c +++ b/board/atmel/sama5d3xek/sama5d3xek.c @@ -207,7 +207,7 @@ void lcd_show_board_info(void) nand_size = 0; #ifdef CONFIG_NAND_ATMEL for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) - nand_size += nand_info[i].size; + nand_size += nand_info[i]->size; #endif lcd_printf("%ld MB SDRAM, %lld MB NAND\n", dram_size >> 20, nand_size >> 20); diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/board/atmel/sama5d4_xplained/sama5d4_xplained.c index f4eef9609f..23ec274468 100644 --- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c +++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c @@ -191,7 +191,7 @@ void lcd_show_board_info(void) nand_size = 0; #ifdef CONFIG_NAND_ATMEL for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) - nand_size += nand_info[i].size; + nand_size += nand_info[i]->size; #endif lcd_printf("%ld MB SDRAM, %ld MB NAND\n", dram_size >> 20, nand_size >> 20); diff --git a/board/atmel/sama5d4ek/sama5d4ek.c b/board/atmel/sama5d4ek/sama5d4ek.c index aee621789e..72bad23087 100644 --- a/board/atmel/sama5d4ek/sama5d4ek.c +++ b/board/atmel/sama5d4ek/sama5d4ek.c @@ -187,7 +187,7 @@ void lcd_show_board_info(void) nand_size = 0; #ifdef CONFIG_NAND_ATMEL for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) - nand_size += nand_info[i].size; + nand_size += nand_info[i]->size; #endif lcd_printf("%ld MB SDRAM, %ld MB NAND\n", dram_size >> 20, nand_size >> 20); diff --git a/board/avionic-design/common/tamonten-ng.c b/board/avionic-design/common/tamonten-ng.c index 1704627112..106be9b761 100644 --- a/board/avionic-design/common/tamonten-ng.c +++ b/board/avionic-design/common/tamonten-ng.c @@ -42,12 +42,12 @@ void pinmux_init(void) void gpio_early_init(void) { /* Turn on the alive signal */ - gpio_request(GPIO_PV2, "ALIVE"); - gpio_direction_output(GPIO_PV2, 1); + gpio_request(TEGRA_GPIO(V, 2), "ALIVE"); + gpio_direction_output(TEGRA_GPIO(V, 2), 1); /* Remove the reset on the external periph */ - gpio_request(GPIO_PI4, "nRST_PERIPH"); - gpio_direction_output(GPIO_PI4, 1); + gpio_request(TEGRA_GPIO(I, 4), "nRST_PERIPH"); + gpio_direction_output(TEGRA_GPIO(I, 4), 1); } void pmu_write(uchar reg, uchar data) @@ -73,8 +73,8 @@ void board_sdmmc_voltage_init(void) pmu_write(PMU_REG_LDO5, PMU_LDO5(HIGH_POWER, 3300)); /* Switch the power on */ - gpio_request(GPIO_PJ2, "EN_3V3_EMMC"); - gpio_direction_output(GPIO_PJ2, 1); + gpio_request(TEGRA_GPIO(J, 2), "EN_3V3_EMMC"); + gpio_direction_output(TEGRA_GPIO(J, 2), 1); } /* diff --git a/board/avionic-design/common/tamonten.c b/board/avionic-design/common/tamonten.c index 9c8677943a..4fb36a2cf8 100644 --- a/board/avionic-design/common/tamonten.c +++ b/board/avionic-design/common/tamonten.c @@ -23,8 +23,8 @@ #ifdef CONFIG_BOARD_EARLY_INIT_F void gpio_early_init(void) { - gpio_request(GPIO_PI4, NULL); - gpio_direction_output(GPIO_PI4, 1); + gpio_request(TEGRA_GPIO(I, 4), NULL); + gpio_direction_output(TEGRA_GPIO(I, 4), 1); } #endif diff --git a/board/esd/common/esd405ep_nand.c b/board/esd/common/esd405ep_nand.c index f46936ca36..51ac10c8c0 100644 --- a/board/esd/common/esd405ep_nand.c +++ b/board/esd/common/esd405ep_nand.c @@ -16,7 +16,7 @@ */ static void esd405ep_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) { - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); if (ctrl & NAND_CTRL_CHANGE) { if ( ctrl & NAND_CLE ) out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CLE); diff --git a/board/freescale/b4860qds/Makefile b/board/freescale/b4860qds/Makefile index 0acd2a9aa4..673d2ea56a 100644 --- a/board/freescale/b4860qds/Makefile +++ b/board/freescale/b4860qds/Makefile @@ -5,11 +5,11 @@ # ifdef CONFIG_SPL_BUILD -obj-y += spl.o +obj-y += spl.o else obj-y += b4860qds.o -obj-$(CONFIG_B4860QDS)+= eth_b4860qds.o -obj-$(CONFIG_PCI) += pci.o +obj-$(CONFIG_B4860QDS) += eth_b4860qds.o +obj-$(CONFIG_PCI) += pci.o endif obj-y += ddr.o diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c index eb10a6f364..31b186ea8c 100644 --- a/board/freescale/b4860qds/ddr.c +++ b/board/freescale/b4860qds/ddr.c @@ -179,15 +179,13 @@ phys_size_t initdram(int board_type) #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) puts("Initializing....using SPD\n"); - dram_size = fsl_ddr_sdram(); - - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - #else dram_size = fsl_ddr_sdram_size(); #endif + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + return dram_size; } diff --git a/board/freescale/b4860qds/spl.c b/board/freescale/b4860qds/spl.c index 3f7cc03581..fabc78301a 100644 --- a/board/freescale/b4860qds/spl.c +++ b/board/freescale/b4860qds/spl.c @@ -91,6 +91,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) get_clocks(); mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, CONFIG_SPL_RELOC_MALLOC_SIZE); + gd->flags |= GD_FLG_FULL_MALLOC_INIT; #ifndef CONFIG_SPL_NAND_BOOT env_init(); diff --git a/board/freescale/bsc9131rdb/Makefile b/board/freescale/bsc9131rdb/Makefile index b26d3a1e63..8027750efb 100644 --- a/board/freescale/bsc9131rdb/Makefile +++ b/board/freescale/bsc9131rdb/Makefile @@ -13,15 +13,11 @@ endif endif ifdef MINIMAL - -obj-y += spl_minimal.o tlb.o law.o - +obj-y += spl_minimal.o else - -obj-y += bsc9131rdb.o -obj-y += ddr.o -obj-y += law.o -obj-y += tlb.o -#obj-y += bsc9131rdb_mux.o - +obj-y += bsc9131rdb.o +obj-y += ddr.o endif + +obj-y += law.o +obj-y += tlb.o diff --git a/board/freescale/bsc9132qds/Makefile b/board/freescale/bsc9132qds/Makefile index 2e4170f512..54193350af 100644 --- a/board/freescale/bsc9132qds/Makefile +++ b/board/freescale/bsc9132qds/Makefile @@ -13,14 +13,11 @@ endif endif ifdef MINIMAL - -obj-y += spl_minimal.o tlb.o law.o - +obj-y += spl_minimal.o else - obj-y += bsc9132qds.o obj-y += ddr.o +endif + obj-y += law.o obj-y += tlb.o - -endif diff --git a/board/freescale/c29xpcie/Makefile b/board/freescale/c29xpcie/Makefile index 818484a57d..93b3cba031 100644 --- a/board/freescale/c29xpcie/Makefile +++ b/board/freescale/c29xpcie/Makefile @@ -11,15 +11,15 @@ endif endif ifdef MINIMAL -obj-y += spl_minimal.o tlb.o law.o +obj-y += spl_minimal.o else ifdef CONFIG_SPL_BUILD obj-y += spl.o endif - obj-y += c29xpcie.o obj-y += cpld.o obj-y += ddr.o +endif + obj-y += law.o obj-y += tlb.o -endif diff --git a/board/freescale/c29xpcie/spl.c b/board/freescale/c29xpcie/spl.c index 3d31d41a4f..d8d73c70b8 100644 --- a/board/freescale/c29xpcie/spl.c +++ b/board/freescale/c29xpcie/spl.c @@ -57,6 +57,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) get_clocks(); mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, CONFIG_SPL_RELOC_MALLOC_SIZE); + gd->flags |= GD_FLG_FULL_MALLOC_INIT; /* relocate environment function pointers etc. */ nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, diff --git a/board/freescale/common/ls102xa_stream_id.c b/board/freescale/common/ls102xa_stream_id.c index 3d5404ee10..0abaffb334 100644 --- a/board/freescale/common/ls102xa_stream_id.c +++ b/board/freescale/common/ls102xa_stream_id.c @@ -12,9 +12,12 @@ void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num) { void *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; int i; + u32 icid; - for (i = 0; i < num; i++) - out_be32((u32 *)(scfg + id[i].offset), id[i].stream_id); + for (i = 0; i < num; i++) { + icid = (id[i].stream_id & 0xff) << 24; + out_be32((u32 *)(scfg + id[i].offset), icid); + } } void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size) diff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c index 113295f64a..0db0ed6670 100644 --- a/board/freescale/common/qixis.c +++ b/board/freescale/common/qixis.c @@ -14,6 +14,13 @@ #include <i2c.h> #include "qixis.h" +#ifndef QIXIS_LBMAP_BRDCFG_REG +/* + * For consistency with existing platforms + */ +#define QIXIS_LBMAP_BRDCFG_REG 0x00 +#endif + #ifdef CONFIG_SYS_I2C_FPGA_ADDR u8 qixis_read_i2c(unsigned int reg) { @@ -27,6 +34,7 @@ void qixis_write_i2c(unsigned int reg, u8 value) } #endif +#ifdef QIXIS_BASE u8 qixis_read(unsigned int reg) { void *p = (void *)QIXIS_BASE; @@ -40,6 +48,7 @@ void qixis_write(unsigned int reg, u8 value) out_8(p + reg, value); } +#endif u16 qixis_read_minor(void) { @@ -142,9 +151,9 @@ static void __maybe_unused set_lbmap(int lbmap) { u8 reg; - reg = QIXIS_READ(brdcfg[0]); + reg = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]); reg = (reg & ~QIXIS_LBMAP_MASK) | lbmap; - QIXIS_WRITE(brdcfg[0], reg); + QIXIS_WRITE(brdcfg[QIXIS_LBMAP_BRDCFG_REG], reg); } static void __maybe_unused set_rcw_src(int rcw_src) diff --git a/board/freescale/ls1012afrdm/Kconfig b/board/freescale/ls1012afrdm/Kconfig new file mode 100644 index 0000000000..a34521cf79 --- /dev/null +++ b/board/freescale/ls1012afrdm/Kconfig @@ -0,0 +1,15 @@ +if TARGET_LS1012AFRDM + +config SYS_BOARD + default "ls1012afrdm" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls1012afrdm" + +endif diff --git a/board/freescale/ls1012afrdm/MAINTAINERS b/board/freescale/ls1012afrdm/MAINTAINERS new file mode 100644 index 0000000000..842f86f861 --- /dev/null +++ b/board/freescale/ls1012afrdm/MAINTAINERS @@ -0,0 +1,6 @@ +LS1012AFRDM BOARD +M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> +S: Maintained +F: board/freescale/ls1012afrdm/ +F: include/configs/ls1012afrdm.h +F: configs/ls1012afrdm_qspi_defconfig diff --git a/board/freescale/ls1012afrdm/Makefile b/board/freescale/ls1012afrdm/Makefile new file mode 100644 index 0000000000..dbfa2cea38 --- /dev/null +++ b/board/freescale/ls1012afrdm/Makefile @@ -0,0 +1,7 @@ +# +# Copyright 2016 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ls1012afrdm.o diff --git a/board/freescale/ls1012afrdm/README b/board/freescale/ls1012afrdm/README new file mode 100644 index 0000000000..181c4615a8 --- /dev/null +++ b/board/freescale/ls1012afrdm/README @@ -0,0 +1,58 @@ +Overview +-------- +QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance development +platform, with a complete debugging environment. The LS1012AFRDM board +supports the QorIQ LS1012A processor and is optimized to support the +high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports. + +LS1012A SoC Overview +-------------------- +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A +SoC overview. + + LS1012AFRDM board Overview + ----------------------- + - SERDES Connections, 2 lanes supportingspeeds upto 1 Gbit/s + - 2 SGMII 1G PHYs + - DDR Controller + - 4 Gb DDR3L SDRAM memory, running at data rates up to 1 GT/s + operating at 1.35 V + - QSPI + - Onboard 512 Mbit QSPI flash memory running at speed up + to 108/54 MHz + - One high-speed USB 2.0/3.0 port, one USB 2.0 port + - USB 2.0/3.0 port is configured as On-The-Go (OTG) with a + Micro-AB connector. + - USB 2.0 port is a debug port (CMSIS DAP) and is configured + as a Micro-AB device. + - I2C controller + - One I2C bus with connectivity to Arduino headers + - UART + - UART (Console): UART1 (Without flow control) for console + - ARM JTAG support + - ARM Cortex® 10-pin JTAG connector for LS1012A + - CMSIS DAP through K20 microcontroller + - SAI Audio interface + - One SAI port, SAI 2 with full duplex support + - Clocks + - 25 MHz crystal for LS1012A + - 8 MHz Crystal for K20 + - 24 MHz for SC16IS740IPW SPI to Dual UART bridge + - Power Supplies + - 5 V input supply from USB + - 0.9 V, 1.35 V, and 1.8 V for VDD/Core, DDR, I/O, and + other board interfaces + +Booting Options +--------------- +QSPI Flash 1 + +QSPI flash map +-------------- +Images | Size |QSPI Flash Address +------------------------------------------ +RCW + PBI | 1MB | 0x4000_0000 +U-boot | 1MB | 0x4010_0000 +U-boot Env | 1MB | 0x4020_0000 +PPA FIT image | 2MB | 0x4050_0000 +Linux ITB | ~53MB | 0x40A0_0000 diff --git a/board/freescale/ls1012afrdm/ls1012afrdm.c b/board/freescale/ls1012afrdm/ls1012afrdm.c new file mode 100644 index 0000000000..a94a458f53 --- /dev/null +++ b/board/freescale/ls1012afrdm/ls1012afrdm.c @@ -0,0 +1,192 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/fsl_serdes.h> +#include <asm/arch/soc.h> +#include <hwconfig.h> +#include <fsl_csu.h> +#include <environment.h> +#include <fsl_mmdc.h> +#include <netdev.h> + +DECLARE_GLOBAL_DATA_PTR; + +static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits) +{ + int timeout = 1000; + + out_be32(ptr, value); + + while (in_be32(ptr) & bits) { + udelay(100); + timeout--; + } + if (timeout <= 0) + puts("Error: wait for clear timeout.\n"); +} + +int checkboard(void) +{ + puts("Board: LS1012AFRDM "); + + return 0; +} + +void mmdc_init(void) +{ + struct mmdc_p_regs *mmdc = + (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR; + + out_be32(&mmdc->mdscr, CONFIGURATION_REQ); + + /* configure timing parms */ + out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING); + out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0); + out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1); + out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2); + + /* other parms */ + out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC); + out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT); + out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY); + out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL); + + /* out of reset delays */ + out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY); + + /* physical parms */ + out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1); + out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION); + + /* Enable MMDC */ + out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2); + + /* dram init sequence: update MRs */ + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2)); + out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | + CMD_BANK_ADDR_3)); + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1)); + out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) | + CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0)); + + /* dram init sequence: ZQCL */ + out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | + CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0)); + set_wait_for_bits_clear(&mmdc->mpzqhwctrl, + CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL, + FORCE_ZQ_AUTO_CALIBRATION); + + /* Calibrations now: wr lvl */ + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) | + CONFIGURATION_REQ | CMD_LOAD_MODE_REG | + CMD_BANK_ADDR_1)); + out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL)); + set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN); + + mdelay(1); + + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1)); + out_be32(&mmdc->mdscr, CONFIGURATION_REQ); + + mdelay(1); + + /* Calibrations now: Read DQS gating calibration */ + out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | + CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0)); + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3)); + out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN); + out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG); + set_wait_for_bits_clear(&mmdc->mpdgctrl0, + AUTO_RD_DQS_GATING_CALIBRATION_EN, + AUTO_RD_DQS_GATING_CALIBRATION_EN); + + out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | + CMD_BANK_ADDR_3)); + + /* Calibrations now: Read calibration */ + out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | + CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0)); + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3)); + out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN); + set_wait_for_bits_clear(&mmdc->mprddlhwctl, + AUTO_RD_CALIBRATION_EN, + AUTO_RD_CALIBRATION_EN); + + out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | + CMD_BANK_ADDR_3)); + + /* PD, SR */ + out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL); + out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT); + + /* refresh scheme */ + set_wait_for_bits_clear(&mmdc->mdref, + CONFIG_SYS_MMDC_CORE_REFRESH_CTL, + START_REFRESH); + + /* disable CON_REQ */ + out_be32(&mmdc->mdscr, DISABLE_CFG_REQ); +} + +int dram_init(void) +{ + mmdc_init(); + + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} + +int board_early_init_f(void) +{ + fsl_lsch2_early_init_f(); + + return 0; +} + +int board_init(void) +{ + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; + /* + * Set CCI-400 control override register to enable barrier + * transaction + */ + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); + +#ifdef CONFIG_ENV_IS_NOWHERE + gd->env_addr = (ulong)&default_environment[0]; +#endif + +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); +#endif + + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + arch_fixup_fdt(blob); + + ft_cpu_setup(blob, bd); + + return 0; +} diff --git a/board/freescale/ls1012aqds/Kconfig b/board/freescale/ls1012aqds/Kconfig new file mode 100644 index 0000000000..1257ec8d06 --- /dev/null +++ b/board/freescale/ls1012aqds/Kconfig @@ -0,0 +1,15 @@ +if TARGET_LS1012AQDS + +config SYS_BOARD + default "ls1012aqds" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls1012aqds" + +endif diff --git a/board/freescale/ls1012aqds/MAINTAINERS b/board/freescale/ls1012aqds/MAINTAINERS new file mode 100644 index 0000000000..27c4affd30 --- /dev/null +++ b/board/freescale/ls1012aqds/MAINTAINERS @@ -0,0 +1,6 @@ +LS1012AQDS BOARD +M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> +S: Maintained +F: board/freescale/ls1012aqds/ +F: include/configs/ls1012aqds.h +F: configs/ls1012aqds_qspi_defconfig diff --git a/board/freescale/ls1012aqds/Makefile b/board/freescale/ls1012aqds/Makefile new file mode 100644 index 0000000000..0b813f9784 --- /dev/null +++ b/board/freescale/ls1012aqds/Makefile @@ -0,0 +1,7 @@ +# +# Copyright 2016 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ls1012aqds.o diff --git a/board/freescale/ls1012aqds/README b/board/freescale/ls1012aqds/README new file mode 100644 index 0000000000..dee4b302c1 --- /dev/null +++ b/board/freescale/ls1012aqds/README @@ -0,0 +1,59 @@ +Overview +-------- +QorIQ LS1012A Development System (LS1012AQDS) is a high-performance +development platform, with a complete debugging environment. +The LS1012AQDS board supports the QorIQ LS1012A processor and is +optimized to support the high-bandwidth DDR3L memory and +a full complement of high-speed SerDes ports. + +LS1012A SoC Overview +-------------------- +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1012A +SoC overview. + +LS1012AQDS board Overview +----------------------- + - SERDES Connections, 4 lanes supporting: + - PCI Express - 3.0 + - SGMII, SGMII 2.5 + - SATA 3.0 + - DDR Controller + - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s + - QSPI Controller + - A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select + signals to QSPI NOR flash memory (2 virtual banks) and the QSPI + emulator + - USB 3.0 + - One USB 3.0 controller with integrated PHY + - One high-speed USB 3.0 port + - USB 2.0 + - One USB 2.0 controller with ULPI interface + - Two enhanced secure digital host controllers: + - SDHC1 controller can be connected to onboard SDHC connector + - SDHC2 controller: 1-/4-bit SD/MMC card supporting 1.8 V devices + - 2 I2C controllers + - One SATA onboard connectors + - UART + - 5 SAI + - One SAI port with audio codec SGTL5000: + • Provides MIC bias + • Provides headphone and line output + - One SAI port terminated at 2x6 header + - Three SAI Tx/Rx ports terminated at 2x3 headers + - ARM JTAG support + +Booting Options +--------------- +a) QSPI Flash Emu Boot +b) QSPI Flash 1 +c) QSPI Flash 2 + +QSPI flash map +-------------- +Images | Size |QSPI Flash Address +------------------------------------------ +RCW + PBI | 1MB | 0x4000_0000 +U-boot | 1MB | 0x4010_0000 +U-boot Env | 1MB | 0x4020_0000 +PPA FIT image | 2MB | 0x4050_0000 +Linux ITB | ~53MB | 0x40A0_0000 diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c new file mode 100644 index 0000000000..71eea82a03 --- /dev/null +++ b/board/freescale/ls1012aqds/ls1012aqds.c @@ -0,0 +1,234 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include <fdt_support.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/fsl_serdes.h> +#include <asm/arch/fdt.h> +#include <asm/arch/soc.h> +#include <ahci.h> +#include <hwconfig.h> +#include <mmc.h> +#include <scsi.h> +#include <fm_eth.h> +#include <fsl_csu.h> +#include <fsl_esdhc.h> +#include <fsl_mmdc.h> +#include <spl.h> +#include <netdev.h> + +#include "../common/qixis.h" +#include "ls1012aqds_qixis.h" + +DECLARE_GLOBAL_DATA_PTR; + +static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits) +{ + int timeout = 1000; + + out_be32(ptr, value); + + while (in_be32(ptr) & bits) { + udelay(100); + timeout--; + } + if (timeout <= 0) + puts("Error: wait for clear timeout.\n"); +} + +int checkboard(void) +{ + char buf[64]; + u8 sw; + + sw = QIXIS_READ(arch); + printf("Board Arch: V%d, ", sw >> 4); + printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1); + + sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]); + + if (sw & QIXIS_LBMAP_ALTBANK) + printf("flash: 2\n"); + else + printf("flash: 1\n"); + + printf("FPGA: v%d (%s), build %d", + (int)QIXIS_READ(scver), qixis_read_tag(buf), + (int)qixis_read_minor()); + + /* the timestamp string contains "\n" at the end */ + printf(" on %s", qixis_read_time(buf)); + return 0; +} + +void mmdc_init(void) +{ + struct mmdc_p_regs *mmdc = + (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR; + + out_be32(&mmdc->mdscr, CONFIGURATION_REQ); + + /* configure timing parms */ + out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING); + out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0); + out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1); + out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2); + + /* other parms */ + out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC); + out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT); + out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY); + out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL); + + /* out of reset delays */ + out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY); + + /* physical parms */ + out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1); + out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION); + + /* Enable MMDC */ + out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2); + + /* dram init sequence: update MRs */ + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2)); + out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | + CMD_BANK_ADDR_3)); + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1)); + out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) | + CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0)); + + /* dram init sequence: ZQCL */ + out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | + CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0)); + set_wait_for_bits_clear(&mmdc->mpzqhwctrl, + CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL, + FORCE_ZQ_AUTO_CALIBRATION); + + /* Calibrations now: wr lvl */ + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) | + CONFIGURATION_REQ | CMD_LOAD_MODE_REG | + CMD_BANK_ADDR_1)); + out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL)); + set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN); + + mdelay(1); + + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1)); + out_be32(&mmdc->mdscr, CONFIGURATION_REQ); + + mdelay(1); + + /* Calibrations now: Read DQS gating calibration */ + out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | + CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0)); + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3)); + out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN); + out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG); + set_wait_for_bits_clear(&mmdc->mpdgctrl0, + AUTO_RD_DQS_GATING_CALIBRATION_EN, + AUTO_RD_DQS_GATING_CALIBRATION_EN); + + out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | + CMD_BANK_ADDR_3)); + + /* Calibrations now: Read calibration */ + out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | + CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0)); + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3)); + out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN); + set_wait_for_bits_clear(&mmdc->mprddlhwctl, + AUTO_RD_CALIBRATION_EN, + AUTO_RD_CALIBRATION_EN); + + out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | + CMD_BANK_ADDR_3)); + + /* PD, SR */ + out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL); + out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT); + + /* refresh scheme */ + set_wait_for_bits_clear(&mmdc->mdref, + CONFIG_SYS_MMDC_CORE_REFRESH_CTL, + START_REFRESH); + + /* disable CON_REQ */ + out_be32(&mmdc->mdscr, DISABLE_CFG_REQ); +} + +int dram_init(void) +{ + mmdc_init(); + + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + + return 0; +} + +int board_early_init_f(void) +{ + fsl_lsch2_early_init_f(); + + return 0; +} + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + u8 mux_sdhc_cd = 0x80; + + i2c_set_bus_num(0); + + i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1); + return 0; +} +#endif + +int board_init(void) +{ + struct ccsr_cci400 *cci = (struct ccsr_cci400 *) + CONFIG_SYS_CCI400_ADDR; + + /* Set CCI-400 control override register to enable barrier + * transaction */ + out_le32(&cci->ctrl_ord, + CCI400_CTRLORD_EN_BARRIER); + +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); +#endif + +#ifdef CONFIG_ENV_IS_NOWHERE + gd->env_addr = (ulong)&default_environment[0]; +#endif + return 0; +} + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} + +#ifdef CONFIG_OF_BOARD_SETUP +int ft_board_setup(void *blob, bd_t *bd) +{ + arch_fixup_fdt(blob); + + ft_cpu_setup(blob, bd); + + return 0; +} +#endif diff --git a/board/freescale/ls1012aqds/ls1012aqds_qixis.h b/board/freescale/ls1012aqds/ls1012aqds_qixis.h new file mode 100644 index 0000000000..584f604aa8 --- /dev/null +++ b/board/freescale/ls1012aqds/ls1012aqds_qixis.h @@ -0,0 +1,35 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LS1043AQDS_QIXIS_H__ +#define __LS1043AQDS_QIXIS_H__ + +/* Definitions of QIXIS Registers for LS1043AQDS */ + +/* BRDCFG4[4:7] select EC1 and EC2 as a pair */ +#define BRDCFG4_EMISEL_MASK 0xe0 +#define BRDCFG4_EMISEL_SHIFT 5 + +/* SYSCLK */ +#define QIXIS_SYSCLK_66 0x0 +#define QIXIS_SYSCLK_83 0x1 +#define QIXIS_SYSCLK_100 0x2 +#define QIXIS_SYSCLK_125 0x3 +#define QIXIS_SYSCLK_133 0x4 + +/* DDRCLK */ +#define QIXIS_DDRCLK_66 0x0 +#define QIXIS_DDRCLK_100 0x1 +#define QIXIS_DDRCLK_125 0x2 +#define QIXIS_DDRCLK_133 0x3 + +/* BRDCFG2 - SD clock*/ +#define QIXIS_SDCLK1_100 0x0 +#define QIXIS_SDCLK1_125 0x1 +#define QIXIS_SDCLK1_165 0x2 +#define QIXIS_SDCLK1_100_SP 0x3 + +#endif diff --git a/board/freescale/ls1012ardb/Kconfig b/board/freescale/ls1012ardb/Kconfig new file mode 100644 index 0000000000..3f67c2841f --- /dev/null +++ b/board/freescale/ls1012ardb/Kconfig @@ -0,0 +1,15 @@ +if TARGET_LS1012ARDB + +config SYS_BOARD + default "ls1012ardb" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "fsl-layerscape" + +config SYS_CONFIG_NAME + default "ls1012ardb" + +endif diff --git a/board/freescale/ls1012ardb/MAINTAINERS b/board/freescale/ls1012ardb/MAINTAINERS new file mode 100644 index 0000000000..79a2a7dd24 --- /dev/null +++ b/board/freescale/ls1012ardb/MAINTAINERS @@ -0,0 +1,6 @@ +LS1012ARDB BOARD +M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> +S: Maintained +F: board/freescale/ls1012ardb/ +F: include/configs/ls1012ardb.h +F: configs/ls1012ardb_qspi_defconfig diff --git a/board/freescale/ls1012ardb/Makefile b/board/freescale/ls1012ardb/Makefile new file mode 100644 index 0000000000..05fa9d9c5b --- /dev/null +++ b/board/freescale/ls1012ardb/Makefile @@ -0,0 +1,7 @@ +# +# Copyright 2016 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ls1012ardb.o diff --git a/board/freescale/ls1012ardb/README b/board/freescale/ls1012ardb/README new file mode 100644 index 0000000000..453b432915 --- /dev/null +++ b/board/freescale/ls1012ardb/README @@ -0,0 +1,54 @@ +Overview +-------- +QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance +development platform, with a complete debugging environment. +The LS1012ARDB board supports the QorIQ LS1012A processor and is +optimized to support the high-bandwidth DDR3L memory and +a full complement of high-speed SerDes ports. + +LS1012A SoC Overview +-------------------- +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A +SoC overview. + +LS1012ARDB board Overview +----------------------- + - SERDES Connections, 4 lanes supporting: + - PCI Express - 3.0 + - SGMII, SGMII 2.5 + - SATA 3.0 + - DDR Controller + - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s + -QSPI: A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select + signals to + - QSPI NOR flash memory (2 virtual banks) + - the QSPI emulator.s + - USB 3.0 + - one high-speed USB 2.0/3.0 port. + - Two enhanced secure digital host controllers: + - SDHC1 controller can be connected to onboard SDHC connector + - SDHC2 controller: Three dual 1:4 mux/demux devices, + 74CBTLV3253DS (U30, U31, U33) drive the SDHC2 signals to eMMC, + SDIO WiFi, SPI, and Ardiuno shield + - 2 I2C controllers + - One SATA onboard connectors + - UART + - The LS1012A processor consists of two UART controllers, + out of which only UART1 is used on RDB. + - ARM JTAG support + +Booting Options +--------------- +a) QSPI Flash Emu Boot +b) QSPI Flash 1 +c) QSPI Flash 2 + +QSPI flash map +-------------- +Images | Size |QSPI Flash Address +------------------------------------------ +RCW + PBI | 1MB | 0x4000_0000 +U-boot | 1MB | 0x4010_0000 +U-boot Env | 1MB | 0x4020_0000 +PPA FIT image | 2MB | 0x4050_0000 +Linux ITB | ~53MB | 0x40A0_0000 diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c new file mode 100644 index 0000000000..f69768d24e --- /dev/null +++ b/board/freescale/ls1012ardb/ls1012ardb.c @@ -0,0 +1,224 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/fsl_serdes.h> +#include <asm/arch/soc.h> +#include <hwconfig.h> +#include <ahci.h> +#include <mmc.h> +#include <scsi.h> +#include <fsl_csu.h> +#include <fsl_esdhc.h> +#include <environment.h> +#include <fsl_mmdc.h> +#include <netdev.h> + +DECLARE_GLOBAL_DATA_PTR; + +static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits) +{ + int timeout = 1000; + + out_be32(ptr, value); + + while (in_be32(ptr) & bits) { + udelay(100); + timeout--; + } + if (timeout <= 0) + puts("Error: wait for clear timeout.\n"); +} + +int checkboard(void) +{ + u8 in1; + + puts("Board: LS1012ARDB "); + + /* Initialize i2c early for Serial flash bank information */ + i2c_set_bus_num(0); + + if (i2c_read(I2C_MUX_IO1_ADDR, 1, 1, &in1, 1) < 0) { + printf("Error reading i2c boot information!\n"); + return 0; /* Don't want to hang() on this error */ + } + + puts("Version"); + if ((in1 & (~__SW_REV_MASK)) == __SW_REV_A) + puts(": RevA"); + else if ((in1 & (~__SW_REV_MASK)) == __SW_REV_B) + puts(": RevB"); + else + puts(": unknown"); + + printf(", boot from QSPI"); + if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_EMU) + puts(": emu\n"); + else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK1) + puts(": bank1\n"); + else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK2) + puts(": bank2\n"); + else + puts("unknown\n"); + + return 0; +} + +void mmdc_init(void) +{ + struct mmdc_p_regs *mmdc = + (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR; + + out_be32(&mmdc->mdscr, CONFIGURATION_REQ); + + /* configure timing parms */ + out_be32(&mmdc->mdotc, CONFIG_SYS_MMDC_CORE_ODT_TIMING); + out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0); + out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1); + out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2); + + /* other parms */ + out_be32(&mmdc->mdmisc, CONFIG_SYS_MMDC_CORE_MISC); + out_be32(&mmdc->mpmur0, CONFIG_SYS_MMDC_PHY_MEASURE_UNIT); + out_be32(&mmdc->mdrwd, CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY); + out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL); + + /* out of reset delays */ + out_be32(&mmdc->mdor, CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY); + + /* physical parms */ + out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1); + out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION); + + /* Enable MMDC */ + out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2); + + /* dram init sequence: update MRs */ + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2)); + out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | + CMD_BANK_ADDR_3)); + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1)); + out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) | + CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0)); + + /* dram init sequence: ZQCL */ + out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | + CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0)); + set_wait_for_bits_clear(&mmdc->mpzqhwctrl, + CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL, + FORCE_ZQ_AUTO_CALIBRATION); + + /* Calibrations now: wr lvl */ + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) | + CONFIGURATION_REQ | CMD_LOAD_MODE_REG | + CMD_BANK_ADDR_1)); + out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL)); + set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN); + + mdelay(1); + + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1)); + out_be32(&mmdc->mdscr, CONFIGURATION_REQ); + + mdelay(1); + + /* Calibrations now: Read DQS gating calibration */ + out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | + CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0)); + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3)); + out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN); + out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG); + set_wait_for_bits_clear(&mmdc->mpdgctrl0, + AUTO_RD_DQS_GATING_CALIBRATION_EN, + AUTO_RD_DQS_GATING_CALIBRATION_EN); + + out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | + CMD_BANK_ADDR_3)); + + /* Calibrations now: Read calibration */ + out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ | + CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0)); + out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ | + CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3)); + out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN); + set_wait_for_bits_clear(&mmdc->mprddlhwctl, + AUTO_RD_CALIBRATION_EN, + AUTO_RD_CALIBRATION_EN); + + out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG | + CMD_BANK_ADDR_3)); + + /* PD, SR */ + out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL); + out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT); + + /* refresh scheme */ + set_wait_for_bits_clear(&mmdc->mdref, + CONFIG_SYS_MMDC_CORE_REFRESH_CTL, + START_REFRESH); + + /* disable CON_REQ */ + out_be32(&mmdc->mdscr, DISABLE_CFG_REQ); +} + +int dram_init(void) +{ + mmdc_init(); + + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} + +int board_early_init_f(void) +{ + fsl_lsch2_early_init_f(); + + return 0; +} + +int board_init(void) +{ + struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; + /* + * Set CCI-400 control override register to enable barrier + * transaction + */ + out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); + +#ifdef CONFIG_ENV_IS_NOWHERE + gd->env_addr = (ulong)&default_environment[0]; +#endif + +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); +#endif + + return 0; +} + +int ft_board_setup(void *blob, bd_t *bd) +{ + arch_fixup_fdt(blob); + + ft_cpu_setup(blob, bd); + + return 0; +} diff --git a/board/freescale/ls1021aqds/ddr.h b/board/freescale/ls1021aqds/ddr.h index f819c99dba..b39b561dc1 100644 --- a/board/freescale/ls1021aqds/ddr.h +++ b/board/freescale/ls1021aqds/ddr.h @@ -31,21 +31,21 @@ static const struct board_specific_parameters udimm0[] = { * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | */ #ifdef CONFIG_SYS_FSL_DDR4 - {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, - {2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,}, - {1, 1666, 0, 4, 8, 0x090A0B0B, 0x0C0D0E0C,}, - {1, 1900, 0, 4, 9, 0x0A0B0C0B, 0x0D0E0F0D,}, - {1, 2200, 0, 4, 10, 0x0B0C0D0C, 0x0E0F110E,}, + {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, + {2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,}, + {1, 1666, 0, 8, 8, 0x090A0B0B, 0x0C0D0E0C,}, + {1, 1900, 0, 8, 9, 0x0A0B0C0B, 0x0D0E0F0D,}, + {1, 2200, 0, 8, 10, 0x0B0C0D0C, 0x0E0F110E,}, #elif defined(CONFIG_SYS_FSL_DDR3) - {1, 833, 1, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, - {1, 1350, 1, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, - {1, 833, 2, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, - {1, 1350, 2, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, - {2, 833, 4, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, - {2, 1350, 4, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, - {2, 1350, 0, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, - {2, 1666, 4, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, - {2, 1666, 0, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, + {1, 833, 1, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, + {1, 1350, 1, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {1, 833, 2, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, + {1, 1350, 2, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {2, 833, 4, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, + {2, 1350, 4, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {2, 1350, 0, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {2, 1666, 4, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, + {2, 1666, 0, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, #else #error DDR type not defined #endif diff --git a/board/freescale/ls1043aqds/README b/board/freescale/ls1043aqds/README index a6fd7a35f5..913537d451 100644 --- a/board/freescale/ls1043aqds/README +++ b/board/freescale/ls1043aqds/README @@ -8,41 +8,8 @@ debugging environment. LS1043A SoC Overview -------------------- -The LS1043A integrated multicore processor combines four ARM Cortex-A53 -processor cores with datapath acceleration optimized for L2/3 packet -processing, single pass security offload and robust traffic management -and quality of service. - -The LS1043A SoC includes the following function and features: - - Four 64-bit ARM Cortex-A53 CPUs - - 1 MB unified L2 Cache - - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving - support - - Data Path Acceleration Architecture (DPAA) incorporating acceleration the - the following functions: - - Packet parsing, classification, and distribution (FMan) - - Queue management for scheduling, packet sequencing, and congestion - management (QMan) - - Hardware buffer management for buffer allocation and de-allocation (BMan) - - Cryptography acceleration (SEC) - - Ethernet interfaces by FMan - - Up to 1 x XFI supporting 10G interface - - Up to 1 x QSGMII - - Up to 4 x SGMII supporting 1000Mbps - - Up to 2 x SGMII supporting 2500Mbps - - Up to 2 x RGMII supporting 1000Mbps - - High-speed peripheral interfaces - - Three PCIe 2.0 controllers, one supporting x4 operation - - One serial ATA (SATA 3.0) controllers - - Additional peripheral interfaces - - Three high-speed USB 3.0 controllers with integrated PHY - - Enhanced secure digital host controller (eSDXC/eMMC) - - Quad Serial Peripheral Interface (QSPI) Controller - - Serial peripheral interface (SPI) controller - - Four I2C controllers - - Two DUARTs - - Integrated flash controller supporting NAND and NOR flash - - QorIQ platform's trust architecture 2.1 +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A +SoC overview. LS1043AQDS board Overview ----------------------- diff --git a/board/freescale/ls1043aqds/ddr.h b/board/freescale/ls1043aqds/ddr.h index d3f40822b7..ad709ba216 100644 --- a/board/freescale/ls1043aqds/ddr.h +++ b/board/freescale/ls1043aqds/ddr.h @@ -34,21 +34,21 @@ static const struct board_specific_parameters udimm0[] = { * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | */ #ifdef CONFIG_SYS_FSL_DDR4 - {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, - {2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,}, - {1, 1666, 0, 4, 6, 0x0708090B, 0x0C0D0E0A,}, - {1, 1900, 0, 4, 9, 0x0A0B0C0B, 0x0D0E0F0D,}, - {1, 2200, 0, 4, 10, 0x0B0C0D0C, 0x0E0F110E,}, + {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, + {2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,}, + {1, 1666, 0, 8, 6, 0x0708090B, 0x0C0D0E0A,}, + {1, 1900, 0, 8, 9, 0x0A0B0C0B, 0x0D0E0F0D,}, + {1, 2200, 0, 8, 10, 0x0B0C0D0C, 0x0E0F110E,}, #elif defined(CONFIG_SYS_FSL_DDR3) - {1, 833, 1, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, - {1, 1350, 1, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, - {1, 833, 2, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, - {1, 1350, 2, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, - {2, 833, 4, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, - {2, 1350, 4, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, - {2, 1350, 0, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, - {2, 1666, 4, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, - {2, 1666, 0, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, + {1, 833, 1, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, + {1, 1350, 1, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {1, 833, 2, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, + {1, 1350, 2, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {2, 833, 4, 12, 8, 0x06060607, 0x08080807, 0x1f, 2, 0}, + {2, 1350, 4, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {2, 1350, 0, 12, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0}, + {2, 1666, 4, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, + {2, 1666, 0, 8, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0}, #else #error DDR type not defined #endif diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index ca393e862d..7e47ef0d82 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -238,8 +238,8 @@ int board_early_init_f(void) out_be32(&scfg->rcwpmuxcr0, 0x3333); out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1); usb_pwrfault = - (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB3_SHIFT) | - (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB2_SHIFT) | + (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) | + (SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) | (SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT); out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); #endif diff --git a/board/freescale/ls1043ardb/README b/board/freescale/ls1043ardb/README index 0556e73b3a..709ddbbef3 100644 --- a/board/freescale/ls1043ardb/README +++ b/board/freescale/ls1043ardb/README @@ -8,41 +8,8 @@ debugging environment. The LS1043A RDB is lead-free and RoHS-compliant. LS1043A SoC Overview -------------------- -The LS1043A integrated multicore processor combines four ARM Cortex-A53 -processor cores with datapath acceleration optimized for L2/3 packet -processing, single pass security offload and robust traffic management -and quality of service. - -The LS1043A SoC includes the following function and features: - - Four 64-bit ARM Cortex-A53 CPUs - - 1 MB unified L2 Cache - - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving - support - - Data Path Acceleration Architecture (DPAA) incorporating acceleration the - the following functions: - - Packet parsing, classification, and distribution (FMan) - - Queue management for scheduling, packet sequencing, and congestion - management (QMan) - - Hardware buffer management for buffer allocation and de-allocation (BMan) - - Cryptography acceleration (SEC) - - Ethernet interfaces by FMan - - Up to 1 x XFI supporting 10G interface - - Up to 1 x QSGMII - - Up to 4 x SGMII supporting 1000Mbps - - Up to 2 x SGMII supporting 2500Mbps - - Up to 2 x RGMII supporting 1000Mbps - - High-speed peripheral interfaces - - Three PCIe 2.0 controllers, one supporting x4 operation - - One serial ATA (SATA 3.0) controllers - - Additional peripheral interfaces - - Three high-speed USB 3.0 controllers with integrated PHY - - Enhanced secure digital host controller (eSDXC/eMMC) - - Quad Serial Peripheral Interface (QSPI) Controller - - Serial peripheral interface (SPI) controller - - Four I2C controllers - - Two DUARTs - - Integrated flash controller supporting NAND and NOR flash - - QorIQ platform's trust architecture 2.1 +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A +SoC overview. LS1043ARDB board Overview ----------------------- diff --git a/board/freescale/ls1043ardb/ddr.h b/board/freescale/ls1043ardb/ddr.h index 8ca166b3ac..a77ddf3d24 100644 --- a/board/freescale/ls1043ardb/ddr.h +++ b/board/freescale/ls1043ardb/ddr.h @@ -34,9 +34,9 @@ static const struct board_specific_parameters udimm0[] = { * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | */ #ifdef CONFIG_SYS_FSL_DDR4 - {1, 1666, 0, 6, 7, 0x07090800, 0x00000000,}, - {1, 1900, 0, 6, 7, 0x07090800, 0x00000000,}, - {1, 2200, 0, 6, 7, 0x07090800, 0x00000000,}, + {1, 1666, 0, 12, 7, 0x07090800, 0x00000000,}, + {1, 1900, 0, 12, 7, 0x07090800, 0x00000000,}, + {1, 2200, 0, 12, 7, 0x07090800, 0x00000000,}, #endif {} }; diff --git a/board/freescale/ls2080aqds/README b/board/freescale/ls2080aqds/README index 6ddad92f2c..5c98866712 100644 --- a/board/freescale/ls2080aqds/README +++ b/board/freescale/ls2080aqds/README @@ -7,48 +7,9 @@ SW development platform for the Freescale LS2080A processor series, with a complete debugging environment. LS2080A SoC Overview ------------------- -The LS2080A integrated multicore processor combines eight ARM Cortex-A57 -processor cores with high-performance data path acceleration logic and network -and peripheral bus interfaces required for networking, telecom/datacom, -wireless infrastructure, and mil/aerospace applications. - -The LS2080A SoC includes the following function and features: - - - Eight 64-bit ARM Cortex-A57 CPUs - - 1 MB platform cache with ECC - - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support - - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by - the AIOP - - Data path acceleration architecture (DPAA2) incorporating acceleration for - the following functions: - - Packet parsing, classification, and distribution (WRIOP) - - Queue and Hardware buffer management for scheduling, packet sequencing, and - congestion management, buffer allocation and de-allocation (QBMan) - - Cryptography acceleration (SEC) at up to 10 Gbps - - RegEx pattern matching acceleration (PME) at up to 10 Gbps - - Decompression/compression acceleration (DCE) at up to 20 Gbps - - Accelerated I/O processing (AIOP) at up to 20 Gbps - - QDMA engine - - 16 SerDes lanes at up to 10.3125 GHz - - Ethernet interfaces - - Up to eight 10 Gbps Ethernet MACs - - Up to eight 1 / 2.5 Gbps Ethernet MACs - - High-speed peripheral interfaces - - Four PCIe 3.0 controllers, one supporting SR-IOV - - Additional peripheral interfaces - - Two serial ATA (SATA 3.0) controllers - - Two high-speed USB 3.0 controllers with integrated PHY - - Enhanced secure digital host controller (eSDXC/eMMC) - - Serial peripheral interface (SPI) controller - - Quad Serial Peripheral Interface (QSPI) Controller - - Four I2C controllers - - Two DUARTs - - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash - - Support for hardware virtualization and partitioning enforcement - - QorIQ platform's trust architecture 3.0 - - Service processor (SP) provides pre-boot initialization and secure-boot - capabilities +-------------------- +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A +SoC overview. LS2080AQDS board Overview ----------------------- diff --git a/board/freescale/ls2080aqds/ddr.h b/board/freescale/ls2080aqds/ddr.h index b76ea61ba0..eba62c33b2 100644 --- a/board/freescale/ls2080aqds/ddr.h +++ b/board/freescale/ls2080aqds/ddr.h @@ -28,10 +28,10 @@ static const struct board_specific_parameters udimm0[] = { * num| hi| rank| clk| wrlvl | wrlvl | wrlvl * ranks| mhz| GB |adjst| start | ctl2 | ctl3 */ - {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,}, - {2, 1666, 0, 4, 7, 0x08090A0C, 0x0D0F100B,}, - {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,}, - {2, 2300, 0, 4, 8, 0x090A0C0F, 0x1012130C,}, + {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, + {2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,}, + {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,}, + {2, 2300, 0, 8, 8, 0x090A0C0F, 0x1012130C,}, {} }; @@ -42,10 +42,10 @@ static const struct board_specific_parameters udimm2[] = { * num| hi| rank| clk| wrlvl | wrlvl | wrlvl * ranks| mhz| GB |adjst| start | ctl2 | ctl3 */ - {2, 1350, 0, 4, 0xd, 0x0C0A0A00, 0x00000009,}, - {2, 1666, 0, 4, 0xd, 0x0C0A0A00, 0x00000009,}, - {2, 1900, 0, 4, 0xe, 0x0D0C0B00, 0x0000000A,}, - {2, 2200, 0, 4, 0xe, 0x0D0C0B00, 0x0000000A,}, + {2, 1350, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,}, + {2, 1666, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,}, + {2, 1900, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,}, + {2, 2200, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,}, {} }; @@ -55,10 +55,10 @@ static const struct board_specific_parameters rdimm0[] = { * num| hi| rank| clk| wrlvl | wrlvl | wrlvl * ranks| mhz| GB |adjst| start | ctl2 | ctl3 */ - {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,}, - {2, 1666, 0, 4, 7, 0x08090A0C, 0x0D0F100B,}, - {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,}, - {2, 2200, 0, 4, 8, 0x090A0C0F, 0x1012130C,}, + {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, + {2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,}, + {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,}, + {2, 2200, 0, 8, 8, 0x090A0C0F, 0x1012130C,}, {} }; @@ -69,10 +69,10 @@ static const struct board_specific_parameters rdimm2[] = { * num| hi| rank| clk| wrlvl | wrlvl | wrlvl * ranks| mhz| GB |adjst| start | ctl2 | ctl3 */ - {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,}, - {2, 1666, 0, 4, 7, 0x0B0A090C, 0x0D0F100B,}, - {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,}, - {2, 2200, 0, 4, 8, 0x090A0C0F, 0x1012130C,}, + {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, + {2, 1666, 0, 8, 7, 0x0B0A090C, 0x0D0F100B,}, + {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,}, + {2, 2200, 0, 8, 8, 0x090A0C0F, 0x1012130C,}, {} }; diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c index b3bd40afb7..897793d85b 100644 --- a/board/freescale/ls2080aqds/ls2080aqds.c +++ b/board/freescale/ls2080aqds/ls2080aqds.c @@ -282,7 +282,9 @@ void fdt_fixup_board_enet(void *fdt) #ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, bd_t *bd) { +#ifdef CONFIG_FSL_MC_ENET int err; +#endif u64 base[CONFIG_NR_DRAM_BANKS]; u64 size[CONFIG_NR_DRAM_BANKS]; diff --git a/board/freescale/ls2080ardb/README b/board/freescale/ls2080ardb/README index 6708ca9cc7..b1613ba680 100644 --- a/board/freescale/ls2080ardb/README +++ b/board/freescale/ls2080ardb/README @@ -5,48 +5,9 @@ evaluation, and development platform that supports the QorIQ LS2080A Layerscape Architecture processor. LS2080A SoC Overview ------------------- -The LS2080A integrated multicore processor combines eight ARM Cortex-A57 -processor cores with high-performance data path acceleration logic and network -and peripheral bus interfaces required for networking, telecom/datacom, -wireless infrastructure, and mil/aerospace applications. - -The LS2080A SoC includes the following function and features: - - - Eight 64-bit ARM Cortex-A57 CPUs - - 1 MB platform cache with ECC - - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support - - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by - the AIOP - - Data path acceleration architecture (DPAA2) incorporating acceleration for - the following functions: - - Packet parsing, classification, and distribution (WRIOP) - - Queue and Hardware buffer management for scheduling, packet sequencing, and - congestion management, buffer allocation and de-allocation (QBMan) - - Cryptography acceleration (SEC) at up to 10 Gbps - - RegEx pattern matching acceleration (PME) at up to 10 Gbps - - Decompression/compression acceleration (DCE) at up to 20 Gbps - - Accelerated I/O processing (AIOP) at up to 20 Gbps - - QDMA engine - - 16 SerDes lanes at up to 10.3125 GHz - - Ethernet interfaces - - Up to eight 10 Gbps Ethernet MACs - - Up to eight 1 / 2.5 Gbps Ethernet MACs - - High-speed peripheral interfaces - - Four PCIe 3.0 controllers, one supporting SR-IOV - - Additional peripheral interfaces - - Two serial ATA (SATA 3.0) controllers - - Two high-speed USB 3.0 controllers with integrated PHY - - Enhanced secure digital host controller (eSDXC/eMMC) - - Serial peripheral interface (SPI) controller - - Quad Serial Peripheral Interface (QSPI) Controller - - Four I2C controllers - - Two DUARTs - - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash - - Support for hardware virtualization and partitioning enforcement - - QorIQ platform's trust architecture 3.0 - - Service processor (SP) provides pre-boot initialization and secure-boot - capabilities +-------------------- +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A +SoC overview. LS2080ARDB board Overview ----------------------- diff --git a/board/freescale/ls2080ardb/ddr.h b/board/freescale/ls2080ardb/ddr.h index b3c6306b8f..8d5a49061c 100644 --- a/board/freescale/ls2080ardb/ddr.h +++ b/board/freescale/ls2080ardb/ddr.h @@ -28,10 +28,10 @@ static const struct board_specific_parameters udimm0[] = { * num| hi| rank| clk| wrlvl | wrlvl | wrlvl * ranks| mhz| GB |adjst| start | ctl2 | ctl3 */ - {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,}, - {2, 1666, 0, 5, 9, 0x090A0B0E, 0x0F11110C,}, - {2, 1900, 0, 6, 0xA, 0x0B0C0E11, 0x1214140F,}, - {2, 2300, 0, 6, 0xB, 0x0C0D0F12, 0x14161610,}, + {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, + {2, 1666, 0, 10, 9, 0x090A0B0E, 0x0F11110C,}, + {2, 1900, 0, 12, 0xA, 0x0B0C0E11, 0x1214140F,}, + {2, 2300, 0, 12, 0xB, 0x0C0D0F12, 0x14161610,}, {} }; @@ -42,10 +42,10 @@ static const struct board_specific_parameters udimm2[] = { * num| hi| rank| clk| wrlvl | wrlvl | wrlvl * ranks| mhz| GB |adjst| start | ctl2 | ctl3 */ - {2, 1350, 0, 4, 0xd, 0x0C0A0A00, 0x00000009,}, - {2, 1666, 0, 4, 0xd, 0x0C0A0A00, 0x00000009,}, - {2, 1900, 0, 4, 0xe, 0x0D0C0B00, 0x0000000A,}, - {2, 2200, 0, 4, 0xe, 0x0D0C0B00, 0x0000000A,}, + {2, 1350, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,}, + {2, 1666, 0, 8, 0xd, 0x0C0A0A00, 0x00000009,}, + {2, 1900, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,}, + {2, 2200, 0, 8, 0xe, 0x0D0C0B00, 0x0000000A,}, {} }; @@ -55,10 +55,10 @@ static const struct board_specific_parameters rdimm0[] = { * num| hi| rank| clk| wrlvl | wrlvl | wrlvl * ranks| mhz| GB |adjst| start | ctl2 | ctl3 */ - {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,}, - {2, 1666, 0, 4, 7, 0x08090A0C, 0x0D0F100B,}, - {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,}, - {2, 2200, 0, 4, 8, 0x090A0C0F, 0x1012130C,}, + {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, + {2, 1666, 0, 8, 7, 0x08090A0C, 0x0D0F100B,}, + {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,}, + {2, 2200, 0, 8, 8, 0x090A0C0F, 0x1012130C,}, {} }; @@ -69,10 +69,10 @@ static const struct board_specific_parameters rdimm2[] = { * num| hi| rank| clk| wrlvl | wrlvl | wrlvl * ranks| mhz| GB |adjst| start | ctl2 | ctl3 */ - {2, 1350, 0, 4, 6, 0x0708090B, 0x0C0D0E09,}, - {2, 1666, 0, 4, 7, 0x0B0A090C, 0x0D0F100B,}, - {2, 1900, 0, 4, 7, 0x09090B0D, 0x0E10120B,}, - {2, 2200, 0, 4, 8, 0x090A0C0F, 0x1012130C,}, + {2, 1350, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, + {2, 1666, 0, 8, 7, 0x0B0A090C, 0x0D0F100B,}, + {2, 1900, 0, 8, 7, 0x09090B0D, 0x0E10120B,}, + {2, 2200, 0, 8, 8, 0x090A0C0F, 0x1012130C,}, {} }; diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index fb39af6445..52e5e3f516 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -156,7 +156,9 @@ int board_init(void) { char *env_hwconfig; u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; +#ifdef CONFIG_FSL_MC_ENET u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE; +#endif u32 val; init_final_memctl_regs(); @@ -178,8 +180,10 @@ int board_init(void) QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN); +#ifdef CONFIG_FSL_MC_ENET /* invert AQR405 IRQ pins polarity */ out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK); +#endif return 0; } @@ -261,7 +265,9 @@ void fdt_fixup_board_enet(void *fdt) #ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, bd_t *bd) { +#ifdef CONFIG_FSL_MC_ENET int err; +#endif u64 base[CONFIG_NR_DRAM_BANKS]; u64 size[CONFIG_NR_DRAM_BANKS]; diff --git a/board/freescale/m5329evb/nand.c b/board/freescale/m5329evb/nand.c index 8d88bc03c0..88496812bf 100644 --- a/board/freescale/m5329evb/nand.c +++ b/board/freescale/m5329evb/nand.c @@ -24,7 +24,7 @@ DECLARE_GLOBAL_DATA_PTR; static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) { - struct nand_chip *this = mtdinfo->priv; + struct nand_chip *this = mtd_to_nand(mtdinfo); volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR; if (ctrl & NAND_CTRL_CHANGE) { diff --git a/board/freescale/m5373evb/nand.c b/board/freescale/m5373evb/nand.c index 92cef2a97d..a96a59991f 100644 --- a/board/freescale/m5373evb/nand.c +++ b/board/freescale/m5373evb/nand.c @@ -24,7 +24,7 @@ DECLARE_GLOBAL_DATA_PTR; static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) { - struct nand_chip *this = mtdinfo->priv; + struct nand_chip *this = mtd_to_nand(mtdinfo); volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR; if (ctrl & NAND_CTRL_CHANGE) { diff --git a/board/freescale/p1010rdb/Makefile b/board/freescale/p1010rdb/Makefile index 660d1bbc2a..86eb6946dd 100644 --- a/board/freescale/p1010rdb/Makefile +++ b/board/freescale/p1010rdb/Makefile @@ -13,18 +13,14 @@ endif endif ifdef MINIMAL - -obj-y += spl_minimal.o tlb.o law.o - +obj-y += spl_minimal.o else - ifdef CONFIG_SPL_BUILD -obj-y += spl.o +obj-y += spl.o endif - obj-y += p1010rdb.o obj-y += ddr.o +endif + obj-y += law.o obj-y += tlb.o - -endif diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c index eb8e567554..f8584084ce 100644 --- a/board/freescale/p1010rdb/spl.c +++ b/board/freescale/p1010rdb/spl.c @@ -72,6 +72,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) get_clocks(); mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, CONFIG_SPL_RELOC_MALLOC_SIZE); + gd->flags |= GD_FLG_FULL_MALLOC_INIT; #ifndef CONFIG_SPL_NAND_BOOT env_init(); diff --git a/board/freescale/p1022ds/Makefile b/board/freescale/p1022ds/Makefile index a5821277ef..9793853463 100644 --- a/board/freescale/p1022ds/Makefile +++ b/board/freescale/p1022ds/Makefile @@ -13,17 +13,15 @@ endif endif ifdef MINIMAL - -obj-y += spl_minimal.o tlb.o law.o - +obj-y += spl_minimal.o else ifdef CONFIG_SPL_BUILD -obj-y += spl.o +obj-y += spl.o endif obj-y += p1022ds.o obj-y += ddr.o -obj-y += law.o -obj-y += tlb.o - obj-$(CONFIG_FSL_DIU_FB) += diu.o endif + +obj-y += law.o +obj-y += tlb.o diff --git a/board/freescale/p1022ds/spl.c b/board/freescale/p1022ds/spl.c index 89ef95aab8..04db767f98 100644 --- a/board/freescale/p1022ds/spl.c +++ b/board/freescale/p1022ds/spl.c @@ -86,6 +86,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) get_clocks(); mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, CONFIG_SPL_RELOC_MALLOC_SIZE); + gd->flags |= GD_FLG_FULL_MALLOC_INIT; #ifndef CONFIG_SPL_NAND_BOOT env_init(); #endif diff --git a/board/freescale/p1_p2_rdb_pc/Makefile b/board/freescale/p1_p2_rdb_pc/Makefile index a2a1f92ce8..045d4093ae 100644 --- a/board/freescale/p1_p2_rdb_pc/Makefile +++ b/board/freescale/p1_p2_rdb_pc/Makefile @@ -13,17 +13,14 @@ endif endif ifdef MINIMAL - -obj-y += spl_minimal.o tlb.o law.o - +obj-y += spl_minimal.o else ifdef CONFIG_SPL_BUILD -obj-y += spl.o +obj-y += spl.o endif - -obj-y += p1_p2_rdb_pc.o -obj-y += ddr.o -obj-y += law.o -obj-y += tlb.o - +obj-y += p1_p2_rdb_pc.o +obj-y += ddr.o endif + +obj-y += law.o +obj-y += tlb.o diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c index 0142746c84..76a3cf47cc 100644 --- a/board/freescale/p1_p2_rdb_pc/spl.c +++ b/board/freescale/p1_p2_rdb_pc/spl.c @@ -83,6 +83,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) get_clocks(); mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, CONFIG_SPL_RELOC_MALLOC_SIZE); + gd->flags |= GD_FLG_FULL_MALLOC_INIT; #ifndef CONFIG_SPL_NAND_BOOT env_init(); diff --git a/board/freescale/p2041rdb/Makefile b/board/freescale/p2041rdb/Makefile index c74f4c62f8..a335ec65fa 100644 --- a/board/freescale/p2041rdb/Makefile +++ b/board/freescale/p2041rdb/Makefile @@ -7,6 +7,6 @@ # obj-y += p2041rdb.o -obj-y += cpld.o +obj-y += cpld.o obj-y += ddr.o obj-y += eth.o diff --git a/board/freescale/t102xqds/Makefile b/board/freescale/t102xqds/Makefile index d94f2307d9..afbc9146ed 100644 --- a/board/freescale/t102xqds/Makefile +++ b/board/freescale/t102xqds/Makefile @@ -5,7 +5,7 @@ # ifdef CONFIG_SPL_BUILD -obj-y += spl.o +obj-y += spl.o else obj-y += t102xqds.o obj-y += eth_t102xqds.o diff --git a/board/freescale/t102xqds/ddr.c b/board/freescale/t102xqds/ddr.c index 2d4d10f351..c26f3503b9 100644 --- a/board/freescale/t102xqds/ddr.c +++ b/board/freescale/t102xqds/ddr.c @@ -35,18 +35,18 @@ static const struct board_specific_parameters udimm0[] = { * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | */ #if defined(CONFIG_SYS_FSL_DDR4) - {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, - {2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,}, - {1, 1666, 0, 4, 6, 0x0708090B, 0x0C0D0E09,}, - {1, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,}, - {1, 2200, 0, 4, 7, 0x08090A0D, 0x0F0F100C,}, + {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, + {2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,}, + {1, 1666, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, + {1, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,}, + {1, 2200, 0, 8, 7, 0x08090A0D, 0x0F0F100C,}, #elif defined(CONFIG_SYS_FSL_DDR3) - {2, 833, 0, 4, 6, 0x06060607, 0x08080807,}, - {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,}, - {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, - {1, 833, 0, 4, 6, 0x06060607, 0x08080807,}, - {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,}, - {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, + {2, 833, 0, 8, 6, 0x06060607, 0x08080807,}, + {2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,}, + {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, + {1, 833, 0, 8, 6, 0x06060607, 0x08080807,}, + {1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,}, + {1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, #else #error DDR type not defined #endif @@ -172,14 +172,13 @@ phys_size_t initdram(int board_type) #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) puts("Initializing....using SPD\n"); - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; #else /* DDR has been initialised by first stage boot loader */ dram_size = fsl_ddr_sdram_size(); #endif + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) fsl_dp_resume(); diff --git a/board/freescale/t102xqds/spl.c b/board/freescale/t102xqds/spl.c index 073ff2dcde..d59d3431ec 100644 --- a/board/freescale/t102xqds/spl.c +++ b/board/freescale/t102xqds/spl.c @@ -120,6 +120,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) get_clocks(); mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, CONFIG_SPL_RELOC_MALLOC_SIZE); + gd->flags |= GD_FLG_FULL_MALLOC_INIT; #ifdef CONFIG_SPL_NAND_BOOT nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, diff --git a/board/freescale/t102xrdb/Makefile b/board/freescale/t102xrdb/Makefile index 052006610e..64528656ac 100644 --- a/board/freescale/t102xrdb/Makefile +++ b/board/freescale/t102xrdb/Makefile @@ -5,7 +5,7 @@ # ifdef CONFIG_SPL_BUILD -obj-y += spl.o +obj-y += spl.o else obj-y += t102xrdb.o obj-$(CONFIG_T1024RDB) += cpld.o diff --git a/board/freescale/t102xrdb/ddr.c b/board/freescale/t102xrdb/ddr.c index adf9fd5f78..edfbdbf3a8 100644 --- a/board/freescale/t102xrdb/ddr.c +++ b/board/freescale/t102xrdb/ddr.c @@ -34,12 +34,12 @@ static const struct board_specific_parameters udimm0[] = { * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | */ - {2, 833, 0, 4, 6, 0x06060607, 0x08080807,}, - {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,}, - {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, - {1, 833, 0, 4, 6, 0x06060607, 0x08080807,}, - {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,}, - {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, + {2, 833, 0, 8, 6, 0x06060607, 0x08080807,}, + {2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,}, + {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, + {1, 833, 0, 8, 6, 0x06060607, 0x08080807,}, + {1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,}, + {1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, {} }; @@ -234,12 +234,12 @@ phys_size_t initdram(int board_type) puts("Initializing....using SPD\n"); #endif dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; #else /* DDR has been initialised by first stage boot loader */ dram_size = fsl_ddr_sdram_size(); #endif + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) fsl_dp_resume(); diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c index da97c440c4..bd3cbbf11c 100644 --- a/board/freescale/t102xrdb/spl.c +++ b/board/freescale/t102xrdb/spl.c @@ -107,6 +107,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) get_clocks(); mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, CONFIG_SPL_RELOC_MALLOC_SIZE); + gd->flags |= GD_FLG_FULL_MALLOC_INIT; #ifdef CONFIG_SPL_NAND_BOOT nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, diff --git a/board/freescale/t1040qds/ddr.h b/board/freescale/t1040qds/ddr.h index a6e1673525..1e087460cb 100644 --- a/board/freescale/t1040qds/ddr.h +++ b/board/freescale/t1040qds/ddr.h @@ -29,18 +29,18 @@ static const struct board_specific_parameters udimm0[] = { * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | */ #ifdef CONFIG_SYS_FSL_DDR4 - {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, - {2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,}, - {1, 1666, 0, 4, 6, 0x0708090B, 0x0C0D0E09,}, - {1, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,}, - {1, 2200, 0, 4, 7, 0x08090A0D, 0x0F0F100C,}, + {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, + {2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,}, + {1, 1666, 0, 8, 6, 0x0708090B, 0x0C0D0E09,}, + {1, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,}, + {1, 2200, 0, 8, 7, 0x08090A0D, 0x0F0F100C,}, #elif defined(CONFIG_SYS_FSL_DDR3) - {2, 833, 0, 4, 6, 0x06060607, 0x08080807,}, - {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,}, - {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, - {1, 833, 0, 4, 6, 0x06060607, 0x08080807,}, - {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,}, - {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,}, + {2, 833, 0, 8, 6, 0x06060607, 0x08080807,}, + {2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,}, + {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, + {1, 833, 0, 8, 6, 0x06060607, 0x08080807,}, + {1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,}, + {1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,}, #else #error DDR type not defined #endif diff --git a/board/freescale/t104xrdb/ddr.c b/board/freescale/t104xrdb/ddr.c index cf79d2ddb2..22d6a5f617 100644 --- a/board/freescale/t104xrdb/ddr.c +++ b/board/freescale/t104xrdb/ddr.c @@ -124,15 +124,12 @@ phys_size_t initdram(int board_type) #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) puts("Initializing....using SPD\n"); - dram_size = fsl_ddr_sdram(); - - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - #else dram_size = fsl_ddr_sdram_size(); #endif + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) fsl_dp_resume(); diff --git a/board/freescale/t104xrdb/ddr.h b/board/freescale/t104xrdb/ddr.h index b9c02f7fe0..012991cf46 100644 --- a/board/freescale/t104xrdb/ddr.h +++ b/board/freescale/t104xrdb/ddr.h @@ -29,20 +29,20 @@ static const struct board_specific_parameters udimm0[] = { * ranks| mhz| GB |adjst| start | ctl2 */ #ifdef CONFIG_SYS_FSL_DDR4 - {2, 1600, 4, 4, 6, 0x07090A0c, 0x0e0f100a}, + {2, 1600, 4, 8, 6, 0x07090A0c, 0x0e0f100a}, #elif defined(CONFIG_SYS_FSL_DDR3) - {2, 833, 4, 4, 6, 0x06060607, 0x08080807}, - {2, 833, 0, 4, 6, 0x06060607, 0x08080807}, - {2, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09}, - {2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09}, - {2, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A}, - {2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A}, - {1, 833, 4, 4, 6, 0x06060607, 0x08080807}, - {1, 833, 0, 4, 6, 0x06060607, 0x08080807}, - {1, 1350, 4, 4, 7, 0x0708080A, 0x0A0B0C09}, - {1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09}, - {1, 1666, 4, 4, 7, 0x0808090B, 0x0C0D0E0A}, - {1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A}, + {2, 833, 4, 8, 6, 0x06060607, 0x08080807}, + {2, 833, 0, 8, 6, 0x06060607, 0x08080807}, + {2, 1350, 4, 8, 7, 0x0708080A, 0x0A0B0C09}, + {2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09}, + {2, 1666, 4, 8, 7, 0x0808090B, 0x0C0D0E0A}, + {2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A}, + {1, 833, 4, 8, 6, 0x06060607, 0x08080807}, + {1, 833, 0, 8, 6, 0x06060607, 0x08080807}, + {1, 1350, 4, 8, 7, 0x0708080A, 0x0A0B0C09}, + {1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09}, + {1, 1666, 4, 8, 7, 0x0808090B, 0x0C0D0E0A}, + {1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A}, #else #error DDR type not defined #endif diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c index 81f48c4c30..4b35af63f6 100644 --- a/board/freescale/t104xrdb/spl.c +++ b/board/freescale/t104xrdb/spl.c @@ -98,6 +98,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) get_clocks(); mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, CONFIG_SPL_RELOC_MALLOC_SIZE); + gd->flags |= GD_FLG_FULL_MALLOC_INIT; #ifdef CONFIG_SPL_MMC_BOOT mmc_initialize(bd); diff --git a/board/freescale/t208xqds/Makefile b/board/freescale/t208xqds/Makefile index 6cb72c9fd5..ef04a26463 100644 --- a/board/freescale/t208xqds/Makefile +++ b/board/freescale/t208xqds/Makefile @@ -7,10 +7,8 @@ ifdef CONFIG_SPL_BUILD obj-y += spl.o else -obj-$(CONFIG_T2080QDS) += t208xqds.o -obj-$(CONFIG_T2080QDS) += eth_t208xqds.o -obj-$(CONFIG_T2081QDS) += t208xqds.o -obj-$(CONFIG_T2081QDS) += eth_t208xqds.o +obj-$(CONFIG_T2080QDS) += t208xqds.o eth_t208xqds.o +obj-$(CONFIG_T2081QDS) += t208xqds.o eth_t208xqds.o obj-$(CONFIG_PCI) += pci.o endif diff --git a/board/freescale/t208xqds/ddr.c b/board/freescale/t208xqds/ddr.c index f1aff5481e..f96470f020 100644 --- a/board/freescale/t208xqds/ddr.c +++ b/board/freescale/t208xqds/ddr.c @@ -108,13 +108,12 @@ phys_size_t initdram(int board_type) #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) puts("Initializing....using SPD\n"); dram_size = fsl_ddr_sdram(); - - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; #else /* DDR has been initialised by first stage boot loader */ dram_size = fsl_ddr_sdram_size(); #endif + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; return dram_size; } diff --git a/board/freescale/t208xqds/ddr.h b/board/freescale/t208xqds/ddr.h index 9c26fdf3bd..255ab2c543 100644 --- a/board/freescale/t208xqds/ddr.h +++ b/board/freescale/t208xqds/ddr.h @@ -28,17 +28,17 @@ static const struct board_specific_parameters udimm0[] = { * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | */ - {2, 1200, 0, 5, 7, 0x0708090a, 0x0b0c0d09}, - {2, 1400, 0, 5, 7, 0x08090a0c, 0x0d0e0f0a}, - {2, 1700, 0, 5, 8, 0x090a0b0c, 0x0e10110c}, - {2, 1900, 0, 5, 8, 0x090b0c0f, 0x1012130d}, - {2, 2140, 0, 5, 8, 0x090b0c0f, 0x1012130d}, - {1, 1200, 0, 5, 7, 0x0808090a, 0x0b0c0c0a}, - {1, 1500, 0, 5, 6, 0x07070809, 0x0a0b0b09}, - {1, 1600, 0, 5, 8, 0x090b0b0d, 0x0d0e0f0b}, - {1, 1700, 0, 4, 8, 0x080a0a0c, 0x0c0d0e0a}, - {1, 1900, 0, 5, 8, 0x090a0c0d, 0x0e0f110c}, - {1, 2140, 0, 4, 8, 0x090a0b0d, 0x0e0f110b}, + {2, 1200, 0, 10, 7, 0x0708090a, 0x0b0c0d09}, + {2, 1400, 0, 10, 7, 0x08090a0c, 0x0d0e0f0a}, + {2, 1700, 0, 10, 8, 0x090a0b0c, 0x0e10110c}, + {2, 1900, 0, 10, 8, 0x090b0c0f, 0x1012130d}, + {2, 2140, 0, 10, 8, 0x090b0c0f, 0x1012130d}, + {1, 1200, 0, 10, 7, 0x0808090a, 0x0b0c0c0a}, + {1, 1500, 0, 10, 6, 0x07070809, 0x0a0b0b09}, + {1, 1600, 0, 10, 8, 0x090b0b0d, 0x0d0e0f0b}, + {1, 1700, 0, 8, 8, 0x080a0a0c, 0x0c0d0e0a}, + {1, 1900, 0, 10, 8, 0x090a0c0d, 0x0e0f110c}, + {1, 2140, 0, 8, 8, 0x090a0b0d, 0x0e0f110b}, {} }; @@ -49,15 +49,15 @@ static const struct board_specific_parameters rdimm0[] = { * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | */ /* TODO: need tuning these parameters if RDIMM is used */ - {4, 1350, 0, 5, 9, 0x08070605, 0x06070806}, - {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906}, - {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07}, - {2, 1350, 0, 5, 9, 0x08070605, 0x06070806}, - {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06}, - {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07}, - {1, 1350, 0, 5, 9, 0x08070605, 0x06070806}, - {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06}, - {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07}, + {4, 1350, 0, 10, 9, 0x08070605, 0x06070806}, + {4, 1666, 0, 10, 11, 0x0a080706, 0x07090906}, + {4, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07}, + {2, 1350, 0, 10, 9, 0x08070605, 0x06070806}, + {2, 1666, 0, 10, 11, 0x0a090806, 0x08090a06}, + {2, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07}, + {1, 1350, 0, 10, 9, 0x08070605, 0x06070806}, + {1, 1666, 0, 10, 11, 0x0a090806, 0x08090a06}, + {1, 2140, 0, 8, 12, 0x0b090807, 0x080a0b07}, {} }; diff --git a/board/freescale/t208xqds/spl.c b/board/freescale/t208xqds/spl.c index 55a0f8fdce..bb02dab2f1 100644 --- a/board/freescale/t208xqds/spl.c +++ b/board/freescale/t208xqds/spl.c @@ -106,6 +106,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) get_clocks(); mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, CONFIG_SPL_RELOC_MALLOC_SIZE); + gd->flags |= GD_FLG_FULL_MALLOC_INIT; #ifdef CONFIG_SPL_NAND_BOOT nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, diff --git a/board/freescale/t208xrdb/Makefile b/board/freescale/t208xrdb/Makefile index 9605f8b606..cd8fe096d8 100644 --- a/board/freescale/t208xrdb/Makefile +++ b/board/freescale/t208xrdb/Makefile @@ -5,11 +5,9 @@ # ifdef CONFIG_SPL_BUILD -obj-y += spl.o +obj-y += spl.o else -obj-$(CONFIG_T2080RDB) += t208xrdb.o -obj-$(CONFIG_T2080RDB) += eth_t208xrdb.o -obj-$(CONFIG_T2080RDB) += cpld.o +obj-$(CONFIG_T2080RDB) += t208xrdb.o eth_t208xrdb.o cpld.o obj-$(CONFIG_PCI) += pci.o endif diff --git a/board/freescale/t208xrdb/ddr.c b/board/freescale/t208xrdb/ddr.c index 053f128e5b..f6c8ca30ac 100644 --- a/board/freescale/t208xrdb/ddr.c +++ b/board/freescale/t208xrdb/ddr.c @@ -101,12 +101,12 @@ phys_size_t initdram(int board_type) #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) puts("Initializing....using SPD\n"); dram_size = fsl_ddr_sdram(); - - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; #else /* DDR has been initialised by first stage boot loader */ dram_size = fsl_ddr_sdram_size(); #endif + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + return dram_size; } diff --git a/board/freescale/t208xrdb/ddr.h b/board/freescale/t208xrdb/ddr.h index 08cbb606d5..175cf56a09 100644 --- a/board/freescale/t208xrdb/ddr.h +++ b/board/freescale/t208xrdb/ddr.h @@ -28,16 +28,16 @@ static const struct board_specific_parameters udimm0[] = { * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | */ - {2, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a}, - {2, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09}, - {2, 1600, 2, 5, 8, 0x0808070b, 0x0c0d0e0a}, - {2, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a}, - {2, 1900, 0, 5, 7, 0x0808080c, 0x0b0c0c09}, - {1, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a}, - {1, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09}, - {1, 1600, 2, 5, 8, 0x0808070b, 0x0c0d0e0a}, - {1, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a}, - {1, 1900, 0, 5, 7, 0x0808080c, 0x0b0c0c09}, + {2, 1200, 2, 10, 7, 0x0808090a, 0x0b0c0c0a}, + {2, 1500, 2, 10, 6, 0x07070809, 0x0a0b0b09}, + {2, 1600, 2, 10, 8, 0x0808070b, 0x0c0d0e0a}, + {2, 1700, 2, 8, 7, 0x080a0a0c, 0x0c0d0e0a}, + {2, 1900, 0, 10, 7, 0x0808080c, 0x0b0c0c09}, + {1, 1200, 2, 10, 7, 0x0808090a, 0x0b0c0c0a}, + {1, 1500, 2, 10, 6, 0x07070809, 0x0a0b0b09}, + {1, 1600, 2, 10, 8, 0x0808070b, 0x0c0d0e0a}, + {1, 1700, 2, 8, 7, 0x080a0a0c, 0x0c0d0e0a}, + {1, 1900, 0, 10, 7, 0x0808080c, 0x0b0c0c09}, {} }; diff --git a/board/freescale/t208xrdb/spl.c b/board/freescale/t208xrdb/spl.c index f63366bb0e..2ff05a29f5 100644 --- a/board/freescale/t208xrdb/spl.c +++ b/board/freescale/t208xrdb/spl.c @@ -76,6 +76,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) get_clocks(); mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, CONFIG_SPL_RELOC_MALLOC_SIZE); + gd->flags |= GD_FLG_FULL_MALLOC_INIT; #ifdef CONFIG_SPL_NAND_BOOT nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, diff --git a/board/freescale/t4qds/Makefile b/board/freescale/t4qds/Makefile index bd2c1f1622..731ccb0b29 100644 --- a/board/freescale/t4qds/Makefile +++ b/board/freescale/t4qds/Makefile @@ -5,12 +5,12 @@ # ifdef CONFIG_SPL_BUILD -obj-y += spl.o +obj-y += spl.o else -obj-$(CONFIG_T4240QDS) += t4240qds.o -obj-$(CONFIG_T4240QDS)+= eth.o +obj-$(CONFIG_T4240QDS) += t4240qds.o eth.o obj-$(CONFIG_PCI) += pci.o endif + obj-y += ddr.o obj-y += law.o obj-y += tlb.o diff --git a/board/freescale/t4qds/ddr.c b/board/freescale/t4qds/ddr.c index 62d58c5b1f..d533924a0d 100644 --- a/board/freescale/t4qds/ddr.c +++ b/board/freescale/t4qds/ddr.c @@ -117,13 +117,12 @@ phys_size_t initdram(int board_type) #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) dram_size = fsl_ddr_sdram(); - - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - #else /* DDR has been initialised by first stage boot loader */ dram_size = fsl_ddr_sdram_size(); #endif + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + return dram_size; } diff --git a/board/freescale/t4qds/ddr.h b/board/freescale/t4qds/ddr.h index 4d0e3c497d..0b0cc9af39 100644 --- a/board/freescale/t4qds/ddr.h +++ b/board/freescale/t4qds/ddr.h @@ -31,16 +31,16 @@ static const struct board_specific_parameters udimm0[] = { * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | */ - {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, - {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0}, - {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0}, - {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0}, - {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, - {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, - {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, - {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, - {1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0}, - {1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0}, + {2, 1350, 4, 8, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, + {2, 1350, 0, 10, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0}, + {2, 1666, 4, 8, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0}, + {2, 1666, 0, 10, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0}, + {2, 1900, 0, 8, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, + {2, 2140, 0, 8, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, + {1, 1350, 0, 10, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, + {1, 1700, 0, 10, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, + {1, 1900, 0, 8, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0}, + {1, 2140, 0, 8, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0}, {} }; @@ -50,15 +50,15 @@ static const struct board_specific_parameters rdimm0[] = { * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | */ - {4, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, - {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906, 0xff, 2, 0}, - {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, - {2, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, - {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0}, - {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, - {1, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, - {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0}, - {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, + {4, 1350, 0, 10, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, + {4, 1666, 0, 10, 11, 0x0a080706, 0x07090906, 0xff, 2, 0}, + {4, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, + {2, 1350, 0, 10, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, + {2, 1666, 0, 10, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0}, + {2, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, + {1, 1350, 0, 10, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, + {1, 1666, 0, 10, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0}, + {1, 2140, 0, 8, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, {} }; diff --git a/board/freescale/t4qds/spl.c b/board/freescale/t4qds/spl.c index d52059a145..6ca0f03ffe 100644 --- a/board/freescale/t4qds/spl.c +++ b/board/freescale/t4qds/spl.c @@ -116,6 +116,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) get_clocks(); mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, CONFIG_SPL_RELOC_MALLOC_SIZE); + gd->flags |= GD_FLG_FULL_MALLOC_INIT; #ifdef CONFIG_SPL_NAND_BOOT nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, diff --git a/board/freescale/t4rdb/Makefile b/board/freescale/t4rdb/Makefile index 83b55ee193..4f29eea0f4 100644 --- a/board/freescale/t4rdb/Makefile +++ b/board/freescale/t4rdb/Makefile @@ -5,13 +5,14 @@ # ifdef CONFIG_SPL_BUILD -obj-y += spl.o +obj-y += spl.o else -obj-$(CONFIG_T4240RDB) += t4240rdb.o -obj-y += cpld.o -obj-y += eth.o +obj-$(CONFIG_T4240RDB) += t4240rdb.o +obj-y += cpld.o +obj-y += eth.o obj-$(CONFIG_PCI) += pci.o endif + obj-y += ddr.o obj-y += law.o obj-y += tlb.o diff --git a/board/freescale/t4rdb/ddr.c b/board/freescale/t4rdb/ddr.c index 27b37b5cc4..230f031a3b 100644 --- a/board/freescale/t4rdb/ddr.c +++ b/board/freescale/t4rdb/ddr.c @@ -110,13 +110,12 @@ phys_size_t initdram(int board_type) #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL) dram_size = fsl_ddr_sdram(); - - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; #else /* DDR has been initialised by first stage boot loader */ dram_size = fsl_ddr_sdram_size(); #endif + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; return dram_size; } diff --git a/board/freescale/t4rdb/ddr.h b/board/freescale/t4rdb/ddr.h index 7b854767e7..f01ebb22b5 100644 --- a/board/freescale/t4rdb/ddr.h +++ b/board/freescale/t4rdb/ddr.h @@ -27,16 +27,16 @@ static const struct board_specific_parameters udimm0[] = { * num| hi| rank| clk| wrlvl | wrlvl | wrlvl * ranks| mhz| GB |adjst| start | ctl2 | ctl3 */ - {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a}, - {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09}, - {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b}, - {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a}, - {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c}, - {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c}, - {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a}, - {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a}, - {1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a}, - {1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b}, + {2, 1350, 4, 8, 8, 0x0809090b, 0x0c0c0d0a}, + {2, 1350, 0, 10, 7, 0x0709090b, 0x0c0c0d09}, + {2, 1666, 4, 8, 8, 0x080a0a0d, 0x0d10100b}, + {2, 1666, 0, 10, 7, 0x080a0a0c, 0x0d0d0e0a}, + {2, 1900, 0, 8, 8, 0x090a0b0e, 0x0f11120c}, + {2, 2140, 0, 8, 8, 0x090a0b0e, 0x0f11120c}, + {1, 1350, 0, 10, 8, 0x0809090b, 0x0c0c0d0a}, + {1, 1700, 0, 10, 8, 0x080a0a0c, 0x0c0d0e0a}, + {1, 1900, 0, 8, 8, 0x080a0a0c, 0x0e0e0f0a}, + {1, 2140, 0, 8, 8, 0x090a0b0c, 0x0e0f100b}, {} }; @@ -46,15 +46,15 @@ static const struct board_specific_parameters rdimm0[] = { * num| hi| rank| clk| wrlvl | wrlvl | wrlvl * ranks| mhz| GB |adjst| start | ctl2 | ctl3 */ - {4, 1350, 0, 5, 9, 0x08070605, 0x06070806}, - {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906}, - {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07}, - {2, 1350, 0, 5, 9, 0x08070605, 0x06070806}, - {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06}, - {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07}, - {1, 1350, 0, 5, 9, 0x08070605, 0x06070806}, - {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06}, - {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07}, + {4, 1350, 0, 10, 9, 0x08070605, 0x06070806}, + {4, 1666, 0, 10, 11, 0x0a080706, 0x07090906}, + {4, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07}, + {2, 1350, 0, 10, 9, 0x08070605, 0x06070806}, + {2, 1666, 0, 10, 11, 0x0a090806, 0x08090a06}, + {2, 2140, 0, 10, 12, 0x0b090807, 0x080a0b07}, + {1, 1350, 0, 10, 9, 0x08070605, 0x06070806}, + {1, 1666, 0, 10, 11, 0x0a090806, 0x08090a06}, + {1, 2140, 0, 8, 12, 0x0b090807, 0x080a0b07}, {} }; diff --git a/board/freescale/t4rdb/spl.c b/board/freescale/t4rdb/spl.c index 4c1e0cc8d0..b148a7fd1f 100644 --- a/board/freescale/t4rdb/spl.c +++ b/board/freescale/t4rdb/spl.c @@ -80,6 +80,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) get_clocks(); mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, CONFIG_SPL_RELOC_MALLOC_SIZE); + gd->flags |= GD_FLG_FULL_MALLOC_INIT; mmc_initialize(bd); mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, diff --git a/board/nvidia/cardhu/cardhu.c b/board/nvidia/cardhu/cardhu.c index ba15e2e6cf..f04f843c31 100644 --- a/board/nvidia/cardhu/cardhu.c +++ b/board/nvidia/cardhu/cardhu.c @@ -110,11 +110,11 @@ int tegra_pcie_board_init(void) } /* GPIO: PEX = 3.3V */ - err = gpio_request(GPIO_PL7, "PEX"); + err = gpio_request(TEGRA_GPIO(L, 7), "PEX"); if (err < 0) return err; - gpio_direction_output(GPIO_PL7, 1); + gpio_direction_output(TEGRA_GPIO(L, 7), 1); /* TPS659110: LDO2_REG = 1.05V, ACTIVE */ data[0] = 0x15; diff --git a/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h b/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h index 7eb1e6c1b3..7955ca5cdf 100644 --- a/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h +++ b/board/nvidia/e2220-1170/pinmux-config-e2220-1170.h @@ -15,71 +15,71 @@ #ifndef _PINMUX_CONFIG_E2220_1170_H_ #define _PINMUX_CONFIG_E2220_1170_H_ -#define GPIO_INIT(_gpio, _init) \ +#define GPIO_INIT(_port, _gpio, _init) \ { \ - .gpio = GPIO_P##_gpio, \ + .gpio = TEGRA_GPIO(_port, _gpio), \ .init = TEGRA_GPIO_INIT_##_init, \ } static const struct tegra_gpio_config e2220_1170_gpio_inits[] = { - /* gpio, init_val */ - GPIO_INIT(A5, IN), - GPIO_INIT(A6, IN), - GPIO_INIT(B4, IN), - GPIO_INIT(E6, IN), - GPIO_INIT(G2, OUT0), - GPIO_INIT(G3, OUT0), - GPIO_INIT(H0, OUT0), - GPIO_INIT(H1, OUT0), - GPIO_INIT(H2, IN), - GPIO_INIT(H3, OUT0), - GPIO_INIT(H4, OUT0), - GPIO_INIT(H5, IN), - GPIO_INIT(H6, OUT0), - GPIO_INIT(H7, OUT0), - GPIO_INIT(I0, OUT0), - GPIO_INIT(I1, IN), - GPIO_INIT(I2, OUT0), - GPIO_INIT(I3, OUT0), - GPIO_INIT(K0, IN), - GPIO_INIT(K1, OUT0), - GPIO_INIT(K2, OUT0), - GPIO_INIT(K3, OUT0), - GPIO_INIT(K4, IN), - GPIO_INIT(K5, OUT0), - GPIO_INIT(K6, IN), - GPIO_INIT(K7, OUT0), - GPIO_INIT(L0, OUT0), - GPIO_INIT(S4, OUT0), - GPIO_INIT(S5, OUT0), - GPIO_INIT(S6, OUT0), - GPIO_INIT(S7, OUT0), - GPIO_INIT(T0, OUT0), - GPIO_INIT(T1, OUT0), - GPIO_INIT(V1, OUT0), - GPIO_INIT(V2, OUT0), - GPIO_INIT(V3, IN), - GPIO_INIT(V5, OUT0), - GPIO_INIT(V6, OUT0), - GPIO_INIT(X0, IN), - GPIO_INIT(X1, IN), - GPIO_INIT(X2, IN), - GPIO_INIT(X3, IN), - GPIO_INIT(X4, IN), - GPIO_INIT(X5, IN), - GPIO_INIT(X6, IN), - GPIO_INIT(X7, IN), - GPIO_INIT(Y0, IN), - GPIO_INIT(Y1, IN), - GPIO_INIT(Z0, IN), - GPIO_INIT(Z4, OUT0), - GPIO_INIT(BB2, OUT0), - GPIO_INIT(BB3, OUT0), - GPIO_INIT(BB4, IN), - GPIO_INIT(CC1, IN), - GPIO_INIT(CC5, OUT0), - GPIO_INIT(CC6, IN), - GPIO_INIT(CC7, OUT0), + /* port, pin, init_val */ + GPIO_INIT(A, 5, IN), + GPIO_INIT(A, 6, IN), + GPIO_INIT(B, 4, IN), + GPIO_INIT(E, 6, IN), + GPIO_INIT(G, 2, OUT0), + GPIO_INIT(G, 3, OUT0), + GPIO_INIT(H, 0, OUT0), + GPIO_INIT(H, 1, OUT0), + GPIO_INIT(H, 2, IN), + GPIO_INIT(H, 3, OUT0), + GPIO_INIT(H, 4, OUT0), + GPIO_INIT(H, 5, IN), + GPIO_INIT(H, 6, OUT0), + GPIO_INIT(H, 7, OUT0), + GPIO_INIT(I, 0, OUT0), + GPIO_INIT(I, 1, IN), + GPIO_INIT(I, 2, OUT0), + GPIO_INIT(I, 3, OUT0), + GPIO_INIT(K, 0, IN), + GPIO_INIT(K, 1, OUT0), + GPIO_INIT(K, 2, OUT0), + GPIO_INIT(K, 3, OUT0), + GPIO_INIT(K, 4, IN), + GPIO_INIT(K, 5, OUT0), + GPIO_INIT(K, 6, IN), + GPIO_INIT(K, 7, OUT0), + GPIO_INIT(L, 0, OUT0), + GPIO_INIT(S, 4, OUT0), + GPIO_INIT(S, 5, OUT0), + GPIO_INIT(S, 6, OUT0), + GPIO_INIT(S, 7, OUT0), + GPIO_INIT(T, 0, OUT0), + GPIO_INIT(T, 1, OUT0), + GPIO_INIT(V, 1, OUT0), + GPIO_INIT(V, 2, OUT0), + GPIO_INIT(V, 3, IN), + GPIO_INIT(V, 5, OUT0), + GPIO_INIT(V, 6, OUT0), + GPIO_INIT(X, 0, IN), + GPIO_INIT(X, 1, IN), + GPIO_INIT(X, 2, IN), + GPIO_INIT(X, 3, IN), + GPIO_INIT(X, 4, IN), + GPIO_INIT(X, 5, IN), + GPIO_INIT(X, 6, IN), + GPIO_INIT(X, 7, IN), + GPIO_INIT(Y, 0, IN), + GPIO_INIT(Y, 1, IN), + GPIO_INIT(Z, 0, IN), + GPIO_INIT(Z, 4, OUT0), + GPIO_INIT(BB, 2, OUT0), + GPIO_INIT(BB, 3, OUT0), + GPIO_INIT(BB, 4, IN), + GPIO_INIT(CC, 1, IN), + GPIO_INIT(CC, 5, OUT0), + GPIO_INIT(CC, 6, IN), + GPIO_INIT(CC, 7, OUT0), }; #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \ diff --git a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h index 00e0cdc4b8..01237dbc29 100644 --- a/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h +++ b/board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h @@ -15,63 +15,63 @@ #ifndef _PINMUX_CONFIG_JETSON_TK1_H_ #define _PINMUX_CONFIG_JETSON_TK1_H_ -#define GPIO_INIT(_gpio, _init) \ +#define GPIO_INIT(_port, _gpio, _init) \ { \ - .gpio = GPIO_P##_gpio, \ + .gpio = TEGRA_GPIO(_port, _gpio), \ .init = TEGRA_GPIO_INIT_##_init, \ } static const struct tegra_gpio_config jetson_tk1_gpio_inits[] = { - /* gpio, init_val */ - GPIO_INIT(G0, IN), - GPIO_INIT(G1, IN), - GPIO_INIT(G2, IN), - GPIO_INIT(G3, IN), - GPIO_INIT(G4, IN), - GPIO_INIT(H2, OUT0), - GPIO_INIT(H4, IN), - GPIO_INIT(H7, IN), - GPIO_INIT(I0, OUT0), - GPIO_INIT(I1, IN), - GPIO_INIT(I6, IN), - GPIO_INIT(J0, IN), - GPIO_INIT(K1, OUT0), - GPIO_INIT(K2, IN), - GPIO_INIT(K4, OUT0), - GPIO_INIT(K6, OUT0), - GPIO_INIT(N7, IN), - GPIO_INIT(O1, IN), - GPIO_INIT(O4, IN), - GPIO_INIT(P2, OUT0), - GPIO_INIT(Q0, IN), - GPIO_INIT(Q3, IN), - GPIO_INIT(Q5, IN), - GPIO_INIT(R0, OUT0), - GPIO_INIT(R2, OUT0), - GPIO_INIT(R4, IN), - GPIO_INIT(R7, IN), - GPIO_INIT(S7, IN), - GPIO_INIT(T0, OUT0), - GPIO_INIT(T1, IN), - GPIO_INIT(U0, IN), - GPIO_INIT(U1, IN), - GPIO_INIT(U2, IN), - GPIO_INIT(U3, IN), - GPIO_INIT(U4, IN), - GPIO_INIT(U5, IN), - GPIO_INIT(U6, IN), - GPIO_INIT(V0, IN), - GPIO_INIT(V1, IN), - GPIO_INIT(X1, IN), - GPIO_INIT(X4, IN), - GPIO_INIT(X7, OUT0), - GPIO_INIT(BB3, OUT0), - GPIO_INIT(BB5, OUT0), - GPIO_INIT(BB6, OUT0), - GPIO_INIT(BB7, OUT0), - GPIO_INIT(CC1, IN), - GPIO_INIT(CC2, IN), - GPIO_INIT(EE2, OUT1), + /* port, pin, init_val */ + GPIO_INIT(G, 0, IN), + GPIO_INIT(G, 1, IN), + GPIO_INIT(G, 2, IN), + GPIO_INIT(G, 3, IN), + GPIO_INIT(G, 4, IN), + GPIO_INIT(H, 2, OUT0), + GPIO_INIT(H, 4, IN), + GPIO_INIT(H, 7, IN), + GPIO_INIT(I, 0, OUT0), + GPIO_INIT(I, 1, IN), + GPIO_INIT(I, 6, IN), + GPIO_INIT(J, 0, IN), + GPIO_INIT(K, 1, OUT0), + GPIO_INIT(K, 2, IN), + GPIO_INIT(K, 4, OUT0), + GPIO_INIT(K, 6, OUT0), + GPIO_INIT(N, 7, IN), + GPIO_INIT(O, 1, IN), + GPIO_INIT(O, 4, IN), + GPIO_INIT(P, 2, OUT0), + GPIO_INIT(Q, 0, IN), + GPIO_INIT(Q, 3, IN), + GPIO_INIT(Q, 5, IN), + GPIO_INIT(R, 0, OUT0), + GPIO_INIT(R, 2, OUT0), + GPIO_INIT(R, 4, IN), + GPIO_INIT(R, 7, IN), + GPIO_INIT(S, 7, IN), + GPIO_INIT(T, 0, OUT0), + GPIO_INIT(T, 1, IN), + GPIO_INIT(U, 0, IN), + GPIO_INIT(U, 1, IN), + GPIO_INIT(U, 2, IN), + GPIO_INIT(U, 3, IN), + GPIO_INIT(U, 4, IN), + GPIO_INIT(U, 5, IN), + GPIO_INIT(U, 6, IN), + GPIO_INIT(V, 0, IN), + GPIO_INIT(V, 1, IN), + GPIO_INIT(X, 1, IN), + GPIO_INIT(X, 4, IN), + GPIO_INIT(X, 7, OUT0), + GPIO_INIT(BB, 3, OUT0), + GPIO_INIT(BB, 5, OUT0), + GPIO_INIT(BB, 6, OUT0), + GPIO_INIT(BB, 7, OUT0), + GPIO_INIT(CC, 1, IN), + GPIO_INIT(CC, 2, IN), + GPIO_INIT(EE, 2, OUT1), }; #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \ diff --git a/board/nvidia/nyan-big/nyan-big.c b/board/nvidia/nyan-big/nyan-big.c index ba96401890..8f68ae9fbe 100644 --- a/board/nvidia/nyan-big/nyan-big.c +++ b/board/nvidia/nyan-big/nyan-big.c @@ -36,8 +36,9 @@ void pinmux_init(void) int tegra_board_id(void) { - static const int vector[] = {GPIO_PQ3, GPIO_PT1, GPIO_PX1, - GPIO_PX4, -1}; + static const int vector[] = {TEGRA_GPIO(Q, 3), TEGRA_GPIO(T, 1), + TEGRA_GPIO(X, 1), TEGRA_GPIO(X, 4), + -1}; gpio_claim_vector(vector, "board_id%d"); return gpio_get_values_as_int(vector); diff --git a/board/nvidia/nyan-big/pinmux-config-nyan-big.h b/board/nvidia/nyan-big/pinmux-config-nyan-big.h index dca0171f26..fd7f1d17f4 100644 --- a/board/nvidia/nyan-big/pinmux-config-nyan-big.h +++ b/board/nvidia/nyan-big/pinmux-config-nyan-big.h @@ -15,59 +15,59 @@ #ifndef _PINMUX_CONFIG_NYAN_BIG_H_ #define _PINMUX_CONFIG_NYAN_BIG_H_ -#define GPIO_INIT(_gpio, _init) \ +#define GPIO_INIT(_port, _gpio, _init) \ { \ - .gpio = GPIO_P##_gpio, \ + .gpio = TEGRA_GPIO(_port, _gpio), \ .init = TEGRA_GPIO_INIT_##_init, \ } static const struct tegra_gpio_config nyan_big_gpio_inits[] = { - /* gpio, init_val */ - GPIO_INIT(A0, IN), - GPIO_INIT(C7, IN), - GPIO_INIT(G0, IN), - GPIO_INIT(G1, IN), - GPIO_INIT(G2, IN), - GPIO_INIT(G3, IN), - GPIO_INIT(H2, IN), - GPIO_INIT(H4, IN), - GPIO_INIT(H6, IN), - GPIO_INIT(H7, OUT1), - GPIO_INIT(I0, IN), - GPIO_INIT(I1, IN), - GPIO_INIT(I5, OUT1), - GPIO_INIT(I6, IN), - GPIO_INIT(I7, IN), - GPIO_INIT(J0, IN), - GPIO_INIT(J7, IN), - GPIO_INIT(K1, OUT0), - GPIO_INIT(K2, IN), - GPIO_INIT(K4, OUT0), - GPIO_INIT(K6, OUT0), - GPIO_INIT(K7, IN), - GPIO_INIT(N7, IN), - GPIO_INIT(P2, OUT0), - GPIO_INIT(Q0, IN), - GPIO_INIT(Q2, IN), - GPIO_INIT(Q3, IN), - GPIO_INIT(Q6, IN), - GPIO_INIT(Q7, IN), - GPIO_INIT(R0, OUT0), - GPIO_INIT(R1, IN), - GPIO_INIT(R4, IN), - GPIO_INIT(R7, IN), - GPIO_INIT(S3, OUT0), - GPIO_INIT(S4, OUT0), - GPIO_INIT(S7, IN), - GPIO_INIT(T1, IN), - GPIO_INIT(U4, IN), - GPIO_INIT(U5, IN), - GPIO_INIT(U6, IN), - GPIO_INIT(V0, IN), - GPIO_INIT(W3, IN), - GPIO_INIT(X1, IN), - GPIO_INIT(X4, IN), - GPIO_INIT(X7, OUT0), + /* port, pin, init_val */ + GPIO_INIT(A, 0, IN), + GPIO_INIT(C, 7, IN), + GPIO_INIT(G, 0, IN), + GPIO_INIT(G, 1, IN), + GPIO_INIT(G, 2, IN), + GPIO_INIT(G, 3, IN), + GPIO_INIT(H, 2, IN), + GPIO_INIT(H, 4, IN), + GPIO_INIT(H, 6, IN), + GPIO_INIT(H, 7, OUT1), + GPIO_INIT(I, 0, IN), + GPIO_INIT(I, 1, IN), + GPIO_INIT(I, 5, OUT1), + GPIO_INIT(I, 6, IN), + GPIO_INIT(I, 7, IN), + GPIO_INIT(J, 0, IN), + GPIO_INIT(J, 7, IN), + GPIO_INIT(K, 1, OUT0), + GPIO_INIT(K, 2, IN), + GPIO_INIT(K, 4, OUT0), + GPIO_INIT(K, 6, OUT0), + GPIO_INIT(K, 7, IN), + GPIO_INIT(N, 7, IN), + GPIO_INIT(P, 2, OUT0), + GPIO_INIT(Q, 0, IN), + GPIO_INIT(Q, 2, IN), + GPIO_INIT(Q, 3, IN), + GPIO_INIT(Q, 6, IN), + GPIO_INIT(Q, 7, IN), + GPIO_INIT(R, 0, OUT0), + GPIO_INIT(R, 1, IN), + GPIO_INIT(R, 4, IN), + GPIO_INIT(R, 7, IN), + GPIO_INIT(S, 3, OUT0), + GPIO_INIT(S, 4, OUT0), + GPIO_INIT(S, 7, IN), + GPIO_INIT(T, 1, IN), + GPIO_INIT(U, 4, IN), + GPIO_INIT(U, 5, IN), + GPIO_INIT(U, 6, IN), + GPIO_INIT(V, 0, IN), + GPIO_INIT(W, 3, IN), + GPIO_INIT(X, 1, IN), + GPIO_INIT(X, 4, IN), + GPIO_INIT(X, 7, OUT0), }; #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \ diff --git a/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h b/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h index 35706b4745..24acbccd97 100644 --- a/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h +++ b/board/nvidia/p2371-0000/pinmux-config-p2371-0000.h @@ -15,62 +15,62 @@ #ifndef _PINMUX_CONFIG_P2371_0000_H_ #define _PINMUX_CONFIG_P2371_0000_H_ -#define GPIO_INIT(_gpio, _init) \ +#define GPIO_INIT(_port, _gpio, _init) \ { \ - .gpio = GPIO_P##_gpio, \ + .gpio = TEGRA_GPIO(_port, _gpio), \ .init = TEGRA_GPIO_INIT_##_init, \ } static const struct tegra_gpio_config p2371_0000_gpio_inits[] = { - /* gpio, init_val */ - GPIO_INIT(A5, IN), - GPIO_INIT(E4, OUT0), - GPIO_INIT(E6, IN), - GPIO_INIT(G0, IN), - GPIO_INIT(G3, OUT0), - GPIO_INIT(H0, OUT0), - GPIO_INIT(H2, IN), - GPIO_INIT(H3, OUT0), - GPIO_INIT(H4, OUT0), - GPIO_INIT(H5, IN), - GPIO_INIT(H6, OUT0), - GPIO_INIT(H7, OUT0), - GPIO_INIT(I0, OUT0), - GPIO_INIT(I1, IN), - GPIO_INIT(I2, OUT0), - GPIO_INIT(I3, OUT0), - GPIO_INIT(K4, IN), - GPIO_INIT(K5, OUT0), - GPIO_INIT(K6, IN), - GPIO_INIT(K7, OUT0), - GPIO_INIT(L0, OUT0), - GPIO_INIT(S4, OUT0), - GPIO_INIT(S5, OUT0), - GPIO_INIT(S6, OUT0), - GPIO_INIT(S7, OUT0), - GPIO_INIT(T0, OUT0), - GPIO_INIT(T1, OUT0), - GPIO_INIT(V1, OUT0), - GPIO_INIT(V2, OUT0), - GPIO_INIT(V5, OUT0), - GPIO_INIT(V6, OUT0), - GPIO_INIT(V7, OUT1), - GPIO_INIT(X0, IN), - GPIO_INIT(X1, IN), - GPIO_INIT(X2, IN), - GPIO_INIT(X3, IN), - GPIO_INIT(X4, IN), - GPIO_INIT(X5, IN), - GPIO_INIT(X6, IN), - GPIO_INIT(X7, IN), - GPIO_INIT(Y1, IN), - GPIO_INIT(Z0, IN), - GPIO_INIT(Z4, OUT0), - GPIO_INIT(BB2, OUT0), - GPIO_INIT(BB3, OUT0), - GPIO_INIT(CC1, IN), - GPIO_INIT(CC6, IN), - GPIO_INIT(CC7, OUT0), + /* port, pin, init_val */ + GPIO_INIT(A, 5, IN), + GPIO_INIT(E, 4, OUT0), + GPIO_INIT(E, 6, IN), + GPIO_INIT(G, 0, IN), + GPIO_INIT(G, 3, OUT0), + GPIO_INIT(H, 0, OUT0), + GPIO_INIT(H, 2, IN), + GPIO_INIT(H, 3, OUT0), + GPIO_INIT(H, 4, OUT0), + GPIO_INIT(H, 5, IN), + GPIO_INIT(H, 6, OUT0), + GPIO_INIT(H, 7, OUT0), + GPIO_INIT(I, 0, OUT0), + GPIO_INIT(I, 1, IN), + GPIO_INIT(I, 2, OUT0), + GPIO_INIT(I, 3, OUT0), + GPIO_INIT(K, 4, IN), + GPIO_INIT(K, 5, OUT0), + GPIO_INIT(K, 6, IN), + GPIO_INIT(K, 7, OUT0), + GPIO_INIT(L, 0, OUT0), + GPIO_INIT(S, 4, OUT0), + GPIO_INIT(S, 5, OUT0), + GPIO_INIT(S, 6, OUT0), + GPIO_INIT(S, 7, OUT0), + GPIO_INIT(T, 0, OUT0), + GPIO_INIT(T, 1, OUT0), + GPIO_INIT(V, 1, OUT0), + GPIO_INIT(V, 2, OUT0), + GPIO_INIT(V, 5, OUT0), + GPIO_INIT(V, 6, OUT0), + GPIO_INIT(V, 7, OUT1), + GPIO_INIT(X, 0, IN), + GPIO_INIT(X, 1, IN), + GPIO_INIT(X, 2, IN), + GPIO_INIT(X, 3, IN), + GPIO_INIT(X, 4, IN), + GPIO_INIT(X, 5, IN), + GPIO_INIT(X, 6, IN), + GPIO_INIT(X, 7, IN), + GPIO_INIT(Y, 1, IN), + GPIO_INIT(Z, 0, IN), + GPIO_INIT(Z, 4, OUT0), + GPIO_INIT(BB, 2, OUT0), + GPIO_INIT(BB, 3, OUT0), + GPIO_INIT(CC, 1, IN), + GPIO_INIT(CC, 6, IN), + GPIO_INIT(CC, 7, OUT0), }; #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \ diff --git a/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h b/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h index d5be6ecda9..601728e469 100644 --- a/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h +++ b/board/nvidia/p2371-2180/pinmux-config-p2371-2180.h @@ -15,73 +15,73 @@ #ifndef _PINMUX_CONFIG_P2371_2180_H_ #define _PINMUX_CONFIG_P2371_2180_H_ -#define GPIO_INIT(_gpio, _init) \ +#define GPIO_INIT(_port, _gpio, _init) \ { \ - .gpio = GPIO_P##_gpio, \ + .gpio = TEGRA_GPIO(_port, _gpio), \ .init = TEGRA_GPIO_INIT_##_init, \ } static const struct tegra_gpio_config p2371_2180_gpio_inits[] = { - /* gpio, init_val */ - GPIO_INIT(A5, IN), - GPIO_INIT(B0, IN), - GPIO_INIT(B1, IN), - GPIO_INIT(B2, IN), - GPIO_INIT(B3, IN), - GPIO_INIT(C0, IN), - GPIO_INIT(C1, IN), - GPIO_INIT(C2, IN), - GPIO_INIT(C3, IN), - GPIO_INIT(C4, IN), - GPIO_INIT(E4, IN), - GPIO_INIT(E5, IN), - GPIO_INIT(E6, IN), - GPIO_INIT(H0, OUT0), - GPIO_INIT(H1, OUT0), - GPIO_INIT(H2, IN), - GPIO_INIT(H3, OUT0), - GPIO_INIT(H4, OUT0), - GPIO_INIT(H5, IN), - GPIO_INIT(H6, IN), - GPIO_INIT(H7, IN), - GPIO_INIT(I0, OUT0), - GPIO_INIT(I1, IN), - GPIO_INIT(I2, OUT0), - GPIO_INIT(K4, IN), - GPIO_INIT(K5, OUT0), - GPIO_INIT(K6, IN), - GPIO_INIT(K7, IN), - GPIO_INIT(L1, IN), - GPIO_INIT(S4, OUT0), - GPIO_INIT(S5, OUT0), - GPIO_INIT(S6, OUT0), - GPIO_INIT(S7, OUT0), - GPIO_INIT(T0, OUT0), - GPIO_INIT(T1, OUT0), - GPIO_INIT(U2, IN), - GPIO_INIT(U3, IN), - GPIO_INIT(V1, OUT0), - GPIO_INIT(V2, OUT0), - GPIO_INIT(V3, IN), - GPIO_INIT(V5, OUT0), - GPIO_INIT(V6, OUT0), - GPIO_INIT(X0, IN), - GPIO_INIT(X1, IN), - GPIO_INIT(X2, IN), - GPIO_INIT(X3, IN), - GPIO_INIT(X4, IN), - GPIO_INIT(X5, IN), - GPIO_INIT(X6, IN), - GPIO_INIT(X7, IN), - GPIO_INIT(Y0, IN), - GPIO_INIT(Y1, IN), - GPIO_INIT(Z0, IN), - GPIO_INIT(Z2, IN), - GPIO_INIT(Z3, OUT0), - GPIO_INIT(BB0, IN), - GPIO_INIT(BB2, OUT0), - GPIO_INIT(BB3, IN), - GPIO_INIT(CC1, IN), + /* port, pin, init_val */ + GPIO_INIT(A, 5, IN), + GPIO_INIT(B, 0, IN), + GPIO_INIT(B, 1, IN), + GPIO_INIT(B, 2, IN), + GPIO_INIT(B, 3, IN), + GPIO_INIT(C, 0, IN), + GPIO_INIT(C, 1, IN), + GPIO_INIT(C, 2, IN), + GPIO_INIT(C, 3, IN), + GPIO_INIT(C, 4, IN), + GPIO_INIT(E, 4, IN), + GPIO_INIT(E, 5, IN), + GPIO_INIT(E, 6, IN), + GPIO_INIT(H, 0, OUT0), + GPIO_INIT(H, 1, OUT0), + GPIO_INIT(H, 2, IN), + GPIO_INIT(H, 3, OUT0), + GPIO_INIT(H, 4, OUT0), + GPIO_INIT(H, 5, IN), + GPIO_INIT(H, 6, IN), + GPIO_INIT(H, 7, IN), + GPIO_INIT(I, 0, OUT0), + GPIO_INIT(I, 1, IN), + GPIO_INIT(I, 2, OUT0), + GPIO_INIT(K, 4, IN), + GPIO_INIT(K, 5, OUT0), + GPIO_INIT(K, 6, IN), + GPIO_INIT(K, 7, IN), + GPIO_INIT(L, 1, IN), + GPIO_INIT(S, 4, OUT0), + GPIO_INIT(S, 5, OUT0), + GPIO_INIT(S, 6, OUT0), + GPIO_INIT(S, 7, OUT0), + GPIO_INIT(T, 0, OUT0), + GPIO_INIT(T, 1, OUT0), + GPIO_INIT(U, 2, IN), + GPIO_INIT(U, 3, IN), + GPIO_INIT(V, 1, OUT0), + GPIO_INIT(V, 2, OUT0), + GPIO_INIT(V, 3, IN), + GPIO_INIT(V, 5, OUT0), + GPIO_INIT(V, 6, OUT0), + GPIO_INIT(X, 0, IN), + GPIO_INIT(X, 1, IN), + GPIO_INIT(X, 2, IN), + GPIO_INIT(X, 3, IN), + GPIO_INIT(X, 4, IN), + GPIO_INIT(X, 5, IN), + GPIO_INIT(X, 6, IN), + GPIO_INIT(X, 7, IN), + GPIO_INIT(Y, 0, IN), + GPIO_INIT(Y, 1, IN), + GPIO_INIT(Z, 0, IN), + GPIO_INIT(Z, 2, IN), + GPIO_INIT(Z, 3, OUT0), + GPIO_INIT(BB, 0, IN), + GPIO_INIT(BB, 2, OUT0), + GPIO_INIT(BB, 3, IN), + GPIO_INIT(CC, 1, IN), }; #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \ diff --git a/board/nvidia/p2571/p2571.c b/board/nvidia/p2571/p2571.c index d80a7d0d3e..7ce656f51a 100644 --- a/board/nvidia/p2571/p2571.c +++ b/board/nvidia/p2571/p2571.c @@ -58,6 +58,6 @@ void pinmux_init(void) void start_cpu_fan(void) { /* GPIO_PE4 is PS_VDD_FAN_ENABLE */ - gpio_request(GPIO_PE4, "FAN_VDD"); - gpio_direction_output(GPIO_PE4, 1); + gpio_request(TEGRA_GPIO(E, 4), "FAN_VDD"); + gpio_direction_output(TEGRA_GPIO(E, 4), 1); } diff --git a/board/nvidia/p2571/pinmux-config-p2571.h b/board/nvidia/p2571/pinmux-config-p2571.h index d3233016b5..dd4228f671 100644 --- a/board/nvidia/p2571/pinmux-config-p2571.h +++ b/board/nvidia/p2571/pinmux-config-p2571.h @@ -15,37 +15,37 @@ #ifndef _PINMUX_CONFIG_P2571_H_ #define _PINMUX_CONFIG_P2571_H_ -#define GPIO_INIT(_gpio, _init) \ +#define GPIO_INIT(_port, _gpio, _init) \ { \ - .gpio = GPIO_P##_gpio, \ + .gpio = TEGRA_GPIO(_port, _gpio), \ .init = TEGRA_GPIO_INIT_##_init, \ } static const struct tegra_gpio_config p2571_gpio_inits[] = { - /* gpio, init_val */ - GPIO_INIT(A0, IN), - GPIO_INIT(A5, IN), - GPIO_INIT(D4, IN), - GPIO_INIT(E4, OUT0), - GPIO_INIT(G0, IN), - GPIO_INIT(H0, OUT0), - GPIO_INIT(H2, IN), - GPIO_INIT(H3, OUT0), - GPIO_INIT(H4, OUT0), - GPIO_INIT(H5, IN), - GPIO_INIT(I0, OUT0), - GPIO_INIT(I1, IN), - GPIO_INIT(V1, OUT0), - GPIO_INIT(V6, OUT1), - GPIO_INIT(X4, IN), - GPIO_INIT(X6, IN), - GPIO_INIT(X7, IN), - GPIO_INIT(Y1, IN), - GPIO_INIT(Z0, IN), - GPIO_INIT(Z4, OUT0), - GPIO_INIT(BB2, OUT0), - GPIO_INIT(CC1, IN), - GPIO_INIT(CC3, IN), + /* port, pin, init_val */ + GPIO_INIT(A, 0, IN), + GPIO_INIT(A, 5, IN), + GPIO_INIT(D, 4, IN), + GPIO_INIT(E, 4, OUT0), + GPIO_INIT(G, 0, IN), + GPIO_INIT(H, 0, OUT0), + GPIO_INIT(H, 2, IN), + GPIO_INIT(H, 3, OUT0), + GPIO_INIT(H, 4, OUT0), + GPIO_INIT(H, 5, IN), + GPIO_INIT(I, 0, OUT0), + GPIO_INIT(I, 1, IN), + GPIO_INIT(V, 1, OUT0), + GPIO_INIT(V, 6, OUT1), + GPIO_INIT(X, 4, IN), + GPIO_INIT(X, 6, IN), + GPIO_INIT(X, 7, IN), + GPIO_INIT(Y, 1, IN), + GPIO_INIT(Z, 0, IN), + GPIO_INIT(Z, 4, OUT0), + GPIO_INIT(BB, 2, OUT0), + GPIO_INIT(CC, 1, IN), + GPIO_INIT(CC, 3, IN), }; #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \ diff --git a/board/nvidia/p2771-0000/Kconfig b/board/nvidia/p2771-0000/Kconfig new file mode 100644 index 0000000000..1b1116f020 --- /dev/null +++ b/board/nvidia/p2771-0000/Kconfig @@ -0,0 +1,16 @@ +# Copyright (c) 2016, NVIDIA CORPORATION. +# +# SPDX-License-Identifier: GPL-2.0 + +if TARGET_P2771_0000 + +config SYS_BOARD + default "p2771-0000" + +config SYS_VENDOR + default "nvidia" + +config SYS_CONFIG_NAME + default "p2771-0000" + +endif diff --git a/board/nvidia/p2771-0000/MAINTAINERS b/board/nvidia/p2771-0000/MAINTAINERS new file mode 100644 index 0000000000..4fc4ebd5e0 --- /dev/null +++ b/board/nvidia/p2771-0000/MAINTAINERS @@ -0,0 +1,6 @@ +P2771-0000 BOARD +M: Stephen Warren <swarren@nvidia.com> +S: Maintained +F: board/nvidia/p2771-0000/ +F: include/configs/p2771-0000.h +F: configs/p2771-0000_defconfig diff --git a/board/nvidia/p2771-0000/Makefile b/board/nvidia/p2771-0000/Makefile new file mode 100644 index 0000000000..b28a47d907 --- /dev/null +++ b/board/nvidia/p2771-0000/Makefile @@ -0,0 +1,5 @@ +# Copyright (c) 2016, NVIDIA CORPORATION. +# +# SPDX-License-Identifier: GPL-2.0 + +obj-y += p2771-0000.o diff --git a/board/nvidia/p2771-0000/p2771-0000.c b/board/nvidia/p2771-0000/p2771-0000.c new file mode 100644 index 0000000000..4ba8ebc0dc --- /dev/null +++ b/board/nvidia/p2771-0000/p2771-0000.c @@ -0,0 +1,7 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> diff --git a/board/nvidia/seaboard/seaboard.c b/board/nvidia/seaboard/seaboard.c index 2d07001800..fc9c1c9b34 100644 --- a/board/nvidia/seaboard/seaboard.c +++ b/board/nvidia/seaboard/seaboard.c @@ -20,8 +20,8 @@ void gpio_early_init_uart(void) { /* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */ - gpio_request(GPIO_PI3, "uart_en"); - gpio_direction_output(GPIO_PI3, 0); + gpio_request(TEGRA_GPIO(I, 3), "uart_en"); + gpio_direction_output(TEGRA_GPIO(I, 3), 0); } #endif diff --git a/board/nvidia/venice2/pinmux-config-venice2.h b/board/nvidia/venice2/pinmux-config-venice2.h index fb444b3b1d..59d53efe44 100644 --- a/board/nvidia/venice2/pinmux-config-venice2.h +++ b/board/nvidia/venice2/pinmux-config-venice2.h @@ -15,70 +15,70 @@ #ifndef _PINMUX_CONFIG_VENICE2_H_ #define _PINMUX_CONFIG_VENICE2_H_ -#define GPIO_INIT(_gpio, _init) \ +#define GPIO_INIT(_port, _gpio, _init) \ { \ - .gpio = GPIO_P##_gpio, \ + .gpio = TEGRA_GPIO(_port, _gpio), \ .init = TEGRA_GPIO_INIT_##_init, \ } static const struct tegra_gpio_config venice2_gpio_inits[] = { - /* gpio, init_val */ - GPIO_INIT(A0, IN), - GPIO_INIT(C7, IN), - GPIO_INIT(G0, IN), - GPIO_INIT(G1, IN), - GPIO_INIT(G2, IN), - GPIO_INIT(G3, IN), - GPIO_INIT(H2, IN), - GPIO_INIT(H4, IN), - GPIO_INIT(H5, OUT0), - GPIO_INIT(H6, IN), - GPIO_INIT(H7, OUT1), - GPIO_INIT(I0, IN), - GPIO_INIT(I1, IN), - GPIO_INIT(I2, OUT0), - GPIO_INIT(I4, OUT0), - GPIO_INIT(I5, OUT1), - GPIO_INIT(I6, IN), - GPIO_INIT(J0, IN), - GPIO_INIT(J7, IN), - GPIO_INIT(K0, IN), - GPIO_INIT(K1, OUT0), - GPIO_INIT(K2, IN), - GPIO_INIT(K3, IN), - GPIO_INIT(K4, OUT0), - GPIO_INIT(K6, OUT0), - GPIO_INIT(K7, IN), - GPIO_INIT(N7, IN), - GPIO_INIT(O2, IN), - GPIO_INIT(O5, IN), - GPIO_INIT(O6, OUT0), - GPIO_INIT(O7, IN), - GPIO_INIT(P2, OUT0), - GPIO_INIT(Q0, IN), - GPIO_INIT(Q2, IN), - GPIO_INIT(Q3, IN), - GPIO_INIT(Q6, IN), - GPIO_INIT(Q7, IN), - GPIO_INIT(R0, OUT0), - GPIO_INIT(R1, IN), - GPIO_INIT(R4, IN), - GPIO_INIT(S0, IN), - GPIO_INIT(S3, OUT0), - GPIO_INIT(S4, OUT0), - GPIO_INIT(S7, IN), - GPIO_INIT(T1, IN), - GPIO_INIT(U4, IN), - GPIO_INIT(U5, IN), - GPIO_INIT(U6, IN), - GPIO_INIT(V0, IN), - GPIO_INIT(V1, IN), - GPIO_INIT(W3, IN), - GPIO_INIT(X1, IN), - GPIO_INIT(X3, IN), - GPIO_INIT(X4, IN), - GPIO_INIT(X7, OUT0), - GPIO_INIT(CC5, OUT0), + /* port, pin, init_val */ + GPIO_INIT(A, 0, IN), + GPIO_INIT(C, 7, IN), + GPIO_INIT(G, 0, IN), + GPIO_INIT(G, 1, IN), + GPIO_INIT(G, 2, IN), + GPIO_INIT(G, 3, IN), + GPIO_INIT(H, 2, IN), + GPIO_INIT(H, 4, IN), + GPIO_INIT(H, 5, OUT0), + GPIO_INIT(H, 6, IN), + GPIO_INIT(H, 7, OUT1), + GPIO_INIT(I, 0, IN), + GPIO_INIT(I, 1, IN), + GPIO_INIT(I, 2, OUT0), + GPIO_INIT(I, 4, OUT0), + GPIO_INIT(I, 5, OUT1), + GPIO_INIT(I, 6, IN), + GPIO_INIT(J, 0, IN), + GPIO_INIT(J, 7, IN), + GPIO_INIT(K, 0, IN), + GPIO_INIT(K, 1, OUT0), + GPIO_INIT(K, 2, IN), + GPIO_INIT(K, 3, IN), + GPIO_INIT(K, 4, OUT0), + GPIO_INIT(K, 6, OUT0), + GPIO_INIT(K, 7, IN), + GPIO_INIT(N, 7, IN), + GPIO_INIT(O, 2, IN), + GPIO_INIT(O, 5, IN), + GPIO_INIT(O, 6, OUT0), + GPIO_INIT(O, 7, IN), + GPIO_INIT(P, 2, OUT0), + GPIO_INIT(Q, 0, IN), + GPIO_INIT(Q, 2, IN), + GPIO_INIT(Q, 3, IN), + GPIO_INIT(Q, 6, IN), + GPIO_INIT(Q, 7, IN), + GPIO_INIT(R, 0, OUT0), + GPIO_INIT(R, 1, IN), + GPIO_INIT(R, 4, IN), + GPIO_INIT(S, 0, IN), + GPIO_INIT(S, 3, OUT0), + GPIO_INIT(S, 4, OUT0), + GPIO_INIT(S, 7, IN), + GPIO_INIT(T, 1, IN), + GPIO_INIT(U, 4, IN), + GPIO_INIT(U, 5, IN), + GPIO_INIT(U, 6, IN), + GPIO_INIT(V, 0, IN), + GPIO_INIT(V, 1, IN), + GPIO_INIT(W, 3, IN), + GPIO_INIT(X, 1, IN), + GPIO_INIT(X, 3, IN), + GPIO_INIT(X, 4, IN), + GPIO_INIT(X, 7, OUT0), + GPIO_INIT(CC, 5, OUT0), }; #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \ diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c index 3cc01cb687..e2cb94ee13 100644 --- a/board/ronetix/pm9261/pm9261.c +++ b/board/ronetix/pm9261/pm9261.c @@ -194,7 +194,7 @@ void lcd_show_board_info(void) nand_size = 0; for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) - nand_size += nand_info[i].size; + nand_size += nand_info[i]->size; flash_size = 0; for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c index 276ff80943..e9f9b67b77 100644 --- a/board/ronetix/pm9263/pm9263.c +++ b/board/ronetix/pm9263/pm9263.c @@ -293,7 +293,7 @@ void lcd_show_board_info(void) nand_size = 0; for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) - nand_size += nand_info[i].size; + nand_size += nand_info[i]->size; flash_size = 0; for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) diff --git a/board/socrates/nand.c b/board/socrates/nand.c index 15e6ea6944..a67d812c81 100644 --- a/board/socrates/nand.c +++ b/board/socrates/nand.c @@ -48,7 +48,7 @@ static void sc_nand_write_byte(struct mtd_info *mtd, u_char byte) static void sc_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) { int i; - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); for (i = 0; i < len; i++) { out_be32(this->IO_ADDR_W, @@ -88,7 +88,7 @@ static u16 sc_nand_read_word(struct mtd_info *mtd) static void sc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) { int i; - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); int val; val = (state & FPGA_NAND_ENABLE) | FPGA_NAND_CMD_READ; @@ -105,7 +105,7 @@ static void sc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) */ static int sc_nand_device_ready(struct mtd_info *mtdinfo) { - struct nand_chip *this = mtdinfo->priv; + struct nand_chip *this = mtd_to_nand(mtdinfo); if (in_be32(this->IO_ADDR_W) & FPGA_NAND_BUSY) return 0; /* busy */ diff --git a/board/toradex/colibri_t20/colibri_t20.c b/board/toradex/colibri_t20/colibri_t20.c index 879f25a538..68fbf49579 100644 --- a/board/toradex/colibri_t20/colibri_t20.c +++ b/board/toradex/colibri_t20/colibri_t20.c @@ -103,11 +103,11 @@ void pin_mux_usb(void) pinmux_tristate_disable(PMUX_PINGRP_DTE); /* Reset ASIX using LAN_RESET */ - gpio_request(GPIO_PV4, "LAN_RESET"); - gpio_direction_output(GPIO_PV4, 0); + gpio_request(TEGRA_GPIO(V, 4), "LAN_RESET"); + gpio_direction_output(TEGRA_GPIO(V, 4), 0); pinmux_tristate_disable(PMUX_PINGRP_GPV); udelay(5); - gpio_set_value(GPIO_PV4, 1); + gpio_set_value(TEGRA_GPIO(V, 4), 1); /* USBH_PEN: USB 1 aka Tegra USB port 3 VBus */ pinmux_tristate_disable(PMUX_PINGRP_SPIG); diff --git a/board/toradex/colibri_t30/colibri_t30.c b/board/toradex/colibri_t30/colibri_t30.c index 44b5beb928..e32362a93a 100644 --- a/board/toradex/colibri_t30/colibri_t30.c +++ b/board/toradex/colibri_t30/colibri_t30.c @@ -47,8 +47,8 @@ void pinmux_init(void) void pin_mux_usb(void) { /* Reset ASIX using LAN_RESET */ - gpio_request(GPIO_PDD0, "LAN_RESET"); - gpio_direction_output(GPIO_PDD0, 0); + gpio_request(TEGRA_GPIO(DD, 0), "LAN_RESET"); + gpio_direction_output(TEGRA_GPIO(DD, 0), 0); udelay(5); - gpio_set_value(GPIO_PDD0, 1); + gpio_set_value(TEGRA_GPIO(DD, 0), 1); } diff --git a/board/xes/common/actl_nand.c b/board/xes/common/actl_nand.c index bf896fe0ce..d1f3668bcb 100644 --- a/board/xes/common/actl_nand.c +++ b/board/xes/common/actl_nand.c @@ -16,7 +16,7 @@ */ static void nand_addr_hwcontrol(struct mtd_info *mtd, int cmd, uint ctrl) { - struct nand_chip *this = mtd->priv; + struct nand_chip *this = mtd_to_nand(mtd); ulong IO_ADDR_W; if (ctrl & NAND_CTRL_CHANGE) { |