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-rw-r--r--board/amcc/bamboo/bamboo.c61
-rw-r--r--board/amcc/canyonlands/canyonlands.c37
-rw-r--r--board/amcc/ebony/ebony.c39
-rw-r--r--board/amcc/katmai/katmai.c40
-rw-r--r--board/amcc/luan/luan.c40
-rw-r--r--board/amcc/ocotea/ocotea.c40
-rw-r--r--board/amcc/sequoia/sequoia.c65
-rw-r--r--board/amcc/taishan/taishan.c39
-rw-r--r--board/amcc/yosemite/yosemite.c61
-rw-r--r--board/amcc/yucca/yucca.c38
-rw-r--r--board/esd/du440/du440.c67
-rw-r--r--board/esd/du440/du440.h3
-rw-r--r--board/gdsys/gdppc440etx/gdppc440etx.c63
-rw-r--r--board/gdsys/intip/intip.c37
-rw-r--r--board/korat/korat.c57
-rw-r--r--board/lwmon5/lwmon5.c61
-rw-r--r--board/netstal/hcu5/hcu5.c65
-rw-r--r--board/pcs440ep/pcs440ep.c61
-rw-r--r--board/prodrive/alpr/alpr.c39
-rw-r--r--board/prodrive/p3p440/p3p440.c39
-rw-r--r--board/sandburst/common/sb_common.c40
-rw-r--r--board/xes/xpedite1000/xpedite1000.c32
22 files changed, 4 insertions, 1020 deletions
diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c
index 313f9f36a6..3ffdac8bd5 100644
--- a/board/amcc/bamboo/bamboo.c
+++ b/board/amcc/bamboo/bamboo.c
@@ -522,67 +522,6 @@ int pci_pre_init(struct pci_controller *hose)
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller *hose)
-{
- /*--------------------------------------------------------------------------+
- * Set up Direct MMIO registers
- *--------------------------------------------------------------------------*/
- /*--------------------------------------------------------------------------+
- | PowerPC440 EP PCI Master configuration.
- | Map one 1Gig range of PLB/processor addresses to PCI memory space.
- | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
- | Use byte reversed out routines to handle endianess.
- | Make this region non-prefetchable.
- +--------------------------------------------------------------------------*/
- out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
- out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
- out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
- out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
-
- out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
- out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
- out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
- out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
-
- out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
- out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */
- out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */
- out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */
-
- /*--------------------------------------------------------------------------+
- * Set up Configuration registers
- *--------------------------------------------------------------------------*/
-
- /* Program the board's subsystem id/vendor id */
- pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
- CONFIG_SYS_PCI_SUBSYS_VENDORID);
- pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
-
- /* Configure command register as bus master */
- pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
-
- /* 240nS PCI clock */
- pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
-
- /* No error reporting */
- pci_write_config_word(0, PCI_ERREN, 0);
-
- pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
-
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
-/*************************************************************************
* pci_master_init
*
************************************************************************/
diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c
index 9a8ca8ecea..13a0daced7 100644
--- a/board/amcc/canyonlands/canyonlands.c
+++ b/board/amcc/canyonlands/canyonlands.c
@@ -326,43 +326,6 @@ phys_size_t initdram(int board_type)
}
#endif
-/*
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- */
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller * hose )
-{
- /*
- * Disable everything
- */
- out_le32((void *)PCIL0_PIM0SA, 0); /* disable */
- out_le32((void *)PCIL0_PIM1SA, 0); /* disable */
- out_le32((void *)PCIL0_PIM2SA, 0); /* disable */
- out_le32((void *)PCIL0_EROMBA, 0); /* disable expansion rom */
-
- /*
- * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
- * strapping options to not support sizes such as 128/256 MB.
- */
- out_le32((void *)PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
- out_le32((void *)PCIL0_PIM0LAH, 0);
- out_le32((void *)PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
- out_le32((void *)PCIL0_BAR0, 0);
-
- /*
- * Program the board's subsystem id/vendor id
- */
- out_le16((void *)PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
- out_le16((void *)PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
-
- out_le16((void *)PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY);
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
#if defined(CONFIG_PCI)
int board_pcie_first(void)
{
diff --git a/board/amcc/ebony/ebony.c b/board/amcc/ebony/ebony.c
index 1524b5333a..e4d168f9d8 100644
--- a/board/amcc/ebony/ebony.c
+++ b/board/amcc/ebony/ebony.c
@@ -195,42 +195,3 @@ int pci_pre_init(struct pci_controller *hose)
return 1;
}
#endif /* defined(CONFIG_PCI) */
-
-/*************************************************************************
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller *hose)
-{
- /*--------------------------------------------------------------------------+
- * Disable everything
- *--------------------------------------------------------------------------*/
- out32r(PCIL0_PIM0SA, 0); /* disable */
- out32r(PCIL0_PIM1SA, 0); /* disable */
- out32r(PCIL0_PIM2SA, 0); /* disable */
- out32r(PCIL0_EROMBA, 0); /* disable expansion rom */
-
- /*--------------------------------------------------------------------------+
- * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
- * options to not support sizes such as 128/256 MB.
- *--------------------------------------------------------------------------*/
- out32r(PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
- out32r(PCIL0_PIM0LAH, 0);
- out32r(PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
-
- out32r(PCIL0_BAR0, 0);
-
- /*--------------------------------------------------------------------------+
- * Program the board's subsystem id/vendor id
- *--------------------------------------------------------------------------*/
- out16r(PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
- out16r(PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
-
- out16r(PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY);
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c
index f43e76448b..f0b48c0d32 100644
--- a/board/amcc/katmai/katmai.c
+++ b/board/amcc/katmai/katmai.c
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2007-2008
+ * (C) Copyright 2007-2009
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
@@ -291,44 +291,6 @@ int pci_pre_init(struct pci_controller * hose )
}
#endif /* defined(CONFIG_PCI) */
-/*************************************************************************
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller * hose )
-{
- /*-------------------------------------------------------------------+
- * Disable everything
- *-------------------------------------------------------------------*/
- out32r( PCIL0_PIM0SA, 0 ); /* disable */
- out32r( PCIL0_PIM1SA, 0 ); /* disable */
- out32r( PCIL0_PIM2SA, 0 ); /* disable */
- out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
-
- /*-------------------------------------------------------------------+
- * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
- * strapping options to not support sizes such as 128/256 MB.
- *-------------------------------------------------------------------*/
- out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
- out32r( PCIL0_PIM0LAH, 0 );
- out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
- out32r( PCIL0_BAR0, 0 );
-
- /*-------------------------------------------------------------------+
- * Program the board's subsystem id/vendor id
- *-------------------------------------------------------------------*/
- out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
- out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
-
- out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
#if defined(CONFIG_PCI)
int board_pcie_card_present(int port)
{
diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c
index 94ba6437f6..e0b297e707 100644
--- a/board/amcc/luan/luan.c
+++ b/board/amcc/luan/luan.c
@@ -160,46 +160,6 @@ int pci_pre_init( struct pci_controller *hose )
/*************************************************************************
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller *hose)
-{
- /*--------------------------------------------------------------------------+
- * Disable everything
- *--------------------------------------------------------------------------*/
- out32r( PCIL0_PIM0SA, 0 ); /* disable */
- out32r( PCIL0_PIM1SA, 0 ); /* disable */
- out32r( PCIL0_PIM2SA, 0 ); /* disable */
- out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
-
- /*--------------------------------------------------------------------------+
- * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
- * options to not support sizes such as 128/256 MB.
- *--------------------------------------------------------------------------*/
- out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
- out32r( PCIL0_PIM0LAH, 0 );
- out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
-
- out32r( PCIL0_BAR0, 0 );
-
- /*--------------------------------------------------------------------------+
- * Program the board's subsystem id/vendor id
- *--------------------------------------------------------------------------*/
- out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
- out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
-
- out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
-
-/*************************************************************************
* hw_watchdog_reset
*
* This routine is called to reset (keep alive) the watchdog timer
diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c
index 2f64764ee2..b38f3cc400 100644
--- a/board/amcc/ocotea/ocotea.c
+++ b/board/amcc/ocotea/ocotea.c
@@ -307,46 +307,6 @@ int pci_pre_init(struct pci_controller * hose )
}
#endif /* defined(CONFIG_PCI) */
-/*************************************************************************
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller * hose )
-{
- /*--------------------------------------------------------------------------+
- * Disable everything
- *--------------------------------------------------------------------------*/
- out32r( PCIL0_PIM0SA, 0 ); /* disable */
- out32r( PCIL0_PIM1SA, 0 ); /* disable */
- out32r( PCIL0_PIM2SA, 0 ); /* disable */
- out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
-
- /*--------------------------------------------------------------------------+
- * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
- * options to not support sizes such as 128/256 MB.
- *--------------------------------------------------------------------------*/
- out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
- out32r( PCIL0_PIM0LAH, 0 );
- out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
-
- out32r( PCIL0_BAR0, 0 );
-
- /*--------------------------------------------------------------------------+
- * Program the board's subsystem id/vendor id
- *--------------------------------------------------------------------------*/
- out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
- out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
-
- out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
-
void fpga_init(void)
{
unsigned long group;
diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index 4393820061..b8ef4e7633 100644
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -427,71 +427,6 @@ int pci_pre_init(struct pci_controller *hose)
}
#endif /* defined(CONFIG_PCI) */
-/*
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- */
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller *hose)
-{
- /*
- * Set up Direct MMIO registers
- */
- /*
- * PowerPC440EPX PCI Master configuration.
- * Map one 1Gig range of PLB/processor addresses to PCI memory space.
- * PLB address 0xA0000000-0xDFFFFFFF
- * ==> PCI address 0xA0000000-0xDFFFFFFF
- * Use byte reversed out routines to handle endianess.
- * Make this region non-prefetchable.
- */
- out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
- /* - disabled b4 setting */
- out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
- out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
- out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */
- /* and enable region */
-
- out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */
- /* - disabled b4 setting */
- out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
- out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
- out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */
- /* and enable region */
-
- out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
- out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */
- out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */
- out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */
-
- /*
- * Set up Configuration registers
- */
-
- /* Program the board's subsystem id/vendor id */
- pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
- CONFIG_SYS_PCI_SUBSYS_VENDORID);
- pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
-
- /* Configure command register as bus master */
- pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
-
- /* 240nS PCI clock */
- pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
-
- /* No error reporting */
- pci_write_config_word(0, PCI_ERREN, 0);
-
- pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
-
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
void pci_master_init(struct pci_controller *hose)
{
diff --git a/board/amcc/taishan/taishan.c b/board/amcc/taishan/taishan.c
index 81e8fe14ab..574ff1a7bc 100644
--- a/board/amcc/taishan/taishan.c
+++ b/board/amcc/taishan/taishan.c
@@ -240,45 +240,6 @@ int pci_pre_init(struct pci_controller * hose )
}
#endif /* defined(CONFIG_PCI) */
-/*************************************************************************
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller * hose )
-{
- /*--------------------------------------------------------------------------+
- * Disable everything
- *--------------------------------------------------------------------------*/
- out32r( PCIL0_PIM0SA, 0 ); /* disable */
- out32r( PCIL0_PIM1SA, 0 ); /* disable */
- out32r( PCIL0_PIM2SA, 0 ); /* disable */
- out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
-
- /*--------------------------------------------------------------------------+
- * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
- * options to not support sizes such as 128/256 MB.
- *--------------------------------------------------------------------------*/
- out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
- out32r( PCIL0_PIM0LAH, 0 );
- out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
-
- out32r( PCIL0_BAR0, 0 );
-
- /*--------------------------------------------------------------------------+
- * Program the board's subsystem id/vendor id
- *--------------------------------------------------------------------------*/
- out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
- out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
-
- out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
#ifdef CONFIG_POST
/*
* Returns 1 if keys pressed to start the power-on long-running tests
diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c
index e416eeb167..cd14a6a487 100644
--- a/board/amcc/yosemite/yosemite.c
+++ b/board/amcc/yosemite/yosemite.c
@@ -408,67 +408,6 @@ int pci_pre_init(struct pci_controller *hose)
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller *hose)
-{
- /*--------------------------------------------------------------------------+
- * Set up Direct MMIO registers
- *--------------------------------------------------------------------------*/
- /*--------------------------------------------------------------------------+
- | PowerPC440 EP PCI Master configuration.
- | Map one 1Gig range of PLB/processor addresses to PCI memory space.
- | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
- | Use byte reversed out routines to handle endianess.
- | Make this region non-prefetchable.
- +--------------------------------------------------------------------------*/
- out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
- out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
- out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
- out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
-
- out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
- out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
- out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
- out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
-
- out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
- out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */
- out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */
- out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */
-
- /*--------------------------------------------------------------------------+
- * Set up Configuration registers
- *--------------------------------------------------------------------------*/
-
- /* Program the board's subsystem id/vendor id */
- pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
- CONFIG_SYS_PCI_SUBSYS_VENDORID);
- pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
-
- /* Configure command register as bus master */
- pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
-
- /* 240nS PCI clock */
- pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
-
- /* No error reporting */
- pci_write_config_word(0, PCI_ERREN, 0);
-
- pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
-
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
-/*************************************************************************
* pci_master_init
*
************************************************************************/
diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c
index 7315033dc8..0ec26f14d1 100644
--- a/board/amcc/yucca/yucca.c
+++ b/board/amcc/yucca/yucca.c
@@ -619,44 +619,6 @@ int pci_pre_init(struct pci_controller * hose )
}
#endif /* defined(CONFIG_PCI) */
-/*************************************************************************
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller * hose )
-{
- /*-------------------------------------------------------------------+
- * Disable everything
- *-------------------------------------------------------------------*/
- out32r( PCIL0_PIM0SA, 0 ); /* disable */
- out32r( PCIL0_PIM1SA, 0 ); /* disable */
- out32r( PCIL0_PIM2SA, 0 ); /* disable */
- out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
-
- /*-------------------------------------------------------------------+
- * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
- * strapping options to not support sizes such as 128/256 MB.
- *-------------------------------------------------------------------*/
- out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
- out32r( PCIL0_PIM0LAH, 0 );
- out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
- out32r( PCIL0_BAR0, 0 );
-
- /*-------------------------------------------------------------------+
- * Program the board's subsystem id/vendor id
- *-------------------------------------------------------------------*/
- out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
- out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
-
- out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
#if defined(CONFIG_PCI)
int board_pcie_card_present(int port)
{
diff --git a/board/esd/du440/du440.c b/board/esd/du440/du440.c
index 8f9f9500e2..866dcafcfa 100644
--- a/board/esd/du440/du440.c
+++ b/board/esd/du440/du440.c
@@ -414,73 +414,6 @@ int pci_pre_init(struct pci_controller *hose)
}
#endif /* defined(CONFIG_PCI) */
-/*
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- */
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller *hose)
-{
- /*
- * Set up Direct MMIO registers
- */
- /*
- * PowerPC440EPX PCI Master configuration.
- * Map one 1Gig range of PLB/processor addresses to PCI memory space.
- * PLB address 0xA0000000-0xDFFFFFFF
- * ==> PCI address 0xA0000000-0xDFFFFFFF
- * Use byte reversed out routines to handle endianess.
- * Make this region non-prefetchable.
- */
- out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
- /* - disabled b4 setting */
- out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
- out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
- out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */
- /* and enable region */
-
- out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */
- /* - disabled b4 setting */
- out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
- out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
- out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */
- /* and enable region */
-
- out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
- out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */
- out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */
- out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */
-
- /*
- * Set up Configuration registers
- */
-
- /* Program the board's subsystem id/vendor id */
- pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
- PCI_VENDOR_ID_ESDGMBH);
- pci_write_config_word(0, PCI_SUBSYSTEM_ID, PCI_DEVICE_ID_DU440);
-
- pci_write_config_word(0, PCI_CLASS_SUB_CODE, PCI_CLASS_BRIDGE_HOST);
-
- /* Configure command register as bus master */
- pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
-
- /* 240nS PCI clock */
- pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
-
- /* No error reporting */
- pci_write_config_word(0, PCI_ERREN, 0);
-
- pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
-
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
void pci_master_init(struct pci_controller *hose)
{
diff --git a/board/esd/du440/du440.h b/board/esd/du440/du440.h
index a124a7ee9b..37697ec854 100644
--- a/board/esd/du440/du440.h
+++ b/board/esd/du440/du440.h
@@ -38,6 +38,3 @@
#define PWR_RDY 0x10
#define CPLD_IRQ (32+30)
-
-#define PCI_VENDOR_ID_ESDGMBH 0x12fe
-#define PCI_DEVICE_ID_DU440 0x0444
diff --git a/board/gdsys/gdppc440etx/gdppc440etx.c b/board/gdsys/gdppc440etx/gdppc440etx.c
index 92f5d822f6..b93a420154 100644
--- a/board/gdsys/gdppc440etx/gdppc440etx.c
+++ b/board/gdsys/gdppc440etx/gdppc440etx.c
@@ -217,69 +217,6 @@ int pci_pre_init(struct pci_controller *hose)
#endif /* defined(CONFIG_PCI) */
/*
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- *
- */
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller *hose)
-{
- /*
- * Set up Direct MMIO registers
- */
-
- /*
- * PowerPC440 EP PCI Master configuration.
- * Map one 1Gig range of PLB/processor addresses to PCI memory space.
- * PLB address 0xA0000000-0xDFFFFFFF
- * ==> PCI address 0xA0000000-0xDFFFFFFF
- * Use byte reversed out routines to handle endianess.
- * Make this region non-prefetchable.
- */
- out32r(PCIL0_PMM0MA, 0x00000000); /* disabled b4 setting */
- out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);
- out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);
- out32r(PCIL0_PMM0PCIHA, 0x00000000);
- out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M, no prefetch, enable region */
-
- out32r(PCIL0_PMM1MA, 0x00000000); /* disabled b4 setting */
- out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);
- out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);
- out32r(PCIL0_PMM1PCIHA, 0x00000000);
- out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M, no prefetch, enable region */
-
- out32r(PCIL0_PTM1MS, 0x00000001);
- out32r(PCIL0_PTM1LA, 0);
- out32r(PCIL0_PTM2MS, 0);
- out32r(PCIL0_PTM2LA, 0);
-
- /*
- * Set up Configuration registers
- */
-
- /* Program the board's subsystem id/vendor id */
- pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
- CONFIG_SYS_PCI_SUBSYS_VENDORID);
- pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
-
- /* Configure command register as bus master */
- pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
-
- /* 240nS PCI clock */
- pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
-
- /* No error reporting */
- pci_write_config_word(0, PCI_ERREN, 0);
-
- pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
-
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
-/*
* pci_master_init
*
*/
diff --git a/board/gdsys/intip/intip.c b/board/gdsys/intip/intip.c
index 49d2451358..23a10c41f9 100644
--- a/board/gdsys/intip/intip.c
+++ b/board/gdsys/intip/intip.c
@@ -141,43 +141,6 @@ int checkboard(void)
return 0;
}
-/*
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- */
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller *hose)
-{
- /*
- * Disable everything
- */
- out_le32((void *)PCIL0_PIM0SA, 0); /* disable */
- out_le32((void *)PCIL0_PIM1SA, 0); /* disable */
- out_le32((void *)PCIL0_PIM2SA, 0); /* disable */
- out_le32((void *)PCIL0_EROMBA, 0); /* disable expansion rom */
-
- /*
- * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
- * strapping options to not support sizes such as 128/256 MB.
- */
- out_le32((void *)PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
- out_le32((void *)PCIL0_PIM0LAH, 0);
- out_le32((void *)PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
- out_le32((void *)PCIL0_BAR0, 0);
-
- /*
- * Program the board's subsystem id/vendor id
- */
- out_le16((void *)PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
- out_le16((void *)PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
-
- out_le16((void *)PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY);
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
int board_early_init_r(void)
{
/*
diff --git a/board/korat/korat.c b/board/korat/korat.c
index b0e6a56a63..02ebfdf371 100644
--- a/board/korat/korat.c
+++ b/board/korat/korat.c
@@ -35,6 +35,7 @@
#include <asm/io.h>
#include <asm/ppc4xx-uic.h>
#include <asm/processor.h>
+#include <asm/4xx_pci.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -668,60 +669,8 @@ int pci_pre_init(struct pci_controller *hose)
#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller *hose)
{
- /*
- * Set up Direct MMIO registers
- */
- /*
- * PowerPC440EPX PCI Master configuration.
- * Map one 1Gig range of PLB/processor addresses to PCI memory space.
- * PLB address 0x80000000-0xBFFFFFFF
- * ==> PCI address 0x80000000-0xBFFFFFFF
- * Use byte reversed out routines to handle endianess.
- * Make this region non-prefetchable.
- */
- out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */
- /* - disabled b4 setting */
- out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
- out32r(PCIL0_PMM0PCILA,
- CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
- out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */
- /* and enable region */
-
- out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */
- /* - disabled b4 setting */
- out32r(PCIL0_PMM1LA,
- CONFIG_SYS_PCI_MEMBASE + 0x20000000); /* PMM0 Local Address */
- out32r(PCIL0_PMM1PCILA,
- CONFIG_SYS_PCI_MEMBASE + 0x20000000); /* PMM0 PCI Low Address */
- out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */
- /* and enable region */
-
- out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
- out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */
- out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */
- out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */
-
- /*
- * Set up Configuration registers
- */
-
- /* Program the board's subsystem id/vendor id */
- pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
- CONFIG_SYS_PCI_SUBSYS_VENDORID);
- pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
-
- /* Configure command register as bus master */
- pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
-
- /* 240nS PCI clock */
- pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
-
- /* No error reporting */
- pci_write_config_word(0, PCI_ERREN, 0);
-
- pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
+ /* First do 440EP(x) common setup */
+ __pci_target_init(hose);
/*
* Set up Configuration registers for on-board NEC uPD720101 USB
diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c
index 09ba2b933d..77f2d7f688 100644
--- a/board/lwmon5/lwmon5.c
+++ b/board/lwmon5/lwmon5.c
@@ -331,67 +331,6 @@ int pci_pre_init(struct pci_controller *hose)
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller *hose)
-{
- /*--------------------------------------------------------------------------+
- * Set up Direct MMIO registers
- *--------------------------------------------------------------------------*/
- /*--------------------------------------------------------------------------+
- | PowerPC440EPX PCI Master configuration.
- | Map one 1Gig range of PLB/processor addresses to PCI memory space.
- | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
- | Use byte reversed out routines to handle endianess.
- | Make this region non-prefetchable.
- +--------------------------------------------------------------------------*/
- out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
- out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
- out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
- out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
-
- out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
- out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
- out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
- out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
-
- out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
- out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */
- out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */
- out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */
-
- /*--------------------------------------------------------------------------+
- * Set up Configuration registers
- *--------------------------------------------------------------------------*/
-
- /* Program the board's subsystem id/vendor id */
- pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
- CONFIG_SYS_PCI_SUBSYS_VENDORID);
- pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
-
- /* Configure command register as bus master */
- pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
-
- /* 240nS PCI clock */
- pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
-
- /* No error reporting */
- pci_write_config_word(0, PCI_ERREN, 0);
-
- pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
-
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
-/*************************************************************************
* pci_master_init
*
************************************************************************/
diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c
index 7ffc262024..144fdd9704 100644
--- a/board/netstal/hcu5/hcu5.c
+++ b/board/netstal/hcu5/hcu5.c
@@ -377,71 +377,6 @@ int pci_pre_init(struct pci_controller *hose)
}
/*
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- *
- */
-void pci_target_init(struct pci_controller *hose)
-{
- if (!board_with_pci()) { return; }
- /*
- * Set up Direct MMIO registers
- *
- * PowerPC440EPX PCI Master configuration.
- * Map one 1Gig range of PLB/processor addresses to PCI memory space.
- * PLB address 0xA0000000-0xDFFFFFFF ==> PCI address
- * 0xA0000000-0xDFFFFFFF
- * Use byte reversed out routines to handle endianess.
- * Make this region non-prefetchable.
- */
- /* PMM0 Mask/Attribute - disabled b4 setting */
- out32r(PCIL0_PMM0MA, 0x00000000);
- out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
- /* PMM0 PCI Low Address */
- out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);
- out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
- /* 512M + No prefetching, and enable region */
- out32r(PCIL0_PMM0MA, 0xE0000001);
-
- /* PMM0 Mask/Attribute - disabled b4 setting */
- out32r(PCIL0_PMM1MA, 0x00000000);
- out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
- /* PMM0 PCI Low Address */
- out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);
- out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
- /* 512M + No prefetching, and enable region */
- out32r(PCIL0_PMM1MA, 0xE0000001);
-
- out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
- out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */
- out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */
- out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */
-
- /*
- * Set up Configuration registers
- */
-
- /* Program the board's subsystem id/vendor id */
- pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
- CONFIG_SYS_PCI_SUBSYS_VENDORID);
- pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
-
- /* Configure command register as bus master */
- pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
-
- /* 240nS PCI clock */
- pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
-
- /* No error reporting */
- pci_write_config_word(0, PCI_ERREN, 0);
-
- pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
-}
-
-/*
* pci_master_init
*
*/
diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c
index 2155711d6f..929375987c 100644
--- a/board/pcs440ep/pcs440ep.c
+++ b/board/pcs440ep/pcs440ep.c
@@ -606,67 +606,6 @@ int pci_pre_init(struct pci_controller *hose)
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller *hose)
-{
- /*--------------------------------------------------------------------------+
- * Set up Direct MMIO registers
- *--------------------------------------------------------------------------*/
- /*--------------------------------------------------------------------------+
- | PowerPC440 EP PCI Master configuration.
- | Map one 1Gig range of PLB/processor addresses to PCI memory space.
- | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
- | Use byte reversed out routines to handle endianess.
- | Make this region non-prefetchable.
- +--------------------------------------------------------------------------*/
- out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
- out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */
- out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
- out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
-
- out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
- out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
- out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
- out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
- out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
-
- out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
- out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */
- out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */
- out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */
-
- /*--------------------------------------------------------------------------+
- * Set up Configuration registers
- *--------------------------------------------------------------------------*/
-
- /* Program the board's subsystem id/vendor id */
- pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
- CONFIG_SYS_PCI_SUBSYS_VENDORID);
- pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
-
- /* Configure command register as bus master */
- pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
-
- /* 240nS PCI clock */
- pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
-
- /* No error reporting */
- pci_write_config_word(0, PCI_ERREN, 0);
-
- pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
-
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
-/*************************************************************************
* pci_master_init
*
************************************************************************/
diff --git a/board/prodrive/alpr/alpr.c b/board/prodrive/alpr/alpr.c
index e9e2bf3e0b..c06aadb414 100644
--- a/board/prodrive/alpr/alpr.c
+++ b/board/prodrive/alpr/alpr.c
@@ -179,45 +179,6 @@ int pci_pre_init(struct pci_controller * hose )
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller * hose )
-{
- /*--------------------------------------------------------------------------+
- * Disable everything
- *--------------------------------------------------------------------------*/
- out32r( PCIL0_PIM0SA, 0 ); /* disable */
- out32r( PCIL0_PIM1SA, 0 ); /* disable */
- out32r( PCIL0_PIM2SA, 0 ); /* disable */
- out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
-
- /*--------------------------------------------------------------------------+
- * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
- * options to not support sizes such as 128/256 MB.
- *--------------------------------------------------------------------------*/
- out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
- out32r( PCIL0_PIM0LAH, 0 );
- out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
-
- out32r( PCIL0_BAR0, 0 );
-
- /*--------------------------------------------------------------------------+
- * Program the board's subsystem id/vendor id
- *--------------------------------------------------------------------------*/
- out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
- out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
-
- out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
-/*************************************************************************
* Override weak is_pci_host()
*
* This routine is called to determine if a pci scan should be
diff --git a/board/prodrive/p3p440/p3p440.c b/board/prodrive/p3p440/p3p440.c
index e07400794b..5761e70845 100644
--- a/board/prodrive/p3p440/p3p440.c
+++ b/board/prodrive/p3p440/p3p440.c
@@ -196,45 +196,6 @@ int pci_pre_init(struct pci_controller *hose)
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller *hose)
-{
- /*--------------------------------------------------------------------------+
- * Disable everything
- *--------------------------------------------------------------------------*/
- out32r(PCIL0_PIM0SA, 0); /* disable */
- out32r(PCIL0_PIM1SA, 0); /* disable */
- out32r(PCIL0_PIM2SA, 0); /* disable */
- out32r(PCIL0_EROMBA, 0); /* disable expansion rom */
-
- /*--------------------------------------------------------------------------+
- * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
- * options to not support sizes such as 128/256 MB.
- *--------------------------------------------------------------------------*/
- out32r(PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
- out32r(PCIL0_PIM0LAH, 0);
- out32r(PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
-
- out32r(PCIL0_BAR0, 0);
-
- /*--------------------------------------------------------------------------+
- * Program the board's subsystem id/vendor id
- *--------------------------------------------------------------------------*/
- out16r(PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
- out16r(PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
-
- out16r(PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY);
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
-/*************************************************************************
* Override weak is_pci_host()
*
* This routine is called to determine if a pci scan should be
diff --git a/board/sandburst/common/sb_common.c b/board/sandburst/common/sb_common.c
index 5749084583..45e9043851 100644
--- a/board/sandburst/common/sb_common.c
+++ b/board/sandburst/common/sb_common.c
@@ -333,46 +333,6 @@ int pci_pre_init(struct pci_controller * hose )
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller * hose )
-{
- /*--------------------------------------------------------------------------+
- * Disable everything
- *--------------------------------------------------------------------------*/
- out32r( PCIL0_PIM0SA, 0 ); /* disable */
- out32r( PCIL0_PIM1SA, 0 ); /* disable */
- out32r( PCIL0_PIM2SA, 0 ); /* disable */
- out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */
-
- /*--------------------------------------------------------------------------+
- * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
- * options to not support sizes such as 128/256 MB.
- *--------------------------------------------------------------------------*/
- out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
- out32r( PCIL0_PIM0LAH, 0 );
- out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 );
-
- out32r( PCIL0_BAR0, 0 );
-
- /*--------------------------------------------------------------------------+
- * Program the board's subsystem id/vendor id
- *--------------------------------------------------------------------------*/
- out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
- out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
-
- out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY );
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
-
-/*************************************************************************
* board_get_enetaddr
*
* Get the ethernet MAC address for the management ethernet from the
diff --git a/board/xes/xpedite1000/xpedite1000.c b/board/xes/xpedite1000/xpedite1000.c
index 0c4cf9463f..db37ca0516 100644
--- a/board/xes/xpedite1000/xpedite1000.c
+++ b/board/xes/xpedite1000/xpedite1000.c
@@ -166,38 +166,6 @@ int pci_pre_init(struct pci_controller * hose)
}
#endif /* defined(CONFIG_PCI) */
-#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
-/*
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- */
-void pci_target_init(struct pci_controller * hose)
-{
- /* Disable everything */
- out32r(PCIL0_PIM0SA, 0);
- out32r(PCIL0_PIM1SA, 0);
- out32r(PCIL0_PIM2SA, 0);
- out32r(PCIL0_EROMBA, 0); /* disable expansion rom */
-
- /*
- * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
- * options to not support sizes such as 128/256 MB.
- */
- out32r(PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
- out32r(PCIL0_PIM0LAH, 0);
- out32r(PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
-
- out32r(PCIL0_BAR0, 0);
-
- /* Program the board's subsystem id/vendor id */
- out16r(PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
- out16r(PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
-
- out16r(PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY);
-}
-#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
-
#if defined(CONFIG_PCI)
/*
* Override weak is_pci_host()