diff options
Diffstat (limited to 'board')
82 files changed, 1403 insertions, 582 deletions
diff --git a/board/armadeus/opos6uldev/board.c b/board/armadeus/opos6uldev/board.c index a830dc326d1..0679acd832a 100644 --- a/board/armadeus/opos6uldev/board.c +++ b/board/armadeus/opos6uldev/board.c @@ -12,8 +12,6 @@ #include <asm/io.h> #include <common.h> -DECLARE_GLOBAL_DATA_PTR; - #ifdef CONFIG_VIDEO_MXS #define LCD_PAD_CTRL ( \ PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ diff --git a/board/astro/mcf5373l/fpga.c b/board/astro/mcf5373l/fpga.c index 53e00728c3d..72b93ac1e58 100644 --- a/board/astro/mcf5373l/fpga.c +++ b/board/astro/mcf5373l/fpga.c @@ -25,8 +25,6 @@ #include <asm/io.h> #include "fpga.h" -DECLARE_GLOBAL_DATA_PTR; - int altera_pre_fn(int cookie) { gpio_t *gpiop = (gpio_t *)MMAP_GPIO; diff --git a/board/bachmann/ot1200/ot1200_spl.c b/board/bachmann/ot1200/ot1200_spl.c index f3dff95710a..dd1ade78779 100644 --- a/board/bachmann/ot1200/ot1200_spl.c +++ b/board/bachmann/ot1200/ot1200_spl.c @@ -8,8 +8,6 @@ #include <spl.h> #include <asm/arch/mx6-ddr.h> -DECLARE_GLOBAL_DATA_PTR; - /* Configure MX6Q/DUAL mmdc DDR io registers */ static struct mx6dq_iomux_ddr_regs ot1200_ddr_ioregs = { /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 48ohm */ diff --git a/board/barco/platinum/spl_picon.c b/board/barco/platinum/spl_picon.c index f49adf03296..0f6ff3a38f7 100644 --- a/board/barco/platinum/spl_picon.c +++ b/board/barco/platinum/spl_picon.c @@ -21,8 +21,6 @@ #include "platinum.h" -DECLARE_GLOBAL_DATA_PTR; - #undef RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */ /* Configure MX6Q/DUAL mmdc DDR io registers */ diff --git a/board/barco/platinum/spl_titanium.c b/board/barco/platinum/spl_titanium.c index c27fb4836a1..7af890a902e 100644 --- a/board/barco/platinum/spl_titanium.c +++ b/board/barco/platinum/spl_titanium.c @@ -21,8 +21,6 @@ #include "platinum.h" -DECLARE_GLOBAL_DATA_PTR; - #undef RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */ /* Configure MX6Q/DUAL mmdc DDR io registers */ diff --git a/board/cavium/thunderx/atf.c b/board/cavium/thunderx/atf.c index 6ab9de944f2..51b4a9fa277 100644 --- a/board/cavium/thunderx/atf.c +++ b/board/cavium/thunderx/atf.c @@ -16,8 +16,6 @@ #include <malloc.h> -DECLARE_GLOBAL_DATA_PTR; - ssize_t atf_read_mmc(uintptr_t offset, void *buffer, size_t size) { struct pt_regs regs; diff --git a/board/cei/cei-tk1-som/cei-tk1-som.c b/board/cei/cei-tk1-som/cei-tk1-som.c index 7c87bd1eb11..c2e27b7b675 100644 --- a/board/cei/cei-tk1-som/cei-tk1-som.c +++ b/board/cei/cei-tk1-som/cei-tk1-som.c @@ -13,8 +13,6 @@ #include "pinmux-config-cei-tk1-som.h" -DECLARE_GLOBAL_DATA_PTR; - /* * Routine: pinmux_init * Description: Do individual peripheral pinmux configs diff --git a/board/compulab/cm_fx6/common.c b/board/compulab/cm_fx6/common.c index 19fa5d3cf70..796931dc991 100644 --- a/board/compulab/cm_fx6/common.c +++ b/board/compulab/cm_fx6/common.c @@ -15,8 +15,6 @@ #include <fsl_esdhc.h> #include "common.h" -DECLARE_GLOBAL_DATA_PTR; - #ifdef CONFIG_FSL_ESDHC #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ diff --git a/board/compulab/cm_fx6/spl.c b/board/compulab/cm_fx6/spl.c index 16e5bf8dfa2..924f5d79df7 100644 --- a/board/compulab/cm_fx6/spl.c +++ b/board/compulab/cm_fx6/spl.c @@ -20,8 +20,6 @@ #include <fsl_esdhc.h> #include "common.h" -DECLARE_GLOBAL_DATA_PTR; - enum ddr_config { DDR_16BIT_256MB, DDR_32BIT_512MB, diff --git a/board/compulab/cm_t43/spl.c b/board/compulab/cm_t43/spl.c index b7d118eb9ce..ccdf6b3e342 100644 --- a/board/compulab/cm_t43/spl.c +++ b/board/compulab/cm_t43/spl.c @@ -14,8 +14,6 @@ #include <power/tps65218.h> #include "board.h" -DECLARE_GLOBAL_DATA_PTR; - const struct dpll_params dpll_mpu = { 800, 24, 1, -1, -1, -1, -1 }; const struct dpll_params dpll_core = { 1000, 24, -1, -1, 10, 8, 4 }; const struct dpll_params dpll_per = { 960, 24, 5, -1, -1, -1, -1 }; diff --git a/board/compulab/common/omap3_display.c b/board/compulab/common/omap3_display.c index ed2077e3617..e19fbb91613 100644 --- a/board/compulab/common/omap3_display.c +++ b/board/compulab/common/omap3_display.c @@ -17,8 +17,6 @@ #include <scf0403_lcd.h> #include <asm/arch-omap3/dss.h> -DECLARE_GLOBAL_DATA_PTR; - enum display_type { NONE, DVI, diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c index 57ae7f15ce8..c4b81a9f92f 100644 --- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c +++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c @@ -45,8 +45,6 @@ (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) -DECLARE_GLOBAL_DATA_PTR; - static const struct mx6dq_iomux_ddr_regs dhcom6dq_ddr_ioregs = { .dram_sdclk_0 = 0x00020030, .dram_sdclk_1 = 0x00020030, diff --git a/board/engicam/common/spl.c b/board/engicam/common/spl.c index 6e2389dd4b4..6d4f8c34267 100644 --- a/board/engicam/common/spl.c +++ b/board/engicam/common/spl.c @@ -23,8 +23,6 @@ #include <asm/mach-imx/iomux-v3.h> #include <asm/mach-imx/video.h> -DECLARE_GLOBAL_DATA_PTR; - #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) diff --git a/board/engicam/imx6q/imx6q.c b/board/engicam/imx6q/imx6q.c index fe37088b491..1c57358d167 100644 --- a/board/engicam/imx6q/imx6q.c +++ b/board/engicam/imx6q/imx6q.c @@ -22,8 +22,6 @@ #include "../common/board.h" -DECLARE_GLOBAL_DATA_PTR; - #ifdef CONFIG_NAND_MXS #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \ diff --git a/board/engicam/imx6ul/imx6ul.c b/board/engicam/imx6ul/imx6ul.c index a903a3603ba..26c6354c377 100644 --- a/board/engicam/imx6ul/imx6ul.c +++ b/board/engicam/imx6ul/imx6ul.c @@ -22,8 +22,6 @@ #include "../common/board.h" -DECLARE_GLOBAL_DATA_PTR; - #ifdef CONFIG_NAND_MXS #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP) diff --git a/board/esd/vme8349/pci.c b/board/esd/vme8349/pci.c index 4d3b21ddff4..f1cfa23b42b 100644 --- a/board/esd/vme8349/pci.c +++ b/board/esd/vme8349/pci.c @@ -20,8 +20,6 @@ #include <asm/fsl_i2c.h> #include "vme8349pin.h" -DECLARE_GLOBAL_DATA_PTR; - static struct pci_region pci1_regions[] = { { bus_start: CONFIG_SYS_PCI1_MEM_BASE, diff --git a/board/freescale/bsc9131rdb/ddr.c b/board/freescale/bsc9131rdb/ddr.c index 339c5762563..2a5e61e2304 100644 --- a/board/freescale/bsc9131rdb/ddr.c +++ b/board/freescale/bsc9131rdb/ddr.c @@ -13,8 +13,6 @@ #include <asm/io.h> #include <asm/fsl_law.h> -DECLARE_GLOBAL_DATA_PTR; - #ifndef CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_SYS_DRAM_SIZE 1024 diff --git a/board/freescale/bsc9132qds/ddr.c b/board/freescale/bsc9132qds/ddr.c index 43f163a2c62..49b6b8fe586 100644 --- a/board/freescale/bsc9132qds/ddr.c +++ b/board/freescale/bsc9132qds/ddr.c @@ -13,8 +13,6 @@ #include <asm/io.h> #include <asm/fsl_law.h> -DECLARE_GLOBAL_DATA_PTR; - #ifndef CONFIG_SYS_DDR_RAW_TIMING fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = { diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c index a9451c5c6ee..eb25f5e23f8 100644 --- a/board/freescale/common/vid.c +++ b/board/freescale/common/vid.c @@ -17,8 +17,6 @@ #endif #include "vid.h" -DECLARE_GLOBAL_DATA_PTR; - int __weak i2c_multiplexer_select_vid_channel(u8 channel) { return 0; diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 8b3f4ad78d8..99c103239bd 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -38,8 +38,6 @@ #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0x0f) | value) #define SET_EC_MUX_SEL(reg, value) ((reg & 0xf0) | value) -DECLARE_GLOBAL_DATA_PTR; - enum { MUX_TYPE_CAN, MUX_TYPE_IIC2, diff --git a/board/freescale/ls1088a/eth_ls1088ardb.c b/board/freescale/ls1088a/eth_ls1088ardb.c index 97accc90fd7..fa86118acc8 100644 --- a/board/freescale/ls1088a/eth_ls1088ardb.c +++ b/board/freescale/ls1088a/eth_ls1088ardb.c @@ -18,8 +18,6 @@ #include <fsl-mc/fsl_mc.h> #include <fsl-mc/ldpaa_wriop.h> -DECLARE_GLOBAL_DATA_PTR; - int board_eth_init(bd_t *bis) { #if defined(CONFIG_FSL_MC_ENET) diff --git a/board/freescale/m5329evb/nand.c b/board/freescale/m5329evb/nand.c index 88496812bf8..291346d612b 100644 --- a/board/freescale/m5329evb/nand.c +++ b/board/freescale/m5329evb/nand.c @@ -13,8 +13,6 @@ #include <asm/io.h> #include <asm/immap.h> -DECLARE_GLOBAL_DATA_PTR; - #if defined(CONFIG_CMD_NAND) #include <nand.h> #include <linux/mtd/mtd.h> diff --git a/board/freescale/m5373evb/nand.c b/board/freescale/m5373evb/nand.c index a96a59991f5..4b0354029d4 100644 --- a/board/freescale/m5373evb/nand.c +++ b/board/freescale/m5373evb/nand.c @@ -13,8 +13,6 @@ #include <asm/io.h> #include <asm/immap.h> -DECLARE_GLOBAL_DATA_PTR; - #if defined(CONFIG_CMD_NAND) #include <nand.h> #include <linux/mtd/mtd.h> diff --git a/board/freescale/mpc8308rdb/mpc8308rdb.c b/board/freescale/mpc8308rdb/mpc8308rdb.c index 93c7200509c..0cf1c08f29e 100644 --- a/board/freescale/mpc8308rdb/mpc8308rdb.c +++ b/board/freescale/mpc8308rdb/mpc8308rdb.c @@ -20,8 +20,6 @@ #include <asm/fsl_serdes.h> #include <asm/fsl_mpc83xx_serdes.h> -DECLARE_GLOBAL_DATA_PTR; - /* * The following are used to control the SPI chip selects for the SPI command. */ diff --git a/board/freescale/mpc832xemds/pci.c b/board/freescale/mpc832xemds/pci.c index e8b2b11d88b..274bf9384ef 100644 --- a/board/freescale/mpc832xemds/pci.c +++ b/board/freescale/mpc832xemds/pci.c @@ -16,8 +16,6 @@ #include <asm/fsl_i2c.h> #include "../common/pq-mds-pib.h" -DECLARE_GLOBAL_DATA_PTR; - static struct pci_region pci1_regions[] = { { bus_start: CONFIG_SYS_PCI1_MEM_BASE, diff --git a/board/freescale/mpc8349emds/pci.c b/board/freescale/mpc8349emds/pci.c index 9f7324feddf..311517f75ba 100644 --- a/board/freescale/mpc8349emds/pci.c +++ b/board/freescale/mpc8349emds/pci.c @@ -12,8 +12,6 @@ #include <i2c.h> #include <asm/fsl_i2c.h> -DECLARE_GLOBAL_DATA_PTR; - static struct pci_region pci1_regions[] = { { bus_start: CONFIG_SYS_PCI1_MEM_BASE, diff --git a/board/freescale/mpc8349itx/pci.c b/board/freescale/mpc8349itx/pci.c index afc9df0923b..adb0ed80817 100644 --- a/board/freescale/mpc8349itx/pci.c +++ b/board/freescale/mpc8349itx/pci.c @@ -13,8 +13,6 @@ #include <i2c.h> #include <asm/fsl_i2c.h> -DECLARE_GLOBAL_DATA_PTR; - static struct pci_region pci1_regions[] = { { bus_start: CONFIG_SYS_PCI1_MEM_BASE, diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c index 4e3c824e750..89acea33d11 100644 --- a/board/freescale/p1022ds/p1022ds.c +++ b/board/freescale/p1022ds/p1022ds.c @@ -28,8 +28,6 @@ #include "../common/ngpixis.h" -DECLARE_GLOBAL_DATA_PTR; - int board_early_init_f(void) { ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; diff --git a/board/freescale/p1023rdb/ddr.c b/board/freescale/p1023rdb/ddr.c index d587df527ab..191a8244110 100644 --- a/board/freescale/p1023rdb/ddr.c +++ b/board/freescale/p1023rdb/ddr.c @@ -13,8 +13,6 @@ #include <asm/io.h> #include <asm/fsl_law.h> -DECLARE_GLOBAL_DATA_PTR; - /* CONFIG_SYS_DDR_RAW_TIMING */ /* * Hynix H5TQ1G83TFR-H9C diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index bdbe5e70270..ee93e545ded 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -21,8 +21,6 @@ #include "gsc.h" #include "common.h" -DECLARE_GLOBAL_DATA_PTR; - #define RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */ #define GSC_EEPROM_DDR_SIZE 0x2B /* enum (512,1024,2048) MB */ #define GSC_EEPROM_DDR_WIDTH 0x2D /* enum (32,64) bit */ diff --git a/board/gdsys/mpc8308/hrcon.c b/board/gdsys/mpc8308/hrcon.c index ed5cb332794..d1ed273a083 100644 --- a/board/gdsys/mpc8308/hrcon.c +++ b/board/gdsys/mpc8308/hrcon.c @@ -33,8 +33,6 @@ #include <miiphy.h> -DECLARE_GLOBAL_DATA_PTR; - #define MAX_MUX_CHANNELS 2 enum { diff --git a/board/gdsys/mpc8308/strider.c b/board/gdsys/mpc8308/strider.c index c8ea8a4ae0a..c3b09b29d59 100644 --- a/board/gdsys/mpc8308/strider.c +++ b/board/gdsys/mpc8308/strider.c @@ -36,8 +36,6 @@ #include <miiphy.h> -DECLARE_GLOBAL_DATA_PTR; - #define MAX_MUX_CHANNELS 2 enum { diff --git a/board/gdsys/p1022/controlcenterd.c b/board/gdsys/p1022/controlcenterd.c index b5f445a943d..7bdc924a89d 100644 --- a/board/gdsys/p1022/controlcenterd.c +++ b/board/gdsys/p1022/controlcenterd.c @@ -44,8 +44,6 @@ #include "../common/dp501.h" #include "controlcenterd-id.h" -DECLARE_GLOBAL_DATA_PTR; - enum { HWVER_100 = 0, HWVER_110 = 1, diff --git a/board/geekbuying/geekbox/geekbox.c b/board/geekbuying/geekbox/geekbox.c index 88b67f9d5f3..b638186e8f5 100644 --- a/board/geekbuying/geekbox/geekbox.c +++ b/board/geekbuying/geekbox/geekbox.c @@ -6,8 +6,6 @@ #include <common.h> -DECLARE_GLOBAL_DATA_PTR; - int board_init(void) { return 0; diff --git a/board/intel/edison/edison.c b/board/intel/edison/edison.c index 4b1e6d0f471..e3334f84387 100644 --- a/board/intel/edison/edison.c +++ b/board/intel/edison/edison.c @@ -17,8 +17,6 @@ #include <asm/scu.h> #include <asm/u-boot-x86.h> -DECLARE_GLOBAL_DATA_PTR; - static struct dwc3_device dwc3_device_data = { .maximum_speed = USB_SPEED_HIGH, .base = CONFIG_SYS_USB_OTG_BASE, diff --git a/board/keymile/kmp204x/kmp204x.c b/board/keymile/kmp204x/kmp204x.c index d70b1d1393c..bc229e872fa 100644 --- a/board/keymile/kmp204x/kmp204x.c +++ b/board/keymile/kmp204x/kmp204x.c @@ -24,8 +24,6 @@ #include "../common/common.h" #include "kmp204x.h" -DECLARE_GLOBAL_DATA_PTR; - static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; int checkboard(void) diff --git a/board/kosagi/novena/novena_spl.c b/board/kosagi/novena/novena_spl.c index b4a68da88f2..0dd0b6eec24 100644 --- a/board/kosagi/novena/novena_spl.c +++ b/board/kosagi/novena/novena_spl.c @@ -27,8 +27,6 @@ #include "novena.h" -DECLARE_GLOBAL_DATA_PTR; - #define UART_PAD_CTRL \ (PAD_CTL_PKE | PAD_CTL_PUE | \ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ diff --git a/board/liebherr/mccmon6/spl.c b/board/liebherr/mccmon6/spl.c index 196da46df9a..61d12ba239b 100644 --- a/board/liebherr/mccmon6/spl.c +++ b/board/liebherr/mccmon6/spl.c @@ -20,8 +20,6 @@ #include <asm/arch/sys_proto.h> #include <spl.h> -DECLARE_GLOBAL_DATA_PTR; - #if defined(CONFIG_SPL_BUILD) #include <asm/arch/mx6-ddr.h> /* diff --git a/board/mpc8308_p1m/mpc8308_p1m.c b/board/mpc8308_p1m/mpc8308_p1m.c index e96645f82dc..a5a036f9cff 100644 --- a/board/mpc8308_p1m/mpc8308_p1m.c +++ b/board/mpc8308_p1m/mpc8308_p1m.c @@ -16,8 +16,6 @@ #include <asm/fsl_serdes.h> #include <asm/fsl_mpc83xx_serdes.h> -DECLARE_GLOBAL_DATA_PTR; - int checkboard(void) { printf("Board: MPC8308 P1M\n"); diff --git a/board/nvidia/jetson-tk1/jetson-tk1.c b/board/nvidia/jetson-tk1/jetson-tk1.c index c20da29a98a..31695d4a0fc 100644 --- a/board/nvidia/jetson-tk1/jetson-tk1.c +++ b/board/nvidia/jetson-tk1/jetson-tk1.c @@ -15,8 +15,6 @@ #include "pinmux-config-jetson-tk1.h" -DECLARE_GLOBAL_DATA_PTR; - /* * Routine: pinmux_init * Description: Do individual peripheral pinmux configs diff --git a/board/overo/overo.c b/board/overo/overo.c index 7b44a37103b..102f9805fa2 100644 --- a/board/overo/overo.c +++ b/board/overo/overo.c @@ -32,8 +32,6 @@ #include <asm/ehci-omap.h> #endif -DECLARE_GLOBAL_DATA_PTR; - #define TWL4030_I2C_BUS 0 #define EXPANSION_EEPROM_I2C_BUS 2 #define EXPANSION_EEPROM_I2C_ADDRESS 0x51 diff --git a/board/qca/ap121/ap121.c b/board/qca/ap121/ap121.c index ac9be35dd9b..56ae8e1ea4d 100644 --- a/board/qca/ap121/ap121.c +++ b/board/qca/ap121/ap121.c @@ -13,8 +13,6 @@ #include <mach/ath79.h> #include <debug_uart.h> -DECLARE_GLOBAL_DATA_PTR; - #ifdef CONFIG_DEBUG_UART_BOARD_INIT void board_debug_uart_init(void) { diff --git a/board/qca/ap143/ap143.c b/board/qca/ap143/ap143.c index 19b55acbf2d..1ebd3622565 100644 --- a/board/qca/ap143/ap143.c +++ b/board/qca/ap143/ap143.c @@ -13,8 +13,6 @@ #include <mach/ath79.h> #include <debug_uart.h> -DECLARE_GLOBAL_DATA_PTR; - #ifdef CONFIG_DEBUG_UART_BOARD_INIT void board_debug_uart_init(void) { diff --git a/board/renesas/alt/Makefile b/board/renesas/alt/Makefile index 22ab1f43d96..53418699b27 100644 --- a/board/renesas/alt/Makefile +++ b/board/renesas/alt/Makefile @@ -6,4 +6,8 @@ # SPDX-License-Identifier: GPL-2.0 # -obj-y := alt.o qos.o ../rcar-common/common.o +ifdef CONFIG_SPL_BUILD +obj-y := alt_spl.o +else +obj-y := alt.o qos.o +endif diff --git a/board/renesas/alt/alt.c b/board/renesas/alt/alt.c index f2200ef0810..7598b1a4b92 100644 --- a/board/renesas/alt/alt.c +++ b/board/renesas/alt/alt.c @@ -43,176 +43,65 @@ void s_init(void) qos_init(); } -#define TMU0_MSTP125 (1 << 25) -#define SCIF2_MSTP719 (1 << 19) -#define ETHER_MSTP813 (1 << 13) -#define IIC1_MSTP323 (1 << 23) -#define MMC0_MSTP315 (1 << 15) -#define SDHI0_MSTP314 (1 << 14) -#define SDHI1_MSTP312 (1 << 12) +#define TMU0_MSTP125 BIT(25) +#define MMC0_MSTP315 BIT(15) #define SD1CKCR 0xE6150078 -#define SD1_97500KHZ 0x7 +#define SD_97500KHZ 0x7 int board_early_init_f(void) { /* TMU */ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); - /* SCIF2 */ - mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719); + /* Set SD1 to the 97.5MHz */ + writel(SD_97500KHZ, SD1CKCR); - /* ETHER */ - mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); - - /* IIC1 / sh-i2c ch1 */ - mstp_clrbits_le32(MSTPSR3, SMSTPCR3, IIC1_MSTP323); - -#ifdef CONFIG_SH_MMCIF - /* MMC */ - mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC0_MSTP315); -#endif - -#ifdef CONFIG_SH_SDHI - /* SDHI0, 1 */ - mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314 | SDHI1_MSTP312); - - /* - * SD0 clock is set to 97.5MHz by default. - * Set SD1 to the 97.5MHz as well. - */ - writel(SD1_97500KHZ, SD1CKCR); -#endif return 0; } +#define ETHERNET_PHY_RESET 56 /* GPIO 1 24 */ + int board_init(void) { /* adress of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - /* Init PFC controller */ - r8a7794_pinmux_init(); - - /* Ether Enable */ -#if defined(CONFIG_R8A7794_ETHERNET_B) - gpio_request(GPIO_FN_ETH_CRS_DV_B, NULL); - gpio_request(GPIO_FN_ETH_RX_ER_B, NULL); - gpio_request(GPIO_FN_ETH_RXD0_B, NULL); - gpio_request(GPIO_FN_ETH_RXD1_B, NULL); - gpio_request(GPIO_FN_ETH_LINK_B, NULL); - gpio_request(GPIO_FN_ETH_REFCLK_B, NULL); - gpio_request(GPIO_FN_ETH_MDIO_B, NULL); - gpio_request(GPIO_FN_ETH_TXD1_B, NULL); - gpio_request(GPIO_FN_ETH_TX_EN_B, NULL); - gpio_request(GPIO_FN_ETH_MAGIC_B, NULL); - gpio_request(GPIO_FN_ETH_TXD0_B, NULL); - gpio_request(GPIO_FN_ETH_MDC_B, NULL); -#else - gpio_request(GPIO_FN_ETH_CRS_DV, NULL); - gpio_request(GPIO_FN_ETH_RX_ER, NULL); - gpio_request(GPIO_FN_ETH_RXD0, NULL); - gpio_request(GPIO_FN_ETH_RXD1, NULL); - gpio_request(GPIO_FN_ETH_LINK, NULL); - gpio_request(GPIO_FN_ETH_REFCLK, NULL); - gpio_request(GPIO_FN_ETH_MDIO, NULL); - gpio_request(GPIO_FN_ETH_TXD1, NULL); - gpio_request(GPIO_FN_ETH_TX_EN, NULL); - gpio_request(GPIO_FN_ETH_MAGIC, NULL); - gpio_request(GPIO_FN_ETH_TXD0, NULL); - gpio_request(GPIO_FN_ETH_MDC, NULL); -#endif - gpio_request(GPIO_FN_IRQ8, NULL); - - /* PHY reset */ - gpio_request(GPIO_GP_1_24, NULL); - gpio_direction_output(GPIO_GP_1_24, 0); + /* Force ethernet PHY out of reset */ + gpio_request(ETHERNET_PHY_RESET, "phy_reset"); + gpio_direction_output(ETHERNET_PHY_RESET, 0); mdelay(20); - gpio_set_value(GPIO_GP_1_24, 1); + gpio_direction_output(ETHERNET_PHY_RESET, 1); udelay(1); return 0; } -#define CXR24 0xEE7003C0 /* MAC address high register */ -#define CXR25 0xEE7003C8 /* MAC address low register */ -int board_eth_init(bd_t *bis) +int dram_init(void) { -#ifdef CONFIG_SH_ETHER - int ret = -ENODEV; - u32 val; - unsigned char enetaddr[6]; - - ret = sh_eth_initialize(bis); - if (!eth_env_get_enetaddr("ethaddr", enetaddr)) - return ret; + if (fdtdec_setup_memory_size() != 0) + return -EINVAL; - /* Set Mac address */ - val = enetaddr[0] << 24 | enetaddr[1] << 16 | - enetaddr[2] << 8 | enetaddr[3]; - writel(val, CXR24); - - val = enetaddr[4] << 8 | enetaddr[5]; - writel(val, CXR25); - - return ret; -#else return 0; -#endif } -int board_mmc_init(bd_t *bis) +int dram_init_banksize(void) { - int ret = -ENODEV; - -#ifdef CONFIG_SH_MMCIF - gpio_request(GPIO_GP_4_31, NULL); - gpio_set_value(GPIO_GP_4_31, 1); - - ret = mmcif_mmc_init(); -#endif - -#ifdef CONFIG_SH_SDHI - gpio_request(GPIO_FN_SD0_DATA0, NULL); - gpio_request(GPIO_FN_SD0_DATA1, NULL); - gpio_request(GPIO_FN_SD0_DATA2, NULL); - gpio_request(GPIO_FN_SD0_DATA3, NULL); - gpio_request(GPIO_FN_SD0_CLK, NULL); - gpio_request(GPIO_FN_SD0_CMD, NULL); - gpio_request(GPIO_FN_SD0_CD, NULL); - gpio_request(GPIO_FN_SD1_DATA0, NULL); - gpio_request(GPIO_FN_SD1_DATA1, NULL); - gpio_request(GPIO_FN_SD1_DATA2, NULL); - gpio_request(GPIO_FN_SD1_DATA3, NULL); - gpio_request(GPIO_FN_SD1_CLK, NULL); - gpio_request(GPIO_FN_SD1_CMD, NULL); - gpio_request(GPIO_FN_SD1_CD, NULL); - - /* SDHI 0 */ - gpio_request(GPIO_GP_2_26, NULL); - gpio_request(GPIO_GP_2_29, NULL); - gpio_direction_output(GPIO_GP_2_26, 1); - gpio_direction_output(GPIO_GP_2_29, 1); - - ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0, - SH_SDHI_QUIRK_16BIT_BUF); - if (ret) - return ret; + fdtdec_setup_memory_banksize(); - /* SDHI 1 */ - gpio_request(GPIO_GP_4_26, NULL); - gpio_request(GPIO_GP_4_29, NULL); - gpio_direction_output(GPIO_GP_4_26, 1); - gpio_direction_output(GPIO_GP_4_29, 1); - - ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI1_BASE, 1, 0); -#endif - return ret; + return 0; } -int dram_init(void) +/* KSZ8041RNLI */ +#define PHY_CONTROL1 0x1E +#define PHY_LED_MODE 0xC0000 +#define PHY_LED_MODE_ACK 0x4000 +int board_phy_config(struct phy_device *phydev) { - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1); + ret &= ~PHY_LED_MODE; + ret |= PHY_LED_MODE_ACK; + ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret); return 0; } @@ -223,22 +112,38 @@ const struct rmobile_sysinfo sysinfo = { void reset_cpu(ulong addr) { - u8 val; + struct udevice *dev; + const u8 pmic_bus = 1; + const u8 pmic_addr = 0x58; + u8 data; + int ret; - i2c_set_bus_num(1); /* PowerIC connected to ch1 */ - i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); - val |= 0x02; - i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); + ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev); + if (ret) + hang(); + + ret = dm_i2c_read(dev, 0x13, &data, 1); + if (ret) + hang(); + + data |= BIT(1); + + ret = dm_i2c_write(dev, 0x13, &data, 1); + if (ret) + hang(); } -static const struct sh_serial_platdata serial_platdata = { - .base = SCIF2_BASE, - .type = PORT_SCIF, - .clk = 14745600, - .clk_mode = EXT_CLK, -}; +enum env_location env_get_location(enum env_operation op, int prio) +{ + const u32 load_magic = 0xb33fc0de; -U_BOOT_DEVICE(alt_serials) = { - .name = "serial_sh", - .platdata = &serial_platdata, -}; + /* Block environment access if loaded using JTAG */ + if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) && + (op != ENVOP_INIT)) + return ENVL_UNKNOWN; + + if (prio) + return ENVL_UNKNOWN; + + return ENVL_SPI_FLASH; +} diff --git a/board/renesas/alt/alt_spl.c b/board/renesas/alt/alt_spl.c new file mode 100644 index 00000000000..f893a49257d --- /dev/null +++ b/board/renesas/alt/alt_spl.c @@ -0,0 +1,411 @@ +/* + * board/renesas/alt/alt_spl.c + * + * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <malloc.h> +#include <dm/platform_data/serial_sh.h> +#include <asm/processor.h> +#include <asm/mach-types.h> +#include <asm/io.h> +#include <linux/errno.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/arch/rmobile.h> +#include <asm/arch/rcar-mstp.h> + +#include <spl.h> + +#define TMU0_MSTP125 BIT(25) +#define SCIF2_MSTP719 BIT(19) +#define QSPI_MSTP917 BIT(17) + +#define SD1CKCR 0xE6150078 +#define SD_97500KHZ 0x7 + +struct reg_config { + u16 off; + u32 val; +}; + +static void dbsc_wait(u16 reg) +{ + static const u32 dbsc3_0_base = DBSC3_0_BASE; + + while (!(readl(dbsc3_0_base + reg) & BIT(0))) + ; +} + +static void spl_init_sys(void) +{ + u32 r0 = 0; + + writel(0xa5a5a500, 0xe6020004); + writel(0xa5a5a500, 0xe6030004); + + asm volatile( + /* ICIALLU - Invalidate I$ to PoU */ + "mcr 15, 0, %0, cr7, cr5, 0 \n" + /* BPIALL - Invalidate branch predictors */ + "mcr 15, 0, %0, cr7, cr5, 6 \n" + /* Set SCTLR[IZ] */ + "mrc 15, 0, %0, cr1, cr0, 0 \n" + "orr %0, #0x1800 \n" + "mcr 15, 0, %0, cr1, cr0, 0 \n" + "isb sy \n" + :"=r"(r0)); +} + +static void spl_init_pfc(void) +{ + static const struct reg_config pfc_with_unlock[] = { + { 0x0090, 0x00000000 }, + { 0x0094, 0x00000000 }, + { 0x0098, 0x00000000 }, + { 0x0020, 0x00000000 }, + { 0x0024, 0x00000000 }, + { 0x0028, 0x40000000 }, + { 0x002c, 0x00000155 }, + { 0x0030, 0x00000002 }, + { 0x0034, 0x00000000 }, + { 0x0038, 0x00000000 }, + { 0x003c, 0x00000000 }, + { 0x0040, 0x60000000 }, + { 0x0044, 0x36dab6db }, + { 0x0048, 0x926da012 }, + { 0x004c, 0x0008c383 }, + { 0x0050, 0x00000000 }, + { 0x0054, 0x00000140 }, + { 0x0004, 0xffffffff }, + { 0x0008, 0x00ec3fff }, + { 0x000c, 0x5bffffff }, + { 0x0010, 0x01bfe1ff }, + { 0x0014, 0x5bffffff }, + { 0x0018, 0x0f4b200f }, + { 0x001c, 0x03ffffff }, + }; + + static const struct reg_config pfc_without_unlock[] = { + { 0x0100, 0x00000000 }, + { 0x0104, 0x4203fc00 }, + { 0x0108, 0x00000000 }, + { 0x010c, 0x159007ff }, + { 0x0110, 0x80000000 }, + { 0x0114, 0x00de481f }, + { 0x0118, 0x00000000 }, + }; + + static const struct reg_config pfc_with_unlock2[] = { + { 0x0060, 0xffffffff }, + { 0x0064, 0xfffff000 }, + { 0x0068, 0x55555500 }, + { 0x006c, 0xffffff00 }, + { 0x0070, 0x00000000 }, + }; + + static const u32 pfc_base = 0xe6060000; + + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) { + writel(~pfc_with_unlock[i].val, pfc_base); + writel(pfc_with_unlock[i].val, + pfc_base | pfc_with_unlock[i].off); + } + + for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++) + writel(pfc_without_unlock[i].val, + pfc_base | pfc_without_unlock[i].off); + + for (i = 0; i < ARRAY_SIZE(pfc_with_unlock2); i++) { + writel(~pfc_with_unlock2[i].val, pfc_base); + writel(pfc_with_unlock2[i].val, + pfc_base | pfc_with_unlock2[i].off); + } +} + +static void spl_init_gpio(void) +{ + static const u16 gpio_offs[] = { + 0x1000, 0x2000, 0x3000, 0x4000, 0x5000 + }; + + static const struct reg_config gpio_set[] = { + { 0x2000, 0x24000000 }, + { 0x4000, 0xa4000000 }, + { 0x5000, 0x0004c000 }, + }; + + static const struct reg_config gpio_clr[] = { + { 0x1000, 0x01000000 }, + { 0x2000, 0x24000000 }, + { 0x3000, 0x00000000 }, + { 0x4000, 0xa4000000 }, + { 0x5000, 0x0084c380 }, + }; + + static const u32 gpio_base = 0xe6050000; + + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(gpio_offs); i++) + writel(0, gpio_base | 0x20 | gpio_offs[i]); + + for (i = 0; i < ARRAY_SIZE(gpio_offs); i++) + writel(0, gpio_base | 0x00 | gpio_offs[i]); + + for (i = 0; i < ARRAY_SIZE(gpio_set); i++) + writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off); + + for (i = 0; i < ARRAY_SIZE(gpio_clr); i++) + writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off); +} + +static void spl_init_lbsc(void) +{ + static const struct reg_config lbsc_config[] = { + { 0x00, 0x00000020 }, + { 0x08, 0x00002020 }, + { 0x30, 0x2a103320 }, + { 0x38, 0xff70ff70 }, + }; + + static const u16 lbsc_offs[] = { + 0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8 + }; + + static const u32 lbsc_base = 0xfec00200; + + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) { + writel(lbsc_config[i].val, + lbsc_base | lbsc_config[i].off); + writel(lbsc_config[i].val, + lbsc_base | (lbsc_config[i].off + 4)); + } + + for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++) + writel(0, lbsc_base | lbsc_offs[i]); +} + +static void spl_init_dbsc(void) +{ + static const struct reg_config dbsc_config1[] = { + { 0x0018, 0x21000000 }, + { 0x0018, 0x11000000 }, + { 0x0018, 0x10000000 }, + { 0x0280, 0x0000a55a }, + { 0x0290, 0x00000001 }, + { 0x02a0, 0x80000000 }, + { 0x0290, 0x00000004 }, + }; + + static const struct reg_config dbsc_config2[] = { + { 0x0290, 0x00000006 }, + { 0x02a0, 0x0005c000 }, + }; + + static const struct reg_config dbsc_config4[] = { + { 0x0290, 0x00000010 }, + { 0x02a0, 0xf00464db }, + { 0x0290, 0x00000061 }, + { 0x02a0, 0x0000006d }, + { 0x0290, 0x00000001 }, + { 0x02a0, 0x00000073 }, + { 0x0020, 0x00000007 }, + { 0x0024, 0x0f030a02 }, + { 0x0030, 0x00000001 }, + { 0x00b0, 0x00000000 }, + { 0x0040, 0x00000009 }, + { 0x0044, 0x00000007 }, + { 0x0048, 0x00000000 }, + { 0x0050, 0x00000009 }, + { 0x0054, 0x000a0009 }, + { 0x0058, 0x00000021 }, + { 0x005c, 0x00000018 }, + { 0x0060, 0x00000005 }, + { 0x0064, 0x0000001b }, + { 0x0068, 0x00000007 }, + { 0x006c, 0x0000000a }, + { 0x0070, 0x00000009 }, + { 0x0074, 0x00000010 }, + { 0x0078, 0x000000ae }, + { 0x007c, 0x00140005 }, + { 0x0080, 0x00050004 }, + { 0x0084, 0x50213005 }, + { 0x0088, 0x000c0000 }, + { 0x008c, 0x00000200 }, + { 0x0090, 0x00000040 }, + { 0x0100, 0x00000001 }, + { 0x00c0, 0x00020001 }, + { 0x00c8, 0x20082008 }, + { 0x0380, 0x00020003 }, + { 0x0390, 0x0000001f }, + }; + + static const struct reg_config dbsc_config5[] = { + { 0x0244, 0x00000011 }, + { 0x0290, 0x00000003 }, + { 0x02a0, 0x0300c4e1 }, + { 0x0290, 0x00000023 }, + { 0x02a0, 0x00fcb6d0 }, + { 0x0290, 0x00000011 }, + { 0x02a0, 0x1000040b }, + { 0x0290, 0x00000012 }, + { 0x02a0, 0x85589955 }, + { 0x0290, 0x00000013 }, + { 0x02a0, 0x1a852400 }, + { 0x0290, 0x00000014 }, + { 0x02a0, 0x300210b4 }, + { 0x0290, 0x00000015 }, + { 0x02a0, 0x00000b50 }, + { 0x0290, 0x00000016 }, + { 0x02a0, 0x00000006 }, + { 0x0290, 0x00000017 }, + { 0x02a0, 0x00000010 }, + { 0x0290, 0x0000001a }, + { 0x02a0, 0x910035c7 }, + { 0x0290, 0x00000004 }, + }; + + static const struct reg_config dbsc_config6[] = { + { 0x0290, 0x00000001 }, + { 0x02a0, 0x00000181 }, + { 0x0018, 0x11000000 }, + { 0x0290, 0x00000004 }, + }; + + static const struct reg_config dbsc_config7[] = { + { 0x0290, 0x00000001 }, + { 0x02a0, 0x0000fe01 }, + { 0x0304, 0x00000000 }, + { 0x00f4, 0x01004c20 }, + { 0x00f8, 0x014000aa }, + { 0x00e0, 0x00000140 }, + { 0x00e4, 0x00081450 }, + { 0x00e8, 0x00010000 }, + { 0x0290, 0x00000004 }, + }; + + static const struct reg_config dbsc_config8[] = { + { 0x0014, 0x00000001 }, + { 0x0010, 0x00000001 }, + { 0x0280, 0x00000000 }, + }; + + static const u32 dbsc3_0_base = DBSC3_0_BASE; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++) + writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off); + + dbsc_wait(0x2a0); + + for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++) + writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off); + + for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++) + writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off); + + dbsc_wait(0x240); + + for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++) + writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off); + + dbsc_wait(0x2a0); + + for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++) + writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off); + + dbsc_wait(0x2a0); + + for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++) + writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off); + + dbsc_wait(0x2a0); + + for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++) + writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off); + +} + +static void spl_init_qspi(void) +{ + mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917); + + static const u32 qspi_base = 0xe6b10000; + + writeb(0x08, qspi_base + 0x00); + writeb(0x00, qspi_base + 0x01); + writeb(0x06, qspi_base + 0x02); + writeb(0x01, qspi_base + 0x0a); + writeb(0x00, qspi_base + 0x0b); + writeb(0x00, qspi_base + 0x0c); + writeb(0x00, qspi_base + 0x0d); + writeb(0x00, qspi_base + 0x0e); + + writew(0xe080, qspi_base + 0x10); + + writeb(0xc0, qspi_base + 0x18); + writeb(0x00, qspi_base + 0x18); + writeb(0x00, qspi_base + 0x08); + writeb(0x48, qspi_base + 0x00); +} + +void board_init_f(ulong dummy) +{ + mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); + mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719); + + /* Set SD1 to the 97.5MHz */ + writel(SD_97500KHZ, SD1CKCR); + + spl_init_sys(); + spl_init_pfc(); + spl_init_gpio(); + spl_init_lbsc(); + spl_init_dbsc(); + spl_init_qspi(); +} + +void spl_board_init(void) +{ + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); +} + +void board_boot_order(u32 *spl_boot_list) +{ + const u32 jtag_magic = 0x1337c0de; + const u32 load_magic = 0xb33fc0de; + + /* + * If JTAG probe sets special word at 0xe6300020, then it must + * put U-Boot into RAM and SPL will start it from RAM. + */ + if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) { + printf("JTAG boot detected!\n"); + + while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic) + ; + + spl_boot_list[0] = BOOT_DEVICE_RAM; + spl_boot_list[1] = BOOT_DEVICE_NONE; + + return; + } + + /* Boot from SPI NOR with YMODEM UART fallback. */ + spl_boot_list[0] = BOOT_DEVICE_SPI; + spl_boot_list[1] = BOOT_DEVICE_UART; + spl_boot_list[2] = BOOT_DEVICE_NONE; +} + +void reset_cpu(ulong addr) +{ +} diff --git a/board/renesas/gose/Makefile b/board/renesas/gose/Makefile index e09ae1e4143..c6a1dc21cda 100644 --- a/board/renesas/gose/Makefile +++ b/board/renesas/gose/Makefile @@ -1,9 +1,13 @@ # -# board/renesas/alt/Makefile +# board/renesas/gose/Makefile # # Copyright (C) 2014 Renesas Electronics Corporation # # SPDX-License-Identifier: GPL-2.0 # -obj-y := gose.o qos.o ../rcar-common/common.o +ifdef CONFIG_SPL_BUILD +obj-y := gose_spl.o +else +obj-y := gose.o qos.o +endif diff --git a/board/renesas/gose/gose.c b/board/renesas/gose/gose.c index 99d4ba6fd8b..c9209701dd3 100644 --- a/board/renesas/gose/gose.c +++ b/board/renesas/gose/gose.c @@ -46,13 +46,7 @@ void s_init(void) qos_init(); } -#define TMU0_MSTP125 (1 << 25) -#define SCIF0_MSTP721 (1 << 21) -#define ETHER_MSTP813 (1 << 13) - -#define SDHI0_MSTP314 (1 << 14) -#define SDHI1_MSTP312 (1 << 12) -#define SDHI2_MSTP311 (1 << 11) +#define TMU0_MSTP125 BIT(25) #define SD1CKCR 0xE6150078 #define SD2CKCR 0xE615026C @@ -60,143 +54,59 @@ void s_init(void) int board_early_init_f(void) { - /* TMU0 */ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); - /* SCIF0 */ - mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); - - /* ETHER */ - mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); - - /* SDHI */ - mstp_clrbits_le32(MSTPSR3, SMSTPCR3, - SDHI0_MSTP314 | SDHI1_MSTP312 | SDHI2_MSTP311); + /* + * SD0 clock is set to 97.5MHz by default. + * Set SD1 and SD2 to the 97.5MHz as well. + */ writel(SD_97500KHZ, SD1CKCR); writel(SD_97500KHZ, SD2CKCR); return 0; } -#define PUPR5 0xE6060114 -#define PUPR5_ETH 0x3FFC0000 -#define PUPR5_ETH_MAGIC (1 << 27) +#define ETHERNET_PHY_RESET 176 /* GPIO 5 22 */ int board_init(void) { /* adress of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - /* Init PFC controller */ - r8a7793_pinmux_init(); - - /* ETHER Enable */ - gpio_request(GPIO_FN_ETH_CRS_DV, NULL); - gpio_request(GPIO_FN_ETH_RX_ER, NULL); - gpio_request(GPIO_FN_ETH_RXD0, NULL); - gpio_request(GPIO_FN_ETH_RXD1, NULL); - gpio_request(GPIO_FN_ETH_LINK, NULL); - gpio_request(GPIO_FN_ETH_REFCLK, NULL); - gpio_request(GPIO_FN_ETH_MDIO, NULL); - gpio_request(GPIO_FN_ETH_TXD1, NULL); - gpio_request(GPIO_FN_ETH_TX_EN, NULL); - gpio_request(GPIO_FN_ETH_TXD0, NULL); - gpio_request(GPIO_FN_ETH_MDC, NULL); - gpio_request(GPIO_FN_IRQ0, NULL); - - mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC); - gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */ - mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC); - - gpio_direction_output(GPIO_GP_5_22, 0); - mdelay(20); - gpio_set_value(GPIO_GP_5_22, 1); - udelay(1); + /* Force ethernet PHY out of reset */ + gpio_request(ETHERNET_PHY_RESET, "phy_reset"); + gpio_direction_output(ETHERNET_PHY_RESET, 0); + mdelay(10); + gpio_direction_output(ETHERNET_PHY_RESET, 1); return 0; } -#define CXR24 0xEE7003C0 /* MAC address high register */ -#define CXR25 0xEE7003C8 /* MAC address low register */ - -int board_eth_init(bd_t *bis) +int dram_init(void) { - int ret = -ENODEV; - u32 val; - unsigned char enetaddr[6]; - -#ifdef CONFIG_SH_ETHER - ret = sh_eth_initialize(bis); - if (!eth_env_get_enetaddr("ethaddr", enetaddr)) - return ret; - - /* Set Mac address */ - val = enetaddr[0] << 24 | enetaddr[1] << 16 | - enetaddr[2] << 8 | enetaddr[3]; - writel(val, CXR24); + if (fdtdec_setup_memory_size() != 0) + return -EINVAL; - val = enetaddr[4] << 8 | enetaddr[5]; - writel(val, CXR25); -#endif - - return ret; + return 0; } -int board_mmc_init(bd_t *bis) +int dram_init_banksize(void) { - int ret = -ENODEV; - -#ifdef CONFIG_SH_SDHI - gpio_request(GPIO_FN_SD0_DATA0, NULL); - gpio_request(GPIO_FN_SD0_DATA1, NULL); - gpio_request(GPIO_FN_SD0_DATA2, NULL); - gpio_request(GPIO_FN_SD0_DATA3, NULL); - gpio_request(GPIO_FN_SD0_CLK, NULL); - gpio_request(GPIO_FN_SD0_CMD, NULL); - gpio_request(GPIO_FN_SD0_CD, NULL); - gpio_request(GPIO_FN_SD2_DATA0, NULL); - gpio_request(GPIO_FN_SD2_DATA1, NULL); - gpio_request(GPIO_FN_SD2_DATA2, NULL); - gpio_request(GPIO_FN_SD2_DATA3, NULL); - gpio_request(GPIO_FN_SD2_CLK, NULL); - gpio_request(GPIO_FN_SD2_CMD, NULL); - gpio_request(GPIO_FN_SD2_CD, NULL); - - /* SDHI 0 */ - gpio_request(GPIO_GP_7_17, NULL); - gpio_request(GPIO_GP_2_12, NULL); - gpio_direction_output(GPIO_GP_7_17, 1); /* power on */ - gpio_direction_output(GPIO_GP_2_12, 1); /* 1: 3.3V, 0: 1.8V */ - - ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0, - SH_SDHI_QUIRK_16BIT_BUF); - if (ret) - return ret; - - /* SDHI 1 */ - gpio_request(GPIO_GP_7_18, NULL); - gpio_request(GPIO_GP_2_13, NULL); - gpio_direction_output(GPIO_GP_7_18, 1); /* power on */ - gpio_direction_output(GPIO_GP_2_13, 1); /* 1: 3.3V, 0: 1.8V */ - - ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI1_BASE, 1, 0); - if (ret) - return ret; - - /* SDHI 2 */ - gpio_request(GPIO_GP_7_19, NULL); - gpio_request(GPIO_GP_2_26, NULL); - gpio_direction_output(GPIO_GP_7_19, 1); /* power on */ - gpio_direction_output(GPIO_GP_2_26, 1); /* 1: 3.3V, 0: 1.8V */ + fdtdec_setup_memory_banksize(); - ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0); -#endif - return ret; + return 0; } -int dram_init(void) +/* KSZ8041RNLI */ +#define PHY_CONTROL1 0x1E +#define PHY_LED_MODE 0xC0000 +#define PHY_LED_MODE_ACK 0x4000 +int board_phy_config(struct phy_device *phydev) { - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1); + ret &= ~PHY_LED_MODE; + ret |= PHY_LED_MODE_ACK; + ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret); return 0; } @@ -207,22 +117,38 @@ const struct rmobile_sysinfo sysinfo = { void reset_cpu(ulong addr) { - u8 val; + struct udevice *dev; + const u8 pmic_bus = 6; + const u8 pmic_addr = 0x58; + u8 data; + int ret; + + ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev); + if (ret) + hang(); + + ret = dm_i2c_read(dev, 0x13, &data, 1); + if (ret) + hang(); + + data |= BIT(1); - i2c_set_bus_num(2); /* PowerIC connected to ch2 */ - i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); - val |= 0x02; - i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); + ret = dm_i2c_write(dev, 0x13, &data, 1); + if (ret) + hang(); } -static const struct sh_serial_platdata serial_platdata = { - .base = SCIF0_BASE, - .type = PORT_SCIF, - .clk = 14745600, - .clk_mode = EXT_CLK, -}; +enum env_location env_get_location(enum env_operation op, int prio) +{ + const u32 load_magic = 0xb33fc0de; -U_BOOT_DEVICE(gose_serials) = { - .name = "serial_sh", - .platdata = &serial_platdata, -}; + /* Block environment access if loaded using JTAG */ + if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) && + (op != ENVOP_INIT)) + return ENVL_UNKNOWN; + + if (prio) + return ENVL_UNKNOWN; + + return ENVL_SPI_FLASH; +} diff --git a/board/renesas/gose/gose_spl.c b/board/renesas/gose/gose_spl.c new file mode 100644 index 00000000000..17b9da69d03 --- /dev/null +++ b/board/renesas/gose/gose_spl.c @@ -0,0 +1,408 @@ +/* + * board/renesas/gose/gose_spl.c + * + * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <malloc.h> +#include <dm/platform_data/serial_sh.h> +#include <asm/processor.h> +#include <asm/mach-types.h> +#include <asm/io.h> +#include <linux/errno.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/arch/rmobile.h> +#include <asm/arch/rcar-mstp.h> + +#include <spl.h> + +#define TMU0_MSTP125 BIT(25) +#define SCIF0_MSTP721 BIT(21) +#define QSPI_MSTP917 BIT(17) + +#define SD2CKCR 0xE615026C +#define SD_97500KHZ 0x7 + +struct reg_config { + u16 off; + u32 val; +}; + +static void dbsc_wait(u16 reg) +{ + static const u32 dbsc3_0_base = DBSC3_0_BASE; + + while (!(readl(dbsc3_0_base + reg) & BIT(0))) + ; +} + +static void spl_init_sys(void) +{ + u32 r0 = 0; + + writel(0xa5a5a500, 0xe6020004); + writel(0xa5a5a500, 0xe6030004); + + asm volatile( + /* ICIALLU - Invalidate I$ to PoU */ + "mcr 15, 0, %0, cr7, cr5, 0 \n" + /* BPIALL - Invalidate branch predictors */ + "mcr 15, 0, %0, cr7, cr5, 6 \n" + /* Set SCTLR[IZ] */ + "mrc 15, 0, %0, cr1, cr0, 0 \n" + "orr %0, #0x1800 \n" + "mcr 15, 0, %0, cr1, cr0, 0 \n" + "isb sy \n" + :"=r"(r0)); +} + +static void spl_init_pfc(void) +{ + static const struct reg_config pfc_with_unlock[] = { + { 0x0090, 0x60000000 }, + { 0x0094, 0x60000000 }, + { 0x0098, 0x00800200 }, + { 0x009c, 0x00000000 }, + { 0x0020, 0x00000000 }, + { 0x0024, 0x00000000 }, + { 0x0028, 0x000244c8 }, + { 0x002c, 0x00000000 }, + { 0x0030, 0x00002400 }, + { 0x0034, 0x01520000 }, + { 0x0038, 0x00724003 }, + { 0x003c, 0x00000000 }, + { 0x0040, 0x00000000 }, + { 0x0044, 0x00000000 }, + { 0x0048, 0x00000000 }, + { 0x004c, 0x00000000 }, + { 0x0050, 0x00000000 }, + { 0x0054, 0x00000000 }, + { 0x0058, 0x00000000 }, + { 0x005c, 0x00000000 }, + { 0x0160, 0x00000000 }, + { 0x0004, 0xffffffff }, + { 0x0008, 0x00ec3fff }, + { 0x000c, 0x3bc001e7 }, + { 0x0010, 0x5bffffff }, + { 0x0014, 0x1ffffffb }, + { 0x0018, 0x01bffff0 }, + { 0x001c, 0xcf7fffff }, + { 0x0074, 0x0381fc00 }, + }; + + static const struct reg_config pfc_without_unlock[] = { + { 0x0100, 0xffffffdf }, + { 0x0104, 0xc883c3ff }, + { 0x0108, 0x1201f3c9 }, + { 0x010c, 0x00000000 }, + { 0x0110, 0xffffeb04 }, + { 0x0114, 0xc003ffff }, + { 0x0118, 0x0800000f }, + { 0x011c, 0x001800f0 }, + }; + + static const u32 pfc_base = 0xe6060000; + + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) { + writel(~pfc_with_unlock[i].val, pfc_base); + writel(pfc_with_unlock[i].val, + pfc_base | pfc_with_unlock[i].off); + } + + for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++) + writel(pfc_without_unlock[i].val, + pfc_base | pfc_without_unlock[i].off); +} + +static void spl_init_gpio(void) +{ + static const u16 gpio_offs[] = { + 0x1000, 0x2000, 0x3000, 0x4000, 0x5000, 0x5400, 0x5800 + }; + + static const struct reg_config gpio_set[] = { + { 0x2000, 0x04381000 }, + { 0x5000, 0x00000000 }, + { 0x5800, 0x000e0000 }, + }; + + static const struct reg_config gpio_clr[] = { + { 0x1000, 0x00000000 }, + { 0x2000, 0x04381010 }, + { 0x3000, 0x00000000 }, + { 0x4000, 0x00000000 }, + { 0x5000, 0x00400000 }, + { 0x5400, 0x00000000 }, + { 0x5800, 0x000e0380 }, + }; + + static const u32 gpio_base = 0xe6050000; + + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(gpio_offs); i++) + writel(0, gpio_base | 0x20 | gpio_offs[i]); + + for (i = 0; i < ARRAY_SIZE(gpio_offs); i++) + writel(0, gpio_base | 0x00 | gpio_offs[i]); + + for (i = 0; i < ARRAY_SIZE(gpio_set); i++) + writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off); + + for (i = 0; i < ARRAY_SIZE(gpio_clr); i++) + writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off); +} + +static void spl_init_lbsc(void) +{ + static const struct reg_config lbsc_config[] = { + { 0x00, 0x00000020 }, + { 0x08, 0x00002020 }, + { 0x30, 0x2a103320 }, + { 0x38, 0xff70ff70 }, + }; + + static const u16 lbsc_offs[] = { + 0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180 + }; + + static const u32 lbsc_base = 0xfec00200; + + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) { + writel(lbsc_config[i].val, + lbsc_base | lbsc_config[i].off); + writel(lbsc_config[i].val, + lbsc_base | (lbsc_config[i].off + 4)); + } + + for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++) + writel(0, lbsc_base | lbsc_offs[i]); +} + +static void spl_init_dbsc(void) +{ + static const struct reg_config dbsc_config1[] = { + { 0x0280, 0x0000a55a }, + { 0x0018, 0x21000000 }, + { 0x0018, 0x11000000 }, + { 0x0018, 0x10000000 }, + { 0x0290, 0x00000001 }, + { 0x02a0, 0x80000000 }, + { 0x0290, 0x00000004 }, + }; + + static const struct reg_config dbsc_config2[] = { + { 0x0290, 0x00000006 }, + { 0x02a0, 0x0001c000 }, + }; + + static const struct reg_config dbsc_config4[] = { + { 0x0290, 0x00000010 }, + { 0x02a0, 0xf00464db }, + { 0x0290, 0x00000061 }, + { 0x02a0, 0x0000006d }, + { 0x0290, 0x00000001 }, + { 0x02a0, 0x00000073 }, + { 0x0020, 0x00000007 }, + { 0x0024, 0x0f030a02 }, + { 0x0030, 0x00000001 }, + { 0x00b0, 0x00000000 }, + { 0x0040, 0x0000000b }, + { 0x0044, 0x00000008 }, + { 0x0048, 0x00000000 }, + { 0x0050, 0x0000000b }, + { 0x0054, 0x000c000b }, + { 0x0058, 0x00000027 }, + { 0x005c, 0x0000001c }, + { 0x0060, 0x00000006 }, + { 0x0064, 0x00000020 }, + { 0x0068, 0x00000008 }, + { 0x006c, 0x0000000c }, + { 0x0070, 0x00000009 }, + { 0x0074, 0x00000012 }, + { 0x0078, 0x000000d0 }, + { 0x007c, 0x00140005 }, + { 0x0080, 0x00050004 }, + { 0x0084, 0x70233005 }, + { 0x0088, 0x000c0000 }, + { 0x008c, 0x00000200 }, + { 0x0090, 0x00000040 }, + { 0x0100, 0x00000001 }, + { 0x00c0, 0x00020001 }, + { 0x00c8, 0x20042004 }, + { 0x0380, 0x00020002 }, + { 0x0390, 0x0000001f }, + }; + + static const struct reg_config dbsc_config5[] = { + { 0x0244, 0x00000011 }, + { 0x0290, 0x00000003 }, + { 0x02a0, 0x0300c561 }, + { 0x0290, 0x00000023 }, + { 0x02a0, 0x00fcdb60 }, + { 0x0290, 0x00000011 }, + { 0x02a0, 0x1000040b }, + { 0x0290, 0x00000012 }, + { 0x02a0, 0x9d9cbb66 }, + { 0x0290, 0x00000013 }, + { 0x02a0, 0x1a868400 }, + { 0x0290, 0x00000014 }, + { 0x02a0, 0x300214d8 }, + { 0x0290, 0x00000015 }, + { 0x02a0, 0x00000d70 }, + { 0x0290, 0x00000016 }, + { 0x02a0, 0x00000006 }, + { 0x0290, 0x00000017 }, + { 0x02a0, 0x00000018 }, + { 0x0290, 0x0000001a }, + { 0x02a0, 0x910035c7 }, + { 0x0290, 0x00000004 }, + }; + + static const struct reg_config dbsc_config6[] = { + { 0x0290, 0x00000001 }, + { 0x02a0, 0x00000181 }, + { 0x0018, 0x11000000 }, + { 0x0290, 0x00000004 }, + }; + + static const struct reg_config dbsc_config7[] = { + { 0x0290, 0x00000001 }, + { 0x02a0, 0x0000fe01 }, + { 0x0304, 0x00000000 }, + { 0x00f4, 0x01004c20 }, + { 0x00f8, 0x014000aa }, + { 0x00e0, 0x00000140 }, + { 0x00e4, 0x00081860 }, + { 0x00e8, 0x00010000 }, + { 0x0290, 0x00000004 }, + }; + + static const struct reg_config dbsc_config8[] = { + { 0x0014, 0x00000001 }, + { 0x0010, 0x00000001 }, + { 0x0280, 0x00000000 }, + }; + + static const u32 dbsc3_0_base = DBSC3_0_BASE; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++) + writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off); + + dbsc_wait(0x2a0); + + for (i = 0; i < ARRAY_SIZE(dbsc_config2); i++) + writel(dbsc_config2[i].val, dbsc3_0_base | dbsc_config2[i].off); + + for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++) + writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off); + + dbsc_wait(0x240); + + for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++) + writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off); + + dbsc_wait(0x2a0); + + for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++) + writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off); + + dbsc_wait(0x2a0); + + for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++) + writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off); + + dbsc_wait(0x2a0); + + for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++) + writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off); + +} + +static void spl_init_qspi(void) +{ + mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917); + + static const u32 qspi_base = 0xe6b10000; + + writeb(0x08, qspi_base + 0x00); + writeb(0x00, qspi_base + 0x01); + writeb(0x06, qspi_base + 0x02); + writeb(0x01, qspi_base + 0x0a); + writeb(0x00, qspi_base + 0x0b); + writeb(0x00, qspi_base + 0x0c); + writeb(0x00, qspi_base + 0x0d); + writeb(0x00, qspi_base + 0x0e); + + writew(0xe080, qspi_base + 0x10); + + writeb(0xc0, qspi_base + 0x18); + writeb(0x00, qspi_base + 0x18); + writeb(0x00, qspi_base + 0x08); + writeb(0x48, qspi_base + 0x00); +} + +void board_init_f(ulong dummy) +{ + mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); + mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); + + /* + * SD0 clock is set to 97.5MHz by default. + * Set SD2 to the 97.5MHz as well. + */ + writel(SD_97500KHZ, SD2CKCR); + + spl_init_sys(); + spl_init_pfc(); + spl_init_gpio(); + spl_init_lbsc(); + spl_init_dbsc(); + spl_init_qspi(); +} + +void spl_board_init(void) +{ + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); +} + +void board_boot_order(u32 *spl_boot_list) +{ + const u32 jtag_magic = 0x1337c0de; + const u32 load_magic = 0xb33fc0de; + + /* + * If JTAG probe sets special word at 0xe6300020, then it must + * put U-Boot into RAM and SPL will start it from RAM. + */ + if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) { + printf("JTAG boot detected!\n"); + + while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic) + ; + + spl_boot_list[0] = BOOT_DEVICE_RAM; + spl_boot_list[1] = BOOT_DEVICE_NONE; + + return; + } + + /* Boot from SPI NOR with YMODEM UART fallback. */ + spl_boot_list[0] = BOOT_DEVICE_SPI; + spl_boot_list[1] = BOOT_DEVICE_UART; + spl_boot_list[2] = BOOT_DEVICE_NONE; +} + +void reset_cpu(ulong addr) +{ +} diff --git a/board/renesas/lager/Makefile b/board/renesas/lager/Makefile index 0e44c69fd6a..379368fdfce 100644 --- a/board/renesas/lager/Makefile +++ b/board/renesas/lager/Makefile @@ -6,4 +6,8 @@ # SPDX-License-Identifier: GPL-2.0 # -obj-y := lager.o qos.o ../rcar-common/common.o +ifdef CONFIG_SPL_BUILD +obj-y := lager_spl.o +else +obj-y := lager.o qos.o +endif diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c index 3566bcc7889..505efb5bc46 100644 --- a/board/renesas/lager/lager.c +++ b/board/renesas/lager/lager.c @@ -57,105 +57,60 @@ void s_init(void) qos_init(); } -#define TMU0_MSTP125 (1 << 25) -#define SCIF0_MSTP721 (1 << 21) -#define ETHER_MSTP813 (1 << 13) -#define MMC1_MSTP305 (1 << 5) +#define TMU0_MSTP125 BIT(25) -#define MSTPSR3 0xE6150048 -#define SMSTPCR3 0xE615013C -#define SDHI0_MSTP314 (1 << 14) -#define SDHI1_MSTP313 (1 << 13) -#define SDHI2_MSTP312 (1 << 12) - -#define SD2CKCR 0xE6150078 -#define SD2_97500KHZ 0x7 +#define SD1CKCR 0xE6150078 +#define SD2CKCR 0xE615026C +#define SD_97500KHZ 0x7 int board_early_init_f(void) { - /* TMU0 */ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); - /* SCIF0 */ - mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); - /* ETHER */ - mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); - /* eMMC */ - mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC1_MSTP305); - /* SDHI0, 2 */ - mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SDHI0_MSTP314 | SDHI2_MSTP312); /* * SD0 clock is set to 97.5MHz by default. - * Set SD2 to the 97.5MHz as well. + * Set SD1 and SD2 to the 97.5MHz as well. */ - writel(SD2_97500KHZ, SD2CKCR); + writel(SD_97500KHZ, SD1CKCR); + writel(SD_97500KHZ, SD2CKCR); return 0; } -DECLARE_GLOBAL_DATA_PTR; +#define ETHERNET_PHY_RESET 185 /* GPIO 5 31 */ + int board_init(void) { /* adress of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - /* Init PFC controller */ - r8a7790_pinmux_init(); - - /* ETHER Enable */ - gpio_request(GPIO_FN_ETH_CRS_DV, NULL); - gpio_request(GPIO_FN_ETH_RX_ER, NULL); - gpio_request(GPIO_FN_ETH_RXD0, NULL); - gpio_request(GPIO_FN_ETH_RXD1, NULL); - gpio_request(GPIO_FN_ETH_LINK, NULL); - gpio_request(GPIO_FN_ETH_REF_CLK, NULL); - gpio_request(GPIO_FN_ETH_MDIO, NULL); - gpio_request(GPIO_FN_ETH_TXD1, NULL); - gpio_request(GPIO_FN_ETH_TX_EN, NULL); - gpio_request(GPIO_FN_ETH_MAGIC, NULL); - gpio_request(GPIO_FN_ETH_TXD0, NULL); - gpio_request(GPIO_FN_ETH_MDC, NULL); - gpio_request(GPIO_FN_IRQ0, NULL); - - gpio_request(GPIO_GP_5_31, NULL); /* PHY_RST */ - gpio_direction_output(GPIO_GP_5_31, 0); - mdelay(20); - gpio_set_value(GPIO_GP_5_31, 1); - udelay(1); + /* Force ethernet PHY out of reset */ + gpio_request(ETHERNET_PHY_RESET, "phy_reset"); + gpio_direction_output(ETHERNET_PHY_RESET, 0); + mdelay(10); + gpio_direction_output(ETHERNET_PHY_RESET, 1); return 0; } -#define CXR24 0xEE7003C0 /* MAC address high register */ -#define CXR25 0xEE7003C8 /* MAC address low register */ -int board_eth_init(bd_t *bis) +int dram_init(void) { - int ret = -ENODEV; - -#ifdef CONFIG_SH_ETHER - u32 val; - unsigned char enetaddr[6]; + if (fdtdec_setup_memory_size() != 0) + return -EINVAL; - ret = sh_eth_initialize(bis); - if (!eth_env_get_enetaddr("ethaddr", enetaddr)) - return ret; - - /* Set Mac address */ - val = enetaddr[0] << 24 | enetaddr[1] << 16 | - enetaddr[2] << 8 | enetaddr[3]; - writel(val, CXR24); - - val = enetaddr[4] << 8 | enetaddr[5]; - writel(val, CXR25); + return 0; +} -#endif +int dram_init_banksize(void) +{ + fdtdec_setup_memory_banksize(); - return ret; + return 0; } -/* lager has KSZ8041NL/RNL */ -#define PHY_CONTROL1 0x1E -#define PHY_LED_MODE 0xC0000 +/* KSZ8041NL/RNL */ +#define PHY_CONTROL1 0x1E +#define PHY_LED_MODE 0xC0000 #define PHY_LED_MODE_ACK 0x4000 int board_phy_config(struct phy_device *phydev) { @@ -167,97 +122,44 @@ int board_phy_config(struct phy_device *phydev) return 0; } -int board_mmc_init(bd_t *bis) +const struct rmobile_sysinfo sysinfo = { + CONFIG_ARCH_RMOBILE_BOARD_STRING +}; + +void reset_cpu(ulong addr) { - int ret = -ENODEV; - -#ifdef CONFIG_SH_MMCIF - gpio_request(GPIO_FN_MMC1_D0, NULL); - gpio_request(GPIO_FN_MMC1_D1, NULL); - gpio_request(GPIO_FN_MMC1_D2, NULL); - gpio_request(GPIO_FN_MMC1_D3, NULL); - gpio_request(GPIO_FN_MMC1_D4, NULL); - gpio_request(GPIO_FN_MMC1_D5, NULL); - gpio_request(GPIO_FN_MMC1_D6, NULL); - gpio_request(GPIO_FN_MMC1_D7, NULL); - gpio_request(GPIO_FN_MMC1_CLK, NULL); - gpio_request(GPIO_FN_MMC1_CMD, NULL); - - ret = mmcif_mmc_init(); -#endif - -#ifdef CONFIG_SH_SDHI - gpio_request(GPIO_FN_SD0_DAT0, NULL); - gpio_request(GPIO_FN_SD0_DAT1, NULL); - gpio_request(GPIO_FN_SD0_DAT2, NULL); - gpio_request(GPIO_FN_SD0_DAT3, NULL); - gpio_request(GPIO_FN_SD0_CLK, NULL); - gpio_request(GPIO_FN_SD0_CMD, NULL); - gpio_request(GPIO_FN_SD0_CD, NULL); - gpio_request(GPIO_FN_SD2_DAT0, NULL); - gpio_request(GPIO_FN_SD2_DAT1, NULL); - gpio_request(GPIO_FN_SD2_DAT2, NULL); - gpio_request(GPIO_FN_SD2_DAT3, NULL); - gpio_request(GPIO_FN_SD2_CLK, NULL); - gpio_request(GPIO_FN_SD2_CMD, NULL); - gpio_request(GPIO_FN_SD2_CD, NULL); + struct udevice *dev; + const u8 pmic_bus = 2; + const u8 pmic_addr = 0x58; + u8 data; + int ret; - /* - * SDHI 0 - * need JP3 set to pin-1 side on board. - */ - gpio_request(GPIO_GP_5_24, NULL); - gpio_request(GPIO_GP_5_29, NULL); - gpio_direction_output(GPIO_GP_5_24, 1); /* power on */ - gpio_direction_output(GPIO_GP_5_29, 1); /* 1: 3.3V, 0: 1.8V */ + ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev); + if (ret) + hang(); - ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE, 0, - SH_SDHI_QUIRK_16BIT_BUF); + ret = dm_i2c_read(dev, 0x13, &data, 1); if (ret) - return ret; + hang(); - /* SDHI 2 */ - gpio_request(GPIO_GP_5_25, NULL); - gpio_request(GPIO_GP_5_30, NULL); - gpio_direction_output(GPIO_GP_5_25, 1); /* power on */ - gpio_direction_output(GPIO_GP_5_30, 1); /* 1: 3.3V, 0: 1.8V */ + data |= BIT(1); - ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 2, 0); -#endif - return ret; + ret = dm_i2c_write(dev, 0x13, &data, 1); + if (ret) + hang(); } - -int dram_init(void) +enum env_location env_get_location(enum env_operation op, int prio) { - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + const u32 load_magic = 0xb33fc0de; - return 0; -} + /* Block environment access if loaded using JTAG */ + if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) && + (op != ENVOP_INIT)) + return ENVL_UNKNOWN; -const struct rmobile_sysinfo sysinfo = { - CONFIG_ARCH_RMOBILE_BOARD_STRING -}; - -void reset_cpu(ulong addr) -{ - u8 val; + if (prio) + return ENVL_UNKNOWN; - i2c_set_bus_num(3); /* PowerIC connected to ch3 */ - i2c_init(400000, 0); - i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); - val |= 0x02; - i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); + return ENVL_SPI_FLASH; } - -static const struct sh_serial_platdata serial_platdata = { - .base = SCIF0_BASE, - .type = PORT_SCIF, - .clk = 14745600, - .clk_mode = EXT_CLK, -}; - -U_BOOT_DEVICE(lager_serials) = { - .name = "serial_sh", - .platdata = &serial_platdata, -}; diff --git a/board/renesas/lager/lager_spl.c b/board/renesas/lager/lager_spl.c new file mode 100644 index 00000000000..5730eb2f1ef --- /dev/null +++ b/board/renesas/lager/lager_spl.c @@ -0,0 +1,396 @@ +/* + * board/renesas/lager/lager_spl.c + * + * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <malloc.h> +#include <dm/platform_data/serial_sh.h> +#include <asm/processor.h> +#include <asm/mach-types.h> +#include <asm/io.h> +#include <linux/errno.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/arch/rmobile.h> +#include <asm/arch/rcar-mstp.h> + +#include <spl.h> + +#define TMU0_MSTP125 BIT(25) +#define SCIF0_MSTP721 BIT(21) +#define QSPI_MSTP917 BIT(17) + +#define SD2CKCR 0xE615026C +#define SD_97500KHZ 0x7 + +struct reg_config { + u16 off; + u32 val; +}; + +static void dbsc_wait(u16 reg) +{ + static const u32 dbsc3_0_base = DBSC3_0_BASE; + + while (!(readl(dbsc3_0_base + reg) & BIT(0))) + ; +} + +static void spl_init_sys(void) +{ + u32 r0 = 0; + + writel(0xa5a5a500, 0xe6020004); + writel(0xa5a5a500, 0xe6030004); + + asm volatile( + /* ICIALLU - Invalidate I$ to PoU */ + "mcr 15, 0, %0, cr7, cr5, 0 \n" + /* BPIALL - Invalidate branch predictors */ + "mcr 15, 0, %0, cr7, cr5, 6 \n" + /* Set SCTLR[IZ] */ + "mrc 15, 0, %0, cr1, cr0, 0 \n" + "orr %0, #0x1800 \n" + "mcr 15, 0, %0, cr1, cr0, 0 \n" + "isb sy \n" + :"=r"(r0)); +} + +static void spl_init_pfc(void) +{ + static const struct reg_config pfc_with_unlock[] = { + { 0x0090, 0x00000000 }, + { 0x0094, 0x00000000 }, + { 0x0098, 0xc0000000 }, + { 0x0020, 0x00000000 }, + { 0x0024, 0x00000000 }, + { 0x0028, 0x00000000 }, + { 0x002c, 0x20000000 }, + { 0x0030, 0x00001249 }, + { 0x0034, 0x00000278 }, + { 0x0038, 0x00000841 }, + { 0x003c, 0x00000000 }, + { 0x0040, 0x00000000 }, + { 0x0044, 0x10000000 }, + { 0x0048, 0x00000001 }, + { 0x004c, 0x0004aab0 }, + { 0x0050, 0x37301b00 }, + { 0x0054, 0x00048da3 }, + { 0x0058, 0x089044a1 }, + { 0x005c, 0x2a3a55b4 }, + { 0x0160, 0x00000003 }, + { 0x0004, 0xffffffff }, + { 0x0008, 0x2aef3fff }, + { 0x000c, 0x3fffffff }, + { 0x0010, 0xff7fc07f }, + { 0x0014, 0x7f3ff3f8 }, + { 0x0018, 0x1cfdfff7 }, + }; + + static const struct reg_config pfc_without_unlock[] = { + { 0x0100, 0x1fffffff }, + { 0x0104, 0xffff0318 }, + { 0x0108, 0x387fffe1 }, + { 0x010c, 0x00803f80 }, + { 0x0110, 0x1520009f }, + { 0x0114, 0x00000000 }, + { 0x0118, 0x00000000 }, + }; + + static const u32 pfc_base = 0xe6060000; + + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(pfc_with_unlock); i++) { + writel(~pfc_with_unlock[i].val, pfc_base); + writel(pfc_with_unlock[i].val, + pfc_base | pfc_with_unlock[i].off); + } + + for (i = 0; i < ARRAY_SIZE(pfc_without_unlock); i++) + writel(pfc_without_unlock[i].val, + pfc_base | pfc_without_unlock[i].off); +} + +static void spl_init_gpio(void) +{ + static const u16 gpio_offs[] = { + 0x1000, 0x3000, 0x4000, 0x5000 + }; + + static const struct reg_config gpio_set[] = { + { 0x4000, 0x00c00000 }, + { 0x5000, 0x63020000 }, + }; + + static const struct reg_config gpio_clr[] = { + { 0x1000, 0x00000000 }, + { 0x3000, 0x00000000 }, + { 0x4000, 0x00c00000 }, + { 0x5000, 0xe3020000 }, + }; + + static const u32 gpio_base = 0xe6050000; + + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(gpio_offs); i++) + writel(0, gpio_base | 0x20 | gpio_offs[i]); + + for (i = 0; i < ARRAY_SIZE(gpio_offs); i++) + writel(0, gpio_base | 0x00 | gpio_offs[i]); + + for (i = 0; i < ARRAY_SIZE(gpio_set); i++) + writel(gpio_set[i].val, gpio_base | 0x08 | gpio_set[i].off); + + for (i = 0; i < ARRAY_SIZE(gpio_clr); i++) + writel(gpio_clr[i].val, gpio_base | 0x04 | gpio_clr[i].off); +} + +static void spl_init_lbsc(void) +{ + static const struct reg_config lbsc_config[] = { + { 0x00, 0x00000020 }, + { 0x08, 0x00002020 }, + { 0x30, 0x02150326 }, + { 0x38, 0x077f077f }, + }; + + static const u16 lbsc_offs[] = { + 0x80, 0x84, 0x88, 0x8c, 0xa0, 0xc0, 0xc4, 0xc8, 0x180 + }; + + static const u32 lbsc_base = 0xfec00200; + + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(lbsc_config); i++) { + writel(lbsc_config[i].val, + lbsc_base | lbsc_config[i].off); + writel(lbsc_config[i].val, + lbsc_base | (lbsc_config[i].off + 4)); + } + + for (i = 0; i < ARRAY_SIZE(lbsc_offs); i++) + writel(0, lbsc_base | lbsc_offs[i]); +} + +static void spl_init_dbsc(void) +{ + static const struct reg_config dbsc_config1[] = { + { 0x0018, 0x21000000 }, + { 0x0018, 0x11000000 }, + { 0x0018, 0x10000000 }, + { 0x0280, 0x0000a55a }, + { 0x0290, 0x00000001 }, + { 0x02a0, 0x80000000 }, + { 0x0290, 0x00000004 }, + }; + + static const struct reg_config dbsc_config4[] = { + { 0x0290, 0x00000010 }, + { 0x02a0, 0xf004649b }, + { 0x0290, 0x0000000f }, + { 0x02a0, 0x00181ee4 }, + { 0x0290, 0x00000060 }, + { 0x02a0, 0x330657b2 }, + { 0x0290, 0x00000001 }, + { 0x02a0, 0x00000071 }, + { 0x0020, 0x00000007 }, + { 0x0024, 0x10030a02 }, + { 0x0030, 0x00000001 }, + { 0x00b0, 0x00000000 }, + { 0x0040, 0x0000000b }, + { 0x0044, 0x00000008 }, + { 0x0048, 0x00000000 }, + { 0x0050, 0x0000000b }, + { 0x0054, 0x000c000b }, + { 0x0058, 0x00000027 }, + { 0x005c, 0x0000001c }, + { 0x0060, 0x00000005 }, + { 0x0064, 0x00000018 }, + { 0x0068, 0x00000008 }, + { 0x006c, 0x0000000c }, + { 0x0070, 0x00000009 }, + { 0x0074, 0x00000012 }, + { 0x0078, 0x000000d0 }, + { 0x007c, 0x00140005 }, + { 0x0080, 0x00050004 }, + { 0x0084, 0x70233005 }, + { 0x0088, 0x000c0000 }, + { 0x008c, 0x00000300 }, + { 0x0090, 0x00000040 }, + { 0x0100, 0x00000001 }, + { 0x00c0, 0x00020001 }, + { 0x00c8, 0x20082008 }, + { 0x0380, 0x00020002 }, + { 0x0390, 0x0000000f }, + }; + + static const struct reg_config dbsc_config5[] = { + { 0x0244, 0x00000011 }, + { 0x0290, 0x00000006 }, + { 0x02a0, 0x0005c000 }, + { 0x0290, 0x00000003 }, + { 0x02a0, 0x0300c481 }, + { 0x0290, 0x00000023 }, + { 0x02a0, 0x00fdb6c0 }, + { 0x0290, 0x00000011 }, + { 0x02a0, 0x1000040b }, + { 0x0290, 0x00000012 }, + { 0x02a0, 0x9d5cbb66 }, + { 0x0290, 0x00000013 }, + { 0x02a0, 0x1a868300 }, + { 0x0290, 0x00000014 }, + { 0x02a0, 0x300214d8 }, + { 0x0290, 0x00000015 }, + { 0x02a0, 0x00000d70 }, + { 0x0290, 0x00000016 }, + { 0x02a0, 0x00000006 }, + { 0x0290, 0x00000017 }, + { 0x02a0, 0x00000018 }, + { 0x0290, 0x0000001a }, + { 0x02a0, 0x910035c7 }, + { 0x0290, 0x00000004 }, + }; + + static const struct reg_config dbsc_config6[] = { + { 0x0290, 0x00000001 }, + { 0x02a0, 0x00000181 }, + { 0x0018, 0x11000000 }, + { 0x0290, 0x00000004 }, + }; + + static const struct reg_config dbsc_config7[] = { + { 0x0290, 0x00000001 }, + { 0x02a0, 0x0000fe01 }, + { 0x0290, 0x00000004 }, + }; + + static const struct reg_config dbsc_config8[] = { + { 0x0304, 0x00000000 }, + { 0x00f4, 0x01004c20 }, + { 0x00f8, 0x014000aa }, + { 0x00e0, 0x00000140 }, + { 0x00e4, 0x00081860 }, + { 0x00e8, 0x00010000 }, + { 0x0014, 0x00000001 }, + { 0x0010, 0x00000001 }, + { 0x0280, 0x00000000 }, + }; + + static const u32 dbsc3_0_base = DBSC3_0_BASE; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(dbsc_config1); i++) + writel(dbsc_config1[i].val, dbsc3_0_base | dbsc_config1[i].off); + + dbsc_wait(0x2a0); + + for (i = 0; i < ARRAY_SIZE(dbsc_config4); i++) + writel(dbsc_config4[i].val, dbsc3_0_base | dbsc_config4[i].off); + + dbsc_wait(0x240); + + for (i = 0; i < ARRAY_SIZE(dbsc_config5); i++) + writel(dbsc_config5[i].val, dbsc3_0_base | dbsc_config5[i].off); + + dbsc_wait(0x2a0); + + for (i = 0; i < ARRAY_SIZE(dbsc_config6); i++) + writel(dbsc_config6[i].val, dbsc3_0_base | dbsc_config6[i].off); + + dbsc_wait(0x2a0); + + for (i = 0; i < ARRAY_SIZE(dbsc_config7); i++) + writel(dbsc_config7[i].val, dbsc3_0_base | dbsc_config7[i].off); + + dbsc_wait(0x2a0); + + for (i = 0; i < ARRAY_SIZE(dbsc_config8); i++) + writel(dbsc_config8[i].val, dbsc3_0_base | dbsc_config8[i].off); + +} + +static void spl_init_qspi(void) +{ + mstp_clrbits_le32(MSTPSR9, SMSTPCR9, QSPI_MSTP917); + + static const u32 qspi_base = 0xe6b10000; + + writeb(0x08, qspi_base + 0x00); + writeb(0x00, qspi_base + 0x01); + writeb(0x06, qspi_base + 0x02); + writeb(0x01, qspi_base + 0x0a); + writeb(0x00, qspi_base + 0x0b); + writeb(0x00, qspi_base + 0x0c); + writeb(0x00, qspi_base + 0x0d); + writeb(0x00, qspi_base + 0x0e); + + writew(0xe080, qspi_base + 0x10); + + writeb(0xc0, qspi_base + 0x18); + writeb(0x00, qspi_base + 0x18); + writeb(0x00, qspi_base + 0x08); + writeb(0x48, qspi_base + 0x00); +} + +void board_init_f(ulong dummy) +{ + mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); + mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721); + + /* + * SD0 clock is set to 97.5MHz by default. + * Set SD2 to the 97.5MHz as well. + */ + writel(SD_97500KHZ, SD2CKCR); + + spl_init_sys(); + spl_init_pfc(); + spl_init_gpio(); + spl_init_lbsc(); + spl_init_dbsc(); + spl_init_qspi(); +} + +void spl_board_init(void) +{ + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); +} + +void board_boot_order(u32 *spl_boot_list) +{ + const u32 jtag_magic = 0x1337c0de; + const u32 load_magic = 0xb33fc0de; + + /* + * If JTAG probe sets special word at 0xe6300020, then it must + * put U-Boot into RAM and SPL will start it from RAM. + */ + if (readl(CONFIG_SPL_TEXT_BASE + 0x20) == jtag_magic) { + printf("JTAG boot detected!\n"); + + while (readl(CONFIG_SPL_TEXT_BASE + 0x24) != load_magic) + ; + + spl_boot_list[0] = BOOT_DEVICE_RAM; + spl_boot_list[1] = BOOT_DEVICE_NONE; + + return; + } + + /* Boot from SPI NOR with YMODEM UART fallback. */ + spl_boot_list[0] = BOOT_DEVICE_SPI; + spl_boot_list[1] = BOOT_DEVICE_UART; + spl_boot_list[2] = BOOT_DEVICE_NONE; +} + +void reset_cpu(ulong addr) +{ +} diff --git a/board/renesas/silk/silk.c b/board/renesas/silk/silk.c index bfe9909dafe..c932c255a08 100644 --- a/board/renesas/silk/silk.c +++ b/board/renesas/silk/silk.c @@ -114,7 +114,7 @@ void reset_cpu(ulong addr) { struct udevice *dev; const u8 pmic_bus = 1; - const u8 pmic_addr = 0x58; + const u8 pmic_addr = 0x5a; u8 data; int ret; diff --git a/board/rockchip/evb_rk3036/evb_rk3036.c b/board/rockchip/evb_rk3036/evb_rk3036.c index 288370a80b1..86187e37c2d 100644 --- a/board/rockchip/evb_rk3036/evb_rk3036.c +++ b/board/rockchip/evb_rk3036/evb_rk3036.c @@ -10,8 +10,6 @@ #include <asm/arch/uart.h> #include <asm/arch/sdram_rk3036.h> -DECLARE_GLOBAL_DATA_PTR; - void get_ddr_config(struct rk3036_ddr_config *config) { /* K4B4G1646Q config */ diff --git a/board/rockchip/evb_rk3229/evb_rk3229.c b/board/rockchip/evb_rk3229/evb_rk3229.c index a9a3a40ce82..5fe1868f61e 100644 --- a/board/rockchip/evb_rk3229/evb_rk3229.c +++ b/board/rockchip/evb_rk3229/evb_rk3229.c @@ -9,4 +9,3 @@ #include <asm/io.h> #include <asm/arch/uart.h> -DECLARE_GLOBAL_DATA_PTR; diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c b/board/rockchip/evb_rk3399/evb-rk3399.c index 502dec325fc..0f9267b68e4 100644 --- a/board/rockchip/evb_rk3399/evb-rk3399.c +++ b/board/rockchip/evb_rk3399/evb-rk3399.c @@ -12,8 +12,6 @@ #include <power/regulator.h> #include <spl.h> -DECLARE_GLOBAL_DATA_PTR; - int board_init(void) { struct udevice *pinctrl, *regulator; diff --git a/board/rockchip/kylin_rk3036/kylin_rk3036.c b/board/rockchip/kylin_rk3036/kylin_rk3036.c index 91349948740..e1af124e325 100644 --- a/board/rockchip/kylin_rk3036/kylin_rk3036.c +++ b/board/rockchip/kylin_rk3036/kylin_rk3036.c @@ -11,8 +11,6 @@ #include <asm/arch/sdram_rk3036.h> #include <asm/gpio.h> -DECLARE_GLOBAL_DATA_PTR; - void get_ddr_config(struct rk3036_ddr_config *config) { /* K4B4G1646Q config */ diff --git a/board/rockchip/sheep_rk3368/sheep_rk3368.c b/board/rockchip/sheep_rk3368/sheep_rk3368.c index 17adb02469d..348818cbf0f 100644 --- a/board/rockchip/sheep_rk3368/sheep_rk3368.c +++ b/board/rockchip/sheep_rk3368/sheep_rk3368.c @@ -9,8 +9,6 @@ #include <asm/arch/grf_rk3368.h> #include <syscon.h> -DECLARE_GLOBAL_DATA_PTR; - int mach_cpu_init(void) { return 0; diff --git a/board/samsung/espresso7420/espresso7420.c b/board/samsung/espresso7420/espresso7420.c index 04a83bc07d7..1ed86800100 100644 --- a/board/samsung/espresso7420/espresso7420.c +++ b/board/samsung/espresso7420/espresso7420.c @@ -8,8 +8,6 @@ #include <common.h> -DECLARE_GLOBAL_DATA_PTR; - int exynos_init(void) { return 0; diff --git a/board/samsung/origen/origen.c b/board/samsung/origen/origen.c index 99a2facd1ee..3d27a9433bf 100644 --- a/board/samsung/origen/origen.c +++ b/board/samsung/origen/origen.c @@ -13,8 +13,6 @@ #include <asm/arch/pinmux.h> #include <usb.h> -DECLARE_GLOBAL_DATA_PTR; - u32 get_board_rev(void) { return 0; diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index f0913383b97..781b5799675 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -30,8 +30,6 @@ #include "setup.h" -DECLARE_GLOBAL_DATA_PTR; - unsigned int board_rev; #ifdef CONFIG_REVISION_TAG diff --git a/board/samsung/trats2/trats2.c b/board/samsung/trats2/trats2.c index f9acbd35712..6abafeb1b3e 100644 --- a/board/samsung/trats2/trats2.c +++ b/board/samsung/trats2/trats2.c @@ -24,8 +24,6 @@ #include <usb/dwc2_udc.h> #include <usb_mass_storage.h> -DECLARE_GLOBAL_DATA_PTR; - static unsigned int board_rev = -1; static inline u32 get_model_rev(void); diff --git a/board/sbc8349/pci.c b/board/sbc8349/pci.c index e792fe313d0..9b1560bd777 100644 --- a/board/sbc8349/pci.c +++ b/board/sbc8349/pci.c @@ -16,8 +16,6 @@ #include <i2c.h> #include <asm/fsl_i2c.h> -DECLARE_GLOBAL_DATA_PTR; - static struct pci_region pci1_regions[] = { { bus_start: CONFIG_SYS_PCI1_MEM_BASE, diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 1a48a6c89f2..566777cf7fb 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -24,8 +24,6 @@ #include <linux/libfdt.h> #include <fdt_support.h> -DECLARE_GLOBAL_DATA_PTR; - void local_bus_init(void); int board_early_init_f (void) diff --git a/board/siemens/draco/board.c b/board/siemens/draco/board.c index c705b5ab0f6..c7a6a7aaa38 100644 --- a/board/siemens/draco/board.c +++ b/board/siemens/draco/board.c @@ -36,8 +36,6 @@ #include "../common/factoryset.h" #include <nand.h> -DECLARE_GLOBAL_DATA_PTR; - #ifdef CONFIG_SPL_BUILD static struct draco_baseboard_id __attribute__((section(".data"))) settings; diff --git a/board/siemens/pxm2/board.c b/board/siemens/pxm2/board.c index ab54e58861a..7339135050f 100644 --- a/board/siemens/pxm2/board.c +++ b/board/siemens/pxm2/board.c @@ -39,8 +39,6 @@ #include <nand.h> #include <bmp_layout.h> -DECLARE_GLOBAL_DATA_PTR; - #ifdef CONFIG_SPL_BUILD static void board_init_ddr(void) { diff --git a/board/siemens/rut/board.c b/board/siemens/rut/board.c index 2a97414bafa..ed5cde3a0b7 100644 --- a/board/siemens/rut/board.c +++ b/board/siemens/rut/board.c @@ -35,8 +35,6 @@ #include "../common/factoryset.h" #include "../../../drivers/video/da8xx-fb.h" -DECLARE_GLOBAL_DATA_PTR; - /* * Read header information from EEPROM into global structure. */ diff --git a/board/theobroma-systems/lion_rk3368/lion_rk3368.c b/board/theobroma-systems/lion_rk3368/lion_rk3368.c index 73b14883c31..c8fe4d5678a 100644 --- a/board/theobroma-systems/lion_rk3368/lion_rk3368.c +++ b/board/theobroma-systems/lion_rk3368/lion_rk3368.c @@ -12,8 +12,6 @@ #include <asm/arch/timer.h> #include <syscon.h> -DECLARE_GLOBAL_DATA_PTR; - int mach_cpu_init(void) { return 0; diff --git a/board/theobroma-systems/puma_rk3399/puma-rk3399.c b/board/theobroma-systems/puma_rk3399/puma-rk3399.c index 1d8b605b693..a5371fc0783 100644 --- a/board/theobroma-systems/puma_rk3399/puma-rk3399.c +++ b/board/theobroma-systems/puma_rk3399/puma-rk3399.c @@ -24,8 +24,6 @@ #include <power/regulator.h> #include <u-boot/sha256.h> -DECLARE_GLOBAL_DATA_PTR; - int board_init(void) { int ret; diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index c33bf58ddcb..896b9b63bbb 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -243,9 +243,11 @@ static struct emif_regs ddr3_icev2_emif_reg_data = { #ifdef CONFIG_SPL_OS_BOOT int spl_start_uboot(void) { +#ifdef CONFIG_SPL_SERIAL_SUPPORT /* break into full u-boot on 'c' */ if (serial_tstc() && serial_getc() == 'c') return 1; +#endif #ifdef CONFIG_SPL_ENV_SUPPORT env_init(); diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c index 6c77d915e5b..e96636b6ecb 100644 --- a/board/ti/ks2_evm/board_k2e.c +++ b/board/ti/ks2_evm/board_k2e.c @@ -12,8 +12,6 @@ #include <asm/arch/hardware.h> #include <asm/ti-common/keystone_net.h> -DECLARE_GLOBAL_DATA_PTR; - unsigned int get_external_clk(u32 clk) { unsigned int clk_freq; diff --git a/board/ti/ks2_evm/board_k2hk.c b/board/ti/ks2_evm/board_k2hk.c index e99e6355b47..d61f72921ae 100644 --- a/board/ti/ks2_evm/board_k2hk.c +++ b/board/ti/ks2_evm/board_k2hk.c @@ -12,8 +12,6 @@ #include <asm/arch/hardware.h> #include <asm/ti-common/keystone_net.h> -DECLARE_GLOBAL_DATA_PTR; - unsigned int external_clk[ext_clk_count] = { [sys_clk] = 122880000, [alt_core_clk] = 125000000, diff --git a/board/ti/ks2_evm/board_k2l.c b/board/ti/ks2_evm/board_k2l.c index c65f33131da..b114c246905 100644 --- a/board/ti/ks2_evm/board_k2l.c +++ b/board/ti/ks2_evm/board_k2l.c @@ -12,8 +12,6 @@ #include <asm/arch/hardware.h> #include <asm/ti-common/keystone_net.h> -DECLARE_GLOBAL_DATA_PTR; - unsigned int get_external_clk(u32 clk) { unsigned int clk_freq; diff --git a/board/toradex/colibri_vf/dcu.c b/board/toradex/colibri_vf/dcu.c index 3fa6a763d81..c0add005eb1 100644 --- a/board/toradex/colibri_vf/dcu.c +++ b/board/toradex/colibri_vf/dcu.c @@ -11,8 +11,6 @@ #include <fsl_dcu_fb.h> #include "div64.h" -DECLARE_GLOBAL_DATA_PTR; - unsigned int dcu_set_pixel_clock(unsigned int pixclock) { struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; diff --git a/board/tplink/wdr4300/wdr4300.c b/board/tplink/wdr4300/wdr4300.c index 0f59648b1fe..ac265579e83 100644 --- a/board/tplink/wdr4300/wdr4300.c +++ b/board/tplink/wdr4300/wdr4300.c @@ -13,8 +13,6 @@ #include <mach/ddr.h> #include <debug_uart.h> -DECLARE_GLOBAL_DATA_PTR; - #ifdef CONFIG_USB static void wdr4300_usb_start(void) { diff --git a/board/tqc/tqm834x/pci.c b/board/tqc/tqm834x/pci.c index 1acec849683..43ecdf14954 100644 --- a/board/tqc/tqm834x/pci.c +++ b/board/tqc/tqm834x/pci.c @@ -14,8 +14,6 @@ #include <i2c.h> #include <asm/fsl_i2c.h> -DECLARE_GLOBAL_DATA_PTR; - static struct pci_region pci1_regions[] = { { bus_start: CONFIG_SYS_PCI1_MEM_BASE, diff --git a/board/tqc/tqma6/tqma6_mba6.c b/board/tqc/tqma6/tqma6_mba6.c index be4c132fbe0..37ad916853d 100644 --- a/board/tqc/tqma6/tqma6_mba6.c +++ b/board/tqc/tqma6/tqma6_mba6.c @@ -30,8 +30,6 @@ #include "tqma6_bb.h" -DECLARE_GLOBAL_DATA_PTR; - #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) diff --git a/board/udoo/udoo_spl.c b/board/udoo/udoo_spl.c index 694055bd2e5..c862ed15d9f 100644 --- a/board/udoo/udoo_spl.c +++ b/board/udoo/udoo_spl.c @@ -21,8 +21,6 @@ #include <asm/arch/sys_proto.h> #include <spl.h> -DECLARE_GLOBAL_DATA_PTR; - #if defined(CONFIG_SPL_BUILD) #include <asm/arch/mx6-ddr.h> diff --git a/board/varisys/cyrus/cyrus.c b/board/varisys/cyrus/cyrus.c index f4586272b1f..1daea066a32 100644 --- a/board/varisys/cyrus/cyrus.c +++ b/board/varisys/cyrus/cyrus.c @@ -22,8 +22,6 @@ #include "cyrus.h" #include "../common/eeprom.h" -DECLARE_GLOBAL_DATA_PTR; - #define GPIO_OPENDRAIN 0x30000000 #define GPIO_DIR 0x3c000004 #define GPIO_INITIAL 0x30000000 diff --git a/board/wandboard/spl.c b/board/wandboard/spl.c index 5b9622e75ec..d03ab439422 100644 --- a/board/wandboard/spl.c +++ b/board/wandboard/spl.c @@ -20,8 +20,6 @@ #include <asm/arch/sys_proto.h> #include <spl.h> -DECLARE_GLOBAL_DATA_PTR; - #if defined(CONFIG_SPL_BUILD) #include <asm/arch/mx6-ddr.h> /* diff --git a/board/xes/xpedite537x/xpedite537x.c b/board/xes/xpedite537x/xpedite537x.c index ae606f5ba70..785533d7f2c 100644 --- a/board/xes/xpedite537x/xpedite537x.c +++ b/board/xes/xpedite537x/xpedite537x.c @@ -16,8 +16,6 @@ #include <fdt_support.h> #include <pca953x.h> -DECLARE_GLOBAL_DATA_PTR; - extern void ft_board_pci_setup(void *blob, bd_t *bd); static void flash_cs_fixup(void) diff --git a/board/xes/xpedite550x/xpedite550x.c b/board/xes/xpedite550x/xpedite550x.c index c90bb89dae0..080197c1c6d 100644 --- a/board/xes/xpedite550x/xpedite550x.c +++ b/board/xes/xpedite550x/xpedite550x.c @@ -16,8 +16,6 @@ #include <fdt_support.h> #include <pca953x.h> -DECLARE_GLOBAL_DATA_PTR; - extern void ft_board_pci_setup(void *blob, bd_t *bd); static void flash_cs_fixup(void) |