diff options
Diffstat (limited to 'board')
42 files changed, 1130 insertions, 411 deletions
diff --git a/board/BuR/brxre1/Makefile b/board/BuR/brxre1/Makefile index 1cf7124dbd..1d224e9e71 100644 --- a/board/BuR/brxre1/Makefile +++ b/board/BuR/brxre1/Makefile @@ -6,5 +6,6 @@ # Bernecker & Rainer Industrielektronik GmbH - http://www.br-automation.com/ obj-$(CONFIG_SPL_BUILD) += mux.o +obj-y += ../common/br_resetc.o obj-y += ../common/common.o obj-y += board.o diff --git a/board/BuR/brxre1/board.c b/board/BuR/brxre1/board.c index 2d0ed41dde..0d1c6c4720 100644 --- a/board/BuR/brxre1/board.c +++ b/board/BuR/brxre1/board.c @@ -23,59 +23,28 @@ #include <asm/emif.h> #include <asm/gpio.h> #include <dm.h> -#include <i2c.h> #include <power/tps65217.h> #include "../common/bur_common.h" -#include <lcd.h> +#include "../common/br_resetc.h" /* -------------------------------------------------------------------------*/ /* -- defines for used GPIO Hardware -- */ -#define ESC_KEY (0+19) -#define LCD_PWR (0+5) -#define PUSH_KEY (0+31) -/* -------------------------------------------------------------------------*/ -/* -- PSOC Resetcontroller Register defines -- */ - -/* I2C Address of controller */ -#define RSTCTRL_ADDR 0x75 -/* Register for CTRL-word */ -#define RSTCTRL_CTRLREG 0x01 -/* Register for giving some information to VxWorks OS */ -#define RSTCTRL_SCRATCHREG 0x04 +#define ESC_KEY (0 + 19) +#define LCD_PWR (0 + 5) -/* -- defines for RSTCTRL_CTRLREG -- */ -#define RSTCTRL_FORCE_PWR_NEN 0x0404 -#define RSTCTRL_CAN_STB 0x4040 +#define RSTCTRL_FORCE_PWR_NEN 0x04 +#define RSTCTRL_CAN_STB 0x40 DECLARE_GLOBAL_DATA_PTR; -static int rstctrl_rw(u8 reg, unsigned char rnw, void *pdat, int size) -{ - struct udevice *i2cdev; - int rc; - - rc = i2c_get_chip_for_busnum(0, RSTCTRL_ADDR, 1, &i2cdev); - if (rc >= 0) { - if (rnw) - rc = dm_i2c_read(i2cdev, reg, pdat, size); - else - rc = dm_i2c_write(i2cdev, reg, pdat, size); - } else { - printf("%s: cannot get udevice for chip 0x%02x!\n", - __func__, RSTCTRL_ADDR); - } - - return rc; -} - #if defined(CONFIG_SPL_BUILD) -/* TODO: check ram-timing ! */ static const struct ddr_data ddr3_data = { .datardsratio0 = MT41K256M16HA125E_RD_DQS, .datawdsratio0 = MT41K256M16HA125E_WR_DQS, .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, }; + static const struct cmd_control ddr3_cmd_ctrl_data = { .cmd0csratio = MT41K256M16HA125E_RATIO, .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, @@ -86,6 +55,7 @@ static const struct cmd_control ddr3_cmd_ctrl_data = { .cmd2csratio = MT41K256M16HA125E_RATIO, .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, }; + static struct emif_regs ddr3_emif_reg_data = { .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, @@ -104,12 +74,11 @@ static const struct ctrl_ioregs ddr3_ioregs = { .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, }; -#define OSC (V_OSCK/1000000) -const struct dpll_params dpll_ddr3 = { 400, OSC-1, 1, -1, -1, -1, -1}; +#define OSC (V_OSCK / 1000000) +const struct dpll_params dpll_ddr3 = { 400, OSC - 1, 1, -1, -1, -1, -1}; void am33xx_spl_board_init(void) { - unsigned short buf; int rc; struct cm_perpll *const cmper = (struct cm_perpll *)CM_PER; @@ -143,10 +112,10 @@ void am33xx_spl_board_init(void) enable_i2c_pin_mux(); /* power-ON 3V3 via Resetcontroller */ - buf = RSTCTRL_FORCE_PWR_NEN | RSTCTRL_CAN_STB; - rc = rstctrl_rw(RSTCTRL_CTRLREG, 0, (uint8_t *)&buf, sizeof(buf)); + rc = br_resetc_regset(RSTCTRL_CTRLREG, + RSTCTRL_FORCE_PWR_NEN | RSTCTRL_CAN_STB); if (rc != 0) - printf("ERROR: cannot write to resetc (turn on PWR_nEN)\n"); + printf("ERROR: cannot write to resetc (turn on PWR_nEN)!\n"); pmicsetup(0, 0); } @@ -169,6 +138,9 @@ void sdram_init(void) */ int board_init(void) { + /* request common used gpios */ + gpio_request(ESC_KEY, "boot-key"); + if (power_tps65217_init(0)) printf("WARN: cannot setup PMIC 0x24 @ bus #0, not found!.\n"); @@ -176,121 +148,23 @@ int board_init(void) } #ifdef CONFIG_BOARD_LATE_INIT -int board_late_init(void) -{ - const unsigned int toff = 1000; - unsigned int cnt = 3; - unsigned short buf = 0xAAAA; - unsigned char scratchreg = 0; - int rc; - /* try to read out some boot-instruction from resetcontroller */ - rc = rstctrl_rw(RSTCTRL_SCRATCHREG, 1, &scratchreg, sizeof(scratchreg)); - if (rc != 0) - printf("ERROR: read scratchregister (resetc) failed!\n"); +int board_boot_key(void) +{ + return gpio_get_value(ESC_KEY); +} - if (gpio_request(ESC_KEY, "boot-key") != 0) { - printf("cannot request boot-key!\n"); - } else if (gpio_get_value(ESC_KEY)) { - do { - lcd_position_cursor(1, 8); - switch (cnt) { - case 3: - lcd_puts( - "release ESC-KEY to enter SERVICE-mode."); - break; - case 2: - lcd_puts( - "release ESC-KEY to enter DIAGNOSE-mode."); - break; - case 1: - lcd_puts( - "release ESC-KEY to enter BOOT-mode. "); - break; - } - mdelay(toff); - cnt--; - if (!gpio_get_value(ESC_KEY) && - gpio_get_value(PUSH_KEY) && 2 == cnt) { - lcd_position_cursor(1, 8); - lcd_puts( - "switching to network-console ... "); - env_set("bootcmd", "run netconsole"); - cnt = 4; - break; - } else if (!gpio_get_value(ESC_KEY) && - gpio_get_value(PUSH_KEY) && 1 == cnt) { - lcd_position_cursor(1, 8); - lcd_puts( - "starting u-boot script from USB ... "); - env_set("bootcmd", "run usbscript"); - cnt = 4; - break; - } else if ((!gpio_get_value(ESC_KEY) && - gpio_get_value(PUSH_KEY) && cnt == 0) || - (gpio_get_value(ESC_KEY) && - gpio_get_value(PUSH_KEY) && cnt == 0)) { - lcd_position_cursor(1, 8); - lcd_puts( - "starting script from network ... "); - env_set("bootcmd", "run netscript"); - cnt = 4; - break; - } else if (!gpio_get_value(ESC_KEY)) { - break; - } - } while (cnt); - } else if (scratchreg == 0xCC) { - lcd_position_cursor(1, 8); - lcd_puts( - "starting vxworks from network ... "); - env_set("bootcmd", "run netboot"); - cnt = 4; - } else if (scratchreg == 0xCD) { - lcd_position_cursor(1, 8); - lcd_puts( - "starting script from network ... "); - env_set("bootcmd", "run netscript"); - cnt = 4; - } else if (scratchreg == 0xCE) { - lcd_position_cursor(1, 8); - lcd_puts( - "starting AR from eMMC ... "); - env_set("bootcmd", "run mmcboot"); - cnt = 4; - } +int board_late_init(void) +{ + char othbootargs[128]; - lcd_position_cursor(1, 8); - switch (cnt) { - case 0: - lcd_puts("entering BOOT-mode. "); - env_set("bootcmd", "run defaultAR"); - buf = 0x0000; - break; - case 1: - lcd_puts("entering DIAGNOSE-mode. "); - buf = 0x0F0F; - break; - case 2: - lcd_puts("entering SERVICE mode. "); - buf = 0xB4B4; - break; - case 3: - lcd_puts("loading OS... "); - buf = 0x0404; - break; - } - /* write bootinfo into scratchregister of resetcontroller */ - rc = rstctrl_rw(RSTCTRL_SCRATCHREG, 0, (uint8_t *)&buf, sizeof(buf)); - if (rc != 0) - printf("ERROR: write scratchregister (resetc) failed!\n"); + br_resetc_bmode(); /* setup othbootargs for bootvx-command (vxWorks bootline) */ - char othbootargs[128]; snprintf(othbootargs, sizeof(othbootargs), "u=vxWorksFTP pw=vxWorks o=0x%08x;0x%08x;0x%08x;0x%08x", - (unsigned int) gd->fb_base-0x20, - (u32)env_get_ulong("vx_memtop", 16, gd->fb_base-0x20), + (u32)gd->fb_base - 0x20, + (u32)env_get_ulong("vx_memtop", 16, gd->fb_base - 0x20), (u32)env_get_ulong("vx_romfsbase", 16, 0), (u32)env_get_ulong("vx_romfssize", 16, 0)); env_set("othbootargs", othbootargs); diff --git a/board/BuR/common/br_resetc.c b/board/BuR/common/br_resetc.c new file mode 100644 index 0000000000..190f141091 --- /dev/null +++ b/board/BuR/common/br_resetc.c @@ -0,0 +1,234 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * common reset-controller functions for B&R boards + * + * Copyright (C) 2019 Hannes Schmelzer <oe5hpm@oevsv.at> + * B&R Industrial Automation GmbH - http://www.br-automation.com/ * + */ +#include <common.h> +#include <errno.h> +#include <i2c.h> +#include <dm/uclass.h> +#include "br_resetc.h" + +/* I2C Address of controller */ +#define RSTCTRL_ADDR_PSOC 0x75 +#define RSTCTRL_ADDR_STM32 0x60 + +#define BMODE_DEFAULTAR 0 +#define BMODE_SERVICE 2 +#define BMODE_RUN 4 +#define BMODE_PME 12 +#define BMODE_DIAG 15 + +#ifdef CONFIG_LCD +#include <lcd.h> +#define LCD_SETCURSOR(x, y) lcd_position_cursor(x, y) +#define LCD_PUTS(x) lcd_puts(x) +#else +#define LCD_SETCURSOR(x, y) +#define LCD_PUTS(x) +#endif /* CONFIG_LCD */ + +static const char *bootmodeascii[16] = { + "BOOT", "reserved", "reserved", "reserved", + "RUN", "reserved", "reserved", "reserved", + "reserved", "reserved", "reserved", "reserved", + "PME", "reserved", "reserved", "DIAG", +}; + +struct br_reset_t { + struct udevice *i2cdev; + u8 is_psoc; +}; + +static struct br_reset_t resetc; + +__weak int board_boot_key(void) +{ + return 0; +} + +__weak void board_boot_led(unsigned int on) +{ +} + +static int resetc_init(void) +{ + struct udevice *i2cbus; + int rc; + + rc = uclass_get_device_by_seq(UCLASS_I2C, 0, &i2cbus); + if (rc) { + printf("Cannot find I2C bus #0!\n"); + return -1; + } + + rc = dm_i2c_probe(i2cbus, + RSTCTRL_ADDR_PSOC, 0, &resetc.i2cdev); + if (rc) { + resetc.is_psoc = 0; + rc = dm_i2c_probe(i2cbus, + RSTCTRL_ADDR_STM32, 0, &resetc.i2cdev); + } + + if (rc) + printf("Warning: cannot probe BuR resetcontroller!\n"); + + return rc; +} + +int br_resetc_regget(u8 reg, u8 *dst) +{ + int rc = 0; + + if (!resetc.i2cdev) + rc = resetc_init(); + + if (rc != 0) + return rc; + + return dm_i2c_read(resetc.i2cdev, reg, dst, 1); +} + +int br_resetc_regset(u8 reg, u8 val) +{ + int rc = 0; + u16 regw = (val << 8) | val; + + if (!resetc.i2cdev) + rc = resetc_init(); + + if (rc != 0) + return rc; + + if (resetc.is_psoc) + return dm_i2c_write(resetc.i2cdev, reg, (u8 *)®w, 2); + + return dm_i2c_write(resetc.i2cdev, reg, (u8 *)®w, 1); +} + +int br_resetc_bmode(void) +{ + int rc = 0; + u16 regw; + u8 regb, scr; + int cnt; + unsigned int bmode = 0; + + if (!resetc.i2cdev) + rc = resetc_init(); + + if (rc != 0) + return rc; + + rc = dm_i2c_read(resetc.i2cdev, RSTCTRL_ENHSTATUS, ®b, 1); + if (rc != 0) { + printf("WARN: cannot read ENHSTATUS from resetcontroller!\n"); + return -1; + } + + rc = dm_i2c_read(resetc.i2cdev, RSTCTRL_SCRATCHREG0, &scr, 1); + if (rc != 0) { + printf("WARN: cannot read SCRATCHREG from resetcontroller!\n"); + return -1; + } + + board_boot_led(1); + + /* special bootmode from resetcontroller */ + if (regb & 0x4) { + bmode = BMODE_DIAG; + } else if (regb & 0x8) { + bmode = BMODE_DEFAULTAR; + } else if (board_boot_key() != 0) { + cnt = 4; + do { + LCD_SETCURSOR(1, 8); + switch (cnt) { + case 4: + LCD_PUTS + ("release KEY to enter SERVICE-mode. "); + break; + case 3: + LCD_PUTS + ("release KEY to enter DIAGNOSE-mode. "); + break; + case 2: + LCD_PUTS + ("release KEY to enter BOOT-mode. "); + break; + } + mdelay(1000); + cnt--; + if (board_boot_key() == 0) + break; + } while (cnt); + + switch (cnt) { + case 0: + bmode = BMODE_PME; + break; + case 1: + bmode = BMODE_DEFAULTAR; + break; + case 2: + bmode = BMODE_DIAG; + break; + case 3: + bmode = BMODE_SERVICE; + break; + } + } else if ((regb & 0x1) || scr == 0xCC) { + bmode = BMODE_PME; + } else { + bmode = BMODE_RUN; + } + + LCD_SETCURSOR(1, 8); + + switch (bmode) { + case BMODE_PME: + LCD_PUTS("entering PME-Mode (netscript). "); + regw = 0x0C0C; + break; + case BMODE_DEFAULTAR: + LCD_PUTS("entering BOOT-mode. "); + regw = 0x0000; + break; + case BMODE_DIAG: + LCD_PUTS("entering DIAGNOSE-mode. "); + regw = 0x0F0F; + break; + case BMODE_SERVICE: + LCD_PUTS("entering SERVICE mode. "); + regw = 0xB4B4; + break; + case BMODE_RUN: + LCD_PUTS("loading OS... "); + regw = 0x0404; + break; + } + + board_boot_led(0); + + if (resetc.is_psoc) + rc = dm_i2c_write(resetc.i2cdev, RSTCTRL_SCRATCHREG0, + (u8 *)®w, 2); + else + rc = dm_i2c_write(resetc.i2cdev, RSTCTRL_SCRATCHREG0, + (u8 *)®w, 1); + + if (rc != 0) + printf("WARN: cannot write into resetcontroller!\n"); + + if (resetc.is_psoc) + printf("Reset: PSOC controller\n"); + else + printf("Reset: STM32 controller\n"); + + printf("Mode: %s\n", bootmodeascii[regw & 0x0F]); + env_set_ulong("b_mode", regw & 0x0F); + + return rc; +} diff --git a/board/BuR/common/br_resetc.h b/board/BuR/common/br_resetc.h new file mode 100644 index 0000000000..ba0689bf20 --- /dev/null +++ b/board/BuR/common/br_resetc.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * common reset-controller functions for B&R boards + * + * Copyright (C) 2019 Hannes Schmelzer <oe5hpm@oevsv.at> + * B&R Industrial Automation GmbH - http://www.br-automation.com/ * + */ +#ifndef __CONFIG_BRRESETC_H__ +#define __CONFIG_BRRESETC_H__ +#include <common.h> + +int br_resetc_regget(u8 reg, u8 *dst); +int br_resetc_regset(u8 reg, u8 val); +int br_resetc_bmode(void); + +/* reset controller register defines */ +#define RSTCTRL_CTRLREG 0x01 +#define RSTCTRL_SCRATCHREG0 0x04 +#define RSTCTRL_ENHSTATUS 0x07 +#define RSTCTRL_SCRATCHREG1 0x08 +#define RSTCTRL_RSTCAUSE 0x00 +#define RSTCTRL_ERSTCAUSE 0x09 +#define RSTCTRL_SPECGPIO_I 0x0A +#define RSTCTRL_SPECGPIO_O 0x0B + +#endif /* __CONFIG_BRRESETC_H__ */ diff --git a/board/BuR/common/bur_common.h b/board/BuR/common/bur_common.h index f743194c34..2591bf4bb3 100644 --- a/board/BuR/common/bur_common.h +++ b/board/BuR/common/bur_common.h @@ -21,4 +21,6 @@ void enable_i2c_pin_mux(void); void enable_board_pin_mux(void); int board_eth_init(bd_t *bis); +int brdefaultip_setup(int bus, int chip); + #endif diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c index 602c571f9c..89087d7dba 100644 --- a/board/BuR/common/common.c +++ b/board/BuR/common/common.c @@ -10,28 +10,22 @@ */ #include <version.h> #include <common.h> -#include <environment.h> -#include <errno.h> -#include <asm/arch/cpu.h> -#include <asm/arch/hardware.h> -#include <asm/arch/omap.h> -#include <asm/arch/clock.h> -#include <asm/arch/gpio.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/mmc_host_def.h> -#include <asm/io.h> -#include <asm/gpio.h> +#include <fdtdec.h> #include <i2c.h> -#include <power/tps65217.h> #include <lcd.h> #include "bur_common.h" -#include "../../../drivers/video/am335x-fb.h" DECLARE_GLOBAL_DATA_PTR; /* --------------------------------------------------------------------------*/ #if defined(CONFIG_LCD) && defined(CONFIG_AM335X_LCD) && \ !defined(CONFIG_SPL_BUILD) +#include <asm/arch/hardware.h> +#include <asm/arch/cpu.h> +#include <asm/gpio.h> +#include <power/tps65217.h> +#include "../../../drivers/video/am335x-fb.h" + void lcdbacklight(int on) { unsigned int driver = env_get_ulong("ds1_bright_drv", 16, 0UL); @@ -272,7 +266,51 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } -#ifdef CONFIG_SPL_BUILD +int brdefaultip_setup(int bus, int chip) +{ + int rc; + struct udevice *i2cdev; + u8 u8buf = 0; + char defip[256] = { 0 }; + + rc = i2c_get_chip_for_busnum(bus, chip, 2, &i2cdev); + if (rc != 0) { + printf("WARN: cannot probe baseboard EEPROM!\n"); + return -1; + } + + rc = dm_i2c_read(i2cdev, 0, &u8buf, 1); + if (rc != 0) { + printf("WARN: cannot read baseboard EEPROM!\n"); + return -1; + } + + if (u8buf != 0xFF) + snprintf(defip, sizeof(defip), + "if test -r ${ipaddr}; then; else setenv ipaddr 192.168.60.%d; setenv serverip 192.168.60.254; setenv gatewayip 192.168.60.254; setenv netmask 255.255.255.0; fi;", + u8buf); + else + strncpy(defip, + "if test -r ${ipaddr}; then; else setenv ipaddr 192.168.60.1; setenv serverip 192.168.60.254; setenv gatewayip 192.168.60.254; setenv netmask 255.255.255.0; fi;", + sizeof(defip)); + + env_set("brdefaultip", defip); + env_set_hex("board_id", u8buf); + + return 0; +} + +int overwrite_console(void) +{ + return 1; +} + +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_AM33XX) +#include <asm/arch/hardware.h> +#include <asm/arch/omap.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <power/tps65217.h> static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; @@ -359,9 +397,4 @@ void set_mux_conf_regs(void) enable_board_pin_mux(); } -#endif /* CONFIG_SPL_BUILD */ - -int overwrite_console(void) -{ - return 1; -} +#endif /* CONFIG_SPL_BUILD && CONFIG_AM33XX */ diff --git a/board/CZ.NIC/turris_mox/turris_mox.c b/board/CZ.NIC/turris_mox/turris_mox.c index 96cb9c7e5c..8a4872343b 100644 --- a/board/CZ.NIC/turris_mox/turris_mox.c +++ b/board/CZ.NIC/turris_mox/turris_mox.c @@ -119,41 +119,11 @@ int board_fix_fdt(void *blob) } #endif -#ifdef CONFIG_WDT_ARMADA_37XX -static struct udevice *watchdog_dev __attribute__((section(".data"))) = NULL; - -void watchdog_reset(void) -{ - static ulong next_reset; - ulong now; - - if (!watchdog_dev) - return; - - now = timer_get_us(); - - /* Do not reset the watchdog too often */ - if (now > next_reset) { - wdt_reset(watchdog_dev); - next_reset = now + 100000; - } -} -#endif - int board_init(void) { /* address of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; -#ifdef CONFIG_WDT_ARMADA_37XX - if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) { - printf("Cannot find Armada 3720 watchdog!\n"); - } else { - printf("Enabling Armada 3720 watchdog (3 minutes timeout).\n"); - wdt_start(watchdog_dev, 180000, 0); - } -#endif - return 0; } diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c index c21d2f3ffa..4c08f810a2 100644 --- a/board/CZ.NIC/turris_omnia/turris_omnia.c +++ b/board/CZ.NIC/turris_omnia/turris_omnia.c @@ -32,13 +32,13 @@ DECLARE_GLOBAL_DATA_PTR; -#define OMNIA_I2C_EEPROM_DM_NAME "i2c@0" +#define OMNIA_I2C_EEPROM_DM_NAME "i2c@11000->i2cmux@70->i2c@0" #define OMNIA_I2C_EEPROM 0x54 #define OMNIA_I2C_EEPROM_CONFIG_ADDR 0x0 #define OMNIA_I2C_EEPROM_ADDRLEN 2 #define OMNIA_I2C_EEPROM_MAGIC 0x0341a034 -#define OMNIA_I2C_MCU_DM_NAME "i2c@0" +#define OMNIA_I2C_MCU_DM_NAME "i2c@11000->i2cmux@70->i2c@0" #define OMNIA_I2C_MCU_ADDR_STATUS 0x1 #define OMNIA_I2C_MCU_SATA 0x20 #define OMNIA_I2C_MCU_CARDDET 0x10 @@ -364,25 +364,12 @@ static bool disable_mcu_watchdog(void) } #endif -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT_ORION) -static struct udevice *watchdog_dev __attribute__((section(".data"))) = NULL; -#endif - int board_init(void) { /* adress of boot parameters */ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; #ifndef CONFIG_SPL_BUILD -# ifdef CONFIG_WDT_ORION - if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) { - puts("Cannot find Armada 385 watchdog!\n"); - } else { - puts("Enabling Armada 385 watchdog.\n"); - wdt_start(watchdog_dev, 120000, 0); - } -# endif - if (disable_mcu_watchdog()) puts("Disabled MCU startup watchdog.\n"); @@ -392,28 +379,6 @@ int board_init(void) return 0; } -#ifdef CONFIG_WATCHDOG -/* Called by macro WATCHDOG_RESET */ -void watchdog_reset(void) -{ -# if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT_ORION) - static ulong next_reset = 0; - ulong now; - - if (!watchdog_dev) - return; - - now = timer_get_us(); - - /* Do not reset the watchdog too often */ - if (now > next_reset) { - wdt_reset(watchdog_dev); - next_reset = now + 1000; - } -# endif -} -#endif - int board_late_init(void) { #ifndef CONFIG_SPL_BUILD diff --git a/board/Marvell/db-88f6281-bp/.gitignore b/board/Marvell/db-88f6281-bp/.gitignore new file mode 100644 index 0000000000..775b9346b8 --- /dev/null +++ b/board/Marvell/db-88f6281-bp/.gitignore @@ -0,0 +1 @@ +kwbimage.cfg diff --git a/board/Marvell/db-88f6281-bp/Kconfig b/board/Marvell/db-88f6281-bp/Kconfig new file mode 100644 index 0000000000..38467399e6 --- /dev/null +++ b/board/Marvell/db-88f6281-bp/Kconfig @@ -0,0 +1,12 @@ +if TARGET_DB_88F6281_BP + +config SYS_BOARD + default "db-88f6281-bp" + +config SYS_VENDOR + default "Marvell" + +config SYS_CONFIG_NAME + default "db-88f6281-bp" + +endif diff --git a/board/Marvell/db-88f6281-bp/MAINTAINERS b/board/Marvell/db-88f6281-bp/MAINTAINERS new file mode 100644 index 0000000000..acf0b051ff --- /dev/null +++ b/board/Marvell/db-88f6281-bp/MAINTAINERS @@ -0,0 +1,10 @@ +DB_88F6820_AMC BOARD +M: Chris Packham <judge.packham@gmail.com> +S: Maintained +F: arch/arm/dts/kirkwood-db-88f6281.dts +F: arch/arm/dts/kirkwood-db-88f6281-spi.dts +F: arch/arm/dts/kirkwood-db.dtsi +F: board/Marvell/db-88f6281-bp/ +F: include/configs/db-88f6281-bp.h +F: configs/db-88f6281-bp-nand_defconfig +F: configs/db-88f6281-bp-spi_defconfig diff --git a/board/Marvell/db-88f6281-bp/Makefile b/board/Marvell/db-88f6281-bp/Makefile new file mode 100644 index 0000000000..e6aa7e39a0 --- /dev/null +++ b/board/Marvell/db-88f6281-bp/Makefile @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y := db-88f6281-bp.o +extra-y := kwbimage.cfg + +quiet_cmd_sed = SED $@ + cmd_sed = sed $(SEDFLAGS_$(@F)) $< >$(dir $<)$(@F) + +SEDFLAGS_kwbimage.cfg = -e "s/^\#@BOOT_FROM.*/BOOT_FROM $(if $(CONFIG_CMD_NAND),nand,spi)/" +$(src)/kwbimage.cfg: $(src)/kwbimage.cfg.in include/autoconf.mk \ + include/config/auto.conf + $(call if_changed,sed) diff --git a/board/Marvell/db-88f6281-bp/db-88f6281-bp.c b/board/Marvell/db-88f6281-bp/db-88f6281-bp.c new file mode 100644 index 0000000000..b68f2f3c89 --- /dev/null +++ b/board/Marvell/db-88f6281-bp/db-88f6281-bp.c @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#include <common.h> +#include <linux/io.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/arch/cpu.h> +#include <asm/arch/soc.h> +#include <asm/arch/mpp.h> +#include <asm/arch/gpio.h> + +#define DB_88F6281_OE_LOW ~(BIT(7)) +#define DB_88F6281_OE_HIGH ~(BIT(15) | BIT(14) | BIT(13) | BIT(4)) +#define DB_88F6281_OE_VAL_LOW BIT(7) +#define DB_88F6281_OE_VAL_HIGH 0 + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + mvebu_config_gpio(DB_88F6281_OE_VAL_LOW, + DB_88F6281_OE_VAL_HIGH, + DB_88F6281_OE_LOW, DB_88F6281_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + static const u32 kwmpp_config[] = { +#ifdef CONFIG_CMD_NAND + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, +#else + MPP0_SPI_SCn, + MPP1_SPI_MOSI, + MPP2_SPI_SCK, + MPP3_SPI_MISO, +#endif + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP7_GPO, + MPP8_TW_SDA, + MPP9_TW_SCK, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_SD_CLK, + MPP13_SD_CMD, + MPP14_SD_D0, + MPP15_SD_D1, + MPP16_SD_D2, + MPP17_SD_D3, + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_SATA1_ACTn, + MPP21_SATA0_ACTn, + MPP22_GPIO, + MPP23_GPIO, + MPP24_GPIO, + MPP25_GPIO, + MPP26_GPIO, + MPP27_GPIO, + MPP28_GPIO, + MPP29_GPIO, + MPP30_GPIO, + MPP31_GPIO, + MPP32_GPIO, + MPP33_GPIO, + MPP34_GPIO, + MPP35_GPIO, + MPP36_GPIO, + MPP37_GPIO, + MPP38_GPIO, + MPP39_GPIO, + MPP40_GPIO, + MPP41_GPIO, + MPP42_GPIO, + MPP43_GPIO, + MPP44_GPIO, + MPP45_GPIO, + MPP46_GPIO, + MPP47_GPIO, + MPP48_GPIO, + MPP49_GPIO, + 0 + }; + kirkwood_mpp_conf(kwmpp_config, NULL); + + return 0; +} + +int board_init(void) +{ + gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; + + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +/* automatically defined by kirkwood config.h */ +void reset_phy(void) +{ +} +#endif diff --git a/board/Marvell/db-88f6281-bp/kwbimage.cfg.in b/board/Marvell/db-88f6281-bp/kwbimage.cfg.in new file mode 100644 index 0000000000..05f8b275f6 --- /dev/null +++ b/board/Marvell/db-88f6281-bp/kwbimage.cfg.in @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0+ + +# Boot Media configurations +#@BOOT_FROM + +DATA 0xd00100e0 0x1b1b1b9b +DATA 0xd0020134 0xbbbbbbbb +DATA 0xd0020138 0x00bbbbbb +DATA 0xd0020154 0x00000200 +DATA 0xd002014c 0x00001c00 +DATA 0xd0020148 0x00000001 + +DATA 0xd0001400 0x43000c30 +DATA 0xd0001404 0x39543000 +DATA 0xd0001408 0x22125451 +DATA 0xd000140c 0x00000833 +DATA 0xd0001410 0x000000cc +DATA 0xd0001414 0x00000000 +DATA 0xd0001418 0x00000000 +DATA 0xd000141c 0x00000c52 +DATA 0xd0001420 0x00000044 +DATA 0xd0001424 0x0000f1ff +DATA 0xd0001428 0x00085520 +DATA 0xd000147c 0x00008552 +DATA 0xd0001504 0x0ffffff1 +DATA 0xd0001508 0x10000000 +DATA 0xd000150c 0x0ffffff5 +DATA 0xd0001514 0x00000000 +DATA 0xd000151c 0x00000000 +DATA 0xd0001494 0x84210000 +DATA 0xd0001498 0x00000000 +DATA 0xd000149c 0x0000f40f +DATA 0xd0001480 0x00000001 + +# End of Header extension +DATA 0x0 0x0 diff --git a/board/Marvell/openrd/MAINTAINERS b/board/Marvell/openrd/MAINTAINERS index b24fff0a78..8170452b44 100644 --- a/board/Marvell/openrd/MAINTAINERS +++ b/board/Marvell/openrd/MAINTAINERS @@ -1,6 +1,6 @@ OPENRD / OPENRD_CLIENT BOARD -#M: Albert ARIBAUD <albert-u-boot@aribaud.net> -S: Orphaned (Since 2018-09) +M: Stefan Roese <sr@denx.de> +S: Maintained F: board/Marvell/openrd/ F: include/configs/openrd.h F: configs/openrd_base_defconfig diff --git a/board/alliedtelesis/x530/x530.c b/board/alliedtelesis/x530/x530.c index 6934fd8017..97dbed79dd 100644 --- a/board/alliedtelesis/x530/x530.c +++ b/board/alliedtelesis/x530/x530.c @@ -25,10 +25,6 @@ DECLARE_GLOBAL_DATA_PTR; #define CONFIG_NVS_LOCATION 0xf4800000 #define CONFIG_NVS_SIZE (512 << 10) -#ifdef CONFIG_WATCHDOG -static struct udevice *watchdog_dev; -#endif - static struct serdes_map board_serdes_map[] = { {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, @@ -80,10 +76,6 @@ struct mv_ddr_topology_map *mv_ddr_topology_map_get(void) int board_early_init_f(void) { -#ifdef CONFIG_WATCHDOG - watchdog_dev = NULL; -#endif - /* Configure MPP */ writel(0x00001111, MVEBU_MPP_BASE + 0x00); writel(0x00000000, MVEBU_MPP_BASE + 0x04); @@ -99,13 +91,6 @@ int board_early_init_f(void) void spl_board_init(void) { -#ifdef CONFIG_WATCHDOG - int ret; - - ret = uclass_get_device(UCLASS_WDT, 0, &watchdog_dev); - if (!ret) - wdt_start(watchdog_dev, 120000, 0); -#endif } int board_init(void) @@ -128,29 +113,10 @@ int board_init(void) void arch_preboot_os(void) { #ifdef CONFIG_WATCHDOG - wdt_stop(watchdog_dev); + wdt_stop(gd->watchdog_dev); #endif } -#ifdef CONFIG_WATCHDOG -void watchdog_reset(void) -{ - static ulong next_reset = 0; - ulong now; - - if (!watchdog_dev) - return; - - now = timer_get_us(); - - /* Do not reset the watchdog too often */ - if (now > next_reset) { - wdt_reset(watchdog_dev); - next_reset = now + 1000; - } -} -#endif - static int led_7seg_init(unsigned int segments) { int node; diff --git a/board/amlogic/odroid-c2/MAINTAINERS b/board/amlogic/p200/MAINTAINERS index 6a853066d7..96fe92dd08 100644 --- a/board/amlogic/odroid-c2/MAINTAINERS +++ b/board/amlogic/p200/MAINTAINERS @@ -1,8 +1,8 @@ -ODROID-C2 +P200 M: Beniamino Galvani <b.galvani@gmail.com> M: Neil Armstrong <narmstrong@baylibre.com> S: Maintained -F: board/amlogic/odroid-c2/ -F: include/configs/odroid-c2.h +F: board/amlogic/p200/ F: configs/nanopi-k2_defconfig F: configs/odroid-c2_defconfig +F: configs/p200_defconfig diff --git a/board/amlogic/odroid-c2/Makefile b/board/amlogic/p200/Makefile index a6a3db755f..f82a7ea9ca 100644 --- a/board/amlogic/odroid-c2/Makefile +++ b/board/amlogic/p200/Makefile @@ -2,4 +2,4 @@ # # (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com> -obj-y := odroid-c2.o +obj-y := p200.o diff --git a/board/amlogic/odroid-c2/README.nanopi-k2 b/board/amlogic/p200/README.nanopi-k2 index d450d3c2b2..d450d3c2b2 100644 --- a/board/amlogic/odroid-c2/README.nanopi-k2 +++ b/board/amlogic/p200/README.nanopi-k2 diff --git a/board/amlogic/odroid-c2/README.odroid-c2 b/board/amlogic/p200/README.odroid-c2 index bed48c5728..bed48c5728 100644 --- a/board/amlogic/odroid-c2/README.odroid-c2 +++ b/board/amlogic/p200/README.odroid-c2 diff --git a/board/amlogic/p200/README.p200 b/board/amlogic/p200/README.p200 new file mode 100644 index 0000000000..01d82d1e79 --- /dev/null +++ b/board/amlogic/p200/README.p200 @@ -0,0 +1,103 @@ +U-Boot for Amlogic P200 +======================= + +P200 is a reference board manufactured by Amlogic with the following +specifications: + + - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 1.5GHz + - ARM Mali 450 GPU + - 2GB DDR3 SDRAM + - Gigabit Ethernet + - HDMI 2.0 4K/60Hz display + - 2 x USB 2.0 Host + - eMMC, microSD + - Infrared receiver + - SDIO WiFi Module + - CVBS+Stereo Audio Jack + +Schematics are available from Amlogic on demand. + +Currently the u-boot port supports the following devices: + - serial + - eMMC, microSD + - Ethernet + - I2C + - Regulators + - Reset controller + - Clock controller + - USB Host + - ADC + +u-boot compilation +================== + + > export ARCH=arm + > export CROSS_COMPILE=aarch64-none-elf- + > make p200_defconfig + > make + +Image creation +============== + +Amlogic doesn't provide sources for the firmware and for tools needed +to create the bootloader image, so it is necessary to obtain them from +the git tree published by the board vendor: + + > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH + > git clone https://github.com/BayLibre/u-boot.git -b n-amlogic-openlinux-20170606 amlogic-u-boot + > cd amlogic-u-boot + > make gxb_p200_v1_defconfig + > make + > export FIPDIR=$PWD/fip + +Go back to mainline U-boot source tree then : + > mkdir fip + + > cp $FIPDIR/gxl/bl2.bin fip/ + > cp $FIPDIR/gxl/acs.bin fip/ + > cp $FIPDIR/gxl/bl21.bin fip/ + > cp $FIPDIR/gxl/bl30.bin fip/ + > cp $FIPDIR/gxl/bl301.bin fip/ + > cp $FIPDIR/gxl/bl31.img fip/ + > cp u-boot.bin fip/bl33.bin + + > $FIPDIR/blx_fix.sh \ + fip/bl30.bin \ + fip/zero_tmp \ + fip/bl30_zero.bin \ + fip/bl301.bin \ + fip/bl301_zero.bin \ + fip/bl30_new.bin \ + bl30 + + > $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 + + > $FIPDIR/blx_fix.sh \ + fip/bl2_acs.bin \ + fip/zero_tmp \ + fip/bl2_zero.bin \ + fip/bl21.bin \ + fip/bl21_zero.bin \ + fip/bl2_new.bin \ + bl2 + + > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin + > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img + > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin + > $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig + > $FIPDIR/gxl/aml_encrypt_gxl --bootmk \ + --output fip/u-boot.bin \ + --bl2 fip/bl2.n.bin.sig \ + --bl30 fip/bl30_new.bin.enc \ + --bl31 fip/bl31.img.enc \ + --bl33 fip/bl33.bin.enc + +and then write the image to SD with: + + > DEV=/dev/your_sd_device + > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 + > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/odroid-c2/odroid-c2.c b/board/amlogic/p200/p200.c index 62f0f4c871..62f0f4c871 100644 --- a/board/amlogic/odroid-c2/odroid-c2.c +++ b/board/amlogic/p200/p200.c diff --git a/board/amlogic/p201/MAINTAINERS b/board/amlogic/p201/MAINTAINERS new file mode 100644 index 0000000000..3e84a8e2a2 --- /dev/null +++ b/board/amlogic/p201/MAINTAINERS @@ -0,0 +1,5 @@ +P201 +M: Neil Armstrong <narmstrong@baylibre.com> +S: Maintained +F: board/amlogic/p201/ +F: configs/p201_defconfig diff --git a/board/amlogic/p201/Makefile b/board/amlogic/p201/Makefile new file mode 100644 index 0000000000..11de5396ab --- /dev/null +++ b/board/amlogic/p201/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com> + +obj-y := p201.o diff --git a/board/amlogic/p201/README.p201 b/board/amlogic/p201/README.p201 new file mode 100644 index 0000000000..c251096ce1 --- /dev/null +++ b/board/amlogic/p201/README.p201 @@ -0,0 +1,103 @@ +U-Boot for Amlogic P201 +======================= + +P201 is a reference board manufactured by Amlogic with the following +specifications: + + - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 1.5GHz + - ARM Mali 450 GPU + - 2GB DDR3 SDRAM + - 10/100 Ethernet + - HDMI 2.0 4K/60Hz display + - 2 x USB 2.0 Host + - eMMC, microSD + - Infrared receiver + - SDIO WiFi Module + - CVBS+Stereo Audio Jack + +Schematics are available from Amlogic on demand. + +Currently the u-boot port supports the following devices: + - serial + - eMMC, microSD + - Ethernet + - I2C + - Regulators + - Reset controller + - Clock controller + - USB Host + - ADC + +u-boot compilation +================== + + > export ARCH=arm + > export CROSS_COMPILE=aarch64-none-elf- + > make p201_defconfig + > make + +Image creation +============== + +Amlogic doesn't provide sources for the firmware and for tools needed +to create the bootloader image, so it is necessary to obtain them from +the git tree published by the board vendor: + + > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH + > git clone https://github.com/BayLibre/u-boot.git -b n-amlogic-openlinux-20170606 amlogic-u-boot + > cd amlogic-u-boot + > make gxb_p201_v1_defconfig + > make + > export FIPDIR=$PWD/fip + +Go back to mainline U-boot source tree then : + > mkdir fip + + > cp $FIPDIR/gxl/bl2.bin fip/ + > cp $FIPDIR/gxl/acs.bin fip/ + > cp $FIPDIR/gxl/bl21.bin fip/ + > cp $FIPDIR/gxl/bl30.bin fip/ + > cp $FIPDIR/gxl/bl301.bin fip/ + > cp $FIPDIR/gxl/bl31.img fip/ + > cp u-boot.bin fip/bl33.bin + + > $FIPDIR/blx_fix.sh \ + fip/bl30.bin \ + fip/zero_tmp \ + fip/bl30_zero.bin \ + fip/bl301.bin \ + fip/bl301_zero.bin \ + fip/bl30_new.bin \ + bl30 + + > $FIPDIR/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 + + > $FIPDIR/blx_fix.sh \ + fip/bl2_acs.bin \ + fip/zero_tmp \ + fip/bl2_zero.bin \ + fip/bl21.bin \ + fip/bl21_zero.bin \ + fip/bl2_new.bin \ + bl2 + + > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin + > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img + > $FIPDIR/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin + > $FIPDIR/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig + > $FIPDIR/gxl/aml_encrypt_gxl --bootmk \ + --output fip/u-boot.bin \ + --bl2 fip/bl2.n.bin.sig \ + --bl30 fip/bl30_new.bin.enc \ + --bl31 fip/bl31.img.enc \ + --bl33 fip/bl33.bin.enc + +and then write the image to SD with: + + > DEV=/dev/your_sd_device + > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 + > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/p201/p201.c b/board/amlogic/p201/p201.c new file mode 100644 index 0000000000..ef0c65cd9f --- /dev/null +++ b/board/amlogic/p201/p201.c @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016 Beniamino Galvani <b.galvani@gmail.com> + */ + +#include <common.h> +#include <dm.h> +#include <environment.h> +#include <asm/io.h> +#include <asm/arch/gx.h> +#include <asm/arch/sm.h> +#include <asm/arch/eth.h> +#include <asm/arch/mem.h> + +#define EFUSE_SN_OFFSET 20 +#define EFUSE_SN_SIZE 16 +#define EFUSE_MAC_OFFSET 52 +#define EFUSE_MAC_SIZE 6 + +int misc_init_r(void) +{ + u8 mac_addr[EFUSE_MAC_SIZE]; + char serial[EFUSE_SN_SIZE]; + ssize_t len; + + meson_eth_init(PHY_INTERFACE_MODE_RMII, 0); + + if (!eth_env_get_enetaddr("ethaddr", mac_addr)) { + len = meson_sm_read_efuse(EFUSE_MAC_OFFSET, + mac_addr, EFUSE_MAC_SIZE); + if (len == EFUSE_MAC_SIZE && is_valid_ethaddr(mac_addr)) + eth_env_set_enetaddr("ethaddr", mac_addr); + } + + if (!env_get("serial#")) { + len = meson_sm_read_efuse(EFUSE_SN_OFFSET, serial, + EFUSE_SN_SIZE); + if (len == EFUSE_SN_SIZE) + env_set("serial#", serial); + } + + return 0; +} diff --git a/board/amlogic/p212/MAINTAINERS b/board/amlogic/p212/MAINTAINERS index 07ca6f204d..74ad3716ec 100644 --- a/board/amlogic/p212/MAINTAINERS +++ b/board/amlogic/p212/MAINTAINERS @@ -4,5 +4,6 @@ S: Maintained F: board/amlogic/p212/ F: include/configs/p212.h F: configs/khadas-vim_defconfig +F: configs/libretech-ac_defconfig F: configs/libretech-cc_defconfig F: configs/p212_defconfig diff --git a/board/amlogic/p212/README.libretech-ac b/board/amlogic/p212/README.libretech-ac new file mode 100644 index 0000000000..538604261b --- /dev/null +++ b/board/amlogic/p212/README.libretech-ac @@ -0,0 +1,103 @@ +U-Boot for LibreTech AC +======================= + +LibreTech AC is a single board computer manufactured by Libre Technology +with the following specifications: + + - Amlogic S805X ARM Cortex-A53 quad-core SoC @ 1.2GHz + - ARM Mali 450 GPU + - 512MiB DDR4 SDRAM + - 10/100 Ethernet + - HDMI 2.0 4K/60Hz display + - 40-pin GPIO header + - 4 x USB 2.0 Host + - eMMC, SPI NOR Flash + - Infrared receiver + +Schematics are available on the manufacturer website. + +Currently the U-Boot port supports the following devices: + - serial + - eMMC + - Ethernet + - USB + +U-Boot compilation +================== + + > export ARCH=arm + > export CROSS_COMPILE=aarch64-none-elf- + > make libretech-ac_defconfig + > make + +Image creation +============== + +Amlogic doesn't provide sources for the firmware and for tools needed +to create the bootloader image, so it is necessary to obtain them from +the git tree published by the board vendor: + + > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH + > git clone https://github.com/BayLibre/u-boot.git -b libretech-ac amlogic-u-boot + > cd amlogic-u-boot + > wget https://raw.githubusercontent.com/BayLibre/u-boot/libretech-cc/fip/blx_fix.sh + > make libretech_ac_defconfig + > make + > export UBOOTDIR=$PWD + +Download the latest Amlogic Buildroot package, and extract it : + > wget http://openlinux2.amlogic.com:8000/ARM/filesystem/Linux_BSP/buildroot_openlinux_kernel_4.9_fbdev_20180418.tar.gz + > tar xfz buildroot_openlinux_kernel_4.9_fbdev_20180418.tar.gz buildroot_openlinux_kernel_4.9_fbdev_20180418/bootloader + > export BRDIR=$PWD/buildroot_openlinux_kernel_4.9_fbdev_20180418 + +Go back to mainline U-Boot source tree then : + > mkdir fip + + > cp $UBOOTDIR/build/scp_task/bl301.bin fip/ + > cp $UBOOTDIR/build/board/amlogic/libretech_ac/firmware/bl21.bin fip/ + > cp $UBOOTDIR/build/board/amlogic/libretech_ac/firmware/acs.bin fip/ + > cp $BRDIR/bootloader/uboot-repo/bl2/bin/gxl/bl2.bin fip/ + > cp $BRDIR/bootloader/uboot-repo/bl30/bin/gxl/bl30.bin fip/ + > cp $BRDIR/bootloader/uboot-repo/bl31/bin/gxl/bl31.img fip/ + > cp u-boot.bin fip/bl33.bin + + > sh $UBOOTDIR/blx_fix.sh \ + fip/bl30.bin \ + fip/zero_tmp \ + fip/bl30_zero.bin \ + fip/bl301.bin \ + fip/bl301_zero.bin \ + fip/bl30_new.bin \ + bl30 + + > $BRDIR/bootloader/uboot-repo/fip/acs_tool.pyc fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 + + > sh $UBOOTDIR/blx_fix.sh \ + fip/bl2_acs.bin \ + fip/zero_tmp \ + fip/bl2_zero.bin \ + fip/bl21.bin \ + fip/bl21_zero.bin \ + fip/bl2_new.bin \ + bl2 + + > $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bl3enc --input fip/bl30_new.bin + > $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bl3enc --input fip/bl31.img + > $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bl3enc --input fip/bl33.bin + > $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bl2sig --input fip/bl2_new.bin --output fip/bl2.n.bin.sig + > $BRDIR/bootloader/uboot-repo/fip/gxl/aml_encrypt_gxl --bootmk \ + --output fip/u-boot.bin \ + --bl2 fip/bl2.n.bin.sig \ + --bl30 fip/bl30_new.bin.enc \ + --bl31 fip/bl31.img.enc \ + --bl33 fip/bl33.bin.enc + +and then write the image to SD with: + + > DEV=/dev/your_sd_device + > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 + > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/q200/README.khadas-vim2 b/board/amlogic/q200/README.khadas-vim2 index 578693fd2d..8bcfc296f3 100644 --- a/board/amlogic/q200/README.khadas-vim2 +++ b/board/amlogic/q200/README.khadas-vim2 @@ -48,9 +48,9 @@ the git tree published by the board vendor: > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH - > git clone https://github.com/khadas/u-boot -b Vim vim-u-boot + > git clone https://github.com/khadas/u-boot -b khadas-vim-v2015.01 vim-u-boot > cd vim-u-boot - > make kvim_defconfig + > make kvim2_defconfig > make > export FIPDIR=$PWD/fip diff --git a/board/amlogic/u200/MAINTAINERS b/board/amlogic/u200/MAINTAINERS new file mode 100644 index 0000000000..baf3813fd0 --- /dev/null +++ b/board/amlogic/u200/MAINTAINERS @@ -0,0 +1,5 @@ +U200 +M: Neil Armstrong <narmstrong@baylibre.com> +S: Maintained +F: board/amlogic/u200/ +F: configs/u200_defconfig diff --git a/board/amlogic/u200/Makefile b/board/amlogic/u200/Makefile new file mode 100644 index 0000000000..485791bbb2 --- /dev/null +++ b/board/amlogic/u200/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2016 BayLibre, SAS +# Author: Neil Armstrong <narmstrong@baylibre.com> + +obj-y := u200.o diff --git a/board/amlogic/u200/README b/board/amlogic/u200/README new file mode 100644 index 0000000000..bffac5e7ae --- /dev/null +++ b/board/amlogic/u200/README @@ -0,0 +1,128 @@ +U-Boot for Amlogic U200 +======================= + +U200 is a reference board manufactured by Amlogic with the following +specifications: + + - Amlogic S905D2 ARM Cortex-A53 quad-core SoC + - 2GB DDR4 SDRAM + - 10/100 Ethernet (Internal PHY) + - 1 x USB 3.0 Host + - eMMC + - SDcard + - Infrared receiver + - SDIO WiFi Module + - MIPI DSI Connector + - Audio HAT Connector + - PCI-E M.2 Connector + +Schematics are available from Amlogic on demand. + +Currently the u-boot port supports the following devices: + - serial + - Ethernet + - Regulators + - Clock controller + +u-boot compilation +================== + + > export ARCH=arm + > export CROSS_COMPILE=aarch64-none-elf- + > make u200_defconfig + > make + +Image creation +============== + +Amlogic doesn't provide sources for the firmware and for tools needed +to create the bootloader image, so it is necessary to obtain them from +the git tree published by the board vendor: + + > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + > wget https://releases.linaro.org/archive/13.11/components/toolchain/binaries/gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + > tar xvfJ gcc-linaro-aarch64-none-elf-4.8-2013.11_linux.tar.xz + > tar xvfJ gcc-linaro-arm-none-eabi-4.8-2013.11_linux.tar.xz + > export PATH=$PWD/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin:$PWD/gcc-linaro-arm-none-eabi-4.8-2013.11_linux/bin:$PATH + > git clone https://github.com/BayLibre/u-boot.git -b buildroot-openlinux-20180418 amlogic-u-boot + > cd amlogic-u-boot + > make g12a_u200_v1_defconfig + > make + > export UBOOTDIR=$PWD + +Download the latest Amlogic Buildroot package, and extract it : + > wget http://openlinux2.amlogic.com:8000/ARM/filesystem/Linux_BSP/buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz + > tar xfz buildroot_openlinux_kernel_4.9_fbdev_20180706.tar.gz buildroot_openlinux_kernel_4.9_fbdev_20180706/bootloader + > export BRDIR=$PWD/buildroot_openlinux_kernel_4.9_fbdev_20180706 + > export FIPDIR=$BRDIR/bootloader/uboot-repo/fip + +Go back to mainline U-Boot source tree then : + > mkdir fip + + > wget https://github.com/BayLibre/u-boot/releases/download/v2017.11-libretech-cc/blx_fix_g12a.sh -O fip/blx_fix.sh + > cp $UBOOTDIR/build/scp_task/bl301.bin fip/ + > cp $UBOOTDIR/build/board/amlogic/g12a_u200_v1/firmware/acs.bin fip/ + > cp $BRDIR/bootloader/uboot-repo/bl2/bin/g12a/bl2.bin fip/ + > cp $BRDIR/bootloader/uboot-repo/bl30/bin/g12a/bl30.bin fip/ + > cp $BRDIR/bootloader/uboot-repo/bl31_1.3/bin/g12a/bl31.img fip/ + > cp $FIPDIR/g12a/ddr3_1d.fw fip/ + > cp $FIPDIR/g12a/ddr4_1d.fw fip/ + > cp $FIPDIR/g12a/ddr4_2d.fw fip/ + > cp $FIPDIR/g12a/diag_lpddr4.fw fip/ + > cp $FIPDIR/g12a/lpddr4_1d.fw fip/ + > cp $FIPDIR/g12a/lpddr4_2d.fw fip/ + > cp $FIPDIR/g12a/piei.fw fip/ + > cp u-boot.bin fip/bl33.bin + + > sh fip/blx_fix.sh \ + fip/bl30.bin \ + fip/zero_tmp \ + fip/bl30_zero.bin \ + fip/bl301.bin \ + fip/bl301_zero.bin \ + fip/bl30_new.bin \ + bl30 + + > sh fip/blx_fix.sh \ + fip/bl2.bin \ + fip/zero_tmp \ + fip/bl2_zero.bin \ + fip/acs.bin \ + fip/bl21_zero.bin \ + fip/bl2_new.bin \ + bl2 + + > $FIPDIR/g12a/aml_encrypt_g12a --bl30sig --input fip/bl30_new.bin \ + --output fip/bl30_new.bin.g12a.enc \ + --level v3 + > $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl30_new.bin.g12a.enc \ + --output fip/bl30_new.bin.enc \ + --level v3 --type bl30 + > $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl31.img \ + --output fip/bl31.img.enc \ + --level v3 --type bl31 + > $FIPDIR/g12a/aml_encrypt_g12a --bl3sig --input fip/bl33.bin --compress lz4 \ + --output fip/bl33.bin.enc \ + --level v3 --type bl33 + > $FIPDIR/g12a/aml_encrypt_g12a --bl2sig --input fip/bl2_new.bin \ + --output fip/bl2.n.bin.sig + > $FIPDIR/g12a/aml_encrypt_g12a --bootmk \ + --output fip/u-boot.bin \ + --bl2 fip/bl2.n.bin.sig \ + --bl30 fip/bl30_new.bin.enc \ + --bl31 fip/bl31.img.enc \ + --bl33 fip/bl33.bin.enc \ + --ddrfw1 fip/ddr4_1d.fw \ + --ddrfw2 fip/ddr4_2d.fw \ + --ddrfw3 fip/ddr3_1d.fw \ + --ddrfw4 fip/piei.fw \ + --ddrfw5 fip/lpddr4_1d.fw \ + --ddrfw6 fip/lpddr4_2d.fw \ + --ddrfw7 fip/diag_lpddr4.fw \ + --level v3 + +and then write the image to SD with: + + > DEV=/dev/your_sd_device + > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 + > dd if=fip/u-boot.bin.sd.bin of=$DEV conv=fsync,notrunc bs=1 count=444 diff --git a/board/amlogic/u200/u200.c b/board/amlogic/u200/u200.c new file mode 100644 index 0000000000..94ee3ce6e4 --- /dev/null +++ b/board/amlogic/u200/u200.c @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +#include <common.h> +#include <dm.h> +#include <environment.h> +#include <asm/io.h> +#include <asm/arch/axg.h> +#include <asm/arch/sm.h> +#include <asm/arch/eth.h> +#include <asm/arch/mem.h> + +int misc_init_r(void) +{ + meson_eth_init(PHY_INTERFACE_MODE_RMII, + MESON_USE_INTERNAL_RMII_PHY); + + return 0; +} diff --git a/board/buffalo/lsxl/README b/board/buffalo/lsxl/README index ef5ed42880..fffb1ce8ec 100644 --- a/board/buffalo/lsxl/README +++ b/board/buffalo/lsxl/README @@ -8,6 +8,16 @@ the LS-XHL PCB has two SDRAM chips. Both have a Kirkwood CPU (Marvell bootloader and its environment. The linux kernel and the initial ramdisk are loaded from the hard disk. +Important! Changes since v2019.07 +--------------------------------- +In u-boot v2019.07 the driver for the SATA port was changed to a new +one. This means that the old "ide" command and block interface is not +supported anymore. More important, the boot commands have changed. You have +to overwrite the boot commands in your envionment with the new ones: + + env default -f bootcmd_legacy + env default -f bootcmd_hdd + saveenv Rescue Mode ----------- diff --git a/board/ebv/socrates/qts/iocsr_config.h b/board/ebv/socrates/qts/iocsr_config.h index 011fa2bac3..18b9c6ce4d 100644 --- a/board/ebv/socrates/qts/iocsr_config.h +++ b/board/ebv/socrates/qts/iocsr_config.h @@ -108,7 +108,7 @@ const unsigned long iocsr_scan_chain2_table[] = { 0x00018004, 0x06001209, 0x00004000, - 0x20002412, + 0x20042412, 0x00904800, 0x00000030, 0x80000000, diff --git a/board/samtec/vining_fpga/socfpga.c b/board/samtec/vining_fpga/socfpga.c index d99aac6828..efc8ddf162 100644 --- a/board/samtec/vining_fpga/socfpga.c +++ b/board/samtec/vining_fpga/socfpga.c @@ -52,14 +52,7 @@ int misc_init_r(void) u32 serial; int ret; - /* EEPROM is at bus 0. */ - ret = i2c_set_bus_num(0); - if (ret) { - puts("Cannot select EEPROM I2C bus.\n"); - return 0; - } - - /* EEPROM is at address 0x50. */ + /* EEPROM is at address 0x50 (at bus CONFIG_SYS_EEPROM_BUS_NUM). */ ret = eeprom_read(0x50, 0, data, sizeof(data)); if (ret) { puts("Cannot read I2C EEPROM.\n"); diff --git a/board/sandbox/README.sandbox b/board/sandbox/README.sandbox index 9b09404294..48c1e2b9e7 100644 --- a/board/sandbox/README.sandbox +++ b/board/sandbox/README.sandbox @@ -392,6 +392,49 @@ state_setprop() which does this automatically and avoids running out of space. See existing code for examples. +Debugging the init sequence +--------------------------- + +If you get a failure in the initcall sequence, like this: + + initcall sequence 0000560775957c80 failed at call 0000000000048134 (err=-96) + +Then you use can use grep to see which init call failed, e.g.: + + $ grep 0000000000048134 u-boot.map + stdio_add_devices + +Of course another option is to run it with a debugger such as gdb: + + $ gdb u-boot + ... + (gdb) br initcall.h:41 + Breakpoint 1 at 0x4db9d: initcall.h:41. (2 locations) + +Note that two locations are reported, since this function is used in both +board_init_f() and board_init_r(). + + (gdb) r + Starting program: /tmp/b/sandbox/u-boot + [Thread debugging using libthread_db enabled] + Using host libthread_db library "/lib/x86_64-linux-gnu/libthread_db.so.1". + + U-Boot 2018.09-00264-ge0c2ba9814-dirty (Sep 22 2018 - 12:21:46 -0600) + + DRAM: 128 MiB + MMC: + + Breakpoint 1, initcall_run_list (init_sequence=0x5555559619e0 <init_sequence_f>) + at /scratch/sglass/cosarm/src/third_party/u-boot/files/include/initcall.h:41 + 41 printf("initcall sequence %p failed at call %p (err=%d)\n", + (gdb) print *init_fnc_ptr + $1 = (const init_fnc_t) 0x55555559c114 <stdio_add_devices> + (gdb) + + +This approach can be used on normal boards as well as sandbox. + + Testing ------- @@ -434,6 +477,9 @@ that are mapped into that memory: 0 CONFIG_SYS_FDT_LOAD_ADDR Device tree e000 CONFIG_BLOBLIST_ADDR Blob list 10000 CONFIG_MALLOC_F_ADDR Early memory allocation + f0000 CONFIG_PRE_CON_BUF_ADDR Pre-console buffer + 100000 CONFIG_TRACE_EARLY_ADDR Early trace buffer (if enabled) += -- diff --git a/board/sandbox/sandbox.c b/board/sandbox/sandbox.c index 397e7561d4..9ca1eca027 100644 --- a/board/sandbox/sandbox.c +++ b/board/sandbox/sandbox.c @@ -31,7 +31,7 @@ void flush_cache(unsigned long start, unsigned long size) /* system timer offset in ms */ static unsigned long sandbox_timer_offset; -void sandbox_timer_add_offset(unsigned long offset) +void timer_test_add_offset(unsigned long offset) { sandbox_timer_offset += offset; } diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c index 7c9b1ad82a..e89ed2153b 100644 --- a/board/st/stm32f746-disco/stm32f746-disco.c +++ b/board/st/stm32f746-disco/stm32f746-disco.c @@ -7,6 +7,8 @@ #include <common.h> #include <dm.h> #include <lcd.h> +#include <miiphy.h> +#include <phy_interface.h> #include <ram.h> #include <spl.h> #include <splash.h> @@ -123,8 +125,25 @@ int board_init(void) gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; #ifdef CONFIG_ETH_DESIGNWARE - /* Set >RMII mode */ - STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL; + const char *phy_mode; + int node; + + node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, "st,stm32-dwmac"); + if (node < 0) + return -1; + + phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL); + + switch (phy_get_interface_by_name(phy_mode)) { + case PHY_INTERFACE_MODE_RMII: + STM32_SYSCFG->pmc |= SYSCFG_PMC_MII_RMII_SEL; + break; + case PHY_INTERFACE_MODE_MII: + STM32_SYSCFG->pmc &= ~SYSCFG_PMC_MII_RMII_SEL; + break; + default: + printf("PHY interface %s not supported !\n", phy_mode); + } #endif #if defined(CONFIG_CMD_BMP) diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c index 28c9efa3a2..ba82292e35 100644 --- a/board/xilinx/microblaze-generic/microblaze-generic.c +++ b/board/xilinx/microblaze-generic/microblaze-generic.c @@ -24,10 +24,6 @@ DECLARE_GLOBAL_DATA_PTR; -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT) -static struct udevice *watchdog_dev __attribute__((section(".data"))) = NULL; -#endif /* !CONFIG_SPL_BUILD && CONFIG_WDT */ - ulong ram_base; int dram_init_banksize(void) @@ -43,44 +39,8 @@ int dram_init(void) return 0; }; -#ifdef CONFIG_WDT -/* Called by macro WATCHDOG_RESET */ -void watchdog_reset(void) -{ -#if !defined(CONFIG_SPL_BUILD) - ulong now; - static ulong next_reset; - - if (!watchdog_dev) - return; - - now = timer_get_us(); - - /* Do not reset the watchdog too often */ - if (now > next_reset) { - wdt_reset(watchdog_dev); - next_reset = now + 1000; - } -#endif /* !CONFIG_SPL_BUILD */ -} -#endif /* CONFIG_WDT */ - int board_late_init(void) { -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT) - watchdog_dev = NULL; - - if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev)) { - debug("Watchdog: Not found by seq!\n"); - if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) { - puts("Watchdog: Not found!\n"); - return 0; - } - } - - wdt_start(watchdog_dev, 0, 0); - puts("Watchdog: Started\n"); -#endif /* !CONFIG_SPL_BUILD && CONFIG_WDT */ #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SYSRESET_MICROBLAZE) int ret; diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index ea26aad16f..6857f2c0b8 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -18,10 +18,6 @@ DECLARE_GLOBAL_DATA_PTR; -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT) -static struct udevice *watchdog_dev __attribute__((section(".data"))) = NULL; -#endif - #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOARD_EARLY_INIT_F) int board_early_init_f(void) { @@ -31,19 +27,6 @@ int board_early_init_f(void) int board_init(void) { -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT) - if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev)) { - debug("Watchdog: Not found by seq!\n"); - if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) { - puts("Watchdog: Not found!\n"); - return 0; - } - } - - wdt_start(watchdog_dev, 0, 0); - puts("Watchdog: Started\n"); -# endif - return 0; } @@ -127,25 +110,3 @@ int dram_init(void) return 0; } #endif - -#if defined(CONFIG_WATCHDOG) -/* Called by macro WATCHDOG_RESET */ -void watchdog_reset(void) -{ -# if !defined(CONFIG_SPL_BUILD) - static ulong next_reset; - ulong now; - - if (!watchdog_dev) - return; - - now = timer_get_us(); - - /* Do not reset the watchdog too often */ - if (now > next_reset) { - wdt_reset(watchdog_dev); - next_reset = now + 1000; - } -# endif -} -#endif diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index 5189925beb..c840e92d9c 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -24,10 +24,6 @@ DECLARE_GLOBAL_DATA_PTR; -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT) -static struct udevice *watchdog_dev __attribute__((section(".data"))) = NULL; -#endif - #if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \ !defined(CONFIG_SPL_BUILD) static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC; @@ -344,44 +340,9 @@ int board_init(void) } #endif -#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT) - if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev)) { - debug("Watchdog: Not found by seq!\n"); - if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) { - puts("Watchdog: Not found!\n"); - return 0; - } - } - - wdt_start(watchdog_dev, 0, 0); - puts("Watchdog: Started\n"); -#endif - return 0; } -#ifdef CONFIG_WATCHDOG -/* Called by macro WATCHDOG_RESET */ -void watchdog_reset(void) -{ -# if !defined(CONFIG_SPL_BUILD) - static ulong next_reset; - ulong now; - - if (!watchdog_dev) - return; - - now = timer_get_us(); - - /* Do not reset the watchdog too often */ - if (now > next_reset) { - wdt_reset(watchdog_dev); - next_reset = now + 1000; - } -# endif -} -#endif - int board_early_init_r(void) { u32 val; |