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-rw-r--r--board/at91rm9200dk/at91rm9200dk.c2
-rw-r--r--board/incaip/incaip.c28
-rw-r--r--board/incaip/memsetup.S2
3 files changed, 30 insertions, 2 deletions
diff --git a/board/at91rm9200dk/at91rm9200dk.c b/board/at91rm9200dk/at91rm9200dk.c
index 7c3670bdf61..07def18fdca 100644
--- a/board/at91rm9200dk/at91rm9200dk.c
+++ b/board/at91rm9200dk/at91rm9200dk.c
@@ -23,7 +23,7 @@
*/
#include <common.h>
-#include <AT91RM9200.h>
+#include <asm/arch/AT91RM9200.h>
/* ------------------------------------------------------------------------- */
/*
diff --git a/board/incaip/incaip.c b/board/incaip/incaip.c
index 72f1c21512f..10171ddc102 100644
--- a/board/incaip/incaip.c
+++ b/board/incaip/incaip.c
@@ -27,6 +27,8 @@
#include <asm/inca-ip.h>
+extern uint incaip_get_cpuclk(void);
+
static ulong max_sdram_size(void)
{
/* The only supported SDRAM data width is 16bit.
@@ -127,3 +129,29 @@ long int initdram(int board_type)
return max_size;
}
+int checkboard (void)
+{
+
+ unsigned long chipid = *INCA_IP_WDT_CHIPID;
+ int part_num;
+
+ puts ("Board: INCA-IP ");
+ part_num = (chipid >> 12) & 0xffff;
+ switch (part_num) {
+ case 0xc0:
+ printf ("Standard Version, ");
+ break;
+ case 0xc1:
+ printf ("Basic Version, ");
+ break;
+ default:
+ printf ("Unknown Part Number 0x%x ", part_num);
+ break;
+ }
+
+ printf ("Chip V1.%ld, ", (chipid >> 28));
+
+ printf("CPU Speed %d MHz\n", incaip_get_cpuclk()/1000000);
+
+ return 0;
+}
diff --git a/board/incaip/memsetup.S b/board/incaip/memsetup.S
index 4faf627f077..0d4de5ad5e9 100644
--- a/board/incaip/memsetup.S
+++ b/board/incaip/memsetup.S
@@ -68,7 +68,7 @@ memsetup:
sw t1, EBU_ADDSEL0(t0)
#if CPU_CLOCK_RATE==150000000 /* 150 MHz clock for the MIPS core */
- li t1, 0xE841417E
+ li t1, 0xA841417E
sw t1, EBU_BUSCON0(t0) /* value set up by magic flash word */
sw t1, EBU_BUSCON2(t0)
#else /* 100 MHz */