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-rw-r--r--board/toradex/verdin-imx8mm/lpddr4_timing.c51
1 files changed, 24 insertions, 27 deletions
diff --git a/board/toradex/verdin-imx8mm/lpddr4_timing.c b/board/toradex/verdin-imx8mm/lpddr4_timing.c
index d114abf9d6..4dfec679b1 100644
--- a/board/toradex/verdin-imx8mm/lpddr4_timing.c
+++ b/board/toradex/verdin-imx8mm/lpddr4_timing.c
@@ -1,12 +1,11 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2020 Toradex
+ * Copyright 2023 Toradex
*
* Generated code from MX8M_DDR_tool
- * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga
*
- * DDR calibration created with mscale_ddr_tool_v210_setup.exe using
- * MX8M_Mini_LPDDR4_RPA_v14 Verdin iMX8MM V1.0.xlsx as of 1. Nov. 2019.
+ * DDR calibration created with mscale_ddr_tool_v3.31_setup.exe using
+ * MX8M_Mini_LPDDR4_RPA_v22 Verdin iMX8MM V1.0.xlsx as of 7. Aug. 2023.
*/
#include <linux/kernel.h>
@@ -17,22 +16,22 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{0x3d400304, 0x1},
{0x3d400030, 0x1},
{0x3d400000, 0xa1080020},
- {0x3d400020, 0x203},
+ {0x3d400020, 0x202},
{0x3d400024, 0x3a980},
- {0x3d400064, 0x5b00d2},
+ {0x3d400064, 0x2d00d2},
{0x3d4000d0, 0xc00305ba},
{0x3d4000d4, 0x940000},
{0x3d4000dc, 0xd4002d},
{0x3d4000e0, 0x310000},
{0x3d4000e8, 0x66004d},
{0x3d4000ec, 0x16004d},
- {0x3d400100, 0x191e1920},
+ {0x3d400100, 0x191e0c20},
{0x3d400104, 0x60630},
{0x3d40010c, 0xb0b000},
{0x3d400110, 0xe04080e},
{0x3d400114, 0x2040c0c},
{0x3d400118, 0x1010007},
- {0x3d40011c, 0x401},
+ {0x3d40011c, 0x402},
{0x3d400130, 0x20600},
{0x3d400134, 0xc100002},
{0x3d400138, 0xd8},
@@ -49,7 +48,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{0x3d4001b0, 0x11},
{0x3d4001c0, 0x1},
{0x3d4001c4, 0x1},
- {0x3d4000f4, 0xc99},
+ {0x3d4000f4, 0x699},
{0x3d400108, 0x70e1617},
{0x3d400200, 0x1f},
{0x3d40020c, 0x0},
@@ -57,6 +56,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{0x3d400204, 0x80808},
{0x3d400214, 0x7070707},
{0x3d400218, 0x7070707},
+ {0x3d40021c, 0xf0f},
{0x3d400250, 0x29001701},
{0x3d400254, 0x2c},
{0x3d40025c, 0x4000030},
@@ -68,22 +68,22 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{0x3d400498, 0x620096},
{0x3d40049c, 0x1100e07},
{0x3d4004a0, 0xc8012c},
- {0x3d402020, 0x1},
+ {0x3d402020, 0x0},
{0x3d402024, 0x7d00},
{0x3d402050, 0x20d040},
- {0x3d402064, 0xc001c},
+ {0x3d402064, 0x6001c},
{0x3d4020dc, 0x840000},
{0x3d4020e0, 0x310000},
{0x3d4020e8, 0x66004d},
{0x3d4020ec, 0x16004d},
- {0x3d402100, 0xa040305},
+ {0x3d402100, 0xa040105},
{0x3d402104, 0x30407},
{0x3d402108, 0x203060b},
{0x3d40210c, 0x505000},
{0x3d402110, 0x2040202},
{0x3d402114, 0x2030202},
{0x3d402118, 0x1010004},
- {0x3d40211c, 0x301},
+ {0x3d40211c, 0x302},
{0x3d402130, 0x20300},
{0x3d402134, 0xa100002},
{0x3d402138, 0x1d},
@@ -92,8 +92,8 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{0x3d402190, 0x3818200},
{0x3d402194, 0x80303},
{0x3d4021b4, 0x100},
- {0x3d4020f4, 0xc99},
- {0x3d403020, 0x1},
+ {0x3d4020f4, 0x599},
+ {0x3d403020, 0x0},
{0x3d403024, 0x1f40},
{0x3d403050, 0x20d040},
{0x3d403064, 0x30007},
@@ -108,7 +108,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{0x3d403110, 0x2040202},
{0x3d403114, 0x2030202},
{0x3d403118, 0x1010004},
- {0x3d40311c, 0x301},
+ {0x3d40311c, 0x302},
{0x3d403130, 0x20300},
{0x3d403134, 0xa100002},
{0x3d403138, 0x8},
@@ -117,7 +117,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{0x3d403190, 0x3818200},
{0x3d403194, 0x80303},
{0x3d4031b4, 0x100},
- {0x3d4030f4, 0xc99},
+ {0x3d4030f4, 0x599},
{0x3d400028, 0x0},
};
@@ -205,8 +205,8 @@ struct dram_cfg_param ddr_ddrphy_cfg[] = {
{0x220024, 0x1ab},
{0x2003a, 0x0},
{0x20056, 0x3},
- {0x120056, 0xa},
- {0x220056, 0xa},
+ {0x120056, 0x3},
+ {0x220056, 0x3},
{0x1004d, 0xe00},
{0x1014d, 0xe00},
{0x1104d, 0xe00},
@@ -1058,7 +1058,6 @@ struct dram_cfg_param ddr_fsp0_cfg[] = {
{0x54008, 0x131f},
{0x54009, 0xc8},
{0x5400b, 0x2},
- {0x5400d, 0x100},
{0x54012, 0x110},
{0x54019, 0x2dd4},
{0x5401a, 0x31},
@@ -1098,7 +1097,6 @@ struct dram_cfg_param ddr_fsp1_cfg[] = {
{0x54008, 0x121f},
{0x54009, 0xc8},
{0x5400b, 0x2},
- {0x5400d, 0x100},
{0x54012, 0x110},
{0x54019, 0x84},
{0x5401a, 0x31},
@@ -1138,7 +1136,6 @@ struct dram_cfg_param ddr_fsp2_cfg[] = {
{0x54008, 0x121f},
{0x54009, 0xc8},
{0x5400b, 0x2},
- {0x5400d, 0x100},
{0x54012, 0x110},
{0x54019, 0x84},
{0x5401a, 0x31},
@@ -1204,7 +1201,7 @@ struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
{0x5403b, 0x4d},
{0x5403c, 0x4d},
{0x5403d, 0x1600},
- { 0xd0000, 0x1 },
+ {0xd0000, 0x1},
};
/* DRAM PHY init engine image */
@@ -1697,15 +1694,15 @@ struct dram_cfg_param ddr_phy_pie[] = {
{0x400d6, 0x20a},
{0x400d7, 0x20b},
{0x2003a, 0x2},
- {0x2000b, 0x5d},
+ {0x2000b, 0x34b},
{0x2000c, 0xbb},
{0x2000d, 0x753},
{0x2000e, 0x2c},
- {0x12000b, 0xc},
+ {0x12000b, 0x70},
{0x12000c, 0x19},
{0x12000d, 0xfa},
{0x12000e, 0x10},
- {0x22000b, 0x3},
+ {0x22000b, 0x1c},
{0x22000c, 0x6},
{0x22000d, 0x3e},
{0x22000e, 0x10},
@@ -1846,5 +1843,5 @@ struct dram_timing_info dram_timing = {
.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
.ddrphy_pie = ddr_phy_pie,
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
- .fsp_table = { 3000, 400, 100, },
+ .fsp_table = {3000, 400, 100,},
};