summaryrefslogtreecommitdiff
path: root/board/terasic/sockit/qts/sdram_config.h
diff options
context:
space:
mode:
Diffstat (limited to 'board/terasic/sockit/qts/sdram_config.h')
-rw-r--r--board/terasic/sockit/qts/sdram_config.h30
1 files changed, 15 insertions, 15 deletions
diff --git a/board/terasic/sockit/qts/sdram_config.h b/board/terasic/sockit/qts/sdram_config.h
index 81c7d8e9a8..769aa77394 100644
--- a/board/terasic/sockit/qts/sdram_config.h
+++ b/board/terasic/sockit/qts/sdram_config.h
@@ -32,11 +32,11 @@
#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0
#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 11
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 8
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 12
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6
@@ -46,7 +46,7 @@
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20
-#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3
#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512
#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0
@@ -127,8 +127,8 @@
/* Sequencer defines configuration */
#define AFI_RATE_RATIO 1
-#define CALIB_LFIFO_OFFSET 8
-#define CALIB_VFIFO_OFFSET 6
+#define CALIB_LFIFO_OFFSET 12
+#define CALIB_VFIFO_OFFSET 10
#define ENABLE_SUPER_QUICK_CALIBRATION 0
#define IO_DELAY_PER_DCHAIN_TAP 25
#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25
@@ -147,7 +147,7 @@
#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0
#define MAX_LATENCY_COUNT_WIDTH 5
#define READ_VALID_FIFO_SIZE 16
-#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048d
+#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048c
#define RW_MGR_MEM_ADDRESS_MIRRORING 0
#define RW_MGR_MEM_DATA_MASK_WIDTH 4
#define RW_MGR_MEM_DATA_WIDTH 32
@@ -171,16 +171,16 @@
const u32 ac_rom_init[] = {
0x20700000,
0x20780000,
- 0x10080431,
- 0x10080530,
- 0x10090044,
- 0x100a0008,
+ 0x10080471,
+ 0x10080570,
+ 0x10090006,
+ 0x100a0218,
0x100b0000,
0x10380400,
- 0x10080449,
- 0x100804c8,
- 0x100a0024,
- 0x10090010,
+ 0x10080469,
+ 0x100804e8,
+ 0x100a0006,
+ 0x10090218,
0x100b0000,
0x30780000,
0x38780000,