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-rw-r--r--board/logodl/config.mk2
-rw-r--r--board/logodl/flash.c51
-rw-r--r--board/logodl/logodl.c2
-rw-r--r--board/logodl/memsetup.S137
-rw-r--r--board/logodl/u-boot.lds20
5 files changed, 105 insertions, 107 deletions
diff --git a/board/logodl/config.mk b/board/logodl/config.mk
index 41663579860..76c382d57cf 100644
--- a/board/logodl/config.mk
+++ b/board/logodl/config.mk
@@ -11,5 +11,5 @@
# FIXME: armboot does only work correctly when being compiled
# # for the addresses _after_ relocation to RAM!! Otherwhise the
# # .bss segment is assumed in flash...
-#
+#
TEXT_BASE = 0x083E0000
diff --git a/board/logodl/flash.c b/board/logodl/flash.c
index 3837401fd34..cef0b4dee47 100644
--- a/board/logodl/flash.c
+++ b/board/logodl/flash.c
@@ -82,18 +82,18 @@ ulong flash_init(void)
flash_info[i].size = FLASH_BANK_SIZE;
flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
- switch (i)
- {
- case 0:
- flashbase = PHYS_FLASH_1;
- break;
- case 1:
- flashbase = PHYS_FLASH_2;
- break;
- default:
- panic("configured to many flash banks!\n");
- break;
- }
+ switch (i)
+ {
+ case 0:
+ flashbase = PHYS_FLASH_1;
+ break;
+ case 1:
+ flashbase = PHYS_FLASH_2;
+ break;
+ default:
+ panic("configured to many flash banks!\n");
+ break;
+ }
for (j = 0; j < flash_info[i].sector_count; j++)
{
flash_info[i].start[j] = flashbase + j*MAIN_SECT_SIZE;
@@ -208,32 +208,32 @@ void flash_print_info (flash_info_t *info)
case FLASH_AM640U:
fmt = "29LV641D (64 Mbit, uniform sectors)\n";
break;
- case FLASH_28F800C3B:
- case FLASH_28F800C3T:
+ case FLASH_28F800C3B:
+ case FLASH_28F800C3T:
fmt = "28F800C3%s (8 Mbit, %s)\n";
break;
case FLASH_INTEL800B:
case FLASH_INTEL800T:
fmt = "28F800B3%s (8 Mbit, %s)\n";
break;
- case FLASH_28F160C3B:
- case FLASH_28F160C3T:
+ case FLASH_28F160C3B:
+ case FLASH_28F160C3T:
fmt = "28F160C3%s (16 Mbit, %s)\n";
break;
case FLASH_INTEL160B:
case FLASH_INTEL160T:
fmt = "28F160B3%s (16 Mbit, %s)\n";
break;
- case FLASH_28F320C3B:
- case FLASH_28F320C3T:
+ case FLASH_28F320C3B:
+ case FLASH_28F320C3T:
fmt = "28F320C3%s (32 Mbit, %s)\n";
break;
case FLASH_INTEL320B:
case FLASH_INTEL320T:
fmt = "28F320B3%s (32 Mbit, %s)\n";
break;
- case FLASH_28F640C3B:
- case FLASH_28F640C3T:
+ case FLASH_28F640C3B:
+ case FLASH_28F640C3T:
fmt = "28F640C3%s (64 Mbit, %s)\n";
break;
case FLASH_INTEL640B:
@@ -554,15 +554,15 @@ int bad_write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
left > 0 && res == 0;
addr += sizeof(data), left -= sizeof(data) - bytes) {
- bytes = addr & (sizeof(data) - 1);
- addr &= ~(sizeof(data) - 1);
+ bytes = addr & (sizeof(data) - 1);
+ addr &= ~(sizeof(data) - 1);
/* combine source and destination data so can program
* an entire word of 16 or 32 bits
*/
- for (i = 0; i < sizeof(data); i++) {
- data <<= 8;
- if (i < bytes || i - bytes >= left )
+ for (i = 0; i < sizeof(data); i++) {
+ data <<= 8;
+ if (i < bytes || i - bytes >= left )
data += *((uchar *)addr + i);
else
data += *src++;
@@ -662,7 +662,6 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
}
-
/*-----------------------------------------------------------------------
* Write a word to Flash for AMD FLASH
* A word is 16 or 32 bits, whichever the bus width of the flash bank
diff --git a/board/logodl/logodl.c b/board/logodl/logodl.c
index f16c05bb656..95634ac0044 100644
--- a/board/logodl/logodl.c
+++ b/board/logodl/logodl.c
@@ -62,7 +62,7 @@ int dram_init (void)
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
- return 0;
+ return 0;
}
diff --git a/board/logodl/memsetup.S b/board/logodl/memsetup.S
index 60f9d50b58e..68577ca0699 100644
--- a/board/logodl/memsetup.S
+++ b/board/logodl/memsetup.S
@@ -159,7 +159,7 @@ memsetup:
mem_init:
- ldr r1, =MEMC_BASE /* get memory controller base addr. */
+ ldr r1, =MEMC_BASE /* get memory controller base addr. */
/* ---------------------------------------------------------------- */
/* Step 2a: Initialize Asynchronous static memory controller */
@@ -167,65 +167,65 @@ mem_init:
/* MSC registers: timing, bus width, mem type */
- /* MSC0: nCS(0,1) */
- ldr r2, =CFG_MSC0_VAL
- str r2, [r1, #MSC0_OFFSET]
- ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
+ /* MSC0: nCS(0,1) */
+ ldr r2, =CFG_MSC0_VAL
+ str r2, [r1, #MSC0_OFFSET]
+ ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
/* that data latches */
- /* MSC1: nCS(2,3) */
- ldr r2, =CFG_MSC1_VAL
- str r2, [r1, #MSC1_OFFSET]
- ldr r2, [r1, #MSC1_OFFSET]
+ /* MSC1: nCS(2,3) */
+ ldr r2, =CFG_MSC1_VAL
+ str r2, [r1, #MSC1_OFFSET]
+ ldr r2, [r1, #MSC1_OFFSET]
/* MSC2: nCS(4,5) */
- ldr r2, =CFG_MSC2_VAL
- str r2, [r1, #MSC2_OFFSET]
- ldr r2, [r1, #MSC2_OFFSET]
+ ldr r2, =CFG_MSC2_VAL
+ str r2, [r1, #MSC2_OFFSET]
+ ldr r2, [r1, #MSC2_OFFSET]
/* ---------------------------------------------------------------- */
/* Step 2b: Initialize Card Interface */
/* ---------------------------------------------------------------- */
/* MECR: Memory Expansion Card Register */
- ldr r2, =CFG_MECR_VAL
- str r2, [r1, #MECR_OFFSET]
+ ldr r2, =CFG_MECR_VAL
+ str r2, [r1, #MECR_OFFSET]
ldr r2, [r1, #MECR_OFFSET]
/* MCMEM0: Card Interface slot 0 timing */
- ldr r2, =CFG_MCMEM0_VAL
- str r2, [r1, #MCMEM0_OFFSET]
+ ldr r2, =CFG_MCMEM0_VAL
+ str r2, [r1, #MCMEM0_OFFSET]
ldr r2, [r1, #MCMEM0_OFFSET]
- /* MCMEM1: Card Interface slot 1 timing */
- ldr r2, =CFG_MCMEM1_VAL
- str r2, [r1, #MCMEM1_OFFSET]
+ /* MCMEM1: Card Interface slot 1 timing */
+ ldr r2, =CFG_MCMEM1_VAL
+ str r2, [r1, #MCMEM1_OFFSET]
ldr r2, [r1, #MCMEM1_OFFSET]
/* MCATT0: Card Interface Attribute Space Timing, slot 0 */
- ldr r2, =CFG_MCATT0_VAL
- str r2, [r1, #MCATT0_OFFSET]
+ ldr r2, =CFG_MCATT0_VAL
+ str r2, [r1, #MCATT0_OFFSET]
ldr r2, [r1, #MCATT0_OFFSET]
/* MCATT1: Card Interface Attribute Space Timing, slot 1 */
- ldr r2, =CFG_MCATT1_VAL
- str r2, [r1, #MCATT1_OFFSET]
+ ldr r2, =CFG_MCATT1_VAL
+ str r2, [r1, #MCATT1_OFFSET]
ldr r2, [r1, #MCATT1_OFFSET]
/* MCIO0: Card Interface I/O Space Timing, slot 0 */
- ldr r2, =CFG_MCIO0_VAL
- str r2, [r1, #MCIO0_OFFSET]
+ ldr r2, =CFG_MCIO0_VAL
+ str r2, [r1, #MCIO0_OFFSET]
ldr r2, [r1, #MCIO0_OFFSET]
/* MCIO1: Card Interface I/O Space Timing, slot 1 */
- ldr r2, =CFG_MCIO1_VAL
- str r2, [r1, #MCIO1_OFFSET]
+ ldr r2, =CFG_MCIO1_VAL
+ str r2, [r1, #MCIO1_OFFSET]
ldr r2, [r1, #MCIO1_OFFSET]
/* ---------------------------------------------------------------- */
- /* Step 2c: Write FLYCNFG FIXME: what's that??? */
- /* ---------------------------------------------------------------- */
+ /* Step 2c: Write FLYCNFG FIXME: what's that??? */
+ /* ---------------------------------------------------------------- */
- /* test if we run from flash or RAM - RAM/BDI: don't setup RAM */
+ /* test if we run from flash or RAM - RAM/BDI: don't setup RAM */
adr r3, mem_init /* r0 <- current position of code */
ldr r2, =mem_init
cmp r3, r2 /* skip init if in place */
@@ -233,8 +233,8 @@ mem_init:
/* ---------------------------------------------------------------- */
- /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
- /* ---------------------------------------------------------------- */
+ /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
+ /* ---------------------------------------------------------------- */
/* Before accessing MDREFR we need a valid DRI field, so we set */
/* this to power on defaults + DRI field. */
@@ -246,7 +246,7 @@ mem_init:
orr r4, r4, r3
str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
+ ldr r4, [r1, #MDREFR_OFFSET]
/* ---------------------------------------------------------------- */
@@ -262,9 +262,9 @@ mem_init:
/* FIXME: we use async mode for now */
- /* ---------------------------------------------------------------- */
- /* Step 4: Initialize SDRAM */
- /* ---------------------------------------------------------------- */
+ /* ---------------------------------------------------------------- */
+ /* Step 4: Initialize SDRAM */
+ /* ---------------------------------------------------------------- */
/* Step 4a: assert MDREFR:K?RUN and configure */
/* MDREFR:K1DB2 and MDREFR:K2DB2 as desired. */
@@ -277,16 +277,16 @@ mem_init:
bic r4, r4, #(MDREFR_SLFRSH)
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
+ str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
+ ldr r4, [r1, #MDREFR_OFFSET]
/* Step 4c: assert MDREFR:E1PIN and E0PIO */
orr r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN)
- str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
- ldr r4, [r1, #MDREFR_OFFSET]
+ str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
+ ldr r4, [r1, #MDREFR_OFFSET]
/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
@@ -295,8 +295,8 @@ mem_init:
ldr r4, =CFG_MDCNFG_VAL
bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
- str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
- ldr r4, [r1, #MDCNFG_OFFSET]
+ str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
+ ldr r4, [r1, #MDCNFG_OFFSET]
/* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
@@ -345,8 +345,8 @@ mem_init:
/* Step 4h: Write MDMRS. */
- ldr r2, =CFG_MDMRS_VAL
- str r2, [r1, #MDMRS_OFFSET]
+ ldr r2, =CFG_MDMRS_VAL
+ str r2, [r1, #MDMRS_OFFSET]
/* We are finished with Intel's memory controller initialisation */
@@ -357,17 +357,17 @@ mem_init:
initirqs:
- mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
- ldr r2, =ICLR
- str r1, [r2]
+ mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
+ ldr r2, =ICLR
+ str r1, [r2]
- ldr r2, =ICMR /* mask all interrupts at the controller */
- str r1, [r2]
+ ldr r2, =ICMR /* mask all interrupts at the controller */
+ str r1, [r2]
- /* ---------------------------------------------------------------- */
+ /* ---------------------------------------------------------------- */
/* Clock initialisation */
- /* ---------------------------------------------------------------- */
+ /* ---------------------------------------------------------------- */
initclks:
@@ -376,34 +376,34 @@ initclks:
/* Turn Off ALL on-chip peripheral clocks for re-configuration */
/* Note: See label 'ENABLECLKS' for the re-enabling */
- ldr r1, =CKEN
- mov r2, #0
- str r2, [r1]
+ ldr r1, =CKEN
+ mov r2, #0
+ str r2, [r1]
- /* default value in case no valid rotary switch setting is found */
- ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
+ /* default value in case no valid rotary switch setting is found */
+ ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
- /* ... and write the core clock config register */
- ldr r1, =CCCR
- str r2, [r1]
+ /* ... and write the core clock config register */
+ ldr r1, =CCCR
+ str r2, [r1]
/* enable the 32Khz oscillator for RTC and PowerManager */
/*
- ldr r1, =OSCC
- mov r2, #OSCC_OON
- str r2, [r1]
+ ldr r1, =OSCC
+ mov r2, #OSCC_OON
+ str r2, [r1]
*/
/* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
/* has settled. */
60:
- ldr r2, [r1]
- ands r2, r2, #1
- beq 60b
+ ldr r2, [r1]
+ ands r2, r2, #1
+ beq 60b
/* ---------------------------------------------------------------- */
/* */
- /* ---------------------------------------------------------------- */
+ /* ---------------------------------------------------------------- */
/* Save SDRAM size */
ldr r1, =DRAM_SIZE
@@ -428,11 +428,10 @@ initclks:
mcr p14,0,r0,c10,c0,0 /* dcsr */
#endif
- /* ---------------------------------------------------------------- */
+ /* ---------------------------------------------------------------- */
/* End memsetup */
- /* ---------------------------------------------------------------- */
+ /* ---------------------------------------------------------------- */
endmemsetup:
mov pc, lr
-
diff --git a/board/logodl/u-boot.lds b/board/logodl/u-boot.lds
index 46beb152c77..5aef1279335 100644
--- a/board/logodl/u-boot.lds
+++ b/board/logodl/u-boot.lds
@@ -26,29 +26,29 @@ OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
- . = 0x00000000;
+ . = 0x00000000;
- . = ALIGN(4);
+ . = ALIGN(4);
.text :
{
cpu/pxa/start.o (.text)
*(.text)
}
- . = ALIGN(4);
- .rodata : { *(.rodata) }
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
- . = ALIGN(4);
- .data : { *(.data) }
+ . = ALIGN(4);
+ .data : { *(.data) }
- . = ALIGN(4);
- .got : { *(.got) }
+ . = ALIGN(4);
+ .got : { *(.got) }
armboot_end_data = .;
- . = ALIGN(4);
+ . = ALIGN(4);
bss_start = .;
- .bss : { *(.bss) }
+ .bss : { *(.bss) }
bss_end = .;
armboot_end = .;
generated by cgit v1.2.3 (git 2.0.4) at 2024-11-12 20:23:28 +0000