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-rw-r--r--board/keymile/kmp204x/kmp204x.c75
-rw-r--r--board/keymile/kmp204x/kmp204x.h3
-rw-r--r--board/keymile/kmp204x/pbi.cfg43
-rw-r--r--board/keymile/kmp204x/pci.c17
-rw-r--r--board/keymile/kmp204x/qrio.c31
-rw-r--r--board/keymile/kmp204x/rcw_kmp204x.cfg2
6 files changed, 145 insertions, 26 deletions
diff --git a/board/keymile/kmp204x/kmp204x.c b/board/keymile/kmp204x/kmp204x.c
index 95a19cdb2c1..6bc8eb85eaa 100644
--- a/board/keymile/kmp204x/kmp204x.c
+++ b/board/keymile/kmp204x/kmp204x.c
@@ -79,7 +79,7 @@ int get_scl(void)
#define ZL30158_RST 8
-#define ZL30343_RST 9
+#define BFTIC4_RST 0
int board_early_init_f(void)
{
@@ -88,13 +88,15 @@ int board_early_init_f(void)
/* board only uses the DDR_MCK0, so disable the DDR_MCK1/2/3 */
setbits_be32(&gur->ddrclkdr, 0x001f000f);
- /* take the Zarlinks out of reset as soon as possible */
- qrio_prst(ZL30158_RST, false, false);
- qrio_prst(ZL30343_RST, false, false);
+ /* set the BFTIC's prstcfg to reset at power-up and unit reset only */
+ qrio_prstcfg(BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST);
+ /* and enable WD on it */
+ qrio_wdmask(BFTIC4_RST, true);
- /* and set their reset to power-up only */
- qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_RST);
- qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_RST);
+ /* set the ZL30138's prstcfg to reset at power-up and unit reset only */
+ qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_UNIT_RST);
+ /* and take it out of reset as soon as possible (needed for Hooper) */
+ qrio_prst(ZL30158_RST, false, false);
return 0;
}
@@ -113,6 +115,12 @@ int board_early_init_r(void)
if (ret)
printf("error triggering PCIe FPGA config\n");
+ /* enable the Unit LED (red) & Boot LED (on) */
+ qrio_set_leds();
+
+ /* enable Application Buffer */
+ qrio_enable_app_buffer();
+
return ret;
}
@@ -121,16 +129,37 @@ unsigned long get_board_sys_clk(unsigned long dummy)
return 66666666;
}
+#define ETH_FRONT_PHY_RST 15
+#define QSFP2_RST 11
+#define QSFP1_RST 10
+#define ZL30343_RST 9
+
int misc_init_f(void)
{
/* configure QRIO pis for i2c deblocking */
i2c_deblock_gpio_cfg();
+ /* configure the front phy's prstcfg and take it out of reset */
+ qrio_prstcfg(ETH_FRONT_PHY_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
+ qrio_prst(ETH_FRONT_PHY_RST, false, false);
+
+ /* set the ZL30343 prstcfg to reset at power-up and unit reset only */
+ qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_UNIT_RST);
+ /* and enable the WD on it */
+ qrio_wdmask(ZL30343_RST, true);
+
+ /* set the QSFPs' prstcfg to reset at power-up and unit rst only */
+ qrio_prstcfg(QSFP1_RST, PRSTCFG_POWUP_UNIT_RST);
+ qrio_prstcfg(QSFP2_RST, PRSTCFG_POWUP_UNIT_RST);
+
+ /* and enable the WD on them */
+ qrio_wdmask(QSFP1_RST, true);
+ qrio_wdmask(QSFP2_RST, true);
+
return 0;
}
#define NUM_SRDS_BANKS 2
-#define PHY_RST 15
int misc_init_r(void)
{
@@ -151,9 +180,6 @@ int misc_init_r(void)
}
}
- /* take the mgmt eth phy out of reset */
- qrio_prst(PHY_RST, false, false);
-
return 0;
}
@@ -166,9 +192,23 @@ int hush_init_var(void)
#endif
#if defined(CONFIG_LAST_STAGE_INIT)
+
int last_stage_init(void)
{
+#if defined(CONFIG_KMCOGE4)
+ /* on KMCOGE4, the BFTIC4 is on the LBAPP2 */
+ struct bfticu_iomap *bftic4 =
+ (struct bfticu_iomap *)CONFIG_SYS_LBAPP2_BASE;
+ u8 dip_switch = in_8((u8 *)&(bftic4->mswitch)) & BFTICU_DIPSWITCH_MASK;
+
+ if (dip_switch != 0) {
+ /* start bootloader */
+ puts("DIP: Enabled\n");
+ setenv("actual_bank", "0");
+ }
+#endif
set_km_env();
+
return 0;
}
#endif
@@ -232,3 +272,16 @@ void ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_fman_mac_addresses(blob);
#endif
}
+
+#if defined(CONFIG_POST)
+
+/* DIC26_SELFTEST GPIO used to start factory test sw */
+#define SELFTEST_PORT GPIO_A
+#define SELFTEST_PIN 31
+
+int post_hotkeys_pressed(void)
+{
+ qrio_gpio_direction_input(SELFTEST_PORT, SELFTEST_PIN);
+ return qrio_get_gpio(SELFTEST_PORT, SELFTEST_PIN);
+}
+#endif
diff --git a/board/keymile/kmp204x/kmp204x.h b/board/keymile/kmp204x/kmp204x.h
index 0267596e4e5..afede994f17 100644
--- a/board/keymile/kmp204x/kmp204x.h
+++ b/board/keymile/kmp204x/kmp204x.h
@@ -20,6 +20,9 @@ void qrio_gpio_direction_input(u8 port_off, u8 gpio_nr);
#define PRSTCFG_POWUP_RST 0x3
void qrio_prst(u8 bit, bool en, bool wden);
+void qrio_wdmask(u8 bit, bool wden);
void qrio_prstcfg(u8 bit, u8 mode);
+void qrio_set_leds(void);
+void qrio_enable_app_buffer(void);
void pci_of_setup(void *blob, bd_t *bd);
diff --git a/board/keymile/kmp204x/pbi.cfg b/board/keymile/kmp204x/pbi.cfg
index 9af8bd5b57a..1e0a171d88b 100644
--- a/board/keymile/kmp204x/pbi.cfg
+++ b/board/keymile/kmp204x/pbi.cfg
@@ -8,16 +8,47 @@
#
#PBI commands
-#Workaround for A-006559 needed for rev 2.0 of P2041 silicon
-#Freescale's errarta sheet suggests it may be done with PBI
+#Configure ALTCBAR for DCSR -> DCSR@89000000
+091380c0 000009C4
09000010 00000000
+091380c0 000009C4
09000014 00000000
+091380c0 000009C4
09000018 81d00000
-09021008 0000f000
-09021028 0000f000
-09021048 0000f000
-09021068 0000f000
+#Workaround for A-004849
+091380c0 000009C4
+890B0050 00000002
+091380c0 000009C4
+890B0054 00000002
+091380c0 000009C4
+890B0058 00000002
+091380c0 000009C4
+890B005C 00000002
+091380c0 000009C4
+890B0090 00000002
+091380c0 000009C4
+890B0094 00000002
+091380c0 000009C4
+890B0098 00000002
+091380c0 000009C4
+890B009C 00000002
+091380c0 000009C4
+890B0108 00000012
+091380c0 000009C4
+#Workaround for A-006559 needed for rev 2.0 of P2041 silicon
+89021008 0000f000
+091380c0 000009C4
+89021028 0000f000
+091380c0 000009C4
+89021048 0000f000
+091380c0 000009C4
+89021068 0000f000
+091380c0 000009C4
+#Flush PBL data
+09138000 00000000
+#Disable ALTCBAR
09000018 00000000
+091380c0 000009C4
#Initialize CPC1 as 1MB SRAM
09010000 00200400
09138000 00000000
diff --git a/board/keymile/kmp204x/pci.c b/board/keymile/kmp204x/pci.c
index a484eb57495..2b0b054a11c 100644
--- a/board/keymile/kmp204x/pci.c
+++ b/board/keymile/kmp204x/pci.c
@@ -94,20 +94,23 @@ err_out:
}
#define PCIE_SW_RST 14
-#define PEXHC_SW_RST 13
-#define HOOPER_SW_RST 12
+#define PEXHC_RST 13
+#define HOOPER_RST 12
void pci_init_board(void)
{
- /* first wait for the PCIe FPGA to be configured
+ qrio_prstcfg(PCIE_SW_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
+ qrio_prstcfg(PEXHC_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
+ qrio_prstcfg(HOOPER_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
+
+ /* wait for the PCIe FPGA to be configured
* it has been triggered earlier in board_early_init_r */
- int ret = wait_for_fpga_config();
- if (ret)
+ if (wait_for_fpga_config())
printf("error finishing PCIe FPGA config\n");
qrio_prst(PCIE_SW_RST, false, false);
- qrio_prst(PEXHC_SW_RST, false, false);
- qrio_prst(HOOPER_SW_RST, false, false);
+ qrio_prst(PEXHC_RST, false, false);
+ qrio_prst(HOOPER_RST, false, false);
/* Hooper is not direcly PCIe capable */
mdelay(50);
diff --git a/board/keymile/kmp204x/qrio.c b/board/keymile/kmp204x/qrio.c
index 49f9aa25462..b6ba93ada8f 100644
--- a/board/keymile/kmp204x/qrio.c
+++ b/board/keymile/kmp204x/qrio.c
@@ -91,7 +91,7 @@ void qrio_set_opendrain_gpio(u8 port_off, u8 gpio_nr, u8 val)
#define WDMASK_OFF 0x16
-static void qrio_wdmask(u8 bit, bool wden)
+void qrio_wdmask(u8 bit, bool wden)
{
u16 wdmask;
void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
@@ -144,3 +144,32 @@ void qrio_prstcfg(u8 bit, u8 mode)
out_be32(qrio_base + PRSTCFG_OFF, prstcfg);
}
+
+#define CTRLH_OFF 0x02
+#define CTRLH_WRL_BOOT 0x01
+#define CTRLH_WRL_UNITRUN 0x02
+
+void qrio_set_leds(void)
+{
+ u8 ctrlh;
+ void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+ /* set UNIT LED to RED and BOOT LED to ON */
+ ctrlh = in_8(qrio_base + CTRLH_OFF);
+ ctrlh |= (CTRLH_WRL_BOOT | CTRLH_WRL_UNITRUN);
+ out_8(qrio_base + CTRLH_OFF, ctrlh);
+}
+
+#define CTRLL_OFF 0x03
+#define CTRLL_WRB_BUFENA 0x20
+
+void qrio_enable_app_buffer(void)
+{
+ u8 ctrll;
+ void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;
+
+ /* enable application buffer */
+ ctrll = in_8(qrio_base + CTRLL_OFF);
+ ctrll |= (CTRLL_WRB_BUFENA);
+ out_8(qrio_base + CTRLL_OFF, ctrll);
+}
diff --git a/board/keymile/kmp204x/rcw_kmp204x.cfg b/board/keymile/kmp204x/rcw_kmp204x.cfg
index 2d4c48cb9cd..236d5138bc7 100644
--- a/board/keymile/kmp204x/rcw_kmp204x.cfg
+++ b/board/keymile/kmp204x/rcw_kmp204x.cfg
@@ -7,5 +7,5 @@ aa55aa55 010e0100
#64 bytes RCW data
14600000 00000000 28200000 00000000
148E70CF CFC02000 58000000 41000000
-00000000 00000000 00000000 F0428002
+00000000 00000000 00000000 F0428816
00000000 00000000 00000000 00000000
generated by cgit v1.2.3 (git 2.0.4) at 2024-09-09 04:04:29 +0000