diff options
Diffstat (limited to 'board/gateworks/gw_ventana/gw_ventana_spl.c')
| -rw-r--r-- | board/gateworks/gw_ventana/gw_ventana_spl.c | 60 |
1 files changed, 59 insertions, 1 deletions
diff --git a/board/gateworks/gw_ventana/gw_ventana_spl.c b/board/gateworks/gw_ventana/gw_ventana_spl.c index 97fd346ebf..668e1122e8 100644 --- a/board/gateworks/gw_ventana/gw_ventana_spl.c +++ b/board/gateworks/gw_ventana/gw_ventana_spl.c @@ -220,6 +220,50 @@ static struct mx6_ddr3_cfg mt41k256m16ha_125 = { * calibration - these are the various CPU/DDR3 combinations we support */ +static struct mx6_mmdc_calibration mx6dq_128x16_mmdc_calib = { + /* write leveling calibration determine */ + .p0_mpwldectrl0 = 0x00190017, + /* Read DQS Gating calibration */ + .p0_mpdgctrl0 = 0x43380347, + /* Read Calibration: DQS delay relative to DQ read access */ + .p0_mprddlctl = 0x3C313539, + /* Write Calibration: DQ/DM delay relative to DQS write access */ + .p0_mpwrdlctl = 0x36393C39, +}; + +static struct mx6_mmdc_calibration mx6dq_256x16_mmdc_calib = { + /* write leveling calibration determine */ + .p0_mpwldectrl0 = 0x00190017, + /* Read DQS Gating calibration */ + .p0_mpdgctrl0 = 0x43380347, + /* Read Calibration: DQS delay relative to DQ read access */ + .p0_mprddlctl = 0x3C313539, + /* Write Calibration: DQ/DM delay relative to DQS write access */ + .p0_mpwrdlctl = 0x36393C39, +}; + +static struct mx6_mmdc_calibration mx6sdl_128x16_mmdc_calib = { + /* write leveling calibration determine */ + .p0_mpwldectrl0 = 0x00190017, + /* Read DQS Gating calibration */ + .p0_mpdgctrl0 = 0x43380347, + /* Read Calibration: DQS delay relative to DQ read access */ + .p0_mprddlctl = 0x3C313539, + /* Write Calibration: DQ/DM delay relative to DQS write access */ + .p0_mpwrdlctl = 0x36393C39, +}; + +static struct mx6_mmdc_calibration mx6sdl_256x16_mmdc_calib = { + /* write leveling calibration determine */ + .p0_mpwldectrl0 = 0x00190017, + /* Read DQS Gating calibration */ + .p0_mpdgctrl0 = 0x43380347, + /* Read Calibration: DQS delay relative to DQ read access */ + .p0_mprddlctl = 0x3C313539, + /* Write Calibration: DQ/DM delay relative to DQS write access */ + .p0_mpwrdlctl = 0x36393C39, +}; + static struct mx6_mmdc_calibration mx6dq_128x32_mmdc_calib = { /* write leveling calibration determine */ .p0_mpwldectrl0 = 0x00190017, @@ -363,7 +407,21 @@ static void spl_dram_init(int width, int size_mb, int board_model) * mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc) * mx6_ddr_cfg - chip specific timing/layout details */ - if (width == 32 && size_mb == 512) { + if (width == 16 && size_mb == 256) { + mem = &mt41k128m16jt_125; + if (is_cpu_type(MXC_CPU_MX6Q)) + calib = &mx6dq_128x16_mmdc_calib; + else + calib = &mx6sdl_128x16_mmdc_calib; + debug("2gB density\n"); + } else if (width == 16 && size_mb == 512) { + mem = &mt41k256m16ha_125; + if (is_cpu_type(MXC_CPU_MX6Q)) + calib = &mx6dq_256x16_mmdc_calib; + else + calib = &mx6sdl_256x16_mmdc_calib; + debug("4gB density\n"); + } else if (width == 32 && size_mb == 512) { mem = &mt41k128m16jt_125; if (is_cpu_type(MXC_CPU_MX6Q)) calib = &mx6dq_128x32_mmdc_calib; |