diff options
Diffstat (limited to 'board/freescale')
21 files changed, 629 insertions, 28 deletions
diff --git a/board/freescale/ls1021aiot/Kconfig b/board/freescale/ls1021aiot/Kconfig new file mode 100644 index 00000000000..4a12c1687fc --- /dev/null +++ b/board/freescale/ls1021aiot/Kconfig @@ -0,0 +1,15 @@ +if TARGET_LS1021AIOT + +config SYS_BOARD + default "ls1021aiot" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "ls102xa" + +config SYS_CONFIG_NAME + default "ls1021aiot" + +endif diff --git a/board/freescale/ls1021aiot/MAINTAINERS b/board/freescale/ls1021aiot/MAINTAINERS new file mode 100644 index 00000000000..2dab7988eeb --- /dev/null +++ b/board/freescale/ls1021aiot/MAINTAINERS @@ -0,0 +1,7 @@ +LS1021AIOT BOARD +M: Feng Li <feng.li_2@nxp.com> +S: Maintained +F: board/freescale/ls1021aiot/ +F: include/configs/ls1021aiot.h +F: configs/ls1021aiot_sdcard_defconfig +F: configs/ls1021aiot_qspi_defconfig diff --git a/board/freescale/ls1021aiot/Makefile b/board/freescale/ls1021aiot/Makefile new file mode 100644 index 00000000000..05709e685cc --- /dev/null +++ b/board/freescale/ls1021aiot/Makefile @@ -0,0 +1,9 @@ +# +# Copyright 2016 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += ls1021aiot.o +obj-$(CONFIG_FSL_DCU_FB) += dcu.o +obj-$(CONFIG_ARMV7_PSCI) += psci.o diff --git a/board/freescale/ls1021aiot/README b/board/freescale/ls1021aiot/README new file mode 100644 index 00000000000..08b0268b9bd --- /dev/null +++ b/board/freescale/ls1021aiot/README @@ -0,0 +1,58 @@ +Overview +-------- +The LS1021A-IOT is a Freescale reference board that hosts +the LS1021A SoC. + +LS1021AIOT board Overview +------------------------- + - DDR Controller + - Supports 1GB un-buffered DDR3L SDRAM discrete + devices(32-bit bus) with 4 bit ECC + - DDR power supplies 1.35V to all devices with + automatic tracking of VTT + - Soldered DDR chip + - Supprot one fixed speed + - Ethernet + - Two on-board SGMII 10/100/1G ethernet ports + - One Gbit Etherent RGMII interface to 4-ports switch + with 4x 10/100/1000 RJ145 ports + - CPLD + - 8-bit registers in CPLD for system configuration + - connected to IFC_AD[0:7] + - Power Supplies + - 12V@5A DC + - SDHC + - SDHC port connects directly to a full 8-bit SD/MMC slot + - Support for SDIO devices + - USB + - Two on-board USB 3.0 + - One on-board USB k22 + - PCIe + - Two MiniPCIe Solts + - SATA + - Support SATA Connector + - AUDIO + - AUDIO in and out + - I/O Expansion + - Arduino Shield Connector + - Port0 - CAN/GPIO/Flextimer + - Port1 - GPIO/CPLD Expansion + - Port2 - SPI/I2C/UART + +Memory map +----------- +The addresses in brackets are physical addresses. + +Start Address End Address Description Size +0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB +0x00_4000_0000 0x00_43FF_FFFF QSPI(Chip select 0) 64MB +0x00_4400_0000 0x00_47FF_FFFF QSPI(Chip select 1) 64MB +0x00_6000_0000 0x00_6000_FFFF CPLD 64K +0x00_8000_0000 0x00_BFFF_FFFF DDR 1GB + +Boot description +----------------- +LS1021A-IOT support two ways of boot: +Qspi boot and SD boot +The board doesn't support boot from another +source without changing any switch/jumper. diff --git a/board/freescale/ls1021aiot/dcu.c b/board/freescale/ls1021aiot/dcu.c new file mode 100644 index 00000000000..e27647f6e65 --- /dev/null +++ b/board/freescale/ls1021aiot/dcu.c @@ -0,0 +1,47 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * FSL DCU Framebuffer driver + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <fsl_dcu_fb.h> +#include "div64.h" +#include "../common/dcu_sii9022a.h" + +DECLARE_GLOBAL_DATA_PTR; + +unsigned int dcu_set_pixel_clock(unsigned int pixclock) +{ + unsigned long long div; + + div = (unsigned long long)(gd->bus_clk / 1000); + div *= (unsigned long long)pixclock; + do_div(div, 1000000000); + + return div; +} + +int platform_dcu_init(unsigned int xres, unsigned int yres, + const char *port, + struct fb_videomode *dcu_fb_videomode) +{ + const char *name; + unsigned int pixel_format; + + if (strncmp(port, "twr_lcd", 4) == 0) { + name = "TWR_LCD_RGB card"; + } else { + name = "HDMI"; + dcu_set_dvi_encoder(dcu_fb_videomode); + } + + printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres); + + pixel_format = 32; + fsl_dcu_init(xres, yres, pixel_format); + + return 0; +} diff --git a/board/freescale/ls1021aiot/ls1021aiot.c b/board/freescale/ls1021aiot/ls1021aiot.c new file mode 100644 index 00000000000..3340e4db80b --- /dev/null +++ b/board/freescale/ls1021aiot/ls1021aiot.c @@ -0,0 +1,259 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/immap_ls102xa.h> +#include <asm/arch/clock.h> +#include <asm/arch/fsl_serdes.h> +#include <asm/arch/ls102xa_stream_id.h> + +#include <asm/arch/ls102xa_devdis.h> +#include <asm/arch/ls102xa_soc.h> +#include <asm/arch/ls102xa_sata.h> +#include <fsl_csu.h> +#include <fsl_esdhc.h> +#include <fsl_immap.h> +#include <netdev.h> +#include <fsl_mdio.h> +#include <tsec.h> +#include <spl.h> + +#include <fsl_validate.h> +#include "../common/sleep.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define DDR_SIZE 0x40000000 + + +int checkboard(void) +{ + puts("Board: LS1021AIOT\n"); + +#ifndef CONFIG_QSPI_BOOT + struct ccsr_gur *dcfg = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR; + u32 cpldrev; + + cpldrev = in_be32(&dcfg->gpporcr1); + + printf("CPLD: V%d.%d\n", ((cpldrev >> 28) & 0xf), ((cpldrev >> 24) & + 0xf)); +#endif + return 0; +} + +void ddrmc_init(void) +{ + struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR; + u32 temp_sdram_cfg, tmp; + + out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG); + + out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS); + out_be32(&ddr->cs0_config, DDR_CS0_CONFIG); + + out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0); + out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1); + out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2); + out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3); + out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4); + out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5); + + out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2); + out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2); + + out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE); + out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2); + + out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL); + + out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL); + + out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2); + out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3); + + out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1); + + out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL); + out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL); + + out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2); + + /* DDR erratum A-009942 */ + tmp = in_be32(&ddr->debug[28]); + out_be32(&ddr->debug[28], tmp | 0x0070006f); + + udelay(500); + + temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI); + + out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg); +} + +int dram_init(void) +{ +#if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) + ddrmc_init(); +#endif + + gd->ram_size = DDR_SIZE; + return 0; +} + +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg esdhc_cfg[1] = { + {CONFIG_SYS_FSL_ESDHC_ADDR}, +}; + +int board_mmc_init(bd_t *bis) +{ + esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + + return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); +} + +#endif + +#ifdef CONFIG_TSEC_ENET +int board_eth_init(bd_t *bis) +{ + struct fsl_pq_mdio_info mdio_info; + struct tsec_info_struct tsec_info[4]; + int num = 0; + +#ifdef CONFIG_TSEC1 + SET_STD_TSEC_INFO(tsec_info[num], 1); + if (is_serdes_configured(SGMII_TSEC1)) { + puts("eTSEC1 is in sgmii mode.\n"); + tsec_info[num].flags |= TSEC_SGMII; + } + num++; +#endif +#ifdef CONFIG_TSEC2 + SET_STD_TSEC_INFO(tsec_info[num], 2); + if (is_serdes_configured(SGMII_TSEC2)) { + puts("eTSEC2 is in sgmii mode.\n"); + tsec_info[num].flags |= TSEC_SGMII; + } + num++; +#endif + if (!num) { + printf("No TSECs initialized\n"); + return 0; + } + + mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; + mdio_info.name = DEFAULT_MII_NAME; + fsl_pq_mdio_init(bis, &mdio_info); + + tsec_eth_init(bis, tsec_info, num); + + return pci_eth_init(bis); +} +#endif + +int board_early_init_f(void) +{ + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + +#ifdef CONFIG_TSEC_ENET + /* clear BD & FR bits for BE BD's and frame data */ + clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); + out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); + +#endif + + arch_soc_init(); + + return 0; +} + +#ifdef CONFIG_SPL_BUILD +void board_init_f(ulong dummy) +{ + /* Clear the BSS */ + memset(__bss_start, 0, __bss_end - __bss_start); + + get_clocks(); + + preloader_console_init(); + + dram_init(); + + /* Allow OCRAM access permission as R/W */ + +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); +#endif + + board_init_r(NULL, 0); +} +#endif + +int board_init(void) +{ +#ifndef CONFIG_SYS_FSL_NO_SERDES + fsl_serdes_init(); +#endif + + ls102xa_smmu_stream_id_init(); + +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); +#endif + + return 0; +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_SCSI_AHCI_PLAT + ls1021a_sata_init(); +#endif + + return 0; +} +#endif + +#if defined(CONFIG_MISC_INIT_R) +int misc_init_r(void) +{ +#ifdef CONFIG_FSL_DEVICE_DISABLE + device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl)); + +#endif + +#ifdef CONFIG_FSL_CAAM + return sec_init(); +#endif +} +#endif + +int ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); + +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif + + return 0; +} + +void flash_write16(u16 val, void *addr) +{ + u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); + + __raw_writew(shftval, addr); +} + +u16 flash_read16(void *addr) +{ + u16 val = __raw_readw(addr); + + return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); +} diff --git a/board/freescale/ls1021aiot/ls102xa_pbi.cfg b/board/freescale/ls1021aiot/ls102xa_pbi.cfg new file mode 100644 index 00000000000..b5ac5e27e9d --- /dev/null +++ b/board/freescale/ls1021aiot/ls102xa_pbi.cfg @@ -0,0 +1,14 @@ +#PBI commands + +09570200 ffffffff +09570158 00000300 +8940007c 21f47300 + +#Configure Scratch register +09ee0200 10000000 +#Configure alternate space +09570158 00001000 +#Flush PBL data +096100c0 000FFFFF + +09ea085c 00502880 diff --git a/board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg b/board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg new file mode 100644 index 00000000000..a1984c713d5 --- /dev/null +++ b/board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg @@ -0,0 +1,27 @@ +#PBL preamble and RCW header +aa55aa55 01ee0100 +# serdes protocol + +#Default with 2 x SGMII (no SATA) +0608000a 00000000 00000000 00000000 +20000000 08407900 60025a00 21046000 +00000000 00000000 00000000 20038000 +20024800 881b1340 00000000 00000000 + +#SATA set-up +#0608000a 00000000 00000000 00000000 +#70000000 08007900 60025a00 21046000 +#00000000 00000000 00000000 20038000 +#20024800 881b1340 00000000 00000000 + +#HDMI set-up +#0608000a 00000000 00000000 00000000 +#20000000 08407900 60025a00 21046000 +#00000000 00000000 00000000 20038000 +#00000000 881b1340 00000000 00000000 + +#QE testing +#0608000a 00000000 00000000 00000000 +#20000000 08407900 60025a00 21046000 +#00000000 00000000 00000000 00038000 +#20094800 881b1340 00000000 00000000 diff --git a/board/freescale/ls1021aiot/psci.S b/board/freescale/ls1021aiot/psci.S new file mode 100644 index 00000000000..564145c42a9 --- /dev/null +++ b/board/freescale/ls1021aiot/psci.S @@ -0,0 +1,28 @@ +/* + * Copyright 2016 NXP Semiconductor. + * Author: Feng Li <feng.li_2@nxp.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <linux/linkage.h> + +#include <asm/armv7.h> +#include <asm/psci.h> + + .pushsection ._secure.text, "ax" + + .arch_extension sec + + .align 5 + +.globl psci_system_off +psci_system_off: +1: wfi + b 1b + +.globl psci_text_end +psci_text_end: + nop + .popsection diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg b/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg index 222c71dcb61..d76e9132e35 100644 --- a/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg +++ b/board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg @@ -1,7 +1,7 @@ #PBL preamble and RCW header aa55aa55 01ee0100 # serdes protocol -0608000a 00000000 00000000 00000000 +0608000c 00000000 00000000 00000000 60000000 00407900 e0106a00 21046000 00000000 00000000 00000000 00038000 00000000 001b7200 00000000 00000000 diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg b/board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg index 9d99bd862dd..f0cf9c2b38d 100644 --- a/board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg +++ b/board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg @@ -2,13 +2,13 @@ aa55aa55 01ee0100 #enable IFC, disable QSPI and DSPI -0608000a 00000000 00000000 00000000 +0608000c 00000000 00000000 00000000 60000000 00407900 60040a00 21046000 00000000 00000000 00000000 00038000 00000000 001b7200 00000000 00000000 #disable IFC, enable QSPI and DSPI -#0608000a 00000000 00000000 00000000 +#0608000c 00000000 00000000 00000000 #60000000 00407900 60040a00 21046000 #00000000 00000000 00000000 00038000 #20024800 001b7200 00000000 00000000 diff --git a/board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg b/board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg index 2bd398cc539..10cc4a9ab0b 100644 --- a/board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg +++ b/board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg @@ -2,13 +2,13 @@ aa55aa55 01ee0100 #enable IFC, disable QSPI and DSPI -#0608000a 00000000 00000000 00000000 +#0608000c 00000000 00000000 00000000 #60000000 00407900 60040a00 21046000 #00000000 00000000 00000000 00038000 #00000000 001b7200 00000000 00000000 #disable IFC, enable QSPI and DSPI -0608000a 00000000 00000000 00000000 +0608000c 00000000 00000000 00000000 60000000 00407900 60040a00 21046000 00000000 00000000 00000000 00038000 20024800 001b7200 00000000 00000000 diff --git a/board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg b/board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg index 205606f4d2f..f94997d5384 100644 --- a/board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg +++ b/board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg @@ -2,7 +2,7 @@ aa55aa55 01ee0100 #enable IFC, disable QSPI and DSPI -0608000a 00000000 00000000 00000000 +0608000c 00000000 00000000 00000000 30000000 00007900 60040a00 21046000 00000000 00000000 00000000 20000000 00080000 881b7340 00000000 00000000 diff --git a/board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg b/board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg index 6767e093880..541b604cffc 100644 --- a/board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg +++ b/board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg @@ -2,7 +2,7 @@ aa55aa55 01ee0100 #disable IFC, enable QSPI and DSPI -0608000a 00000000 00000000 00000000 +0608000c 00000000 00000000 00000000 30000000 00007900 60040a00 21046000 00000000 00000000 00000000 20000000 20024800 881b7340 00000000 00000000 diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c index 8c185385030..552365b9d88 100644 --- a/board/freescale/ls1046aqds/ls1046aqds.c +++ b/board/freescale/ls1046aqds/ls1046aqds.c @@ -120,6 +120,13 @@ unsigned long get_board_ddr_clk(void) return 66666666; } +#ifdef CONFIG_LPUART +u32 get_lpuart_clk(void) +{ + return gd->bus_clk; +} +#endif + int select_i2c_ch_pca9547(u8 ch) { int ret; @@ -157,6 +164,9 @@ int board_early_init_f(void) struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; u32 usb_pwrfault; #endif +#ifdef CONFIG_LPUART + u8 uart; +#endif #ifdef CONFIG_SYS_I2C_EARLY_INIT i2c_early_init_f(); @@ -175,6 +185,14 @@ int board_early_init_f(void) out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault); #endif +#ifdef CONFIG_LPUART + /* We use lpuart0 as system console */ + uart = QIXIS_READ(brdcfg[14]); + uart &= ~CFG_UART_MUX_MASK; + uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT; + QIXIS_WRITE(brdcfg[14], uart); +#endif + return 0; } diff --git a/board/freescale/ls2080a/MAINTAINERS b/board/freescale/ls2080a/MAINTAINERS index c8dac99889a..de137ef64f4 100644 --- a/board/freescale/ls2080a/MAINTAINERS +++ b/board/freescale/ls2080a/MAINTAINERS @@ -1,5 +1,5 @@ LS2080A BOARD -M: York Sun <york.sun@nxp.com> +M: York Sun <york.sun@nxp.com>, Priyanka Jain <priyanka.jain@nxp.com> S: Maintained F: board/freescale/ls2080a/ F: include/configs/ls2080a_emu.h diff --git a/board/freescale/ls2080aqds/MAINTAINERS b/board/freescale/ls2080aqds/MAINTAINERS index 8f78b67baae..79877d77742 100644 --- a/board/freescale/ls2080aqds/MAINTAINERS +++ b/board/freescale/ls2080aqds/MAINTAINERS @@ -1,5 +1,5 @@ LS2080A BOARD -M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> +M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>, Priyanka Jain <priyanka.jain@nxp.com> S: Maintained F: board/freescale/ls2080aqds/ F: board/freescale/ls2080a/ls2080aqds.c diff --git a/board/freescale/ls2080aqds/README b/board/freescale/ls2080aqds/README index f2887509936..2808bd58519 100644 --- a/board/freescale/ls2080aqds/README +++ b/board/freescale/ls2080aqds/README @@ -2,14 +2,14 @@ Overview -------- The LS2080A Development System (QDS) is a high-performance computing, evaluation, and development platform that supports the QorIQ LS2080A -Layerscape Architecture processor. The LS2080AQDS provides validation and -SW development platform for the Freescale LS2080A processor series, with -a complete debugging environment. +and LS2088A Layerscape Architecture processor. The LS2080AQDS provides +validation and SW development platform for the Freescale LS2080A, LS2088A +processor series, with a complete debugging environment. -LS2080A SoC Overview +LS2080A, LS2088A SoC Overview -------------------- -Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A -SoC overview. +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A, +LS2088A SoC overview. LS2080AQDS board Overview ----------------------- diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c index 95ff68b3649..59361e9111f 100644 --- a/board/freescale/ls2080aqds/eth.c +++ b/board/freescale/ls2080aqds/eth.c @@ -64,7 +64,7 @@ static int sgmii_riser_phy_addr[] = { }; /* Slot2 does not have EMI connections */ -#define EMI_NONE 0xFFFFFFFF +#define EMI_NONE 0xFF #define EMI1_SLOT1 0 #define EMI1_SLOT2 1 #define EMI1_SLOT3 2 @@ -144,8 +144,10 @@ static void sgmii_configure_repeater(int serdes_port) mdelay(10); - if ((value & 0xfff) == 0x40f) { + if ((value & 0xfff) == 0x401) { printf("DPMAC %d:PHY is ..... Configured\n", dpmac_id); + miiphy_write(dev[mii_bus], riser_phy_addr[dpmac], + 0x1f, 0); continue; } @@ -181,28 +183,29 @@ static void sgmii_configure_repeater(int serdes_port) if (ret > 0) goto error; - mdelay(1); + mdelay(100); ret = miiphy_read(dev[mii_bus], riser_phy_addr[dpmac], 0x11, &value); if (ret > 0) goto error; - mdelay(10); - if ((value & 0xfff) == 0x40f) { + if ((value & 0xfff) == 0x401) { printf("DPMAC %d :PHY is configured ", dpmac_id); printf("after setting repeater 0x%x\n", value); i = 5; j = 5; - } else + } else { printf("DPMAC %d :PHY is failed to ", dpmac_id); printf("configure the repeater 0x%x\n", value); } + } } + miiphy_write(dev[mii_bus], riser_phy_addr[dpmac], 0x1f, 0); } error: if (ret) @@ -470,7 +473,49 @@ static void initialize_dpmac_to_slot(void) } break; + case 0x39: + printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n", + serdes1_prtcl); + if (hwconfig_f("xqsgmii", env_hwconfig)) { + lane_to_slot_fsm1[0] = EMI1_SLOT3; + lane_to_slot_fsm1[1] = EMI1_SLOT3; + lane_to_slot_fsm1[2] = EMI1_SLOT3; + lane_to_slot_fsm1[3] = EMI_NONE; + } else { + lane_to_slot_fsm1[0] = EMI_NONE; + lane_to_slot_fsm1[1] = EMI_NONE; + lane_to_slot_fsm1[2] = EMI_NONE; + lane_to_slot_fsm1[3] = EMI_NONE; + } + lane_to_slot_fsm1[4] = EMI1_SLOT3; + lane_to_slot_fsm1[5] = EMI1_SLOT3; + lane_to_slot_fsm1[6] = EMI1_SLOT3; + lane_to_slot_fsm1[7] = EMI_NONE; + break; + + case 0x4D: + printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n", + serdes1_prtcl); + if (hwconfig_f("xqsgmii", env_hwconfig)) { + lane_to_slot_fsm1[0] = EMI1_SLOT3; + lane_to_slot_fsm1[1] = EMI1_SLOT3; + lane_to_slot_fsm1[2] = EMI_NONE; + lane_to_slot_fsm1[3] = EMI_NONE; + } else { + lane_to_slot_fsm1[0] = EMI_NONE; + lane_to_slot_fsm1[1] = EMI_NONE; + lane_to_slot_fsm1[2] = EMI_NONE; + lane_to_slot_fsm1[3] = EMI_NONE; + } + lane_to_slot_fsm1[4] = EMI1_SLOT3; + lane_to_slot_fsm1[5] = EMI1_SLOT3; + lane_to_slot_fsm1[6] = EMI_NONE; + lane_to_slot_fsm1[7] = EMI_NONE; + break; + case 0x2A: + case 0x4B: + case 0x4C: printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n", serdes1_prtcl); break; @@ -505,6 +550,38 @@ static void initialize_dpmac_to_slot(void) lane_to_slot_fsm2[7] = EMI1_SLOT6; } break; + + case 0x47: + printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n", + serdes2_prtcl); + lane_to_slot_fsm2[0] = EMI_NONE; + lane_to_slot_fsm2[1] = EMI1_SLOT5; + lane_to_slot_fsm2[2] = EMI1_SLOT5; + lane_to_slot_fsm2[3] = EMI1_SLOT5; + + if (hwconfig_f("xqsgmii", env_hwconfig)) { + lane_to_slot_fsm2[4] = EMI_NONE; + lane_to_slot_fsm2[5] = EMI1_SLOT5; + lane_to_slot_fsm2[6] = EMI1_SLOT5; + lane_to_slot_fsm2[7] = EMI1_SLOT5; + } + break; + + case 0x57: + printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n", + serdes2_prtcl); + if (hwconfig_f("xqsgmii", env_hwconfig)) { + lane_to_slot_fsm2[0] = EMI_NONE; + lane_to_slot_fsm2[1] = EMI_NONE; + lane_to_slot_fsm2[2] = EMI_NONE; + lane_to_slot_fsm2[3] = EMI_NONE; + } + lane_to_slot_fsm2[4] = EMI_NONE; + lane_to_slot_fsm2[5] = EMI_NONE; + lane_to_slot_fsm2[6] = EMI1_SLOT5; + lane_to_slot_fsm2[7] = EMI1_SLOT5; + break; + default: printf(" %s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n", __func__ , serdes2_prtcl); @@ -537,8 +614,10 @@ void ls2080a_handle_phy_interface_sgmii(int dpmac_id) switch (serdes1_prtcl) { case 0x07: + case 0x39: + case 0x4D: + lane = serdes_get_first_lane(FSL_SRDS_1, SGMII1 + dpmac_id - 1); - lane = serdes_get_first_lane(FSL_SRDS_1, SGMII1 + dpmac_id); slot = lane_to_slot_fsm1[lane]; switch (++slot) { @@ -559,6 +638,26 @@ void ls2080a_handle_phy_interface_sgmii(int dpmac_id) wriop_set_mdio(dpmac_id, bus); break; case 3: + if (slot == EMI_NONE) + return; + if (serdes1_prtcl == 0x39) { + wriop_set_phy_address(dpmac_id, + riser_phy_addr[dpmac_id - 2]); + if (dpmac_id >= 6 && hwconfig_f("xqsgmii", + env_hwconfig)) + wriop_set_phy_address(dpmac_id, + riser_phy_addr[dpmac_id - 3]); + } else { + wriop_set_phy_address(dpmac_id, + riser_phy_addr[dpmac_id - 2]); + if (dpmac_id >= 7 && hwconfig_f("xqsgmii", + env_hwconfig)) + wriop_set_phy_address(dpmac_id, + riser_phy_addr[dpmac_id - 3]); + } + dpmac_info[dpmac_id].board_mux = EMI1_SLOT3; + bus = mii_dev_for_muxval(EMI1_SLOT3); + wriop_set_mdio(dpmac_id, bus); break; case 4: break; @@ -579,6 +678,8 @@ serdes2: case 0x07: case 0x08: case 0x49: + case 0x47: + case 0x57: lane = serdes_get_first_lane(FSL_SRDS_2, SGMII9 + (dpmac_id - 9)); slot = lane_to_slot_fsm2[lane]; @@ -597,7 +698,23 @@ serdes2: wriop_set_mdio(dpmac_id, bus); break; case 5: - break; + if (slot == EMI_NONE) + return; + if (serdes2_prtcl == 0x47) { + wriop_set_phy_address(dpmac_id, + riser_phy_addr[dpmac_id - 10]); + if (dpmac_id >= 14 && hwconfig_f("xqsgmii", + env_hwconfig)) + wriop_set_phy_address(dpmac_id, + riser_phy_addr[dpmac_id - 11]); + } else { + wriop_set_phy_address(dpmac_id, + riser_phy_addr[dpmac_id - 11]); + } + dpmac_info[dpmac_id].board_mux = EMI1_SLOT5; + bus = mii_dev_for_muxval(EMI1_SLOT5); + wriop_set_mdio(dpmac_id, bus); + break; case 6: /* Slot housing a SGMII riser card? */ wriop_set_phy_address(dpmac_id, @@ -691,6 +808,8 @@ void ls2080a_handle_phy_interface_xsgmii(int i) switch (serdes1_prtcl) { case 0x2A: + case 0x4B: + case 0x4C: /* * XFI does not need a PHY to work, but to avoid U-Boot use * default PHY address which is zero to a MAC when it found diff --git a/board/freescale/ls2080ardb/MAINTAINERS b/board/freescale/ls2080ardb/MAINTAINERS index a20c003ce75..759a14605c6 100644 --- a/board/freescale/ls2080ardb/MAINTAINERS +++ b/board/freescale/ls2080ardb/MAINTAINERS @@ -1,5 +1,5 @@ LS2080A BOARD -M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> +M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>, Priyanka Jain <priyanka.jain@nxp.com> S: Maintained F: board/freescale/ls2080ardb/ F: board/freescale/ls2080a/ls2080ardb.c diff --git a/board/freescale/ls2080ardb/README b/board/freescale/ls2080ardb/README index b1613ba6800..0c9c574f338 100644 --- a/board/freescale/ls2080ardb/README +++ b/board/freescale/ls2080ardb/README @@ -1,13 +1,13 @@ Overview -------- The LS2080A Reference Design (RDB) is a high-performance computing, -evaluation, and development platform that supports the QorIQ LS2080A +evaluation, and development platform that supports the QorIQ LS2080A, LS2088A Layerscape Architecture processor. -LS2080A SoC Overview +LS2080A, LS2088A SoC Overview -------------------- -Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A -SoC overview. +Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A, +LS2088A SoC overview. LS2080ARDB board Overview ----------------------- |