diff options
Diffstat (limited to 'board/freescale')
| -rw-r--r-- | board/freescale/mx6qarm2/imximage.cfg | 182 | ||||
| -rw-r--r-- | board/freescale/mx6qarm2/imximage_mx6dl.cfg | 15 | ||||
| -rw-r--r-- | board/freescale/mx6qarm2/mx6qarm2.c | 88 |
3 files changed, 279 insertions, 6 deletions
diff --git a/board/freescale/mx6qarm2/imximage.cfg b/board/freescale/mx6qarm2/imximage.cfg index c85bde510e..fbc28ba392 100644 --- a/board/freescale/mx6qarm2/imximage.cfg +++ b/board/freescale/mx6qarm2/imximage.cfg @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011-2014 Freescale Semiconductor, Inc. + * Copyright (C) 2011-2015 Freescale Semiconductor, Inc. * Jason Liu <r64343@freescale.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -10,6 +10,9 @@ * The syntax is taken as close as possible with the kwbimage */ +#define __ASSEMBLY__ +#include <config.h> + /* image version */ IMAGE_VERSION 2 @@ -19,6 +22,15 @@ IMAGE_VERSION 2 */ BOOT_FROM sd +#ifdef CONFIG_USE_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6qarm2/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF 0x2000 +#endif + /* * Device Configuration Data (DCD) * @@ -30,7 +42,172 @@ BOOT_FROM sd * Address absolute address of the register * value value to be stored in the register */ -#ifdef CONFIG_MX6DQ_LPDDR2 +#ifdef CONFIG_MX6DQ_POP_LPDDR2 + +DATA 4 0x020c4068 0xffffffff +DATA 4 0x020c406c 0xffffffff +DATA 4 0x020c4070 0xffffffff +DATA 4 0x020c4074 0xffffffff +DATA 4 0x020c4078 0xffffffff +DATA 4 0x020c407c 0xffffffff +DATA 4 0x020c4080 0xffffffff +DATA 4 0x020c4084 0xffffffff + +/* DCD */ +DATA 4 0x020e0798 0x00080000 +DATA 4 0x020e0758 0x00000000 + +DATA 4 0x020e0588 0x00000030 +DATA 4 0x020e0594 0x00000030 + +DATA 4 0x020e056c 0x00000030 +DATA 4 0x020e0578 0x00000030 +DATA 4 0x020e074c 0x00000030 + +DATA 4 0x020e057c 0x00000030 +DATA 4 0x020e058c 0x00000000 +DATA 4 0x020e059c 0x00000030 +DATA 4 0x020e05a0 0x00000030 +DATA 4 0x020e078c 0x00000030 + +DATA 4 0x020e0750 0x00020000 +DATA 4 0x020e05a8 0x00003030 +DATA 4 0x020e05b0 0x00003030 +DATA 4 0x020e0524 0x00003030 +DATA 4 0x020e051c 0x00003030 +DATA 4 0x020e0518 0x00003030 +DATA 4 0x020e050c 0x00003030 +DATA 4 0x020e05b8 0x00003030 +DATA 4 0x020e05c0 0x00003030 + +DATA 4 0x020e0774 0x00020000 +DATA 4 0x020e0784 0x00000030 +DATA 4 0x020e0788 0x00000030 +DATA 4 0x020e0794 0x00000030 +DATA 4 0x020e079c 0x00000030 +DATA 4 0x020e07a0 0x00000030 +DATA 4 0x020e07a4 0x00000030 +DATA 4 0x020e07a8 0x00000030 +DATA 4 0x020e0748 0x00000030 + +DATA 4 0x020e05ac 0x00000030 +DATA 4 0x020e05b4 0x00000030 +DATA 4 0x020e0528 0x00000030 +DATA 4 0x020e0520 0x00000030 +DATA 4 0x020e0514 0x00000030 +DATA 4 0x020e0510 0x00000030 +DATA 4 0x020e05bc 0x00000030 +DATA 4 0x020e05c4 0x00000030 + +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b401c 0x00008000 + +DATA 4 0x021b085c 0x1B5F0107 +DATA 4 0x021b485c 0x1B5F0107 + +DATA 4 0x021b0800 0xA1390003 + +DATA 4 0x021b0890 0x00400000 +DATA 4 0x021b4890 0x00400000 + +DATA 4 0x021b0848 0x3C3A3A44 +DATA 4 0x021b4848 0x3C3A3A44 + +DATA 4 0x021b0850 0x4238423A +DATA 4 0x021b4850 0x4238423A + +DATA 4 0x021b083c 0x20000000 +DATA 4 0x021b0840 0x00000000 +DATA 4 0x021b483c 0x20000000 +DATA 4 0x021b4840 0x00000000 + +DATA 4 0x021b081c 0x33333333 +DATA 4 0x021b0820 0x33333333 +DATA 4 0x021b0824 0x33333333 +DATA 4 0x021b0828 0x33333333 +DATA 4 0x021b481c 0x33333333 +DATA 4 0x021b4820 0x33333333 +DATA 4 0x021b4824 0x33333333 +DATA 4 0x021b4828 0x33333333 + +DATA 4 0x021b082c 0xf3333333 +DATA 4 0x021b0830 0xf3333333 +DATA 4 0x021b0834 0xf3333333 +DATA 4 0x021b0838 0xf3333333 +DATA 4 0x021b482c 0xf3333333 +DATA 4 0x021b4830 0xf3333333 +DATA 4 0x021b4834 0xf3333333 +DATA 4 0x021b4838 0xf3333333 + +DATA 4 0x021b08b8 0x00000800 +DATA 4 0x021b48b8 0x00000800 + +DATA 4 0x021b0004 0x00020036 +DATA 4 0x021b0008 0x00000000 +DATA 4 0x021b000c 0x444961A5 +DATA 4 0x021b0010 0x00160E83 +DATA 4 0x021b0014 0x000000DD + +DATA 4 0x021b0018 0x0000174C +DATA 4 0x021b001c 0x00008000 +DATA 4 0x021b002c 0x149F26D2 +DATA 4 0x021b0030 0x00000010 +DATA 4 0x021b0038 0x0021099B +DATA 4 0x021b0040 0x0000004F +DATA 4 0x021b0400 0x11420000 +DATA 4 0x021b0000 0x83110000 + +DATA 4 0x021b4004 0x00020036 +DATA 4 0x021b4008 0x00000000 +DATA 4 0x021b400c 0x444961A5 +DATA 4 0x021b4010 0x00160E83 +DATA 4 0x021b4014 0x000000DD + +DATA 4 0x021b4018 0x0000174C +DATA 4 0x021b401c 0x00008000 +DATA 4 0x021b402c 0x149F26D2 +DATA 4 0x021b4030 0x00000010 +DATA 4 0x021b4038 0x0021099B +DATA 4 0x021b4040 0x00000017 +DATA 4 0x021b4400 0x11420000 +DATA 4 0x021b4000 0x83110000 + +DATA 4 0x021b001c 0x003F8030 +DATA 4 0x021b001c 0xFF0A8030 +DATA 4 0x021b001c 0xC2018030 +DATA 4 0x021b001c 0x06028030 +DATA 4 0x021b001c 0x02038030 + +DATA 4 0x021b401c 0x003F8030 +DATA 4 0x021b401c 0xFF0A8030 +DATA 4 0x021b401c 0xC2018030 +DATA 4 0x021b401c 0x06028030 +DATA 4 0x021b401c 0x02038030 + +DATA 4 0x021b0800 0xA1390003 + +DATA 4 0x021b0020 0x00001800 +DATA 4 0x021b4020 0x00001800 + +DATA 4 0x021b0818 0x00000000 +DATA 4 0x021b4818 0x00000000 + +DATA 4 0x021b0004 0x00025576 +DATA 4 0x021b4004 0x00025576 + +DATA 4 0x021b0404 0x00011006 +DATA 4 0x021b4404 0x00011006 + +DATA 4 0x021b001c 0x00000000 +DATA 4 0x021b401c 0x00000000 + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4, 0x020e0010, 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4, 0x020e0018, 0x007F007F +DATA 4, 0x020e001c, 0x007F007F + +#elif defined(CONFIG_MX6DQ_LPDDR2) /* DCD */ DATA 4 0x020C4018 0x60324 @@ -336,3 +513,4 @@ DATA 4 0x020e0018 0x007F007F DATA 4 0x020e001c 0x007F007F #endif /* CONFIG_MX6DQ_LPDDR2 */ +#endif diff --git a/board/freescale/mx6qarm2/imximage_mx6dl.cfg b/board/freescale/mx6qarm2/imximage_mx6dl.cfg index ae8dcc626e..8d1b8bd3aa 100644 --- a/board/freescale/mx6qarm2/imximage_mx6dl.cfg +++ b/board/freescale/mx6qarm2/imximage_mx6dl.cfg @@ -1,5 +1,5 @@ /* - * Copyright (C) 2014 Freescale Semiconductor, Inc. + * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. * Jason Liu <r64343@freescale.com> * * SPDX-License-Identifier: GPL-2.0+ @@ -10,6 +10,9 @@ * The syntax is taken as close as possible with the kwbimage */ +#define __ASSEMBLY__ +#include <config.h> + /* image version */ IMAGE_VERSION 2 @@ -19,6 +22,15 @@ IMAGE_VERSION 2 */ BOOT_FROM sd +#ifdef CONFIG_USE_PLUGIN +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ +PLUGIN board/freescale/mx6qarm2/plugin.bin 0x00907000 +#else + +#ifdef CONFIG_SECURE_BOOT +CSF 0x2000 +#endif + /* * Device Configuration Data (DCD) * @@ -460,3 +472,4 @@ DATA 4 0x020e0010 0xF00000CF DATA 4 0x020e0018 0x007F007F DATA 4 0x020e001c 0x007F007F #endif /* CONFIG_MX6DL_LPDDR2 */ +#endif diff --git a/board/freescale/mx6qarm2/mx6qarm2.c b/board/freescale/mx6qarm2/mx6qarm2.c index 98ccdb785b..2f03f9229a 100644 --- a/board/freescale/mx6qarm2/mx6qarm2.c +++ b/board/freescale/mx6qarm2/mx6qarm2.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. + * Copyright (C) 2010-2015 Freescale Semiconductor, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -59,7 +59,11 @@ iomux_v3_cfg_t const usdhc3_pads[] = { MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +#ifdef CONFIG_MX6DQ_POP_LPDDR2 + MX6_PAD_GPIO_18__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), +#else MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +#endif }; iomux_v3_cfg_t const usdhc4_pads[] = { @@ -110,17 +114,46 @@ struct fsl_esdhc_cfg usdhc_cfg[2] = { {USDHC4_BASE_ADDR}, }; +int mmc_get_env_devno(void) +{ + u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4); + u32 dev_no; + u32 bootsel; + + bootsel = (soc_sbmr & 0x000000FF) >> 6 ; + + /* If not boot from sd/mmc, use default value */ + if (bootsel != 1) + return CONFIG_SYS_MMC_ENV_DEV; + + /* BOOT_CFG2[3] and BOOT_CFG2[4] */ + dev_no = (soc_sbmr & 0x00001800) >> 11; + + /* need ubstract 1 to map to the mmc device id + * see the comments in board_mmc_init function + */ + + dev_no -= 2; + + return dev_no; +} + +int mmc_map_to_kernel_blk(int dev_no) +{ + return dev_no + 2; +} int board_mmc_getcd(struct mmc *mmc) { + int ret = 1; +#ifndef CONFIG_MX6DQ_POP_LPDDR2 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - int ret; if (cfg->esdhc_base == USDHC3_BASE_ADDR) { gpio_direction_input(IMX_GPIO_NR(6, 11)); ret = !gpio_get_value(IMX_GPIO_NR(6, 11)); } else /* Don't have the CD GPIO pin on board */ ret = 1; - +#endif return ret; } @@ -156,6 +189,39 @@ int board_mmc_init(bd_t *bis) return 0; } + +int check_mmc_autodetect(void) +{ + char *autodetect_str = getenv("mmcautodetect"); + + if ((autodetect_str != NULL) && + (strcmp(autodetect_str, "yes") == 0)) { + return 1; + } + + return 0; +} + +void board_late_mmc_env_init(void) +{ + char cmd[32]; + char mmcblk[32]; + u32 dev_no = mmc_get_env_devno(); + + if (!check_mmc_autodetect()) + return; + + setenv_ulong("mmcdev", dev_no); + + /* Set mmcblk env */ + sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw", + mmc_map_to_kernel_blk(dev_no)); + setenv("mmcroot", mmcblk); + + sprintf(cmd, "mmc dev %d", dev_no); + run_command(cmd, 0); +} + #endif #define MII_MMD_ACCESS_CTRL_REG 0xd @@ -271,6 +337,15 @@ int board_init(void) return 0; } +int board_late_init(void) +{ +#ifdef CONFIG_ENV_IS_IN_MMC + board_late_mmc_env_init(); +#endif + + return 0; +} + int checkboard(void) { #ifdef CONFIG_MX6DL @@ -281,3 +356,10 @@ int checkboard(void) return 0; } +#ifdef CONFIG_LDO_BYPASS_CHECK +/* no external pmic, always ldo_enable */ +void ldo_mode_set(int ldo_bypass) +{ + return; +} +#endif |