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Diffstat (limited to 'board/freescale/vf610twr/vf610twr.c')
-rw-r--r--board/freescale/vf610twr/vf610twr.c141
1 files changed, 104 insertions, 37 deletions
diff --git a/board/freescale/vf610twr/vf610twr.c b/board/freescale/vf610twr/vf610twr.c
index 54a9f2c7c3..b634965ad2 100644
--- a/board/freescale/vf610twr/vf610twr.c
+++ b/board/freescale/vf610twr/vf610twr.c
@@ -45,6 +45,7 @@ void setup_iomux_ddr(void)
VF610_PAD_DDR_A3__DDR_A_3,
VF610_PAD_DDR_A2__DDR_A_2,
VF610_PAD_DDR_A1__DDR_A_1,
+ VF610_PAD_DDR_A0__DDR_A_0,
VF610_PAD_DDR_BA2__DDR_BA_2,
VF610_PAD_DDR_BA1__DDR_BA_1,
VF610_PAD_DDR_BA0__DDR_BA_0,
@@ -76,6 +77,7 @@ void setup_iomux_ddr(void)
VF610_PAD_DDR_WE__DDR_WE_B,
VF610_PAD_DDR_ODT1__DDR_ODT_0,
VF610_PAD_DDR_ODT0__DDR_ODT_1,
+ VF610_PAD_DDR_RESETB,
};
imx_iomux_v3_setup_multiple_pads(ddr_pads, ARRAY_SIZE(ddr_pads));
@@ -88,30 +90,30 @@ void ddr_phy_init(void)
writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[0]);
writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[16]);
writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[32]);
- writel(DDRMC_PHY_DQ_TIMING, &ddrmr->phy[48]);
writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[1]);
writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[17]);
- writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[33]);
- writel(DDRMC_PHY_DQS_TIMING, &ddrmr->phy[49]);
writel(DDRMC_PHY_CTRL, &ddrmr->phy[2]);
writel(DDRMC_PHY_CTRL, &ddrmr->phy[18]);
writel(DDRMC_PHY_CTRL, &ddrmr->phy[34]);
- writel(DDRMC_PHY_CTRL, &ddrmr->phy[50]);
writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[3]);
writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[19]);
writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[35]);
- writel(DDRMC_PHY_MASTER_CTRL, &ddrmr->phy[51]);
writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[4]);
writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[20]);
writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[36]);
- writel(DDRMC_PHY_SLAVE_CTRL, &ddrmr->phy[52]);
+
+ /* LPDDR2 only parameter */
+ writel(DDRMC_PHY_OFF, &ddrmr->phy[49]);
writel(DDRMC_PHY50_DDR3_MODE | DDRMC_PHY50_EN_SW_HALF_CYCLE,
&ddrmr->phy[50]);
+
+ /* Processor Pad ODT settings */
+ writel(DDRMC_PHY_PROC_PAD_ODT, &ddrmr->phy[52]);
}
void ddr_ctrl_init(void)
@@ -120,12 +122,12 @@ void ddr_ctrl_init(void)
writel(DDRMC_CR00_DRAM_CLASS_DDR3, &ddrmr->cr[0]);
writel(DDRMC_CR02_DRAM_TINIT(32), &ddrmr->cr[2]);
- writel(DDRMC_CR10_TRST_PWRON(124), &ddrmr->cr[10]);
+ writel(DDRMC_CR10_TRST_PWRON(80000), &ddrmr->cr[10]);
- writel(DDRMC_CR11_CKE_INACTIVE(80000), &ddrmr->cr[11]);
+ writel(DDRMC_CR11_CKE_INACTIVE(200000), &ddrmr->cr[11]);
writel(DDRMC_CR12_WRLAT(5) | DDRMC_CR12_CASLAT_LIN(12), &ddrmr->cr[12]);
- writel(DDRMC_CR13_TRC(21) | DDRMC_CR13_TRRD(4) | DDRMC_CR13_TCCD(4) |
- DDRMC_CR13_TBST_INT_INTERVAL(4), &ddrmr->cr[13]);
+ writel(DDRMC_CR13_TRC(21) | DDRMC_CR13_TRRD(4) | DDRMC_CR13_TCCD(4),
+ &ddrmr->cr[13]);
writel(DDRMC_CR14_TFAW(20) | DDRMC_CR14_TRP(6) | DDRMC_CR14_TWTR(4) |
DDRMC_CR14_TRAS_MIN(15), &ddrmr->cr[14]);
writel(DDRMC_CR16_TMRD(4) | DDRMC_CR16_TRTP(4), &ddrmr->cr[16]);
@@ -134,24 +136,23 @@ void ddr_ctrl_init(void)
writel(DDRMC_CR18_TCKESR(4) | DDRMC_CR18_TCKE(3), &ddrmr->cr[18]);
writel(DDRMC_CR20_AP_EN, &ddrmr->cr[20]);
- writel(DDRMC_CR21_TRCD_INT(6) | DDRMC_CR21_TRAS_LOCKOUT |
- DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]);
+ writel(DDRMC_CR21_TRCD_INT(6) | DDRMC_CR21_CCMAP_EN, &ddrmr->cr[21]);
- writel(DDRMC_CR22_TDAL(11), &ddrmr->cr[22]);
+ writel(DDRMC_CR22_TDAL(12), &ddrmr->cr[22]);
writel(DDRMC_CR23_BSTLEN(3) | DDRMC_CR23_TDLL(512), &ddrmr->cr[23]);
writel(DDRMC_CR24_TRP_AB(6), &ddrmr->cr[24]);
writel(DDRMC_CR25_TREF_EN, &ddrmr->cr[25]);
- writel(DDRMC_CR26_TREF(3112) | DDRMC_CR26_TRFC(44), &ddrmr->cr[26]);
- writel(DDRMC_CR28_TREF_INT(5), &ddrmr->cr[28]);
+ writel(DDRMC_CR26_TREF(3120) | DDRMC_CR26_TRFC(44), &ddrmr->cr[26]);
+ writel(DDRMC_CR28_TREF_INT(0), &ddrmr->cr[28]);
writel(DDRMC_CR29_TPDEX(3), &ddrmr->cr[29]);
writel(DDRMC_CR30_TXPDLL(10), &ddrmr->cr[30]);
- writel(DDRMC_CR31_TXSNR(68) | DDRMC_CR31_TXSR(512), &ddrmr->cr[31]);
+ writel(DDRMC_CR31_TXSNR(48) | DDRMC_CR31_TXSR(468), &ddrmr->cr[31]);
writel(DDRMC_CR33_EN_QK_SREF, &ddrmr->cr[33]);
writel(DDRMC_CR34_CKSRX(5) | DDRMC_CR34_CKSRE(5), &ddrmr->cr[34]);
- writel(DDRMC_CR38_FREQ_CHG_EN, &ddrmr->cr[38]);
+ writel(DDRMC_CR38_FREQ_CHG_EN(0), &ddrmr->cr[38]);
writel(DDRMC_CR39_PHY_INI_COM(1024) | DDRMC_CR39_PHY_INI_STA(16) |
DDRMC_CR39_FRQ_CH_DLLOFF(2), &ddrmr->cr[39]);
@@ -164,37 +165,45 @@ void ddr_ctrl_init(void)
writel(DDRMC_CR69_ZQ_ON_SREF_EX(2), &ddrmr->cr[69]);
writel(DDRMC_CR70_REF_PER_ZQ(64), &ddrmr->cr[70]);
- writel(DDRMC_CR72_ZQCS_ROTATE, &ddrmr->cr[72]);
+ writel(DDRMC_CR72_ZQCS_ROTATE(0), &ddrmr->cr[72]);
writel(DDRMC_CR73_APREBIT(10) | DDRMC_CR73_COL_DIFF(1) |
DDRMC_CR73_ROW_DIFF(3), &ddrmr->cr[73]);
writel(DDRMC_CR74_BANKSPLT_EN | DDRMC_CR74_ADDR_CMP_EN |
- DDRMC_CR74_CMD_AGE_CNT(255) | DDRMC_CR74_AGE_CNT(255),
+ DDRMC_CR74_CMD_AGE_CNT(64) | DDRMC_CR74_AGE_CNT(64),
&ddrmr->cr[74]);
writel(DDRMC_CR75_RW_PG_EN | DDRMC_CR75_RW_EN | DDRMC_CR75_PRI_EN |
DDRMC_CR75_PLEN, &ddrmr->cr[75]);
writel(DDRMC_CR76_NQENT_ACTDIS(3) | DDRMC_CR76_D_RW_G_BKCN(3) |
- DDRMC_CR76_W2R_SPLT_EN | DDRMC_CR76_CS_EN, &ddrmr->cr[76]);
+ DDRMC_CR76_W2R_SPLT_EN, &ddrmr->cr[76]);
writel(DDRMC_CR77_CS_MAP | DDRMC_CR77_DI_RD_INTLEAVE |
DDRMC_CR77_SWAP_EN, &ddrmr->cr[77]);
- writel(DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]);
- writel(DDRMC_CR79_CTLUPD_AREF, &ddrmr->cr[79]);
+ writel(DDRMC_CR78_Q_FULLNESS(7) | DDRMC_CR78_BUR_ON_FLY_BIT(12),
+ &ddrmr->cr[78]);
+ writel(DDRMC_CR79_CTLUPD_AREF(0), &ddrmr->cr[79]);
writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]);
- writel(DDRMC_CR87_ODT_WR_MAPCS0 | DDRMC_CR87_ODT_RD_MAPCS0,
- &ddrmr->cr[87]);
+ writel(DDRMC_CR87_ODT_WR_MAPCS0, &ddrmr->cr[87]);
writel(DDRMC_CR88_TODTL_CMD(4), &ddrmr->cr[88]);
writel(DDRMC_CR89_AODT_RWSMCS(2), &ddrmr->cr[89]);
writel(DDRMC_CR91_R2W_SMCSDL(2), &ddrmr->cr[91]);
writel(DDRMC_CR96_WLMRD(40) | DDRMC_CR96_WLDQSEN(25), &ddrmr->cr[96]);
+ writel(DDRMC_CR97_WRLVL_EN, &ddrmr->cr[97]);
+ writel(DDRMC_CR98_WRLVL_DL_0, &ddrmr->cr[98]);
+ writel(DDRMC_CR99_WRLVL_DL_1, &ddrmr->cr[99]);
+
+ writel(DDRMC_CR102_RDLVL_GT_REGEN | DDRMC_CR102_RDLVL_REG_EN,
+ &ddrmr->cr[102]);
- writel(DDRMC_CR105_RDLVL_DL_0(32), &ddrmr->cr[105]);
- writel(DDRMC_CR110_RDLVL_DL_1(32), &ddrmr->cr[110]);
- writel(DDRMC_CR114_RDLVL_GTDL_2(8224), &ddrmr->cr[114]);
+ writel(DDRMC_CR105_RDLVL_DL_0(0), &ddrmr->cr[105]);
+ writel(DDRMC_CR106_RDLVL_GTDL_0(4), &ddrmr->cr[106]);
+ writel(DDRMC_CR110_RDLVL_GTDL_1(4), &ddrmr->cr[110]);
+ writel(DDRMC_CR114_RDLVL_GTDL_2(0), &ddrmr->cr[114]);
+ writel(DDRMC_CR115_RDLVL_GTDL_2(0), &ddrmr->cr[115]);
- writel(DDRMC_CR117_AXI0_W_PRI(1) | DDRMC_CR117_AXI0_R_PRI(1),
+ writel(DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0),
&ddrmr->cr[117]);
writel(DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1),
&ddrmr->cr[118]);
@@ -205,23 +214,40 @@ void ddr_ctrl_init(void)
&ddrmr->cr[121]);
writel(DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
DDRMC_CR122_AXI0_PRIRLX(100), &ddrmr->cr[122]);
- writel(DDRMC_CR123_AXI1_PRI3_RPRI(1) | DDRMC_CR123_AXI1_PRI2_RPRI(1),
- &ddrmr->cr[123]);
+ writel(DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
+ DDRMC_CR123_AXI1_PRI2_RPRI(1), &ddrmr->cr[123]);
writel(DDRMC_CR124_AXI1_PRIRLX(100), &ddrmr->cr[124]);
- writel(DDRMC_CR126_PHY_RDLAT(11), &ddrmr->cr[126]);
+ writel(DDRMC_CR126_PHY_RDLAT(8), &ddrmr->cr[126]);
writel(DDRMC_CR132_WRLAT_ADJ(5) | DDRMC_CR132_RDLAT_ADJ(6),
&ddrmr->cr[132]);
+ writel(DDRMC_CR137_PHYCTL_DL(2), &ddrmr->cr[137]);
+ writel(DDRMC_CR138_PHY_WRLV_MXDL(256) | DDRMC_CR138_PHYDRAM_CK_EN(1),
+ &ddrmr->cr[138]);
writel(DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
DDRMC_CR139_PHY_WRLV_DLL(3) | DDRMC_CR139_PHY_WRLV_EN(3),
&ddrmr->cr[139]);
+ writel(DDRMC_CR140_PHY_WRLV_WW(64), &ddrmr->cr[140]);
+ writel(DDRMC_CR143_RDLV_GAT_MXDL(1536) | DDRMC_CR143_RDLV_MXDL(128),
+ &ddrmr->cr[143]);
+ writel(DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) |
+ DDRMC_CR144_PHY_RDLV_DLL(3) | DDRMC_CR144_PHY_RDLV_EN(3),
+ &ddrmr->cr[144]);
+ writel(DDRMC_CR145_PHY_RDLV_RR(64), &ddrmr->cr[145]);
+ writel(DDRMC_CR146_PHY_RDLVL_RESP(64), &ddrmr->cr[146]);
+ writel(DDRMC_CR147_RDLV_RESP_MASK(983040), &ddrmr->cr[147]);
+ writel(DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), &ddrmr->cr[148]);
+ writel(DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) |
+ DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), &ddrmr->cr[151]);
writel(DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
- DDRMC_CR154_PAD_ZQ_MODE(1) |
- DDRMC_CR154_DDR_SEL_PAD_CONTR(3), &ddrmr->cr[154]);
- writel(DDRMC_CR155_AXI0_AWCACHE | DDRMC_CR155_PAD_ODT_BYTE1(2),
+ DDRMC_CR154_PAD_ZQ_MODE(1) | DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
+ DDRMC_CR154_PAD_ZQ_HW_FOR(1), &ddrmr->cr[154]);
+ writel(DDRMC_CR155_PAD_ODT_BYTE1(2) | DDRMC_CR155_PAD_ODT_BYTE0(2),
&ddrmr->cr[155]);
writel(DDRMC_CR158_TWR(6), &ddrmr->cr[158]);
+ writel(DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
+ DDRMC_CR161_TODTH_WR(2), &ddrmr->cr[161]);
ddr_phy_init();
@@ -278,6 +304,39 @@ static void setup_iomux_i2c(void)
imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads));
}
+#ifdef CONFIG_NAND_VF610_NFC
+static void setup_iomux_nfc(void)
+{
+ static const iomux_v3_cfg_t nfc_pads[] = {
+ VF610_PAD_PTD31__NF_IO15,
+ VF610_PAD_PTD30__NF_IO14,
+ VF610_PAD_PTD29__NF_IO13,
+ VF610_PAD_PTD28__NF_IO12,
+ VF610_PAD_PTD27__NF_IO11,
+ VF610_PAD_PTD26__NF_IO10,
+ VF610_PAD_PTD25__NF_IO9,
+ VF610_PAD_PTD24__NF_IO8,
+ VF610_PAD_PTD23__NF_IO7,
+ VF610_PAD_PTD22__NF_IO6,
+ VF610_PAD_PTD21__NF_IO5,
+ VF610_PAD_PTD20__NF_IO4,
+ VF610_PAD_PTD19__NF_IO3,
+ VF610_PAD_PTD18__NF_IO2,
+ VF610_PAD_PTD17__NF_IO1,
+ VF610_PAD_PTD16__NF_IO0,
+ VF610_PAD_PTB24__NF_WE_B,
+ VF610_PAD_PTB25__NF_CE0_B,
+ VF610_PAD_PTB27__NF_RE_B,
+ VF610_PAD_PTC26__NF_RB_B,
+ VF610_PAD_PTC27__NF_ALE,
+ VF610_PAD_PTC28__NF_CLE
+ };
+
+ imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
+}
+#endif
+
+
static void setup_iomux_qspi(void)
{
static const iomux_v3_cfg_t qspi0_pads[] = {
@@ -354,6 +413,8 @@ static void clock_init(void)
CCM_CCGR7_SDHC1_CTRL_MASK);
clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
+ clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
+ CCM_CCGR10_NFC_CTRL_MASK);
clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN,
ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT);
@@ -373,14 +434,17 @@ static void clock_init(void)
CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
CCM_CACRR_ARM_CLK_DIV(0));
clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
- CCM_CSCMR1_ESDHC1_CLK_SEL(3) | CCM_CSCMR1_QSPI0_CLK_SEL(3));
+ CCM_CSCMR1_ESDHC1_CLK_SEL(3) | CCM_CSCMR1_QSPI0_CLK_SEL(3) |
+ CCM_CSCMR1_NFC_CLK_SEL(0));
clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
CCM_CSCDR1_RMII_CLK_EN);
clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
- CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0));
+ CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) |
+ CCM_CSCDR2_NFC_EN);
clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) |
- CCM_CSCDR3_QSPI0_X2_DIV(1) | CCM_CSCDR3_QSPI0_X4_DIV(3));
+ CCM_CSCDR3_QSPI0_X2_DIV(1) | CCM_CSCDR3_QSPI0_X4_DIV(3) |
+ CCM_CSCDR3_NFC_PRE_DIV(5));
clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
CCM_CSCMR2_RMII_CLK_SEL(0));
}
@@ -411,6 +475,9 @@ int board_early_init_f(void)
setup_iomux_enet();
setup_iomux_i2c();
setup_iomux_qspi();
+#ifdef CONFIG_NAND_VF610_NFC
+ setup_iomux_nfc();
+#endif
return 0;
}
generated by cgit v1.2.3 (git 2.0.4) at 2024-07-03 08:58:16 +0000