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-rw-r--r--board/freescale/mx7dsabresd/Kconfig2
-rw-r--r--board/freescale/mx7dsabresd/imximage.cfg20
-rw-r--r--board/freescale/mx7dsabresd/imximage_TO_1_1.cfg124
-rw-r--r--board/freescale/mx7dsabresd/mx7dsabresd.c102
-rw-r--r--board/freescale/mx7dsabresd/plugin.S228
5 files changed, 448 insertions, 28 deletions
diff --git a/board/freescale/mx7dsabresd/Kconfig b/board/freescale/mx7dsabresd/Kconfig
index bf3ceafe2b..0f1d12a526 100644
--- a/board/freescale/mx7dsabresd/Kconfig
+++ b/board/freescale/mx7dsabresd/Kconfig
@@ -12,4 +12,6 @@ config SYS_CONFIG_NAME
config IMX_CONFIG
default "board/freescale/mx7dsabresd/imximage.cfg"
+config SYS_TEXT_BASE
+ default 0x87800000
endif
diff --git a/board/freescale/mx7dsabresd/imximage.cfg b/board/freescale/mx7dsabresd/imximage.cfg
index 59e66fbda1..cf0115b3fb 100644
--- a/board/freescale/mx7dsabresd/imximage.cfg
+++ b/board/freescale/mx7dsabresd/imximage.cfg
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
*
* Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
* and create imximage boot image
@@ -20,6 +21,10 @@ IMAGE_VERSION 2
BOOT_FROM sd
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
+PLUGIN board/freescale/mx7dsabresd/plugin.bin 0x00910000
+#else
/*
* Secure boot support
*/
@@ -40,6 +45,9 @@ CSF CONFIG_CSF_SIZE
*/
DATA 4 0x30340004 0x4F400005
+/* Clear then set bit30 to ensure exit from DDR retention */
+DATA 4 0x30360388 0x40000000
+DATA 4 0x30360384 0x40000000
DATA 4 0x30391000 0x00000002
DATA 4 0x307a0000 0x01040001
@@ -66,9 +74,10 @@ DATA 4 0x307a0184 0x02000100
DATA 4 0x307a0190 0x02098204
DATA 4 0x307a0194 0x00030303
DATA 4 0x307a0200 0x00000016
-DATA 4 0x307a0204 0x00171717
-DATA 4 0x307a0214 0x04040404
-DATA 4 0x307a0218 0x0f040404
+DATA 4 0x307a0204 0x00080808
+DATA 4 0x307a0210 0x00000f0f
+DATA 4 0x307a0214 0x07070707
+DATA 4 0x307a0218 0x0f070707
DATA 4 0x307a0240 0x06000604
DATA 4 0x307a0244 0x00000001
DATA 4 0x30391000 0x00000000
@@ -76,7 +85,7 @@ DATA 4 0x30790000 0x17420f40
DATA 4 0x30790004 0x10210100
DATA 4 0x30790010 0x00060807
DATA 4 0x307900b0 0x1010007e
-DATA 4 0x3079009c 0x00000d6e
+DATA 4 0x3079009c 0x00000b24
DATA 4 0x30790020 0x08080808
DATA 4 0x30790030 0x08080808
DATA 4 0x30790050 0x01000010
@@ -88,7 +97,6 @@ DATA 4 0x307900c0 0x0e447306
CHECK_BITS_SET 4 0x307900c4 0x1
-DATA 4 0x307900c0 0x0e447304
DATA 4 0x307900c0 0x0e407304
DATA 4 0x30384130 0x00000000
@@ -97,3 +105,5 @@ DATA 4 0x30384130 0x00000002
DATA 4 0x30790018 0x0000000f
CHECK_BITS_SET 4 0x307a0004 0x1
+
+#endif
diff --git a/board/freescale/mx7dsabresd/imximage_TO_1_1.cfg b/board/freescale/mx7dsabresd/imximage_TO_1_1.cfg
new file mode 100644
index 0000000000..854e3e552d
--- /dev/null
+++ b/board/freescale/mx7dsabresd/imximage_TO_1_1.cfg
@@ -0,0 +1,124 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * Refer doc/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM sd
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
+PLUGIN board/freescale/mx7dsabresd/plugin.bin 0x00910000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+
+#ifdef CONFIG_IMX_OPTEE
+DATA 4 0x30340024 0x1
+CHECK_BITS_SET 4 0x30340024 0x1
+#endif
+DATA 4 0x30360070 0x00703021
+DATA 4 0x30360090 0x0
+DATA 4 0x30360070 0x00603021
+CHECK_BITS_SET 4 0x30360070 0x80000000
+DATA 4 0x30389880 0x1
+
+DATA 4 0x30340004 0x4F400005
+/* Clear then set bit30 to ensure exit from DDR retention */
+DATA 4 0x30360388 0x40000000
+DATA 4 0x30360384 0x40000000
+
+DATA 4 0x30391000 0x00000002
+DATA 4 0x307a0000 0x01040001
+DATA 4 0x307a01a0 0x80400003
+DATA 4 0x307a01a4 0x00100020
+DATA 4 0x307a01a8 0x80100004
+DATA 4 0x307a0064 0x00400046
+DATA 4 0x307a0490 0x00000001
+DATA 4 0x307a00d0 0x00020083
+DATA 4 0x307a00d4 0x00690000
+DATA 4 0x307a00dc 0x09300004
+DATA 4 0x307a00e0 0x04080000
+DATA 4 0x307a00e4 0x00100004
+DATA 4 0x307a00f4 0x0000033f
+DATA 4 0x307a0100 0x09081109
+DATA 4 0x307a0104 0x0007020d
+DATA 4 0x307a0108 0x03040407
+DATA 4 0x307a010c 0x00002006
+DATA 4 0x307a0110 0x04020205
+DATA 4 0x307a0114 0x03030202
+DATA 4 0x307a0120 0x00000803
+DATA 4 0x307a0180 0x00800020
+DATA 4 0x307a0184 0x02000100
+DATA 4 0x307a0190 0x02098204
+DATA 4 0x307a0194 0x00030303
+DATA 4 0x307a0200 0x00000016
+DATA 4 0x307a0204 0x00080808
+DATA 4 0x307a0210 0x00000f0f
+DATA 4 0x307a0214 0x07070707
+DATA 4 0x307a0218 0x0f070707
+DATA 4 0x307a0240 0x06000604
+DATA 4 0x307a0244 0x00000001
+DATA 4 0x30391000 0x00000000
+DATA 4 0x30790000 0x17420f40
+DATA 4 0x30790004 0x10210100
+DATA 4 0x30790010 0x00060807
+DATA 4 0x307900b0 0x1010007e
+DATA 4 0x3079009c 0x00000dee
+DATA 4 0x3079007c 0x18181818
+DATA 4 0x30790080 0x18181818
+DATA 4 0x30790084 0x40401818
+DATA 4 0x30790088 0x00000040
+DATA 4 0x3079006c 0x40404040
+DATA 4 0x30790020 0x08080808
+DATA 4 0x30790030 0x08080808
+DATA 4 0x30790050 0x01000010
+DATA 4 0x30790050 0x00000010
+
+DATA 4 0x307900c0 0x0e407304
+DATA 4 0x307900c0 0x0e447304
+DATA 4 0x307900c0 0x0e447306
+
+CHECK_BITS_SET 4 0x307900c4 0x1
+
+DATA 4 0x307900c0 0x0e407304
+
+
+DATA 4 0x30384130 0x00000000
+DATA 4 0x30340020 0x00000178
+DATA 4 0x30384130 0x00000002
+DATA 4 0x30790018 0x0000000f
+
+CHECK_BITS_SET 4 0x307a0004 0x1
+
+#endif
diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c
index d28e52ba66..5c65986a2d 100644
--- a/board/freescale/mx7dsabresd/mx7dsabresd.c
+++ b/board/freescale/mx7dsabresd/mx7dsabresd.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
*/
#include <init.h>
@@ -12,6 +13,7 @@
#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
+#include <asm/mach-imx/boot_mode.h>
#include <asm/io.h>
#include <linux/delay.h>
#include <linux/sizes.h>
@@ -77,6 +79,55 @@ static iomux_v3_cfg_t const uart1_pads[] = {
MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
+#define BOARD_REV_C 0x300
+#define BOARD_REV_B 0x200
+#define BOARD_REV_A 0x100
+
+static int mx7sabre_rev(void)
+{
+ /*
+ * Get Board ID information from OCOTP_GP1[15:8]
+ * i.MX7D SDB RevA: 0x41
+ * i.MX7D SDB RevB: 0x42
+ */
+ struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+ struct fuse_bank *bank = &ocotp->bank[14];
+ int reg = readl(&bank->fuse_regs[0]);
+ int ret;
+
+ if (reg != 0) {
+ switch (reg >> 8 & 0x0F) {
+ case 0x3:
+ ret = BOARD_REV_C;
+ break;
+ case 0x02:
+ ret = BOARD_REV_B;
+ break;
+ case 0x01:
+ default:
+ ret = BOARD_REV_A;
+ break;
+ }
+ } else {
+ /* If the gp1 fuse is not burn, we have to use TO rev for the board rev */
+ if (is_soc_rev(CHIP_REV_1_0))
+ ret = BOARD_REV_A;
+ else if (is_soc_rev(CHIP_REV_1_1))
+ ret = BOARD_REV_B;
+ else
+ ret = BOARD_REV_C;
+ }
+
+ return ret;
+}
+
+u32 get_board_rev(void)
+{
+ int rev = mx7sabre_rev();
+
+ return (get_cpu_rev() & ~(0xF << 8)) | rev;
+}
+
#ifdef CONFIG_NAND_MXS
static iomux_v3_cfg_t const gpmi_pads[] = {
MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
@@ -222,22 +273,6 @@ static void setup_iomux_uart(void)
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
}
-int board_mmc_get_env_dev(int devno)
-{
- if (devno == 2)
- devno--;
-
- return devno;
-}
-
-int mmc_map_to_kernel_blk(int dev_no)
-{
- if (dev_no == 1)
- dev_no++;
-
- return dev_no;
-}
-
#ifdef CONFIG_FEC_MXC
static int setup_fec(void)
{
@@ -311,11 +346,13 @@ int board_init(void)
return 0;
}
+
#ifdef CONFIG_DM_PMIC
int power_init_board(void)
{
struct udevice *dev;
int ret, dev_id, rev_id;
+ u32 sw3mode;
ret = pmic_get("pfuze3000@8", &dev);
if (ret == -ENODEV)
@@ -335,6 +372,12 @@ int power_init_board(void)
*/
pmic_clrsetbits(dev, PFUZE3000_VLD4CTL, 0xF, 0xA);
+ /* change sw3 mode to avoid DDR power off */
+ sw3mode = pmic_reg_read(dev, PFUZE3000_SW3MODE);
+ ret = pmic_reg_write(dev, PFUZE3000_SW3MODE, sw3mode | 0x20);
+ if (ret < 0)
+ printf("PMIC: PFUZE3000 change sw3 mode failed\n");
+
return 0;
}
#endif
@@ -343,29 +386,42 @@ int board_late_init(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
+#ifdef CONFIG_ENV_IS_IN_MMC
+ board_late_mmc_env_init();
+#endif
+
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
set_wdog_reset(wdog);
- /*
- * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
- * since we use PMIC_PWRON to reset the board.
- */
- clrsetbits_le16(&wdog->wcr, 0, 0x10);
-
return 0;
}
int checkboard(void)
{
+ int rev = mx7sabre_rev();
char *mode;
+ char *revname;
if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT))
mode = "secure";
else
mode = "non-secure";
- printf("Board: i.MX7D SABRESD in %s mode\n", mode);
+ switch (rev) {
+ case BOARD_REV_C:
+ revname = "C";
+ break;
+ case BOARD_REV_B:
+ revname = "B";
+ break;
+ case BOARD_REV_A:
+ default:
+ revname = "A";
+ break;
+ }
+
+ printf("Board: i.MX7D SABRESD Rev%s in %s mode\n", revname, mode);
return 0;
}
diff --git a/board/freescale/mx7dsabresd/plugin.S b/board/freescale/mx7dsabresd/plugin.S
new file mode 100644
index 0000000000..025f50a777
--- /dev/null
+++ b/board/freescale/mx7dsabresd/plugin.S
@@ -0,0 +1,228 @@
+/*
+ * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+
+/* DDR script */
+.macro imx7d_ddrphy_latency_setting
+ ldr r2, =ANATOP_BASE_ADDR
+ ldr r3, [r2, #0x800]
+ and r3, r3, #0xFF
+ cmp r3, #0x11
+ bne NO_DELAY
+
+ /*TO 1.1*/
+ ldr r1, =0x00000dee
+ str r1, [r0, #0x9c]
+ ldr r1, =0x18181818
+ str r1, [r0, #0x7c]
+ ldr r1, =0x18181818
+ str r1, [r0, #0x80]
+ ldr r1, =0x40401818
+ str r1, [r0, #0x84]
+ ldr r1, =0x00000040
+ str r1, [r0, #0x88]
+ ldr r1, =0x40404040
+ str r1, [r0, #0x6c]
+ b TUNE_END
+
+NO_DELAY:
+ /*TO 1.0*/
+ ldr r1, =0x00000b24
+ str r1, [r0, #0x9c]
+
+TUNE_END:
+.endm
+
+.macro imx7d_ddr_freq_setting
+ ldr r2, =ANATOP_BASE_ADDR
+ ldr r3, [r2, #0x800]
+ and r3, r3, #0xFF
+ cmp r3, #0x11
+ bne FREQ_DEFAULT_533
+
+ /* Change to 400Mhz for TO1.1 */
+ ldr r0, =ANATOP_BASE_ADDR
+ ldr r1, =0x70
+ ldr r2, =0x00703021
+ str r2, [r0, r1]
+ ldr r1, =0x90
+ ldr r2, =0x0
+ str r2, [r0, r1]
+ ldr r1, =0x70
+ ldr r2, =0x00603021
+ str r2, [r0, r1]
+
+ ldr r3, =0x80000000
+wait_lock:
+ ldr r2, [r0, r1]
+ and r2, r3
+ cmp r2, r3
+ bne wait_lock
+
+ ldr r0, =CCM_BASE_ADDR
+ ldr r1, =0x9880
+ ldr r2, =0x1
+ str r2, [r0, r1]
+
+FREQ_DEFAULT_533:
+.endm
+
+.macro imx7d_sabresd_ddr_setting
+ imx7d_ddr_freq_setting
+
+ /* Configure ocram_epdc */
+ ldr r0, =IOMUXC_GPR_BASE_ADDR
+ ldr r1, =0x4f400005
+ str r1, [r0, #0x4]
+
+ /* clear/set bit30 of SNVS_MISC_CTRL to ensure exit from ddr retention */
+ ldr r0, =ANATOP_BASE_ADDR
+ ldr r1, =(0x1 << 30)
+ str r1, [r0, #0x388]
+ str r1, [r0, #0x384]
+
+ ldr r0, =SRC_BASE_ADDR
+ ldr r1, =0x2
+ ldr r2, =0x1000
+ str r1, [r0, r2]
+
+ ldr r0, =DDRC_IPS_BASE_ADDR
+ ldr r1, =0x01040001
+ str r1, [r0]
+ ldr r1, =0x80400003
+ str r1, [r0, #0x1a0]
+ ldr r1, =0x00100020
+ str r1, [r0, #0x1a4]
+ ldr r1, =0x80100004
+ str r1, [r0, #0x1a8]
+ ldr r1, =0x00400046
+ str r1, [r0, #0x64]
+ ldr r1, =0x1
+ str r1, [r0, #0x490]
+ ldr r1, =0x00020001
+ str r1, [r0, #0xd0]
+ ldr r1, =0x00690000
+ str r1, [r0, #0xd4]
+ ldr r1, =0x09300004
+ str r1, [r0, #0xdc]
+ ldr r1, =0x04080000
+ str r1, [r0, #0xe0]
+ ldr r1, =0x00100004
+ str r1, [r0, #0xe4]
+ ldr r1, =0x33f
+ str r1, [r0, #0xf4]
+ ldr r1, =0x09081109
+ str r1, [r0, #0x100]
+ ldr r1, =0x0007020d
+ str r1, [r0, #0x104]
+ ldr r1, =0x03040407
+ str r1, [r0, #0x108]
+ ldr r1, =0x00002006
+ str r1, [r0, #0x10c]
+ ldr r1, =0x04020205
+ str r1, [r0, #0x110]
+ ldr r1, =0x03030202
+ str r1, [r0, #0x114]
+ ldr r1, =0x00000803
+ str r1, [r0, #0x120]
+ ldr r1, =0x00800020
+ str r1, [r0, #0x180]
+ ldr r1, =0x02000100
+ str r1, [r0, #0x184]
+ ldr r1, =0x02098204
+ str r1, [r0, #0x190]
+ ldr r1, =0x00030303
+ str r1, [r0, #0x194]
+
+ ldr r1, =0x00000016
+ str r1, [r0, #0x200]
+ ldr r1, =0x00080808
+ str r1, [r0, #0x204]
+ ldr r1, =0x00000f0f
+ str r1, [r0, #0x210]
+ ldr r1, =0x07070707
+ str r1, [r0, #0x214]
+ ldr r1, =0x0f070707
+ str r1, [r0, #0x218]
+
+ ldr r1, =0x06000604
+ str r1, [r0, #0x240]
+ ldr r1, =0x00000001
+ str r1, [r0, #0x244]
+
+ ldr r0, =SRC_BASE_ADDR
+ mov r1, #0x0
+ ldr r2, =0x1000
+ str r1, [r0, r2]
+
+ ldr r0, =DDRPHY_IPS_BASE_ADDR
+ ldr r1, =0x17420f40
+ str r1, [r0]
+ ldr r1, =0x10210100
+ str r1, [r0, #0x4]
+ ldr r1, =0x00060807
+ str r1, [r0, #0x10]
+ ldr r1, =0x1010007e
+ str r1, [r0, #0xb0]
+ imx7d_ddrphy_latency_setting
+ ldr r1, =0x08080808
+ str r1, [r0, #0x20]
+ ldr r1, =0x08080808
+ str r1, [r0, #0x30]
+ ldr r1, =0x01000010
+ str r1, [r0, #0x50]
+
+ ldr r1, =0x0e407304
+ str r1, [r0, #0xc0]
+ ldr r1, =0x0e447304
+ str r1, [r0, #0xc0]
+ ldr r1, =0x0e447306
+ str r1, [r0, #0xc0]
+
+wait_zq:
+ ldr r1, [r0, #0xc4]
+ tst r1, #0x1
+ beq wait_zq
+
+ ldr r1, =0x0e407304
+ str r1, [r0, #0xc0]
+
+ ldr r0, =CCM_BASE_ADDR
+ mov r1, #0x0
+ ldr r2, =0x4130
+ str r1, [r0, r2]
+ ldr r0, =IOMUXC_GPR_BASE_ADDR
+ mov r1, #0x178
+ str r1, [r0, #0x20]
+ ldr r0, =CCM_BASE_ADDR
+ mov r1, #0x2
+ ldr r2, =0x4130
+ str r1, [r0, r2]
+ ldr r0, =DDRPHY_IPS_BASE_ADDR
+ ldr r1, =0x0000000f
+ str r1, [r0, #0x18]
+
+ ldr r0, =DDRC_IPS_BASE_ADDR
+wait_stat:
+ ldr r1, [r0, #0x4]
+ tst r1, #0x1
+ beq wait_stat
+.endm
+
+.macro imx7_clock_gating
+.endm
+
+.macro imx7_qos_setting
+.endm
+
+.macro imx7_ddr_setting
+ imx7d_sabresd_ddr_setting
+.endm
+
+/* include the common plugin code here */
+#include <asm/arch/mx7_plugin.S>
generated by cgit v1.2.3 (git 2.0.4) at 2024-07-02 05:17:30 +0000