diff options
Diffstat (limited to 'board/freescale/mx6q_arm2/flash_header.S')
| -rw-r--r-- | board/freescale/mx6q_arm2/flash_header.S | 29 |
1 files changed, 6 insertions, 23 deletions
diff --git a/board/freescale/mx6q_arm2/flash_header.S b/board/freescale/mx6q_arm2/flash_header.S index 1eec5c4969..b62428bf14 100644 --- a/board/freescale/mx6q_arm2/flash_header.S +++ b/board/freescale/mx6q_arm2/flash_header.S @@ -65,8 +65,8 @@ image_len: .word _end_of_copy - TEXT_BASE + CONFIG_FLASH_HEADER_OFFSET plugin: .word 0x0 #if defined CONFIG_MX6DL_DDR3 -dcd_hdr: .word 0x40F802D2 /* Tag=0xD2, Len=94*8 + 4 + 4, Ver=0x40 */ -write_dcd_cmd: .word 0x04F402CC /* Tag=0xCC, Len=94*8 + 4, Param=0x04 */ +dcd_hdr: .word 0x40E002D2 /* Tag=0xD2, Len=91*8 + 4 + 4, Ver=0x40 */ +write_dcd_cmd: .word 0x04DC02CC /* Tag=0xCC, Len=91*8 + 4, Param=0x04 */ # IOMUXC_BASE_ADDR = 0x20e0000 # DDR IO TYPE @@ -194,12 +194,6 @@ MXC_DCD_ITEM(89, MMDC_P0_BASE_ADDR + 0x004, 0x0002556d) MXC_DCD_ITEM(90, MMDC_P1_BASE_ADDR + 0x004, 0x00011006) MXC_DCD_ITEM(91, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000) -/* enable AXI cache for VDOA/VPU/IPU */ -MXC_DCD_ITEM(92, IOMUXC_BASE_ADDR + 0x010, 0xf00000ff) -/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ -MXC_DCD_ITEM(93, IOMUXC_BASE_ADDR + 0x018, 0x007f007f) -MXC_DCD_ITEM(94, IOMUXC_BASE_ADDR + 0x01c, 0x007f007f) - #elif defined CONFIG_MX6DL_LPDDR2 dcd_hdr: .word 0x408803D2 /* Tag=0xD2, Len=112*8 + 4 + 4, Ver=0x40 */ @@ -506,8 +500,8 @@ MXC_DCD_ITEM(111, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000) MXC_DCD_ITEM(112, MMDC_P1_BASE_ADDR + 0x01c, 0x00000000) #elif defined(CONFIG_LPDDR2) -dcd_hdr: .word 0x400804D2 /* Tag=0xD2, Len=128*8 + 4 + 4, Ver=0x40 */ -write_dcd_cmd: .word 0x040404CC /* Tag=0xCC, Len=128*8 + 4, Param=0x04 */ +dcd_hdr: .word 0x40F003D2 /* Tag=0xD2, Len=125*8 + 4 + 4, Ver=0x40 */ +write_dcd_cmd: .word 0x04EC03CC /* Tag=0xCC, Len=125*8 + 4, Param=0x04 */ /* DCD */ MXC_DCD_ITEM(1, CCM_BASE_ADDR + 0x18, 0x60324) @@ -672,12 +666,6 @@ MXC_DCD_ITEM(124, MMDC_P1_BASE_ADDR + 0x1c, 0x0) MXC_DCD_ITEM(125, MMDC_P0_BASE_ADDR + 0x404, 0x00011006) -/* enable AXI cache for VDOA/VPU/IPU */ -MXC_DCD_ITEM(126, IOMUXC_BASE_ADDR + 0x010, 0xf00000ff) -/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ -MXC_DCD_ITEM(127, IOMUXC_BASE_ADDR + 0x018, 0x007f007f) -MXC_DCD_ITEM(128, IOMUXC_BASE_ADDR + 0x01c, 0x007f007f) - #elif defined CONFIG_LPDDR2POP dcd_hdr: .word 0x40F003D2 /* Tag=0xD2, Len=125*8 + 4 + 4, Ver=0x40 */ write_dcd_cmd: .word 0x04E403CC /* Tag=0xCC, Len=125*8 + 4, Param=0x04 */ @@ -819,8 +807,8 @@ MXC_DCD_ITEM(123, MMDC_P1_BASE_ADDR + 0x404, 0x00011006) MXC_DCD_ITEM(124, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000) MXC_DCD_ITEM(125, MMDC_P1_BASE_ADDR + 0x01c, 0x00000000) #else -dcd_hdr: .word 0x40F002D2 /* Tag=0xD2, Len=93*8 + 4 + 4, Ver=0x40 */ -write_dcd_cmd: .word 0x04EC02CC /* Tag=0xCC, Len=93*8 + 4, Param=0x04 */ +dcd_hdr: .word 0x40D802D2 /* Tag=0xD2, Len=90*8 + 4 + 4, Ver=0x40 */ +write_dcd_cmd: .word 0x04D402CC /* Tag=0xCC, Len=90*8 + 4, Param=0x04 */ /* DCD */ @@ -936,11 +924,6 @@ MXC_DCD_ITEM(88, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800) MXC_DCD_ITEM(89, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000) MXC_DCD_ITEM(90, MMDC_P0_BASE_ADDR + 0x404, 0x00011006) -/* enable AXI cache for VDOA/VPU/IPU */ -MXC_DCD_ITEM(91, IOMUXC_BASE_ADDR + 0x010, 0xf00000ff) -/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ -MXC_DCD_ITEM(92, IOMUXC_BASE_ADDR + 0x018, 0x007f007f) -MXC_DCD_ITEM(93, IOMUXC_BASE_ADDR + 0x01c, 0x007f007f) #endif #else |