9 files changed, 0 insertions, 629 deletions
diff --git a/board/freescale/bsc9131rdb/Kconfig b/board/freescale/bsc9131rdb/Kconfig
deleted file mode 100644
index dd9f765d7d..0000000000
--- a/board/freescale/bsc9131rdb/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_BSC9131RDB
-
-config SYS_BOARD
-	default "bsc9131rdb"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "BSC9131RDB"
-
-endif
diff --git a/board/freescale/bsc9131rdb/MAINTAINERS b/board/freescale/bsc9131rdb/MAINTAINERS
deleted file mode 100644
index 272d4ad3aa..0000000000
--- a/board/freescale/bsc9131rdb/MAINTAINERS
+++ /dev/null
@@ -1,9 +0,0 @@
-BSC9131RDB BOARD
-M:	Poonam Aggrwal <poonam.aggrwal@nxp.com>
-S:	Maintained
-F:	board/freescale/bsc9131rdb/
-F:	include/configs/BSC9131RDB.h
-F:	configs/BSC9131RDB_NAND_defconfig
-F:	configs/BSC9131RDB_NAND_SYSCLK100_defconfig
-F:	configs/BSC9131RDB_SPIFLASH_defconfig
-F:	configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig
diff --git a/board/freescale/bsc9131rdb/Makefile b/board/freescale/bsc9131rdb/Makefile
deleted file mode 100644
index 063db4495e..0000000000
--- a/board/freescale/bsc9131rdb/Makefile
+++ /dev/null
@@ -1,21 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2011-2012 Freescale Semiconductor, Inc.
-
-MINIMAL=
-
-ifdef CONFIG_SPL_BUILD
-ifdef CONFIG_SPL_INIT_MINIMAL
-MINIMAL=y
-endif
-endif
-
-ifdef MINIMAL
-obj-y	+= spl_minimal.o
-else
-obj-y	+= bsc9131rdb.o
-obj-y	+= ddr.o
-endif
-
-obj-y	+= law.o
-obj-y	+= tlb.o
diff --git a/board/freescale/bsc9131rdb/README b/board/freescale/bsc9131rdb/README
deleted file mode 100644
index c8405970c1..0000000000
--- a/board/freescale/bsc9131rdb/README
+++ /dev/null
@@ -1,151 +0,0 @@
-Overview
---------
-- BSC9131 is integrated device that targets Femto base station market.
- It combines Power Architecture e500v2 and DSP StarCore SC3850 core
- technologies with MAPLE-B2F baseband acceleration processing elements.
-- It's MAPLE disabled personality is called 9231.
-
-The BSC9131 SoC includes the following function and features:
-. Power Architecture subsystem including a e500 processor with 256-Kbyte shared
-  L2 cache
-. StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
-. The Multi Accelerator Platform Engine for Femto BaseStation Baseband
-  Processing (MAPLE-B2F)
-. A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding,
- Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing,
- and CRC algorithms
-. Consists of accelerators for Convolution, Filtering, Turbo Encoding,
- Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion
- operations
-. DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with
- ECC, up to 400-MHz clock/800 MHz data rate
-. Dedicated security engine featuring trusted boot
-. DMA controller
-. OCNDMA with four bidirectional channels
-. Interfaces
-. Two triple-speed Gigabit Ethernet controllers featuring network acceleration
-  including IEEE 1588. v2 hardware support and virtualization (eTSEC)
-. eTSEC 1 supports RGMII/RMII
-. eTSEC 2 supports RGMII
-. High-speed USB 2.0 host and device controller with ULPI interface
-. Enhanced secure digital (SD/MMC) host controller (eSDHC)
-. Antenna interface controller (AIC), supporting three industry standard
-  JESD207/three custom ADI RF interfaces (two dual port and one single port)
-  and three MAXIM's MaxPHY serial interfaces
-. ADI lanes support both full duplex FDD support and half duplex TDD support
-. Universal Subscriber Identity Module (USIM) interface that facilitates
-  communication to SIM cards or Eurochip pre-paid phone cards
-. TDM with one TDM port
-. Two DUART, four eSPI, and two I2C controllers
-. Integrated Flash memory controller (IFC)
-. TDM with 256 channels
-. GPIO
-. Sixteen 32-bit timers
-
-The e500 core subsystem within the Power Architecture consists of the following:
-. 32-Kbyte L1 instruction cache
-. 32-Kbyte L1 data cache
-. 256-Kbyte L2 cache/L2 memory/L2 stash
-. programmable interrupt controller (PIC)
-. Debug support
-. Timers
-
-The SC3850 core subsystem consists of the following:
-. 32 Kbyte 8-way level 1 instruction cache (L1 ICache)
-. 32 Kbyte 8-way level 1 data cache (L1 DCache)
-. 512 Kbyte 8-way level 2 unified instruction/data cache (M2 memory)
-. Memory management unit (MMU)
-. Enhanced programmable interrupt controller (EPIC)
-. Debug and profiling unit (DPU)
-. Two 32-bit timers
-
-BSC9131RDB board Overview
--------------------------
- 1Gbyte DDR3 (on board DDR)
- 128Mbyte 2K page size NAND Flash
- 256 Kbit M24256 I2C EEPROM
- 128 Mbit SPI Flash memory
- USB-ULPI
- eTSEC1: Connected to RGMII PHY
- eTSEC2: Connected to RGMII PHY
- DUART interface: supports one UARTs up to 115200 bps for console display
- USIM connector
-
-Frequency Combinations Supported
---------------------------------
-Core MHz/CCB MHz/DDR(MT/s)
-1. 1000/500/800
-2. 800/400/667
-
-Boot Methods Supported
------------------------
-1. NAND Flash
-2. SPI Flash
-
-Default Boot Method
---------------------
-NAND boot
-
-Building U-Boot
---------------
-To build the U-Boot for BSC9131RDB:
-1. NAND Flash with sysclk 66MHz(J16 on RDB closed, default)
-	make BSC9131RDB_NAND
-2. NAND Flash with sysclk 100MHz(J16 on RDB open)
-	make BSC9131RDB_NAND_SYSCLK100
-3. SPI Flash with sysclk 66MHz(J16 on RDB closed, default)
-	make BSC9131RDB_SPIFLASH
-4. SPI Flash with sysclk 100MHz(J16 on RDB open)
-	make BSC9131RDB_SPIFLASH_SYSCLK100
-
-Memory map
------------
- 0x0000_0000	0x7FFF_FFFF	DDR			1G cacheable
- 0xA0000000	0xBFFFFFFF	Shared DSP core L2/M2 space	512M
- 0xC100_0000	0xC13F_FFFF	MAPLE-2F		4M
- 0xC1F0_0000	0xC1F3_FFFF	PA SRAM Region 0	256K
- 0xC1F8_0000	0xC1F9_FFFF	PA SRAM Region 1	128K
- 0xFED0_0000	0xFED0_3FFF	SEC Secured RAM		16K
- 0xFEE0_0000	0xFEE0_0FFF	DSP Boot ROM		4K
- 0xFF60_0000	0xFF6F_FFFF 	DSP CCSR		1M
- 0xFF70_0000	0xFF7F_FFFF	PA CCSR			1M
- 0xFF80_0000	0xFFFF_FFFF	Boot Page & NAND Buffer 8M
-
-DDR Memory map
----------------
- 0x0000_0000	0x36FF_FFFF	Memory passed onto Linux
- 0x3700_0000	0x37FF_FFFF	PowerPC-DSP shared control area
- 0x3800_0000	0x4FFF_FFFF	DSP Private area
-
- Out of 880M, passed onto Linux, 1hugetlb page of 256M is reserved for
- data communcation between PowerPC and DSP core.
- Rest is PowerPC private area.
-
-Flashing Images
----------------
-To place a new U-Boot image in the NAND flash and then boot
-with that new image temporarily, use this:
-	tftp 1000000 u-boot-nand.bin
-	nand erase 0 100000
-	nand write 1000000 0 100000
-	reset
-
-Using the Device Tree Source File
----------------------------------
-To create the DTB (Device Tree Binary) image file,
-use a command similar to this:
-
-	dtc -b 0 -f -I dts -O dtb bsc9131rdb.dts > bsc9131rdb.dtb
-
-Likely, that .dts file will come from here;
-
-	linux-2.6/arch/powerpc/boot/dts/bsc9131rdb.dts
-
-Booting Linux
--------------
-Place a linux uImage in the TFTP disk area.
-
-	tftp 1000000 uImage
-	tftp 2000000 rootfs.ext2.gz.uboot
-	tftp c00000 bsc9131rdb.dtb
-	bootm 1000000 2000000 c00000
diff --git a/board/freescale/bsc9131rdb/bsc9131rdb.c b/board/freescale/bsc9131rdb/bsc9131rdb.c
deleted file mode 100644
index 75c2aec75d..0000000000
--- a/board/freescale/bsc9131rdb/bsc9131rdb.c
+++ /dev/null
@@ -1,82 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <image.h>
-#include <init.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/cache.h>
-#include <asm/immap_85xx.h>
-#include <asm/io.h>
-#include <env.h>
-#include <miiphy.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <fsl_mdio.h>
-#include <tsec.h>
-#include <jffs2/load_kernel.h>
-#include <mtd_node.h>
-#include <flash.h>
-#include <netdev.h>
-
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
-	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
-	clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42);
-	setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS);
-
-	clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43);
-	setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK |
-			MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD);
-	setbits_be32(&gur->halt_req_mask, HALTED_TO_HALT_REQ_MASK_0);
-	clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_IFC_AD_GPIO_MASK |
-			MPC85xx_PMUXCR_IFC_AD17_GPO_MASK,
-			MPC85xx_PMUXCR_IFC_AD_GPIO |
-			MPC85xx_PMUXCR_IFC_AD17_GPO | MPC85xx_PMUXCR_SDHC_USIM);
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	struct cpu_type *cpu;
-
-	cpu = gd->arch.cpu;
-	printf("Board: %sRDB\n", cpu->name);
-
-	return 0;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-#ifdef CONFIG_FDT_FIXUP_PARTITIONS
-static const struct node_info nodes[] = {
-	{ "fsl,ifc-nand",		MTD_DEV_TYPE_NAND, },
-};
-#endif
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	phys_addr_t base;
-	phys_size_t size;
-
-	ft_cpu_setup(blob, bd);
-
-	base = env_get_bootm_low();
-	size = env_get_bootm_size();
-
-	fdt_fixup_memory(blob, (u64)base, (u64)size);
-#ifdef CONFIG_FDT_FIXUP_PARTITIONS
-	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
-#endif
-
-	fsl_fdt_fixup_dr_usb(blob, bd);
-
-	return 0;
-}
-#endif
diff --git a/board/freescale/bsc9131rdb/ddr.c b/board/freescale/bsc9131rdb/ddr.c
deleted file mode 100644
index 0951d7758a..0000000000
--- a/board/freescale/bsc9131rdb/ddr.c
+++ /dev/null
@@ -1,170 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <init.h>
-#include <vsprintf.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/processor.h>
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-#include <asm/io.h>
-#include <asm/fsl_law.h>
-
-#ifndef CONFIG_SYS_DDR_RAW_TIMING
-#define CONFIG_SYS_DRAM_SIZE	1024
-
-fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
-	.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
-	.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
-	.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
-	.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
-	.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
-	.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
-	.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
-	.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
-	.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
-	.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
-	.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
-	.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
-	.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
-	.ddr_data_init = CONFIG_MEM_INIT_VALUE,
-	.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
-	.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
-	.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
-	.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
-	.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
-	.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
-	.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800,
-	.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
-	.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
-	.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
-};
-
-fixed_ddr_parm_t fixed_ddr_parm_0[] = {
-	{750, 850, &ddr_cfg_regs_800},
-	{0, 0, NULL}
-};
-
-unsigned long get_sdram_size(void)
-{
-	return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DRAM_SIZE);
-}
-
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-phys_size_t fixed_sdram(void)
-{
-	int i;
-	char buf[32];
-	fsl_ddr_cfg_regs_t ddr_cfg_regs;
-	phys_size_t ddr_size;
-	ulong ddr_freq, ddr_freq_mhz;
-
-	ddr_freq = get_ddr_freq(0);
-	ddr_freq_mhz = ddr_freq / 1000000;
-
-	printf("Configuring DDR for %s MT/s data rate\n",
-				strmhz(buf, ddr_freq));
-
-	for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
-		if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
-		   (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
-			memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings,
-							sizeof(ddr_cfg_regs));
-			break;
-		}
-	}
-
-	if (fixed_ddr_parm_0[i].max_freq == 0) {
-		panic("Unsupported DDR data rate %s MT/s data rate\n",
-					strmhz(buf, ddr_freq));
-	}
-
-	ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-	fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
-
-	if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
-					LAW_TRGT_IF_DDR_1) < 0) {
-		printf("ERROR setting Local Access Windows for DDR\n");
-		return 0;
-	}
-
-	return ddr_size;
-}
-
-#else /* CONFIG_SYS_DDR_RAW_TIMING */
-/* Micron MT41J256M8HX-15E */
-dimm_params_t ddr_raw_timing = {
-	.n_ranks = 1,
-	.rank_density = 1073741824u,
-	.capacity = 1073741824u,
-	.primary_sdram_width = 32,
-	.ec_sdram_width = 0,
-	.registered_dimm = 0,
-	.mirrored_dimm = 0,
-	.n_row_addr = 15,
-	.n_col_addr = 10,
-	.n_banks_per_sdram_device = 8,
-	.edc_config = 0,
-	.burst_lengths_bitmask = 0x0c,
-
-	.tckmin_x_ps = 1870,
-	.caslat_x = 0x1e << 4,	/* 5,6,7,8 */
-	.taa_ps = 13125,
-	.twr_ps = 15000,
-	.trcd_ps = 13125,
-	.trrd_ps = 7500,
-	.trp_ps = 13125,
-	.tras_ps = 37500,
-	.trc_ps = 50625,
-	.trfc_ps = 160000,
-	.twtr_ps = 7500,
-	.trtp_ps = 7500,
-	.refresh_rate_ps = 7800000,
-	.tfaw_ps = 37500,
-};
-
-int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
-		unsigned int controller_number,
-		unsigned int dimm_number)
-{
-	const char dimm_model[] = "Fixed DDR on board";
-
-	if ((controller_number == 0) && (dimm_number == 0)) {
-		memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
-		memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
-		memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
-	}
-
-	return 0;
-}
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num)
-{
-	int i;
-	popts->clk_adjust = 6;
-	popts->cpo_override = 0x1f;
-	popts->write_data_delay = 2;
-	popts->half_strength_driver_enable = 1;
-	/* Write leveling override */
-	popts->wrlvl_en = 1;
-	popts->wrlvl_override = 1;
-	popts->wrlvl_sample = 0xf;
-	popts->wrlvl_start = 0x8;
-	popts->trwt_override = 1;
-	popts->trwt = 0;
-
-	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
-		popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
-		popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
-	}
-}
-
-#endif /* CONFIG_SYS_DDR_RAW_TIMING */
diff --git a/board/freescale/bsc9131rdb/law.c b/board/freescale/bsc9131rdb/law.c
deleted file mode 100644
index ccfe4a2410..0000000000
--- a/board/freescale/bsc9131rdb/law.c
+++ /dev/null
@@ -1,18 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
-	SET_LAW(CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, LAW_SIZE_1M,
-		LAW_TRGT_IF_DSP_CCSR),
-	SET_LAW(CONFIG_SYS_FSL_DSP_M2_RAM_ADDR, LAW_SIZE_16M,
-		LAW_TRGT_IF_OCN_DSP),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/bsc9131rdb/spl_minimal.c b/board/freescale/bsc9131rdb/spl_minimal.c
deleted file mode 100644
index 4ae9ba06c8..0000000000
--- a/board/freescale/bsc9131rdb/spl_minimal.c
+++ /dev/null
@@ -1,105 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <init.h>
-#include <ns16550.h>
-#include <asm/io.h>
-#include <nand.h>
-#include <linux/compiler.h>
-#include <asm/fsl_law.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/global_data.h>
-#include <linux/delay.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-static void sdram_init(void)
-{
-	struct ccsr_ddr __iomem *ddr =
-		(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
-
-	__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
-	__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
-#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
-	__raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
-	__raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
-#endif
-	__raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3);
-	__raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0);
-	__raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1);
-	__raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2);
-
-	__raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
-	__raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode);
-	__raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2);
-
-	__raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval);
-	__raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
-	__raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl);
-
-	__raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl);
-	__raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
-	__raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
-	__raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
-
-	/* Set, but do not enable the memory */
-	__raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg);
-
-	asm volatile("sync;isync");
-	udelay(500);
-
-	/* Let the controller go */
-	out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
-
-	set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1);
-}
-
-void board_init_f(ulong bootflag)
-{
-	u32 plat_ratio;
-	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
-	/* initialize selected port with appropriate baud rate */
-	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
-	plat_ratio >>= 1;
-	gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
-
-	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
-		     gd->bus_clk / 16 / CONFIG_BAUDRATE);
-
-	puts("\nNAND boot... ");
-
-	/* Initialize the DDR3 */
-	sdram_init();
-
-	/* copy code to RAM and jump to it - this should not return */
-	/* NOTE - code has to be copied out of NAND buffer before
-	 * other blocks can be read.
-	 */
-	relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
-	nand_boot();
-}
-
-void putc(char c)
-{
-	if (c == '\n')
-		NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
-
-	NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
-}
-
-void puts(const char *str)
-{
-	while (*str)
-		putc(*str++);
-}
diff --git a/board/freescale/bsc9131rdb/tlb.c b/board/freescale/bsc9131rdb/tlb.c
deleted file mode 100644
index e1aacf0607..0000000000
--- a/board/freescale/bsc9131rdb/tlb.c
+++ /dev/null
@@ -1,61 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
-			MAS3_SX|MAS3_SW|MAS3_SR, 0,
-			0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
-			CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-			MAS3_SX|MAS3_SW|MAS3_SR, 0,
-			0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
-			CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-			MAS3_SX|MAS3_SW|MAS3_SR, 0,
-			0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
-			CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-			MAS3_SX|MAS3_SW|MAS3_SR, 0,
-			0, 0, BOOKE_PAGESZ_4K, 0),
-
-	/* TLB 1 */
-	/* *I*** - Covers boot page */
-	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_4K, 1),
-#ifdef CONFIG_SPL_NAND_BOOT
-	SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 10, BOOKE_PAGESZ_4K, 1),
-#endif
-
-	/* *I*G* - CCSRBAR (PA) */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, 1, BOOKE_PAGESZ_1M, 1),
-
-	/* CCSRBAR (DSP) */
-	SET_TLB_ENTRY(1, CONFIG_SYS_FSL_DSP_CCSRBAR,
-		      CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS,
-		      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 2, BOOKE_PAGESZ_1M, 1),
-
-#if  defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
-	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
-			0, 8, BOOKE_PAGESZ_1G, 1),
-#endif
-
-	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
-			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-			0, 3, BOOKE_PAGESZ_1M, 1)
-
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);