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-rw-r--r--board/coreboot/coreboot/Kconfig40
-rw-r--r--board/coreboot/coreboot/MAINTAINERS6
-rw-r--r--board/coreboot/coreboot/Makefile15
-rw-r--r--board/coreboot/coreboot/coreboot.c24
-rw-r--r--board/coreboot/coreboot/coreboot_start.S13
5 files changed, 98 insertions, 0 deletions
diff --git a/board/coreboot/coreboot/Kconfig b/board/coreboot/coreboot/Kconfig
new file mode 100644
index 00000000000..981de1f0711
--- /dev/null
+++ b/board/coreboot/coreboot/Kconfig
@@ -0,0 +1,40 @@
+if TARGET_COREBOOT
+
+config SYS_BOARD
+ default "coreboot"
+
+config SYS_VENDOR
+ default "coreboot"
+
+config SYS_SOC
+ default "coreboot"
+
+comment "coreboot-specific options"
+
+config SYS_CONFIG_NAME
+ string "Board configuration file"
+ default "chromebook_link"
+ help
+ This option selects the board configuration file in include/configs/
+ directory to be used to build U-Boot for coreboot.
+
+config DEFAULT_DEVICE_TREE
+ string "Board Device Tree Source (dts) file"
+ default "chromebook_link"
+ help
+ This option selects the board Device Tree Source (dts) file in
+ arch/x86/dts/ directory to be used to build U-Boot for coreboot.
+
+config SYS_CAR_ADDR
+ hex "Board specific Cache-As-RAM (CAR) address"
+ default 0x19200000
+ help
+ This option specifies the board specific Cache-As-RAM (CAR) address.
+
+config SYS_CAR_SIZE
+ hex "Board specific Cache-As-RAM (CAR) size"
+ default 0x4000
+ help
+ This option specifies the board specific Cache-As-RAM (CAR) size.
+
+endif
diff --git a/board/coreboot/coreboot/MAINTAINERS b/board/coreboot/coreboot/MAINTAINERS
new file mode 100644
index 00000000000..2736aa02826
--- /dev/null
+++ b/board/coreboot/coreboot/MAINTAINERS
@@ -0,0 +1,6 @@
+COREBOOT BOARD
+M: Simon Glass <sjg@chromium.org>
+S: Maintained
+F: board/coreboot/coreboot/
+F: include/configs/chromebook_link.h
+F: configs/coreboot-x86_defconfig
diff --git a/board/coreboot/coreboot/Makefile b/board/coreboot/coreboot/Makefile
new file mode 100644
index 00000000000..27ebe78eb13
--- /dev/null
+++ b/board/coreboot/coreboot/Makefile
@@ -0,0 +1,15 @@
+#
+# Copyright (c) 2011 The Chromium OS Authors.
+# (C) Copyright 2008
+# Graeme Russ, graeme.russ@gmail.com.
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2002
+# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += coreboot_start.o coreboot.o
diff --git a/board/coreboot/coreboot/coreboot.c b/board/coreboot/coreboot/coreboot.c
new file mode 100644
index 00000000000..e076ea69cfa
--- /dev/null
+++ b/board/coreboot/coreboot/coreboot.c
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <cros_ec.h>
+#include <asm/gpio.h>
+
+int arch_early_init_r(void)
+{
+#ifdef CONFIG_CROS_EC
+ if (cros_ec_board_init())
+ return -1;
+#endif
+
+ return 0;
+}
+
+void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
+{
+ return;
+}
diff --git a/board/coreboot/coreboot/coreboot_start.S b/board/coreboot/coreboot/coreboot_start.S
new file mode 100644
index 00000000000..932fe6c24bf
--- /dev/null
+++ b/board/coreboot/coreboot/coreboot_start.S
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ@gmail.com.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* board early intialization */
+.globl early_board_init
+early_board_init:
+ /* No 32-bit board specific initialisation */
+ jmp early_board_init_ret