diff options
Diffstat (limited to 'board/at91sam9263ek')
-rw-r--r-- | board/at91sam9263ek/Makefile | 46 | ||||
-rw-r--r-- | board/at91sam9263ek/at91sam9263ek.c | 224 | ||||
-rw-r--r-- | board/at91sam9263ek/config.mk | 1 | ||||
-rw-r--r-- | board/at91sam9263ek/dm9161a.c | 300 | ||||
-rw-r--r-- | board/at91sam9263ek/flash.c | 567 | ||||
-rw-r--r-- | board/at91sam9263ek/nand.c | 107 | ||||
-rw-r--r-- | board/at91sam9263ek/u-boot.lds | 55 |
7 files changed, 1300 insertions, 0 deletions
diff --git a/board/at91sam9263ek/Makefile b/board/at91sam9263ek/Makefile new file mode 100644 index 0000000000..66f99ac956 --- /dev/null +++ b/board/at91sam9263ek/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := at91sam9263ek.o flash.o dm9161a.o nand.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/at91sam9263ek/at91sam9263ek.c b/board/at91sam9263ek/at91sam9263ek.c new file mode 100644 index 0000000000..05195adc01 --- /dev/null +++ b/board/at91sam9263ek/at91sam9263ek.c @@ -0,0 +1,224 @@ +/* + * (C) Copyright 2006 + * M. Amine SAYA ATEML Rousset, France. + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger@sysgo.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/hardware.h> + +#include <net.h> + +/* ------------------------------------------------------------------------- */ +/* + * Miscelaneous platform dependent initialisations + */ +int board_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* Enable Ctrlc */ + console_init_f (); + + /* Enable clocks for SMC */ + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SYS; + + /* memory and cpu-speed are setup before relocation */ + /* so we do _nothing_ here */ + +#ifdef CONFIG_LCD + gd->fb_base = (unsigned long) AT91C_IRAM; +#endif + + /* arch number of AT91SAM9263EK-Board */ + gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK; + /* adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + + +int dram_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM; + gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + return 0; +} + +int board_late_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* Fix Ethernet Initialization Bug when starting Linux from U-Boot */ +#if (CONFIG_COMMANDS & CFG_CMD_NET) + eth_init(gd->bd); +#endif + + return 0; +} + + +void hw_flash_init(void){ + + /* Configure SMC CS0 for parallel flash */ + AT91C_BASE_SMC0->SMC_SETUP0 = (AT91C_FLASH_NWE_SETUP | AT91C_FLASH_NCS_WR_SETUP | + AT91C_FLASH_NRD_SETUP | AT91C_FLASH_NCS_RD_SETUP); + + AT91C_BASE_SMC0->SMC_PULSE0 = (AT91C_FLASH_NWE_PULSE | AT91C_FLASH_NCS_WR_PULSE | + AT91C_FLASH_NRD_PULSE | AT91C_FLASH_NCS_RD_PULSE); + + AT91C_BASE_SMC0->SMC_CYCLE0 = AT91C_FLASH_NWE_CYCLE | AT91C_FLASH_NRD_CYCLE; + + AT91C_BASE_SMC0->SMC_CTRL0 = (AT91C_SMC_READMODE | AT91C_SMC_WRITEMODE | + AT91C_SMC_NWAITM_NWAIT_DISABLE | AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS | + AT91C_FLASH_TDF); +} + + +int AT91F_Serial_Hardware_Init(void) +{ + +/* DBGU */ +#ifdef CONFIG_DBGU + *AT91C_PIOC_PDR = AT91C_PC31_DTXD | AT91C_PC30_DRXD; /* PA 31 & 30 */ + *AT91C_PMC_PCER = 1 << AT91C_ID_SYS; /* enable clock */ +#endif + +/* USART 0 */ +#ifdef CONFIG_USART0 + *AT91C_PIOA_PDR = AT91C_PA26_TXD0 | AT91C_PA27_RXD0; + *AT91C_PMC_PCER |= 1 << AT91C_ID_US0; /* enable clock */ +#endif + +#ifdef CONFIG_USART1 + *AT91C_PIOD_PDR = AT91C_PD0_TXD1 | AT91C_PD1_RXD1; + *AT91C_PMC_PCER |= 1 << AT91C_ID_US1; /* enable clock */ +#endif + +#ifdef CONFIG_USART2 + *AT91C_PIOD_PDR = AT91C_PD2_TXD2 | AT91C_PD3_RXD2; + *AT91C_PMC_PCER |= 1 << AT91C_ID_US2; /* enable clock */ +#endif + +} + + +#ifdef CONFIG_DRIVER_ETHER +#if (CONFIG_COMMANDS & CFG_CMD_NET) + +extern AT91PS_EMAC p_mac; + +void AT91F_EMAC_Hardware_Init(void) +{ + unsigned int periphAEnable, periphBEnable; + + p_mac = AT91C_BASE_EMAC; + + /* Disable pull-up on: + RXDV (PA17) => PHY normal mode (not Test mode) + + ERX0 (PE25) => PHY ADDR0 + ERX1 (PE26) => PHY ADDR1 + ERX2 (PA25) => PHY ADDR2 + ERX3 (PA26) => PHY ADDR3 + ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0 + + PHY has internal pull-down + */ + AT91C_BASE_PIOC->PIO_PPUDR = AT91C_PC25_E_RXDV; + AT91C_BASE_PIOE->PIO_PPUDR = AT91C_PE25_E_RX0 | AT91C_PE26_E_RX1; + + /* Need to reset PHY -> 500ms reset */ + AT91C_BASE_RSTC->RSTC_RMR = (AT91C_RSTC_KEY & ((unsigned int)0xA5<<24)) | + (AT91C_RSTC_ERSTL & (0x0D << 8)) | AT91C_RSTC_URSTEN; + AT91C_BASE_RSTC->RSTC_RCR = (AT91C_RSTC_KEY & ((unsigned int)0xA5<<24)) | + AT91C_RSTC_EXTRST; + + /* Wait for end hardware reset */ + while (!(AT91C_BASE_RSTC->RSTC_RSR & AT91C_RSTC_NRSTL)); + + /* Re-enable pull-up */ + AT91C_BASE_PIOC->PIO_PPUER = AT91C_PC25_E_RXDV; + AT91C_BASE_PIOE->PIO_PPUER = AT91C_PE25_E_RX0 | AT91C_PE26_E_RX1; + +#ifdef CONFIG_AT91C_USE_RMII + + periphAEnable = 0; + periphBEnable = ((unsigned int) AT91C_PC25_E_RXDV); + + AT91C_BASE_PIOC->PIO_ASR = periphAEnable; + AT91C_BASE_PIOC->PIO_BSR = periphBEnable; + AT91C_BASE_PIOC->PIO_PDR = (periphAEnable | periphBEnable); + + periphAEnable = ((unsigned int) AT91C_PE28_E_TXEN ) | + ((unsigned int) AT91C_PE26_E_RX1 ) | + ((unsigned int) AT91C_PE24_E_TX1 ) | + ((unsigned int) AT91C_PE29_E_MDC ) | + ((unsigned int) AT91C_PE27_E_RXER ) | + ((unsigned int) AT91C_PE23_E_TX0 ) | + ((unsigned int) AT91C_PE25_E_RX0 ) | + ((unsigned int) AT91C_PE21_E_TXCK ) | + ((unsigned int) AT91C_PE30_E_MDIO ); + periphBEnable = 0; + AT91C_BASE_PIOE->PIO_ASR = periphAEnable; + AT91C_BASE_PIOE->PIO_BSR = periphBEnable; + AT91C_BASE_PIOE->PIO_PDR = (periphAEnable | periphBEnable); + +#else + periphAEnable = 0; + periphBEnable = ((unsigned int) AT91C_PC25_E_RXDV) | + ((unsigned int) AT91C_PC20_E_TX2 ) | + ((unsigned int) AT91C_PC24_E_TXER ) | + ((unsigned int) AT91C_PC27_E_RXCK ) | + ((unsigned int) AT91C_PC26_E_COL ) | + ((unsigned int) AT91C_PC21_E_TX3 ) | + ((unsigned int) AT91C_PC22_E_RX2 ) | + ((unsigned int) AT91C_PC23_E_RX3 ); + + AT91C_BASE_PIOC->PIO_ASR = periphAEnable; + AT91C_BASE_PIOC->PIO_BSR = periphBEnable; + AT91C_BASE_PIOC->PIO_PDR = (periphAEnable | periphBEnable); + + periphAEnable = ((unsigned int) AT91C_PE28_E_TXEN ) | + ((unsigned int) AT91C_PE26_E_RX1 ) | + ((unsigned int) AT91C_PE24_E_TX1 ) | + ((unsigned int) AT91C_PE29_E_MDC ) | + ((unsigned int) AT91C_PE27_E_RXER ) | + ((unsigned int) AT91C_PE23_E_TX0 ) | + ((unsigned int) AT91C_PE25_E_RX0 ) | + ((unsigned int) AT91C_PE22_E_CRS ) | + ((unsigned int) AT91C_PE21_E_TXCK ) | + ((unsigned int) AT91C_PE30_E_MDIO ); + periphBEnable = 0; + AT91C_BASE_PIOE->PIO_ASR = periphAEnable; + AT91C_BASE_PIOE->PIO_BSR = periphBEnable; + AT91C_BASE_PIOE->PIO_PDR = (periphAEnable | periphBEnable); +#endif +} + +#endif /* CONFIG_COMMANDS & CFG_CMD_NET */ +#endif /* CONFIG_DRIVER_ETHER */ diff --git a/board/at91sam9263ek/config.mk b/board/at91sam9263ek/config.mk new file mode 100644 index 0000000000..ff2cfd170b --- /dev/null +++ b/board/at91sam9263ek/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0x23f00000 diff --git a/board/at91sam9263ek/dm9161a.c b/board/at91sam9263ek/dm9161a.c new file mode 100644 index 0000000000..63177d29fc --- /dev/null +++ b/board/at91sam9263ek/dm9161a.c @@ -0,0 +1,300 @@ +/* + * (C) Copyright 2003 + * Author : Hamid Ikdoumi (Atmel) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <at91_net.h> +#include <net.h> +#include <dm9161.h> + +#ifdef CONFIG_DRIVER_ETHER + +#if (CONFIG_COMMANDS & CFG_CMD_NET) + +/* + * Name: + * dm9161a_IsPhyConnected + * Description: + * Reads the 2 PHY ID registers + * Arguments: + * p_mac - pointer to AT91S_EMAC struct + * Return value: + * TRUE - if id read successfully + * FALSE- if error + */ +static unsigned int dm9161a_IsPhyConnected (AT91PS_EMAC p_mac) +{ + unsigned short Id1, Id2; + + at91_EmacEnableMDIO (p_mac); + at91_EmacReadPhy (p_mac, SAM9263EK_PHY_ADDRESS, DM9161_PHYID1, &Id1); + at91_EmacReadPhy (p_mac, SAM9263EK_PHY_ADDRESS, DM9161_PHYID2, &Id2); + at91_EmacDisableMDIO (p_mac); + + if ((Id1 == (DM9161_PHYID1_OUI >> 6)) && + ((Id2 >> 10) == (DM9161_PHYID1_OUI & DM9161_LSB_MASK))) { + printf("DM9161A PHY Detected\n\r"); + return TRUE; + } + + return FALSE; +} + +/* + * Name: + * dm9161a_GetLinkSpeed + * Description: + * Link parallel detection status of MAC is checked and set in the + * MAC configuration registers + * Arguments: + * p_mac - pointer to MAC + * Return value: + * TRUE - if link status set succesfully + * FALSE - if link status not set + */ +static uchar dm9161a_GetLinkSpeed (AT91PS_EMAC p_mac) +{ + unsigned short stat1, stat2; + + if (!at91_EmacReadPhy (p_mac, SAM9263EK_PHY_ADDRESS, DM9161_BMSR, &stat1)) + return FALSE; + + if (!(stat1 & DM9161_LINK_STATUS)) /* link status up? */ + return FALSE; + + if (!at91_EmacReadPhy (p_mac, SAM9263EK_PHY_ADDRESS, DM9161_DSCSR, &stat2)) + return FALSE; + + if ((stat1 & DM9161_100BASE_TX_FD) && (stat2 & DM9161_100FDX)) { + /*set Emac for 100BaseTX and Full Duplex */ + p_mac->EMAC_NCFGR |= AT91C_EMAC_SPD | AT91C_EMAC_FD; + return TRUE; + } + + if ((stat1 & DM9161_10BASE_T_FD) && (stat2 & DM9161_10FDX)) { + /*set MII for 10BaseT and Full Duplex */ + p_mac->EMAC_NCFGR = (p_mac->EMAC_NCFGR & + ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) + | AT91C_EMAC_FD; + return TRUE; + } + + if ((stat1 & DM9161_100BASE_T4_HD) && (stat2 & DM9161_100HDX)) { + /*set MII for 100BaseTX and Half Duplex */ + p_mac->EMAC_NCFGR = (p_mac->EMAC_NCFGR & + ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) + | AT91C_EMAC_SPD; + return TRUE; + } + + if ((stat1 & DM9161_10BASE_T_HD) && (stat2 & DM9161_10HDX)) { + /*set MII for 10BaseT and Half Duplex */ + p_mac->EMAC_NCFGR &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD); + return TRUE; + } + + return FALSE; +} + + +/* + * Name: + * dm9161a_ResetPhy + * Description: + * Resets PHY + * Arguments: + * p_mac - pointer to struct AT91S_EMAC + * Return value: + * TRUE - if link status set succesfully + * FALSE - if link status not set + */ +static uchar dm9161a_ResetPhy(AT91PS_EMAC p_mac) +{ + unsigned short bmcr; + int timeout = 10; + uchar ret = TRUE; + + + bmcr = DM9161_RESET; + at91_EmacEnableMDIO (p_mac); + at91_EmacWritePhy (p_mac, SAM9263EK_PHY_ADDRESS, DM9161_BMCR, &bmcr); + + do { + at91_EmacReadPhy (p_mac, SAM9263EK_PHY_ADDRESS, DM9161_BMCR, &bmcr); + timeout--; + } while ((bmcr & DM9161_RESET) && timeout); + + at91_EmacDisableMDIO (p_mac); + + if (!timeout) + ret = FALSE; + + return ret; +} + + +/* + * Name: + * dm9161a_InitPhy + * Description: + * MAC starts checking its link by using parallel detection and + * Autonegotiation and the same is set in the MAC configuration registers + * Arguments: + * p_mac - pointer to struct AT91S_EMAC + * Return value: + * TRUE - if link status set succesfully + * FALSE - if link status not set + */ +static uchar dm9161a_InitPhy (AT91PS_EMAC p_mac) +{ + unsigned int tick = 0; + unsigned short IntValue; + uchar ret = TRUE; + + at91_EmacEnableMDIO (p_mac); + + do { + /* Link status is latched, so read twice to get current value */ + at91_EmacReadPhy(p_mac, AT91C_PHY_ADDR, DM9161_BMSR, &IntValue); + at91_EmacReadPhy(p_mac, AT91C_PHY_ADDR, DM9161_BMSR, &IntValue); + + tick++; + } while (!(IntValue & DM9161_LINK_STATUS) && (tick < AT91C_ETH_TIMEOUT)); + + if (!(IntValue & DM9161_LINK_STATUS)){ + at91_EmacDisableMDIO (p_mac); + printf ("No link\n\r"); + ret = FALSE; + return ret; + } + + if (!dm9161a_GetLinkSpeed (p_mac)) { + /* Try another time */ + ret = dm9161a_GetLinkSpeed (p_mac); + } + + /* Disable PHY Interrupts */ + at91_EmacReadPhy (p_mac, SAM9263EK_PHY_ADDRESS, DM9161_MDINTR, &IntValue); + /* clear FDX, SPD, Link, INTR masks */ + IntValue &= ~(DM9161_FDX_MASK | DM9161_SPD_MASK | + DM9161_LINK_MASK | DM9161_INTR_MASK); + at91_EmacWritePhy (p_mac, SAM9263EK_PHY_ADDRESS, DM9161_MDINTR, &IntValue); + at91_EmacDisableMDIO (p_mac); + + return (ret); +} + + +/* + * Name: + * dm9161a_AutoNegotiate + * Description: + * MAC Autonegotiates with the partner status of same is set in the + * MAC configuration registers + * Arguments: + * dev - pointer to struct net_device + * Return value: + * TRUE - if link status set successfully + * FALSE - if link status not set + */ +static uchar dm9161a_AutoNegotiate (AT91PS_EMAC p_mac, int *status) +{ + unsigned short value; + unsigned short PhyAnar; + unsigned short PhyAnalpar; + + /* Set dm9161 control register */ + if (!at91_EmacReadPhy (p_mac, SAM9263EK_PHY_ADDRESS, DM9161_BMCR, &value)) + return FALSE; + value &= ~DM9161_AUTONEG; /* remove autonegotiation enable */ + value |= DM9161_ISOLATE; /* Electrically isolate PHY */ + if (!at91_EmacWritePhy (p_mac, SAM9263EK_PHY_ADDRESS, DM9161_BMCR, &value)) + return FALSE; + + /* Set the Auto_negotiation Advertisement Register */ + /* MII advertising for Next page, 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3 */ + PhyAnar = DM9161_NP | DM9161_TX_FDX | DM9161_TX_HDX | + DM9161_10_FDX | DM9161_10_HDX | DM9161_AN_IEEE_802_3; + if (!at91_EmacWritePhy (p_mac, SAM9263EK_PHY_ADDRESS, DM9161_ANAR, &PhyAnar)) + return FALSE; + + /* Read the Control Register */ + if (!at91_EmacReadPhy (p_mac, SAM9263EK_PHY_ADDRESS, DM9161_BMCR, &value)) + return FALSE; + + value |= DM9161_SPEED_SELECT | DM9161_AUTONEG | DM9161_DUPLEX_MODE; + if (!at91_EmacWritePhy (p_mac, SAM9263EK_PHY_ADDRESS, DM9161_BMCR, &value)) + return FALSE; + /* Restart Auto_negotiation */ + value |= DM9161_RESTART_AUTONEG; + if (!at91_EmacWritePhy (p_mac, SAM9263EK_PHY_ADDRESS, DM9161_BMCR, &value)) + return FALSE; + + /*check AutoNegotiate complete */ + udelay (10000); + at91_EmacReadPhy (p_mac, SAM9263EK_PHY_ADDRESS, DM9161_BMSR, &value); + if (!(value & DM9161_AUTONEG_COMP)) + return FALSE; + + /* Get the AutoNeg Link partner base page */ + if (!at91_EmacReadPhy (p_mac, SAM9263EK_PHY_ADDRESS, DM9161_ANLPAR, &PhyAnalpar)) + return FALSE; + + if ((PhyAnar & DM9161_TX_FDX) && (PhyAnalpar & DM9161_TX_FDX)) { + /*set MII for 100BaseTX and Full Duplex */ + p_mac->EMAC_NCFGR |= AT91C_EMAC_SPD | AT91C_EMAC_FD; + return TRUE; + } + + if ((PhyAnar & DM9161_10_FDX) && (PhyAnalpar & DM9161_10_FDX)) { + /*set MII for 10BaseT and Full Duplex */ + p_mac->EMAC_NCFGR = (p_mac->EMAC_NCFGR & + ~(AT91C_EMAC_SPD | AT91C_EMAC_FD)) + | AT91C_EMAC_FD; + return TRUE; + } + return FALSE; +} + + +/* + * Name: + * at91_GetPhyInterface + * Description: + * Initialise the interface functions to the PHY + * Arguments: + * None + * Return value: + * None + */ +void at91_GetPhyInterface(AT91PS_PhyOps p_phyops) +{ + p_phyops->Init = dm9161a_InitPhy; + p_phyops->IsPhyConnected = dm9161a_IsPhyConnected; + p_phyops->GetLinkSpeed = dm9161a_GetLinkSpeed; + p_phyops->AutoNegotiate = dm9161a_AutoNegotiate; + p_phyops->Reset = dm9161a_ResetPhy; +} + +#endif /* CONFIG_COMMANDS & CFG_CMD_NET */ + +#endif /* CONFIG_DRIVER_ETHER */ + diff --git a/board/at91sam9263ek/flash.c b/board/at91sam9263ek/flash.c new file mode 100644 index 0000000000..9e05b47d8e --- /dev/null +++ b/board/at91sam9263ek/flash.c @@ -0,0 +1,567 @@ +/* + * (C) Copyright 2002 + * Lineo, Inc. <www.lineo.com> + * Bernhard Kuhn <bkuhn@lineo.com> + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Alex Zuepke <azu@sysgo.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#ifndef CFG_NO_FLASH +ulong myflush(void); + + +/* Flash Organization Structure */ +typedef struct OrgDef +{ + unsigned int sector_number; + unsigned int sector_size; +} OrgDef; + + +/* Flash Organizations */ +OrgDef OrgAT49BV16x4[] = +{ + { 8, 8*1024 }, /* 8 * 8 kBytes sectors */ + { 2, 32*1024 }, /* 2 * 32 kBytes sectors */ + { 30, 64*1024 }, /* 30 * 64 kBytes sectors */ +}; + +OrgDef OrgAT49BV16x4A[] = +{ + { 8, 8*1024 }, /* 8 * 8 kBytes sectors */ + { 31, 64*1024 }, /* 31 * 64 kBytes sectors */ +}; + +OrgDef OrgAT49BV6416[] = +{ + { 8, 8*1024 }, /* 8 * 8 kBytes sectors */ + { 127, 64*1024 }, /* 127 * 64 kBytes sectors */ +}; + +OrgDef OrgAT49BV322A[] = +{ + { 8, 8*1024 }, /* 8 * 8 kBytes sectors */ + { 63, 64*1024 }, /* 63 * 64 kBytes sectors */ +}; + +/* AMD/Spansion S29JL032H is the same as AM29DL323GB */ +OrgDef OrgS29JL032H[] = +{ + { 8, 8*1024 }, + { 63, 64*1024 }, +}; + + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; + +/* AT49BV1614A Codes */ +#define FLASH_CODE1 0xAA +#define FLASH_CODE2 0x55 +#define ID_IN_CODE 0x90 +#define ID_OUT_CODE 0xF0 + + +#define CMD_READ_ARRAY 0x00F0 +#define CMD_UNLOCK1 0x00AA +#define CMD_UNLOCK2 0x0055 +#define CMD_ERASE_SETUP 0x0080 +#define CMD_ERASE_CONFIRM 0x0030 +#define CMD_PROGRAM 0x00A0 +#define CMD_UNLOCK_BYPASS 0x0020 +#define CMD_SECTOR_UNLOCK 0x0070 + +#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00005555<<1))) +#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CFG_FLASH_BASE + (0x00002AAA<<1))) + +#define BIT_ERASE_DONE 0x0080 +#define BIT_RDY_MASK 0x0080 +#define BIT_PROGRAM_ERROR 0x0020 +#define BIT_TIMEOUT 0x80000000 /* our flag */ + +#define READY 1 +#define ERR 2 +#define TMO 4 + +/*----------------------------------------------------------------------- + */ +void flash_identification (flash_info_t * info) +{ + volatile u16 manuf_code, device_code, add_device_code; + char *manuf_name, *device_name; + + MEM_FLASH_ADDR1 = FLASH_CODE1; + MEM_FLASH_ADDR2 = FLASH_CODE2; + MEM_FLASH_ADDR1 = ID_IN_CODE; + + manuf_code = *(volatile u16 *) CFG_FLASH_BASE; + device_code = *(volatile u16 *) (CFG_FLASH_BASE + 2); + add_device_code = *(volatile u16 *) (CFG_FLASH_BASE + (3 << 1)); + + MEM_FLASH_ADDR1 = FLASH_CODE1; + MEM_FLASH_ADDR2 = FLASH_CODE2; + MEM_FLASH_ADDR1 = ID_OUT_CODE; + + /* Get the manufacturer code (Is is in 32 bits but mirrored. Only 16 bits, MSB or LSB, count) + info->flash_id contains manuf_code in 16 MSB bits and device_code in 16 LSB bits. */ + info->flash_id = (manuf_code << 16) | manuf_code; + + switch(info->flash_id) { + case ATM_MANUFACT : + manuf_name = "ATMEL"; + + /* Reset 16 LSB bits to store device_code. */ + info->flash_id &= ~FLASH_TYPEMASK; + + if (device_code == (ATM_ID_BV1614 & FLASH_TYPEMASK)) { + + if (add_device_code == (ATM_ID_BV1614A & FLASH_TYPEMASK)) { + info->flash_id |= ATM_ID_BV1614A & FLASH_TYPEMASK; + device_name = "AT49BV1614A (16Mbit)"; + } else { /* AT49BV1614 Flash */ + info->flash_id |= ATM_ID_BV1614 & FLASH_TYPEMASK; + device_name = "AT49BV1614 (16Mbit)"; + } + + } else if (device_code == (ATM_ID_BV6416 & FLASH_TYPEMASK)) { + info->flash_id |= ATM_ID_BV6416 & FLASH_TYPEMASK; + device_name = "AT49BV6416 (64Mbit)"; + } else if (device_code == (ATM_ID_BV322A & FLASH_TYPEMASK)) { + info->flash_id |= ATM_ID_BV322A & FLASH_TYPEMASK; + device_name = "AT49BV322A (32Mbit)"; + } + + break; + + case AMD_MANUFACT : + manuf_name = "AMD"; + + /* Reset 16 LSB bits to store device_code. */ + info->flash_id &= ~FLASH_TYPEMASK; + + if (device_code == (AMD_ID_DL323B & FLASH_TYPEMASK)) { + info->flash_id |= AMD_ID_DL323B & FLASH_TYPEMASK; + device_name = "AM29DL323B (S29JL032H)"; + } + + break; + + default: + manuf_name = "No Manufacturer detected"; + device_name = "No Flash chip detected"; + + break; + } + + printf ("%s : %s\n", manuf_name, device_name); +} + +ushort flash_number_sector(OrgDef *pOrgDef, unsigned int nb_blocks) +{ + int i, nb_sectors = 0; + + for (i=0; i<nb_blocks; i++){ + nb_sectors += pOrgDef[i].sector_number; + } + + return nb_sectors; +} + +void flash_unlock_sector(flash_info_t * info, unsigned int sector) +{ + volatile u16 *addr = (volatile u16 *) (info->start[sector]); + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + *addr = CMD_SECTOR_UNLOCK; +} + + +ulong flash_init (void) +{ + int i, j, k; + unsigned int flash_nb_blocks, sector; + unsigned int start_address; + OrgDef *pOrgDef; + + ulong size = 0; + + /* Perform hardware init for flash (SMC CS0 init) + This function is declared in board dependent files */ + hw_flash_init(); + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + ulong flashbase = 0; + + flash_identification (&flash_info[i]); + + if ((flash_info[i].flash_id & FLASH_TYPEMASK) == + (ATM_ID_BV1614 & FLASH_TYPEMASK)) { + + pOrgDef = OrgAT49BV16x4; + flash_nb_blocks = sizeof (OrgAT49BV16x4) / sizeof (OrgDef); + } else if ((flash_info[i].flash_id & FLASH_TYPEMASK) == + (ATM_ID_BV322A & FLASH_TYPEMASK)){ /* AT49BV322A Flash */ + + pOrgDef = OrgAT49BV322A; + flash_nb_blocks = sizeof (OrgAT49BV322A) / sizeof (OrgDef); + } else if ((flash_info[i].flash_id & FLASH_TYPEMASK) == + (ATM_ID_BV6416 & FLASH_TYPEMASK)){ /* AT49BV6416 Flash */ + + pOrgDef = OrgAT49BV6416; + flash_nb_blocks = sizeof (OrgAT49BV6416) / sizeof (OrgDef); + } else if ((flash_info[i].flash_id & FLASH_TYPEMASK) == + (AMD_ID_DL323B & FLASH_TYPEMASK)){ /* S29JL032H (ex AM29DL323GB) Flash */ + + pOrgDef = OrgS29JL032H; + flash_nb_blocks = sizeof (OrgS29JL032H) / sizeof (OrgDef); + } else { + flash_nb_blocks = 0; + pOrgDef = OrgAT49BV16x4; + } + + flash_info[i].sector_count = flash_number_sector(pOrgDef, flash_nb_blocks); + memset (flash_info[i].protect, 0, flash_info[i].sector_count); + + if (i == 0) + flashbase = PHYS_FLASH_1; + else + panic ("configured too many flash banks!\n"); + + sector = 0; + start_address = flashbase; + flash_info[i].size = 0; + + for (j = 0; j < flash_nb_blocks; j++) { + for (k = 0; k < pOrgDef[j].sector_number; k++) { + flash_info[i].start[sector++] = start_address; + start_address += pOrgDef[j].sector_size; + flash_info[i].size += pOrgDef[j].sector_size; + } + } + + size += flash_info[i].size; + + if (((flash_info[i].flash_id & FLASH_TYPEMASK) == (ATM_ID_BV6416 & FLASH_TYPEMASK))) + { /* AT49BV6416 Flash */ + + /* Unlock all sectors at reset */ + for (j = 0; j < flash_info[i].sector_count; j++){ + flash_unlock_sector(&flash_info[i], j); + } + } + } + + /* Protect binary boot image */ + flash_protect (FLAG_PROTECT_SET, + CFG_FLASH_BASE, + CFG_FLASH_BASE + CFG_BOOT_SIZE - 1, &flash_info[0]); + + /* Protect environment variables */ + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]); + + /* Protect U-Boot gzipped image */ + flash_protect (FLAG_PROTECT_SET, + CFG_U_BOOT_BASE, + CFG_U_BOOT_BASE + CFG_U_BOOT_SIZE - 1, &flash_info[0]); + + return size; +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + switch (info->flash_id & FLASH_VENDMASK) { + case (ATM_MANUFACT & FLASH_VENDMASK): + printf ("Atmel: "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case (ATM_ID_BV1614 & FLASH_TYPEMASK): + printf ("AT49BV1614 (16Mbit)\n"); + break; + case (ATM_ID_BV322A & FLASH_TYPEMASK): + printf ("AT49BV322A (32Mbit)\n"); + break; + case (ATM_ID_BV6416 & FLASH_TYPEMASK): + printf ("AT49BV6416 (64Mbit)\n"); + break; + default: + printf ("Unknown Chip Type\n"); + goto Done; + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; i++) { + if ((i % 5) == 0) { + printf ("\n "); + } + printf (" %08lX%s", info->start[i], + info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + +Done: ; +} + +/*----------------------------------------------------------------------- + */ + +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + ulong result; + int iflag, cflag, prot, sect; + int rc = ERR_OK; + int chip1; + + /* first look for protection bits */ + + if (info->flash_id == FLASH_UNKNOWN) + return ERR_UNKNOWN_FLASH_TYPE; + + if ((s_first < 0) || (s_first > s_last)) { + return ERR_INVAL; + } + + if ((info->flash_id & FLASH_VENDMASK) != + (ATM_MANUFACT & FLASH_VENDMASK)) { + return ERR_UNKNOWN_FLASH_VENDOR; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + if (prot) + return ERR_PROTECTED; + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + cflag = icache_status (); + icache_disable (); + iflag = disable_interrupts (); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { + printf ("Erasing sector %2d ... ", sect); + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + if (info->protect[sect] == 0) { /* not protected */ + volatile u16 *addr = (volatile u16 *) (info->start[sect]); + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + *addr = CMD_ERASE_CONFIRM; + + /* wait until flash is ready */ + chip1 = 0; + + do { + result = *addr; + + /* check timeout */ + if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + MEM_FLASH_ADDR1 = CMD_READ_ARRAY; + chip1 = TMO; + break; + } + + /* printf("flash_erase : TIMEOUT = %d\n\r", get_timer_masked() / CFG_HZ); */ + if (!chip1 && (result & 0xFFFF) & BIT_ERASE_DONE) + chip1 = READY; + + } while (!chip1); + + MEM_FLASH_ADDR1 = CMD_READ_ARRAY; + + if (chip1 == ERR) { + rc = ERR_PROG_ERROR; + goto outahere; + } + if (chip1 == TMO) { + rc = ERR_TIMOUT; + goto outahere; + } + + printf ("ok.\n"); + } else { /* it was protected */ + printf ("protected!\n"); + } + } + + if (ctrlc ()) + printf ("User Interrupt!\n"); + +outahere: + /* allow flash to settle - wait 10 ms */ + udelay_masked (10000); + + if (iflag) + enable_interrupts (); + + if (cflag) + icache_enable (); + + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash + */ + +volatile static int write_word (flash_info_t * info, ulong dest, + ulong data) +{ + volatile u16 *addr = (volatile u16 *) dest; + ulong result; + int rc = ERR_OK; + int cflag, iflag; + int chip1; + + /* + * Check if Flash is (sufficiently) erased + */ + result = *addr; + if ((result & data) != data) + return ERR_NOT_ERASED; + + + /* + * Disable interrupts which might cause a timeout + * here. Remember that our exception vectors are + * at address 0 in the flash, and we don't want a + * (ticker) exception to happen while the flash + * chip is in programming mode. + */ + cflag = icache_status (); + icache_disable (); + iflag = disable_interrupts (); + + MEM_FLASH_ADDR1 = CMD_UNLOCK1; + MEM_FLASH_ADDR2 = CMD_UNLOCK2; + MEM_FLASH_ADDR1 = CMD_PROGRAM; + *addr = data; + + /* arm simple, non interrupt dependent timer */ + reset_timer_masked (); + + /* wait until flash is ready */ + chip1 = 0; + do { + result = *addr; + + /* check timeout */ + if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) { + chip1 = ERR | TMO; + break; + } + if (!chip1 && ((result & 0x80) == (data & 0x80))) + chip1 = READY; + + } while (!chip1); + + *addr = CMD_READ_ARRAY; + + if (chip1 == ERR || *addr != data) + rc = ERR_PROG_ERROR; + + if (iflag) + enable_interrupts (); + + if (cflag) + icache_enable (); + + return rc; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash. + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong wp, data; + int rc; + + if (addr & 1) { + printf ("unaligned destination not supported\n"); + return ERR_ALIGN; + }; + + if ((int) src & 1) { + printf ("unaligned source not supported\n"); + return ERR_ALIGN; + }; + + wp = addr; + + while (cnt >= 2) { + data = *((volatile u16 *) src); + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + src += 2; + wp += 2; + cnt -= 2; + } + + if (cnt == 1) { + data = (*((volatile u8 *) src)) | (*((volatile u8 *) (wp + 1)) << + 8); + if ((rc = write_word (info, wp, data)) != 0) { + return (rc); + } + src += 1; + wp += 1; + cnt -= 1; + }; + + return ERR_OK; +} +#endif diff --git a/board/at91sam9263ek/nand.c b/board/at91sam9263ek/nand.c new file mode 100644 index 0000000000..96c15058c1 --- /dev/null +++ b/board/at91sam9263ek/nand.c @@ -0,0 +1,107 @@ +/* + * (C) Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/hardware.h> + +#if (CONFIG_COMMANDS & CFG_CMD_NAND) + +#include <nand.h> + +/* + * hardware specific access to control-lines + */ +#define MASK_ALE (1 << 21) /* our ALE is AD21 */ +#define MASK_CLE (1 << 22) /* our CLE is AD22 */ + +/* + * Disk On Chip (NAND) Millenium initialization. + * The NAND lives in the CS3 space + */ +void at91sam9263ek_nand_init (struct nand_chip *nand) +{ + /* Setup Smart Media, first enable the address range of CS3 in HMATRIX user interface */ + AT91C_BASE_MATRIX->MATRIX_EBI0 |= AT91C_MATRIX_CS3A_SM; + + /* Configure SMC CS3 */ + AT91C_BASE_SMC0->SMC_SETUP3 = (AT91C_SM_NWE_SETUP | AT91C_SM_NCS_WR_SETUP | + AT91C_SM_NRD_SETUP | AT91C_SM_NCS_RD_SETUP); + + AT91C_BASE_SMC0->SMC_PULSE3 = (AT91C_SM_NWE_PULSE | AT91C_SM_NCS_WR_PULSE | AT91C_SM_NRD_PULSE | AT91C_SM_NCS_RD_PULSE); + + AT91C_BASE_SMC0->SMC_CYCLE3 = (AT91C_SM_NWE_CYCLE | AT91C_SM_NRD_CYCLE); + + if ((nand->options & NAND_BUSWIDTH_16) == NAND_BUSWIDTH_16) + { + AT91C_BASE_SMC0->SMC_CTRL3 = (AT91C_SMC_READMODE | AT91C_SMC_WRITEMODE | AT91C_SMC_NWAITM_NWAIT_DISABLE | + AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS | AT91C_SM_TDF); + } else { + AT91C_BASE_SMC0->SMC_CTRL3 = (AT91C_SMC_READMODE | AT91C_SMC_WRITEMODE | AT91C_SMC_NWAITM_NWAIT_DISABLE | + AT91C_SMC_DBW_WIDTH_EIGTH_BITS | AT91C_SM_TDF); + } + + /* Configure RDY/BSY input signal */ + AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOA; + + AT91C_BASE_PIOA->PIO_ODR = AT91C_PIO_PA22; + AT91C_BASE_PIOA->PIO_PER = AT91C_PIO_PA22; + + AT91C_BASE_PIOA->PIO_PPUER = AT91C_PIO_PA22; /* Enable pull-up */ + + /* Enable NandFlash */ + AT91C_BASE_PIOD->PIO_PER = AT91C_PIO_PD15; + AT91C_BASE_PIOD->PIO_OER = AT91C_PIO_PD15; +} + +static void at91sam9263ek_nand_hwcontrol(struct mtd_info *mtd, int cmd) +{ + struct nand_chip *this = mtd->priv; + ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; + + IO_ADDR_W &= ~(MASK_ALE|MASK_CLE); + switch (cmd) { + case NAND_CTL_SETCLE: IO_ADDR_W |= MASK_CLE; break; + case NAND_CTL_SETALE: IO_ADDR_W |= MASK_ALE; break; + case NAND_CTL_CLRNCE: *AT91C_PIOD_SODR = AT91C_PIO_PD15; break; + case NAND_CTL_SETNCE: *AT91C_PIOD_CODR = AT91C_PIO_PD15; break; + } + this->IO_ADDR_W = (void *) IO_ADDR_W; +} + +/* + * chip R/B detection + */ +static int at91sam9263ek_nand_ready(struct mtd_info *mtd) +{ + return (*AT91C_PIOA_PDSR & AT91C_PIO_PA22); +} + +void board_nand_init(struct nand_chip *nand) +{ + nand->eccmode = NAND_ECC_SOFT; + nand->hwcontrol = at91sam9263ek_nand_hwcontrol; + nand->dev_ready = at91sam9263ek_nand_ready; + nand->chip_delay = 18; + + at91sam9263ek_nand_init(nand); +} +#endif diff --git a/board/at91sam9263ek/u-boot.lds b/board/at91sam9263ek/u-boot.lds new file mode 100644 index 0000000000..d965a03813 --- /dev/null +++ b/board/at91sam9263ek/u-boot.lds @@ -0,0 +1,55 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} |