diff options
Diffstat (limited to 'board/LaCie/wireless_space/kwbimage.cfg')
| -rw-r--r-- | board/LaCie/wireless_space/kwbimage.cfg | 71 |
1 files changed, 0 insertions, 71 deletions
diff --git a/board/LaCie/wireless_space/kwbimage.cfg b/board/LaCie/wireless_space/kwbimage.cfg deleted file mode 100644 index 037248b3c6..0000000000 --- a/board/LaCie/wireless_space/kwbimage.cfg +++ /dev/null @@ -1,71 +0,0 @@ -# -# Copyright (C) 2012 Albert ARIBAUD <albert.u.boot@aribaud.net> -# -# Based on netspace_v2 kwbimage.cfg: -# Copyright (C) 2011 Simon Guinot <sguinot@lacie.com> -# -# Based on Kirkwood support: -# (C) Copyright 2009 -# Marvell Semiconductor <www.marvell.com> -# Written-by: Prafulla Wadaskar <prafulla@marvell.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# -# Refer doc/README.kwbimage for more details about how-to configure -# and create kirkwood boot image -# - -# Boot Media configurations -BOOT_FROM nand # Boot from NAND flash -NAND_PAGE_SIZE 800 - -# SOC registers configuration using bootrom header extension -# Maximum KWBIMAGE_MAX_CONFIG configurations allowed - -# Values taken from image original LaCie U-Boot header dump! - -# Configure RGMII-0 interface pad voltage to 1.8V -DATA 0xFFD100e0 0x1B1B1B9B - -#Dram initalization for SINGLE x16 CL=5 @ 400MHz -DATA 0xFFD01400 0x43000c30 # DDR Configuration register - -DATA 0xFFD01404 0x37743000 # DDR Controller Control Low - -DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1) - -DATA 0xFFD0140C 0x00000A19 # DDR Timing (High) - -DATA 0xFFD01410 0x0000CCCC # DDR Address Control - -DATA 0xFFD01414 0x00000000 # DDR Open Pages Control - -DATA 0xFFD01418 0x00000000 # DDR Operation - -DATA 0xFFD0141C 0x00000662 # DDR Mode - -DATA 0xFFD01420 0x00000004 # DDR Extended Mode - -DATA 0xFFD01424 0x0000F07F # DDR Controller Control High - -DATA 0xFFD01428 0x00096630 # DDR2 ODT Read Timing (default values) - -DATA 0xFFD0147C 0x00009663 # DDR2 ODT Write Timing (default values) - -DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size -DATA 0xFFD01508 0x00000000 # CS[1]n Base address to 0x0 -DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled -DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled -DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled -DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low) -DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) -DATA 0xFFD0149C 0x0000E40F # CPU ODT Control -DATA 0xFFD01480 0x00000001 # DDR Initialization Control -DATA 0xFFD20134 0x66666666 -DATA 0xFFD20138 0x66666666 -DATA 0xFFD10000 0x01112222 -DATA 0xFFD1000C 0x00000000 -DATA 0xFFD10104 0x00000000 -DATA 0xFFD10100 0x40000000 -# End of Header extension -DATA 0x0 0x0 |