diff options
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/Kconfig | 83 | ||||
-rw-r--r-- | arch/arm/cpu/arm11/cpu.c | 5 | ||||
-rw-r--r-- | arch/arm/cpu/arm926ejs/cache.c | 5 | ||||
-rw-r--r-- | arch/arm/cpu/pxa/cache.c | 5 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-armada100/config.h | 2 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-fsl-layerscape/config.h | 2 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-ls102xa/config.h | 2 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-mx5/imx-regs.h | 2 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-mx6/imx-regs.h | 6 | ||||
-rw-r--r-- | arch/arm/include/asm/arch-mx7/imx-regs.h | 2 | ||||
-rw-r--r-- | arch/arm/include/asm/cache.h | 11 | ||||
-rw-r--r-- | arch/arm/lib/cache-cp15.c | 18 | ||||
-rw-r--r-- | arch/arm/lib/cache.c | 4 | ||||
-rw-r--r-- | arch/arm/mach-kirkwood/include/mach/config.h | 2 | ||||
-rw-r--r-- | arch/arm/mach-mvebu/include/mach/config.h | 2 | ||||
-rw-r--r-- | arch/arm/mach-uniphier/Kconfig | 1 | ||||
-rw-r--r-- | arch/arm/mach-uniphier/dram/cmd_ddrmphy.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-uniphier/dram/cmd_ddrphy.c | 2 |
18 files changed, 79 insertions, 77 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index aef901c3f4..c871eaf4e3 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -7,62 +7,73 @@ config SYS_ARCH config ARM64 bool select PHYS_64BIT + select SYS_CACHE_SHIFT_6 config DMA_ADDR_T_64BIT bool default y if ARM64 config HAS_VBAR - bool + bool config HAS_THUMB2 - bool + bool config CPU_ARM720T - bool + bool + select SYS_CACHE_SHIFT_5 config CPU_ARM920T - bool + bool + select SYS_CACHE_SHIFT_5 config CPU_ARM926EJS - bool + bool + select SYS_CACHE_SHIFT_5 config CPU_ARM946ES - bool + bool + select SYS_CACHE_SHIFT_5 config CPU_ARM1136 - bool + bool + select SYS_CACHE_SHIFT_5 config CPU_ARM1176 - bool - select HAS_VBAR + bool + select HAS_VBAR + select SYS_CACHE_SHIFT_5 config CPU_V7 - bool - select HAS_VBAR - select HAS_THUMB2 + bool + select HAS_VBAR + select HAS_THUMB2 + select SYS_CACHE_SHIFT_6 config CPU_V7M bool - select HAS_THUMB2 + select HAS_THUMB2 + select SYS_CACHE_SHIFT_5 config CPU_PXA - bool + bool + select SYS_CACHE_SHIFT_5 config CPU_SA1100 - bool + bool + select SYS_CACHE_SHIFT_5 config SYS_CPU - default "arm720t" if CPU_ARM720T - default "arm920t" if CPU_ARM920T - default "arm926ejs" if CPU_ARM926EJS - default "arm946es" if CPU_ARM946ES - default "arm1136" if CPU_ARM1136 - default "arm1176" if CPU_ARM1176 - default "armv7" if CPU_V7 - default "armv7m" if CPU_V7M - default "pxa" if CPU_PXA - default "sa1100" if CPU_SA1100 + default "arm720t" if CPU_ARM720T + default "arm920t" if CPU_ARM920T + default "arm926ejs" if CPU_ARM926EJS + default "arm946es" if CPU_ARM946ES + default "arm1136" if CPU_ARM1136 + default "arm1176" if CPU_ARM1176 + default "armv7" if CPU_V7 + default "armv7m" if CPU_V7M + default "pxa" if CPU_PXA + default "sa1100" if CPU_SA1100 default "armv8" if ARM64 config SYS_ARM_ARCH @@ -79,6 +90,21 @@ config SYS_ARM_ARCH default 4 if CPU_SA1100 default 8 if ARM64 +config SYS_CACHE_SHIFT_5 + bool + +config SYS_CACHE_SHIFT_6 + bool + +config SYS_CACHE_SHIFT_7 + bool + +config SYS_CACHELINE_SIZE + int + default 128 if SYS_CACHE_SHIFT_7 + default 64 if SYS_CACHE_SHIFT_6 + default 32 if SYS_CACHE_SHIFT_5 + config SEMIHOSTING bool "support boot from semihosting" help @@ -372,9 +398,9 @@ config TARGET_RASTABAN select DM_GPIO config TARGET_ETAMIN - bool "Support etamin" - select CPU_V7 - select SUPPORT_SPL + bool "Support etamin" + select CPU_V7 + select SUPPORT_SPL select DM select DM_SERIAL select DM_GPIO @@ -867,6 +893,7 @@ config TARGET_THUNDERX_88XX bool "Support ThunderX 88xx" select ARM64 select OF_CONTROL + select SYS_CACHE_SHIFT_7 endchoice diff --git a/arch/arm/cpu/arm11/cpu.c b/arch/arm/cpu/arm11/cpu.c index 7244c2e7d7..ef32c3f0ab 100644 --- a/arch/arm/cpu/arm11/cpu.c +++ b/arch/arm/cpu/arm11/cpu.c @@ -53,11 +53,6 @@ static void cache_flush(void) } #ifndef CONFIG_SYS_DCACHE_OFF - -#ifndef CONFIG_SYS_CACHELINE_SIZE -#define CONFIG_SYS_CACHELINE_SIZE 32 -#endif - void invalidate_dcache_all(void) { asm volatile("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c index 2119382ab2..02cb24c24f 100644 --- a/arch/arm/cpu/arm926ejs/cache.c +++ b/arch/arm/cpu/arm926ejs/cache.c @@ -8,11 +8,6 @@ #include <common.h> #ifndef CONFIG_SYS_DCACHE_OFF - -#ifndef CONFIG_SYS_CACHELINE_SIZE -#define CONFIG_SYS_CACHELINE_SIZE 32 -#endif - void invalidate_dcache_all(void) { asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0)); diff --git a/arch/arm/cpu/pxa/cache.c b/arch/arm/cpu/pxa/cache.c index 7aba112c71..d26354e1aa 100644 --- a/arch/arm/cpu/pxa/cache.c +++ b/arch/arm/cpu/pxa/cache.c @@ -8,11 +8,6 @@ #include <common.h> #ifndef CONFIG_SYS_DCACHE_OFF - -#ifndef CONFIG_SYS_CACHELINE_SIZE -#define CONFIG_SYS_CACHELINE_SIZE 32 -#endif - void invalidate_dcache_all(void) { /* Flush/Invalidate I cache */ diff --git a/arch/arm/include/asm/arch-armada100/config.h b/arch/arm/include/asm/arch-armada100/config.h index e062da18b1..6ebc759f4b 100644 --- a/arch/arm/include/asm/arch-armada100/config.h +++ b/arch/arm/include/asm/arch-armada100/config.h @@ -16,8 +16,6 @@ #define _ARMD1_CONFIG_H #include <asm/arch/armada100.h> -/* default Dcache Line length for armada100 */ -#define CONFIG_SYS_CACHELINE_SIZE 32 #define CONFIG_SYS_TCLK (14745600) /* NS16550 clk config */ #define CONFIG_SYS_HZ_CLOCK (3250000) /* Timer Freq. 3.25MHZ */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index b0ad4b4626..527998111f 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -36,7 +36,6 @@ #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_FSL_SRDS_2 #define CONFIG_SYS_PAGE_SIZE 0x10000 -#define CONFIG_SYS_CACHELINE_SIZE 64 #ifndef L1_CACHE_BYTES #define L1_CACHE_SHIFT 6 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) @@ -150,7 +149,6 @@ #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #elif defined(CONFIG_FSL_LSCH2) -#define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FSL_SEC_COMPAT 5 #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index d408fe4056..56d8f3247f 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -7,8 +7,6 @@ #ifndef _ASM_ARMV7_LS102XA_CONFIG_ #define _ASM_ARMV7_LS102XA_CONFIG_ -#define CONFIG_SYS_CACHELINE_SIZE 64 - #define OCRAM_BASE_ADDR 0x10000000 #define OCRAM_SIZE 0x00010000 #define OCRAM_BASE_S_ADDR 0x10010000 diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index e73cc07653..3e79fa3224 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -9,8 +9,6 @@ #define ARCH_MXC -#define CONFIG_SYS_CACHELINE_SIZE 64 - #if defined(CONFIG_MX51) #define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */ #define IPU_SOC_BASE_ADDR 0x40000000 diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index ac37e4f8e6..53bf05439d 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -9,12 +9,6 @@ #define ARCH_MXC -#ifdef CONFIG_MX6UL -#define CONFIG_SYS_CACHELINE_SIZE 64 -#else -#define CONFIG_SYS_CACHELINE_SIZE 32 -#endif - #define ROMCP_ARB_BASE_ADDR 0x00000000 #define ROMCP_ARB_END_ADDR 0x000FFFFF diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h index 74917f0e69..d33be313c6 100644 --- a/arch/arm/include/asm/arch-mx7/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7/imx-regs.h @@ -9,8 +9,6 @@ #define ARCH_MXC -#define CONFIG_SYS_CACHELINE_SIZE 64 - #define ROM_SW_INFO_ADDR 0x000001E8 #define ROMCP_ARB_BASE_ADDR 0x00000000 #define ROMCP_ARB_END_ADDR 0x00017FFF diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index 16e65c36a9..5400cbe18f 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -43,14 +43,11 @@ void dram_bank_mmu_setup(int bank); #endif /* - * The current upper bound for ARM L1 data cache line sizes is 64 bytes. We - * use that value for aligning DMA buffers unless the board config has specified - * an alternate cache line size. + * The value of the largest data cache relevant to DMA operations shall be set + * for us in CONFIG_SYS_CACHELINE_SIZE. In some cases this may be a larger + * value than found in the L1 cache but this is OK to use in terms of + * alignment. */ -#ifdef CONFIG_SYS_CACHELINE_SIZE #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE -#else -#define ARCH_DMA_MINALIGN 64 -#endif #endif /* _ASM_CACHE_H */ diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 1121dc3a93..70e94f03a4 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -61,7 +61,12 @@ __weak void mmu_page_table_flush(unsigned long start, unsigned long stop) void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, enum dcache_option option) { +#ifdef CONFIG_ARMV7_LPAE + u64 *page_table = (u64 *)gd->arch.tlb_addr; +#else u32 *page_table = (u32 *)gd->arch.tlb_addr; +#endif + unsigned long startpt, stoppt; unsigned long upto, end; end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT; @@ -70,7 +75,18 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, option); for (upto = start; upto < end; upto++) set_section_dcache(upto, option); - mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]); + + /* + * Make sure range is cache line aligned + * Only CPU maintains page tables, hence it is safe to always + * flush complete cache lines... + */ + + startpt = (unsigned long)&page_table[start]; + startpt &= ~(CONFIG_SYS_CACHELINE_SIZE - 1); + stoppt = (unsigned long)&page_table[end]; + stoppt = ALIGN(stoppt, CONFIG_SYS_CACHELINE_SIZE); + mmu_page_table_flush(startpt, stoppt); } __weak void dram_bank_mmu_setup(int bank) diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index d330b09434..4f72f8914c 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -10,10 +10,6 @@ #include <common.h> #include <malloc.h> -#ifndef CONFIG_SYS_CACHELINE_SIZE -#define CONFIG_SYS_CACHELINE_SIZE 32 -#endif - /* * Flush range from all levels of d-cache/unified-cache. * Affects the range [start, start + size - 1]. diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h index 60b60aa6f6..446457fd81 100644 --- a/arch/arm/mach-kirkwood/include/mach/config.h +++ b/arch/arm/mach-kirkwood/include/mach/config.h @@ -24,8 +24,6 @@ #endif /* CONFIG_KW88F6281 */ #include <asm/arch/soc.h> -#define CONFIG_SYS_CACHELINE_SIZE 32 - /* default Dcache Line length for kirkwood */ #define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */ #define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ #define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ diff --git a/arch/arm/mach-mvebu/include/mach/config.h b/arch/arm/mach-mvebu/include/mach/config.h index 4df70d7d3f..1b35e0802b 100644 --- a/arch/arm/mach-mvebu/include/mach/config.h +++ b/arch/arm/mach-mvebu/include/mach/config.h @@ -26,8 +26,6 @@ #define MV88F78X60 /* for the DDR training bin_hdr code */ #endif -#define CONFIG_SYS_CACHELINE_SIZE 32 - #define CONFIG_SYS_L2_PL310 #ifdef CONFIG_SPL_BUILD diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig index a8a0b90c39..89614581bb 100644 --- a/arch/arm/mach-uniphier/Kconfig +++ b/arch/arm/mach-uniphier/Kconfig @@ -75,6 +75,7 @@ config ARCH_UNIPHIER_LD6B config CACHE_UNIPHIER bool "Enable the UniPhier L2 cache controller" depends on ARCH_UNIPHIER_32BIT + select SYS_CACHE_SHIFT_7 default y help This option allows to use the UniPhier System Cache as L2 cache. diff --git a/arch/arm/mach-uniphier/dram/cmd_ddrmphy.c b/arch/arm/mach-uniphier/dram/cmd_ddrmphy.c index 7ac93786be..47cee6fb31 100644 --- a/arch/arm/mach-uniphier/dram/cmd_ddrmphy.c +++ b/arch/arm/mach-uniphier/dram/cmd_ddrmphy.c @@ -304,7 +304,7 @@ static int do_ddrm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD( ddrm, 2, 1, do_ddrm, "UniPhier DDR PHY parameters dumper", - "- dump all of the followings\n" + "- dump all of the following\n" "ddrm zq - dump Impedance Data\n" "ddrm wbdl - dump Write Bit Delay\n" "ddrm rbdl - dump Read Bit Delay\n" diff --git a/arch/arm/mach-uniphier/dram/cmd_ddrphy.c b/arch/arm/mach-uniphier/dram/cmd_ddrphy.c index 0a5a73d8ee..6ac261d23f 100644 --- a/arch/arm/mach-uniphier/dram/cmd_ddrphy.c +++ b/arch/arm/mach-uniphier/dram/cmd_ddrphy.c @@ -258,7 +258,7 @@ static int do_ddr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD( ddr, 2, 1, do_ddr, "UniPhier DDR PHY parameters dumper", - "- dump all of the followings\n" + "- dump all of the following\n" "ddr wbdl - dump Write Bit Delay\n" "ddr rbdl - dump Read Bit Delay\n" "ddr wld - dump Write Leveling\n" |