diff options
Diffstat (limited to 'arch')
390 files changed, 20521 insertions, 2866 deletions
diff --git a/arch/Kconfig b/arch/Kconfig index 566f0443089..d718a681712 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -1,6 +1,9 @@ config CREATE_ARCH_SYMLINK bool +config HAVE_ARCH_IOREMAP + bool + choice prompt "Architecture select" default SANDBOX @@ -33,6 +36,7 @@ config MICROBLAZE config MIPS bool "MIPS architecture" + select HAVE_ARCH_IOREMAP select HAVE_PRIVATE_LIBGCC select SUPPORT_OF_CONTROL @@ -63,6 +67,7 @@ config SANDBOX select DM_I2C select DM_SPI select DM_GPIO + select DM_MMC config SH bool "SuperH architecture" @@ -83,6 +88,11 @@ config X86 select DM_SPI select DM_SPI_FLASH +config XTENSA + bool "Xtensa architecture" + select CREATE_ARCH_SYMLINK + select SUPPORT_OF_CONTROL + endchoice config SYS_ARCH @@ -156,3 +166,4 @@ source "arch/sandbox/Kconfig" source "arch/sh/Kconfig" source "arch/sparc/Kconfig" source "arch/x86/Kconfig" +source "arch/xtensa/Kconfig" diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig index f1dc6c8d77f..4c5696be1c3 100644 --- a/arch/arc/Kconfig +++ b/arch/arc/Kconfig @@ -118,21 +118,21 @@ config SYS_DCACHE_OFF choice prompt "Target select" - default TARGET_AXS101 + default TARGET_AXS10X config TARGET_TB100 bool "Support tb100" -config TARGET_ARCANGEL4 - bool "Support arcangel4" +config TARGET_NSIM + bool "Support standalone nSIM & Free nSIM" -config TARGET_AXS101 - bool "Support axs101" +config TARGET_AXS10X + bool "Support Synopsys Designware SDP board (AXS101 & AXS103)" endchoice source "board/abilis/tb100/Kconfig" source "board/synopsys/Kconfig" -source "board/synopsys/axs101/Kconfig" +source "board/synopsys/axs10x/Kconfig" endmenu diff --git a/arch/arc/cpu/arcv2/ivt.S b/arch/arc/cpu/arcv2/ivt.S index d110b5bba53..7924375fb1d 100644 --- a/arch/arc/cpu/arcv2/ivt.S +++ b/arch/arc/cpu/arcv2/ivt.S @@ -7,21 +7,26 @@ .section .ivt, "a",@progbits .align 4 /* Critical system events */ -.word _start /* 0 - 0x000 */ -.word memory_error /* 1 - 0x008 */ -.word instruction_error /* 2 - 0x010 */ +.word _start /* 0x00 - Reset */ +.word memory_error /* 0x01 - Memory Error */ +.word instruction_error /* 0x02 - Instruction Error */ /* Exceptions */ -.word EV_MachineCheck /* 0x100, Fatal Machine check (0x20) */ -.word EV_TLBMissI /* 0x108, Intruction TLB miss (0x21) */ -.word EV_TLBMissD /* 0x110, Data TLB miss (0x22) */ -.word EV_TLBProtV /* 0x118, Protection Violation (0x23) - or Misaligned Access */ -.word EV_PrivilegeV /* 0x120, Privilege Violation (0x24) */ -.word EV_Trap /* 0x128, Trap exception (0x25) */ -.word EV_Extension /* 0x130, Extn Intruction Excp (0x26) */ +.word EV_MachineCheck /* 0x03 - Fatal Machine check */ +.word EV_TLBMissI /* 0x04 - Intruction TLB miss */ +.word EV_TLBMissD /* 0x05 - Data TLB miss */ +.word EV_TLBProtV /* 0x06 - Protection Violation or Misaligned Access */ +.word EV_PrivilegeV /* 0x07 - Privilege Violation */ +.word EV_SWI /* 0x08 - Software Interrupt */ +.word EV_Trap /* 0x09 - Trap */ +.word EV_Extension /* 0x0A - Extension Intruction Exception */ +.word EV_DivZero /* 0x0B - Division by Zero */ +.word EV_DCError /* 0x0C - Data cache consistency error */ +.word EV_Maligned /* 0x0D - Misaligned data access */ +.word 0 /* 0x0E - Unused */ +.word 0 /* 0x0F - Unused */ /* Device interrupts */ -.rept 29 - j interrupt_handler /* 3:31 - 0x018:0xF8 */ +.rept 240 +.word interrupt_handler /* 0x10 - 0xFF */ .endr diff --git a/arch/arc/cpu/u-boot.lds b/arch/arc/cpu/u-boot.lds index 693df74061f..d3d0a53bf2d 100644 --- a/arch/arc/cpu/u-boot.lds +++ b/arch/arc/cpu/u-boot.lds @@ -4,38 +4,29 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include <config.h> + OUTPUT_FORMAT("elf32-littlearc", "elf32-littlearc", "elf32-littlearc") OUTPUT_ARCH(arc) ENTRY(_start) SECTIONS { - . = ALIGN(4); + . = CONFIG_SYS_TEXT_BASE; + __image_copy_start = .; + __text_start = .; .text : { - *(.__text_start) - *(.__image_copy_start) arch/arc/lib/start.o (.text*) *(.text*) } - - . = ALIGN(4); - .text_end : - { - *(.__text_end) - } + __text_end = .; . = ALIGN(1024); - .ivt_start : { - *(.__ivt_start) - } - + __ivt_start = .; .ivt : { *(.ivt) } - - .ivt_end : { - *(.__ivt_end) - } + __ivt_end = .; . = ALIGN(4); .rodata : { @@ -53,34 +44,20 @@ SECTIONS } . = ALIGN(4); - .rel_dyn_start : { - *(.__rel_dyn_start) - } - + __rel_dyn_start = .; .rela.dyn : { *(.rela.dyn) } - - .rel_dyn_end : { - *(.__rel_dyn_end) - } + __rel_dyn_end = .; . = ALIGN(4); - .bss_start : { - *(.__bss_start); - } - + __bss_start = .; .bss : { *(.bss*) } - - .bss_end : { - *(.__bss_end); - } + __bss_end = .; . = ALIGN(4); - .image_copy_end : { - *(.__image_copy_end) - *(.__init_end) - } + __image_copy_end = .; + __init_end = .; } diff --git a/arch/arc/dts/Makefile b/arch/arc/dts/Makefile index d4772ecabb9..1d94c082ab5 100644 --- a/arch/arc/dts/Makefile +++ b/arch/arc/dts/Makefile @@ -2,8 +2,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -dtb-$(CONFIG_TARGET_AXS101) += axs10x.dtb -dtb-$(CONFIG_TARGET_ARCANGEL4) += arcangel4.dtb +dtb-$(CONFIG_TARGET_AXS10X) += axs10x.dtb +dtb-$(CONFIG_TARGET_NSIM) += nsim.dtb dtb-$(CONFIG_TARGET_TB100) += abilis_tb100.dtb targets += $(dtb-y) diff --git a/arch/arc/dts/arcangel4.dts b/arch/arc/dts/nsim.dts index bfcb9d83698..69e16c2a1b4 100644 --- a/arch/arc/dts/arcangel4.dts +++ b/arch/arc/dts/nsim.dts @@ -1,5 +1,5 @@ /* - * Copyright (C) 2015 Synopsys, Inc. (www.synopsys.com) + * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com) * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/arch/arc/include/asm/sections.h b/arch/arc/include/asm/sections.h index b8f2a859fd9..00f12172ab5 100644 --- a/arch/arc/include/asm/sections.h +++ b/arch/arc/include/asm/sections.h @@ -9,9 +9,7 @@ #include <asm-generic/sections.h> -extern ulong __text_end; extern ulong __ivt_start; extern ulong __ivt_end; -extern ulong __image_copy_start; #endif /* __ASM_ARC_SECTIONS_H */ diff --git a/arch/arc/lib/Makefile b/arch/arc/lib/Makefile index e5928029077..eb62b3c4274 100644 --- a/arch/arc/lib/Makefile +++ b/arch/arc/lib/Makefile @@ -9,7 +9,6 @@ head-y := start.o obj-y += cache.o obj-y += cpu.o obj-y += interrupts.o -obj-y += sections.o obj-y += relocate.o obj-y += strchr-700.o obj-y += strcmp.o diff --git a/arch/arc/lib/interrupts.c b/arch/arc/lib/interrupts.c index d7cab3bb409..ee638d506be 100644 --- a/arch/arc/lib/interrupts.c +++ b/arch/arc/lib/interrupts.c @@ -141,3 +141,29 @@ void do_extension(struct pt_regs *regs) printf("Extension instruction exception\n"); bad_mode(regs); } + +#ifdef CONFIG_ISA_ARCV2 +void do_swi(struct pt_regs *regs) +{ + printf("Software Interrupt exception\n"); + bad_mode(regs); +} + +void do_divzero(unsigned long address, struct pt_regs *regs) +{ + printf("Division by zero exception @ 0x%lx\n", address); + bad_mode(regs); +} + +void do_dcerror(struct pt_regs *regs) +{ + printf("Data cache consistency error exception\n"); + bad_mode(regs); +} + +void do_maligned(unsigned long address, struct pt_regs *regs) +{ + printf("Misaligned data access exception @ 0x%lx\n", address); + bad_mode(regs); +} +#endif diff --git a/arch/arc/lib/ints_low.S b/arch/arc/lib/ints_low.S index 161cf37dc48..e3778847aba 100644 --- a/arch/arc/lib/ints_low.S +++ b/arch/arc/lib/ints_low.S @@ -149,3 +149,31 @@ ENTRY(EV_Extension) mov %r0, %sp j do_extension ENDPROC(EV_Extension) + +#ifdef CONFIG_ISA_ARCV2 +ENTRY(EV_SWI) + SAVE_ALL_SYS + mov %r0, %sp + j do_swi +ENDPROC(EV_SWI) + +ENTRY(EV_DivZero) + SAVE_ALL_SYS + SAVE_EXCEPTION_SOURCE + mov %r1, %sp + j do_divzero +ENDPROC(EV_DivZero) + +ENTRY(EV_DCError) + SAVE_ALL_SYS + mov %r0, %sp + j do_dcerror +ENDPROC(EV_DCError) + +ENTRY(EV_Maligned) + SAVE_ALL_SYS + SAVE_EXCEPTION_SOURCE + mov %r1, %sp + j do_maligned +ENDPROC(EV_Maligned) +#endif diff --git a/arch/arc/lib/relocate.c b/arch/arc/lib/relocate.c index 5c2c2d19309..7802f405459 100644 --- a/arch/arc/lib/relocate.c +++ b/arch/arc/lib/relocate.c @@ -6,7 +6,10 @@ #include <common.h> #include <elf.h> -#include <asm/sections.h> +#include <asm-generic/sections.h> + +extern ulong __image_copy_start; +extern ulong __ivt_end; DECLARE_GLOBAL_DATA_PTR; @@ -37,6 +40,9 @@ int do_elf_reloc_fixups(void) Elf32_Rela *re_src = (Elf32_Rela *)(&__rel_dyn_start); Elf32_Rela *re_end = (Elf32_Rela *)(&__rel_dyn_end); + debug("Section .rela.dyn is located at %08x-%08x\n", + (unsigned int)re_src, (unsigned int)re_end); + Elf32_Addr *offset_ptr_rom, *last_offset = NULL; Elf32_Addr *offset_ptr_ram; @@ -52,6 +58,10 @@ int do_elf_reloc_fixups(void) offset_ptr_ram = (Elf32_Addr *)((ulong)offset_ptr_rom + gd->reloc_off); + debug("Patching value @ %08x (relocated to %08x)\n", + (unsigned int)offset_ptr_rom, + (unsigned int)offset_ptr_ram); + /* * Use "memcpy" because target location might be * 16-bit aligned on ARC so we may need to read diff --git a/arch/arc/lib/sections.c b/arch/arc/lib/sections.c deleted file mode 100644 index a72c6946d53..00000000000 --- a/arch/arc/lib/sections.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * For some reason linker sets linker-generated symbols to zero in PIE mode. - * A work-around is substitution of linker-generated symbols with - * compiler-generated symbols which are properly handled by linker in PAE mode. - */ - -char __bss_start[0] __attribute__((section(".__bss_start"))); -char __bss_end[0] __attribute__((section(".__bss_end"))); -char __image_copy_start[0] __attribute__((section(".__image_copy_start"))); -char __image_copy_end[0] __attribute__((section(".__image_copy_end"))); -char __rel_dyn_start[0] __attribute__((section(".__rel_dyn_start"))); -char __rel_dyn_end[0] __attribute__((section(".__rel_dyn_end"))); -char __text_start[0] __attribute__((section(".__text_start"))); -char __text_end[0] __attribute__((section(".__text_end"))); -char __init_end[0] __attribute__((section(".__init_end"))); -char __ivt_start[0] __attribute__((section(".__ivt_start"))); -char __ivt_end[0] __attribute__((section(".__ivt_end"))); diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 8c867b26da6..aef901c3f44 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -6,6 +6,7 @@ config SYS_ARCH config ARM64 bool + select PHYS_64BIT config DMA_ADDR_T_64BIT bool @@ -553,11 +554,14 @@ config TARGET_MX53SMD config OMAP34XX bool "OMAP34XX SoC" select CPU_V7 + select SUPPORT_SPL + select USE_TINY_PRINTF config OMAP44XX bool "OMAP44XX SoC" select CPU_V7 select SUPPORT_SPL + select USE_TINY_PRINTF config OMAP54XX bool "OMAP54XX SoC" @@ -658,10 +662,13 @@ config ARCH_ZYNQ select DM_GPIO select SPL_DM if SPL select DM_MMC + select DM_MMC_OPS select DM_SPI select DM_SERIAL select DM_SPI_FLASH select SPL_SEPARATE_BSS if SPL + select DM_USB if USB + select BLK config ARCH_ZYNQMP bool "Support Xilinx ZynqMP Platform" @@ -670,6 +677,9 @@ config ARCH_ZYNQMP select OF_CONTROL select DM_SERIAL select SUPPORT_SPL + select CLK + select SPL_CLK + select DM_USB if USB config TEGRA bool "NVIDIA Tegra" @@ -839,11 +849,19 @@ config STM32 config ARCH_ROCKCHIP bool "Support Rockchip SoCs" - select SUPPORT_SPL - select SPL select OF_CONTROL - select CPU_V7 + select BLK select DM + select SPL_DM if SPL + select SYS_MALLOC_F + select SPL_SYS_MALLOC_SIMPLE if SPL + select DM_GPIO + select DM_I2C + select DM_MMC + select DM_MMC_OPS + select DM_SERIAL + select DM_SPI + select DM_SPI_FLASH config TARGET_THUNDERX_88XX bool "Support ThunderX 88xx" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 5000d87fd0b..42093c2b5e2 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -20,6 +20,14 @@ arch-$(CONFIG_CPU_V7) =$(call cc-option, -march=armv7-a, \ $(call cc-option, -march=armv7, -march=armv5)) arch-$(CONFIG_ARM64) =-march=armv8-a +# On Tegra systems we must build SPL for the armv4 core on the device +# but otherwise we can use the value in CONFIG_SYS_ARM_ARCH +ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TEGRA),yy) +arch-y += -D__LINUX_ARM_ARCH__=4 +else +arch-y += -D__LINUX_ARM_ARCH__=$(CONFIG_SYS_ARM_ARCH) +endif + # Evaluate arch cc-option calls now arch-y := $(arch-y) diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 9a5a9747c48..8f8586295ef 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -120,8 +120,8 @@ endif ifdef CONFIG_ARM64 OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .u_boot_list -j .rela.dyn else -OBJCOPYFLAGS += -j .text -j .secure_text -j .rodata -j .hash -j .data -j \ - .got -j .got.plt -j .u_boot_list -j .rel.dyn +OBJCOPYFLAGS += -j .text -j .secure_text -j .secure_data -j .rodata -j .hash \ + -j .data -j .got -j .got.plt -j .u_boot_list -j .rel.dyn endif ifdef CONFIG_OF_EMBED diff --git a/arch/arm/cpu/arm11/cpu.c b/arch/arm/cpu/arm11/cpu.c index 1e4c2142b13..7244c2e7d79 100644 --- a/arch/arm/cpu/arm11/cpu.c +++ b/arch/arm/cpu/arm11/cpu.c @@ -69,23 +69,6 @@ void flush_dcache_all(void) asm volatile("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); } -static int check_cache_range(unsigned long start, unsigned long stop) -{ - int ok = 1; - - if (start & (CONFIG_SYS_CACHELINE_SIZE - 1)) - ok = 0; - - if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1)) - ok = 0; - - if (!ok) - debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n", - start, stop); - - return ok; -} - void invalidate_dcache_range(unsigned long start, unsigned long stop) { if (!check_cache_range(start, stop)) diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c index 2839c863e82..2119382ab24 100644 --- a/arch/arm/cpu/arm926ejs/cache.c +++ b/arch/arm/cpu/arm926ejs/cache.c @@ -29,23 +29,6 @@ void flush_dcache_all(void) ); } -static int check_cache_range(unsigned long start, unsigned long stop) -{ - int ok = 1; - - if (start & (CONFIG_SYS_CACHELINE_SIZE - 1)) - ok = 0; - - if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1)) - ok = 0; - - if (!ok) - debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n", - start, stop); - - return ok; -} - void invalidate_dcache_range(unsigned long start, unsigned long stop) { if (!check_cache_range(start, stop)) diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig index afeaac84dec..41c6639c138 100644 --- a/arch/arm/cpu/armv7/Kconfig +++ b/arch/arm/cpu/armv7/Kconfig @@ -7,32 +7,32 @@ config CPU_V7_HAS_VIRT bool config ARMV7_NONSEC - boolean "Enable support for booting in non-secure mode" if EXPERT + bool "Enable support for booting in non-secure mode" if EXPERT depends on CPU_V7_HAS_NONSEC default y ---help--- Say Y here to enable support for booting in non-secure / SVC mode. config ARMV7_BOOT_SEC_DEFAULT - boolean "Boot in secure mode by default" if EXPERT + bool "Boot in secure mode by default" if EXPERT depends on ARMV7_NONSEC default y if TEGRA ---help--- Say Y here to boot in secure mode by default even if non-secure mode is supported. This option is useful to boot kernels which do not suppport booting in non-secure mode. Only set this if you need it. - This can be overriden at run-time by setting the bootm_boot_mode env. + This can be overridden at run-time by setting the bootm_boot_mode env. variable to "sec" or "nonsec". config ARMV7_VIRT - boolean "Enable support for hardware virtualization" if EXPERT + bool "Enable support for hardware virtualization" if EXPERT depends on CPU_V7_HAS_VIRT && ARMV7_NONSEC default y ---help--- Say Y here to boot in hypervisor (HYP) mode when booting non-secure. config ARMV7_LPAE - boolean "Use LPAE page table format" if EXPERT + bool "Use LPAE page table format" if EXPERT depends on CPU_V7 default n ---help--- diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index ddd8d12d517..0d4bfbc55b3 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -19,7 +19,7 @@ endif endif obj-$(CONFIG_ARMV7_NONSEC) += nonsec_virt.o virt-v7.o virt-dt.o -obj-$(CONFIG_ARMV7_PSCI) += psci.o +obj-$(CONFIG_ARMV7_PSCI) += psci.o psci-common.o obj-$(CONFIG_IPROC) += iproc-common/ obj-$(CONFIG_KONA) += kona-common/ diff --git a/arch/arm/cpu/armv7/am33xx/config.mk b/arch/arm/cpu/armv7/am33xx/config.mk index 6d95d327b45..d4eb21ca14e 100644 --- a/arch/arm/cpu/armv7/am33xx/config.mk +++ b/arch/arm/cpu/armv7/am33xx/config.mk @@ -26,6 +26,7 @@ endif else ifeq ($(CONFIG_TI_SECURE_DEVICE),y) ALL-$(CONFIG_QSPI_BOOT) += u-boot_HS_XIP_X-LOADER +ALL-$(CONFIG_SPL_LOAD_FIT) += u-boot_HS.img endif ALL-y += u-boot.img endif diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c index 888cf1f7326..6acf30c5db0 100644 --- a/arch/arm/cpu/armv7/am33xx/ddr.c +++ b/arch/arm/cpu/armv7/am33xx/ddr.c @@ -120,12 +120,15 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr) writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); writel(regs->sdram_config, &cstat->secure_emif_sdram_config); + + /* Wait 1ms because of L3 timeout error */ + udelay(1000); + writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw); /* Perform hardware leveling for DDR3 */ if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3) { - udelay(1000); writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) | 0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36); writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw) | @@ -289,19 +292,14 @@ static void ext_phy_settings_hwlvl(const struct emif_regs *regs, int nr) void config_ddr_phy(const struct emif_regs *regs, int nr) { /* - * Disable initialization and refreshes for now until we - * finish programming EMIF regs. - * Also set time between rising edge of DDR_RESET to rising - * edge of DDR_CKE to > 500us per memory spec. + * Disable initialization and refreshes for now until we finish + * programming EMIF regs and set time between rising edge of + * DDR_RESET to rising edge of DDR_CKE to > 500us per memory spec. + * We currently hardcode a value based on a max expected frequency + * of 400MHz. */ -#ifndef CONFIG_AM43XX - setbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl, - EMIF_REG_INITREF_DIS_MASK); -#endif - if (regs->zq_config) - /* Set time between rising edge of DDR_RESET to rising - * edge of DDR_CKE to > 500us per memory spec. */ - writel(0x00003100, &emif_reg[nr]->emif_sdram_ref_ctrl); + writel(EMIF_REG_INITREF_DIS_MASK | 0x3100, + &emif_reg[nr]->emif_sdram_ref_ctrl); writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1); diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index dc309dac909..c4bbcc3cc3e 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -19,23 +19,6 @@ void v7_flush_dcache_all(void); void v7_invalidate_dcache_all(void); -static int check_cache_range(unsigned long start, unsigned long stop) -{ - int ok = 1; - - if (start & (CONFIG_SYS_CACHELINE_SIZE - 1)) - ok = 0; - - if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1)) - ok = 0; - - if (!ok) - debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n", - start, stop); - - return ok; -} - static u32 get_ccsidr(void) { u32 ccsidr; @@ -61,27 +44,8 @@ static void v7_dcache_inval_range(u32 start, u32 stop, u32 line_len) { u32 mva; - /* - * If start address is not aligned to cache-line do not - * invalidate the first cache-line - */ - if (start & (line_len - 1)) { - printf("ERROR: %s - start address is not aligned - 0x%08x\n", - __func__, start); - /* move to next cache line */ - start = (start + line_len - 1) & ~(line_len - 1); - } - - /* - * If stop address is not aligned to cache-line do not - * invalidate the last cache-line - */ - if (stop & (line_len - 1)) { - printf("ERROR: %s - stop address is not aligned - 0x%08x\n", - __func__, stop); - /* align to the beginning of this cache line */ - stop &= ~(line_len - 1); - } + if (!check_cache_range(start, stop)) + return; for (mva = start; mva < stop; mva = mva + line_len) { /* DCIMVAC - Invalidate data cache by MVA to PoC */ @@ -111,7 +75,7 @@ static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op) } /* DSB to make sure the operation is complete */ - DSB; + dsb(); } /* Invalidate TLB */ @@ -124,9 +88,9 @@ static void v7_inval_tlb(void) /* Invalidate entire instruction TLB */ asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0)); /* Full system DSB - make sure that the invalidation is complete */ - DSB; + dsb(); /* Full system ISB - make sure the instruction stream sees it */ - ISB; + isb(); } void invalidate_dcache_all(void) @@ -195,6 +159,14 @@ void flush_dcache_all(void) { } +void invalidate_dcache_range(unsigned long start, unsigned long stop) +{ +} + +void flush_dcache_range(unsigned long start, unsigned long stop) +{ +} + void arm_init_before_mmu(void) { } @@ -222,10 +194,10 @@ void invalidate_icache_all(void) asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0)); /* Full system DSB - make sure that the invalidation is complete */ - DSB; + dsb(); /* ISB - make sure the instruction stream sees it */ - ISB; + isb(); } #else void invalidate_icache_all(void) diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S b/arch/arm/cpu/armv7/ls102xa/psci.S index cf5cd48bcbe..8f386800f6c 100644 --- a/arch/arm/cpu/armv7/ls102xa/psci.S +++ b/arch/arm/cpu/armv7/ls102xa/psci.S @@ -12,33 +12,118 @@ #include <asm/arch-armv7/generictimer.h> #include <asm/psci.h> +#define RCPM_TWAITSR 0x04C + #define SCFG_CORE0_SFT_RST 0x130 #define SCFG_CORESRENCR 0x204 -#define DCFG_CCSR_BRR 0x0E4 -#define DCFG_CCSR_SCRATCHRW1 0x200 +#define DCFG_CCSR_RSTCR 0x0B0 +#define DCFG_CCSR_RSTCR_RESET_REQ 0x2 +#define DCFG_CCSR_BRR 0x0E4 +#define DCFG_CCSR_SCRATCHRW1 0x200 + +#define PSCI_FN_PSCI_VERSION_FEATURE_MASK 0x0 +#define PSCI_FN_CPU_SUSPEND_FEATURE_MASK 0x0 +#define PSCI_FN_CPU_OFF_FEATURE_MASK 0x0 +#define PSCI_FN_CPU_ON_FEATURE_MASK 0x0 +#define PSCI_FN_AFFINITY_INFO_FEATURE_MASK 0x0 +#define PSCI_FN_SYSTEM_OFF_FEATURE_MASK 0x0 +#define PSCI_FN_SYSTEM_RESET_FEATURE_MASK 0x0 .pushsection ._secure.text, "ax" .arch_extension sec + .align 5 + #define ONE_MS (GENERIC_TIMER_CLK / 1000) #define RESET_WAIT (30 * ONE_MS) +.globl psci_version +psci_version: + movw r0, #0 + movt r0, #1 + + bx lr + +_ls102x_psci_supported_table: + .word ARM_PSCI_0_2_FN_PSCI_VERSION + .word PSCI_FN_PSCI_VERSION_FEATURE_MASK + .word ARM_PSCI_0_2_FN_CPU_SUSPEND + .word PSCI_FN_CPU_SUSPEND_FEATURE_MASK + .word ARM_PSCI_0_2_FN_CPU_OFF + .word PSCI_FN_CPU_OFF_FEATURE_MASK + .word ARM_PSCI_0_2_FN_CPU_ON + .word PSCI_FN_CPU_ON_FEATURE_MASK + .word ARM_PSCI_0_2_FN_AFFINITY_INFO + .word PSCI_FN_AFFINITY_INFO_FEATURE_MASK + .word ARM_PSCI_0_2_FN_SYSTEM_OFF + .word PSCI_FN_SYSTEM_OFF_FEATURE_MASK + .word ARM_PSCI_0_2_FN_SYSTEM_RESET + .word PSCI_FN_SYSTEM_RESET_FEATURE_MASK + .word 0 + .word ARM_PSCI_RET_NI + +.globl psci_features +psci_features: + adr r2, _ls102x_psci_supported_table +1: ldr r3, [r2] + cmp r3, #0 + beq out_psci_features + cmp r1, r3 + addne r2, r2, #8 + bne 1b + +out_psci_features: + ldr r0, [r2, #4] + bx lr + +@ r0: return value ARM_PSCI_RET_SUCCESS or ARM_PSCI_RET_INVAL +@ r1: input target CPU ID in MPIDR format, original value in r1 may be dropped +@ r4: output validated CPU ID if ARM_PSCI_RET_SUCCESS returns, meaningless for +@ ARM_PSCI_RET_INVAL,suppose caller saves r4 before calling +LENTRY(psci_check_target_cpu_id) + @ Get the real CPU number + and r4, r1, #0xff + mov r0, #ARM_PSCI_RET_INVAL + + @ Bit[31:24], bits must be zero. + tst r1, #0xff000000 + bxne lr + + @ Affinity level 2 - Cluster: only one cluster in LS1021xa. + tst r1, #0xff0000 + bxne lr + + @ Affinity level 1 - Processors: should be in 0xf00 format. + lsr r1, r1, #8 + teq r1, #0xf + bxne lr + + @ Affinity level 0 - CPU: only 0, 1 are valid in LS1021xa. + cmp r4, #2 + bxge lr + + mov r0, #ARM_PSCI_RET_SUCCESS + bx lr +ENDPROC(psci_check_target_cpu_id) + @ r1 = target CPU @ r2 = target PC .globl psci_cpu_on psci_cpu_on: - push {lr} + push {r4, r5, r6, lr} @ Clear and Get the correct CPU number @ r1 = 0xf01 - and r1, r1, #0xff + bl psci_check_target_cpu_id + cmp r0, #ARM_PSCI_RET_INVAL + beq out_psci_cpu_on - mov r0, r1 - bl psci_get_cpu_stack_top - str r2, [r0] - dsb + mov r0, r4 + mov r1, r2 + bl psci_save_target_pc + mov r1, r4 @ Get DCFG base address movw r4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff) @@ -101,7 +186,8 @@ holdoff_release: @ Return mov r0, #ARM_PSCI_RET_SUCCESS - pop {lr} +out_psci_cpu_on: + pop {r4, r5, r6, lr} bx lr .globl psci_cpu_off @@ -111,16 +197,50 @@ psci_cpu_off: 1: wfi b 1b -.globl psci_arch_init -psci_arch_init: - mov r6, lr +.globl psci_affinity_info +psci_affinity_info: + push {lr} + + mov r0, #ARM_PSCI_RET_INVAL + + @ Verify Affinity level + cmp r2, #0 + bne out_affinity_info + + bl psci_check_target_cpu_id + cmp r0, #ARM_PSCI_RET_INVAL + beq out_affinity_info + mov r1, r4 + + @ Get RCPM base address + movw r4, #(CONFIG_SYS_FSL_RCPM_ADDR & 0xffff) + movt r4, #(CONFIG_SYS_FSL_RCPM_ADDR >> 16) + + mov r0, #PSCI_AFFINITY_LEVEL_ON + + @ Detect target CPU state + ldr r2, [r4, #RCPM_TWAITSR] + rev r2, r2 + lsr r2, r2, r1 + ands r2, r2, #1 + beq out_affinity_info + + mov r0, #PSCI_AFFINITY_LEVEL_OFF - bl psci_get_cpu_id - bl psci_get_cpu_stack_top - mov sp, r0 +out_affinity_info: + pop {pc} + +.globl psci_system_reset +psci_system_reset: + @ Get DCFG base address + movw r1, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff) + movt r1, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16) - bx r6 + mov r2, #DCFG_CCSR_RSTCR_RESET_REQ + rev r2, r2 + str r2, [r1, #DCFG_CCSR_RSTCR] + +1: wfi + b 1b - .globl psci_text_end -psci_text_end: .popsection diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index 663f970c4c9..78383f0e897 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -148,6 +148,10 @@ config TARGET_PLATINUM_TITANIUM bool "platinum-titanium" select SUPPORT_SPL +config TARGET_PCM058 + bool "Phytec PCM058 i.MX6 Quad" + select SUPPORT_SPL + config TARGET_SECOMX6 bool "secomx6 boards" @@ -178,6 +182,18 @@ config TARGET_XPRESS select DM_THERMAL select SUPPORT_SPL +config TARGET_ZC5202 + bool "zc5202" + select SUPPORT_SPL + select DM + select DM_THERMAL + +config TARGET_ZC5601 + bool "zc5601" + select SUPPORT_SPL + select DM + select DM_THERMAL + endchoice config SYS_SOC @@ -192,6 +208,7 @@ source "board/boundary/nitrogen6x/Kconfig" source "board/ccv/xpress/Kconfig" source "board/compulab/cm_fx6/Kconfig" source "board/congatec/cgtqmx6eval/Kconfig" +source "board/el/el6x/Kconfig" source "board/embest/mx6boards/Kconfig" source "board/freescale/mx6qarm2/Kconfig" source "board/freescale/mx6qsabreauto/Kconfig" @@ -200,6 +217,7 @@ source "board/freescale/mx6slevk/Kconfig" source "board/freescale/mx6sxsabresd/Kconfig" source "board/freescale/mx6sxsabreauto/Kconfig" source "board/freescale/mx6ul_14x14_evk/Kconfig" +source "board/phytec/pcm058/Kconfig" source "board/gateworks/gw_ventana/Kconfig" source "board/kosagi/novena/Kconfig" source "board/seco/Kconfig" diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index ff932aa7ed4..b3c9dcc9699 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -281,7 +281,7 @@ static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num) case PLL_BUS: if (!is_mx6ul()) { if (pfd_num == 3) { - /* No PFD3 on PPL2 */ + /* No PFD3 on PLL2 */ return 0; } } @@ -433,9 +433,9 @@ static u32 get_axi_clk(void) if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) { if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL) - root_freq = mxc_get_pll_pfd(PLL_BUS, 2); - else root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1); + else + root_freq = mxc_get_pll_pfd(PLL_BUS, 2); } else root_freq = get_periph_clk(); diff --git a/arch/arm/cpu/armv7/mx7/Kconfig b/arch/arm/cpu/armv7/mx7/Kconfig index ecfa4a2c356..5fdc8dd5836 100644 --- a/arch/arm/cpu/armv7/mx7/Kconfig +++ b/arch/arm/cpu/armv7/mx7/Kconfig @@ -3,6 +3,8 @@ if ARCH_MX7 config MX7 bool select ROM_UNIFIED_SECTIONS + select CPU_V7_HAS_VIRT + select CPU_V7_HAS_NONSEC default y config MX7D @@ -25,12 +27,19 @@ config TARGET_WARP7 select DM select DM_THERMAL +config TARGET_COLIBRI_IMX7 + bool "Support Colibri iMX7S/iMX7D modules" + select DM + select DM_SERIAL + select DM_THERMAL + endchoice config SYS_SOC default "mx7" source "board/freescale/mx7dsabresd/Kconfig" +source "board/toradex/colibri_imx7/Kconfig" source "board/warp7/Kconfig" endif diff --git a/arch/arm/cpu/armv7/mx7/psci-mx7.c b/arch/arm/cpu/armv7/mx7/psci-mx7.c index 9a330476cf5..502552d1718 100644 --- a/arch/arm/cpu/armv7/mx7/psci-mx7.c +++ b/arch/arm/cpu/armv7/mx7/psci-mx7.c @@ -1,9 +1,9 @@ #include <asm/io.h> #include <asm/psci.h> +#include <asm/secure.h> #include <asm/arch/imx-regs.h> #include <common.h> -#define __secure __attribute__((section("._secure.text"))) #define GPC_CPU_PGC_SW_PDN_REQ 0xfc #define GPC_CPU_PGC_SW_PUP_REQ 0xf0 diff --git a/arch/arm/cpu/armv7/mx7/psci.S b/arch/arm/cpu/armv7/mx7/psci.S index 34c6ab33f05..96e88d6184e 100644 --- a/arch/arm/cpu/armv7/mx7/psci.S +++ b/arch/arm/cpu/armv7/mx7/psci.S @@ -9,35 +9,22 @@ .arch_extension sec - @ r1 = target CPU - @ r2 = target PC - -.globl psci_arch_init -psci_arch_init: - mov r6, lr - - bl psci_get_cpu_id - bl psci_get_cpu_stack_top - mov sp, r0 - - bx r6 - - @ r1 = target CPU - @ r2 = target PC - .globl psci_cpu_on psci_cpu_on: - push {lr} + push {r4, r5, lr} + mov r4, r0 + mov r5, r1 mov r0, r1 - bl psci_get_cpu_stack_top - str r2, [r0] - dsb + mov r1, r2 + bl psci_save_target_pc + mov r0, r4 + mov r1, r5 ldr r2, =psci_cpu_entry bl imx_cpu_on - pop {pc} + pop {r4, r5, pc} .globl psci_cpu_off psci_cpu_off: @@ -49,6 +36,4 @@ psci_cpu_off: 1: wfi b 1b - .globl psci_text_end -psci_text_end: .popsection diff --git a/arch/arm/cpu/armv7/mx7/soc.c b/arch/arm/cpu/armv7/mx7/soc.c index ef46c92b098..dead1d3a96f 100644 --- a/arch/arm/cpu/armv7/mx7/soc.c +++ b/arch/arm/cpu/armv7/mx7/soc.c @@ -248,6 +248,20 @@ int arch_cpu_init(void) return 0; } +#ifdef CONFIG_ARCH_MISC_INIT +int arch_misc_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + if (is_mx7d()) + setenv("soc", "imx7d"); + else + setenv("soc", "imx7s"); +#endif + + return 0; +} +#endif + #ifdef CONFIG_SERIAL_TAG void get_board_serial(struct tag_serialnr *serialnr) { diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index b7563edbe6b..95ce9387b83 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -49,8 +49,13 @@ _secure_monitor: mcr p15, 0, r5, c12, c0, 1 isb - @ Obtain a secure stack, and configure the PSCI backend + @ Obtain a secure stack + bl psci_stack_setup + + @ Configure the PSCI backend + push {r0, r1, r2, ip} bl psci_arch_init + pop {r0, r1, r2, ip} #endif #ifdef CONFIG_ARM_ERRATA_773022 diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile index 87a7ac03f92..3172bae105b 100644 --- a/arch/arm/cpu/armv7/omap-common/Makefile +++ b/arch/arm/cpu/armv7/omap-common/Makefile @@ -36,3 +36,5 @@ obj-y += boot-common.o obj-y += lowlevel_init.o obj-y += mem-common.o + +obj-$(CONFIG_TI_SECURE_DEVICE) += sec-common.o diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index 2de99357657..9b975831046 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -443,15 +443,12 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic) { u32 offset_code; u32 offset = volt_mv; -#ifndef CONFIG_DRA7XX int ret = 0; -#endif if (!volt_mv) return; pmic->pmic_bus_init(); -#ifndef CONFIG_DRA7XX /* See if we can first get the GPIO if needed */ if (pmic->gpio_en) ret = gpio_request(pmic->gpio, "PMIC_GPIO"); @@ -465,7 +462,7 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic) /* Pull the GPIO low to select SET0 register, while we program SET1 */ if (pmic->gpio_en) gpio_direction_output(pmic->gpio, 0); -#endif + /* convert to uV for better accuracy in the calculations */ offset *= 1000; @@ -476,10 +473,8 @@ void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic) if (pmic->pmic_write(pmic->i2c_slave_addr, vcore_reg, offset_code)) printf("Scaling voltage failed for 0x%x\n", vcore_reg); -#ifndef CONFIG_DRA7XX if (pmic->gpio_en) gpio_direction_output(pmic->gpio, 1); -#endif } static u32 optimize_vcore_voltage(struct volts const *v) @@ -534,7 +529,6 @@ void __weak recalibrate_iodelay(void) */ void scale_vcores(struct vcores_data const *vcores) { -#if defined(CONFIG_DRA7XX) int i; struct volts *pv = (struct volts *)vcores; struct volts *px; @@ -594,7 +588,16 @@ void scale_vcores(struct vcores_data const *vcores) vcores->mpu.abb_tx_done_mask, OMAP_ABB_FAST_OPP); - /* The .mm member is not used for the DRA7xx */ + debug("mm: %d\n", vcores->mm.value); + do_scale_vcore(vcores->mm.addr, vcores->mm.value, vcores->mm.pmic); + /* Configure MM ABB LDO after scale */ + abb_setup(vcores->mm.efuse.reg, + (*ctrl)->control_wkup_ldovbb_mm_voltage_ctrl, + (*prcm)->prm_abbldo_mm_setup, + (*prcm)->prm_abbldo_mm_ctrl, + (*prcm)->prm_irqstatus_mpu, + vcores->mm.abb_tx_done_mask, + OMAP_ABB_FAST_OPP); debug("gpu: %d\n", vcores->gpu.value); do_scale_vcore(vcores->gpu.addr, vcores->gpu.value, vcores->gpu.pmic); @@ -626,56 +629,6 @@ void scale_vcores(struct vcores_data const *vcores) (*prcm)->prm_irqstatus_mpu, vcores->iva.abb_tx_done_mask, OMAP_ABB_FAST_OPP); - /* Might need udelay(1000) here if debug is enabled to see all prints */ -#else - u32 val; - - val = optimize_vcore_voltage(&vcores->core); - do_scale_vcore(vcores->core.addr, val, vcores->core.pmic); - - /* - * IO delay recalibration should be done immediately after - * adjusting AVS voltages for VDD_CORE_L. - * Respective boards should call __recalibrate_iodelay() - * with proper mux, virtual and manual mode configurations. - */ -#ifdef CONFIG_IODELAY_RECALIBRATION - recalibrate_iodelay(); -#endif - - val = optimize_vcore_voltage(&vcores->mpu); - do_scale_vcore(vcores->mpu.addr, val, vcores->mpu.pmic); - - /* Configure MPU ABB LDO after scale */ - abb_setup(vcores->mpu.efuse.reg, - (*ctrl)->control_wkup_ldovbb_mpu_voltage_ctrl, - (*prcm)->prm_abbldo_mpu_setup, - (*prcm)->prm_abbldo_mpu_ctrl, - (*prcm)->prm_irqstatus_mpu_2, - vcores->mpu.abb_tx_done_mask, - OMAP_ABB_FAST_OPP); - - val = optimize_vcore_voltage(&vcores->mm); - do_scale_vcore(vcores->mm.addr, val, vcores->mm.pmic); - - /* Configure MM ABB LDO after scale */ - abb_setup(vcores->mm.efuse.reg, - (*ctrl)->control_wkup_ldovbb_mm_voltage_ctrl, - (*prcm)->prm_abbldo_mm_setup, - (*prcm)->prm_abbldo_mm_ctrl, - (*prcm)->prm_irqstatus_mpu, - vcores->mm.abb_tx_done_mask, - OMAP_ABB_FAST_OPP); - - val = optimize_vcore_voltage(&vcores->gpu); - do_scale_vcore(vcores->gpu.addr, val, vcores->gpu.pmic); - - val = optimize_vcore_voltage(&vcores->eve); - do_scale_vcore(vcores->eve.addr, val, vcores->eve.pmic); - - val = optimize_vcore_voltage(&vcores->iva); - do_scale_vcore(vcores->iva.addr, val, vcores->iva.pmic); -#endif } static inline void enable_clock_domain(u32 const clkctrl_reg, u32 enable_mode) diff --git a/arch/arm/cpu/armv7/omap-common/config_secure.mk b/arch/arm/cpu/armv7/omap-common/config_secure.mk index c7bb101be8e..1122439e38b 100644 --- a/arch/arm/cpu/armv7/omap-common/config_secure.mk +++ b/arch/arm/cpu/armv7/omap-common/config_secure.mk @@ -12,8 +12,8 @@ cmd_mkomapsecimg = $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh \ $(if $(KBUILD_VERBOSE:1=), >/dev/null) else cmd_mkomapsecimg = $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh \ - $(patsubst u-boot_HS_%,%,$(@F)) $< $@ $(CONFIG_ISW_ENTRY_ADDR) \ - $(if $(KBUILD_VERBOSE:1=), >/dev/null) + $(patsubst u-boot_HS_%,%,$(@F)) $< $@ $(CONFIG_ISW_ENTRY_ADDR) \ + $(if $(KBUILD_VERBOSE:1=), >/dev/null) endif else cmd_mkomapsecimg = echo "WARNING:" \ @@ -25,14 +25,33 @@ cmd_mkomapsecimg = echo "WARNING: TI_SECURE_DEV_PKG environment" \ "variable must be defined for TI secure devices. $@ was NOT created!" endif +ifdef CONFIG_SPL_LOAD_FIT +quiet_cmd_omapsecureimg = SECURE $@ +ifneq ($(TI_SECURE_DEV_PKG),) +ifneq ($(wildcard $(TI_SECURE_DEV_PKG)/scripts/secure-binary-image.sh),) +cmd_omapsecureimg = $(TI_SECURE_DEV_PKG)/scripts/secure-binary-image.sh \ + $< $@ \ + $(if $(KBUILD_VERBOSE:1=), >/dev/null) +else +cmd_omapsecureimg = echo "WARNING:" \ + "$(TI_SECURE_DEV_PKG)/scripts/secure-binary-image.sh not found." \ + "$@ was NOT created!"; cp $< $@ +endif +else +cmd_omapsecureimg = echo "WARNING: TI_SECURE_DEV_PKG environment" \ + "variable must be defined for TI secure devices." \ + "$@ was NOT created!"; cp $< $@ +endif +endif + + # Standard X-LOADER target (QPSI, NOR flash) u-boot-spl_HS_X-LOADER: $(obj)/u-boot-spl.bin $(call if_changed,mkomapsecimg) -# For MLO targets (SD card boot) the final file name -# that is copied to the SD card fAT partition must -# be MLO, so we make a copy of the output file to a -# new file with that name +# For MLO targets (SD card boot) the final file name that is copied to the SD +# card FAT partition must be MLO, so we make a copy of the output file to a new +# file with that name u-boot-spl_HS_MLO: $(obj)/u-boot-spl.bin $(call if_changed,mkomapsecimg) @if [ -f $@ ]; then \ @@ -51,16 +70,44 @@ u-boot-spl_HS_ULO: $(obj)/u-boot-spl.bin u-boot-spl_HS_ISSW: $(obj)/u-boot-spl.bin $(call if_changed,mkomapsecimg) -# For SPI flash on AM335x and AM43xx, these -# require special byte swap handling so we use -# the SPI_X-LOADER target instead of X-LOADER -# and let the create-boot-image.sh script handle -# that +# For SPI flash on AM335x and AM43xx, these require special byte swap handling +# so we use the SPI_X-LOADER target instead of X-LOADER and let the +# create-boot-image.sh script handle that u-boot-spl_HS_SPI_X-LOADER: $(obj)/u-boot-spl.bin $(call if_changed,mkomapsecimg) -# For supporting single stage XiP QSPI on AM43xx, the -# image is a full u-boot file, not an SPL. In this case -# the mkomapsecimg command looks for a u-boot-HS_* prefix +# For supporting single stage XiP QSPI on AM43xx, the image is a full u-boot +# file, not an SPL. In this case the mkomapsecimg command looks for a +# u-boot-HS_* prefix u-boot_HS_XIP_X-LOADER: $(obj)/u-boot.bin $(call if_changed,mkomapsecimg) + +# For supporting the SPL loading and interpreting of FIT images whose +# components are pre-processed before being integrated into the FIT image in +# order to secure them in some way +ifdef CONFIG_SPL_LOAD_FIT + +MKIMAGEFLAGS_u-boot_HS.img = -f auto -A $(ARCH) -T firmware -C none -O u-boot \ + -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_UBOOT_START) \ + -n "U-Boot $(UBOOTRELEASE) for $(BOARD) board" -E \ + $(patsubst %,-b arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) + +OF_LIST_TARGETS = $(patsubst %,arch/$(ARCH)/dts/%.dtb,$(subst ",,$(CONFIG_OF_LIST))) +$(OF_LIST_TARGETS): dtbs + +%_HS.dtb: %.dtb + $(call if_changed,omapsecureimg) + $(Q)if [ -f $@ ]; then \ + cp -f $@ $<; \ + fi + +u-boot-nodtb_HS.bin: u-boot-nodtb.bin + $(call if_changed,omapsecureimg) + +u-boot_HS.img: u-boot-nodtb_HS.bin u-boot.img $(patsubst %.dtb,%_HS.dtb,$(OF_LIST_TARGETS)) + $(call if_changed,mkimage) + $(Q)if [ -f $@ ]; then \ + cp -f $@ u-boot.img; \ + fi + +endif diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index 9a9c764b4d1..2b790105b0b 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -37,7 +37,8 @@ void set_lpmode_selfrefresh(u32 base) void force_emif_self_refresh() { set_lpmode_selfrefresh(EMIF1_BASE); - set_lpmode_selfrefresh(EMIF2_BASE); + if (!is_dra72x()) + set_lpmode_selfrefresh(EMIF2_BASE); } inline u32 emif_num(u32 base) diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index 2f9693f28e9..f3172939889 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -147,8 +147,7 @@ void early_system_init(void) hw_data_init(); #ifdef CONFIG_SPL_BUILD - if (warm_reset() && - (is_omap44xx() || (omap_revision() == OMAP5430_ES1_0))) + if (warm_reset()) force_emif_self_refresh(); #endif watchdog_init(); diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S index 528313584f3..66a3b3d26c9 100644 --- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S @@ -16,9 +16,10 @@ #include <asm/arch/spl.h> #include <linux/linkage.h> +.arch_extension sec + #ifdef CONFIG_SPL ENTRY(save_boot_params) - ldr r1, =OMAP_SRAM_SCRATCH_BOOT_PARAMS str r0, [r1] b save_boot_params_ret @@ -26,14 +27,40 @@ ENDPROC(save_boot_params) #endif ENTRY(omap_smc1) - PUSH {r4-r12, lr} @ save registers - ROM code may pollute + push {r4-r12, lr} @ save registers - ROM code may pollute @ our registers - MOV r12, r0 @ Service - MOV r0, r1 @ Argument - DSB - DMB - .word 0xe1600070 @ SMC #0 - hand assembled for GCC versions - @ call ROM Code API for the service requested + mov r12, r0 @ Service + mov r0, r1 @ Argument - POP {r4-r12, pc} + dsb + dmb + smc 0 @ SMC #0 to enter monitor mode + @ call ROM Code API for the service requested + pop {r4-r12, pc} ENDPROC(omap_smc1) + +ENTRY(omap_smc_sec) + push {r4-r12, lr} @ save registers - ROM code may pollute + @ our registers + mov r6, #0xFF @ Indicate new Task call + mov r12, #0x00 @ Secure Service ID in R12 + + dsb + dmb + smc 0 @ SMC #0 to enter monitor mode + + b omap_smc_sec_end @ exit at end of the service execution + nop + + @ In case of IRQ happening in Secure, then ARM will branch here. + @ At that moment, IRQ will be pending and ARM will jump to Non Secure + @ IRQ handler + mov r12, #0xFE + + dsb + dmb + smc 0 @ SMC #0 to enter monitor mode + +omap_smc_sec_end: + pop {r4-r12, pc} +ENDPROC(omap_smc_sec) diff --git a/arch/arm/cpu/armv7/omap-common/mem-common.c b/arch/arm/cpu/armv7/omap-common/mem-common.c index fc4290c3c4e..d72e82e0283 100644 --- a/arch/arm/cpu/armv7/omap-common/mem-common.c +++ b/arch/arm/cpu/armv7/omap-common/mem-common.c @@ -20,8 +20,19 @@ #include <asm/arch/sys_proto.h> #include <command.h> #include <linux/mtd/omap_gpmc.h> +#include <jffs2/load_kernel.h> -struct gpmc *gpmc_cfg; +const struct gpmc *gpmc_cfg = (struct gpmc *)GPMC_BASE; + +#if defined(CONFIG_NOR) +char gpmc_cs0_flash = MTD_DEV_TYPE_NOR; +#elif defined(CONFIG_NAND) || defined(CONFIG_CMD_NAND) +char gpmc_cs0_flash = MTD_DEV_TYPE_NAND; +#elif defined(CONFIG_CMD_ONENAND) +char gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND; +#else +char gpmc_cs0_flash = -1; +#endif #if defined(CONFIG_OMAP34XX) /******************************************************** @@ -50,8 +61,8 @@ u32 mem_ok(u32 cs) } #endif -void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, - u32 size) +void enable_gpmc_cs_config(const u32 *gpmc_config, const struct gpmc_cs *cs, + u32 base, u32 size) { writel(0, &cs->config7); sdelay(1000); @@ -68,6 +79,81 @@ void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, sdelay(2000); } +void set_gpmc_cs0(int flash_type) +{ + const u32 *gpmc_regs; + u32 base, size; +#if defined(CONFIG_NOR) + const u32 gpmc_regs_nor[GPMC_MAX_REG] = { + STNOR_GPMC_CONFIG1, + STNOR_GPMC_CONFIG2, + STNOR_GPMC_CONFIG3, + STNOR_GPMC_CONFIG4, + STNOR_GPMC_CONFIG5, + STNOR_GPMC_CONFIG6, + STNOR_GPMC_CONFIG7 + }; +#endif +#if defined(CONFIG_NAND) || defined(CONFIG_CMD_NAND) + const u32 gpmc_regs_nand[GPMC_MAX_REG] = { + M_NAND_GPMC_CONFIG1, + M_NAND_GPMC_CONFIG2, + M_NAND_GPMC_CONFIG3, + M_NAND_GPMC_CONFIG4, + M_NAND_GPMC_CONFIG5, + M_NAND_GPMC_CONFIG6, + 0 + }; +#endif +#if defined(CONFIG_CMD_ONENAND) + const u32 gpmc_regs_onenand[GPMC_MAX_REG] = { + ONENAND_GPMC_CONFIG1, + ONENAND_GPMC_CONFIG2, + ONENAND_GPMC_CONFIG3, + ONENAND_GPMC_CONFIG4, + ONENAND_GPMC_CONFIG5, + ONENAND_GPMC_CONFIG6, + 0 + }; +#endif + + switch (flash_type) { +#if defined(CONFIG_NOR) + case MTD_DEV_TYPE_NOR: + gpmc_regs = gpmc_regs_nor; + base = CONFIG_SYS_FLASH_BASE; + size = (CONFIG_SYS_FLASH_SIZE > 0x08000000) ? GPMC_SIZE_256M : + ((CONFIG_SYS_FLASH_SIZE > 0x04000000) ? GPMC_SIZE_128M : + ((CONFIG_SYS_FLASH_SIZE > 0x02000000) ? GPMC_SIZE_64M : + ((CONFIG_SYS_FLASH_SIZE > 0x01000000) ? GPMC_SIZE_32M : + GPMC_SIZE_16M))); + break; +#endif +#if defined(CONFIG_NAND) || defined(CONFIG_CMD_NAND) + case MTD_DEV_TYPE_NAND: + gpmc_regs = gpmc_regs_nand; + base = CONFIG_SYS_NAND_BASE; + size = GPMC_SIZE_16M; + break; +#endif +#if defined(CONFIG_CMD_ONENAND) + case MTD_DEV_TYPE_ONENAND: + gpmc_regs = gpmc_regs_onenand; + base = CONFIG_SYS_ONENAND_BASE; + size = GPMC_SIZE_128M; + break; +#endif + default: + /* disable the GPMC0 config set by ROM code */ + writel(0, &gpmc_cfg->cs[0].config7); + sdelay(1000); + return; + } + + /* enable chip-select specific configurations */ + enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size); +} + /***************************************************** * gpmc_init(): init gpmc bus * Init GPMC for x16, MuxMode (SDRAM in x32). @@ -75,70 +161,14 @@ void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, *****************************************************/ void gpmc_init(void) { - /* putting a blanket check on GPMC based on ZeBu for now */ - gpmc_cfg = (struct gpmc *)GPMC_BASE; -#if defined(CONFIG_NOR) -/* configure GPMC for NOR */ - const u32 gpmc_regs[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1, - STNOR_GPMC_CONFIG2, - STNOR_GPMC_CONFIG3, - STNOR_GPMC_CONFIG4, - STNOR_GPMC_CONFIG5, - STNOR_GPMC_CONFIG6, - STNOR_GPMC_CONFIG7 - }; - u32 base = CONFIG_SYS_FLASH_BASE; - u32 size = (CONFIG_SYS_FLASH_SIZE > 0x08000000) ? GPMC_SIZE_256M : - /* > 64MB */ ((CONFIG_SYS_FLASH_SIZE > 0x04000000) ? GPMC_SIZE_128M : - /* > 32MB */ ((CONFIG_SYS_FLASH_SIZE > 0x02000000) ? GPMC_SIZE_64M : - /* > 16MB */ ((CONFIG_SYS_FLASH_SIZE > 0x01000000) ? GPMC_SIZE_32M : - /* min 16MB */ GPMC_SIZE_16M))); -#elif defined(CONFIG_NAND) || defined(CONFIG_CMD_NAND) -/* configure GPMC for NAND */ - const u32 gpmc_regs[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1, - M_NAND_GPMC_CONFIG2, - M_NAND_GPMC_CONFIG3, - M_NAND_GPMC_CONFIG4, - M_NAND_GPMC_CONFIG5, - M_NAND_GPMC_CONFIG6, - 0 - }; - u32 base = CONFIG_SYS_NAND_BASE; - u32 size = GPMC_SIZE_16M; - -#elif defined(CONFIG_CMD_ONENAND) - const u32 gpmc_regs[GPMC_MAX_REG] = { ONENAND_GPMC_CONFIG1, - ONENAND_GPMC_CONFIG2, - ONENAND_GPMC_CONFIG3, - ONENAND_GPMC_CONFIG4, - ONENAND_GPMC_CONFIG5, - ONENAND_GPMC_CONFIG6, - 0 - }; - u32 size = GPMC_SIZE_128M; - u32 base = CONFIG_SYS_ONENAND_BASE; -#else - const u32 gpmc_regs[GPMC_MAX_REG] = { 0, 0, 0, 0, 0, 0, 0 }; - u32 size = 0; - u32 base = 0; -#endif /* global settings */ writel(0x00000008, &gpmc_cfg->sysconfig); writel(0x00000000, &gpmc_cfg->irqstatus); writel(0x00000000, &gpmc_cfg->irqenable); /* disable timeout, set a safe reset value */ writel(0x00001ff0, &gpmc_cfg->timeout_control); -#ifdef CONFIG_NOR - writel(0x00000200, &gpmc_cfg->config); -#else - writel(0x00000012, &gpmc_cfg->config); -#endif - /* - * Disable the GPMC0 config set by ROM code - */ - writel(0, &gpmc_cfg->cs[0].config7); - sdelay(1000); - /* enable chip-select specific configurations */ - if (base != 0) - enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size); + writel(gpmc_cs0_flash == MTD_DEV_TYPE_NOR ? + 0x00000200 : 0x00000012, &gpmc_cfg->config); + + set_gpmc_cs0(gpmc_cs0_flash); } diff --git a/arch/arm/cpu/armv7/omap-common/sec-common.c b/arch/arm/cpu/armv7/omap-common/sec-common.c new file mode 100644 index 00000000000..246a2393dab --- /dev/null +++ b/arch/arm/cpu/armv7/omap-common/sec-common.c @@ -0,0 +1,139 @@ +/* + * + * Common security related functions for OMAP devices + * + * (C) Copyright 2016 + * Texas Instruments, <www.ti.com> + * + * Daniel Allred <d-allred@ti.com> + * Andreas Dannenberg <dannenberg@ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <stdarg.h> + +#include <asm/arch/sys_proto.h> +#include <asm/omap_common.h> +#include <asm/omap_sec_common.h> +#include <asm/spl.h> +#include <spl.h> + +/* Index for signature verify ROM API */ +#define API_HAL_KM_VERIFYCERTIFICATESIGNATURE_INDEX (0x0000000E) + +static uint32_t secure_rom_call_args[5] __aligned(ARCH_DMA_MINALIGN); + +u32 secure_rom_call(u32 service, u32 proc_id, u32 flag, ...) +{ + int i; + u32 num_args; + va_list ap; + + va_start(ap, flag); + + num_args = va_arg(ap, u32); + + if (num_args > 4) + return 1; + + /* Copy args to aligned args structure */ + for (i = 0; i < num_args; i++) + secure_rom_call_args[i + 1] = va_arg(ap, u32); + + secure_rom_call_args[0] = num_args; + + va_end(ap); + + /* if data cache is enabled, flush the aligned args structure */ + flush_dcache_range( + (unsigned int)&secure_rom_call_args[0], + (unsigned int)&secure_rom_call_args[0] + + roundup(sizeof(secure_rom_call_args), ARCH_DMA_MINALIGN)); + + return omap_smc_sec(service, proc_id, flag, secure_rom_call_args); +} + +static u32 find_sig_start(char *image, size_t size) +{ + char *image_end = image + size; + char *sig_start_magic = "CERT_"; + int magic_str_len = strlen(sig_start_magic); + char *ch; + + while (--image_end > image) { + if (*image_end == '_') { + ch = image_end - magic_str_len + 1; + if (!strncmp(ch, sig_start_magic, magic_str_len)) + return (u32)ch; + } + } + return 0; +} + +int secure_boot_verify_image(void **image, size_t *size) +{ + int result = 1; + u32 cert_addr, sig_addr; + size_t cert_size; + + /* Perform cache writeback on input buffer */ + flush_dcache_range( + (u32)*image, + (u32)*image + roundup(*size, ARCH_DMA_MINALIGN)); + + cert_addr = (uint32_t)*image; + sig_addr = find_sig_start((char *)*image, *size); + + if (sig_addr == 0) { + printf("No signature found in image!\n"); + result = 1; + goto auth_exit; + } + + *size = sig_addr - cert_addr; /* Subtract out the signature size */ + cert_size = *size; + + /* Check if image load address is 32-bit aligned */ + if (!IS_ALIGNED(cert_addr, 4)) { + printf("Image is not 4-byte aligned!\n"); + result = 1; + goto auth_exit; + } + + /* Image size also should be multiple of 4 */ + if (!IS_ALIGNED(cert_size, 4)) { + printf("Image size is not 4-byte aligned!\n"); + result = 1; + goto auth_exit; + } + + /* Call ROM HAL API to verify certificate signature */ + debug("%s: load_addr = %x, size = %x, sig_addr = %x\n", __func__, + cert_addr, cert_size, sig_addr); + + result = secure_rom_call( + API_HAL_KM_VERIFYCERTIFICATESIGNATURE_INDEX, 0, 0, + 4, cert_addr, cert_size, sig_addr, 0xFFFFFFFF); +auth_exit: + if (result != 0) { + printf("Authentication failed!\n"); + printf("Return Value = %08X\n", result); + hang(); + } + + /* + * Output notification of successful authentication as well the name of + * the signing certificate used to re-assure the user that the secure + * code is being processed as expected. However suppress any such log + * output in case of building for SPL and booting via YMODEM. This is + * done to avoid disturbing the YMODEM serial protocol transactions. + */ + if (!(IS_ENABLED(CONFIG_SPL_BUILD) && + IS_ENABLED(CONFIG_SPL_YMODEM_SUPPORT) && + spl_boot_device() == BOOT_DEVICE_UART)) + printf("Authentication passed: %s\n", (char *)sig_addr); + + return result; +} diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig index 85d6436904c..99a25f9ff37 100644 --- a/arch/arm/cpu/armv7/omap3/Kconfig +++ b/arch/arm/cpu/armv7/omap3/Kconfig @@ -6,55 +6,39 @@ choice config TARGET_AM3517_EVM bool "AM3517 EVM" - select SUPPORT_SPL config TARGET_MT_VENTOUX bool "TeeJet Mt.Ventoux" - select SUPPORT_SPL config TARGET_OMAP3_BEAGLE bool "TI OMAP3 BeagleBoard" - select SUPPORT_SPL select DM select DM_SERIAL select DM_GPIO config TARGET_CM_T35 bool "CompuLab CM-T3530 and CM-T3730 boards" - select SUPPORT_SPL config TARGET_CM_T3517 bool "CompuLab CM-T3517 boards" config TARGET_DEVKIT8000 bool "TimLL OMAP3 Devkit8000" - select SUPPORT_SPL select DM select DM_SERIAL select DM_GPIO config TARGET_OMAP3_EVM bool "TI OMAP3 EVM" - select SUPPORT_SPL - -config TARGET_OMAP3_EVM_QUICK_MMC - bool "TI OMAP3 EVM Quick MMC" - select SUPPORT_SPL - -config TARGET_OMAP3_EVM_QUICK_NAND - bool "TI OMAP3 EVM Quick NAND" - select SUPPORT_SPL config TARGET_OMAP3_IGEP00X0 bool "IGEP" - select SUPPORT_SPL select DM select DM_SERIAL select DM_GPIO config TARGET_OMAP3_OVERO bool "OMAP35xx Gumstix Overo" - select SUPPORT_SPL select DM select DM_SERIAL select DM_GPIO @@ -67,51 +51,42 @@ config TARGET_OMAP3_ZOOM1 config TARGET_AM3517_CRANE bool "am3517_crane" - select SUPPORT_SPL config TARGET_OMAP3_PANDORA bool "OMAP3 Pandora" config TARGET_ECO5PK bool "ECO5PK" - select SUPPORT_SPL config TARGET_TRICORDER bool "Tricorder" - select SUPPORT_SPL config TARGET_MCX bool "MCX" - select SUPPORT_SPL config TARGET_OMAP3_LOGIC bool "OMAP3 Logic" select DM select DM_SERIAL select DM_GPIO - select SUPPORT_SPL config TARGET_NOKIA_RX51 bool "Nokia RX51" config TARGET_TAO3530 bool "TAO3530" - select SUPPORT_SPL config TARGET_TWISTER bool "Twister" - select SUPPORT_SPL config TARGET_OMAP3_CAIRO bool "QUIPOS CAIRO" - select SUPPORT_SPL select DM select DM_SERIAL select DM_GPIO config TARGET_SNIPER bool "LG Optimus Black" - select SUPPORT_SPL select DM select DM_SERIAL select DM_GPIO diff --git a/arch/arm/cpu/armv7/omap3/spl_id_nand.c b/arch/arm/cpu/armv7/omap3/spl_id_nand.c index db6de0911bf..0e2f0a2f6d6 100644 --- a/arch/arm/cpu/armv7/omap3/spl_id_nand.c +++ b/arch/arm/cpu/armv7/omap3/spl_id_nand.c @@ -13,62 +13,45 @@ */ #include <common.h> +#include <jffs2/load_kernel.h> #include <linux/mtd/nand.h> +#include <linux/mtd/omap_gpmc.h> #include <asm/io.h> #include <asm/arch/sys_proto.h> #include <asm/arch/mem.h> -static struct gpmc *gpmc_config = (struct gpmc *)GPMC_BASE; - -/* nand_command: Send a flash command to the flash chip */ -static void nand_command(u8 command) -{ - writeb(command, &gpmc_config->cs[0].nand_cmd); - - if (command == NAND_CMD_RESET) { - unsigned char ret_val; - writeb(NAND_CMD_STATUS, &gpmc_config->cs[0].nand_cmd); - do { - /* Wait until ready */ - ret_val = readl(&gpmc_config->cs[0].nand_dat); - } while ((ret_val & NAND_STATUS_READY) != NAND_STATUS_READY); - } -} - /* * Many boards will want to know the results of the NAND_CMD_READID command * in order to decide what to do about DDR initialization. This function * allows us to do that very early and to pass those results back to the * board so it can make whatever decisions need to be made. */ -void identify_nand_chip(int *mfr, int *id) +int identify_nand_chip(int *mfr, int *id) { - /* Make sure that we have setup GPMC for NAND correctly. */ - writel(M_NAND_GPMC_CONFIG1, &gpmc_config->cs[0].config1); - writel(M_NAND_GPMC_CONFIG2, &gpmc_config->cs[0].config2); - writel(M_NAND_GPMC_CONFIG3, &gpmc_config->cs[0].config3); - writel(M_NAND_GPMC_CONFIG4, &gpmc_config->cs[0].config4); - writel(M_NAND_GPMC_CONFIG5, &gpmc_config->cs[0].config5); - writel(M_NAND_GPMC_CONFIG6, &gpmc_config->cs[0].config6); + int loops = 1000; - /* - * Enable the config. The CS size goes in bits 11:8. We set - * bit 6 to enable the CS and the base address goes into bits 5:0. - */ - writel((GPMC_SIZE_128M << 8) | (GPMC_CS_ENABLE << 6) | - ((NAND_BASE >> 24) & GPMC_BASEADDR_MASK), - &gpmc_config->cs[0].config7); + /* Make sure that we have setup GPMC for NAND correctly. */ + set_gpmc_cs0(MTD_DEV_TYPE_NAND); sdelay(2000); /* Issue a RESET and then READID */ - nand_command(NAND_CMD_RESET); - nand_command(NAND_CMD_READID); + writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd); + writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd); + while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY) + != NAND_STATUS_READY) { + sdelay(100); + if (--loops == 0) + return 1; + } + writeb(NAND_CMD_READID, &gpmc_cfg->cs[0].nand_cmd); /* Set the address to read to 0x0 */ - writeb(0x0, &gpmc_config->cs[0].nand_adr); + writeb(0x0, &gpmc_cfg->cs[0].nand_adr); /* Read off the manufacturer and device id. */ - *mfr = readb(&gpmc_config->cs[0].nand_dat); - *id = readb(&gpmc_config->cs[0].nand_dat); + *mfr = readb(&gpmc_cfg->cs[0].nand_dat); + *id = readb(&gpmc_cfg->cs[0].nand_dat); + + return 0; } diff --git a/arch/arm/cpu/armv7/omap5/Kconfig b/arch/arm/cpu/armv7/omap5/Kconfig index 4fb5ef95cbe..a8600b102e7 100644 --- a/arch/arm/cpu/armv7/omap5/Kconfig +++ b/arch/arm/cpu/armv7/omap5/Kconfig @@ -13,6 +13,7 @@ config TARGET_OMAP5_UEVM config TARGET_DRA7XX_EVM bool "TI DRA7XX" select TI_I2C_BOARD_DETECT + select PHYS_64BIT config TARGET_AM57XX_EVM bool "AM57XX" diff --git a/arch/arm/cpu/armv7/omap5/config.mk b/arch/arm/cpu/armv7/omap5/config.mk index a7e55a5e244..286ca8688d7 100644 --- a/arch/arm/cpu/armv7/omap5/config.mk +++ b/arch/arm/cpu/armv7/omap5/config.mk @@ -15,5 +15,8 @@ else ALL-y += MLO endif else +ifeq ($(CONFIG_TI_SECURE_DEVICE),y) +ALL-$(CONFIG_SPL_LOAD_FIT) += u-boot_HS.img +endif ALL-y += u-boot.img endif diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 62dd275f7ee..fc991358248 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -160,7 +160,7 @@ static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = { static const struct dpll_params per_dpll_params_768mhz_dra7xx[NUM_SYS_CLKS] = { {32, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 12 MHz */ - {96, 4, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 20 MHz */ + {96, 4, 4, 1, 3, 4, 10, 2, -1, -1, -1, -1}, /* 20 MHz */ {160, 6, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 16.8 MHz */ {20, 0, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 19.2 MHz */ {192, 12, 4, 1, 3, 4, 4, 2, -1, -1, -1, -1}, /* 26 MHz */ @@ -318,6 +318,7 @@ struct pmic_data palmas = { .i2c_slave_addr = SMPS_I2C_SLAVE_ADDR, .pmic_bus_init = sri2c_init, .pmic_write = omap_vc_bypass_send_value, + .gpio_en = 0, }; /* The TPS659038 and TPS65917 are software-compatible, use common struct */ @@ -332,6 +333,7 @@ struct pmic_data tps659038 = { .i2c_slave_addr = TPS659038_I2C_SLAVE_ADDR, .pmic_bus_init = gpi2c_init, .pmic_write = palmas_i2c_write_u8, + .gpio_en = 0, }; struct vcores_data omap5430_volts = { diff --git a/arch/arm/cpu/armv7/psci-common.c b/arch/arm/cpu/armv7/psci-common.c new file mode 100644 index 00000000000..8cb4107be61 --- /dev/null +++ b/arch/arm/cpu/armv7/psci-common.c @@ -0,0 +1,39 @@ +/* + * Common PSCI functions + * + * Copyright (C) 2016 Chen-Yu Tsai + * Author: Chen-Yu Tsai <wens@csie.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <config.h> +#include <asm/armv7.h> +#include <asm/macro.h> +#include <asm/psci.h> +#include <asm/secure.h> +#include <linux/linkage.h> + +static u32 psci_target_pc[CONFIG_ARMV7_PSCI_NR_CPUS] __secure_data = { 0 }; + +void __secure psci_save_target_pc(int cpu, u32 pc) +{ + psci_target_pc[cpu] = pc; + dsb(); +} + +u32 __secure psci_get_target_pc(int cpu) +{ + return psci_target_pc[cpu]; +} + diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S index ab408378fca..f80f6e20d1e 100644 --- a/arch/arm/cpu/armv7/psci.S +++ b/arch/arm/cpu/armv7/psci.S @@ -46,20 +46,62 @@ ENTRY(default_psci_vector) ENDPROC(default_psci_vector) .weak default_psci_vector +ENTRY(psci_version) ENTRY(psci_cpu_suspend) ENTRY(psci_cpu_off) ENTRY(psci_cpu_on) +ENTRY(psci_affinity_info) ENTRY(psci_migrate) +ENTRY(psci_migrate_info_type) +ENTRY(psci_migrate_info_up_cpu) +ENTRY(psci_system_off) +ENTRY(psci_system_reset) +ENTRY(psci_features) +ENTRY(psci_cpu_freeze) +ENTRY(psci_cpu_default_suspend) +ENTRY(psci_node_hw_state) +ENTRY(psci_system_suspend) +ENTRY(psci_set_suspend_mode) +ENTRY(psi_stat_residency) +ENTRY(psci_stat_count) mov r0, #ARM_PSCI_RET_NI @ Return -1 (Not Implemented) mov pc, lr +ENDPROC(psci_stat_count) +ENDPROC(psi_stat_residency) +ENDPROC(psci_set_suspend_mode) +ENDPROC(psci_system_suspend) +ENDPROC(psci_node_hw_state) +ENDPROC(psci_cpu_default_suspend) +ENDPROC(psci_cpu_freeze) +ENDPROC(psci_features) +ENDPROC(psci_system_reset) +ENDPROC(psci_system_off) +ENDPROC(psci_migrate_info_up_cpu) +ENDPROC(psci_migrate_info_type) ENDPROC(psci_migrate) +ENDPROC(psci_affinity_info) ENDPROC(psci_cpu_on) ENDPROC(psci_cpu_off) ENDPROC(psci_cpu_suspend) +ENDPROC(psci_version) +.weak psci_version .weak psci_cpu_suspend .weak psci_cpu_off .weak psci_cpu_on +.weak psci_affinity_info .weak psci_migrate +.weak psci_migrate_info_type +.weak psci_migrate_info_up_cpu +.weak psci_system_off +.weak psci_system_reset +.weak psci_features +.weak psci_cpu_freeze +.weak psci_cpu_default_suspend +.weak psci_node_hw_state +.weak psci_system_suspend +.weak psci_set_suspend_mode +.weak psi_stat_residency +.weak psci_stat_count _psci_table: .word ARM_PSCI_FN_CPU_SUSPEND @@ -70,6 +112,42 @@ _psci_table: .word psci_cpu_on .word ARM_PSCI_FN_MIGRATE .word psci_migrate + .word ARM_PSCI_0_2_FN_PSCI_VERSION + .word psci_version + .word ARM_PSCI_0_2_FN_CPU_SUSPEND + .word psci_cpu_suspend + .word ARM_PSCI_0_2_FN_CPU_OFF + .word psci_cpu_off + .word ARM_PSCI_0_2_FN_CPU_ON + .word psci_cpu_on + .word ARM_PSCI_0_2_FN_AFFINITY_INFO + .word psci_affinity_info + .word ARM_PSCI_0_2_FN_MIGRATE + .word psci_migrate + .word ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE + .word psci_migrate_info_type + .word ARM_PSCI_0_2_FN_MIGRATE_INFO_UP_CPU + .word psci_migrate_info_up_cpu + .word ARM_PSCI_0_2_FN_SYSTEM_OFF + .word psci_system_off + .word ARM_PSCI_0_2_FN_SYSTEM_RESET + .word psci_system_reset + .word ARM_PSCI_1_0_FN_PSCI_FEATURES + .word psci_features + .word ARM_PSCI_1_0_FN_CPU_FREEZE + .word psci_cpu_freeze + .word ARM_PSCI_1_0_FN_CPU_DEFAULT_SUSPEND + .word psci_cpu_default_suspend + .word ARM_PSCI_1_0_FN_NODE_HW_STATE + .word psci_node_hw_state + .word ARM_PSCI_1_0_FN_SYSTEM_SUSPEND + .word psci_system_suspend + .word ARM_PSCI_1_0_FN_SET_SUSPEND_MODE + .word psci_set_suspend_mode + .word ARM_PSCI_1_0_FN_STAT_RESIDENCY + .word psi_stat_residency + .word ARM_PSCI_1_0_FN_STAT_COUNT + .word psci_stat_count .word 0 .word 0 @@ -196,29 +274,56 @@ ENTRY(psci_cpu_off_common) bx lr ENDPROC(psci_cpu_off_common) -@ expects CPU ID in r0 and returns stack top in r0 -ENTRY(psci_get_cpu_stack_top) - mov r3, #0x400 @ 1kB of stack per CPU - mul r0, r0, r3 - - ldr r3, =psci_text_end @ end of monitor text - add r3, r3, #0x2000 @ Skip two pages - lsr r3, r3, #12 @ Align to start of page - lsl r3, r3, #12 - sub r3, r3, #4 @ reserve 1 word for target PC - sub r0, r3, r0 @ here's our stack! - +@ The stacks are allocated in reverse order, i.e. +@ the stack for CPU0 has the highest memory address. +@ +@ -------------------- __secure_stack_end +@ | CPU0 target PC | +@ |------------------| +@ | | +@ | CPU0 stack | +@ | | +@ |------------------| __secure_stack_end - 1KB +@ | . | +@ | . | +@ | . | +@ | . | +@ -------------------- __secure_stack_start +@ +@ This expects CPU ID in r0 and returns stack top in r0 +LENTRY(psci_get_cpu_stack_top) + @ stack top = __secure_stack_end - (cpuid << ARM_PSCI_STACK_SHIFT) + ldr r3, =__secure_stack_end + sub r0, r3, r0, LSL #ARM_PSCI_STACK_SHIFT + sub r0, r0, #4 @ Save space for target PC bx lr ENDPROC(psci_get_cpu_stack_top) +@ {r0, r1, r2, ip} from _do_nonsec_entry(kernel_entry, 0, machid, r2) in +@ arch/arm/lib/bootm.c:boot_jump_linux() must remain unchanged across +@ this function. +ENTRY(psci_stack_setup) + mov r6, lr + mov r7, r0 + bl psci_get_cpu_id @ CPU ID => r0 + bl psci_get_cpu_stack_top @ stack top => r0 + mov sp, r0 + mov r0, r7 + bx r6 +ENDPROC(psci_stack_setup) + +ENTRY(psci_arch_init) + mov pc, lr +ENDPROC(psci_arch_init) +.weak psci_arch_init + ENTRY(psci_cpu_entry) bl psci_enable_smp bl _nonsec_init bl psci_get_cpu_id @ CPU ID => r0 - bl psci_get_cpu_stack_top @ stack top => r0 - ldr r0, [r0] @ target PC at stack top + bl psci_get_target_pc @ target PC => r0 b _do_nonsec_entry ENDPROC(psci_cpu_entry) diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile index c2085101685..b35b9df4a9d 100644 --- a/arch/arm/cpu/armv7/sunxi/Makefile +++ b/arch/arm/cpu/armv7/sunxi/Makefile @@ -14,7 +14,6 @@ obj-$(CONFIG_MACH_SUN8I_H3) += tzpc.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_ARMV7_PSCI) += psci.o -obj-$(CONFIG_ARMV7_PSCI) += psci_head.o endif ifdef CONFIG_SPL_BUILD diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c index a118e9d0c4a..766b8c79d93 100644 --- a/arch/arm/cpu/armv7/sunxi/psci.c +++ b/arch/arm/cpu/armv7/sunxi/psci.c @@ -17,11 +17,11 @@ #include <asm/gic.h> #include <asm/io.h> #include <asm/psci.h> +#include <asm/secure.h> #include <asm/system.h> #include <linux/bitops.h> -#define __secure __attribute__ ((section ("._secure.text"))) #define __irq __attribute__ ((interrupt ("IRQ"))) #define GICD_BASE (SUNXI_GIC400_BASE + GIC_DIST_OFFSET) @@ -53,16 +53,16 @@ static void __secure __mdelay(u32 ms) u32 reg = ONE_MS * ms; cp15_write_cntp_tval(reg); - ISB; + isb(); cp15_write_cntp_ctl(3); do { - ISB; + isb(); reg = cp15_read_cntp_ctl(); } while (!(reg & BIT(2))); cp15_write_cntp_ctl(0); - ISB; + isb(); } static void __secure clamp_release(u32 __maybe_unused *clamp) @@ -164,7 +164,7 @@ static u32 __secure cp15_read_scr(void) static void __secure cp15_write_scr(u32 scr) { asm volatile ("mcr p15, 0, %0, c1, c1, 0" : : "r" (scr)); - ISB; + isb(); } /* @@ -190,7 +190,7 @@ void __secure __irq psci_fiq_enter(void) /* End of interrupt */ writel(reg, GICC_BASE + GICC_EOIR); - DSB; + dsb(); /* Get CPU number */ cpu = (reg >> 10) & 0x7; @@ -209,9 +209,8 @@ int __secure psci_cpu_on(u32 __always_unused unused, u32 mpidr, u32 pc) (struct sunxi_cpucfg_reg *)SUNXI_CPUCFG_BASE; u32 cpu = (mpidr & 0x3); - /* store target PC at target CPU stack top */ - writel(pc, psci_get_cpu_stack_top(cpu)); - DSB; + /* store target PC */ + psci_save_target_pc(cpu, pc); /* Set secondary core power on PC */ writel((u32)&psci_cpu_entry, &cpucfg->priv0); @@ -243,14 +242,14 @@ void __secure psci_cpu_off(void) /* Ask CPU0 via SGI15 to pull the rug... */ writel(BIT(16) | 15, GICD_BASE + GICD_SGIR); - DSB; + dsb(); /* Wait to be turned off */ while (1) wfi(); } -void __secure sunxi_gic_init(void) +void __secure psci_arch_init(void) { u32 reg; diff --git a/arch/arm/cpu/armv7/sunxi/psci_head.S b/arch/arm/cpu/armv7/sunxi/psci_head.S deleted file mode 100644 index 8fa823d1df3..00000000000 --- a/arch/arm/cpu/armv7/sunxi/psci_head.S +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright (C) 2013 - ARM Ltd - * Author: Marc Zyngier <marc.zyngier@arm.com> - * - * Based on code by Carl van Schaik <carl@ok-labs.com>. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#include <config.h> -#include <linux/linkage.h> - -#include <asm/arch-armv7/generictimer.h> -#include <asm/gic.h> -#include <asm/macro.h> -#include <asm/psci.h> -#include <asm/arch/cpu.h> - -/* - * Memory layout: - * - * SECURE_RAM to text_end : - * ._secure_text section - * text_end to ALIGN_PAGE(text_end): - * nothing - * ALIGN_PAGE(text_end) to ALIGN_PAGE(text_end) + 0x1000) - * 1kB of stack per CPU (4 CPUs max). - */ - - .pushsection ._secure.text, "ax" - - .arch_extension sec - -#define GICD_BASE (SUNXI_GIC400_BASE + 0x1000) -#define GICC_BASE (SUNXI_GIC400_BASE + 0x2000) - -@ {r0, r1, r2, ip} from _do_nonsec_entry(kernel_entry, 0, machid, r2) in -@ arch/arm/lib/bootm.c:boot_jump_linux() must remain unchanged across -@ this function. -ENTRY(psci_arch_init) - mov r6, lr - mov r7, r0 - bl psci_get_cpu_id @ CPU ID => r0 - bl psci_get_cpu_stack_top @ stack top => r0 - sub r0, r0, #4 @ Save space for target PC - mov sp, r0 - mov r0, r7 - mov lr, r6 - - push {r0, r1, r2, ip, lr} - bl sunxi_gic_init - pop {r0, r1, r2, ip, pc} -ENDPROC(psci_arch_init) - -ENTRY(psci_text_end) - .popsection diff --git a/arch/arm/cpu/armv7/virt-dt.c b/arch/arm/cpu/armv7/virt-dt.c index 32c368f1455..707dad4829a 100644 --- a/arch/arm/cpu/armv7/virt-dt.c +++ b/arch/arm/cpu/armv7/virt-dt.c @@ -26,69 +26,6 @@ #include <asm/armv7.h> #include <asm/psci.h> -static int fdt_psci(void *fdt) -{ -#ifdef CONFIG_ARMV7_PSCI - int nodeoff; - int tmp; - - nodeoff = fdt_path_offset(fdt, "/cpus"); - if (nodeoff < 0) { - printf("couldn't find /cpus\n"); - return nodeoff; - } - - /* add 'enable-method = "psci"' to each cpu node */ - for (tmp = fdt_first_subnode(fdt, nodeoff); - tmp >= 0; - tmp = fdt_next_subnode(fdt, tmp)) { - const struct fdt_property *prop; - int len; - - prop = fdt_get_property(fdt, tmp, "device_type", &len); - if (!prop) - continue; - if (len < 4) - continue; - if (strcmp(prop->data, "cpu")) - continue; - - fdt_setprop_string(fdt, tmp, "enable-method", "psci"); - } - - nodeoff = fdt_path_offset(fdt, "/psci"); - if (nodeoff < 0) { - nodeoff = fdt_path_offset(fdt, "/"); - if (nodeoff < 0) - return nodeoff; - - nodeoff = fdt_add_subnode(fdt, nodeoff, "psci"); - if (nodeoff < 0) - return nodeoff; - } - - tmp = fdt_setprop_string(fdt, nodeoff, "compatible", "arm,psci"); - if (tmp) - return tmp; - tmp = fdt_setprop_string(fdt, nodeoff, "method", "smc"); - if (tmp) - return tmp; - tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_suspend", ARM_PSCI_FN_CPU_SUSPEND); - if (tmp) - return tmp; - tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_off", ARM_PSCI_FN_CPU_OFF); - if (tmp) - return tmp; - tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_on", ARM_PSCI_FN_CPU_ON); - if (tmp) - return tmp; - tmp = fdt_setprop_u32(fdt, nodeoff, "migrate", ARM_PSCI_FN_MIGRATE); - if (tmp) - return tmp; -#endif - return 0; -} - int armv7_apply_memory_carveout(u64 *start, u64 *size) { #ifdef CONFIG_ARMV7_SECURE_RESERVE_SIZE diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c index 9c533060b85..d33e5c61a9c 100644 --- a/arch/arm/cpu/armv7/virt-v7.c +++ b/arch/arm/cpu/armv7/virt-v7.c @@ -54,10 +54,12 @@ static void relocate_secure_section(void) { #ifdef CONFIG_ARMV7_SECURE_BASE size_t sz = __secure_end - __secure_start; + unsigned long szflush = ALIGN(sz + 1, CONFIG_SYS_CACHELINE_SIZE); memcpy((void *)CONFIG_ARMV7_SECURE_BASE, __secure_start, sz); + flush_dcache_range(CONFIG_ARMV7_SECURE_BASE, - CONFIG_ARMV7_SECURE_BASE + sz + 1); + CONFIG_ARMV7_SECURE_BASE + szflush); protect_secure_section(); invalidate_icache_all(); #endif diff --git a/arch/arm/cpu/armv7m/config.mk b/arch/arm/cpu/armv7m/config.mk index 4a53006b6a7..db4660e15da 100644 --- a/arch/arm/cpu/armv7m/config.mk +++ b/arch/arm/cpu/armv7m/config.mk @@ -5,4 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_CPPFLAGS += -march=armv7-m -mthumb +PLATFORM_CPPFLAGS += -march=armv7-m -mthumb -mno-unaligned-access diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 3d19bbfbe24..7e1fc4cbf94 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -1,6 +1,24 @@ if ARM64 config ARMV8_MULTIENTRY - boolean "Enable multiple CPUs to enter into U-Boot" + bool "Enable multiple CPUs to enter into U-Boot" + +config ARMV8_SPIN_TABLE + bool "Support spin-table enable method" + depends on ARMV8_MULTIENTRY && OF_LIBFDT + help + Say Y here to support "spin-table" enable method for booting Linux. + + To use this feature, you must do: + - Specify enable-method = "spin-table" in each CPU node in the + Device Tree you are using to boot the kernel + - Let secondary CPUs in U-Boot (in a board specific manner) + before the master CPU jumps to the kernel + + U-Boot automatically does: + - Set "cpu-release-addr" property of each CPU node + (overwrites it if already exists). + - Reserve the code for the spin-table and the release address + via a /memreserve/ region in the Device Tree. endif diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index bf8644ccd2e..dea14657d9a 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -15,6 +15,11 @@ obj-y += cache.o obj-y += tlb.o obj-y += transition.o obj-y += fwcall.o +obj-y += cpu-dt.o +ifndef CONFIG_SPL_BUILD +obj-$(CONFIG_ARMV8_SPIN_TABLE) += spin_table.o spin_table_v8.o +endif +obj-$(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) += sec_firmware.o sec_firmware_asm.o obj-$(CONFIG_FSL_LAYERSCAPE) += fsl-layerscape/ obj-$(CONFIG_S32V234) += s32v234/ diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 1615542a99f..cd3f6c10ae1 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -35,7 +35,7 @@ DECLARE_GLOBAL_DATA_PTR; * off: FFF */ -static u64 get_tcr(int el, u64 *pips, u64 *pva_bits) +u64 get_tcr(int el, u64 *pips, u64 *pva_bits) { u64 max_addr = 0; u64 ips, va_bits; @@ -44,7 +44,7 @@ static u64 get_tcr(int el, u64 *pips, u64 *pva_bits) /* Find the largest address we need to support */ for (i = 0; mem_map[i].size || mem_map[i].attrs; i++) - max_addr = max(max_addr, mem_map[i].base + mem_map[i].size); + max_addr = max(max_addr, mem_map[i].virt + mem_map[i].size); /* Calculate the maximum physical (and thus virtual) address */ if (max_addr > (1ULL << 44)) { @@ -167,49 +167,6 @@ static void set_pte_table(u64 *pte, u64 *table) *pte = PTE_TYPE_TABLE | (ulong)table; } -/* Add one mm_region map entry to the page tables */ -static void add_map(struct mm_region *map) -{ - u64 *pte; - u64 addr = map->base; - u64 size = map->size; - u64 attrs = map->attrs | PTE_TYPE_BLOCK | PTE_BLOCK_AF; - u64 blocksize; - int level; - u64 *new_table; - - while (size) { - pte = find_pte(addr, 0); - if (pte && (pte_type(pte) == PTE_TYPE_FAULT)) { - debug("Creating table for addr 0x%llx\n", addr); - new_table = create_table(); - set_pte_table(pte, new_table); - } - - for (level = 1; level < 4; level++) { - pte = find_pte(addr, level); - blocksize = 1ULL << level2shift(level); - debug("Checking if pte fits for addr=%llx size=%llx " - "blocksize=%llx\n", addr, size, blocksize); - if (size >= blocksize && !(addr & (blocksize - 1))) { - /* Page fits, create block PTE */ - debug("Setting PTE %p to block addr=%llx\n", - pte, addr); - *pte = addr | attrs; - addr += blocksize; - size -= blocksize; - break; - } else if ((pte_type(pte) == PTE_TYPE_FAULT)) { - /* Page doesn't fit, create subpages */ - debug("Creating subtable for addr 0x%llx " - "blksize=%llx\n", addr, blocksize); - new_table = create_table(); - set_pte_table(pte, new_table); - } - } - } -} - /* Splits a block PTE into table with subpages spanning the old block */ static void split_block(u64 *pte, int level) { @@ -241,6 +198,58 @@ static void split_block(u64 *pte, int level) set_pte_table(pte, new_table); } +/* Add one mm_region map entry to the page tables */ +static void add_map(struct mm_region *map) +{ + u64 *pte; + u64 virt = map->virt; + u64 phys = map->phys; + u64 size = map->size; + u64 attrs = map->attrs | PTE_TYPE_BLOCK | PTE_BLOCK_AF; + u64 blocksize; + int level; + u64 *new_table; + + while (size) { + pte = find_pte(virt, 0); + if (pte && (pte_type(pte) == PTE_TYPE_FAULT)) { + debug("Creating table for virt 0x%llx\n", virt); + new_table = create_table(); + set_pte_table(pte, new_table); + } + + for (level = 1; level < 4; level++) { + pte = find_pte(virt, level); + if (!pte) + panic("pte not found\n"); + + blocksize = 1ULL << level2shift(level); + debug("Checking if pte fits for virt=%llx size=%llx blocksize=%llx\n", + virt, size, blocksize); + if (size >= blocksize && !(virt & (blocksize - 1))) { + /* Page fits, create block PTE */ + debug("Setting PTE %p to block virt=%llx\n", + pte, virt); + *pte = phys | attrs; + virt += blocksize; + phys += blocksize; + size -= blocksize; + break; + } else if (pte_type(pte) == PTE_TYPE_FAULT) { + /* Page doesn't fit, create subpages */ + debug("Creating subtable for virt 0x%llx blksize=%llx\n", + virt, blocksize); + new_table = create_table(); + set_pte_table(pte, new_table); + } else if (pte_type(pte) == PTE_TYPE_BLOCK) { + debug("Split block into subtable for virt 0x%llx blksize=0x%llx\n", + virt, blocksize); + split_block(pte, level); + } + } + } +} + enum pte_type { PTE_INVAL, PTE_BLOCK, @@ -265,7 +274,7 @@ static int count_required_pts(u64 addr, int level, u64 maxaddr) for (i = 0; mem_map[i].size || mem_map[i].attrs; i++) { struct mm_region *map = &mem_map[i]; - u64 start = map->base; + u64 start = map->virt; u64 end = start + map->size; /* Check if the PTE would overlap with the map */ @@ -349,10 +358,13 @@ __weak u64 get_page_table_size(void) return size; } -static void setup_pgtables(void) +void setup_pgtables(void) { int i; + if (!gd->arch.tlb_fillptr || !gd->arch.tlb_addr) + panic("Page table pointer not setup."); + /* * Allocate the first level we're on with invalidate entries. * If the starting level is 0 (va_bits >= 39), then this is our @@ -363,14 +375,12 @@ static void setup_pgtables(void) /* Now add all MMU table entries one after another to the table */ for (i = 0; mem_map[i].size || mem_map[i].attrs; i++) add_map(&mem_map[i]); - - /* Create the same thing once more for our emergency page table */ - create_table(); } static void setup_all_pgtables(void) { u64 tlb_addr = gd->arch.tlb_addr; + u64 tlb_size = gd->arch.tlb_size; /* Reset the fill ptr */ gd->arch.tlb_fillptr = tlb_addr; @@ -379,10 +389,13 @@ static void setup_all_pgtables(void) setup_pgtables(); /* Create emergency page tables */ + gd->arch.tlb_size -= (uintptr_t)gd->arch.tlb_fillptr - + (uintptr_t)gd->arch.tlb_addr; gd->arch.tlb_addr = gd->arch.tlb_fillptr; setup_pgtables(); gd->arch.tlb_emerg = gd->arch.tlb_addr; gd->arch.tlb_addr = tlb_addr; + gd->arch.tlb_size = tlb_size; } /* to activate the MMU we need to set up virtual memory */ @@ -527,6 +540,9 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, debug("start=%lx size=%lx\n", (ulong)start, (ulong)size); + if (!gd->arch.tlb_emerg) + panic("Emergency page table not setup."); + /* * We can not modify page tables that we're currently running on, * so we first need to switch to the "emergency" page tables where diff --git a/arch/arm/cpu/armv8/cpu-dt.c b/arch/arm/cpu/armv8/cpu-dt.c new file mode 100644 index 00000000000..9ffb49c37cd --- /dev/null +++ b/arch/arm/cpu/armv8/cpu-dt.c @@ -0,0 +1,31 @@ +/* + * Copyright 2016 NXP Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/psci.h> +#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT +#include <asm/armv8/sec_firmware.h> +#endif + +int psci_update_dt(void *fdt) +{ +#ifdef CONFIG_MP +#if defined(CONFIG_ARMV8_PSCI) +#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT + /* + * If the PSCI in SEC Firmware didn't work, avoid to update the + * device node of PSCI. But still return 0 instead of an error + * number to support detecting PSCI dynamically and then switching + * the SMP boot method between PSCI and spin-table. + */ + if (sec_firmware_support_psci_version() == 0xffffffff) + return 0; +#endif + fdt_psci(fdt); +#endif +#endif + return 0; +} diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index eb2cbc3f7e2..8c1317faea2 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -10,6 +10,7 @@ obj-y += soc.o obj-$(CONFIG_MP) += mp.o obj-$(CONFIG_OF_LIBFDT) += fdt.o obj-$(CONFIG_SPL) += spl.o +obj-$(CONFIG_FSL_LS_PPA) += ppa.o ifneq ($(CONFIG_FSL_LSCH3),) obj-y += fsl_lsch3_speed.o @@ -32,3 +33,7 @@ endif ifneq ($(CONFIG_LS1012A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls1012a_serdes.o endif + +ifneq ($(CONFIG_LS1046A),) +obj-$(CONFIG_SYS_HAS_SERDES) += ls1046a_serdes.o +endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 8062106e3e9..e12b7735506 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -23,16 +23,13 @@ #ifdef CONFIG_FSL_ESDHC #include <fsl_esdhc.h> #endif +#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT +#include <asm/armv8/sec_firmware.h> +#endif DECLARE_GLOBAL_DATA_PTR; -static struct mm_region layerscape_mem_map[] = { - { - /* List terminator */ - 0, - } -}; -struct mm_region *mem_map = layerscape_mem_map; +struct mm_region *mem_map = early_map; void cpu_name(char *name) { @@ -56,355 +53,106 @@ void cpu_name(char *name) } #ifndef CONFIG_SYS_DCACHE_OFF -static void set_pgtable_section(u64 *page_table, u64 index, u64 section, - u64 memory_type, u64 attribute) -{ - u64 value; - - value = section | PTE_TYPE_BLOCK | PTE_BLOCK_AF; - value |= PMD_ATTRINDX(memory_type); - value |= attribute; - page_table[index] = value; -} - -static void set_pgtable_table(u64 *page_table, u64 index, u64 *table_addr) -{ - u64 value; - - value = (u64)table_addr | PTE_TYPE_TABLE; - page_table[index] = value; -} - -/* - * Set the block entries according to the information of the table. - */ -static int set_block_entry(const struct sys_mmu_table *list, - struct table_info *table) -{ - u64 block_size = 0, block_shift = 0; - u64 block_addr, index; - int j; - - if (table->entry_size == BLOCK_SIZE_L1) { - block_size = BLOCK_SIZE_L1; - block_shift = SECTION_SHIFT_L1; - } else if (table->entry_size == BLOCK_SIZE_L2) { - block_size = BLOCK_SIZE_L2; - block_shift = SECTION_SHIFT_L2; - } else { - return -EINVAL; - } - - block_addr = list->phys_addr; - index = (list->virt_addr - table->table_base) >> block_shift; - - for (j = 0; j < (list->size >> block_shift); j++) { - set_pgtable_section(table->ptr, - index, - block_addr, - list->memory_type, - list->attribute); - block_addr += block_size; - index++; - } - - return 0; -} - -/* - * Find the corresponding table entry for the list. - */ -static int find_table(const struct sys_mmu_table *list, - struct table_info *table, u64 *level0_table) -{ - u64 index = 0, level = 0; - u64 *level_table = level0_table; - u64 temp_base = 0, block_size = 0, block_shift = 0; - - while (level < 3) { - if (level == 0) { - block_size = BLOCK_SIZE_L0; - block_shift = SECTION_SHIFT_L0; - } else if (level == 1) { - block_size = BLOCK_SIZE_L1; - block_shift = SECTION_SHIFT_L1; - } else if (level == 2) { - block_size = BLOCK_SIZE_L2; - block_shift = SECTION_SHIFT_L2; - } - - index = 0; - while (list->virt_addr >= temp_base) { - index++; - temp_base += block_size; - } - - temp_base -= block_size; - - if ((level_table[index - 1] & PTE_TYPE_MASK) == - PTE_TYPE_TABLE) { - level_table = (u64 *)(level_table[index - 1] & - ~PTE_TYPE_MASK); - level++; - continue; - } else { - if (level == 0) - return -EINVAL; - - if ((list->phys_addr + list->size) > - (temp_base + block_size * NUM_OF_ENTRY)) - return -EINVAL; - - /* - * Check the address and size of the list member is - * aligned with the block size. - */ - if (((list->phys_addr & (block_size - 1)) != 0) || - ((list->size & (block_size - 1)) != 0)) - return -EINVAL; - - table->ptr = level_table; - table->table_base = temp_base - - ((index - 1) << block_shift); - table->entry_size = block_size; - - return 0; - } - } - return -EINVAL; -} - /* * To start MMU before DDR is available, we create MMU table in SRAM. * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three * levels of translation tables here to cover 40-bit address space. * We use 4KB granule size, with 40 bits physical address, T0SZ=24 - * Level 0 IA[39], table address @0 - * Level 1 IA[38:30], table address @0x1000, 0x2000 - * Level 2 IA[29:21], table address @0x3000, 0x4000 - * Address above 0x5000 is free for other purpose. + * Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose. + * Note, the debug print in cache_v8.c is not usable for debugging + * these early MMU tables because UART is not yet available. */ static inline void early_mmu_setup(void) { - unsigned int el, i; - u64 *level0_table = (u64 *)CONFIG_SYS_FSL_OCRAM_BASE; - u64 *level1_table0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x1000); - u64 *level1_table1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x2000); - u64 *level2_table0 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x3000); - u64 *level2_table1 = (u64 *)(CONFIG_SYS_FSL_OCRAM_BASE + 0x4000); - - struct table_info table = {level0_table, 0, BLOCK_SIZE_L0}; + unsigned int el = current_el(); - /* Invalidate all table entries */ - memset(level0_table, 0, 0x5000); + /* global data is already setup, no allocation yet */ + gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE; + gd->arch.tlb_fillptr = gd->arch.tlb_addr; + gd->arch.tlb_size = EARLY_PGTABLE_SIZE; - /* Fill in the table entries */ - set_pgtable_table(level0_table, 0, level1_table0); - set_pgtable_table(level0_table, 1, level1_table1); - set_pgtable_table(level1_table0, 0, level2_table0); + /* Create early page tables */ + setup_pgtables(); -#ifdef CONFIG_FSL_LSCH3 - set_pgtable_table(level1_table0, - CONFIG_SYS_FLASH_BASE >> SECTION_SHIFT_L1, - level2_table1); -#elif defined(CONFIG_FSL_LSCH2) - set_pgtable_table(level1_table0, 1, level2_table1); -#endif - /* Find the table and fill in the block entries */ - for (i = 0; i < ARRAY_SIZE(early_mmu_table); i++) { - if (find_table(&early_mmu_table[i], - &table, level0_table) == 0) { - /* - * If find_table() returns error, it cannot be dealt - * with here. Breakpoint can be added for debugging. - */ - set_block_entry(&early_mmu_table[i], &table); - /* - * If set_block_entry() returns error, it cannot be - * dealt with here too. - */ - } - } - - el = current_el(); - - set_ttbr_tcr_mair(el, (u64)level0_table, LAYERSCAPE_TCR, + /* point TTBR to the new table */ + set_ttbr_tcr_mair(el, gd->arch.tlb_addr, + get_tcr(el, NULL, NULL) & + ~(TCR_ORGN_MASK | TCR_IRGN_MASK), MEMORY_ATTRIBUTES); - set_sctlr(get_sctlr() | CR_M); -} -#ifdef CONFIG_SYS_MEM_RESERVE_SECURE -/* - * Called from final mmu setup. The phys_addr is new, non-existing - * address. A new sub table is created @level2_table_secure to cover - * size of CONFIG_SYS_MEM_RESERVE_SECURE memory. - */ -static inline int final_secure_ddr(u64 *level0_table, - u64 *level2_table_secure, - phys_addr_t phys_addr) -{ - int ret = -EINVAL; - struct table_info table = {}; - struct sys_mmu_table ddr_entry = { - 0, 0, BLOCK_SIZE_L1, MT_NORMAL, - PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS - }; - u64 index; - - /* Need to create a new table */ - ddr_entry.virt_addr = phys_addr & ~(BLOCK_SIZE_L1 - 1); - ddr_entry.phys_addr = phys_addr & ~(BLOCK_SIZE_L1 - 1); - ret = find_table(&ddr_entry, &table, level0_table); - if (ret) - return ret; - index = (ddr_entry.virt_addr - table.table_base) >> SECTION_SHIFT_L1; - set_pgtable_table(table.ptr, index, level2_table_secure); - table.ptr = level2_table_secure; - table.table_base = ddr_entry.virt_addr; - table.entry_size = BLOCK_SIZE_L2; - ret = set_block_entry(&ddr_entry, &table); - if (ret) { - printf("MMU error: could not fill non-secure ddr block entries\n"); - return ret; - } - ddr_entry.virt_addr = phys_addr; - ddr_entry.phys_addr = phys_addr; - ddr_entry.size = CONFIG_SYS_MEM_RESERVE_SECURE; - ddr_entry.attribute = PTE_BLOCK_OUTER_SHARE; - ret = find_table(&ddr_entry, &table, level0_table); - if (ret) { - printf("MMU error: could not find secure ddr table\n"); - return ret; - } - ret = set_block_entry(&ddr_entry, &table); - if (ret) - printf("MMU error: could not set secure ddr block entry\n"); - - return ret; + set_sctlr(get_sctlr() | CR_M); } -#endif /* * The final tables look similar to early tables, but different in detail. * These tables are in DRAM. Sub tables are added to enable cache for * QBMan and OCRAM. * - * Put the MMU table in secure memory if gd->secure_ram is valid. - * OCRAM will be not used for this purpose so gd->secure_ram can't be 0. - * - * Level 1 table 0 contains 512 entries for each 1GB from 0 to 512GB. - * Level 1 table 1 contains 512 entries for each 1GB from 512GB to 1TB. - * Level 2 table 0 contains 512 entries for each 2MB from 0 to 1GB. - * - * For LSCH3: - * Level 2 table 1 contains 512 entries for each 2MB from 32GB to 33GB. - * For LSCH2: - * Level 2 table 1 contains 512 entries for each 2MB from 1GB to 2GB. - * Level 2 table 2 contains 512 entries for each 2MB from 20GB to 21GB. + * Put the MMU table in secure memory if gd->arch.secure_ram is valid. + * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0. */ static inline void final_mmu_setup(void) { + u64 tlb_addr_save = gd->arch.tlb_addr; unsigned int el = current_el(); - unsigned int i; - u64 *level0_table = (u64 *)gd->arch.tlb_addr; - u64 *level1_table0; - u64 *level1_table1; - u64 *level2_table0; - u64 *level2_table1; -#ifdef CONFIG_FSL_LSCH2 - u64 *level2_table2; -#endif - struct table_info table = {NULL, 0, BLOCK_SIZE_L0}; - #ifdef CONFIG_SYS_MEM_RESERVE_SECURE - u64 *level2_table_secure; - - if (el == 3) { - /* - * Only use gd->secure_ram if the address is recalculated - * Align to 4KB for MMU table - */ - if (gd->secure_ram & MEM_RESERVE_SECURE_MAINTAINED) - level0_table = (u64 *)(gd->secure_ram & ~0xfff); - else - printf("MMU warning: gd->secure_ram is not maintained, disabled.\n"); - } -#endif - level1_table0 = level0_table + 512; - level1_table1 = level1_table0 + 512; - level2_table0 = level1_table1 + 512; - level2_table1 = level2_table0 + 512; -#ifdef CONFIG_FSL_LSCH2 - level2_table2 = level2_table1 + 512; -#endif - table.ptr = level0_table; - - /* Invalidate all table entries */ - memset(level0_table, 0, PGTABLE_SIZE); - - /* Fill in the table entries */ - set_pgtable_table(level0_table, 0, level1_table0); - set_pgtable_table(level0_table, 1, level1_table1); - set_pgtable_table(level1_table0, 0, level2_table0); -#ifdef CONFIG_FSL_LSCH3 - set_pgtable_table(level1_table0, - CONFIG_SYS_FSL_QBMAN_BASE >> SECTION_SHIFT_L1, - level2_table1); -#elif defined(CONFIG_FSL_LSCH2) - set_pgtable_table(level1_table0, 1, level2_table1); - set_pgtable_table(level1_table0, - CONFIG_SYS_FSL_QBMAN_BASE >> SECTION_SHIFT_L1, - level2_table2); + int index; #endif - /* Find the table and fill in the block entries */ - for (i = 0; i < ARRAY_SIZE(final_mmu_table); i++) { - if (find_table(&final_mmu_table[i], - &table, level0_table) == 0) { - if (set_block_entry(&final_mmu_table[i], - &table) != 0) { - printf("MMU error: could not set block entry for %p\n", - &final_mmu_table[i]); - } + mem_map = final_map; - } else { - printf("MMU error: could not find the table for %p\n", - &final_mmu_table[i]); - } - } - /* Set the secure memory to secure in MMU */ #ifdef CONFIG_SYS_MEM_RESERVE_SECURE - if (el == 3 && gd->secure_ram & MEM_RESERVE_SECURE_MAINTAINED) { -#ifdef CONFIG_FSL_LSCH3 - level2_table_secure = level2_table1 + 512; -#elif defined(CONFIG_FSL_LSCH2) - level2_table_secure = level2_table2 + 512; -#endif - if (!final_secure_ddr(level0_table, - level2_table_secure, - gd->secure_ram & ~0x3)) { - gd->secure_ram |= MEM_RESERVE_SECURE_SECURED; - debug("Now MMU table is in secured memory at 0x%llx\n", - gd->secure_ram & ~0x3); + if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) { + if (el == 3) { + /* + * Only use gd->arch.secure_ram if the address is + * recalculated. Align to 4KB for MMU table. + */ + /* put page tables in secure ram */ + index = ARRAY_SIZE(final_map) - 2; + gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff; + final_map[index].virt = gd->arch.secure_ram & ~0x3; + final_map[index].phys = final_map[index].virt; + final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE; + final_map[index].attrs = PTE_BLOCK_OUTER_SHARE; + gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED; + tlb_addr_save = gd->arch.tlb_addr; } else { - printf("MMU warning: Failed to secure DDR\n"); + /* Use allocated (board_f.c) memory for TLB */ + tlb_addr_save = gd->arch.tlb_allocated; + gd->arch.tlb_addr = tlb_addr_save; } } #endif + /* Reset the fill ptr */ + gd->arch.tlb_fillptr = tlb_addr_save; + + /* Create normal system page tables */ + setup_pgtables(); + + /* Create emergency page tables */ + gd->arch.tlb_addr = gd->arch.tlb_fillptr; + gd->arch.tlb_emerg = gd->arch.tlb_addr; + setup_pgtables(); + gd->arch.tlb_addr = tlb_addr_save; + /* flush new MMU table */ - flush_dcache_range((ulong)level0_table, - (ulong)level0_table + gd->arch.tlb_size); + flush_dcache_range(gd->arch.tlb_addr, + gd->arch.tlb_addr + gd->arch.tlb_size); /* point TTBR to the new table */ - set_ttbr_tcr_mair(el, (u64)level0_table, LAYERSCAPE_TCR_FINAL, + set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL), MEMORY_ATTRIBUTES); /* - * MMU is already enabled, just need to invalidate TLB to load the + * EL3 MMU is already enabled, just need to invalidate TLB to load the * new table. The new table is compatible with the current table, if * MMU somehow walks through the new table before invalidation TLB, * it still works. So we don't need to turn off MMU here. + * When EL2 MMU table is created by calling this function, MMU needs + * to be enabled. */ + set_sctlr(get_sctlr() | CR_M); } u64 get_page_table_size(void) @@ -422,15 +170,21 @@ int arch_cpu_init(void) return 0; } +void mmu_setup(void) +{ + final_mmu_setup(); +} + /* - * This function is called from lib/board.c. - * It recreates MMU table in main memory. MMU and d-cache are enabled earlier. - * There is no need to disable d-cache for this operation. + * This function is called from common/board_r.c. + * It recreates MMU table in main memory. */ void enable_caches(void) { - final_mmu_setup(); + mmu_setup(); __asm_invalidate_tlb_all(); + icache_enable(); + dcache_enable(); } #endif @@ -558,7 +312,8 @@ int print_cpuinfo(void) printf("CPU%d(%s):%-4s MHz ", core, type == TY_ITYP_VER_A7 ? "A7 " : (type == TY_ITYP_VER_A53 ? "A53" : - (type == TY_ITYP_VER_A57 ? "A57" : " ")), + (type == TY_ITYP_VER_A57 ? "A57" : + (type == TY_ITYP_VER_A72 ? "A72" : " "))), strmhz(buf, sysinfo.freq_processor[core])); } printf("\n Bus: %-4s MHz ", @@ -616,6 +371,7 @@ int arch_early_init_r(void) { #ifdef CONFIG_MP int rv = 1; + u32 psci_ver = 0xffffffff; #endif #ifdef CONFIG_SYS_FSL_ERRATUM_A009635 @@ -623,9 +379,15 @@ int arch_early_init_r(void) #endif #ifdef CONFIG_MP - rv = fsl_layerscape_wake_seconday_cores(); - if (rv) - printf("Did not wake secondary cores\n"); +#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && defined(CONFIG_ARMV8_PSCI) + /* Check the psci version to determine if the psci is supported */ + psci_ver = sec_firmware_support_psci_version(); +#endif + if (psci_ver == 0xffffffff) { + rv = fsl_layerscape_wake_seconday_cores(); + if (rv) + printf("Did not wake secondary cores\n"); + } #endif #ifdef CONFIG_SYS_HAS_SERDES diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 index da5e052569c..7867c379d4b 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 @@ -128,7 +128,7 @@ mcinitcmd: This environment variable is defined to initiate MC and DPL deploymen during U-boot booting.However the MC, DPC and DPL can be applied from console independently. The variable needs to be set from the console once and then on - rebooting the parameters set in the varible will automatically be + rebooting the parameters set in the variable will automatically be executed. The commmand is demostrated taking an example of mc boot using NOR Flash i.e. MC, DPL, and DPC is stored in the NOR flash: diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc index 8eee016f11c..f7b949aca22 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc @@ -3,6 +3,7 @@ SoC overview 1. LS1043A 2. LS2080A 3. LS1012A + 4. LS1046A LS1043A --------- @@ -127,3 +128,44 @@ The LS1012A SoC includes the following function and features: - Two WatchDog timers - ARM generic timer - QorIQ platform's trust architecture 2.1 + +LS1046A +-------- +The LS1046A integrated multicore processor combines four ARM Cortex-A72 +processor cores with datapath acceleration optimized for L2/3 packet +processing, single pass security offload and robust traffic management +and quality of service. + +The LS1046A SoC includes the following function and features: + - Four 64-bit ARM Cortex-A72 CPUs + - 2 MB unified L2 Cache + - One 64-bit DDR4 SDRAM memory controllers with ECC and interleaving + support + - Data Path Acceleration Architecture (DPAA) incorporating acceleration the + the following functions: + - Packet parsing, classification, and distribution (FMan) + - Queue management for scheduling, packet sequencing, and congestion + management (QMan) + - Hardware buffer management for buffer allocation and de-allocation (BMan) + - Cryptography acceleration (SEC) + - Two Configurable x4 SerDes + - Two PLLs per four-lane SerDes + - Support for 10G operation + - Ethernet interfaces by FMan + - Up to 2 x XFI supporting 10G interface (MAC 9, 10) + - Up to 1 x QSGMII (MAC 5, 6, 10, 1) + - Up to 4 x SGMII supporting 1000Mbps (MAC 5, 6, 9, 10) + - Up to 3 x SGMII supporting 2500Mbps (MAC 5, 9, 10) + - Up to 2 x RGMII supporting 1000Mbps (MAC 3, 4) + - High-speed peripheral interfaces + - Three PCIe 3.0 controllers, one supporting x4 operation + - One serial ATA (SATA 3.0) controllers + - Additional peripheral interfaces + - Three high-speed USB 3.0 controllers with integrated PHY + - Enhanced secure digital host controller (eSDXC/eMMC) + - Quad Serial Peripheral Interface (QSPI) Controller + - Serial peripheral interface (SPI) controller + - Four I2C controllers + - Two DUARTs + - Integrated flash controller (IFC) supporting NAND and NOR flash + - QorIQ platform's trust architecture 2.1 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index d17227ab2b2..40d6a761e87 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -22,6 +22,9 @@ #endif #include <fsl_sec.h> #include <asm/arch-fsl-layerscape/soc.h> +#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT +#include <asm/armv8/sec_firmware.h> +#endif int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc) { @@ -38,7 +41,37 @@ void ft_fixup_cpu(void *blob) int addr_cells; u64 val, core_id; size_t *boot_code_size = &(__secondary_boot_code_size); +#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && defined(CONFIG_ARMV8_PSCI) + int node; + u32 psci_ver; + + /* Check the psci version to determine if the psci is supported */ + psci_ver = sec_firmware_support_psci_version(); + if (psci_ver == 0xffffffff) { + /* remove psci DT node */ + node = fdt_path_offset(blob, "/psci"); + if (node >= 0) + goto remove_psci_node; + + node = fdt_node_offset_by_compatible(blob, -1, "arm,psci"); + if (node >= 0) + goto remove_psci_node; + + node = fdt_node_offset_by_compatible(blob, -1, "arm,psci-0.2"); + if (node >= 0) + goto remove_psci_node; + node = fdt_node_offset_by_compatible(blob, -1, "arm,psci-1.0"); + if (node >= 0) + goto remove_psci_node; + +remove_psci_node: + if (node >= 0) + fdt_del_node(blob, node); + } else { + return; + } +#endif off = fdt_path_offset(blob, "/cpus"); if (off < 0) { puts("couldn't find /cpus node\n"); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c index fe3444a91e3..f73092ae3e4 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c @@ -13,6 +13,9 @@ #ifdef CONFIG_SYS_FSL_SRDS_1 static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT]; #endif +#ifdef CONFIG_SYS_FSL_SRDS_2 +static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT]; +#endif int is_serdes_configured(enum srds_prtcl device) { @@ -21,6 +24,9 @@ int is_serdes_configured(enum srds_prtcl device) #ifdef CONFIG_SYS_FSL_SRDS_1 ret |= serdes1_prtcl_map[device]; #endif +#ifdef CONFIG_SYS_FSL_SRDS_2 + ret |= serdes2_prtcl_map[device]; +#endif return !!ret; } @@ -38,6 +44,12 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device) cfg >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; break; #endif +#ifdef CONFIG_SYS_FSL_SRDS_2 + case FSL_SRDS_2: + cfg &= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK; + cfg >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT; + break; +#endif default: printf("invalid SerDes%d\n", sd); break; @@ -114,4 +126,11 @@ void fsl_serdes_init(void) FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT, serdes1_prtcl_map); #endif +#ifdef CONFIG_SYS_FSL_SRDS_2 + serdes_init(FSL_SRDS_2, + CONFIG_SYS_FSL_SERDES_ADDR, + FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK, + FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT, + serdes2_prtcl_map); +#endif } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index d0dc58d1814..8922197d439 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -107,6 +107,12 @@ void get_sys_info(struct sys_info *sys_info) case 3: sys_info->freq_fman[0] = freq_c_pll[0] / 3; break; + case 4: + sys_info->freq_fman[0] = freq_c_pll[0] / 4; + break; + case 5: + sys_info->freq_fman[0] = sys_info->freq_systembus; + break; case 6: sys_info->freq_fman[0] = freq_c_pll[1] / 2; break; @@ -124,8 +130,23 @@ void get_sys_info(struct sys_info *sys_info) #ifdef CONFIG_FSL_ESDHC #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK rcw_tmp = in_be32(&gur->rcwsr[15]); - rcw_tmp = (rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT; - sys_info->freq_sdhc = freq_c_pll[1] / rcw_tmp; + switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) { + case 1: + sys_info->freq_sdhc = freq_c_pll[1]; + break; + case 2: + sys_info->freq_sdhc = freq_c_pll[1] / 2; + break; + case 3: + sys_info->freq_sdhc = freq_c_pll[1] / 3; + break; + case 6: + sys_info->freq_sdhc = freq_c_pll[0] / 2; + break; + default: + printf("Error: Unknown ESDHC clock select!\n"); + break; + } #else sys_info->freq_sdhc = sys_info->freq_systembus; #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c new file mode 100644 index 00000000000..1da6b7135f8 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c @@ -0,0 +1,99 @@ +/* + * Copyright 2016 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/fsl_serdes.h> +#include <asm/arch/immap_lsch2.h> + +struct serdes_config { + u32 protocol; + u8 lanes[SRDS_MAX_LANES]; +}; + +static struct serdes_config serdes1_cfg_tbl[] = { + /* SerDes 1 */ + {0x3333, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5, + SGMII_FM1_DTSEC6} }, + {0x1133, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC5, + SGMII_FM1_DTSEC6} }, + {0x1333, {XFI_FM1_MAC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5, + SGMII_FM1_DTSEC6} }, + {0x2333, {SGMII_2500_FM1_DTSEC9, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC5, + SGMII_FM1_DTSEC6} }, + {0x2233, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, + SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {0x1040, {XFI_FM1_MAC9, NONE, QSGMII_FM1_A, NONE} }, + {0x2040, {SGMII_2500_FM1_DTSEC9, NONE, QSGMII_FM1_A, NONE} }, + {0x1163, {XFI_FM1_MAC9, XFI_FM1_MAC10, PCIE1, SGMII_FM1_DTSEC6} }, + {0x2263, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, PCIE1, + SGMII_FM1_DTSEC6} }, + {0x3363, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, PCIE1, + SGMII_FM1_DTSEC6} }, + {0x2223, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10, + SGMII_2500_FM1_DTSEC5, SGMII_FM1_DTSEC6} }, + {} +}; + +static struct serdes_config serdes2_cfg_tbl[] = { + /* SerDes 2 */ + {0x8888, {PCIE1, PCIE1, PCIE1, PCIE1} }, + {0x5559, {PCIE1, PCIE2, PCIE3, SATA1} }, + {0x5577, {PCIE1, PCIE2, PCIE3, PCIE3} }, + {0x5506, {PCIE1, PCIE2, NONE, PCIE3} }, + {0x0506, {NONE, PCIE2, NONE, PCIE3} }, + {0x0559, {NONE, PCIE2, PCIE3, SATA1} }, + {0x5A59, {PCIE1, SGMII_FM1_DTSEC2, PCIE3, SATA1} }, + {0x5A06, {PCIE1, SGMII_FM1_DTSEC2, NONE, PCIE3} }, + {} +}; + +static struct serdes_config *serdes_cfg_tbl[] = { + serdes1_cfg_tbl, + serdes2_cfg_tbl, +}; + +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) +{ + struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == cfg) + return ptr->lanes[lane]; + ptr++; + } + + return 0; +} + +int is_serdes_prtcl_valid(int serdes, u32 prtcl) +{ + int i; + struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == prtcl) + break; + ptr++; + } + + if (!ptr->protocol) + return 0; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (ptr->lanes[i] != NONE) + return 1; + } + + return 0; +} diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c new file mode 100644 index 00000000000..f54ac3f431e --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c @@ -0,0 +1,48 @@ +/* + * Copyright 2016 NXP Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <config.h> +#include <errno.h> +#include <asm/system.h> +#include <asm/types.h> +#include <asm/arch/soc.h> +#ifdef CONFIG_FSL_LSCH3 +#include <asm/arch/immap_lsch3.h> +#elif defined(CONFIG_FSL_LSCH2) +#include <asm/arch/immap_lsch2.h> +#endif +#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT +#include <asm/armv8/sec_firmware.h> +#endif + +int ppa_init(void) +{ + const void *ppa_fit_addr; + u32 *boot_loc_ptr_l, *boot_loc_ptr_h; + int ret; + +#ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP + ppa_fit_addr = (void *)CONFIG_SYS_LS_PPA_FW_ADDR; +#else +#error "No CONFIG_SYS_LS_PPA_FW_IN_xxx defined" +#endif + +#ifdef CONFIG_FSL_LSCH3 + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + boot_loc_ptr_l = &gur->bootlocptrl; + boot_loc_ptr_h = &gur->bootlocptrh; +#elif defined(CONFIG_FSL_LSCH2) + struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR); + boot_loc_ptr_l = &scfg->scratchrw[1]; + boot_loc_ptr_h = &scfg->scratchrw[0]; +#endif + + debug("fsl-ppa: boot_loc_ptr_l = 0x%p, boot_loc_ptr_h =0x%p\n", + boot_loc_ptr_l, boot_loc_ptr_h); + ret = sec_firmware_init(ppa_fit_addr, boot_loc_ptr_l, boot_loc_ptr_h); + + return ret; +} diff --git a/arch/arm/cpu/armv8/s32v234/cpu.c b/arch/arm/cpu/armv8/s32v234/cpu.c index dac12a2552f..5c97e0eee43 100644 --- a/arch/arm/cpu/armv8/s32v234/cpu.c +++ b/arch/arm/cpu/armv8/s32v234/cpu.c @@ -32,24 +32,28 @@ u32 cpu_mask(void) static struct mm_region s32v234_mem_map[] = { { - .base = S32V234_IRAM_BASE, + .virt = S32V234_IRAM_BASE, + .phys = S32V234_IRAM_BASE, .size = S32V234_IRAM_SIZE, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE }, { - .base = S32V234_DRAM_BASE1, + .virt = S32V234_DRAM_BASE1, + .phys = S32V234_DRAM_BASE1, .size = S32V234_DRAM_SIZE1, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE }, { - .base = S32V234_PERIPH_BASE, + .virt = S32V234_PERIPH_BASE, + .phys = S32V234_PERIPH_BASE, .size = S32V234_PERIPH_SIZE, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE /* TODO: Do we need these? */ /* | PTE_BLOCK_PXN | PTE_BLOCK_UXN */ }, { - .base = S32V234_DRAM_BASE2, + .virt = S32V234_DRAM_BASE2, + .phys = S32V234_DRAM_BASE2, .size = S32V234_DRAM_SIZE2, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | PTE_BLOCK_OUTER_SHARE diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c new file mode 100644 index 00000000000..e21e199381d --- /dev/null +++ b/arch/arm/cpu/armv8/sec_firmware.c @@ -0,0 +1,270 @@ +/* + * Copyright 2016 NXP Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <errno.h> +#include <linux/kernel.h> +#include <asm/io.h> +#include <asm/system.h> +#include <asm/types.h> +#include <asm/macro.h> +#include <asm/armv8/sec_firmware.h> + +DECLARE_GLOBAL_DATA_PTR; +extern void c_runtime_cpu_setup(void); + +#define SEC_FIRMWARE_LOADED 0x1 +#define SEC_FIRMWARE_RUNNING 0x2 +#define SEC_FIRMWARE_ADDR_MASK (~0x3) + /* + * Secure firmware load addr + * Flags used: 0x1 secure firmware has been loaded to secure memory + * 0x2 secure firmware is running + */ + phys_addr_t sec_firmware_addr; + +static int sec_firmware_get_data(const void *sec_firmware_img, + const void **data, size_t *size) +{ + int conf_node_off, fw_node_off; + char *conf_node_name = NULL; + char *desc; + int ret; + + conf_node_name = SEC_FIRMEWARE_FIT_CNF_NAME; + + conf_node_off = fit_conf_get_node(sec_firmware_img, conf_node_name); + if (conf_node_off < 0) { + printf("SEC Firmware: %s: no such config\n", conf_node_name); + return -ENOENT; + } + + fw_node_off = fit_conf_get_prop_node(sec_firmware_img, conf_node_off, + SEC_FIRMWARE_FIT_IMAGE); + if (fw_node_off < 0) { + printf("SEC Firmware: No '%s' in config\n", + SEC_FIRMWARE_FIT_IMAGE); + return -ENOLINK; + } + + /* Verify secure firmware image */ + if (!(fit_image_verify(sec_firmware_img, fw_node_off))) { + printf("SEC Firmware: Bad firmware image (bad CRC)\n"); + return -EINVAL; + } + + if (fit_image_get_data(sec_firmware_img, fw_node_off, data, size)) { + printf("SEC Firmware: Can't get %s subimage data/size", + SEC_FIRMWARE_FIT_IMAGE); + return -ENOENT; + } + + ret = fit_get_desc(sec_firmware_img, fw_node_off, &desc); + if (ret) + printf("SEC Firmware: Can't get description\n"); + else + printf("%s\n", desc); + + return ret; +} + +/* + * SEC Firmware FIT image parser checks if the image is in FIT + * format, verifies integrity of the image and calculates raw + * image address and size values. + * + * Returns 0 on success and a negative errno on error task fail. + */ +static int sec_firmware_parse_image(const void *sec_firmware_img, + const void **raw_image_addr, + size_t *raw_image_size) +{ + int ret; + + ret = sec_firmware_get_data(sec_firmware_img, raw_image_addr, + raw_image_size); + if (ret) + return ret; + + debug("SEC Firmware: raw_image_addr = 0x%p, raw_image_size = 0x%lx\n", + *raw_image_addr, *raw_image_size); + + return 0; +} + +static int sec_firmware_copy_image(const char *title, + u64 image_addr, u32 image_size, u64 sec_firmware) +{ + debug("%s copied to address 0x%p\n", title, (void *)sec_firmware); + memcpy((void *)sec_firmware, (void *)image_addr, image_size); + flush_dcache_range(sec_firmware, sec_firmware + image_size); + + return 0; +} + +/* + * This function will parse the SEC Firmware image, and then load it + * to secure memory. + */ +static int sec_firmware_load_image(const void *sec_firmware_img) +{ + const void *raw_image_addr; + size_t raw_image_size = 0; + int ret; + + /* + * The Excetpion Level must be EL3 to load and initialize + * the SEC Firmware. + */ + if (current_el() != 3) { + ret = -EACCES; + goto out; + } + +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + /* + * The SEC Firmware must be stored in secure memory. + * Append SEC Firmware to secure mmu table. + */ + if (!(gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED)) { + ret = -ENXIO; + goto out; + } + + sec_firmware_addr = (gd->arch.secure_ram & MEM_RESERVE_SECURE_ADDR_MASK) + + gd->arch.tlb_size; +#else +#error "The CONFIG_SYS_MEM_RESERVE_SECURE must be defined when enabled SEC Firmware support" +#endif + + /* Align SEC Firmware base address to 4K */ + sec_firmware_addr = (sec_firmware_addr + 0xfff) & ~0xfff; + debug("SEC Firmware: Load address: 0x%llx\n", + sec_firmware_addr & SEC_FIRMWARE_ADDR_MASK); + + ret = sec_firmware_parse_image(sec_firmware_img, &raw_image_addr, + &raw_image_size); + if (ret) + goto out; + + /* TODO: + * Check if the end addr of SEC Firmware has been extend the secure + * memory. + */ + + /* Copy the secure firmware to secure memory */ + ret = sec_firmware_copy_image("SEC Firmware", (u64)raw_image_addr, + raw_image_size, sec_firmware_addr & + SEC_FIRMWARE_ADDR_MASK); + if (ret) + goto out; + + sec_firmware_addr |= SEC_FIRMWARE_LOADED; + debug("SEC Firmware: Entry point: 0x%llx\n", + sec_firmware_addr & SEC_FIRMWARE_ADDR_MASK); + + return 0; + +out: + printf("SEC Firmware: error (%d)\n", ret); + sec_firmware_addr = 0; + + return ret; +} + +static int sec_firmware_entry(u32 *eret_hold_l, u32 *eret_hold_h) +{ + const void *entry = (void *)(sec_firmware_addr & + SEC_FIRMWARE_ADDR_MASK); + + return _sec_firmware_entry(entry, eret_hold_l, eret_hold_h); +} + +/* Check the secure firmware FIT image */ +__weak bool sec_firmware_is_valid(const void *sec_firmware_img) +{ + if (fdt_check_header(sec_firmware_img)) { + printf("SEC Firmware: Bad firmware image (not a FIT image)\n"); + return false; + } + + if (!fit_check_format(sec_firmware_img)) { + printf("SEC Firmware: Bad firmware image (bad FIT header)\n"); + return false; + } + + return true; +} + +#ifdef CONFIG_ARMV8_PSCI +/* + * The PSCI_VERSION function is added from PSCI v0.2. When the PSCI + * v0.1 received this function, the NOT_SUPPORTED (0xffff_ffff) error + * number will be returned according to SMC Calling Conventions. But + * when getting the NOT_SUPPORTED error number, we cannot ensure if + * the PSCI version is v0.1 or other error occurred. So, PSCI v0.1 + * won't be supported by this framework. + * And if the secure firmware isn't running, return NOT_SUPPORTED. + * + * The return value on success is PSCI version in format + * major[31:16]:minor[15:0]. + */ +unsigned int sec_firmware_support_psci_version(void) +{ + if (sec_firmware_addr & SEC_FIRMWARE_RUNNING) + return _sec_firmware_support_psci_version(); + + return 0xffffffff; +} +#endif + +/* + * sec_firmware_init - Initialize the SEC Firmware + * @sec_firmware_img: the SEC Firmware image address + * @eret_hold_l: the address to hold exception return address low + * @eret_hold_h: the address to hold exception return address high + */ +int sec_firmware_init(const void *sec_firmware_img, + u32 *eret_hold_l, + u32 *eret_hold_h) +{ + int ret; + + if (!sec_firmware_is_valid(sec_firmware_img)) + return -EINVAL; + + ret = sec_firmware_load_image(sec_firmware_img); + if (ret) { + printf("SEC Firmware: Failed to load image\n"); + return ret; + } else if (sec_firmware_addr & SEC_FIRMWARE_LOADED) { + ret = sec_firmware_entry(eret_hold_l, eret_hold_h); + if (ret) { + printf("SEC Firmware: Failed to initialize\n"); + return ret; + } + } + + debug("SEC Firmware: Return from SEC Firmware: current_el = %d\n", + current_el()); + + /* + * The PE will be turned into target EL when returned from + * SEC Firmware. + */ + if (current_el() != SEC_FIRMWARE_TARGET_EL) + return -EACCES; + + sec_firmware_addr |= SEC_FIRMWARE_RUNNING; + + /* Set exception table and enable caches if it isn't EL3 */ + if (current_el() != 3) { + c_runtime_cpu_setup(); + enable_caches(); + } + + return 0; +} diff --git a/arch/arm/cpu/armv8/sec_firmware_asm.S b/arch/arm/cpu/armv8/sec_firmware_asm.S new file mode 100644 index 00000000000..0c6a46249a2 --- /dev/null +++ b/arch/arm/cpu/armv8/sec_firmware_asm.S @@ -0,0 +1,53 @@ +/* + * Copyright 2016 NXP Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <linux/linkage.h> +#include <asm/system.h> +#include <asm/macro.h> + +WEAK(_sec_firmware_entry) + /* + * x0: Secure Firmware entry point + * x1: Exception return address Low + * x2: Exception return address High + */ + + /* Save stack pointer for EL2 */ + mov x3, sp + msr sp_el2, x3 + + /* Set exception return address hold pointer */ + adr x4, 1f + mov x3, x4 +#ifdef SEC_FIRMWARE_ERET_ADDR_REVERT + rev w3, w3 +#endif + str w3, [x1] + lsr x3, x4, #32 +#ifdef SEC_FIRMWARE_ERET_ADDR_REVERT + rev w3, w3 +#endif + str w3, [x2] + + /* Call SEC monitor */ + br x0 + +1: + mov x0, #0 + ret +ENDPROC(_sec_firmware_entry) + +#ifdef CONFIG_ARMV8_PSCI +ENTRY(_sec_firmware_support_psci_version) + mov x0, 0x84000000 + mov x1, 0x0 + mov x2, 0x0 + mov x3, 0x0 + smc #0 + ret +ENDPROC(_sec_firmware_support_psci_version) +#endif diff --git a/arch/arm/cpu/armv8/spin_table.c b/arch/arm/cpu/armv8/spin_table.c new file mode 100644 index 00000000000..ec1c9b8ddb6 --- /dev/null +++ b/arch/arm/cpu/armv8/spin_table.c @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <libfdt.h> +#include <asm/spin_table.h> + +int spin_table_update_dt(void *fdt) +{ + int cpus_offset, offset; + const char *prop; + int ret; + unsigned long rsv_addr = (unsigned long)&spin_table_reserve_begin; + unsigned long rsv_size = &spin_table_reserve_end - + &spin_table_reserve_begin; + + cpus_offset = fdt_path_offset(fdt, "/cpus"); + if (cpus_offset < 0) + return -ENODEV; + + for (offset = fdt_first_subnode(fdt, cpus_offset); + offset >= 0; + offset = fdt_next_subnode(fdt, offset)) { + prop = fdt_getprop(fdt, offset, "device_type", NULL); + if (!prop || strcmp(prop, "cpu")) + continue; + + /* + * In the first loop, we check if every CPU node specifies + * spin-table. Otherwise, just return successfully to not + * disturb other methods, like psci. + */ + prop = fdt_getprop(fdt, offset, "enable-method", NULL); + if (!prop || strcmp(prop, "spin-table")) + return 0; + } + + for (offset = fdt_first_subnode(fdt, cpus_offset); + offset >= 0; + offset = fdt_next_subnode(fdt, offset)) { + prop = fdt_getprop(fdt, offset, "device_type", NULL); + if (!prop || strcmp(prop, "cpu")) + continue; + + ret = fdt_setprop_u64(fdt, offset, "cpu-release-addr", + (unsigned long)&spin_table_cpu_release_addr); + if (ret) + return -ENOSPC; + } + + ret = fdt_add_mem_rsv(fdt, rsv_addr, rsv_size); + if (ret) + return -ENOSPC; + + printf(" Reserved memory region for spin-table: addr=%lx size=%lx\n", + rsv_addr, rsv_size); + + return 0; +} diff --git a/arch/arm/cpu/armv8/spin_table_v8.S b/arch/arm/cpu/armv8/spin_table_v8.S new file mode 100644 index 00000000000..d7f78a6a673 --- /dev/null +++ b/arch/arm/cpu/armv8/spin_table_v8.S @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/linkage.h> + +ENTRY(spin_table_secondary_jump) +.globl spin_table_reserve_begin +spin_table_reserve_begin: +0: wfe + ldr x0, spin_table_cpu_release_addr + cbz x0, 0b + br x0 +.globl spin_table_cpu_release_addr + .align 3 +spin_table_cpu_release_addr: + .quad 0 +.globl spin_table_reserve_end +spin_table_reserve_end: +ENDPROC(spin_table_secondary_jump) diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index 670e323b61b..19c771dba3a 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -53,6 +53,11 @@ _bss_end_ofs: .quad __bss_end - _start reset: + /* Allow the board to save important registers */ + b save_boot_params +.globl save_boot_params_ret +save_boot_params_ret: + #ifdef CONFIG_SYS_RESET_SCTRL bl reset_sctrl #endif @@ -94,7 +99,11 @@ reset: /* Processor specific initialization */ bl lowlevel_init -#ifdef CONFIG_ARMV8_MULTIENTRY +#if CONFIG_IS_ENABLED(ARMV8_SPIN_TABLE) + branch_if_master x0, x1, master_cpu + b spin_table_secondary_jump + /* never return */ +#elif defined(CONFIG_ARMV8_MULTIENTRY) branch_if_master x0, x1, master_cpu /* @@ -106,10 +115,8 @@ slave_cpu: ldr x0, [x1] cbz x0, slave_cpu br x0 /* branch to the given address */ -master_cpu: - /* On the master CPU */ #endif /* CONFIG_ARMV8_MULTIENTRY */ - +master_cpu: bl _main #ifdef CONFIG_SYS_RESET_SCTRL @@ -280,3 +287,7 @@ ENTRY(c_runtime_cpu_setup) ret ENDPROC(c_runtime_cpu_setup) + +WEAK(save_boot_params) + b save_boot_params_ret /* back to my caller */ +ENDPROC(save_boot_params) diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig b/arch/arm/cpu/armv8/zynqmp/Kconfig index 6c71d7840eb..ed3305d7182 100644 --- a/arch/arm/cpu/armv8/zynqmp/Kconfig +++ b/arch/arm/cpu/armv8/zynqmp/Kconfig @@ -20,4 +20,8 @@ config SYS_CONFIG_NAME config ZYNQMP_USB bool "Configure ZynqMP USB" +config SYS_MALLOC_F_LEN + default 0x600 + + endif diff --git a/arch/arm/cpu/armv8/zynqmp/clk.c b/arch/arm/cpu/armv8/zynqmp/clk.c index 690c72dd668..f7e5ebfa634 100644 --- a/arch/arm/cpu/armv8/zynqmp/clk.c +++ b/arch/arm/cpu/armv8/zynqmp/clk.c @@ -12,22 +12,6 @@ DECLARE_GLOBAL_DATA_PTR; -unsigned long get_uart_clk(int dev_id) -{ - u32 ver = zynqmp_get_silicon_version(); - - switch (ver) { - case ZYNQMP_CSU_VERSION_VELOCE: - return 48000; - case ZYNQMP_CSU_VERSION_EP108: - return 25000000; - case ZYNQMP_CSU_VERSION_QEMU: - return 133000000; - } - - return 100000000; -} - unsigned long zynqmp_get_system_timer_freq(void) { u32 ver = zynqmp_get_silicon_version(); diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c index 509f0aa387a..b0f12955a1f 100644 --- a/arch/arm/cpu/armv8/zynqmp/cpu.c +++ b/arch/arm/cpu/armv8/zynqmp/cpu.c @@ -18,40 +18,47 @@ DECLARE_GLOBAL_DATA_PTR; static struct mm_region zynqmp_mem_map[] = { { - .base = 0x0UL, + .virt = 0x0UL, + .phys = 0x0UL, .size = 0x80000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { - .base = 0x80000000UL, + .virt = 0x80000000UL, + .phys = 0x80000000UL, .size = 0x70000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { - .base = 0xf8000000UL, + .virt = 0xf8000000UL, + .phys = 0xf8000000UL, .size = 0x07e00000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { - .base = 0xffe00000UL, + .virt = 0xffe00000UL, + .phys = 0xffe00000UL, .size = 0x00200000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { - .base = 0x400000000UL, + .virt = 0x400000000UL, + .phys = 0x400000000UL, .size = 0x200000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { - .base = 0x600000000UL, + .virt = 0x600000000UL, + .phys = 0x600000000UL, .size = 0x800000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { - .base = 0xe00000000UL, + .virt = 0xe00000000UL, + .phys = 0xe00000000UL, .size = 0xf200000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | diff --git a/arch/arm/cpu/armv8/zynqmp/mp.c b/arch/arm/cpu/armv8/zynqmp/mp.c index 58312a79bc5..e10fc3136c8 100644 --- a/arch/arm/cpu/armv8/zynqmp/mp.c +++ b/arch/arm/cpu/armv8/zynqmp/mp.c @@ -128,7 +128,7 @@ static void enable_clock_r5(void) writel(tmp, &crlapb_base->cpu_r5_ctrl); /* Give some delay for clock - * to propogate */ + * to propagate */ udelay(0x500); } diff --git a/arch/arm/cpu/u-boot.lds b/arch/arm/cpu/u-boot.lds index 1769b6ea881..36c9fd0bd01 100644 --- a/arch/arm/cpu/u-boot.lds +++ b/arch/arm/cpu/u-boot.lds @@ -8,6 +8,7 @@ */ #include <config.h> +#include <asm/psci.h> OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") OUTPUT_ARCH(arm) @@ -48,34 +49,67 @@ SECTIONS #ifdef CONFIG_ARMV7_NONSEC + /* Align the secure section only if we're going to use it in situ */ + .__secure_start : +#ifndef CONFIG_ARMV7_SECURE_BASE + ALIGN(CONSTANT(COMMONPAGESIZE)) +#endif + { + KEEP(*(.__secure_start)) + } + #ifndef CONFIG_ARMV7_SECURE_BASE #define CONFIG_ARMV7_SECURE_BASE #define __ARMV7_PSCI_STACK_IN_RAM #endif - .__secure_start : { - . = ALIGN(0x1000); - *(.__secure_start) - } - .secure_text CONFIG_ARMV7_SECURE_BASE : AT(ADDR(.__secure_start) + SIZEOF(.__secure_start)) { *(._secure.text) } - . = LOADADDR(.__secure_start) + - SIZEOF(.__secure_start) + - SIZEOF(.secure_text); + .secure_data : AT(LOADADDR(.secure_text) + SIZEOF(.secure_text)) + { + *(._secure.data) + } + .secure_stack ALIGN(ADDR(.secure_data) + SIZEOF(.secure_data), + CONSTANT(COMMONPAGESIZE)) (NOLOAD) : #ifdef __ARMV7_PSCI_STACK_IN_RAM - /* Align to page boundary and skip 2 pages */ - . = (. & ~ 0xfff) + 0x2000; -#undef __ARMV7_PSCI_STACK_IN_RAM + AT(ADDR(.secure_stack)) +#else + AT(LOADADDR(.secure_data) + SIZEOF(.secure_data)) +#endif + { + KEEP(*(.__secure_stack_start)) + + /* Skip addreses for stack */ + . = . + CONFIG_ARMV7_PSCI_NR_CPUS * ARM_PSCI_STACK_SIZE; + + /* Align end of stack section to page boundary */ + . = ALIGN(CONSTANT(COMMONPAGESIZE)); + + KEEP(*(.__secure_stack_end)) + +#ifdef CONFIG_ARMV7_SECURE_MAX_SIZE + /* + * We are not checking (__secure_end - __secure_start) here, + * as these are the load addresses, and do not include the + * stack section. Instead, use the end of the stack section + * and the start of the text section. + */ + ASSERT((. - ADDR(.secure_text)) <= CONFIG_ARMV7_SECURE_MAX_SIZE, + "Error: secure section exceeds secure memory size"); +#endif + } + +#ifndef __ARMV7_PSCI_STACK_IN_RAM + /* Reset VMA but don't allocate space if we have secure SRAM */ + . = LOADADDR(.secure_stack); #endif - __secure_end_lma = .; - .__secure_end : AT(__secure_end_lma) { + .__secure_end : AT(ADDR(.__secure_end)) { *(.__secure_end) LONG(0x1d1071c); /* Must output something to reset LMA */ } diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ef573ec6851..223124e791b 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -31,7 +31,12 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-firefly.dtb \ rk3288-jerry.dtb \ rk3288-rock2-square.dtb \ - rk3036-sdk.dtb + rk3288-evb.dtb \ + rk3288-fennec.dtb \ + rk3288-miniarm.dtb \ + rk3288-popmetal.dtb \ + rk3036-sdk.dtb \ + rk3399-evb.dtb dtb-$(CONFIG_ARCH_MESON) += \ meson-gxbb-odroidc2.dtb dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ @@ -53,7 +58,8 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ tegra124-jetson-tk1.dtb \ tegra124-nyan-big.dtb \ tegra124-venice2.dtb \ - tegra186-p2771-0000.dtb \ + tegra186-p2771-0000-a02.dtb \ + tegra186-p2771-0000-b00.dtb \ tegra210-e2220-1170.dtb \ tegra210-p2371-0000.dtb \ tegra210-p2371-2180.dtb \ @@ -242,8 +248,10 @@ dtb-$(CONFIG_MACH_SUN8I_A83T) += \ sun8i-a83t-sinovoip-bpi-m3.dtb dtb-$(CONFIG_MACH_SUN8I_H3) += \ sun8i-h3-orangepi-2.dtb \ + sun8i-h3-orangepi-lite.dtb \ sun8i-h3-orangepi-one.dtb \ sun8i-h3-orangepi-pc.dtb \ + sun8i-h3-orangepi-pc-plus.dtb \ sun8i-h3-orangepi-plus.dtb dtb-$(CONFIG_MACH_SUN50I) += \ sun50i-a64-pine64-plus.dtb \ @@ -262,6 +270,9 @@ dtb-$(CONFIG_SOC_KEYSTONE) += k2hk-evm.dtb \ k2e-evm.dtb \ k2g-evm.dtb +dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \ + at91-sama5d2_xplained.dtb + targets += $(dtb-y) # Add any required device tree compiler flags here diff --git a/arch/arm/dts/am57xx-idk-common.dtsi b/arch/arm/dts/am57xx-idk-common.dtsi index 2805b68f3e0..a5bcd25d7b7 100644 --- a/arch/arm/dts/am57xx-idk-common.dtsi +++ b/arch/arm/dts/am57xx-idk-common.dtsi @@ -300,3 +300,52 @@ ti,non-removable; max-frequency = <96000000>; }; + +&qspi { + status = "okay"; + + spi-max-frequency = <76800000>; + m25p80@0 { + compatible = "s25fl256s1","spi-flash"; + spi-max-frequency = <76800000>; + reg = <0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + + /* MTD partition table. + * The ROM checks the first four physical blocks + * for a valid file to boot and the flash here is + * 64KiB block size. + */ + partition@0 { + label = "QSPI.SPL"; + reg = <0x00000000 0x000040000>; + }; + partition@1 { + label = "QSPI.u-boot"; + reg = <0x00040000 0x00100000>; + }; + partition@2 { + label = "QSPI.u-boot-spl-os"; + reg = <0x00140000 0x00080000>; + }; + partition@3 { + label = "QSPI.u-boot-env"; + reg = <0x001c0000 0x00010000>; + }; + partition@4 { + label = "QSPI.u-boot-env.backup1"; + reg = <0x001d0000 0x0010000>; + }; + partition@5 { + label = "QSPI.kernel"; + reg = <0x001e0000 0x0800000>; + }; + partition@6 { + label = "QSPI.file-system"; + reg = <0x009e0000 0x01620000>; + }; + }; +}; diff --git a/arch/arm/dts/at91-sama5d2_xplained.dts b/arch/arm/dts/at91-sama5d2_xplained.dts new file mode 100644 index 00000000000..37094376b9b --- /dev/null +++ b/arch/arm/dts/at91-sama5d2_xplained.dts @@ -0,0 +1,200 @@ +/dts-v1/; +#include "sama5d2.dtsi" +#include "sama5d2-pinfunc.h" + +/ { + model = "Atmel SAMA5D2 Xplained"; + compatible = "atmel,sama5d2-xplained", "atmel,sama5d2", "atmel,sama5"; + + chosen { + stdout-path = &uart1; + }; + + ahb { + usb1: ohci@00400000 { + num-ports = <3>; + atmel,vbus-gpio = <&pioA 42 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_default>; + status = "okay"; + }; + + usb2: ehci@00500000 { + status = "okay"; + }; + + sdmmc0: sdio-host@a0000000 { + bus-width = <8>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc0_cmd_dat_default &pinctrl_sdmmc0_ck_cd_default>; + status = "okay"; + }; + + sdmmc1: sdio-host@b0000000 { + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc1_cmd_dat_default &pinctrl_sdmmc1_ck_cd_default>; + status = "okay"; /* conflict with qspi0 */ + }; + + apb { + qspi0: spi@f0020000 { + status = "okay"; + + flash@0 { + compatible = "atmel,sama5d2-qspi-flash"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_qspi0_default>; + spi-max-frequency = <83000000>; + + partition@00000000 { + label = "boot"; + reg = <0x00000000 0x00c00000>; + }; + + partition@00c00000 { + label = "rootfs"; + reg = <0x00c00000 0x00000000>; + }; + }; + }; + + spi0: spi@f8000000 { + cs-gpios = <&pioA 17 0>, <0>, <0>, <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0_default>; + status = "okay"; + + spi_flash@0 { + compatible = "spi-flash"; + reg = <0>; + spi-max-frequency = <50000000>; + }; + }; + + macb0: ethernet@f8008000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>; + phy-mode = "rmii"; + status = "okay"; + + ethernet-phy@1 { + reg = <0x1>; + }; + }; + + uart1: serial@f8020000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_default>; + status = "okay"; + }; + + i2c1: i2c@fc028000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_default>; + status = "okay"; + }; + + pioA: gpio@fc038000 { + pinctrl { + pinctrl_i2c1_default: i2c1_default { + pinmux = <PIN_PD4__TWD1>, + <PIN_PD5__TWCK1>; + bias-disable; + }; + + pinctrl_macb0_phy_irq: macb0_phy_irq { + pinmux = <PIN_PC9__GPIO>; + bias-disable; + }; + + pinctrl_macb0_rmii: macb0_rmii { + pinmux = <PIN_PB14__GTXCK>, + <PIN_PB15__GTXEN>, + <PIN_PB16__GRXDV>, + <PIN_PB17__GRXER>, + <PIN_PB18__GRX0>, + <PIN_PB19__GRX1>, + <PIN_PB20__GTX0>, + <PIN_PB21__GTX1>, + <PIN_PB22__GMDC>, + <PIN_PB23__GMDIO>; + bias-disable; + }; + + pinctrl_qspi0_default: qspi0_default { + pinmux = <PIN_PA22__QSPI0_SCK>, + <PIN_PA23__QSPI0_CS>, + <PIN_PA24__QSPI0_IO0>, + <PIN_PA25__QSPI0_IO1>, + <PIN_PA26__QSPI0_IO2>, + <PIN_PA27__QSPI0_IO3>; + bias-disable; + }; + + pinctrl_sdmmc0_cmd_dat_default: sdmmc0_cmd_dat_default { + pinmux = <PIN_PA1__SDMMC0_CMD>, + <PIN_PA2__SDMMC0_DAT0>, + <PIN_PA3__SDMMC0_DAT1>, + <PIN_PA4__SDMMC0_DAT2>, + <PIN_PA5__SDMMC0_DAT3>, + <PIN_PA6__SDMMC0_DAT4>, + <PIN_PA7__SDMMC0_DAT5>, + <PIN_PA8__SDMMC0_DAT6>, + <PIN_PA9__SDMMC0_DAT7>; + bias-pull-up; + }; + + pinctrl_sdmmc0_ck_cd_default: sdmmc0_ck_cd_default { + pinmux = <PIN_PA0__SDMMC0_CK>, + <PIN_PA10__SDMMC0_RSTN>, + <PIN_PA11__SDMMC0_VDDSEL>, + <PIN_PA13__SDMMC0_CD>; + bias-disable; + }; + + pinctrl_sdmmc1_cmd_dat_default: sdmmc1_cmd_dat_default { + pinmux = <PIN_PA28__SDMMC1_CMD>, + <PIN_PA18__SDMMC1_DAT0>, + <PIN_PA19__SDMMC1_DAT1>, + <PIN_PA20__SDMMC1_DAT2>, + <PIN_PA21__SDMMC1_DAT3>; + bias-pull-up; + }; + + pinctrl_sdmmc1_ck_cd_default: sdmmc1_ck_cd_default { + pinmux = <PIN_PA22__SDMMC1_CK>, + <PIN_PA30__SDMMC1_CD>; + bias-disable; + }; + + pinctrl_spi0_default: spi0_default { + pinmux = <PIN_PA14__SPI0_SPCK>, + <PIN_PA15__SPI0_MOSI>, + <PIN_PA16__SPI0_MISO>; + bias-disable; + }; + + pinctrl_uart1_default: uart1_default { + pinmux = <PIN_PD2__URXD1>, + <PIN_PD3__UTXD1>; + bias-disable; + }; + + pinctrl_usb_default: usb_default { + pinmux = <PIN_PB10__GPIO>; + bias-disable; + }; + + pinctrl_usba_vbus: usba_vbus { + pinmux = <PIN_PA31__GPIO>; + bias-disable; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/dra7-evm.dts b/arch/arm/dts/dra7-evm.dts index 08ef04e177b..fe755c05841 100644 --- a/arch/arm/dts/dra7-evm.dts +++ b/arch/arm/dts/dra7-evm.dts @@ -24,6 +24,15 @@ reg = <0x80000000 0x60000000>; /* 1536 MB */ }; + evm_3v3_sd: fixedregulator-sd { + compatible = "regulator-fixed"; + regulator-name = "evm_3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>; + }; + mmc2_3v3: fixedregulator-mmc2 { compatible = "regulator-fixed"; regulator-name = "mmc2_3v3"; @@ -415,6 +424,7 @@ interrupts = <11 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells = <2>; + u-boot,i2c-offset-len = <0>; }; }; @@ -467,7 +477,8 @@ &mmc1 { status = "okay"; - vmmc-supply = <&ldo1_reg>; + vmmc-supply = <&evm_3v3_sd>; + vmmc_aux-supply = <&ldo1_reg>; bus-width = <4>; /* * SDCD signal is not being used here - using the fact that GPIO mode @@ -491,15 +502,13 @@ pinctrl-names = "default"; pinctrl-0 = <&qspi1_pins>; - spi-max-frequency = <48000000>; + spi-max-frequency = <76800000>; m25p80@0 { compatible = "s25fl256s1","spi-flash"; - spi-max-frequency = <48000000>; + spi-max-frequency = <64000000>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; - spi-cpol; - spi-cpha; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/dts/dra72-evm.dts b/arch/arm/dts/dra72-evm.dts index 205103e2b0e..4ca37faa093 100644 --- a/arch/arm/dts/dra72-evm.dts +++ b/arch/arm/dts/dra72-evm.dts @@ -35,6 +35,15 @@ regulator-max-microvolt = <3300000>; }; + evm_3v3_sd: fixedregulator-sd { + compatible = "regulator-fixed"; + regulator-name = "evm_3v3_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>; + }; + extcon_usb1: extcon_usb1 { compatible = "linux,extcon-usb-gpio"; id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; @@ -348,6 +357,7 @@ interrupts = <11 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells = <2>; + u-boot,i2c-offset-len = <0>; }; }; @@ -369,6 +379,7 @@ * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6 */ lines-initial-states = <0x0f2b>; + u-boot,i2c-offset-len = <0>; }; }; @@ -497,7 +508,8 @@ pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins_default>; - vmmc-supply = <&ldo1_reg>; + vmmc_aux-supply = <&ldo1_reg>; + vmmc-supply = <&evm_3v3_sd>; bus-width = <4>; /* * SDCD signal is not being used here - using the fact that GPIO mode @@ -576,6 +588,7 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&cpsw_default>; pinctrl-1 = <&cpsw_sleep>; + mode-gpios = <&pcf_gpio_21 4 GPIO_ACTIVE_HIGH>; }; &cpsw_emac1 { @@ -587,7 +600,6 @@ pinctrl-names = "default", "sleep"; pinctrl-0 = <&davinci_mdio_default>; pinctrl-1 = <&davinci_mdio_sleep>; - active_slave = <1>; }; &dcan1 { @@ -603,15 +615,13 @@ pinctrl-names = "default"; pinctrl-0 = <&qspi1_pins>; - spi-max-frequency = <48000000>; + spi-max-frequency = <76800000>; m25p80@0 { compatible = "s25fl256s1","spi-flash"; - spi-max-frequency = <48000000>; + spi-max-frequency = <64000000>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; - spi-cpol; - spi-cpha; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/dts/exynos4210-origen.dts b/arch/arm/dts/exynos4210-origen.dts index 3f877615844..26c4d7f4c64 100644 --- a/arch/arm/dts/exynos4210-origen.dts +++ b/arch/arm/dts/exynos4210-origen.dts @@ -22,7 +22,7 @@ aliases { serial0 = "/serial@13800000"; console = "/serial@13820000"; - mmc2 = "sdhci@12530000"; + mmc2 = "/sdhci@12530000"; }; sdhci@12510000 { diff --git a/arch/arm/dts/exynos4210-trats.dts b/arch/arm/dts/exynos4210-trats.dts index f3fac801905..2ed38f369e4 100644 --- a/arch/arm/dts/exynos4210-trats.dts +++ b/arch/arm/dts/exynos4210-trats.dts @@ -29,8 +29,8 @@ i2c7 = "/i2c@138d0000"; serial0 = "/serial@13800000"; console = "/serial@13820000"; - mmc0 = "sdhci@12510000"; - mmc2 = "sdhci@12530000"; + mmc0 = "/sdhci@12510000"; + mmc2 = "/sdhci@12530000"; }; fimd@11c00000 { diff --git a/arch/arm/dts/exynos4210-universal_c210.dts b/arch/arm/dts/exynos4210-universal_c210.dts index ad3527ec6f1..8cac7dd752e 100644 --- a/arch/arm/dts/exynos4210-universal_c210.dts +++ b/arch/arm/dts/exynos4210-universal_c210.dts @@ -17,8 +17,8 @@ aliases { serial0 = "/serial@13800000"; console = "/serial@13820000"; - mmc0 = "sdhci@12510000"; - mmc2 = "sdhci@12530000"; + mmc0 = "/sdhci@12510000"; + mmc2 = "/sdhci@12530000"; }; sdhci@12510000 { diff --git a/arch/arm/dts/exynos4412-odroid.dts b/arch/arm/dts/exynos4412-odroid.dts index a63e8abab4a..188cb939bb8 100644 --- a/arch/arm/dts/exynos4412-odroid.dts +++ b/arch/arm/dts/exynos4412-odroid.dts @@ -25,8 +25,8 @@ i2c7 = "/i2c@138d0000"; serial0 = "/serial@13800000"; console = "/serial@13810000"; - mmc2 = "sdhci@12530000"; - mmc4 = "dwmmc@12550000"; + mmc2 = "/sdhci@12530000"; + mmc4 = "/dwmmc@12550000"; }; i2c@13860000 { diff --git a/arch/arm/dts/exynos4412-trats2.dts b/arch/arm/dts/exynos4412-trats2.dts index 2d4e522ea27..1fbcf8914fa 100644 --- a/arch/arm/dts/exynos4412-trats2.dts +++ b/arch/arm/dts/exynos4412-trats2.dts @@ -29,9 +29,9 @@ i2c7 = "/i2c@138d0000"; serial0 = "/serial@13800000"; console = "/serial@13820000"; - mmc0 = "sdhci@12510000"; - mmc2 = "sdhci@12530000"; - mmc4 = "dwmmc@12550000"; + mmc0 = "/sdhci@12510000"; + mmc2 = "/sdhci@12530000"; + mshc0 = "/dwmmc@12550000"; }; i2c@138d0000 { diff --git a/arch/arm/dts/k2e-evm.dts b/arch/arm/dts/k2e-evm.dts index 50c83c21d91..e2c3fb49102 100644 --- a/arch/arm/dts/k2e-evm.dts +++ b/arch/arm/dts/k2e-evm.dts @@ -119,10 +119,11 @@ }; &spi0 { + status = "okay"; nor_flash: n25q128a11@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "Micron,n25q128a11"; + compatible = "Micron,n25q128a11", "spi-flash"; spi-max-frequency = <54000000>; m25p,fast-read; reg = <0>; diff --git a/arch/arm/dts/k2g-evm.dts b/arch/arm/dts/k2g-evm.dts index 0ca36ef39ad..61d0d554333 100644 --- a/arch/arm/dts/k2g-evm.dts +++ b/arch/arm/dts/k2g-evm.dts @@ -31,3 +31,80 @@ &gbe0 { phy-handle = <ðphy0>; }; + +&spi1 { + status = "okay"; + + spi_nor: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <50000000>; + m25p,fast-read; + reg = <0>; + + partition@0 { + label = "u-boot-spl"; + reg = <0x0 0x80000>; + read-only; + }; + + partition@1 { + label = "misc"; + reg = <0x80000 0xf80000>; + }; + }; +}; + +&qspi { + status = "okay"; + + flash0: m25p80@0 { + compatible = "s25fl512s","spi-flash"; + reg = <0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + spi-max-frequency = <96000000>; + #address-cells = <1>; + #size-cells = <1>; + tshsl-ns = <392>; + tsd2d-ns = <392>; + tchsh-ns = <100>; + tslch-ns = <100>; + block-size = <18>; + + + partition@0 { + label = "QSPI.u-boot-spl-os"; + reg = <0x00000000 0x00100000>; + }; + partition@1 { + label = "QSPI.u-boot-env"; + reg = <0x00100000 0x00040000>; + }; + partition@2 { + label = "QSPI.skern"; + reg = <0x00140000 0x0040000>; + }; + partition@3 { + label = "QSPI.pmmc-firmware"; + reg = <0x00180000 0x0040000>; + }; + partition@4 { + label = "QSPI.kernel"; + reg = <0x001C0000 0x0800000>; + }; + partition@5 { + label = "QSPI.file-system"; + reg = <0x009C0000 0x3640000>; + }; + }; +}; + +&mmc0 { + status = "okay"; +}; + +&mmc1 { + status = "okay"; +}; diff --git a/arch/arm/dts/k2g.dtsi b/arch/arm/dts/k2g.dtsi index a3ed444d3c3..add03b74da3 100644 --- a/arch/arm/dts/k2g.dtsi +++ b/arch/arm/dts/k2g.dtsi @@ -19,6 +19,11 @@ aliases { serial0 = &uart0; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + spi3 = &spi3; + spi4 = &qspi; }; memory { @@ -80,6 +85,19 @@ bus_freq = <2500000>; }; + qspi: qspi@2940000 { + compatible = "cadence,qspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x02940000 0x1000>, + <0x24000000 0x4000000>; + interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>; + num-cs = <4>; + fifo-depth = <256>; + sram-size = <256>; + status = "disabled"; + }; + #include "k2g-netcp.dtsi" pmmc: pmmc@2900000 { @@ -88,5 +106,71 @@ ti,lpsc_module = <1>; }; + spi0: spi@21805400 { + compatible = "ti,keystone-spi", "ti,dm6441-spi"; + reg = <0x21805400 0x200>; + num-cs = <4>; + ti,davinci-spi-intr-line = <0>; + interrupts = <GIC_SPI 64 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@21805800 { + compatible = "ti,keystone-spi", "ti,dm6441-spi"; + reg = <0x21805800 0x200>; + num-cs = <4>; + ti,davinci-spi-intr-line = <0>; + interrupts = <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@21805c00 { + compatible = "ti,keystone-spi", "ti,dm6441-spi"; + reg = <0x21805C00 0x200>; + num-cs = <4>; + ti,davinci-spi-intr-line = <0>; + interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi3: spi@21806000 { + compatible = "ti,keystone-spi", "ti,dm6441-spi"; + reg = <0x21806000 0x200>; + num-cs = <4>; + ti,davinci-spi-intr-line = <0>; + interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + mmc0: mmc@23000000 { + compatible = "ti,omap4-hsmmc"; + reg = <0x23000000 0x400>; + interrupts = <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>; + bus-width = <4>; + ti,needs-special-reset; + no-1-8-v; + max-frequency = <96000000>; + status = "disabled"; + }; + + mmc1: mmc@23100000 { + compatible = "ti,omap4-hsmmc"; + reg = <0x23100000 0x400>; + interrupts = <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>; + bus-width = <8>; + ti,needs-special-reset; + ti,non-removable; + max-frequency = <96000000>; + status = "disabled"; + clock-names = "fck"; + }; }; }; diff --git a/arch/arm/dts/k2hk-evm.dts b/arch/arm/dts/k2hk-evm.dts index 660ebf58d54..c5cad2c9da8 100644 --- a/arch/arm/dts/k2hk-evm.dts +++ b/arch/arm/dts/k2hk-evm.dts @@ -147,10 +147,11 @@ }; &spi0 { + status = "okay"; nor_flash: n25q128a11@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "Micron,n25q128a11"; + compatible = "Micron,n25q128a11", "spi-flash"; spi-max-frequency = <54000000>; m25p,fast-read; reg = <0>; diff --git a/arch/arm/dts/k2l-evm.dts b/arch/arm/dts/k2l-evm.dts index 9a69a6b5537..da0661ba3e8 100644 --- a/arch/arm/dts/k2l-evm.dts +++ b/arch/arm/dts/k2l-evm.dts @@ -96,10 +96,11 @@ }; &spi0 { + status ="okay"; nor_flash: n25q128a11@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "Micron,n25q128a11"; + compatible = "Micron,n25q128a11", "spi-flash"; spi-max-frequency = <54000000>; m25p,fast-read; reg = <0>; diff --git a/arch/arm/dts/keystone.dtsi b/arch/arm/dts/keystone.dtsi index f39b969f8d4..be97f3f21f9 100644 --- a/arch/arm/dts/keystone.dtsi +++ b/arch/arm/dts/keystone.dtsi @@ -19,6 +19,9 @@ aliases { serial0 = &uart0; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; }; chosen { diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi index ee0e55461d2..119b1afeb7f 100644 --- a/arch/arm/dts/ls1021a.dtsi +++ b/arch/arm/dts/ls1021a.dtsi @@ -368,7 +368,7 @@ }; usb3@3100000 { - compatible = "snps,dwc3"; + compatible = "fsl,layerscape-dwc3"; reg = <0x3100000 0x10000>; interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; dr_mode = "host"; diff --git a/arch/arm/dts/rk3036-sdk.dts b/arch/arm/dts/rk3036-sdk.dts index a83badb59cb..1c9ddf98561 100644 --- a/arch/arm/dts/rk3036-sdk.dts +++ b/arch/arm/dts/rk3036-sdk.dts @@ -41,6 +41,4 @@ &usb_otg { status = "okay"; - - dr_mode = "host"; }; diff --git a/arch/arm/dts/rk3288-evb.dts b/arch/arm/dts/rk3288-evb.dts new file mode 100644 index 00000000000..3e1ee58a5ee --- /dev/null +++ b/arch/arm/dts/rk3288-evb.dts @@ -0,0 +1,60 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +/dts-v1/; +#include "rk3288-evb.dtsi" + +/ { + model = "Evb-RK3288"; + compatible = "evb-rk3288,evb-rk3288", "rockchip,rk3288"; + + chosen { + stdout-path = &uart2; + }; +}; + +&dmc { + rockchip,num-channels = <2>; + rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d + 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6 + 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0 + 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4 + 0x8 0x1f4>; + rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076 + 0x0 0xc3 0x6 0x2>; + /* Add a dummy value to cause of-platdata think this is bytes */ + rockchip,sdram-channel = /bits/ 8 <0x2 0xa 0x3 0x2 0x2 0x0 0xe 0xe 0xff>; + rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>; +}; + +&pinctrl { + u-boot,dm-pre-reloc; +}; + +&pwm1 { + status = "okay"; +}; + +&uart2 { + u-boot,dm-pre-reloc; + reg-shift = <2>; +}; + +&sdmmc { + u-boot,dm-pre-reloc; +}; + +&emmc { + u-boot,dm-pre-reloc; +}; + +&gpio3 { + u-boot,dm-pre-reloc; +}; + +&gpio8 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3288-evb.dtsi b/arch/arm/dts/rk3288-evb.dtsi new file mode 100644 index 00000000000..cb7d03e5589 --- /dev/null +++ b/arch/arm/dts/rk3288-evb.dtsi @@ -0,0 +1,379 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +#include "rk3288.dtsi" + +/ { + memory { + reg = <0 0x80000000>; + }; + + keys: gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + button@0 { + gpio-key,wakeup = <1>; + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + label = "GPIO Power"; + linux,code = <116>; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key>; + }; + }; + + vcc_sys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_flash: flash-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_flash"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_io>; + }; + + vcc_5v: usb-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + vcc_host_5v: usb-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc_host_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&vcc_5v>; + }; + + vcc_otg_5v: usb-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&otg_vbus_drv>; + regulator-name = "vcc_otg_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&vcc_5v>; + }; +}; + +&cpu0 { + cpu0-supply = <&vdd_cpu>; +}; + +&emmc { + broken-cd; + bus-width = <8>; + cap-mmc-highspeed; + disable-wp; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc_flash>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c5>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + vdd_cpu: syr827@40 { + compatible = "silergy,syr827"; + fcs,suspend-voltage-selector = <1>; + reg = <0x40>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + vdd_gpu: syr828@41 { + compatible = "silergy,syr828"; + fcs,suspend-voltage-selector = <1>; + reg = <0x41>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + interrupt-parent = <&gpio7>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + }; + + act8846: act8846@5a { + compatible = "active-semi,act8846"; + reg = <0x5a>; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_hold>; + system-power-controller; + + regulators { + vcc_ddr: REG1 { + regulator-name = "vcc_ddr"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vcc_io: REG2 { + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_log: REG3 { + regulator-name = "vdd_log"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + vcc_20: REG4 { + regulator-name = "vcc_20"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + }; + + vccio_sd: REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd10_lcd: REG6 { + regulator-name = "vdd10_lcd"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vcca_codec: REG7 { + regulator-name = "vcca_codec"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc_tp: REG8 { + regulator-name = "vcca_33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vccio_pmu: REG9 { + regulator-name = "vccio_pmu"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vdd_10: REG10 { + regulator-name = "vdd_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vcc_18: REG11 { + regulator-name = "vcc_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcc18_lcd: REG12 { + regulator-name = "vcc18_lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&pinctrl { + pcfg_output_high: pcfg-output-high { + output-high; + }; + + pcfg_output_low: pcfg-output-low { + output-low; + }; + + act8846 { + pwr_hold: pwr-hold { + rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + hym8563 { + rtc_int: rtc-int { + rockchip,pins = <0 4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + keys { + pwr_key: pwr-key { + rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdmmc { + sdmmc_pwr: sdmmc-pwr { + rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb_host { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb_otg { + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&saradc { + vref-supply = <&vcc_18>; + status = "okay"; +}; + +&sdio0 { + broken-cd; + bus-width = <4>; + disable-wp; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4>, <&sdio0_cmd>, <&sdio0_clk>; + vmmc-supply = <&vcc_18>; + status = "disabled"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; + vmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_clk>, <&spi0_cs0>, <&spi0_tx>, <&spi0_rx>, <&spi0_cs1>; + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>, <&uart0_cts>, <&uart0_rts>; + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usb_host1 { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3288-fennec.dts b/arch/arm/dts/rk3288-fennec.dts new file mode 100644 index 00000000000..36e9f3dac56 --- /dev/null +++ b/arch/arm/dts/rk3288-fennec.dts @@ -0,0 +1,60 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +/dts-v1/; +#include "rk3288-fennec.dtsi" + +/ { + model = "Rockchip RK3288 Fennec Board"; + compatible = "rockchip,rk3288-fennec", "rockchip,rk3288"; + + chosen { + stdout-path = &uart2; + }; +}; + +&dmc { + rockchip,num-channels = <2>; + rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d + 0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6 + 0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0 + 0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4 + 0x8 0x1f4>; + rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076 + 0x0 0xc3 0x6 0x2>; + /* Add a dummy value to cause of-platdata think this is bytes */ + rockchip,sdram-channel = /bits/ 8 <0x2 0xa 0x3 0x2 0x2 0x0 0xe 0xe 0xff>; + rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>; +}; + +&pinctrl { + u-boot,dm-pre-reloc; +}; + +&pwm1 { + status = "okay"; +}; + +&uart2 { + u-boot,dm-pre-reloc; + reg-shift = <2>; +}; + +&sdmmc { + u-boot,dm-pre-reloc; +}; + +&emmc { + u-boot,dm-pre-reloc; +}; + +&gpio3 { + u-boot,dm-pre-reloc; +}; + +&gpio8 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3288-fennec.dtsi b/arch/arm/dts/rk3288-fennec.dtsi new file mode 100644 index 00000000000..f61252ce9dc --- /dev/null +++ b/arch/arm/dts/rk3288-fennec.dtsi @@ -0,0 +1,421 @@ +/* + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "rk3288.dtsi" + +/ { + memory { + reg = <0x0 0x80000000>; + device_type = "memory"; + }; + + ext_gmac: external-gmac-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + }; + + vcc_sys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&cpu0 { + cpu0-supply = <&vdd_cpu>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + disable-wp; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + status = "okay"; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; +}; + +&gmac { + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + clock_in_out = "input"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>; + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>; + tx_delay = <0x30>; + rx_delay = <0x10>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio0>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int &global_pwroff>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_io>; + vcc9-supply = <&vcc_io>; + vcc10-supply = <&vcc_io>; + vcc11-supply = <&vcc_io>; + vcc12-supply = <&vcc_io>; + vddio-supply = <&vcc_io>; + + regulators { + vdd_cpu: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-name = "vdd_arm"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_io"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vccio_pmu: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_33: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcca_33"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_10: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd_10"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_wl: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_wl"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd10_lcd: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd10_lcd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_18: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_18"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc18_lcd: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_lcd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sd: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_lan: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_lan"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + }; + }; +}; + +&pinctrl { + pcfg_output_high: pcfg-output-high { + output-high; + }; + + pcfg_output_low: pcfg-output-low { + output-low; + }; + + pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { + drive-strength = <8>; + }; + + pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { + bias-pull-up; + drive-strength = <8>; + }; + + gmac { + phy_int: phy-int { + rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_pmeb: phy-pmeb { + rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_rst: phy-rst { + rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdmmc { + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, + <6 17 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, + <6 18 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, + <6 19 RK_FUNC_1 &pcfg_pull_up_drv_8ma>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_8ma>; + }; + + sdmmc_pwr: sdmmc-pwr { + rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usbphy { + host_drv: host-drv { + rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&host_drv>; + vbus_drv-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host1 { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&usb_hsic { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&vpu { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3288-firefly.dts b/arch/arm/dts/rk3288-firefly.dts index aed8d3a712b..3176d5046b2 100644 --- a/arch/arm/dts/rk3288-firefly.dts +++ b/arch/arm/dts/rk3288-firefly.dts @@ -30,7 +30,8 @@ 0x5 0x0>; rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200 0xa60 0x40 0x10 0x0>; - rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf>; + /* Add a dummy value to cause of-platdata think this is bytes */ + rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf 0xff>; rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>; }; diff --git a/arch/arm/dts/rk3288-miniarm.dts b/arch/arm/dts/rk3288-miniarm.dts new file mode 100644 index 00000000000..c7410821d36 --- /dev/null +++ b/arch/arm/dts/rk3288-miniarm.dts @@ -0,0 +1,61 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +/dts-v1/; +#include "rk3288-miniarm.dtsi" + +/ { + model = "Miniarm-RK3288"; + compatible = "rockchip,rk3288-miniarm", "rockchip,rk3288"; + + chosen { + stdout-path = &uart2; + }; +}; + +&dmc { + rockchip,num-channels = <2>; + rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa + 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7 + 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0 + 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0 + 0x5 0x0>; + rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200 + 0xa60 0x40 0x10 0x0>; + /* Add a dummy value to cause of-platdata think this is bytes */ + rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf 0xff>; + rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>; +}; + + +&pinctrl { + u-boot,dm-pre-reloc; +}; + +&pwm1 { + status = "okay"; +}; + +&uart2 { + u-boot,dm-pre-reloc; + reg-shift = <2>; +}; + +&sdmmc { + u-boot,dm-pre-reloc; +}; + +&emmc { + u-boot,dm-pre-reloc; +}; + +&gpio3 { + u-boot,dm-pre-reloc; +}; + +&gpio8 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3288-miniarm.dtsi b/arch/arm/dts/rk3288-miniarm.dtsi new file mode 100644 index 00000000000..b88987557a6 --- /dev/null +++ b/arch/arm/dts/rk3288-miniarm.dtsi @@ -0,0 +1,533 @@ +/* + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "rk3288.dtsi" + +/ { + memory { + device_type = "memory"; + reg = <0x0 0x80000000>; + }; + + ext_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + #clock-cells = <0>; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&pwrbtn>; + + button@0 { + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + label = "GPIO Key Power"; + linux,input-type = <1>; + gpio-key,wakeup = <1>; + debounce-interval = <100>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + pwr-led { + gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + act-led { + gpios=<&gpio2 3 GPIO_ACTIVE_LOW>; + linux,default-trigger="mmc0"; + }; + }; + + vcc_sys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + /* + * NOTE: vcc_sd isn't hooked up on v1.0 boards where power comes from + * vcc_io directly. Those boards won't be able to power cycle SD cards + * but it shouldn't hurt to toggle this pin there anyway. + */ + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio7 11 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwr>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; +}; + +&cpu0 { + cpu0-supply = <&vdd_cpu>; +}; + +&emmc { + broken-cd; + bus-width = <8>; + cap-mmc-highspeed; + disable-wp; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; /* wp not hooked up */ + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + status = "okay"; + supports-sd; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&gmac { + phy-supply = <&vcc33_lan>; + phy-mode = "rgmii"; + clock_in_out = "input"; + snps,reset-gpio = <&gpio4 7 0>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + tx_delay = <0x30>; + rx_delay = <0x10>; + status = "ok"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c5>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio0>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int &global_pwroff>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_18>; + vcc9-supply = <&vcc_io>; + vcc10-supply = <&vcc_io>; + vcc11-supply = <&vcc_sys>; + vcc12-supply = <&vcc_io>; + vddio-supply = <&vcc18_ldo1>; + + regulators { + vdd_cpu: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-name = "vdd_arm"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_io"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc18_ldo1: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_ldo1"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc33_mipi: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc33_mipi"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_10: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd_10"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc18_codec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_codec"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd10_lcd: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd10_lcd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_18: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_18"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc18_lcd: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_lcd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc33_sd: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc33_sd"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc33_lan: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc33_lan"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + }; + }; +}; + +&i2c2 { + status = "okay"; + headset: nau8825@1a { + compatible = "nuvoton,nau8825"; + #sound-dai-cells = <0>; + reg = <0x1a>; + interrupt-parent = <&gpio6>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + nuvoton,jkdet-enable = <1>; + nuvoton,jkdet-pull-enable = <1>; + nuvoton,jkdet-pull-up = <0>; + nuvoton,jkdet-polarity = <1>; + nuvoton,vref-impedance = <2>; + nuvoton,micbias-voltage = <6>; + nuvoton,sar-threshold-num = <4>; + nuvoton,sar-threshold = <0xa 0x14 0x26 0x73>; + nuvoton,sar-hysteresis = <0>; + nuvoton,sar-voltage = <6>; + nuvoton,sar-compare-time = <0>; + nuvoton,sar-sampling-time = <0>; + nuvoton,short-key-debounce = <3>; + nuvoton,jack-insert-debounce = <7>; + nuvoton,jack-eject-debounce = <7>; + clock-names = "mclk"; + clocks = <&cru SCLK_I2S0_OUT>; + }; +}; + +&i2c5 { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc18_ldo1>; + status ="okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host1 { + status = "okay"; +}; + +&usb_otg { + status= "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&pinctrl { + pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { + drive-strength = <8>; + }; + + pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { + bias-pull-up; + drive-strength = <8>; + }; + + backlight { + bl_en: bl-en { + rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + buttons { + pwrbtn: pwrbtn { + rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + eth_phy { + eth_phy_pwr: eth-phy-pwr { + rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdmmc { + /* + * Default drive strength isn't enough to achieve even + * high-speed mode on EVB board so bump up to 8ma. + */ + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, + <6 17 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, + <6 18 RK_FUNC_1 &pcfg_pull_up_drv_8ma>, + <6 19 RK_FUNC_1 &pcfg_pull_up_drv_8ma>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_8ma>; + }; + + sdmmc_pwr: sdmmc-pwr { + rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + pwr_3g: pwr-3g { + rockchip,pins = <7 8 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm/dts/rk3288-popmetal.dts b/arch/arm/dts/rk3288-popmetal.dts new file mode 100644 index 00000000000..3f61a61f97c --- /dev/null +++ b/arch/arm/dts/rk3288-popmetal.dts @@ -0,0 +1,61 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +/dts-v1/; +#include "rk3288-popmetal.dtsi" + +/ { + model = "PopMetal-RK3288"; + compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288"; + + chosen { + stdout-path = &uart2; + }; +}; + +&dmc { + rockchip,num-channels = <2>; + rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa + 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7 + 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0 + 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0 + 0x5 0x0>; + rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200 + 0xa60 0x40 0x10 0x0>; + /* Add a dummy value to cause of-platdata think this is bytes */ + rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf 0xff>; + rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>; +}; + + +&pinctrl { + u-boot,dm-pre-reloc; +}; + +&pwm1 { + status = "okay"; +}; + +&uart2 { + u-boot,dm-pre-reloc; + reg-shift = <2>; +}; + +&sdmmc { + u-boot,dm-pre-reloc; +}; + +&emmc { + u-boot,dm-pre-reloc; +}; + +&gpio3 { + u-boot,dm-pre-reloc; +}; + +&gpio8 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3288-popmetal.dtsi b/arch/arm/dts/rk3288-popmetal.dtsi new file mode 100644 index 00000000000..f3bd4685bd4 --- /dev/null +++ b/arch/arm/dts/rk3288-popmetal.dtsi @@ -0,0 +1,520 @@ +/* + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "rk3288.dtsi" + +/ { + memory{ + device_type = "memory"; + reg = <0 0x80000000>; + }; + + ext_gmac: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + #clock-cells = <0>; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + pinctrl-names = "default"; + pinctrl-0 = <&pwrbtn>; + + power { + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + label = "GPIO Key Power"; + linux,input-type = <1>; + wakeup-source; + debounce-interval = <100>; + }; + }; + + io_domains: io-domains { + compatible = "rockchip,rk3288-io-voltage-domain"; + rockchip,grf = <&grf>; + + audio-supply = <&vcca_33>; + bb-supply = <&vcc_io>; + dvp-supply = <&vcc18_dvp>; + flash0-supply = <&vcc_flash>; + flash1-supply = <&vcc_lan>; + gpio30-supply = <&vcc_io>; + gpio1830-supply = <&vcc_io>; + lcdc-supply = <&vcc_io>; + sdcard-supply = <&vccio_sd>; + wifi-supply = <&vccio_wl>; + }; + + ir: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&ir_int>; + }; + + vcc_flash: flash-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_flash"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_io>; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio7 11 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwr>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; + + vcc_sys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + /* + * A PT5128 creates both dovdd_1v8 and vcc28_dvp, controlled + * by the dvp_pwr pin. + */ + vcc18_dvp: vcc18-dvp-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc18-dvp"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc28_dvp>; + }; + + vcc28_dvp: vcc28-dvp-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dvp_pwr>; + regulator-name = "vcc28_dvp"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + vin-supply = <&vcc_io>; + }; +}; + +&cpu0 { + cpu0-supply = <&vdd_cpu>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + disable-wp; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc_flash>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&gmac { + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + clock_in_out = "input"; + snps,reset-gpio = <&gpio4 7 0>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + tx_delay = <0x30>; + rx_delay = <0x10>; + status = "ok"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c5>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio0>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int &global_pwroff>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_18>; + vcc9-supply = <&vcc_io>; + vcc10-supply = <&vcc_io>; + vcc11-supply = <&vcc_sys>; + vcc12-supply = <&vcc_io>; + vddio-supply = <&vcc_io>; + + regulators { + vdd_cpu: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-name = "vdd_arm"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_io"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_lan: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_lan"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vccio_sd: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_10: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd_10"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc18_lcd: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_lcd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + ldo5: LDO_REG5 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "ldo5"; + }; + + vdd10_lcd: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd10_lcd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_18: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_18"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca_33: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcca_33"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vccio_wl: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vccio_wl"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_lcd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_lcd"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + ak8963: ak8963@0d { + compatible = "asahi-kasei,ak8975"; + reg = <0x0d>; + interrupt-parent = <&gpio8>; + interrupts = <1 IRQ_TYPE_EDGE_RISING>; + pinctrl-names = "default"; + pinctrl-0 = <&comp_int>; + }; + + l3g4200d: l3g4200d@68 { + compatible = "st,l3g4200d-gyro"; + st,drdy-int-pin = <2>; + reg = <0x6b>; + }; + + mma8452: mma8452@1d { + compatible = "fsl,mma8452"; + reg = <0x1d>; + interrupt-parent = <&gpio8>; + interrupts = <0 IRQ_TYPE_EDGE_RISING>; + pinctrl-names = "default"; + pinctrl-0 = <&gsensor_int>; + }; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&pinctrl { + ak8963 { + comp_int: comp-int { + rockchip,pins = <8 1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + buttons { + pwrbtn: pwrbtn { + rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + dvp { + dvp_pwr: dvp-pwr { + rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + ir { + ir_int: ir-int { + rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + mma8452 { + gsensor_int: gsensor-int { + rockchip,pins = <8 0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdmmc { + sdmmc_pwr: sdmmc-pwr { + rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&tsadc { + rockchip,hw-tshut-mode = <0>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3288-rock2-square.dts b/arch/arm/dts/rk3288-rock2-square.dts index 34073c94050..2c30355f06b 100644 --- a/arch/arm/dts/rk3288-rock2-square.dts +++ b/arch/arm/dts/rk3288-rock2-square.dts @@ -192,7 +192,7 @@ 0x5 0x0>; rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200 0xa60 0x40 0x10 0x0>; - rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf>; + rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf 0xff>; rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>; }; diff --git a/arch/arm/dts/rk3288-veyron.dtsi b/arch/arm/dts/rk3288-veyron.dtsi index 421d21290ca..d9d51879f03 100644 --- a/arch/arm/dts/rk3288-veyron.dtsi +++ b/arch/arm/dts/rk3288-veyron.dtsi @@ -253,7 +253,7 @@ 0x5 0x0>; rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200 0xa60 0x40 0x10 0x0>; - rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf>; + rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf 0xff>; rockchip,sdram-params = <0x30B25564 0x627 3 666000000 3 9 1>; }; diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi index 3dab0fc83ea..bcf051a9d9b 100644 --- a/arch/arm/dts/rk3288.dtsi +++ b/arch/arm/dts/rk3288.dtsi @@ -454,6 +454,7 @@ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cru HCLK_OTG0>; clock-names = "otg"; + dr_mode = "otg"; phys = <&usbphy0>; phy-names = "usb2-phy"; status = "disabled"; diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts new file mode 100644 index 00000000000..e92a492545d --- /dev/null +++ b/arch/arm/dts/rk3399-evb.dts @@ -0,0 +1,108 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include <dt-bindings/pwm/pwm.h> +#include "rk3399.dtsi" + +/ { + model = "Rockchip RK3399 Evaluation Board"; + compatible = "rockchip,rk3399-evb", "rockchip,rk3399", + "google,rk3399evb-rev2"; + + chosen { + stdout-path = &uart2; + }; + + vdd_center: vdd-center { + compatible = "pwm-regulator"; + pwms = <&pwm3 0 25000 0>; + regulator-name = "vdd_center"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + status = "okay"; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; +}; + +&emmc_phy { + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&sdmmc { + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + non-removable; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&pinctrl { + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = + <1 21 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + pmic_dvs2: pmic-dvs2 { + rockchip,pins = + <1 18 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi new file mode 100644 index 00000000000..a4c6e27b391 --- /dev/null +++ b/arch/arm/dts/rk3399.dtsi @@ -0,0 +1,1028 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dt-bindings/clock/rk3399-cru.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/rockchip.h> + +/ { + compatible = "rockchip,rk3399"; + + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu_l0>; + }; + core1 { + cpu = <&cpu_l1>; + }; + core2 { + cpu = <&cpu_l2>; + }; + core3 { + cpu = <&cpu_l3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu_b0>; + }; + core1 { + cpu = <&cpu_b1>; + }; + }; + }; + + cpu_l0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + #cooling-cells = <2>; /* min followed by max */ + clocks = <&cru ARMCLKL>; + }; + + cpu_l1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + clocks = <&cru ARMCLKL>; + }; + + cpu_l2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + clocks = <&cru ARMCLKL>; + }; + + cpu_l3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + clocks = <&cru ARMCLKL>; + }; + + cpu_b0: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + #cooling-cells = <2>; /* min followed by max */ + clocks = <&cru ARMCLKB>; + }; + + cpu_b1: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a72", "arm,armv8"; + reg = <0x0 0x101>; + enable-method = "psci"; + clocks = <&cru ARMCLKB>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + }; + + xin24m: xin24m { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + amba { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dmac_bus: dma-controller@ff6d0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xff6d0000 0x0 0x4000>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + clocks = <&cru ACLK_DMAC0_PERILP>; + clock-names = "apb_pclk"; + }; + + dmac_peri: dma-controller@ff6e0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x0 0xff6e0000 0x0 0x4000>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + clocks = <&cru ACLK_DMAC1_PERILP>; + clock-names = "apb_pclk"; + }; + }; + + sdio0: dwmmc@fe310000 { + compatible = "rockchip,rk3399-dw-mshc", + "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe310000 0x0 0x4000>; + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; + clock-freq-min-max = <400000 150000000>; + clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + status = "disabled"; + }; + + sdmmc: dwmmc@fe320000 { + compatible = "rockchip,rk3399-dw-mshc", + "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xfe320000 0x0 0x4000>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + clock-freq-min-max = <400000 150000000>; + clocks = <&cru SCLK_SDMMC>, <&cru HCLK_SDMMC>, + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "ciu", "biu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + status = "disabled"; + }; + + sdhci: sdhci@fe330000 { + compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; + reg = <0x0 0xfe330000 0x0 0x10000>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + assigned-clocks = <&cru SCLK_EMMC>; + assigned-clock-rates = <200000000>; + clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; + clock-names = "clk_xin", "clk_ahb"; + phys = <&emmc_phy>; + phy-names = "phy_arasan"; + status = "disabled"; + }; + + usb_host0_ehci: usb@fe380000 { + compatible = "generic-ehci"; + reg = <0x0 0xfe380000 0x0 0x20000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>; + clock-names = "hclk_host0", "hclk_host0_arb"; + status = "disabled"; + }; + + usb_host0_ohci: usb@fe3a0000 { + compatible = "generic-ohci"; + reg = <0x0 0xfe3a0000 0x0 0x20000>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>; + clock-names = "hclk_host0", "hclk_host0_arb"; + status = "disabled"; + }; + + usb_host1_ehci: usb@fe3c0000 { + compatible = "generic-ehci"; + reg = <0x0 0xfe3c0000 0x0 0x20000>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>; + clock-names = "hclk_host1", "hclk_host1_arb"; + status = "disabled"; + }; + + usb_host1_ohci: usb@fe3e0000 { + compatible = "generic-ohci"; + reg = <0x0 0xfe3e0000 0x0 0x20000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>; + clock-names = "hclk_host1", "hclk_host1_arb"; + status = "disabled"; + }; + + gic: interrupt-controller@fee00000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + + reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ + <0x0 0xfef00000 0 0xc0000>, /* GICR */ + <0x0 0xfff00000 0 0x10000>, /* GICC */ + <0x0 0xfff10000 0 0x10000>, /* GICH */ + <0x0 0xfff20000 0 0x10000>; /* GICV */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + its: interrupt-controller@fee20000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0xfee20000 0x0 0x20000>; + }; + }; + + uart0: serial@ff180000 { + compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff180000 0x0 0x100>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>; + status = "disabled"; + }; + + uart1: serial@ff190000 { + compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff190000 0x0 0x100>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer>; + status = "disabled"; + }; + + uart2: serial@ff1a0000 { + compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff1a0000 0x0 0x100>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <24000000>; + reg-shift = <2>; + reg-io-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2c_xfer>; + status = "disabled"; + }; + + uart3: serial@ff1b0000 { + compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff1b0000 0x0 0x100>; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&uart3_xfer>; + status = "disabled"; + }; + + spi0: spi@ff1c0000 { + compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff1c0000 0x0 0x1000>; + clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; + clock-names = "spiclk", "apb_pclk"; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@ff1d0000 { + compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff1d0000 0x0 0x1000>; + clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; + clock-names = "spiclk", "apb_pclk"; + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@ff1e0000 { + compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff1e0000 0x0 0x1000>; + clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; + clock-names = "spiclk", "apb_pclk"; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi4: spi@ff1f0000 { + compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff1f0000 0x0 0x1000>; + clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; + clock-names = "spiclk", "apb_pclk"; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi5: spi@ff200000 { + compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff200000 0x0 0x1000>; + clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; + clock-names = "spiclk", "apb_pclk"; + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + pmugrf: syscon@ff320000 { + compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; + reg = <0x0 0xff320000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + pmu_io_domains: io-domains { + compatible = "rockchip,rk3399-pmu-io-voltage-domain"; + status = "disabled"; + }; + }; + + spi3: spi@ff350000 { + compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; + reg = <0x0 0xff350000 0x0 0x1000>; + clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; + clock-names = "spiclk", "apb_pclk"; + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart4: serial@ff370000 { + compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; + reg = <0x0 0xff370000 0x0 0x100>; + clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; + clock-names = "baudclk", "apb_pclk"; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_xfer>; + status = "disabled"; + }; + + pwm0: pwm@ff420000 { + compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; + reg = <0x0 0xff420000 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + clocks = <&pmucru PCLK_RKPWM_PMU>; + clock-names = "pwm"; + status = "disabled"; + }; + + pwm1: pwm@ff420010 { + compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; + reg = <0x0 0xff420010 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_pin>; + clocks = <&pmucru PCLK_RKPWM_PMU>; + clock-names = "pwm"; + status = "disabled"; + }; + + pwm2: pwm@ff420020 { + compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; + reg = <0x0 0xff420020 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pin>; + clocks = <&pmucru PCLK_RKPWM_PMU>; + clock-names = "pwm"; + status = "disabled"; + }; + + pwm3: pwm@ff420030 { + compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; + reg = <0x0 0xff420030 0x0 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3a_pin>; + clocks = <&pmucru PCLK_RKPWM_PMU>; + clock-names = "pwm"; + status = "disabled"; + }; + + pmucru: pmu-clock-controller@ff750000 { + compatible = "rockchip,rk3399-pmucru"; + reg = <0x0 0xff750000 0x0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + assigned-clocks = <&pmucru PLL_PPLL>; + assigned-clock-rates = <676000000>; + }; + + cru: clock-controller@ff760000 { + compatible = "rockchip,rk3399-cru"; + reg = <0x0 0xff760000 0x0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + assigned-clocks = + <&cru PLL_GPLL>, <&cru PLL_CPLL>, + <&cru PLL_NPLL>, + <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, + <&cru PCLK_PERIHP>, + <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, + <&cru PCLK_PERILP0>, + <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>; + assigned-clock-rates = + <594000000>, <800000000>, + <1000000000>, + <150000000>, <75000000>, + <37500000>, + <100000000>, <100000000>, + <50000000>, + <100000000>, <50000000>; + }; + + grf: syscon@ff770000 { + compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; + reg = <0x0 0xff770000 0x0 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + + io_domains: io-domains { + compatible = "rockchip,rk3399-io-voltage-domain"; + status = "disabled"; + }; + + emmc_phy: phy@f780 { + compatible = "rockchip,rk3399-emmc-phy"; + reg = <0xf780 0x24>; + #phy-cells = <0>; + status = "disabled"; + }; + }; + + watchdog@ff840000 { + compatible = "snps,dw-wdt"; + reg = <0x0 0xff840000 0x0 0x100>; + clocks = <&cru PCLK_WDT>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + }; + + spdif: spdif@ff870000 { + compatible = "rockchip,rk3399-spdif"; + reg = <0x0 0xff870000 0x0 0x1000>; + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmac_bus 7>; + dma-names = "tx"; + clock-names = "mclk", "hclk"; + clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; + pinctrl-names = "default"; + pinctrl-0 = <&spdif_bus>; + status = "disabled"; + }; + + i2s0: i2s@ff880000 { + compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xff880000 0x0 0x1000>; + rockchip,grf = <&grf>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmac_bus 0>, <&dmac_bus 1>; + dma-names = "tx", "rx"; + clock-names = "i2s_clk", "i2s_hclk"; + clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_8ch_bus>; + status = "disabled"; + }; + + i2s1: i2s@ff890000 { + compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xff890000 0x0 0x1000>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmac_bus 2>, <&dmac_bus 3>; + dma-names = "tx", "rx"; + clock-names = "i2s_clk", "i2s_hclk"; + clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_2ch_bus>; + status = "disabled"; + }; + + i2s2: i2s@ff8a0000 { + compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; + reg = <0x0 0xff8a0000 0x0 0x1000>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmac_bus 4>, <&dmac_bus 5>; + dma-names = "tx", "rx"; + clock-names = "i2s_clk", "i2s_hclk"; + clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; + status = "disabled"; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3399-pinctrl"; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmugrf>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio0: gpio0@ff720000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff720000 0x0 0x100>; + clocks = <&pmucru PCLK_GPIO0_PMU>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <0x2>; + + interrupt-controller; + #interrupt-cells = <0x2>; + }; + + gpio1: gpio1@ff730000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff730000 0x0 0x100>; + clocks = <&pmucru PCLK_GPIO1_PMU>; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <0x2>; + + interrupt-controller; + #interrupt-cells = <0x2>; + }; + + gpio2: gpio2@ff780000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff780000 0x0 0x100>; + clocks = <&cru PCLK_GPIO2>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <0x2>; + + interrupt-controller; + #interrupt-cells = <0x2>; + }; + + gpio3: gpio3@ff788000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff788000 0x0 0x100>; + clocks = <&cru PCLK_GPIO3>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <0x2>; + + interrupt-controller; + #interrupt-cells = <0x2>; + }; + + gpio4: gpio4@ff790000 { + compatible = "rockchip,gpio-bank"; + reg = <0x0 0xff790000 0x0 0x100>; + clocks = <&cru PCLK_GPIO4>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <0x2>; + + interrupt-controller; + #interrupt-cells = <0x2>; + }; + + pcfg_pull_up: pcfg-pull-up { + bias-pull-up; + }; + + pcfg_pull_down: pcfg-pull-down { + bias-pull-down; + }; + + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + pcfg_pull_none_12ma: pcfg-pull-none-12ma { + bias-disable; + drive-strength = <12>; + }; + + pcfg_pull_up_8ma: pcfg-pull-up-8ma { + bias-pull-up; + drive-strength = <8>; + }; + + pcfg_pull_down_4ma: pcfg-pull-down-4ma { + bias-pull-down; + drive-strength = <4>; + }; + + pcfg_pull_up_2ma: pcfg-pull-up-2ma { + bias-pull-up; + drive-strength = <2>; + }; + + pcfg_pull_down_12ma: pcfg-pull-down-12ma { + bias-pull-down; + drive-strength = <12>; + }; + + pcfg_pull_none_13ma: pcfg-pull-none-13ma { + bias-disable; + drive-strength = <13>; + }; + + i2c0 { + i2c0_xfer: i2c0-xfer { + rockchip,pins = + <1 15 RK_FUNC_2 &pcfg_pull_none>, + <1 16 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = + <4 2 RK_FUNC_1 &pcfg_pull_none>, + <4 1 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2c2 { + i2c2_xfer: i2c2-xfer { + rockchip,pins = + <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>, + <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>; + }; + }; + + i2c3 { + i2c3_xfer: i2c3-xfer { + rockchip,pins = + <4 17 RK_FUNC_1 &pcfg_pull_none>, + <4 16 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2c4 { + i2c4_xfer: i2c4-xfer { + rockchip,pins = + <1 12 RK_FUNC_1 &pcfg_pull_none>, + <1 11 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2c5 { + i2c5_xfer: i2c5-xfer { + rockchip,pins = + <3 11 RK_FUNC_2 &pcfg_pull_none>, + <3 10 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + i2c6 { + i2c6_xfer: i2c6-xfer { + rockchip,pins = + <2 10 RK_FUNC_2 &pcfg_pull_none>, + <2 9 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + i2c7 { + i2c7_xfer: i2c7-xfer { + rockchip,pins = + <2 8 RK_FUNC_2 &pcfg_pull_none>, + <2 7 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + i2c8 { + i2c8_xfer: i2c8-xfer { + rockchip,pins = + <1 21 RK_FUNC_1 &pcfg_pull_none>, + <1 20 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2s0 { + i2s0_8ch_bus: i2s0-8ch-bus { + rockchip,pins = + <3 24 RK_FUNC_1 &pcfg_pull_none>, + <3 25 RK_FUNC_1 &pcfg_pull_none>, + <3 26 RK_FUNC_1 &pcfg_pull_none>, + <3 27 RK_FUNC_1 &pcfg_pull_none>, + <3 28 RK_FUNC_1 &pcfg_pull_none>, + <3 29 RK_FUNC_1 &pcfg_pull_none>, + <3 30 RK_FUNC_1 &pcfg_pull_none>, + <3 31 RK_FUNC_1 &pcfg_pull_none>, + <4 0 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + i2s1 { + i2s1_2ch_bus: i2s1-2ch-bus { + rockchip,pins = + <4 3 RK_FUNC_1 &pcfg_pull_none>, + <4 4 RK_FUNC_1 &pcfg_pull_none>, + <4 5 RK_FUNC_1 &pcfg_pull_none>, + <4 6 RK_FUNC_1 &pcfg_pull_none>, + <4 7 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + spdif { + spdif_bus: spdif-bus { + rockchip,pins = + <4 21 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + spi0 { + spi0_clk: spi0-clk { + rockchip,pins = + <3 6 RK_FUNC_2 &pcfg_pull_up>; + }; + spi0_cs0: spi0-cs0 { + rockchip,pins = + <3 7 RK_FUNC_2 &pcfg_pull_up>; + }; + spi0_cs1: spi0-cs1 { + rockchip,pins = + <3 8 RK_FUNC_2 &pcfg_pull_up>; + }; + spi0_tx: spi0-tx { + rockchip,pins = + <3 5 RK_FUNC_2 &pcfg_pull_up>; + }; + spi0_rx: spi0-rx { + rockchip,pins = + <3 4 RK_FUNC_2 &pcfg_pull_up>; + }; + }; + + spi1 { + spi1_clk: spi1-clk { + rockchip,pins = + <1 9 RK_FUNC_2 &pcfg_pull_up>; + }; + spi1_cs0: spi1-cs0 { + rockchip,pins = + <1 10 RK_FUNC_2 &pcfg_pull_up>; + }; + spi1_rx: spi1-rx { + rockchip,pins = + <1 7 RK_FUNC_2 &pcfg_pull_up>; + }; + spi1_tx: spi1-tx { + rockchip,pins = + <1 8 RK_FUNC_2 &pcfg_pull_up>; + }; + }; + + spi2 { + spi2_clk: spi2-clk { + rockchip,pins = + <2 11 RK_FUNC_1 &pcfg_pull_up>; + }; + spi2_cs0: spi2-cs0 { + rockchip,pins = + <2 12 RK_FUNC_1 &pcfg_pull_up>; + }; + spi2_rx: spi2-rx { + rockchip,pins = + <2 9 RK_FUNC_1 &pcfg_pull_up>; + }; + spi2_tx: spi2-tx { + rockchip,pins = + <2 10 RK_FUNC_1 &pcfg_pull_up>; + }; + }; + + spi3 { + spi3_clk: spi3-clk { + rockchip,pins = + <1 17 RK_FUNC_1 &pcfg_pull_up>; + }; + spi3_cs0: spi3-cs0 { + rockchip,pins = + <1 18 RK_FUNC_1 &pcfg_pull_up>; + }; + spi3_rx: spi3-rx { + rockchip,pins = + <1 15 RK_FUNC_1 &pcfg_pull_up>; + }; + spi3_tx: spi3-tx { + rockchip,pins = + <1 16 RK_FUNC_1 &pcfg_pull_up>; + }; + }; + + spi4 { + spi4_clk: spi4-clk { + rockchip,pins = + <3 2 RK_FUNC_2 &pcfg_pull_up>; + }; + spi4_cs0: spi4-cs0 { + rockchip,pins = + <3 3 RK_FUNC_2 &pcfg_pull_up>; + }; + spi4_rx: spi4-rx { + rockchip,pins = + <3 0 RK_FUNC_2 &pcfg_pull_up>; + }; + spi4_tx: spi4-tx { + rockchip,pins = + <3 1 RK_FUNC_2 &pcfg_pull_up>; + }; + }; + + spi5 { + spi5_clk: spi5-clk { + rockchip,pins = + <2 22 RK_FUNC_2 &pcfg_pull_up>; + }; + spi5_cs0: spi5-cs0 { + rockchip,pins = + <2 23 RK_FUNC_2 &pcfg_pull_up>; + }; + spi5_rx: spi5-rx { + rockchip,pins = + <2 20 RK_FUNC_2 &pcfg_pull_up>; + }; + spi5_tx: spi5-tx { + rockchip,pins = + <2 21 RK_FUNC_2 &pcfg_pull_up>; + }; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = + <2 16 RK_FUNC_1 &pcfg_pull_up>, + <2 17 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_cts: uart0-cts { + rockchip,pins = + <2 18 RK_FUNC_1 &pcfg_pull_none>; + }; + + uart0_rts: uart0-rts { + rockchip,pins = + <2 19 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = + <3 12 RK_FUNC_2 &pcfg_pull_up>, + <3 13 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + uart2a { + uart2a_xfer: uart2a-xfer { + rockchip,pins = + <4 8 RK_FUNC_2 &pcfg_pull_up>, + <4 9 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + uart2b { + uart2b_xfer: uart2b-xfer { + rockchip,pins = + <4 16 RK_FUNC_2 &pcfg_pull_up>, + <4 17 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + uart2c { + uart2c_xfer: uart2c-xfer { + rockchip,pins = + <4 19 RK_FUNC_1 &pcfg_pull_up>, + <4 20 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uart3 { + uart3_xfer: uart3-xfer { + rockchip,pins = + <3 14 RK_FUNC_2 &pcfg_pull_up>, + <3 15 RK_FUNC_2 &pcfg_pull_none>; + }; + + uart3_cts: uart3-cts { + rockchip,pins = + <3 18 RK_FUNC_2 &pcfg_pull_none>; + }; + + uart3_rts: uart3-rts { + rockchip,pins = + <3 19 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + uart4 { + uart4_xfer: uart4-xfer { + rockchip,pins = + <1 7 RK_FUNC_1 &pcfg_pull_up>, + <1 8 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + uarthdcp { + uarthdcp_xfer: uarthdcp-xfer { + rockchip,pins = + <4 21 RK_FUNC_2 &pcfg_pull_up>, + <4 22 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + pwm0 { + pwm0_pin: pwm0-pin { + rockchip,pins = + <4 18 RK_FUNC_1 &pcfg_pull_none>; + }; + + vop0_pwm_pin: vop0-pwm-pin { + rockchip,pins = + <4 18 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + + pwm1 { + pwm1_pin: pwm1-pin { + rockchip,pins = + <4 22 RK_FUNC_1 &pcfg_pull_none>; + }; + + vop1_pwm_pin: vop1-pwm-pin { + rockchip,pins = + <4 18 RK_FUNC_3 &pcfg_pull_none>; + }; + }; + + pwm2 { + pwm2_pin: pwm2-pin { + rockchip,pins = + <1 19 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + pwm3a { + pwm3a_pin: pwm3a-pin { + rockchip,pins = + <0 6 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + pwm3b { + pwm3b_pin: pwm3b-pin { + rockchip,pins = + <1 14 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + }; +}; diff --git a/arch/arm/dts/sama5d2-pinfunc.h b/arch/arm/dts/sama5d2-pinfunc.h new file mode 100644 index 00000000000..b0c912feaa2 --- /dev/null +++ b/arch/arm/dts/sama5d2-pinfunc.h @@ -0,0 +1,880 @@ +#define PINMUX_PIN(no, func, ioset) \ +(((no) & 0xffff) | (((func) & 0xf) << 16) | (((ioset) & 0xff) << 20)) + +#define PIN_PA0 0 +#define PIN_PA0__GPIO PINMUX_PIN(PIN_PA0, 0, 0) +#define PIN_PA0__SDMMC0_CK PINMUX_PIN(PIN_PA0, 1, 1) +#define PIN_PA0__QSPI0_SCK PINMUX_PIN(PIN_PA0, 2, 1) +#define PIN_PA0__D0 PINMUX_PIN(PIN_PA0, 6, 2) +#define PIN_PA1 1 +#define PIN_PA1__GPIO PINMUX_PIN(PIN_PA1, 0, 0) +#define PIN_PA1__SDMMC0_CMD PINMUX_PIN(PIN_PA1, 1, 1) +#define PIN_PA1__QSPI0_CS PINMUX_PIN(PIN_PA1, 2, 1) +#define PIN_PA1__D1 PINMUX_PIN(PIN_PA1, 6, 2) +#define PIN_PA2 2 +#define PIN_PA2__GPIO PINMUX_PIN(PIN_PA2, 0, 0) +#define PIN_PA2__SDMMC0_DAT0 PINMUX_PIN(PIN_PA2, 1, 1) +#define PIN_PA2__QSPI0_IO0 PINMUX_PIN(PIN_PA2, 2, 1) +#define PIN_PA2__D2 PINMUX_PIN(PIN_PA2, 6, 2) +#define PIN_PA3 3 +#define PIN_PA3__GPIO PINMUX_PIN(PIN_PA3, 0, 0) +#define PIN_PA3__SDMMC0_DAT1 PINMUX_PIN(PIN_PA3, 1, 1) +#define PIN_PA3__QSPI0_IO1 PINMUX_PIN(PIN_PA3, 2, 1) +#define PIN_PA3__D3 PINMUX_PIN(PIN_PA3, 6, 2) +#define PIN_PA4 4 +#define PIN_PA4__GPIO PINMUX_PIN(PIN_PA4, 0, 0) +#define PIN_PA4__SDMMC0_DAT2 PINMUX_PIN(PIN_PA4, 1, 1) +#define PIN_PA4__QSPI0_IO2 PINMUX_PIN(PIN_PA4, 2, 1) +#define PIN_PA4__D4 PINMUX_PIN(PIN_PA4, 6, 2) +#define PIN_PA5 5 +#define PIN_PA5__GPIO PINMUX_PIN(PIN_PA5, 0, 0) +#define PIN_PA5__SDMMC0_DAT3 PINMUX_PIN(PIN_PA5, 1, 1) +#define PIN_PA5__QSPI0_IO3 PINMUX_PIN(PIN_PA5, 2, 1) +#define PIN_PA5__D5 PINMUX_PIN(PIN_PA5, 6, 2) +#define PIN_PA6 6 +#define PIN_PA6__GPIO PINMUX_PIN(PIN_PA6, 0, 0) +#define PIN_PA6__SDMMC0_DAT4 PINMUX_PIN(PIN_PA6, 1, 1) +#define PIN_PA6__QSPI1_SCK PINMUX_PIN(PIN_PA6, 2, 1) +#define PIN_PA6__TIOA5 PINMUX_PIN(PIN_PA6, 4, 1) +#define PIN_PA6__FLEXCOM2_IO0 PINMUX_PIN(PIN_PA6, 5, 1) +#define PIN_PA6__D6 PINMUX_PIN(PIN_PA6, 6, 2) +#define PIN_PA7 7 +#define PIN_PA7__GPIO PINMUX_PIN(PIN_PA7, 0, 0) +#define PIN_PA7__SDMMC0_DAT5 PINMUX_PIN(PIN_PA7, 1, 1) +#define PIN_PA7__QSPI1_IO0 PINMUX_PIN(PIN_PA7, 2, 1) +#define PIN_PA7__TIOB5 PINMUX_PIN(PIN_PA7, 4, 1) +#define PIN_PA7__FLEXCOM2_IO1 PINMUX_PIN(PIN_PA7, 5, 1) +#define PIN_PA7__D7 PINMUX_PIN(PIN_PA7, 6, 2) +#define PIN_PA8 8 +#define PIN_PA8__GPIO PINMUX_PIN(PIN_PA8, 0, 0) +#define PIN_PA8__SDMMC0_DAT6 PINMUX_PIN(PIN_PA8, 1, 1) +#define PIN_PA8__QSPI1_IO1 PINMUX_PIN(PIN_PA8, 2, 1) +#define PIN_PA8__TCLK5 PINMUX_PIN(PIN_PA8, 4, 1) +#define PIN_PA8__FLEXCOM2_IO2 PINMUX_PIN(PIN_PA8, 5, 1) +#define PIN_PA8__NWE_NANDWE PINMUX_PIN(PIN_PA8, 6, 2) +#define PIN_PA9 9 +#define PIN_PA9__GPIO PINMUX_PIN(PIN_PA9, 0, 0) +#define PIN_PA9__SDMMC0_DAT7 PINMUX_PIN(PIN_PA9, 1, 1) +#define PIN_PA9__QSPI1_IO2 PINMUX_PIN(PIN_PA9, 2, 1) +#define PIN_PA9__TIOA4 PINMUX_PIN(PIN_PA9, 4, 1) +#define PIN_PA9__FLEXCOM2_IO3 PINMUX_PIN(PIN_PA9, 5, 1) +#define PIN_PA9__NCS3 PINMUX_PIN(PIN_PA9, 6, 2) +#define PIN_PA10 10 +#define PIN_PA10__GPIO PINMUX_PIN(PIN_PA10, 0, 0) +#define PIN_PA10__SDMMC0_RSTN PINMUX_PIN(PIN_PA10, 1, 1) +#define PIN_PA10__QSPI1_IO3 PINMUX_PIN(PIN_PA10, 2, 1) +#define PIN_PA10__TIOB4 PINMUX_PIN(PIN_PA10, 4, 1) +#define PIN_PA10__FLEXCOM2_IO4 PINMUX_PIN(PIN_PA10, 5, 1) +#define PIN_PA10__A21_NANDALE PINMUX_PIN(PIN_PA10, 6, 2) +#define PIN_PA11 11 +#define PIN_PA11__GPIO PINMUX_PIN(PIN_PA11, 0, 0) +#define PIN_PA11__SDMMC0_VDDSEL PINMUX_PIN(PIN_PA11, 1, 1) +#define PIN_PA11__QSPI1_CS PINMUX_PIN(PIN_PA11, 2, 1) +#define PIN_PA11__TCLK4 PINMUX_PIN(PIN_PA11, 4, 1) +#define PIN_PA11__A22_NANDCLE PINMUX_PIN(PIN_PA11, 6, 2) +#define PIN_PA12 12 +#define PIN_PA12__GPIO PINMUX_PIN(PIN_PA12, 0, 0) +#define PIN_PA12__SDMMC0_WP PINMUX_PIN(PIN_PA12, 1, 1) +#define PIN_PA12__IRQ PINMUX_PIN(PIN_PA12, 2, 1) +#define PIN_PA12__NRD_NANDOE PINMUX_PIN(PIN_PA12, 6, 2) +#define PIN_PA13 13 +#define PIN_PA13__GPIO PINMUX_PIN(PIN_PA13, 0, 0) +#define PIN_PA13__SDMMC0_CD PINMUX_PIN(PIN_PA13, 1, 1) +#define PIN_PA13__FLEXCOM3_IO1 PINMUX_PIN(PIN_PA13, 5, 1) +#define PIN_PA13__D8 PINMUX_PIN(PIN_PA13, 6, 2) +#define PIN_PA14 14 +#define PIN_PA14__GPIO PINMUX_PIN(PIN_PA14, 0, 0) +#define PIN_PA14__SPI0_SPCK PINMUX_PIN(PIN_PA14, 1, 1) +#define PIN_PA14__TK1 PINMUX_PIN(PIN_PA14, 2, 1) +#define PIN_PA14__QSPI0_SCK PINMUX_PIN(PIN_PA14, 3, 2) +#define PIN_PA14__I2SC1_MCK PINMUX_PIN(PIN_PA14, 4, 2) +#define PIN_PA14__FLEXCOM3_IO2 PINMUX_PIN(PIN_PA14, 5, 1) +#define PIN_PA14__D9 PINMUX_PIN(PIN_PA14, 6, 2) +#define PIN_PA15 15 +#define PIN_PA15__GPIO PINMUX_PIN(PIN_PA15, 0, 0) +#define PIN_PA15__SPI0_MOSI PINMUX_PIN(PIN_PA15, 1, 1) +#define PIN_PA15__TF1 PINMUX_PIN(PIN_PA15, 2, 1) +#define PIN_PA15__QSPI0_CS PINMUX_PIN(PIN_PA15, 3, 2) +#define PIN_PA15__I2SC1_CK PINMUX_PIN(PIN_PA15, 4, 2) +#define PIN_PA15__FLEXCOM3_IO0 PINMUX_PIN(PIN_PA15, 5, 1) +#define PIN_PA15__D10 PINMUX_PIN(PIN_PA15, 6, 2) +#define PIN_PA16 16 +#define PIN_PA16__GPIO PINMUX_PIN(PIN_PA16, 0, 0) +#define PIN_PA16__SPI0_MISO PINMUX_PIN(PIN_PA16, 1, 1) +#define PIN_PA16__TD1 PINMUX_PIN(PIN_PA16, 2, 1) +#define PIN_PA16__QSPI0_IO0 PINMUX_PIN(PIN_PA16, 3, 2) +#define PIN_PA16__I2SC1_WS PINMUX_PIN(PIN_PA16, 4, 2) +#define PIN_PA16__FLEXCOM3_IO3 PINMUX_PIN(PIN_PA16, 5, 1) +#define PIN_PA16__D11 PINMUX_PIN(PIN_PA16, 6, 2) +#define PIN_PA17 17 +#define PIN_PA17__GPIO PINMUX_PIN(PIN_PA17, 0, 0) +#define PIN_PA17__SPI0_NPCS0 PINMUX_PIN(PIN_PA17, 1, 1) +#define PIN_PA17__RD1 PINMUX_PIN(PIN_PA17, 2, 1) +#define PIN_PA17__QSPI0_IO1 PINMUX_PIN(PIN_PA17, 3, 2) +#define PIN_PA17__I2SC1_DI0 PINMUX_PIN(PIN_PA17, 4, 2) +#define PIN_PA17__FLEXCOM3_IO4 PINMUX_PIN(PIN_PA17, 5, 1) +#define PIN_PA17__D12 PINMUX_PIN(PIN_PA17, 6, 2) +#define PIN_PA18 18 +#define PIN_PA18__GPIO PINMUX_PIN(PIN_PA18, 0, 0) +#define PIN_PA18__SPI0_NPCS1 PINMUX_PIN(PIN_PA18, 1, 1) +#define PIN_PA18__RK1 PINMUX_PIN(PIN_PA18, 2, 1) +#define PIN_PA18__QSPI0_IO2 PINMUX_PIN(PIN_PA18, 3, 2) +#define PIN_PA18__I2SC1_DO0 PINMUX_PIN(PIN_PA18, 4, 2) +#define PIN_PA18__SDMMC1_DAT0 PINMUX_PIN(PIN_PA18, 5, 1) +#define PIN_PA18__D13 PINMUX_PIN(PIN_PA18, 6, 2) +#define PIN_PA19 19 +#define PIN_PA19__GPIO PINMUX_PIN(PIN_PA19, 0, 0) +#define PIN_PA19__SPI0_NPCS2 PINMUX_PIN(PIN_PA19, 1, 1) +#define PIN_PA19__RF1 PINMUX_PIN(PIN_PA19, 2, 1) +#define PIN_PA19__QSPI0_IO3 PINMUX_PIN(PIN_PA19, 3, 2) +#define PIN_PA19__TIOA0 PINMUX_PIN(PIN_PA19, 4, 1) +#define PIN_PA19__SDMMC1_DAT1 PINMUX_PIN(PIN_PA19, 5, 1) +#define PIN_PA19__D14 PINMUX_PIN(PIN_PA19, 6, 2) +#define PIN_PA20 20 +#define PIN_PA20__GPIO PINMUX_PIN(PIN_PA20, 0, 0) +#define PIN_PA20__SPI0_NPCS3 PINMUX_PIN(PIN_PA20, 1, 1) +#define PIN_PA20__TIOB0 PINMUX_PIN(PIN_PA20, 4, 1) +#define PIN_PA20__SDMMC1_DAT2 PINMUX_PIN(PIN_PA20, 5, 1) +#define PIN_PA20__D15 PINMUX_PIN(PIN_PA20, 6, 2) +#define PIN_PA21 21 +#define PIN_PA21__GPIO PINMUX_PIN(PIN_PA21, 0, 0) +#define PIN_PA21__IRQ PINMUX_PIN(PIN_PA21, 1, 2) +#define PIN_PA21__PCK2 PINMUX_PIN(PIN_PA21, 2, 3) +#define PIN_PA21__TCLK0 PINMUX_PIN(PIN_PA21, 4, 1) +#define PIN_PA21__SDMMC1_DAT3 PINMUX_PIN(PIN_PA21, 5, 1) +#define PIN_PA21__NANDRDY PINMUX_PIN(PIN_PA21, 6, 2) +#define PIN_PA22 22 +#define PIN_PA22__GPIO PINMUX_PIN(PIN_PA22, 0, 0) +#define PIN_PA22__FLEXCOM1_IO2 PINMUX_PIN(PIN_PA22, 1, 1) +#define PIN_PA22__D0 PINMUX_PIN(PIN_PA22, 2, 1) +#define PIN_PA22__TCK PINMUX_PIN(PIN_PA22, 3, 4) +#define PIN_PA22__SPI1_SPCK PINMUX_PIN(PIN_PA22, 4, 2) +#define PIN_PA22__SDMMC1_CK PINMUX_PIN(PIN_PA22, 5, 1) +#define PIN_PA22__QSPI0_SCK PINMUX_PIN(PIN_PA22, 6, 3) +#define PIN_PA23 23 +#define PIN_PA23__GPIO PINMUX_PIN(PIN_PA23, 0, 0) +#define PIN_PA23__FLEXCOM1_IO1 PINMUX_PIN(PIN_PA23, 1, 1) +#define PIN_PA23__D1 PINMUX_PIN(PIN_PA23, 2, 1) +#define PIN_PA23__TDI PINMUX_PIN(PIN_PA23, 3, 4) +#define PIN_PA23__SPI1_MOSI PINMUX_PIN(PIN_PA23, 4, 2) +#define PIN_PA23__QSPI0_CS PINMUX_PIN(PIN_PA23, 6, 3) +#define PIN_PA24 24 +#define PIN_PA24__GPIO PINMUX_PIN(PIN_PA24, 0, 0) +#define PIN_PA24__FLEXCOM1_IO0 PINMUX_PIN(PIN_PA24, 1, 1) +#define PIN_PA24__D2 PINMUX_PIN(PIN_PA24, 2, 1) +#define PIN_PA24__TDO PINMUX_PIN(PIN_PA24, 3, 4) +#define PIN_PA24__SPI1_MISO PINMUX_PIN(PIN_PA24, 4, 2) +#define PIN_PA24__QSPI0_IO0 PINMUX_PIN(PIN_PA24, 6, 3) +#define PIN_PA25 25 +#define PIN_PA25__GPIO PINMUX_PIN(PIN_PA25, 0, 0) +#define PIN_PA25__FLEXCOM1_IO3 PINMUX_PIN(PIN_PA25, 1, 1) +#define PIN_PA25__D3 PINMUX_PIN(PIN_PA25, 2, 1) +#define PIN_PA25__TMS PINMUX_PIN(PIN_PA25, 3, 4) +#define PIN_PA25__SPI1_NPCS0 PINMUX_PIN(PIN_PA25, 4, 2) +#define PIN_PA25__QSPI0_IO1 PINMUX_PIN(PIN_PA25, 6, 3) +#define PIN_PA26 26 +#define PIN_PA26__GPIO PINMUX_PIN(PIN_PA26, 0, 0) +#define PIN_PA26__FLEXCOM1_IO4 PINMUX_PIN(PIN_PA26, 1, 1) +#define PIN_PA26__D4 PINMUX_PIN(PIN_PA26, 2, 1) +#define PIN_PA26__NTRST PINMUX_PIN(PIN_PA26, 3, 4) +#define PIN_PA26__SPI1_NPCS1 PINMUX_PIN(PIN_PA26, 4, 2) +#define PIN_PA26__QSPI0_IO2 PINMUX_PIN(PIN_PA26, 6, 3) +#define PIN_PA27 27 +#define PIN_PA27__GPIO PINMUX_PIN(PIN_PA27, 0, 0) +#define PIN_PA27__TIOA1 PINMUX_PIN(PIN_PA27, 1, 2) +#define PIN_PA27__D5 PINMUX_PIN(PIN_PA27, 2, 1) +#define PIN_PA27__SPI0_NPCS2 PINMUX_PIN(PIN_PA27, 3, 2) +#define PIN_PA27__SPI1_NPCS2 PINMUX_PIN(PIN_PA27, 4, 2) +#define PIN_PA27__SDMMC1_RSTN PINMUX_PIN(PIN_PA27, 5, 1) +#define PIN_PA27__QSPI0_IO3 PINMUX_PIN(PIN_PA27, 6, 3) +#define PIN_PA28 28 +#define PIN_PA28__GPIO PINMUX_PIN(PIN_PA28, 0, 0) +#define PIN_PA28__TIOB1 PINMUX_PIN(PIN_PA28, 1, 2) +#define PIN_PA28__D6 PINMUX_PIN(PIN_PA28, 2, 1) +#define PIN_PA28__SPI0_NPCS3 PINMUX_PIN(PIN_PA28, 3, 2) +#define PIN_PA28__SPI1_NPCS3 PINMUX_PIN(PIN_PA28, 4, 2) +#define PIN_PA28__SDMMC1_CMD PINMUX_PIN(PIN_PA28, 5, 1) +#define PIN_PA28__CLASSD_L0 PINMUX_PIN(PIN_PA28, 6, 1) +#define PIN_PA29 29 +#define PIN_PA29__GPIO PINMUX_PIN(PIN_PA29, 0, 0) +#define PIN_PA29__TCLK1 PINMUX_PIN(PIN_PA29, 1, 2) +#define PIN_PA29__D7 PINMUX_PIN(PIN_PA29, 2, 1) +#define PIN_PA29__SPI0_NPCS1 PINMUX_PIN(PIN_PA29, 3, 2) +#define PIN_PA29__SDMMC1_WP PINMUX_PIN(PIN_PA29, 5, 1) +#define PIN_PA29__CLASSD_L1 PINMUX_PIN(PIN_PA29, 6, 1) +#define PIN_PA30 30 +#define PIN_PA30__GPIO PINMUX_PIN(PIN_PA30, 0, 0) +#define PIN_PA30__NWE_NANDWE PINMUX_PIN(PIN_PA30, 2, 1) +#define PIN_PA30__SPI0_NPCS0 PINMUX_PIN(PIN_PA30, 3, 2) +#define PIN_PA30__PWMH0 PINMUX_PIN(PIN_PA30, 4, 1) +#define PIN_PA30__SDMMC1_CD PINMUX_PIN(PIN_PA30, 5, 1) +#define PIN_PA30__CLASSD_L2 PINMUX_PIN(PIN_PA30, 6, 1) +#define PIN_PA31 31 +#define PIN_PA31__GPIO PINMUX_PIN(PIN_PA31, 0, 0) +#define PIN_PA31__NCS3 PINMUX_PIN(PIN_PA31, 2, 1) +#define PIN_PA31__SPI0_MISO PINMUX_PIN(PIN_PA31, 3, 2) +#define PIN_PA31__PWML0 PINMUX_PIN(PIN_PA31, 4, 1) +#define PIN_PA31__CLASSD_L3 PINMUX_PIN(PIN_PA31, 6, 1) +#define PIN_PB0 32 +#define PIN_PB0__GPIO PINMUX_PIN(PIN_PB0, 0, 0) +#define PIN_PB0__A21_NANDALE PINMUX_PIN(PIN_PB0, 2, 1) +#define PIN_PB0__SPI0_MOSI PINMUX_PIN(PIN_PB0, 3, 2) +#define PIN_PB0__PWMH1 PINMUX_PIN(PIN_PB0, 4, 1) +#define PIN_PB1 33 +#define PIN_PB1__GPIO PINMUX_PIN(PIN_PB1, 0, 0) +#define PIN_PB1__A22_NANDCLE PINMUX_PIN(PIN_PB1, 2, 1) +#define PIN_PB1__SPI0_SPCK PINMUX_PIN(PIN_PB1, 3, 2) +#define PIN_PB1__PWML1 PINMUX_PIN(PIN_PB1, 4, 1) +#define PIN_PB1__CLASSD_R0 PINMUX_PIN(PIN_PB1, 6, 1) +#define PIN_PB2 34 +#define PIN_PB2__GPIO PINMUX_PIN(PIN_PB2, 0, 0) +#define PIN_PB2__NRD_NANDOE PINMUX_PIN(PIN_PB2, 2, 1) +#define PIN_PB2__PWMFI0 PINMUX_PIN(PIN_PB2, 4, 1) +#define PIN_PB2__CLASSD_R1 PINMUX_PIN(PIN_PB2, 6, 1) +#define PIN_PB3 35 +#define PIN_PB3__GPIO PINMUX_PIN(PIN_PB3, 0, 0) +#define PIN_PB3__URXD4 PINMUX_PIN(PIN_PB3, 1, 1) +#define PIN_PB3__D8 PINMUX_PIN(PIN_PB3, 2, 1) +#define PIN_PB3__IRQ PINMUX_PIN(PIN_PB3, 3, 3) +#define PIN_PB3__PWMEXTRG0 PINMUX_PIN(PIN_PB3, 4, 1) +#define PIN_PB3__CLASSD_R2 PINMUX_PIN(PIN_PB3, 6, 1) +#define PIN_PB4 36 +#define PIN_PB4__GPIO PINMUX_PIN(PIN_PB4, 0, 0) +#define PIN_PB4__UTXD4 PINMUX_PIN(PIN_PB4, 1, 1) +#define PIN_PB4__D9 PINMUX_PIN(PIN_PB4, 2, 1) +#define PIN_PB4__FIQ PINMUX_PIN(PIN_PB4, 3, 4) +#define PIN_PB4__CLASSD_R3 PINMUX_PIN(PIN_PB4, 6, 1) +#define PIN_PB5 37 +#define PIN_PB5__GPIO PINMUX_PIN(PIN_PB5, 0, 0) +#define PIN_PB5__TCLK2 PINMUX_PIN(PIN_PB5, 1, 1) +#define PIN_PB5__D10 PINMUX_PIN(PIN_PB5, 2, 1) +#define PIN_PB5__PWMH2 PINMUX_PIN(PIN_PB5, 3, 1) +#define PIN_PB5__QSPI1_SCK PINMUX_PIN(PIN_PB5, 4, 2) +#define PIN_PB5__GTSUCOMP PINMUX_PIN(PIN_PB5, 6, 3) +#define PIN_PB6 38 +#define PIN_PB6__GPIO PINMUX_PIN(PIN_PB6, 0, 0) +#define PIN_PB6__TIOA2 PINMUX_PIN(PIN_PB6, 1, 1) +#define PIN_PB6__D11 PINMUX_PIN(PIN_PB6, 2, 1) +#define PIN_PB6__PWML2 PINMUX_PIN(PIN_PB6, 3, 1) +#define PIN_PB6__QSPI1_CS PINMUX_PIN(PIN_PB6, 4, 2) +#define PIN_PB6__GTXER PINMUX_PIN(PIN_PB6, 6, 3) +#define PIN_PB7 39 +#define PIN_PB7__GPIO PINMUX_PIN(PIN_PB7, 0, 0) +#define PIN_PB7__TIOB2 PINMUX_PIN(PIN_PB7, 1, 1) +#define PIN_PB7__D12 PINMUX_PIN(PIN_PB7, 2, 1) +#define PIN_PB7__PWMH3 PINMUX_PIN(PIN_PB7, 3, 1) +#define PIN_PB7__QSPI1_IO0 PINMUX_PIN(PIN_PB7, 4, 2) +#define PIN_PB7__GRXCK PINMUX_PIN(PIN_PB7, 6, 3) +#define PIN_PB8 40 +#define PIN_PB8__GPIO PINMUX_PIN(PIN_PB8, 0, 0) +#define PIN_PB8__TCLK3 PINMUX_PIN(PIN_PB8, 1, 1) +#define PIN_PB8__D13 PINMUX_PIN(PIN_PB8, 2, 1) +#define PIN_PB8__PWML3 PINMUX_PIN(PIN_PB8, 3, 1) +#define PIN_PB8__QSPI1_IO1 PINMUX_PIN(PIN_PB8, 4, 2) +#define PIN_PB8__GCRS PINMUX_PIN(PIN_PB8, 6, 3) +#define PIN_PB9 41 +#define PIN_PB9__GPIO PINMUX_PIN(PIN_PB9, 0, 0) +#define PIN_PB9__TIOA3 PINMUX_PIN(PIN_PB9, 1, 1) +#define PIN_PB9__D14 PINMUX_PIN(PIN_PB9, 2, 1) +#define PIN_PB9__PWMFI1 PINMUX_PIN(PIN_PB9, 3, 1) +#define PIN_PB9__QSPI1_IO2 PINMUX_PIN(PIN_PB9, 4, 2) +#define PIN_PB9__GCOL PINMUX_PIN(PIN_PB9, 6, 3) +#define PIN_PB10 42 +#define PIN_PB10__GPIO PINMUX_PIN(PIN_PB10, 0, 0) +#define PIN_PB10__TIOB3 PINMUX_PIN(PIN_PB10, 1, 1) +#define PIN_PB10__D15 PINMUX_PIN(PIN_PB10, 2, 1) +#define PIN_PB10__PWMEXTRG1 PINMUX_PIN(PIN_PB10, 3, 1) +#define PIN_PB10__QSPI1_IO3 PINMUX_PIN(PIN_PB10, 4, 2) +#define PIN_PB10__GRX2 PINMUX_PIN(PIN_PB10, 6, 3) +#define PIN_PB11 43 +#define PIN_PB11__GPIO PINMUX_PIN(PIN_PB11, 0, 0) +#define PIN_PB11__LCDDAT0 PINMUX_PIN(PIN_PB11, 1, 1) +#define PIN_PB11__A0_NBS0 PINMUX_PIN(PIN_PB11, 2, 1) +#define PIN_PB11__URXD3 PINMUX_PIN(PIN_PB11, 3, 3) +#define PIN_PB11__PDMIC_DAT PINMUX_PIN(PIN_PB11, 4, 2) +#define PIN_PB11__GRX3 PINMUX_PIN(PIN_PB11, 6, 3) +#define PIN_PB12 44 +#define PIN_PB12__GPIO PINMUX_PIN(PIN_PB12, 0, 0) +#define PIN_PB12__LCDDAT1 PINMUX_PIN(PIN_PB12, 1, 1) +#define PIN_PB12__A1 PINMUX_PIN(PIN_PB12, 2, 1) +#define PIN_PB12__UTXD3 PINMUX_PIN(PIN_PB12, 3, 3) +#define PIN_PB12__PDMIC_CLK PINMUX_PIN(PIN_PB12, 4, 2) +#define PIN_PB12__GTX2 PINMUX_PIN(PIN_PB12, 6, 3) +#define PIN_PB13 45 +#define PIN_PB13__GPIO PINMUX_PIN(PIN_PB13, 0, 0) +#define PIN_PB13__LCDDAT2 PINMUX_PIN(PIN_PB13, 1, 1) +#define PIN_PB13__A2 PINMUX_PIN(PIN_PB13, 2, 1) +#define PIN_PB13__PCK1 PINMUX_PIN(PIN_PB13, 3, 3) +#define PIN_PB13__GTX3 PINMUX_PIN(PIN_PB13, 6, 3) +#define PIN_PB14 46 +#define PIN_PB14__GPIO PINMUX_PIN(PIN_PB14, 0, 0) +#define PIN_PB14__LCDDAT3 PINMUX_PIN(PIN_PB14, 1, 1) +#define PIN_PB14__A3 PINMUX_PIN(PIN_PB14, 2, 1) +#define PIN_PB14__TK1 PINMUX_PIN(PIN_PB14, 3, 2) +#define PIN_PB14__I2SC1_MCK PINMUX_PIN(PIN_PB14, 4, 1) +#define PIN_PB14__QSPI1_SCK PINMUX_PIN(PIN_PB14, 5, 3) +#define PIN_PB14__GTXCK PINMUX_PIN(PIN_PB14, 6, 3) +#define PIN_PB15 47 +#define PIN_PB15__GPIO PINMUX_PIN(PIN_PB15, 0, 0) +#define PIN_PB15__LCDDAT4 PINMUX_PIN(PIN_PB15, 1, 1) +#define PIN_PB15__A4 PINMUX_PIN(PIN_PB15, 2, 1) +#define PIN_PB15__TF1 PINMUX_PIN(PIN_PB15, 3, 2) +#define PIN_PB15__I2SC1_CK PINMUX_PIN(PIN_PB15, 4, 1) +#define PIN_PB15__QSPI1_CS PINMUX_PIN(PIN_PB15, 5, 3) +#define PIN_PB15__GTXEN PINMUX_PIN(PIN_PB15, 6, 3) +#define PIN_PB16 48 +#define PIN_PB16__GPIO PINMUX_PIN(PIN_PB16, 0, 0) +#define PIN_PB16__LCDDAT5 PINMUX_PIN(PIN_PB16, 1, 1) +#define PIN_PB16__A5 PINMUX_PIN(PIN_PB16, 2, 1) +#define PIN_PB16__TD1 PINMUX_PIN(PIN_PB16, 3, 2) +#define PIN_PB16__I2SC1_WS PINMUX_PIN(PIN_PB16, 4, 1) +#define PIN_PB16__QSPI1_IO0 PINMUX_PIN(PIN_PB16, 5, 3) +#define PIN_PB16__GRXDV PINMUX_PIN(PIN_PB16, 6, 3) +#define PIN_PB17 49 +#define PIN_PB17__GPIO PINMUX_PIN(PIN_PB17, 0, 0) +#define PIN_PB17__LCDDAT6 PINMUX_PIN(PIN_PB17, 1, 1) +#define PIN_PB17__A6 PINMUX_PIN(PIN_PB17, 2, 1) +#define PIN_PB17__RD1 PINMUX_PIN(PIN_PB17, 3, 2) +#define PIN_PB17__I2SC1_DI0 PINMUX_PIN(PIN_PB17, 4, 1) +#define PIN_PB17__QSPI1_IO1 PINMUX_PIN(PIN_PB17, 5, 3) +#define PIN_PB17__GRXER PINMUX_PIN(PIN_PB17, 6, 3) +#define PIN_PB18 50 +#define PIN_PB18__GPIO PINMUX_PIN(PIN_PB18, 0, 0) +#define PIN_PB18__LCDDAT7 PINMUX_PIN(PIN_PB18, 1, 1) +#define PIN_PB18__A7 PINMUX_PIN(PIN_PB18, 2, 1) +#define PIN_PB18__RK1 PINMUX_PIN(PIN_PB18, 3, 2) +#define PIN_PB18__I2SC1_DO0 PINMUX_PIN(PIN_PB18, 4, 1) +#define PIN_PB18__QSPI1_IO2 PINMUX_PIN(PIN_PB18, 5, 3) +#define PIN_PB18__GRX0 PINMUX_PIN(PIN_PB18, 6, 3) +#define PIN_PB19 51 +#define PIN_PB19__GPIO PINMUX_PIN(PIN_PB19, 0, 0) +#define PIN_PB19__LCDDAT8 PINMUX_PIN(PIN_PB19, 1, 1) +#define PIN_PB19__A8 PINMUX_PIN(PIN_PB19, 2, 1) +#define PIN_PB19__RF1 PINMUX_PIN(PIN_PB19, 3, 2) +#define PIN_PB19__TIOA3 PINMUX_PIN(PIN_PB19, 4, 2) +#define PIN_PB19__QSPI1_IO3 PINMUX_PIN(PIN_PB19, 5, 3) +#define PIN_PB19__GRX1 PINMUX_PIN(PIN_PB19, 6, 3) +#define PIN_PB20 52 +#define PIN_PB20__GPIO PINMUX_PIN(PIN_PB20, 0, 0) +#define PIN_PB20__LCDDAT9 PINMUX_PIN(PIN_PB20, 1, 1) +#define PIN_PB20__A9 PINMUX_PIN(PIN_PB20, 2, 1) +#define PIN_PB20__TK0 PINMUX_PIN(PIN_PB20, 3, 1) +#define PIN_PB20__TIOB3 PINMUX_PIN(PIN_PB20, 4, 2) +#define PIN_PB20__PCK1 PINMUX_PIN(PIN_PB20, 5, 4) +#define PIN_PB20__GTX0 PINMUX_PIN(PIN_PB20, 6, 3) +#define PIN_PB21 53 +#define PIN_PB21__GPIO PINMUX_PIN(PIN_PB21, 0, 0) +#define PIN_PB21__LCDDAT10 PINMUX_PIN(PIN_PB21, 1, 1) +#define PIN_PB21__A10 PINMUX_PIN(PIN_PB21, 2, 1) +#define PIN_PB21__TF0 PINMUX_PIN(PIN_PB21, 3, 1) +#define PIN_PB21__TCLK3 PINMUX_PIN(PIN_PB21, 4, 2) +#define PIN_PB21__FLEXCOM3_IO2 PINMUX_PIN(PIN_PB21, 5, 3) +#define PIN_PB21__GTX1 PINMUX_PIN(PIN_PB21, 6, 3) +#define PIN_PB22 54 +#define PIN_PB22__GPIO PINMUX_PIN(PIN_PB22, 0, 0) +#define PIN_PB22__LCDDAT11 PINMUX_PIN(PIN_PB22, 1, 1) +#define PIN_PB22__A11 PINMUX_PIN(PIN_PB22, 2, 1) +#define PIN_PB22__TDO PINMUX_PIN(PIN_PB22, 3, 1) +#define PIN_PB22__TIOA2 PINMUX_PIN(PIN_PB22, 4, 2) +#define PIN_PB22__FLEXCOM3_IO1 PINMUX_PIN(PIN_PB22, 5, 3) +#define PIN_PB22__GMDC PINMUX_PIN(PIN_PB22, 6, 3) +#define PIN_PB23 55 +#define PIN_PB23__GPIO PINMUX_PIN(PIN_PB23, 0, 0) +#define PIN_PB23__LCDDAT12 PINMUX_PIN(PIN_PB23, 1, 1) +#define PIN_PB23__A12 PINMUX_PIN(PIN_PB23, 2, 1) +#define PIN_PB23__RD0 PINMUX_PIN(PIN_PB23, 3, 1) +#define PIN_PB23__TIOB2 PINMUX_PIN(PIN_PB23, 4, 2) +#define PIN_PB23__FLEXCOM3_IO0 PINMUX_PIN(PIN_PB23, 5, 3) +#define PIN_PB23__GMDIO PINMUX_PIN(PIN_PB23, 6, 3) +#define PIN_PB24 56 +#define PIN_PB24__GPIO PINMUX_PIN(PIN_PB24, 0, 0) +#define PIN_PB24__LCDDAT13 PINMUX_PIN(PIN_PB24, 1, 1) +#define PIN_PB24__A13 PINMUX_PIN(PIN_PB24, 2, 1) +#define PIN_PB24__RK0 PINMUX_PIN(PIN_PB24, 3, 1) +#define PIN_PB24__TCLK2 PINMUX_PIN(PIN_PB24, 4, 2) +#define PIN_PB24__FLEXCOM3_IO3 PINMUX_PIN(PIN_PB24, 5, 3) +#define PIN_PB24__ISC_D10 PINMUX_PIN(PIN_PB24, 6, 3) +#define PIN_PB25 57 +#define PIN_PB25__GPIO PINMUX_PIN(PIN_PB25, 0, 0) +#define PIN_PB25__LCDDAT14 PINMUX_PIN(PIN_PB25, 1, 1) +#define PIN_PB25__A14 PINMUX_PIN(PIN_PB25, 2, 1) +#define PIN_PB25__RF0 PINMUX_PIN(PIN_PB25, 3, 1) +#define PIN_PB25__FLEXCOM3_IO4 PINMUX_PIN(PIN_PB25, 5, 3) +#define PIN_PB25__ISC_D11 PINMUX_PIN(PIN_PB25, 6, 3) +#define PIN_PB26 58 +#define PIN_PB26__GPIO PINMUX_PIN(PIN_PB26, 0, 0) +#define PIN_PB26__LCDDAT15 PINMUX_PIN(PIN_PB26, 1, 1) +#define PIN_PB26__A15 PINMUX_PIN(PIN_PB26, 2, 1) +#define PIN_PB26__URXD0 PINMUX_PIN(PIN_PB26, 3, 1) +#define PIN_PB26__PDMIC_DAT PINMUX_PIN(PIN_PB26, 4, 1) +#define PIN_PB26__ISC_D0 PINMUX_PIN(PIN_PB26, 6, 3) +#define PIN_PB27 59 +#define PIN_PB27__GPIO PINMUX_PIN(PIN_PB27, 0, 0) +#define PIN_PB27__LCDDAT16 PINMUX_PIN(PIN_PB27, 1, 1) +#define PIN_PB27__A16 PINMUX_PIN(PIN_PB27, 2, 1) +#define PIN_PB27__UTXD0 PINMUX_PIN(PIN_PB27, 3, 1) +#define PIN_PB27__PDMIC_CLK PINMUX_PIN(PIN_PB27, 4, 1) +#define PIN_PB27__ISC_D1 PINMUX_PIN(PIN_PB27, 6, 3) +#define PIN_PB28 60 +#define PIN_PB28__GPIO PINMUX_PIN(PIN_PB28, 0, 0) +#define PIN_PB28__LCDDAT17 PINMUX_PIN(PIN_PB28, 1, 1) +#define PIN_PB28__A17 PINMUX_PIN(PIN_PB28, 2, 1) +#define PIN_PB28__FLEXCOM0_IO0 PINMUX_PIN(PIN_PB28, 3, 1) +#define PIN_PB28__TIOA5 PINMUX_PIN(PIN_PB28, 4, 2) +#define PIN_PB28__ISC_D2 PINMUX_PIN(PIN_PB28, 6, 3) +#define PIN_PB29 61 +#define PIN_PB29__GPIO PINMUX_PIN(PIN_PB29, 0, 0) +#define PIN_PB29__LCDDAT18 PINMUX_PIN(PIN_PB29, 1, 1) +#define PIN_PB29__A18 PINMUX_PIN(PIN_PB29, 2, 1) +#define PIN_PB29__FLEXCOM0_IO1 PINMUX_PIN(PIN_PB29, 3, 1) +#define PIN_PB29__TIOB5 PINMUX_PIN(PIN_PB29, 4, 2) +#define PIN_PB29__ISC_D3 PINMUX_PIN(PIN_PB29, 7, 3) +#define PIN_PB30 62 +#define PIN_PB30__GPIO PINMUX_PIN(PIN_PB30, 0, 0) +#define PIN_PB30__LCDDAT19 PINMUX_PIN(PIN_PB30, 1, 1) +#define PIN_PB30__A19 PINMUX_PIN(PIN_PB30, 2, 1) +#define PIN_PB30__FLEXCOM0_IO2 PINMUX_PIN(PIN_PB30, 3, 1) +#define PIN_PB30__TCLK5 PINMUX_PIN(PIN_PB30, 4, 2) +#define PIN_PB30__ISC_D4 PINMUX_PIN(PIN_PB30, 6, 3) +#define PIN_PB31 63 +#define PIN_PB31__GPIO PINMUX_PIN(PIN_PB31, 0, 0) +#define PIN_PB31__LCDDAT20 PINMUX_PIN(PIN_PB31, 1, 1) +#define PIN_PB31__A20 PINMUX_PIN(PIN_PB31, 2, 1) +#define PIN_PB31__FLEXCOM0_IO3 PINMUX_PIN(PIN_PB31, 3, 1) +#define PIN_PB31__TWD0 PINMUX_PIN(PIN_PB31, 4, 1) +#define PIN_PB31__ISC_D5 PINMUX_PIN(PIN_PB31, 6, 3) +#define PIN_PC0 64 +#define PIN_PC0__GPIO PINMUX_PIN(PIN_PC0, 0, 0) +#define PIN_PC0__LCDDAT21 PINMUX_PIN(PIN_PC0, 1, 1) +#define PIN_PC0__A23 PINMUX_PIN(PIN_PC0, 2, 1) +#define PIN_PC0__FLEXCOM0_IO4 PINMUX_PIN(PIN_PC0, 3, 1) +#define PIN_PC0__TWCK0 PINMUX_PIN(PIN_PC0, 4, 1) +#define PIN_PC0__ISC_D6 PINMUX_PIN(PIN_PC0, 6, 3) +#define PIN_PC1 65 +#define PIN_PC1__GPIO PINMUX_PIN(PIN_PC1, 0, 0) +#define PIN_PC1__LCDDAT22 PINMUX_PIN(PIN_PC1, 1, 1) +#define PIN_PC1__A24 PINMUX_PIN(PIN_PC1, 2, 1) +#define PIN_PC1__CANTX0 PINMUX_PIN(PIN_PC1, 3, 1) +#define PIN_PC1__SPI1_SPCK PINMUX_PIN(PIN_PC1, 4, 1) +#define PIN_PC1__I2SC0_CK PINMUX_PIN(PIN_PC1, 5, 1) +#define PIN_PC1__ISC_D7 PINMUX_PIN(PIN_PC1, 6, 3) +#define PIN_PC2 66 +#define PIN_PC2__GPIO PINMUX_PIN(PIN_PC2, 0, 0) +#define PIN_PC2__LCDDAT23 PINMUX_PIN(PIN_PC2, 1, 1) +#define PIN_PC2__A25 PINMUX_PIN(PIN_PC2, 2, 1) +#define PIN_PC2__CANRX0 PINMUX_PIN(PIN_PC2, 3, 1) +#define PIN_PC2__SPI1_MOSI PINMUX_PIN(PIN_PC2, 4, 1) +#define PIN_PC2__I2SC0_MCK PINMUX_PIN(PIN_PC2, 5, 1) +#define PIN_PC2__ISC_D8 PINMUX_PIN(PIN_PC2, 6, 3) +#define PIN_PC3 67 +#define PIN_PC3__GPIO PINMUX_PIN(PIN_PC3, 0, 0) +#define PIN_PC3__LCDPWM PINMUX_PIN(PIN_PC3, 1, 1) +#define PIN_PC3__NWAIT PINMUX_PIN(PIN_PC3, 2, 1) +#define PIN_PC3__TIOA1 PINMUX_PIN(PIN_PC3, 3, 1) +#define PIN_PC3__SPI1_MISO PINMUX_PIN(PIN_PC3, 4, 1) +#define PIN_PC3__I2SC0_WS PINMUX_PIN(PIN_PC3, 5, 1) +#define PIN_PC3__ISC_D9 PINMUX_PIN(PIN_PC3, 6, 3) +#define PIN_PC4 68 +#define PIN_PC4__GPIO PINMUX_PIN(PIN_PC4, 0, 0) +#define PIN_PC4__LCDDISP PINMUX_PIN(PIN_PC4, 1, 1) +#define PIN_PC4__NWR1_NBS1 PINMUX_PIN(PIN_PC4, 2, 1) +#define PIN_PC4__TIOB1 PINMUX_PIN(PIN_PC4, 3, 1) +#define PIN_PC4__SPI1_NPCS0 PINMUX_PIN(PIN_PC4, 4, 1) +#define PIN_PC4__I2SC0_DI0 PINMUX_PIN(PIN_PC4, 5, 1) +#define PIN_PC4__ISC_PCK PINMUX_PIN(PIN_PC4, 6, 3) +#define PIN_PC5 69 +#define PIN_PC5__GPIO PINMUX_PIN(PIN_PC5, 0, 0) +#define PIN_PC5__LCDVSYNC PINMUX_PIN(PIN_PC5, 1, 1) +#define PIN_PC5__NCS0 PINMUX_PIN(PIN_PC5, 2, 1) +#define PIN_PC5__TCLK1 PINMUX_PIN(PIN_PC5, 3, 1) +#define PIN_PC5__SPI1_NPCS1 PINMUX_PIN(PIN_PC5, 4, 1) +#define PIN_PC5__I2SC0_DO0 PINMUX_PIN(PIN_PC5, 5, 1) +#define PIN_PC5__ISC_VSYNC PINMUX_PIN(PIN_PC5, 6, 3) +#define PIN_PC6 70 +#define PIN_PC6__GPIO PINMUX_PIN(PIN_PC6, 0, 0) +#define PIN_PC6__LCDHSYNC PINMUX_PIN(PIN_PC6, 1, 1) +#define PIN_PC6__NCS1 PINMUX_PIN(PIN_PC6, 2, 1) +#define PIN_PC6__TWD1 PINMUX_PIN(PIN_PC6, 3, 1) +#define PIN_PC6__SPI1_NPCS2 PINMUX_PIN(PIN_PC6, 4, 1) +#define PIN_PC6__ISC_HSYNC PINMUX_PIN(PIN_PC6, 6, 3) +#define PIN_PC7 71 +#define PIN_PC7__GPIO PINMUX_PIN(PIN_PC7, 0, 0) +#define PIN_PC7__LCDPCK PINMUX_PIN(PIN_PC7, 1, 1) +#define PIN_PC7__NCS2 PINMUX_PIN(PIN_PC7, 2, 1) +#define PIN_PC7__TWCK1 PINMUX_PIN(PIN_PC7, 3, 1) +#define PIN_PC7__SPI1_NPCS3 PINMUX_PIN(PIN_PC7, 4, 1) +#define PIN_PC7__URXD1 PINMUX_PIN(PIN_PC7, 5, 2) +#define PIN_PC7__ISC_MCK PINMUX_PIN(PIN_PC7, 6, 3) +#define PIN_PC8 72 +#define PIN_PC8__GPIO PINMUX_PIN(PIN_PC8, 0, 0) +#define PIN_PC8__LCDDEN PINMUX_PIN(PIN_PC8, 1, 1) +#define PIN_PC8__NANDRDY PINMUX_PIN(PIN_PC8, 2, 1) +#define PIN_PC8__FIQ PINMUX_PIN(PIN_PC8, 3, 1) +#define PIN_PC8__PCK0 PINMUX_PIN(PIN_PC8, 4, 3) +#define PIN_PC8__UTXD1 PINMUX_PIN(PIN_PC8, 5, 2) +#define PIN_PC8__ISC_FIELD PINMUX_PIN(PIN_PC8, 6, 3) +#define PIN_PC9 73 +#define PIN_PC9__GPIO PINMUX_PIN(PIN_PC9, 0, 0) +#define PIN_PC9__FIQ PINMUX_PIN(PIN_PC9, 1, 3) +#define PIN_PC9__GTSUCOMP PINMUX_PIN(PIN_PC9, 2, 1) +#define PIN_PC9__ISC_D0 PINMUX_PIN(PIN_PC9, 2, 1) +#define PIN_PC9__TIOA4 PINMUX_PIN(PIN_PC9, 4, 2) +#define PIN_PC10 74 +#define PIN_PC10__GPIO PINMUX_PIN(PIN_PC10, 0, 0) +#define PIN_PC10__LCDDAT2 PINMUX_PIN(PIN_PC10, 1, 2) +#define PIN_PC10__GTXCK PINMUX_PIN(PIN_PC10, 2, 1) +#define PIN_PC10__ISC_D1 PINMUX_PIN(PIN_PC10, 3, 1) +#define PIN_PC10__TIOB4 PINMUX_PIN(PIN_PC10, 4, 2) +#define PIN_PC10__CANTX0 PINMUX_PIN(PIN_PC10, 5, 2) +#define PIN_PC11 75 +#define PIN_PC11__GPIO PINMUX_PIN(PIN_PC11, 0, 0) +#define PIN_PC11__LCDDAT3 PINMUX_PIN(PIN_PC11, 1, 2) +#define PIN_PC11__GTXEN PINMUX_PIN(PIN_PC11, 2, 1) +#define PIN_PC11__ISC_D2 PINMUX_PIN(PIN_PC11, 3, 1) +#define PIN_PC11__TCLK4 PINMUX_PIN(PIN_PC11, 4, 2) +#define PIN_PC11__CANRX0 PINMUX_PIN(PIN_PC11, 5, 2) +#define PIN_PC11__A0_NBS0 PINMUX_PIN(PIN_PC11, 6, 2) +#define PIN_PC12 76 +#define PIN_PC12__GPIO PINMUX_PIN(PIN_PC12, 0, 0) +#define PIN_PC12__LCDDAT4 PINMUX_PIN(PIN_PC12, 1, 2) +#define PIN_PC12__GRXDV PINMUX_PIN(PIN_PC12, 2, 1) +#define PIN_PC12__ISC_D3 PINMUX_PIN(PIN_PC12, 3, 1) +#define PIN_PC12__URXD3 PINMUX_PIN(PIN_PC12, 4, 1) +#define PIN_PC12__TK0 PINMUX_PIN(PIN_PC12, 5, 2) +#define PIN_PC12__A1 PINMUX_PIN(PIN_PC12, 6, 2) +#define PIN_PC13 77 +#define PIN_PC13__GPIO PINMUX_PIN(PIN_PC13, 0, 0) +#define PIN_PC13__LCDDAT5 PINMUX_PIN(PIN_PC13, 1, 2) +#define PIN_PC13__GRXER PINMUX_PIN(PIN_PC13, 2, 1) +#define PIN_PC13__ISC_D4 PINMUX_PIN(PIN_PC13, 3, 1) +#define PIN_PC13__UTXD3 PINMUX_PIN(PIN_PC13, 4, 1) +#define PIN_PC13__TF0 PINMUX_PIN(PIN_PC13, 5, 2) +#define PIN_PC13__A2 PINMUX_PIN(PIN_PC13, 6, 2) +#define PIN_PC14 78 +#define PIN_PC14__GPIO PINMUX_PIN(PIN_PC14, 0, 0) +#define PIN_PC14__LCDDAT6 PINMUX_PIN(PIN_PC14, 1, 2) +#define PIN_PC14__GRX0 PINMUX_PIN(PIN_PC14, 2, 1) +#define PIN_PC14__ISC_D5 PINMUX_PIN(PIN_PC14, 3, 1) +#define PIN_PC14__TDO PINMUX_PIN(PIN_PC14, 5, 2) +#define PIN_PC14__A3 PINMUX_PIN(PIN_PC14, 6, 2) +#define PIN_PC15 79 +#define PIN_PC15__GPIO PINMUX_PIN(PIN_PC15, 0, 0) +#define PIN_PC15__LCDDAT7 PINMUX_PIN(PIN_PC15, 1, 2) +#define PIN_PC15__GRX1 PINMUX_PIN(PIN_PC15, 2, 1) +#define PIN_PC15__ISC_D6 PINMUX_PIN(PIN_PC15, 3, 1) +#define PIN_PC15__RD0 PINMUX_PIN(PIN_PC15, 5, 2) +#define PIN_PC15__A4 PINMUX_PIN(PIN_PC15, 6, 2) +#define PIN_PC16 80 +#define PIN_PC16__GPIO PINMUX_PIN(PIN_PC16, 0, 0) +#define PIN_PC16__LCDDAT10 PINMUX_PIN(PIN_PC16, 1, 2) +#define PIN_PC16__GTX0 PINMUX_PIN(PIN_PC16, 2, 1) +#define PIN_PC16__ISC_D7 PINMUX_PIN(PIN_PC16, 3, 1) +#define PIN_PC16__RK0 PINMUX_PIN(PIN_PC16, 5, 2) +#define PIN_PC16__A5 PINMUX_PIN(PIN_PC16, 6, 2) +#define PIN_PC17 81 +#define PIN_PC17__GPIO PINMUX_PIN(PIN_PC17, 0, 0) +#define PIN_PC17__LCDDAT11 PINMUX_PIN(PIN_PC17, 1, 2) +#define PIN_PC17__GTX1 PINMUX_PIN(PIN_PC17, 2, 1) +#define PIN_PC17__ISC_D8 PINMUX_PIN(PIN_PC17, 3, 1) +#define PIN_PC17__RF0 PINMUX_PIN(PIN_PC17, 5, 2) +#define PIN_PC17__A6 PINMUX_PIN(PIN_PC17, 6, 2) +#define PIN_PC18 82 +#define PIN_PC18__GPIO PINMUX_PIN(PIN_PC18, 0, 0) +#define PIN_PC18__LCDDAT12 PINMUX_PIN(PIN_PC18, 1, 2) +#define PIN_PC18__GMDC PINMUX_PIN(PIN_PC18, 2, 1) +#define PIN_PC18__ISC_D9 PINMUX_PIN(PIN_PC18, 3, 1) +#define PIN_PC18__FLEXCOM3_IO2 PINMUX_PIN(PIN_PC18, 5, 2) +#define PIN_PC18__A7 PINMUX_PIN(PIN_PC18, 6, 2) +#define PIN_PC19 83 +#define PIN_PC19__GPIO PINMUX_PIN(PIN_PC19, 0, 0) +#define PIN_PC19__LCDDAT13 PINMUX_PIN(PIN_PC19, 1, 2) +#define PIN_PC19__GMDIO PINMUX_PIN(PIN_PC19, 2, 1) +#define PIN_PC19__ISC_D10 PINMUX_PIN(PIN_PC19, 3, 1) +#define PIN_PC19__FLEXCOM3_IO1 PINMUX_PIN(PIN_PC19, 5, 2) +#define PIN_PC19__A8 PINMUX_PIN(PIN_PC19, 6, 2) +#define PIN_PC20 84 +#define PIN_PC20__GPIO PINMUX_PIN(PIN_PC20, 0, 0) +#define PIN_PC20__LCDDAT14 PINMUX_PIN(PIN_PC20, 1, 2) +#define PIN_PC20__GRXCK PINMUX_PIN(PIN_PC20, 2, 1) +#define PIN_PC20__ISC_D11 PINMUX_PIN(PIN_PC20, 3, 1) +#define PIN_PC20__FLEXCOM3_IO0 PINMUX_PIN(PIN_PC20, 5, 2) +#define PIN_PC20__A9 PINMUX_PIN(PIN_PC20, 6, 2) +#define PIN_PC21 85 +#define PIN_PC21__GPIO PINMUX_PIN(PIN_PC21, 0, 0) +#define PIN_PC21__LCDDAT15 PINMUX_PIN(PIN_PC21, 1, 2) +#define PIN_PC21__GTXER PINMUX_PIN(PIN_PC21, 2, 1) +#define PIN_PC21__ISC_PCK PINMUX_PIN(PIN_PC21, 3, 1) +#define PIN_PC21__FLEXCOM3_IO3 PINMUX_PIN(PIN_PC21, 5, 2) +#define PIN_PC21__A10 PINMUX_PIN(PIN_PC21, 6, 2) +#define PIN_PC22 86 +#define PIN_PC22__GPIO PINMUX_PIN(PIN_PC22, 0, 0) +#define PIN_PC22__LCDDAT18 PINMUX_PIN(PIN_PC22, 1, 2) +#define PIN_PC22__GCRS PINMUX_PIN(PIN_PC22, 2, 1) +#define PIN_PC22__ISC_VSYNC PINMUX_PIN(PIN_PC22, 3, 1) +#define PIN_PC22__FLEXCOM3_IO4 PINMUX_PIN(PIN_PC22, 5, 2) +#define PIN_PC22__A11 PINMUX_PIN(PIN_PC22, 6, 2) +#define PIN_PC23 87 +#define PIN_PC23__GPIO PINMUX_PIN(PIN_PC23, 0, 0) +#define PIN_PC23__LCDDAT19 PINMUX_PIN(PIN_PC23, 1, 2) +#define PIN_PC23__GCOL PINMUX_PIN(PIN_PC23, 2, 1) +#define PIN_PC23__ISC_HSYNC PINMUX_PIN(PIN_PC23, 3, 1) +#define PIN_PC23__A12 PINMUX_PIN(PIN_PC23, 6, 2) +#define PIN_PC24 88 +#define PIN_PC24__GPIO PINMUX_PIN(PIN_PC24, 0, 0) +#define PIN_PC24__LCDDAT20 PINMUX_PIN(PIN_PC24, 1, 2) +#define PIN_PC24__GRX2 PINMUX_PIN(PIN_PC24, 2, 1) +#define PIN_PC24__ISC_MCK PINMUX_PIN(PIN_PC24, 3, 1) +#define PIN_PC24__A13 PINMUX_PIN(PIN_PC24, 6, 2) +#define PIN_PC25 89 +#define PIN_PC25__GPIO PINMUX_PIN(PIN_PC25, 0, 0) +#define PIN_PC25__LCDDAT21 PINMUX_PIN(PIN_PC25, 1, 2) +#define PIN_PC25__GRX3 PINMUX_PIN(PIN_PC25, 2, 1) +#define PIN_PC25__ISC_FIELD PINMUX_PIN(PIN_PC25, 3, 1) +#define PIN_PC25__A14 PINMUX_PIN(PIN_PC25, 6, 2) +#define PIN_PC26 90 +#define PIN_PC26__GPIO PINMUX_PIN(PIN_PC26, 0, 0) +#define PIN_PC26__LCDDAT22 PINMUX_PIN(PIN_PC26, 1, 2) +#define PIN_PC26__GTX2 PINMUX_PIN(PIN_PC26, 2, 1) +#define PIN_PC26__CANTX1 PINMUX_PIN(PIN_PC26, 4, 1) +#define PIN_PC26__A15 PINMUX_PIN(PIN_PC26, 6, 2) +#define PIN_PC27 91 +#define PIN_PC27__GPIO PINMUX_PIN(PIN_PC27, 0, 0) +#define PIN_PC27__LCDDAT23 PINMUX_PIN(PIN_PC27, 1, 2) +#define PIN_PC27__GTX3 PINMUX_PIN(PIN_PC27, 2, 1) +#define PIN_PC27__PCK1 PINMUX_PIN(PIN_PC27, 3, 2) +#define PIN_PC27__CANRX1 PINMUX_PIN(PIN_PC27, 4, 1) +#define PIN_PC27__TWD0 PINMUX_PIN(PIN_PC27, 5, 2) +#define PIN_PC27__A16 PINMUX_PIN(PIN_PC27, 6, 2) +#define PIN_PC28 92 +#define PIN_PC28__GPIO PINMUX_PIN(PIN_PC28, 0, 0) +#define PIN_PC28__LCDPWM PINMUX_PIN(PIN_PC28, 1, 2) +#define PIN_PC28__FLEXCOM4_IO0 PINMUX_PIN(PIN_PC28, 2, 1) +#define PIN_PC28__PCK2 PINMUX_PIN(PIN_PC28, 3, 2) +#define PIN_PC28__TWCK0 PINMUX_PIN(PIN_PC28, 5, 2) +#define PIN_PC28__A17 PINMUX_PIN(PIN_PC28, 6, 2) +#define PIN_PC29 93 +#define PIN_PC29__GPIO PINMUX_PIN(PIN_PC29, 0, 0) +#define PIN_PC29__LCDDISP PINMUX_PIN(PIN_PC29, 1, 2) +#define PIN_PC29__FLEXCOM4_IO1 PINMUX_PIN(PIN_PC29, 2, 1) +#define PIN_PC29__A18 PINMUX_PIN(PIN_PC29, 6, 2) +#define PIN_PC30 94 +#define PIN_PC30__GPIO PINMUX_PIN(PIN_PC30, 0, 0) +#define PIN_PC30__LCDVSYNC PINMUX_PIN(PIN_PC30, 1, 2) +#define PIN_PC30__FLEXCOM4_IO2 PINMUX_PIN(PIN_PC30, 2, 1) +#define PIN_PC30__A19 PINMUX_PIN(PIN_PC30, 6, 2) +#define PIN_PC31 95 +#define PIN_PC31__GPIO PINMUX_PIN(PIN_PC31, 0, 0) +#define PIN_PC31__LCDHSYNC PINMUX_PIN(PIN_PC31, 1, 2) +#define PIN_PC31__FLEXCOM4_IO3 PINMUX_PIN(PIN_PC31, 2, 1) +#define PIN_PC31__URXD3 PINMUX_PIN(PIN_PC31, 3, 2) +#define PIN_PC31__A20 PINMUX_PIN(PIN_PC31, 6, 2) +#define PIN_PD0 96 +#define PIN_PD0__GPIO PINMUX_PIN(PIN_PD0, 0, 0) +#define PIN_PD0__LCDPCK PINMUX_PIN(PIN_PD0, 1, 2) +#define PIN_PD0__FLEXCOM4_IO4 PINMUX_PIN(PIN_PD0, 2, 1) +#define PIN_PD0__UTXD3 PINMUX_PIN(PIN_PD0, 3, 2) +#define PIN_PD0__GTSUCOMP PINMUX_PIN(PIN_PD0, 4, 2) +#define PIN_PD0__A23 PINMUX_PIN(PIN_PD0, 6, 2) +#define PIN_PD1 97 +#define PIN_PD1__GPIO PINMUX_PIN(PIN_PD1, 0, 0) +#define PIN_PD1__LCDDEN PINMUX_PIN(PIN_PD1, 1, 2) +#define PIN_PD1__GRXCK PINMUX_PIN(PIN_PD1, 4, 2) +#define PIN_PD1__A24 PINMUX_PIN(PIN_PD1, 6, 2) +#define PIN_PD2 98 +#define PIN_PD2__GPIO PINMUX_PIN(PIN_PD2, 0, 0) +#define PIN_PD2__URXD1 PINMUX_PIN(PIN_PD2, 1, 1) +#define PIN_PD2__GTXER PINMUX_PIN(PIN_PD2, 4, 2) +#define PIN_PD2__ISC_MCK PINMUX_PIN(PIN_PD2, 5, 2) +#define PIN_PD2__A25 PINMUX_PIN(PIN_PD2, 6, 2) +#define PIN_PD3 99 +#define PIN_PD3__GPIO PINMUX_PIN(PIN_PD3, 0, 0) +#define PIN_PD3__UTXD1 PINMUX_PIN(PIN_PD3, 1, 1) +#define PIN_PD3__FIQ PINMUX_PIN(PIN_PD3, 2, 2) +#define PIN_PD3__GCRS PINMUX_PIN(PIN_PD3, 4, 2) +#define PIN_PD3__ISC_D11 PINMUX_PIN(PIN_PD3, 5, 2) +#define PIN_PD3__NWAIT PINMUX_PIN(PIN_PD3, 6, 2) +#define PIN_PD4 100 +#define PIN_PD4__GPIO PINMUX_PIN(PIN_PD4, 0, 0) +#define PIN_PD4__TWD1 PINMUX_PIN(PIN_PD4, 1, 2) +#define PIN_PD4__URXD2 PINMUX_PIN(PIN_PD4, 2, 1) +#define PIN_PD4__GCOL PINMUX_PIN(PIN_PD4, 4, 2) +#define PIN_PD4__ISC_D10 PINMUX_PIN(PIN_PD4, 5, 2) +#define PIN_PD4__NCS0 PINMUX_PIN(PIN_PD4, 6, 2) +#define PIN_PD5 101 +#define PIN_PD5__GPIO PINMUX_PIN(PIN_PD5, 0, 0) +#define PIN_PD5__TWCK1 PINMUX_PIN(PIN_PD5, 1, 2) +#define PIN_PD5__UTXD2 PINMUX_PIN(PIN_PD5, 2, 1) +#define PIN_PD5__GRX2 PINMUX_PIN(PIN_PD5, 4, 2) +#define PIN_PD5__ISC_D9 PINMUX_PIN(PIN_PD5, 5, 2) +#define PIN_PD5__NCS1 PINMUX_PIN(PIN_PD5, 6, 2) +#define PIN_PD6 102 +#define PIN_PD6__GPIO PINMUX_PIN(PIN_PD6, 0, 0) +#define PIN_PD6__TCK PINMUX_PIN(PIN_PD6, 1, 2) +#define PIN_PD6__PCK1 PINMUX_PIN(PIN_PD6, 2, 1) +#define PIN_PD6__GRX3 PINMUX_PIN(PIN_PD6, 4, 2) +#define PIN_PD6__ISC_D8 PINMUX_PIN(PIN_PD6, 5, 2) +#define PIN_PD6__NCS2 PINMUX_PIN(PIN_PD6, 6, 2) +#define PIN_PD7 103 +#define PIN_PD7__GPIO PINMUX_PIN(PIN_PD7, 0, 0) +#define PIN_PD7__TDI PINMUX_PIN(PIN_PD7, 1, 2) +#define PIN_PD7__UTMI_RXVAL PINMUX_PIN(PIN_PD7, 3, 1) +#define PIN_PD7__GTX2 PINMUX_PIN(PIN_PD7, 4, 2) +#define PIN_PD7__ISC_D0 PINMUX_PIN(PIN_PD7, 5, 2) +#define PIN_PD7__NWR1_NBS1 PINMUX_PIN(PIN_PD7, 6, 2) +#define PIN_PD8 104 +#define PIN_PD8__GPIO PINMUX_PIN(PIN_PD8, 0, 0) +#define PIN_PD8__TDO PINMUX_PIN(PIN_PD8, 1, 2) +#define PIN_PD8__UTMI_RXERR PINMUX_PIN(PIN_PD8, 3, 1) +#define PIN_PD8__GTX3 PINMUX_PIN(PIN_PD8, 4, 2) +#define PIN_PD8__ISC_D1 PINMUX_PIN(PIN_PD8, 5, 2) +#define PIN_PD8__NANDRDY PINMUX_PIN(PIN_PD8, 6, 2) +#define PIN_PD9 105 +#define PIN_PD9__GPIO PINMUX_PIN(PIN_PD9, 0, 0) +#define PIN_PD9__TMS PINMUX_PIN(PIN_PD9, 1, 2) +#define PIN_PD9__UTMI_RXACT PINMUX_PIN(PIN_PD9, 3, 1) +#define PIN_PD9__GTXCK PINMUX_PIN(PIN_PD9, 4, 2) +#define PIN_PD9__ISC_D2 PINMUX_PIN(PIN_PD9, 5, 2) +#define PIN_PD10 106 +#define PIN_PD10__GPIO PINMUX_PIN(PIN_PD10, 0, 0) +#define PIN_PD10__NTRST PINMUX_PIN(PIN_PD10, 1, 2) +#define PIN_PD10__UTMI_HDIS PINMUX_PIN(PIN_PD10, 3, 1) +#define PIN_PD10__GTXEN PINMUX_PIN(PIN_PD10, 4, 2) +#define PIN_PD10__ISC_D3 PINMUX_PIN(PIN_PD10, 5, 2) +#define PIN_PD11 107 +#define PIN_PD11__GPIO PINMUX_PIN(PIN_PD11, 0, 0) +#define PIN_PD11__TIOA1 PINMUX_PIN(PIN_PD11, 1, 3) +#define PIN_PD11__PCK2 PINMUX_PIN(PIN_PD11, 2, 2) +#define PIN_PD11__UTMI_LS0 PINMUX_PIN(PIN_PD11, 3, 1) +#define PIN_PD11__GRXDV PINMUX_PIN(PIN_PD11, 4, 2) +#define PIN_PD11__ISC_D4 PINMUX_PIN(PIN_PD11, 5, 2) +#define PIN_PD11__ISC_MCK PINMUX_PIN(PIN_PD11, 7, 4) +#define PIN_PD12 108 +#define PIN_PD12__GPIO PINMUX_PIN(PIN_PD12, 0, 0) +#define PIN_PD12__TIOB1 PINMUX_PIN(PIN_PD12, 1, 3) +#define PIN_PD12__FLEXCOM4_IO0 PINMUX_PIN(PIN_PD12, 2, 2) +#define PIN_PD12__UTMI_LS1 PINMUX_PIN(PIN_PD12, 3, 1) +#define PIN_PD12__GRXER PINMUX_PIN(PIN_PD12, 4, 2) +#define PIN_PD12__ISC_D5 PINMUX_PIN(PIN_PD12, 5, 2) +#define PIN_PD12__ISC_D4 PINMUX_PIN(PIN_PD12, 6, 4) +#define PIN_PD13 109 +#define PIN_PD13__GPIO PINMUX_PIN(PIN_PD13, 0, 0) +#define PIN_PD13__TCLK1 PINMUX_PIN(PIN_PD13, 1, 3) +#define PIN_PD13__FLEXCOM4_IO1 PINMUX_PIN(PIN_PD13, 2, 2) +#define PIN_PD13__UTMI_CDRPCSEL0 PINMUX_PIN(PIN_PD13, 3, 1) +#define PIN_PD13__GRX0 PINMUX_PIN(PIN_PD13, 4, 2) +#define PIN_PD13__ISC_D6 PINMUX_PIN(PIN_PD13, 5, 2) +#define PIN_PD13__ISC_D5 PINMUX_PIN(PIN_PD13, 6, 4) +#define PIN_PD14 110 +#define PIN_PD14__GPIO PINMUX_PIN(PIN_PD14, 0, 0) +#define PIN_PD14__TCK PINMUX_PIN(PIN_PD14, 1, 1) +#define PIN_PD14__FLEXCOM4_IO2 PINMUX_PIN(PIN_PD14, 2, 2) +#define PIN_PD14__UTMI_CDRPCSEL1 PINMUX_PIN(PIN_PD14, 3, 1) +#define PIN_PD14__GRX1 PINMUX_PIN(PIN_PD14, 4, 2) +#define PIN_PD14__ISC_D7 PINMUX_PIN(PIN_PD14, 5, 2) +#define PIN_PD14__ISC_D6 PINMUX_PIN(PIN_PD14, 6, 4) +#define PIN_PD15 111 +#define PIN_PD15__GPIO PINMUX_PIN(PIN_PD15, 0, 0) +#define PIN_PD15__TDI PINMUX_PIN(PIN_PD15, 1, 1) +#define PIN_PD15__FLEXCOM4_IO3 PINMUX_PIN(PIN_PD15, 2, 2) +#define PIN_PD15__UTMI_CDRCPDIVEN PINMUX_PIN(PIN_PD15, 3, 1) +#define PIN_PD15__GTX0 PINMUX_PIN(PIN_PD15, 4, 2) +#define PIN_PD15__ISC_PCK PINMUX_PIN(PIN_PD15, 5, 2) +#define PIN_PD15__ISC_D7 PINMUX_PIN(PIN_PD15, 6, 4) +#define PIN_PD16 112 +#define PIN_PD16__GPIO PINMUX_PIN(PIN_PD16, 0, 0) +#define PIN_PD16__TDO PINMUX_PIN(PIN_PD16, 1, 1) +#define PIN_PD16__FLEXCOM4_IO4 PINMUX_PIN(PIN_PD16, 2, 2) +#define PIN_PD16__UTMI_CDRBISTEN PINMUX_PIN(PIN_PD16, 3, 1) +#define PIN_PD16__GTX1 PINMUX_PIN(PIN_PD16, 4, 2) +#define PIN_PD16__ISC_VSYNC PINMUX_PIN(PIN_PD16, 5, 2) +#define PIN_PD16__ISC_D8 PINMUX_PIN(PIN_PD16, 6, 4) +#define PIN_PD17 113 +#define PIN_PD17__GPIO PINMUX_PIN(PIN_PD17, 0, 0) +#define PIN_PD17__TMS PINMUX_PIN(PIN_PD17, 1, 1) +#define PIN_PD17__UTMI_CDRCPSELDIV PINMUX_PIN(PIN_PD17, 3, 1) +#define PIN_PD17__GMDC PINMUX_PIN(PIN_PD17, 4, 2) +#define PIN_PD17__ISC_HSYNC PINMUX_PIN(PIN_PD17, 5, 2) +#define PIN_PD17__ISC_D9 PINMUX_PIN(PIN_PD17, 6, 4) +#define PIN_PD18 114 +#define PIN_PD18__GPIO PINMUX_PIN(PIN_PD18, 0, 0) +#define PIN_PD18__NTRST PINMUX_PIN(PIN_PD18, 1, 1) +#define PIN_PD18__GMDIO PINMUX_PIN(PIN_PD18, 4, 2) +#define PIN_PD18__ISC_FIELD PINMUX_PIN(PIN_PD18, 5, 2) +#define PIN_PD18__ISC_D10 PINMUX_PIN(PIN_PD18, 6, 4) +#define PIN_PD19 115 +#define PIN_PD19__GPIO PINMUX_PIN(PIN_PD19, 0, 0) +#define PIN_PD19__PCK0 PINMUX_PIN(PIN_PD19, 1, 1) +#define PIN_PD19__TWD1 PINMUX_PIN(PIN_PD19, 2, 3) +#define PIN_PD19__URXD2 PINMUX_PIN(PIN_PD19, 3, 3) +#define PIN_PD19__I2SC0_CK PINMUX_PIN(PIN_PD19, 5, 2) +#define PIN_PD19__ISC_D11 PINMUX_PIN(PIN_PD19, 6, 4) +#define PIN_PD20 116 +#define PIN_PD20__GPIO PINMUX_PIN(PIN_PD20, 0, 0) +#define PIN_PD20__TIOA2 PINMUX_PIN(PIN_PD20, 1, 3) +#define PIN_PD20__TWCK1 PINMUX_PIN(PIN_PD20, 2, 3) +#define PIN_PD20__UTXD2 PINMUX_PIN(PIN_PD20, 3, 3) +#define PIN_PD20__I2SC0_MCK PINMUX_PIN(PIN_PD20, 5, 2) +#define PIN_PD20__ISC_PCK PINMUX_PIN(PIN_PD20, 6, 4) +#define PIN_PD21 117 +#define PIN_PD21__GPIO PINMUX_PIN(PIN_PD21, 0, 0) +#define PIN_PD21__TIOB2 PINMUX_PIN(PIN_PD21, 1, 3) +#define PIN_PD21__TWD0 PINMUX_PIN(PIN_PD21, 2, 4) +#define PIN_PD21__FLEXCOM4_IO0 PINMUX_PIN(PIN_PD21, 3, 3) +#define PIN_PD21__I2SC0_WS PINMUX_PIN(PIN_PD21, 5, 2) +#define PIN_PD21__ISC_VSYNC PINMUX_PIN(PIN_PD21, 6, 4) +#define PIN_PD22 118 +#define PIN_PD22__GPIO PINMUX_PIN(PIN_PD22, 0, 0) +#define PIN_PD22__TCLK2 PINMUX_PIN(PIN_PD22, 1, 3) +#define PIN_PD22__TWCK0 PINMUX_PIN(PIN_PD22, 2, 4) +#define PIN_PD22__FLEXCOM4_IO1 PINMUX_PIN(PIN_PD22, 3, 3) +#define PIN_PD22__I2SC0_DI0 PINMUX_PIN(PIN_PD22, 5, 2) +#define PIN_PD22__ISC_HSYNC PINMUX_PIN(PIN_PD22, 6, 4) +#define PIN_PD23 119 +#define PIN_PD23__GPIO PINMUX_PIN(PIN_PD23, 0, 0) +#define PIN_PD23__URXD2 PINMUX_PIN(PIN_PD23, 1, 2) +#define PIN_PD23__FLEXCOM4_IO2 PINMUX_PIN(PIN_PD23, 3, 3) +#define PIN_PD23__I2SC0_DO0 PINMUX_PIN(PIN_PD23, 5, 2) +#define PIN_PD23__ISC_FIELD PINMUX_PIN(PIN_PD23, 6, 4) +#define PIN_PD24 120 +#define PIN_PD24__GPIO PINMUX_PIN(PIN_PD24, 0, 0) +#define PIN_PD24__UTXD2 PINMUX_PIN(PIN_PD23, 1, 2) +#define PIN_PD24__FLEXCOM4_IO3 PINMUX_PIN(PIN_PD23, 3, 3) +#define PIN_PD25 121 +#define PIN_PD25__GPIO PINMUX_PIN(PIN_PD25, 0, 0) +#define PIN_PD25__SPI1_SPCK PINMUX_PIN(PIN_PD25, 1, 3) +#define PIN_PD25__FLEXCOM4_IO4 PINMUX_PIN(PIN_PD25, 3, 3) +#define PIN_PD26 122 +#define PIN_PD26__GPIO PINMUX_PIN(PIN_PD26, 0, 0) +#define PIN_PD26__SPI1_MOSI PINMUX_PIN(PIN_PD26, 1, 3) +#define PIN_PD26__FLEXCOM2_IO0 PINMUX_PIN(PIN_PD26, 3, 2) +#define PIN_PD27 123 +#define PIN_PD27__GPIO PINMUX_PIN(PIN_PD27, 0, 0) +#define PIN_PD27__SPI1_MISO PINMUX_PIN(PIN_PD27, 1, 3) +#define PIN_PD27__TCK PINMUX_PIN(PIN_PD27, 2, 3) +#define PIN_PD27__FLEXCOM2_IO1 PINMUX_PIN(PIN_PD27, 3, 2) +#define PIN_PD28 124 +#define PIN_PD28__GPIO PINMUX_PIN(PIN_PD28, 0, 0) +#define PIN_PD28__SPI1_NPCS0 PINMUX_PIN(PIN_PD28, 1, 3) +#define PIN_PD28__TCI PINMUX_PIN(PIN_PD28, 2, 3) +#define PIN_PD28__FLEXCOM2_IO2 PINMUX_PIN(PIN_PD28, 3, 2) +#define PIN_PD29 125 +#define PIN_PD29__GPIO PINMUX_PIN(PIN_PD29, 0, 0) +#define PIN_PD29__SPI1_NPCS1 PINMUX_PIN(PIN_PD29, 1, 3) +#define PIN_PD29__TDO PINMUX_PIN(PIN_PD29, 2, 3) +#define PIN_PD29__FLEXCOM2_IO3 PINMUX_PIN(PIN_PD29, 3, 2) +#define PIN_PD29__TIOA3 PINMUX_PIN(PIN_PD29, 4, 3) +#define PIN_PD29__TWD0 PINMUX_PIN(PIN_PD29, 5, 3) +#define PIN_PD30 126 +#define PIN_PD30__GPIO PINMUX_PIN(PIN_PD30, 0, 0) +#define PIN_PD30__SPI1_NPCS2 PINMUX_PIN(PIN_PD30, 1, 3) +#define PIN_PD30__TMS PINMUX_PIN(PIN_PD30, 2, 3) +#define PIN_PD30__FLEXCOM2_IO4 PINMUX_PIN(PIN_PD30, 3, 2) +#define PIN_PD30__TIOB3 PINMUX_PIN(PIN_PD30, 4, 3) +#define PIN_PD30__TWCK0 PINMUX_PIN(PIN_PD30, 5, 3) +#define PIN_PD31 127 +#define PIN_PD31__GPIO PINMUX_PIN(PIN_PD31, 0, 0) +#define PIN_PD31__ADTRG PINMUX_PIN(PIN_PD31, 1, 1) +#define PIN_PD31__NTRST PINMUX_PIN(PIN_PD31, 2, 3) +#define PIN_PD31__IRQ PINMUX_PIN(PIN_PD31, 3, 4) +#define PIN_PD31__TCLK3 PINMUX_PIN(PIN_PD31, 4, 3) +#define PIN_PD31__PCK0 PINMUX_PIN(PIN_PD31, 5, 2) diff --git a/arch/arm/dts/sama5d2.dtsi b/arch/arm/dts/sama5d2.dtsi new file mode 100644 index 00000000000..19feb6609db --- /dev/null +++ b/arch/arm/dts/sama5d2.dtsi @@ -0,0 +1,671 @@ +#include "skeleton.dtsi" + +/ { + model = "Atmel SAMA5D2 family SoC"; + compatible = "atmel,sama5d2"; + + aliases { + spi0 = &spi0; + spi1 = &qspi0; + i2c0 = &i2c0; + i2c1 = &i2c1; + }; + + clocks { + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + usb1: ohci@00400000 { + compatible = "atmel,at91rm9200-ohci", "usb-ohci"; + reg = <0x00400000 0x100000>; + clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; + clock-names = "ohci_clk", "hclk", "uhpck"; + status = "disabled"; + }; + + usb2: ehci@00500000 { + compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; + reg = <0x00500000 0x100000>; + clocks = <&utmi>, <&uhphs_clk>; + clock-names = "usb_clk", "ehci_clk"; + status = "disabled"; + }; + + sdmmc0: sdio-host@a0000000 { + compatible = "atmel,sama5d2-sdhci"; + reg = <0xa0000000 0x300>; + clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>; + clock-names = "hclock", "multclk", "baseclk"; + status = "disabled"; + }; + + sdmmc1: sdio-host@b0000000 { + compatible = "atmel,sama5d2-sdhci"; + reg = <0xb0000000 0x300>; + clocks = <&sdmmc1_hclk>, <&sdmmc1_gclk>, <&main>; + clock-names = "hclock", "multclk", "baseclk"; + status = "disabled"; + }; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + pmc: pmc@f0014000 { + compatible = "atmel,sama5d2-pmc", "syscon"; + reg = <0xf0014000 0x160>; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + main: mainck { + compatible = "atmel,at91sam9x5-clk-main"; + #clock-cells = <0>; + }; + + plla: pllack { + compatible = "atmel,sama5d3-clk-pll"; + #clock-cells = <0>; + clocks = <&main>; + reg = <0>; + atmel,clk-input-range = <12000000 12000000>; + #atmel,pll-clk-output-range-cells = <4>; + atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>; + }; + + plladiv: plladivck { + compatible = "atmel,at91sam9x5-clk-plldiv"; + #clock-cells = <0>; + clocks = <&plla>; + }; + + audio_pll_frac: audiopll_fracck { + compatible = "atmel,sama5d2-clk-audio-pll-frac"; + #clock-cells = <0>; + clocks = <&main>; + }; + + audio_pll_pad: audiopll_padck { + compatible = "atmel,sama5d2-clk-audio-pll-pad"; + #clock-cells = <0>; + clocks = <&audio_pll_frac>; + }; + + audio_pll_pmc: audiopll_pmcck { + compatible = "atmel,sama5d2-clk-audio-pll-pmc"; + #clock-cells = <0>; + clocks = <&audio_pll_frac>; + }; + + utmi: utmick { + compatible = "atmel,at91sam9x5-clk-utmi"; + #clock-cells = <0>; + clocks = <&main>; + }; + + mck: masterck { + compatible = "atmel,at91sam9x5-clk-master"; + #clock-cells = <0>; + clocks = <&main>, <&plladiv>, <&utmi>; + atmel,clk-output-range = <124000000 166000000>; + atmel,clk-divisors = <1 2 4 3>; + }; + + h32ck: h32mxck { + #clock-cells = <0>; + compatible = "atmel,sama5d4-clk-h32mx"; + clocks = <&mck>; + }; + + usb: usbck { + compatible = "atmel,at91sam9x5-clk-usb"; + #clock-cells = <0>; + clocks = <&plladiv>, <&utmi>; + }; + + prog: progck { + compatible = "atmel,at91sam9x5-clk-programmable"; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&pmc>; + clocks = <&main>, <&plladiv>, <&utmi>, <&mck>; + + prog0: prog0 { + #clock-cells = <0>; + reg = <0>; + }; + + prog1: prog1 { + #clock-cells = <0>; + reg = <1>; + }; + + prog2: prog2 { + #clock-cells = <0>; + reg = <2>; + }; + }; + + systemck { + compatible = "atmel,at91rm9200-clk-system"; + #address-cells = <1>; + #size-cells = <0>; + + ddrck: ddrck { + #clock-cells = <0>; + reg = <2>; + clocks = <&mck>; + }; + + lcdck: lcdck { + #clock-cells = <0>; + reg = <3>; + clocks = <&mck>; + }; + + uhpck: uhpck { + #clock-cells = <0>; + reg = <6>; + clocks = <&usb>; + }; + + udpck: udpck { + #clock-cells = <0>; + reg = <7>; + clocks = <&usb>; + }; + + pck0: pck0 { + #clock-cells = <0>; + reg = <8>; + clocks = <&prog0>; + }; + + pck1: pck1 { + #clock-cells = <0>; + reg = <9>; + clocks = <&prog1>; + }; + + pck2: pck2 { + #clock-cells = <0>; + reg = <10>; + clocks = <&prog2>; + }; + + iscck: iscck { + #clock-cells = <0>; + reg = <18>; + clocks = <&mck>; + }; + }; + + periph32ck { + compatible = "atmel,at91sam9x5-clk-peripheral"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&h32ck>; + + macb0_clk: macb0_clk { + #clock-cells = <0>; + reg = <5>; + atmel,clk-output-range = <0 83000000>; + }; + + tdes_clk: tdes_clk { + #clock-cells = <0>; + reg = <11>; + atmel,clk-output-range = <0 83000000>; + }; + + matrix1_clk: matrix1_clk { + #clock-cells = <0>; + reg = <14>; + }; + + hsmc_clk: hsmc_clk { + #clock-cells = <0>; + reg = <17>; + }; + + pioA_clk: pioA_clk { + #clock-cells = <0>; + reg = <18>; + atmel,clk-output-range = <0 83000000>; + }; + + flx0_clk: flx0_clk { + #clock-cells = <0>; + reg = <19>; + atmel,clk-output-range = <0 83000000>; + }; + + flx1_clk: flx1_clk { + #clock-cells = <0>; + reg = <20>; + atmel,clk-output-range = <0 83000000>; + }; + + flx2_clk: flx2_clk { + #clock-cells = <0>; + reg = <21>; + atmel,clk-output-range = <0 83000000>; + }; + + flx3_clk: flx3_clk { + #clock-cells = <0>; + reg = <22>; + atmel,clk-output-range = <0 83000000>; + }; + + flx4_clk: flx4_clk { + #clock-cells = <0>; + reg = <23>; + atmel,clk-output-range = <0 83000000>; + }; + + uart0_clk: uart0_clk { + #clock-cells = <0>; + reg = <24>; + atmel,clk-output-range = <0 83000000>; + }; + + uart1_clk: uart1_clk { + #clock-cells = <0>; + reg = <25>; + atmel,clk-output-range = <0 83000000>; + }; + + uart2_clk: uart2_clk { + #clock-cells = <0>; + reg = <26>; + atmel,clk-output-range = <0 83000000>; + }; + + uart3_clk: uart3_clk { + #clock-cells = <0>; + reg = <27>; + atmel,clk-output-range = <0 83000000>; + }; + + uart4_clk: uart4_clk { + #clock-cells = <0>; + reg = <28>; + atmel,clk-output-range = <0 83000000>; + }; + + twi0_clk: twi0_clk { + reg = <29>; + #clock-cells = <0>; + atmel,clk-output-range = <0 83000000>; + }; + + twi1_clk: twi1_clk { + #clock-cells = <0>; + reg = <30>; + atmel,clk-output-range = <0 83000000>; + }; + + spi0_clk: spi0_clk { + #clock-cells = <0>; + reg = <33>; + atmel,clk-output-range = <0 83000000>; + }; + + spi1_clk: spi1_clk { + #clock-cells = <0>; + reg = <34>; + atmel,clk-output-range = <0 83000000>; + }; + + tcb0_clk: tcb0_clk { + #clock-cells = <0>; + reg = <35>; + atmel,clk-output-range = <0 83000000>; + }; + + tcb1_clk: tcb1_clk { + #clock-cells = <0>; + reg = <36>; + atmel,clk-output-range = <0 83000000>; + }; + + pwm_clk: pwm_clk { + #clock-cells = <0>; + reg = <38>; + atmel,clk-output-range = <0 83000000>; + }; + + adc_clk: adc_clk { + #clock-cells = <0>; + reg = <40>; + atmel,clk-output-range = <0 83000000>; + }; + + uhphs_clk: uhphs_clk { + #clock-cells = <0>; + reg = <41>; + atmel,clk-output-range = <0 83000000>; + }; + + udphs_clk: udphs_clk { + #clock-cells = <0>; + reg = <42>; + atmel,clk-output-range = <0 83000000>; + }; + + ssc0_clk: ssc0_clk { + #clock-cells = <0>; + reg = <43>; + atmel,clk-output-range = <0 83000000>; + }; + + ssc1_clk: ssc1_clk { + #clock-cells = <0>; + reg = <44>; + atmel,clk-output-range = <0 83000000>; + }; + + trng_clk: trng_clk { + #clock-cells = <0>; + reg = <47>; + atmel,clk-output-range = <0 83000000>; + }; + + pdmic_clk: pdmic_clk { + #clock-cells = <0>; + reg = <48>; + atmel,clk-output-range = <0 83000000>; + }; + + i2s0_clk: i2s0_clk { + #clock-cells = <0>; + reg = <54>; + atmel,clk-output-range = <0 83000000>; + }; + + i2s1_clk: i2s1_clk { + #clock-cells = <0>; + reg = <55>; + atmel,clk-output-range = <0 83000000>; + }; + + can0_clk: can0_clk { + #clock-cells = <0>; + reg = <56>; + atmel,clk-output-range = <0 83000000>; + }; + + can1_clk: can1_clk { + #clock-cells = <0>; + reg = <57>; + atmel,clk-output-range = <0 83000000>; + }; + + classd_clk: classd_clk { + #clock-cells = <0>; + reg = <59>; + atmel,clk-output-range = <0 83000000>; + }; + }; + + periph64ck { + compatible = "atmel,at91sam9x5-clk-peripheral"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mck>; + + dma0_clk: dma0_clk { + #clock-cells = <0>; + reg = <6>; + }; + + dma1_clk: dma1_clk { + #clock-cells = <0>; + reg = <7>; + }; + + aes_clk: aes_clk { + #clock-cells = <0>; + reg = <9>; + }; + + aesb_clk: aesb_clk { + #clock-cells = <0>; + reg = <10>; + }; + + sha_clk: sha_clk { + #clock-cells = <0>; + reg = <12>; + }; + + mpddr_clk: mpddr_clk { + #clock-cells = <0>; + reg = <13>; + }; + + matrix0_clk: matrix0_clk { + #clock-cells = <0>; + reg = <15>; + }; + + sdmmc0_hclk: sdmmc0_hclk { + #clock-cells = <0>; + reg = <31>; + }; + + sdmmc1_hclk: sdmmc1_hclk { + #clock-cells = <0>; + reg = <32>; + }; + + lcdc_clk: lcdc_clk { + #clock-cells = <0>; + reg = <45>; + }; + + isc_clk: isc_clk { + #clock-cells = <0>; + reg = <46>; + }; + + qspi0_clk: qspi0_clk { + #clock-cells = <0>; + reg = <52>; + }; + + qspi1_clk: qspi1_clk { + #clock-cells = <0>; + reg = <53>; + }; + }; + + gck { + compatible = "atmel,sama5d2-clk-generated"; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&pmc>; + clocks = <&main>, <&plla>, <&utmi>, <&mck>; + + sdmmc0_gclk: sdmmc0_gclk { + #clock-cells = <0>; + reg = <31>; + }; + + sdmmc1_gclk: sdmmc1_gclk { + #clock-cells = <0>; + reg = <32>; + }; + + tcb0_gclk: tcb0_gclk { + #clock-cells = <0>; + reg = <35>; + atmel,clk-output-range = <0 83000000>; + }; + + tcb1_gclk: tcb1_gclk { + #clock-cells = <0>; + reg = <36>; + atmel,clk-output-range = <0 83000000>; + }; + + pwm_gclk: pwm_gclk { + #clock-cells = <0>; + reg = <38>; + atmel,clk-output-range = <0 83000000>; + }; + + pdmic_gclk: pdmic_gclk { + #clock-cells = <0>; + reg = <48>; + }; + + i2s0_gclk: i2s0_gclk { + #clock-cells = <0>; + reg = <54>; + }; + + i2s1_gclk: i2s1_gclk { + #clock-cells = <0>; + reg = <55>; + }; + + can0_gclk: can0_gclk { + #clock-cells = <0>; + reg = <56>; + atmel,clk-output-range = <0 80000000>; + }; + + can1_gclk: can1_gclk { + #clock-cells = <0>; + reg = <57>; + atmel,clk-output-range = <0 80000000>; + }; + + classd_gclk: classd_gclk { + #clock-cells = <0>; + reg = <59>; + atmel,clk-output-range = <0 100000000>; + }; + }; + }; + + qspi0: spi@f0020000 { + compatible = "atmel,sama5d2-qspi"; + reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>; + reg-names = "qspi_base", "qspi_mmap"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&qspi0_clk>; + status = "disabled"; + }; + + spi0: spi@f8000000 { + compatible = "atmel,at91rm9200-spi"; + reg = <0xf8000000 0x100>; + clocks = <&spi0_clk>; + clock-names = "spi_clk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + macb0: ethernet@f8008000 { + compatible = "cdns,macb"; + reg = <0xf8008000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&macb0_clk>, <&macb0_clk>; + clock-names = "hclk", "pclk"; + status = "disabled"; + }; + + uart1: serial@f8020000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf8020000 0x100>; + status = "disabled"; + }; + + i2c0: i2c@f8028000 { + compatible = "atmel,sama5d2-i2c"; + reg = <0xf8028000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&twi0_clk>; + status = "disabled"; + }; + + sckc@f8048050 { + compatible = "atmel,at91sam9x5-sckc"; + reg = <0xf8048050 0x4>; + + slow_rc_osc: slow_rc_osc { + compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-accuracy = <250000000>; + atmel,startup-time-usec = <75>; + }; + + slow_osc: slow_osc { + compatible = "atmel,at91sam9x5-clk-slow-osc"; + #clock-cells = <0>; + clocks = <&slow_xtal>; + atmel,startup-time-usec = <1200000>; + }; + + clk32k: slowck { + compatible = "atmel,at91sam9x5-clk-slow"; + #clock-cells = <0>; + clocks = <&slow_rc_osc &slow_osc>; + }; + }; + + spi1: spi@fc000000 { + compatible = "atmel,at91rm9200-spi"; + reg = <0xfc000000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@fc028000 { + compatible = "atmel,sama5d2-i2c"; + reg = <0xfc028000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&twi1_clk>; + status = "disabled"; + }; + + pioA: gpio@fc038000 { + compatible = "atmel,sama5d2-gpio"; + reg = <0xfc038000 0x600>; + clocks = <&pioA_clk>; + gpio-controller; + #gpio-cells = <2>; + + pinctrl { + compatible = "atmel,sama5d2-pinctrl"; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/sun50i-a64-pine64-plus.dts b/arch/arm/dts/sun50i-a64-pine64-plus.dts index 549dc15bd5d..389c6096ca1 100644 --- a/arch/arm/dts/sun50i-a64-pine64-plus.dts +++ b/arch/arm/dts/sun50i-a64-pine64-plus.dts @@ -57,3 +57,16 @@ reg = <0x40000000 0x40000000>; }; }; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + phy-mode = "rgmii"; + phy = <&phy1>; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi index 1bd436f8470..7d0dc76a11f 100644 --- a/arch/arm/dts/sun50i-a64.dtsi +++ b/arch/arm/dts/sun50i-a64.dtsi @@ -506,6 +506,25 @@ allwinner,drive = <SUN4I_PINCTRL_10_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; + + rmii_pins: rmii_pins { + allwinner,pins = "PD10", "PD11", "PD13", "PD14", + "PD17", "PD18", "PD19", "PD20", + "PD22", "PD23"; + allwinner,function = "emac"; + allwinner,drive = <SUN4I_PINCTRL_40_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + rgmii_pins: rgmii_pins { + allwinner,pins = "PD8", "PD9", "PD10", "PD11", + "PD12", "PD13", "PD15", + "PD16", "PD17", "PD18", "PD19", + "PD20", "PD21", "PD22", "PD23"; + allwinner,function = "emac"; + allwinner,drive = <SUN4I_PINCTRL_40_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; }; ahb_rst: reset@1c202c0 { @@ -620,5 +639,19 @@ #address-cells = <1>; #size-cells = <0>; }; + + emac: ethernet@01c30000 { + compatible = "allwinner,sun50i-a64-emac"; + reg = <0x01c30000 0x2000>, <0x01c00030 0x4>; + reg-names = "emac", "syscon"; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + resets = <&ahb_rst 17>; + reset-names = "ahb"; + clocks = <&bus_gates 17>; + clock-names = "ahb"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; }; }; diff --git a/arch/arm/dts/sun5i-a10s.dtsi b/arch/arm/dts/sun5i-a10s.dtsi index bddd0de88af..a5f8855389a 100644 --- a/arch/arm/dts/sun5i-a10s.dtsi +++ b/arch/arm/dts/sun5i-a10s.dtsi @@ -241,6 +241,20 @@ allwinner,drive = <SUN4I_PINCTRL_30_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; + + nand_cs2_pins_a: nand_cs@2 { + allwinner,pins = "PC17"; + allwinner,function = "nand0"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + nand_cs3_pins_a: nand_cs@3 { + allwinner,pins = "PC18"; + allwinner,function = "nand0"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; }; &sram_a { diff --git a/arch/arm/dts/sun5i-a13-olinuxino.dts b/arch/arm/dts/sun5i-a13-olinuxino.dts index b3c234c65ea..30e069a6cf4 100644 --- a/arch/arm/dts/sun5i-a13-olinuxino.dts +++ b/arch/arm/dts/sun5i-a13-olinuxino.dts @@ -155,6 +155,21 @@ status = "okay"; }; +&nfc { + pinctrl-names = "default"; + pinctrl-0 = <&nand_pins_a &nand_cs0_pins_a &nand_rb0_pins_a>; + status = "okay"; + + nand@0 { + #address-cells = <2>; + #size-cells = <2>; + reg = <0>; + allwinner,rb = <0>; + nand-ecc-mode = "hw"; + allwinner,randomize; + }; +}; + &ohci0 { status = "okay"; }; diff --git a/arch/arm/dts/sun5i-r8-chip.dts b/arch/arm/dts/sun5i-r8-chip.dts index 6ad19e272f4..b1b62d51164 100644 --- a/arch/arm/dts/sun5i-r8-chip.dts +++ b/arch/arm/dts/sun5i-r8-chip.dts @@ -142,6 +142,21 @@ status = "okay"; }; +&nfc { + pinctrl-names = "default"; + pinctrl-0 = <&nand_pins_a &nand_cs0_pins_a &nand_rb0_pins_a>; + status = "okay"; + + nand@0 { + #address-cells = <2>; + #size-cells = <2>; + reg = <0>; + allwinner,rb = <0>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + }; +}; + &ohci0 { status = "okay"; }; diff --git a/arch/arm/dts/sun5i.dtsi b/arch/arm/dts/sun5i.dtsi index 59a9426e3bd..87e535301a6 100644 --- a/arch/arm/dts/sun5i.dtsi +++ b/arch/arm/dts/sun5i.dtsi @@ -356,6 +356,17 @@ #dma-cells = <2>; }; + nfc: nand@01c03000 { + compatible = "allwinner,sun4i-a10-nand"; + reg = <0x01c03000 0x1000>; + interrupts = <37>; + clocks = <&ahb_gates 13>, <&nand_clk>; + clock-names = "ahb", "mod"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + spi0: spi@01c05000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c05000 0x1000>; @@ -548,6 +559,44 @@ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; }; + nand_pins_a: nand_base0@0 { + allwinner,pins = "PC0", "PC1", "PC2", + "PC5", "PC8", "PC9", "PC10", + "PC11", "PC12", "PC13", "PC14", + "PC15"; + allwinner,function = "nand0"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + nand_cs0_pins_a: nand_cs@0 { + allwinner,pins = "PC4"; + allwinner,function = "nand0"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + nand_cs1_pins_a: nand_cs@1 { + allwinner,pins = "PC3"; + allwinner,function = "nand0"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + nand_rb0_pins_a: nand_rb@0 { + allwinner,pins = "PC6"; + allwinner,function = "nand0"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + nand_rb1_pins_a: nand_rb@1 { + allwinner,pins = "PC7"; + allwinner,function = "nand0"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + uart3_pins_a: uart3@0 { allwinner,pins = "PG9", "PG10"; allwinner,function = "uart3"; diff --git a/arch/arm/dts/sun8i-h3-orangepi-2.dts b/arch/arm/dts/sun8i-h3-orangepi-2.dts index f93f5d1695c..d3f8f550a22 100644 --- a/arch/arm/dts/sun8i-h3-orangepi-2.dts +++ b/arch/arm/dts/sun8i-h3-orangepi-2.dts @@ -184,3 +184,16 @@ usb1_vbus-supply = <®_usb1_vbus>; status = "okay"; }; + +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + phy-mode = "rgmii"; + phy = <&phy1>; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + diff --git a/arch/arm/dts/sun8i-h3-orangepi-lite.dts b/arch/arm/dts/sun8i-h3-orangepi-lite.dts new file mode 100644 index 00000000000..ac7174914e6 --- /dev/null +++ b/arch/arm/dts/sun8i-h3-orangepi-lite.dts @@ -0,0 +1,178 @@ +/* + * Copyright (C) 2016 Hans de Goede <hdegoede@redhat.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> + +/ { + model = "Xunlong Orange Pi Lite"; + compatible = "xunlong,orangepi-lite", "allwinner,sun8i-h3"; + + aliases { + /* The H3 emac is not used so the wifi is ethernet0 */ + ethernet1 = &rtl8189ftv; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_opc>, <&leds_r_opc>; + + pwr_led { + label = "orangepi:green:pwr"; + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + status_led { + label = "orangepi:red:status"; + gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; + }; + }; + + r_gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&sw_r_opc>; + + sw4 { + label = "sw4"; + linux,code = <BTN_0>; + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&ir { + pinctrl-names = "default"; + pinctrl-0 = <&ir_pins_a>; + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + cd-inverted; + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_a>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + non-removable; + status = "okay"; + + /* + * Explicitly define the sdio device, so that we can add an ethernet + * alias for it (which e.g. makes u-boot set a mac-address). + */ + rtl8189ftv: sdio_wifi@1 { + reg = <1>; + }; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +&pio { + leds_opc: led_pins@0 { + allwinner,pins = "PA15"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; +}; + +&r_pio { + leds_r_opc: led_pins@0 { + allwinner,pins = "PL10"; + allwinner,function = "gpio_out"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + + sw_r_opc: key_pins@0 { + allwinner,pins = "PL3"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + /* USB VBUS is always on */ + status = "okay"; +}; diff --git a/arch/arm/dts/sun8i-h3-orangepi-one.dts b/arch/arm/dts/sun8i-h3-orangepi-one.dts index 0adf932fd92..8df5c74f04c 100644 --- a/arch/arm/dts/sun8i-h3-orangepi-one.dts +++ b/arch/arm/dts/sun8i-h3-orangepi-one.dts @@ -94,6 +94,17 @@ status = "okay"; }; +&emac { + phy = <&phy1>; + phy-mode = "mii"; + allwinner,use-internal-phy; + allwinner,leds-active-low; + status = "okay"; + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; diff --git a/arch/arm/dts/sun8i-h3-orangepi-pc-plus.dts b/arch/arm/dts/sun8i-h3-orangepi-pc-plus.dts new file mode 100644 index 00000000000..9a8cdd46e77 --- /dev/null +++ b/arch/arm/dts/sun8i-h3-orangepi-pc-plus.dts @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2016 Hans de Goede <hdegoede@redhat.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* The Orange Pi PC Plus is an extended version of the regular PC */ +#include "sun8i-h3-orangepi-pc.dts" + +/ { + model = "Xunlong Orange Pi PC / PC Plus"; + + aliases { + /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ + ethernet1 = &rtl8189ftv; + }; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_a>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + non-removable; + status = "okay"; + + /* + * Explicitly define the sdio device, so that we can add an ethernet + * alias for it (which e.g. makes u-boot set a mac-address). + */ + rtl8189ftv: sdio_wifi@1 { + reg = <1>; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc3v3>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&mmc2_8bit_pins { + /* Increase drive strength for DDR modes */ + allwinner,drive = <SUN4I_PINCTRL_40_MA>; + /* eMMC is missing pull-ups */ + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; +}; diff --git a/arch/arm/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/dts/sun8i-h3-orangepi-pc.dts index 30ccca019dd..0a74a9193bb 100644 --- a/arch/arm/dts/sun8i-h3-orangepi-pc.dts +++ b/arch/arm/dts/sun8i-h3-orangepi-pc.dts @@ -173,3 +173,15 @@ /* USB VBUS is always on */ status = "okay"; }; + +&emac { + phy = <&phy1>; + phy-mode = "mii"; + allwinner,use-internal-phy; + allwinner,leds-active-low; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; diff --git a/arch/arm/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/dts/sun8i-h3-orangepi-plus.dts index 900ec4fc8c8..28f74f6ffd1 100644 --- a/arch/arm/dts/sun8i-h3-orangepi-plus.dts +++ b/arch/arm/dts/sun8i-h3-orangepi-plus.dts @@ -40,26 +40,13 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -/dts-v1/; -#include "sun8i-h3.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/pinctrl/sun4i-a10.h> +/* The Orange Pi Plus is an extended version of the Orange Pi 2 */ +#include "sun8i-h3-orangepi-2.dts" / { - model = "Xunlong Orange Pi Plus"; + model = "Xunlong Orange Pi Plus / Plus 2 / Plus 2E"; compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3"; - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - reg_usb3_vbus: usb3-vbus { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -71,75 +58,42 @@ enable-active-high; gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>; }; +}; - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&leds_opc>; - - status_led { - label = "status:red:user"; - gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; - }; - }; - - r_leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&leds_r_opc>; - - tx { - label = "pwr:green:user"; - gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - }; - - r_gpio_keys { - compatible = "gpio-keys"; - input-name = "sw4"; - - pinctrl-names = "default"; - pinctrl-0 = <&sw_r_opc>; +&ehci2 { + status = "okay"; +}; - sw4@0 { - label = "sw4"; - linux,code = <BTN_0>; - gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; - }; - }; +&ehci3 { + status = "okay"; }; -&pio { - leds_opc: led_pins@0 { - allwinner,pins = "PA15"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc3v3>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; }; -&r_pio { - leds_r_opc: led_pins@0 { - allwinner,pins = "PL10"; - allwinner,function = "gpio_out"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; +&mmc2_8bit_pins { + /* Increase drive strength for DDR modes */ + allwinner,drive = <SUN4I_PINCTRL_40_MA>; + /* eMMC is missing pull-ups */ + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; +}; - sw_r_opc: key_pins@0 { - allwinner,pins = "PL03"; - allwinner,function = "gpio_in"; - allwinner,drive = <SUN4I_PINCTRL_10_MA>; - allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; - }; +&ohci1 { + status = "okay"; }; -&ehci1 { +&ohci2 { status = "okay"; }; -&ehci3 { +&ohci3 { status = "okay"; }; @@ -152,33 +106,6 @@ }; }; -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ - cd-inverted; - status = "okay"; -}; - -®_usb1_vbus { - gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>; - status = "okay"; -}; - -&uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins_a>; - status = "okay"; -}; - -&usb1_vbus_pin_a { - allwinner,pins = "PG13"; -}; - &usbphy { - usb1_vbus-supply = <®_usb1_vbus>; usb3_vbus-supply = <®_usb3_vbus>; - status = "okay"; }; diff --git a/arch/arm/dts/sun8i-h3.dtsi b/arch/arm/dts/sun8i-h3.dtsi index c2f63c50501..84e52b9cdb2 100644 --- a/arch/arm/dts/sun8i-h3.dtsi +++ b/arch/arm/dts/sun8i-h3.dtsi @@ -48,6 +48,10 @@ / { interrupt-parent = <&gic>; + aliases { + ethernet0 = <&emac>; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -501,6 +505,17 @@ interrupt-controller; #interrupt-cells = <3>; + rgmii_pins: rgmii_pins { + allwinner,pins = "PD0", "PD1", "PD2", "PD3", + "PD4", "PD5", "PD7", + "PD8", "PD9", "PD10", + "PD12", "PD13", "PD15", + "PD16", "PD17"; + allwinner,function = "emac"; + allwinner,drive = <SUN4I_PINCTRL_40_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + uart0_pins_a: uart0@0 { allwinner,pins = "PA4", "PA5"; allwinner,function = "uart0"; @@ -530,6 +545,16 @@ allwinner,drive = <SUN4I_PINCTRL_30_MA>; allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; + + mmc2_8bit_pins: mmc2_8bit { + allwinner,pins = "PC5", "PC6", "PC8", + "PC9", "PC10", "PC11", + "PC12", "PC13", "PC14", + "PC15", "PC16"; + allwinner,function = "mmc2"; + allwinner,drive = <SUN4I_PINCTRL_30_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; }; ahb_rst: reset@01c202c0 { @@ -616,6 +641,20 @@ status = "disabled"; }; + emac: ethernet@01c30000 { + compatible = "allwinner,sun8i-h3-emac"; + reg = <0x01c30000 0x2000>, <0x01c00030 0x4>; + reg-names = "emac", "syscon"; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + resets = <&ahb_rst 17>, <&ahb_rst 66>; + reset-names = "ahb", "ephy"; + clocks = <&bus_gates 17>, <&bus_gates 128>; + clock-names = "ahb", "ephy"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@01c81000 { compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c81000 0x1000>, diff --git a/arch/arm/dts/tegra186-p2771-0000-a02.dts b/arch/arm/dts/tegra186-p2771-0000-a02.dts new file mode 100644 index 00000000000..36a3c21a55d --- /dev/null +++ b/arch/arm/dts/tegra186-p2771-0000-a02.dts @@ -0,0 +1,32 @@ +/dts-v1/; + +#include "tegra186-p2771-0000.dtsi" + +/ { + model = "NVIDIA P2771-0000 A02"; + compatible = "nvidia,p2771-0000-a02", "nvidia,p2771-0000", "nvidia,tegra186"; + + sdhci@3400000 { + cd-gpios = <&gpio_main TEGRA_MAIN_GPIO(P, 6) GPIO_ACTIVE_LOW>; + power-gpios = <&gpio_main TEGRA_MAIN_GPIO(P, 5) GPIO_ACTIVE_HIGH>; + }; + + pcie-controller@10003000 { + status = "okay"; + + pci@1,0 { + status = "okay"; + nvidia,num-lanes = <2>; + }; + + pci@2,0 { + status = "disabled"; + nvidia,num-lanes = <1>; + }; + + pci@3,0 { + status = "okay"; + nvidia,num-lanes = <1>; + }; + }; +}; diff --git a/arch/arm/dts/tegra186-p2771-0000-b00.dts b/arch/arm/dts/tegra186-p2771-0000-b00.dts new file mode 100644 index 00000000000..0f1d0e83e80 --- /dev/null +++ b/arch/arm/dts/tegra186-p2771-0000-b00.dts @@ -0,0 +1,32 @@ +/dts-v1/; + +#include "tegra186-p2771-0000.dtsi" + +/ { + model = "NVIDIA P2771-0000 B00"; + compatible = "nvidia,p2771-0000-b00", "nvidia,p2771-0000", "nvidia,tegra186"; + + sdhci@3400000 { + cd-gpios = <&gpio_main TEGRA_MAIN_GPIO(P, 5) GPIO_ACTIVE_LOW>; + power-gpios = <&gpio_main TEGRA_MAIN_GPIO(P, 6) GPIO_ACTIVE_HIGH>; + }; + + pcie-controller@10003000 { + status = "okay"; + + pci@1,0 { + status = "okay"; + nvidia,num-lanes = <4>; + }; + + pci@2,0 { + status = "disabled"; + nvidia,num-lanes = <0>; + }; + + pci@3,0 { + status = "disabled"; + nvidia,num-lanes = <1>; + }; + }; +}; diff --git a/arch/arm/dts/tegra186-p2771-0000.dts b/arch/arm/dts/tegra186-p2771-0000.dts deleted file mode 100644 index 5f29ee45019..00000000000 --- a/arch/arm/dts/tegra186-p2771-0000.dts +++ /dev/null @@ -1,25 +0,0 @@ -/dts-v1/; - -#include "tegra186.dtsi" - -/ { - model = "NVIDIA P2771-0000"; - compatible = "nvidia,p2771-0000", "nvidia,tegra186"; - - chosen { - stdout-path = &uarta; - }; - - aliases { - sdhci0 = "/sdhci@3460000"; - }; - - memory { - reg = <0x0 0x80000000 0x0 0x60000000>; - }; - - sdhci@3460000 { - status = "okay"; - bus-width = <8>; - }; -}; diff --git a/arch/arm/dts/tegra186-p2771-0000.dtsi b/arch/arm/dts/tegra186-p2771-0000.dtsi new file mode 100644 index 00000000000..d867674fd04 --- /dev/null +++ b/arch/arm/dts/tegra186-p2771-0000.dtsi @@ -0,0 +1,72 @@ +#include "tegra186.dtsi" + +/ { + model = "NVIDIA P2771-0000"; + compatible = "nvidia,p2771-0000", "nvidia,tegra186"; + + chosen { + stdout-path = &uarta; + }; + + aliases { + sdhci0 = "/sdhci@3460000"; + sdhci1 = "/sdhci@3400000"; + i2c0 = "/bpmp/i2c"; + i2c1 = "/i2c@3160000"; + i2c2 = "/i2c@c240000"; + i2c3 = "/i2c@3180000"; + i2c4 = "/i2c@3190000"; + i2c5 = "/i2c@31c0000"; + i2c6 = "/i2c@c250000"; + i2c7 = "/i2c@31e0000"; + }; + + memory { + reg = <0x0 0x80000000 0x0 0x60000000>; + }; + + i2c@3160000 { + status = "okay"; + }; + + i2c@3180000 { + status = "okay"; + }; + + i2c@3190000 { + status = "okay"; + }; + + i2c@31c0000 { + status = "okay"; + }; + + sdhci@3400000 { + status = "okay"; + wp-gpios = <&gpio_main TEGRA_MAIN_GPIO(P, 4) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + }; + + sdhci@3460000 { + status = "okay"; + bus-width = <8>; + }; + + i2c@c240000 { + status = "okay"; + }; + + i2c@c250000 { + status = "okay"; + }; + + i2c@31e0000 { + status = "okay"; + }; + + bpmp { + i2c { + status = "okay"; + }; + }; +}; diff --git a/arch/arm/dts/tegra186.dtsi b/arch/arm/dts/tegra186.dtsi index fce34fa6500..d9e7f0351f5 100644 --- a/arch/arm/dts/tegra186.dtsi +++ b/arch/arm/dts/tegra186.dtsi @@ -1,14 +1,18 @@ #include "skeleton.dtsi" -#include <dt-bindings/gpio/tegra-gpio.h> +#include <dt-bindings/clock/tegra186-clock.h> +#include <dt-bindings/gpio/tegra186-gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/mailbox/tegra-hsp.h> +#include <dt-bindings/mailbox/tegra186-hsp.h> +#include <dt-bindings/power/tegra186-powergate.h> +#include <dt-bindings/reset/tegra186-reset.h> / { compatible = "nvidia,tegra186"; + interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; - gpio@2200000 { + gpio_main: gpio@2200000 { compatible = "nvidia,tegra186-gpio"; reg-names = "security", "gpio"; reg = @@ -34,26 +38,154 @@ status = "disabled"; }; + gen1_i2c: i2c@3160000 { + compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; + reg = <0x0 0x3160000 0x0 0x100>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp TEGRA186_CLK_I2C1>; + clock-names = "i2c"; + resets = <&bpmp TEGRA186_RESET_I2C1>; + reset-names = "i2c"; + status = "disabled"; + }; + + cam_i2c: i2c@3180000 { + compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; + reg = <0x0 0x3180000 0x0 0x100>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp TEGRA186_CLK_I2C3>; + clock-names = "i2c"; + resets = <&bpmp TEGRA186_RESET_I2C3>; + reset-names = "i2c"; + status = "disabled"; + }; + + dp_aux_ch1_i2c: i2c@3190000 { + compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; + reg = <0x0 0x3190000 0x0 0x100>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp TEGRA186_CLK_I2C4>; + clock-names = "i2c"; + resets = <&bpmp TEGRA186_RESET_I2C4>; + reset-names = "i2c"; + status = "disabled"; + }; + + dp_aux_ch0_i2c: i2c@31b0000 { + compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; + reg = <0x0 0x31b0000 0x0 0x100>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp TEGRA186_CLK_I2C6>; + clock-names = "i2c"; + resets = <&bpmp TEGRA186_RESET_I2C6>; + reset-names = "i2c"; + status = "disabled"; + }; + + gen7_i2c: i2c@31c0000 { + compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; + reg = <0x0 0x31c0000 0x0 0x100>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp TEGRA186_CLK_I2C7>; + clock-names = "i2c"; + resets = <&bpmp TEGRA186_RESET_I2C7>; + reset-names = "i2c"; + status = "disabled"; + }; + + gen9_i2c: i2c@31e0000 { + compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; + reg = <0x0 0x31e0000 0x0 0x100>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp TEGRA186_CLK_I2C9>; + clock-names = "i2c"; + resets = <&bpmp TEGRA186_RESET_I2C9>; + reset-names = "i2c"; + status = "disabled"; + }; + + sdhci@3400000 { + compatible = "nvidia,tegra186-sdhci"; + reg = <0x0 0x03400000 0x0 0x200>; + resets = <&bpmp TEGRA186_RESET_SDMMC1>; + reset-names = "sdmmc"; + clocks = <&bpmp TEGRA186_CLK_SDMMC1>; + clock-names = "sdmmc"; + interrupts = <GIC_SPI 62 0x04>; + status = "disabled"; + }; + sdhci@3460000 { compatible = "nvidia,tegra186-sdhci"; reg = <0x0 0x03460000 0x0 0x200>; + resets = <&bpmp TEGRA186_RESET_SDMMC4>; + reset-names = "sdmmc"; + clocks = <&bpmp TEGRA186_CLK_SDMMC4>; + clock-names = "sdmmc"; interrupts = <GIC_SPI 31 0x04>; status = "disabled"; }; + gic: interrupt-controller@3881000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x3881000 0x0 0x1000>, + <0x0 0x3882000 0x0 0x2000>, + <0x0 0x3884000 0x0 0x2000>, + <0x0 0x3886000 0x0 0x2000>; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + interrupt-parent = <&gic>; + }; + hsp: hsp@3c00000 { compatible = "nvidia,tegra186-hsp"; reg = <0x0 0x03c00000 0x0 0xa0000>; interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; - nvidia,num-SM = <0x8>; - nvidia,num-AS = <0x2>; - nvidia,num-SS = <0x2>; - nvidia,num-DB = <0x7>; - nvidia,num-SI = <0x8>; - #mbox-cells = <1>; + interrupt-names = "doorbell"; + #mbox-cells = <2>; + }; + + gen2_i2c: i2c@c240000 { + compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; + reg = <0x0 0xc240000 0x0 0x100>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp TEGRA186_CLK_I2C2>; + clock-names = "i2c"; + resets = <&bpmp TEGRA186_RESET_I2C2>; + reset-names = "i2c"; + status = "disabled"; + }; + + gen8_i2c: i2c@c250000 { + compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; + reg = <0x0 0xc250000 0x0 0x100>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp TEGRA186_CLK_I2C8>; + clock-names = "i2c"; + resets = <&bpmp TEGRA186_RESET_I2C8>; + reset-names = "i2c"; + status = "disabled"; }; - gpio@c2f0000 { + gpio_aon: gpio@c2f0000 { compatible = "nvidia,tegra186-gpio-aon"; reg-names = "security", "gpio"; reg = @@ -66,4 +198,124 @@ interrupt-controller; #interrupt-cells = <2>; }; + + pcie-controller@10003000 { + compatible = "nvidia,tegra186-pcie"; + device_type = "pci"; + reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ + 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ + 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ + reg-names = "pads", "afi", "cs"; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, /* MSI interrupt */ + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; /* Wake interrupt */ + interrupt-names = "intr", "msi", "wake"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + + bus-range = <0x00 0xff>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ + 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ + 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ + 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ + 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07f00000 /* non-prefetchable memory (127 MiB) */ + 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ + + clocks = <&bpmp TEGRA186_CLK_PCIE>, + <&bpmp TEGRA186_CLK_AFI>; + clock-names = "pex", "afi"; + resets = <&bpmp TEGRA186_RESET_PCIE>, + <&bpmp TEGRA186_RESET_AFI>, + <&bpmp TEGRA186_RESET_PCIEXCLK>; + reset-names = "pex", "afi", "pcie_x"; + power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; + status = "disabled"; + + pci@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; + reg = <0x000800 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <2>; + }; + + pci@2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; + reg = <0x001000 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <1>; + }; + + pci@3,0 { + device_type = "pci"; + assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; + reg = <0x001800 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <1>; + }; + }; + + sysram@30000000 { + compatible = "nvidia,tegra186-sysram", "mmio-sram"; + reg = <0x0 0x30000000 0x0 0x50000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; + + sysram_cpu_bpmp_tx: shmem@4e000 { + compatible = "nvidia,tegra186-bpmp-shmem"; + reg = <0x0 0x4e000 0x0 0x1000>; + }; + + sysram_cpu_bpmp_rx: shmem@4f000 { + compatible = "nvidia,tegra186-bpmp-shmem"; + reg = <0x0 0x4f000 0x0 0x1000>; + }; + }; + + bpmp: bpmp { + compatible = "nvidia,tegra186-bpmp"; + mboxes = <&hsp HSP_MBOX_TYPE_DB HSP_DB_MASTER_BPMP>; + /* + * In theory, these references, and the configuration in the + * node these reference point at, are board-specific, since + * they depend on the BCT's memory carve-out setup, the + * firmware that's actually loaded onto the BPMP, etc. However, + * in practice, all boards are likely to use identical values. + */ + shmem = <&sysram_cpu_bpmp_tx &sysram_cpu_bpmp_rx>; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + + bpmp_i2c: i2c { + compatible = "nvidia,tegra186-bpmp-i2c"; + nvidia,bpmp = <&bpmp>; + nvidia,bpmp-bus-id = <5>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; }; diff --git a/arch/arm/dts/uniphier-proxstream2-gentil.dts b/arch/arm/dts/uniphier-proxstream2-gentil.dts index 61f61641afc..117570352f8 100644 --- a/arch/arm/dts/uniphier-proxstream2-gentil.dts +++ b/arch/arm/dts/uniphier-proxstream2-gentil.dts @@ -19,13 +19,13 @@ }; chosen { - stdout-path = "serial2:115200n8"; + stdout-path = "serial0:115200n8"; }; aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; + serial0 = &serial2; + serial1 = &serial0; + serial2 = &serial1; i2c0 = &i2c0; i2c2 = &i2c2; i2c4 = &i2c4; diff --git a/arch/arm/dts/uniphier-proxstream2-vodka.dts b/arch/arm/dts/uniphier-proxstream2-vodka.dts index 3d5b3007160..928a0928fd1 100644 --- a/arch/arm/dts/uniphier-proxstream2-vodka.dts +++ b/arch/arm/dts/uniphier-proxstream2-vodka.dts @@ -19,13 +19,13 @@ }; chosen { - stdout-path = "serial2:115200n8"; + stdout-path = "serial0:115200n8"; }; aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; + serial0 = &serial2; + serial1 = &serial0; + serial2 = &serial1; i2c0 = &i2c0; i2c4 = &i2c4; i2c5 = &i2c5; diff --git a/arch/arm/dts/zynqmp-clk.dtsi b/arch/arm/dts/zynqmp-clk.dtsi index 34189097592..0918c686d70 100644 --- a/arch/arm/dts/zynqmp-clk.dtsi +++ b/arch/arm/dts/zynqmp-clk.dtsi @@ -13,6 +13,7 @@ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; + u-boot,dm-pre-reloc; }; clk125: clk125 { diff --git a/arch/arm/dts/zynqmp-ep108-clk.dtsi b/arch/arm/dts/zynqmp-ep108-clk.dtsi index 48bb426dafa..b3ce0de549e 100644 --- a/arch/arm/dts/zynqmp-ep108-clk.dtsi +++ b/arch/arm/dts/zynqmp-ep108-clk.dtsi @@ -13,6 +13,7 @@ compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; + u-boot,dm-pre-reloc; }; i2c_clk: i2c_clk { diff --git a/arch/arm/imx-common/ddrmc-vf610.c b/arch/arm/imx-common/ddrmc-vf610.c index daf3c7ebfaf..9bc56f6ac13 100644 --- a/arch/arm/imx-common/ddrmc-vf610.c +++ b/arch/arm/imx-common/ddrmc-vf610.c @@ -212,7 +212,7 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings, cr_setting++; } - /* perform default PHY settings (may be overriden by custom settings */ + /* perform default PHY settings (may be overridden by custom settings */ phy_setting = default_phy_settings; while (phy_setting->phy_rnum >= 0) { writel(phy_setting->setting, diff --git a/arch/arm/include/asm/arch-am33xx/sys_proto.h b/arch/arm/include/asm/arch-am33xx/sys_proto.h index 8f573d2d02a..ed1a46c2e71 100644 --- a/arch/arm/include/asm/arch-am33xx/sys_proto.h +++ b/arch/arm/include/asm/arch-am33xx/sys_proto.h @@ -25,9 +25,8 @@ void ddr_pll_config(unsigned int ddrpll_M); void sdelay(unsigned long); -struct gpmc_cs; void gpmc_init(void); -void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, +void enable_gpmc_cs_config(const u32 *gpmc_config, const struct gpmc_cs *cs, u32 base, u32 size); void omap_nand_switch_ecc(uint32_t, uint32_t); diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 44fe0c00953..b0ad4b46268 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -149,43 +149,43 @@ #define CONFIG_ARM_ERRATA_833471 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 -#elif defined(CONFIG_LS1043A) -#define CONFIG_MAX_CPUS 4 +#elif defined(CONFIG_FSL_LSCH2) #define CONFIG_SYS_CACHELINE_SIZE 64 -#define CONFIG_SYS_FMAN_V3 -#define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_NUM_FM1_DTSEC 7 -#define CONFIG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 #define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_SYS_CCSRBAR_DEFAULT 0x01000000 #define CONFIG_SYS_FSL_SEC_COMPAT 5 #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ -#define CONFIG_SYS_FSL_OCRAM_SIZE 0x200000 /* 2 MiB */ -#define CONFIG_SYS_FSL_DDR_BE -#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) -#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE +#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */ +#define CONFIG_SYS_CCSRBAR_DEFAULT 0x01000000 -#define CONFIG_SYS_FSL_CCSR_GUR_BE #define CONFIG_SYS_FSL_CCSR_SCFG_BE -#define CONFIG_SYS_FSL_IFC_BE #define CONFIG_SYS_FSL_ESDHC_BE #define CONFIG_SYS_FSL_WDOG_BE #define CONFIG_SYS_FSL_DSPI_BE #define CONFIG_SYS_FSL_QSPI_BE +#define CONFIG_SYS_FSL_CCSR_GUR_BE #define CONFIG_SYS_FSL_PEX_LUT_BE +#define CONFIG_SYS_FSL_SEC_BE + +#define CONFIG_SYS_FSL_SRDS_1 +/* SoC related */ +#ifdef CONFIG_LS1043A +#define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_FMAN_V3 +#define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_NUM_FM1_DTSEC 7 +#define CONFIG_SYS_NUM_FM1_10GEC 1 +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 +#define CONFIG_SYS_FSL_DDR_BE +#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE #define QE_MURAM_SIZE 0x6000UL #define MAX_QE_RISC 1 #define QE_NUM_OF_SNUM 28 -#define SRDS_MAX_LANES 4 -#define CONFIG_SYS_FSL_SRDS_1 -#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" - +#define CONFIG_SYS_FSL_IFC_BE #define CONFIG_SYS_FSL_SFP_VER_3_2 #define CONFIG_SYS_FSL_SEC_MON_BE -#define CONFIG_SYS_FSL_SEC_BE #define CONFIG_SYS_FSL_SFP_BE #define CONFIG_SYS_FSL_SRK_LE #define CONFIG_KEY_REVOCATION @@ -205,32 +205,40 @@ #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #elif defined(CONFIG_LS1012A) #define CONFIG_MAX_CPUS 1 -#define CONFIG_SYS_CACHELINE_SIZE 64 -#define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_SYS_CCSRBAR_DEFAULT 0x01000000 -#define CONFIG_SYS_FSL_SEC_COMPAT 5 #undef CONFIG_SYS_FSL_DDRC_ARM_GEN3 -#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ -#define CONFIG_SYS_FSL_OCRAM_SIZE 0x200000 /* 2 MiB */ - #define GICD_BASE 0x01401000 #define GICC_BASE 0x01402000 +#elif defined(CONFIG_LS1046A) +#define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_FMAN_V3 +#define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_NUM_FM1_DTSEC 8 +#define CONFIG_SYS_NUM_FM1_10GEC 2 +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 +#define CONFIG_SYS_FSL_DDR_BE +#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) +#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE -#define CONFIG_SYS_FSL_CCSR_GUR_BE -#define CONFIG_SYS_FSL_CCSR_SCFG_BE -#define CONFIG_SYS_FSL_ESDHC_BE -#define CONFIG_SYS_FSL_WDOG_BE -#define CONFIG_SYS_FSL_DSPI_BE -#define CONFIG_SYS_FSL_QSPI_BE -#define CONFIG_SYS_FSL_PEX_LUT_BE +#define CONFIG_SYS_FSL_SRDS_2 +#define CONFIG_SYS_FSL_IFC_BE +#define CONFIG_SYS_FSL_SFP_VER_3_2 +#define CONFIG_SYS_FSL_SNVS_LE +#define CONFIG_SYS_FSL_SFP_BE +#define CONFIG_SYS_FSL_SRK_LE +#define CONFIG_KEY_REVOCATION -#define SRDS_MAX_LANES 4 -#define CONFIG_SYS_FSL_SRDS_1 -#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" -#define CONFIG_SYS_FSL_SEC_BE +/* SMMU Defintions */ +#define SMMU_BASE 0x09000000 + +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE 0x01410000 +#define GICC_BASE 0x01420000 + +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #else #error SoC not defined #endif +#endif #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index 197b0eb5a53..e2d96a1b781 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -13,35 +13,14 @@ static struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(LS2045A, LS2045A, 4), CPU_TYPE_ENTRY(LS1043A, LS1043A, 4), CPU_TYPE_ENTRY(LS1023A, LS1023A, 2), + CPU_TYPE_ENTRY(LS1046A, LS1046A, 4), + CPU_TYPE_ENTRY(LS1026A, LS1026A, 2), CPU_TYPE_ENTRY(LS2040A, LS2040A, 4), CPU_TYPE_ENTRY(LS1012A, LS1012A, 1), }; #ifndef CONFIG_SYS_DCACHE_OFF -#define SECTION_SHIFT_L0 39UL -#define SECTION_SHIFT_L1 30UL -#define SECTION_SHIFT_L2 21UL -#define BLOCK_SIZE_L0 0x8000000000 -#define BLOCK_SIZE_L1 0x40000000 -#define BLOCK_SIZE_L2 0x200000 -#define NUM_OF_ENTRY 512 -#define TCR_EL2_PS_40BIT (2 << 16) - -#define LAYERSCAPE_VA_BITS (40) -#define LAYERSCAPE_TCR (TCR_TG0_4K | \ - TCR_EL2_PS_40BIT | \ - TCR_SHARED_NON | \ - TCR_ORGN_NC | \ - TCR_IRGN_NC | \ - TCR_T0SZ(LAYERSCAPE_VA_BITS)) -#define LAYERSCAPE_TCR_FINAL (TCR_TG0_4K | \ - TCR_EL2_PS_40BIT | \ - TCR_SHARED_OUTER | \ - TCR_ORGN_WBWA | \ - TCR_IRGN_WBWA | \ - TCR_T0SZ(LAYERSCAPE_VA_BITS)) - #ifdef CONFIG_FSL_LSCH3 #define CONFIG_SYS_FSL_CCSR_BASE 0x00000000 #define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000 @@ -101,174 +80,261 @@ static struct cpu_type cpu_type_list[] = { #define CONFIG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */ #endif -struct sys_mmu_table { - u64 virt_addr; - u64 phys_addr; - u64 size; - u64 memory_type; - u64 attribute; -}; - -struct table_info { - u64 *ptr; - u64 table_base; - u64 entry_size; -}; - -static const struct sys_mmu_table early_mmu_table[] = { +#define EARLY_PGTABLE_SIZE 0x5000 +static struct mm_region early_map[] = { #ifdef CONFIG_FSL_LSCH3 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, - CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, + CONFIG_SYS_FSL_CCSR_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, - CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE }, + CONFIG_SYS_FSL_OCRAM_SIZE, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE + }, { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1, - CONFIG_SYS_FSL_QSPI_SIZE1, MT_NORMAL, PTE_BLOCK_NON_SHARE}, + CONFIG_SYS_FSL_QSPI_SIZE1, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE}, /* For IFC Region #1, only the first 4MB is cache-enabled */ { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1, - CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PTE_BLOCK_NON_SHARE }, + CONFIG_SYS_FSL_IFC_SIZE1_1, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE + }, { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1, CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1, - MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE }, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE + }, { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1, - CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE }, + CONFIG_SYS_FSL_IFC_SIZE1, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE + }, { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, - CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, - PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, + CONFIG_SYS_FSL_DRAM_SIZE1, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */ { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2, - MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE }, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE + }, { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, - CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, + CONFIG_SYS_FSL_DCSR_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, - CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, - PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, + CONFIG_SYS_FSL_DRAM_SIZE2, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, #elif defined(CONFIG_FSL_LSCH2) { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, - CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, + CONFIG_SYS_FSL_CCSR_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, - CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE }, + CONFIG_SYS_FSL_OCRAM_SIZE, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE + }, { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, - CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, + CONFIG_SYS_FSL_DCSR_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE, - CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE }, + CONFIG_SYS_FSL_QSPI_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE + }, { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, - CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE }, + CONFIG_SYS_FSL_IFC_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE + }, { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, - CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, - PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, + CONFIG_SYS_FSL_DRAM_SIZE1, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, - CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, - PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, + CONFIG_SYS_FSL_DRAM_SIZE2, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, #endif + {}, /* list terminator */ }; -static const struct sys_mmu_table final_mmu_table[] = { +static struct mm_region final_map[] = { #ifdef CONFIG_FSL_LSCH3 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, - CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, + CONFIG_SYS_FSL_CCSR_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, - CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE }, + CONFIG_SYS_FSL_OCRAM_SIZE, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE + }, { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, - CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, - PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, + CONFIG_SYS_FSL_DRAM_SIZE1, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1, - CONFIG_SYS_FSL_QSPI_SIZE1, MT_NORMAL, PTE_BLOCK_NON_SHARE}, + CONFIG_SYS_FSL_QSPI_SIZE1, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE + }, { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2, - CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, + CONFIG_SYS_FSL_QSPI_SIZE2, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2, - CONFIG_SYS_FSL_IFC_SIZE2, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE }, + CONFIG_SYS_FSL_IFC_SIZE2, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE + }, { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, - CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, + CONFIG_SYS_FSL_DCSR_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE, - CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE, - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, + CONFIG_SYS_FSL_MC_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE, - CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE, - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, + CONFIG_SYS_FSL_NI_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, /* For QBMAN portal, only the first 64MB is cache-enabled */ { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, - CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL, - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS }, + CONFIG_SYS_FSL_QBMAN_SIZE_1, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS + }, { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1, CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1, - MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, - CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, + CONFIG_SYS_PCIE1_PHYS_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, - CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, + CONFIG_SYS_PCIE2_PHYS_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, - CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, + CONFIG_SYS_PCIE3_PHYS_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, #ifdef CONFIG_LS2080A { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, - CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, + CONFIG_SYS_PCIE4_PHYS_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, #endif { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE, - CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE, - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, + CONFIG_SYS_FSL_WRIOP1_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE, - CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE, - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, + CONFIG_SYS_FSL_AIOP1_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE, - CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE, - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, + CONFIG_SYS_FSL_PEBUF_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, - CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, - PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, + CONFIG_SYS_FSL_DRAM_SIZE2, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, #elif defined(CONFIG_FSL_LSCH2) { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE, - CONFIG_SYS_FSL_BOOTROM_SIZE, MT_DEVICE_NGNRNE, - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, + CONFIG_SYS_FSL_BOOTROM_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE, - CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, + CONFIG_SYS_FSL_CCSR_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, - CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE }, + CONFIG_SYS_FSL_OCRAM_SIZE, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE + }, { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE, - CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, + CONFIG_SYS_FSL_DCSR_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE, - CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE, - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, + CONFIG_SYS_FSL_QSPI_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, - CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE }, + CONFIG_SYS_FSL_IFC_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE + }, { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, - CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, - PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, + CONFIG_SYS_FSL_DRAM_SIZE1, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE, - CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE, - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, + CONFIG_SYS_FSL_QBMAN_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, - CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, - PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, + CONFIG_SYS_FSL_DRAM_SIZE2, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, - CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, + CONFIG_SYS_PCIE1_PHYS_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, - CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, + CONFIG_SYS_PCIE2_PHYS_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, - CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, - PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, + CONFIG_SYS_PCIE3_PHYS_SIZE, + PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3, - CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL, - PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, + CONFIG_SYS_FSL_DRAM_SIZE3, + PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS + }, #endif -}; +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE + {}, /* space holder for secure mem */ #endif + {}, +}; +#endif /* !CONFIG_SYS_DCACHE_OFF */ int fsl_qoriq_core_to_cluster(unsigned int core); u32 cpu_mask(void); diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h index 487cba80803..e1b3f44d853 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h @@ -140,6 +140,7 @@ enum srds_prtcl { enum srds { FSL_SRDS_1 = 0, + FSL_SRDS_2 = 1, }; #endif @@ -150,7 +151,7 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device); enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane); int is_serdes_prtcl_valid(int serdes, u32 prtcl); -#ifdef CONFIG_LS1043A +#ifdef CONFIG_FSL_LSCH2 const char *serdes_clock_to_string(u32 clock); int get_serdes_protocol(void); #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 8b8a7c15bdd..95a42935cac 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -31,9 +31,9 @@ #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600) #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500) #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600) -#define CONFIG_SYS_LS1043A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000) -#define CONFIG_SYS_LS1043A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000) -#define CONFIG_SYS_LS1043A_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) +#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000) +#define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000) +#define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) @@ -94,6 +94,7 @@ #define TY_ITYP_VER_A7 0x1 #define TY_ITYP_VER_A53 0x2 #define TY_ITYP_VER_A57 0x3 +#define TY_ITYP_VER_A72 0x4 #define TP_CLUSTER_EOC 0xc0000000 /* end of clusters */ #define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */ @@ -227,6 +228,8 @@ struct ccsr_gur { #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK 0x3f #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK 0xffff0000 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT 16 +#define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK 0x0000ffff +#define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT 0 #define RCW_SB_EN_REG_INDEX 7 #define RCW_SB_EN_MASK 0x00200000 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 3ad46eb3714..93e26c1d7f4 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -52,8 +52,8 @@ #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000) #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000) -#define CONFIG_SYS_LS2080A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) -#define CONFIG_SYS_LS2080A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000) +#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) +#define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000) /* TZ Address Space Controller Definitions */ #define TZASC1_BASE 0x01100000 /* as per CCSR map. */ @@ -156,6 +156,7 @@ #define TY_ITYP_VER_A7 0x1 #define TY_ITYP_VER_A53 0x2 #define TY_ITYP_VER_A57 0x3 +#define TY_ITYP_VER_A72 0x4 #define TP_CLUSTER_EOC 0x80000000 /* end of clusters */ #define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ppa.h b/arch/arm/include/asm/arch-fsl-layerscape/ppa.h new file mode 100644 index 00000000000..1f1442b6f0a --- /dev/null +++ b/arch/arm/include/asm/arch-fsl-layerscape/ppa.h @@ -0,0 +1,16 @@ +/* + * Copyright 2016 NXP Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_PPA_H_ +#define __FSL_PPA_H_ + +#define SEC_FIRMWARE_FIT_IMAGE "firmware" +#define SEC_FIRMEWARE_FIT_CNF_NAME "config@1" +#define SEC_FIRMWARE_TARGET_EL 2 + +int ppa_init(void); + +#endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 39e8c7a17c3..8d4a7adb1d5 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -44,6 +44,8 @@ struct cpu_type { #define SVR_LS1012A 0x870400 #define SVR_LS1043A 0x879200 #define SVR_LS1023A 0x879208 +#define SVR_LS1046A 0x870700 +#define SVR_LS1026A 0x870708 #define SVR_LS2045A 0x870120 #define SVR_LS2080A 0x870110 #define SVR_LS2085A 0x870100 diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 04abec467c2..d408fe40561 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -10,7 +10,7 @@ #define CONFIG_SYS_CACHELINE_SIZE 64 #define OCRAM_BASE_ADDR 0x10000000 -#define OCRAM_SIZE 0x00020000 +#define OCRAM_SIZE 0x00010000 #define OCRAM_BASE_S_ADDR 0x10010000 #define OCRAM_S_SIZE 0x00010000 @@ -32,16 +32,15 @@ #define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) #define CONFIG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) +#define CONFIG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000) #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500) #define CONFIG_SYS_DCU_ADDR (CONFIG_SYS_IMMR + 0x01ce0000) -#define CONFIG_SYS_LS102XA_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) -#define CONFIG_SYS_LS102XA_USB1_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET) +#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000) +#define CONFIG_SYS_EHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x07600000) #define CONFIG_SYS_FSL_SEC_OFFSET 0x00700000 #define CONFIG_SYS_FSL_JR0_OFFSET 0x00710000 -#define CONFIG_SYS_LS102XA_USB1_OFFSET 0x07600000 #define CONFIG_SYS_TSEC1_OFFSET 0x01d10000 #define CONFIG_SYS_TSEC2_OFFSET 0x01d50000 #define CONFIG_SYS_TSEC3_OFFSET 0x01d90000 diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index 24563c08e4d..5979340ac8a 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -40,11 +40,12 @@ void sdrc_init(void); void do_sdrc_init(u32, u32); void get_board_mem_timings(struct board_sdrc_timings *timings); -void identify_nand_chip(int *mfr, int *id); +int identify_nand_chip(int *mfr, int *id); void emif4_init(void); void gpmc_init(void); -void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, - u32 size); +void enable_gpmc_cs_config(const u32 *gpmc_config, const struct gpmc_cs *cs, + u32 base, u32 size); +void set_gpmc_cs0(int flash_type); void watchdog_init(void); void set_muxconf_regs(void); diff --git a/arch/arm/include/asm/arch-omap4/i2c.h b/arch/arm/include/asm/arch-omap4/i2c.h index adc8eb23fff..463e979758e 100644 --- a/arch/arm/include/asm/arch-omap4/i2c.h +++ b/arch/arm/include/asm/arch-omap4/i2c.h @@ -14,9 +14,9 @@ struct i2c { unsigned short revnb_lo; /* 0x00 */ unsigned short res1; unsigned short revnb_hi; /* 0x04 */ - unsigned short res2[13]; - unsigned short sysc; /* 0x20 */ - unsigned short res3; + unsigned short res2[5]; + unsigned short sysc; /* 0x10 */ + unsigned short res3[9]; unsigned short irqstatus_raw; /* 0x24 */ unsigned short res4; unsigned short stat; /* 0x28 */ diff --git a/arch/arm/include/asm/arch-omap5/i2c.h b/arch/arm/include/asm/arch-omap5/i2c.h index d875cfe0b4f..2b55edf7f0c 100644 --- a/arch/arm/include/asm/arch-omap5/i2c.h +++ b/arch/arm/include/asm/arch-omap5/i2c.h @@ -14,9 +14,9 @@ struct i2c { unsigned short revnb_lo; /* 0x00 */ unsigned short res1; unsigned short revnb_hi; /* 0x04 */ - unsigned short res2[13]; - unsigned short sysc; /* 0x20 */ - unsigned short res3; + unsigned short res2[5]; + unsigned short sysc; /* 0x10 */ + unsigned short res3[9]; unsigned short irqstatus_raw; /* 0x24 */ unsigned short res4; unsigned short stat; /* 0x28 */ diff --git a/arch/arm/include/asm/arch-rockchip/clock.h b/arch/arm/include/asm/arch-rockchip/clock.h index 317e5128ed2..21edbc2f898 100644 --- a/arch/arm/include/asm/arch-rockchip/clock.h +++ b/arch/arm/include/asm/arch-rockchip/clock.h @@ -65,6 +65,8 @@ void *rockchip_get_cru(void); struct rk3288_cru; struct rk3288_grf; -void rkclk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf); +void rk3288_clk_configure_cpu(struct rk3288_cru *cru, struct rk3288_grf *grf); + +int rockchip_get_clk(struct udevice **devp); #endif diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h new file mode 100644 index 00000000000..c919f47745d --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h @@ -0,0 +1,93 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_CRU_RK3399_H_ +#define __ASM_ARCH_CRU_RK3399_H_ + +#include <common.h> + +struct rk3399_pmucru { + u32 ppll_con[6]; + u32 reserved[0x1a]; + u32 pmucru_clksel[6]; + u32 pmucru_clkfrac_con[2]; + u32 reserved2[0x18]; + u32 pmucru_clkgate_con[3]; + u32 reserved3; + u32 pmucru_softrst_con[2]; + u32 reserved4[2]; + u32 pmucru_rstnhold_con[2]; + u32 reserved5[2]; + u32 pmucru_gatedis_con[2]; +}; +check_member(rk3399_pmucru, pmucru_gatedis_con[1], 0x134); + +struct rk3399_cru { + u32 apll_l_con[6]; + u32 reserved[2]; + u32 apll_b_con[6]; + u32 reserved1[2]; + u32 dpll_con[6]; + u32 reserved2[2]; + u32 cpll_con[6]; + u32 reserved3[2]; + u32 gpll_con[6]; + u32 reserved4[2]; + u32 npll_con[6]; + u32 reserved5[2]; + u32 vpll_con[6]; + u32 reserved6[0x0a]; + u32 clksel_con[108]; + u32 reserved7[0x14]; + u32 clkgate_con[35]; + u32 reserved8[0x1d]; + u32 softrst_con[21]; + u32 reserved9[0x2b]; + u32 glb_srst_fst_value; + u32 glb_srst_snd_value; + u32 glb_cnt_th; + u32 misc_con; + u32 glb_rst_con; + u32 glb_rst_st; + u32 reserved10[0x1a]; + u32 sdmmc_con[2]; + u32 sdio0_con[2]; + u32 sdio1_con[2]; +}; +check_member(rk3399_cru, sdio1_con[1], 0x594); +#define MHz 1000000 +#define KHz 1000 +#define OSC_HZ (24*MHz) +#define APLL_HZ (600*MHz) +#define GPLL_HZ (594*MHz) +#define CPLL_HZ (384*MHz) +#define PPLL_HZ (594*MHz) + +#define PMU_PCLK_HZ (99*MHz) + +#define ACLKM_CORE_HZ (300*MHz) +#define ATCLK_CORE_HZ (300*MHz) +#define PCLK_DBG_HZ (100*MHz) + +#define PERIHP_ACLK_HZ (148500*KHz) +#define PERIHP_HCLK_HZ (148500*KHz) +#define PERIHP_PCLK_HZ (37125*KHz) + +#define PERILP0_ACLK_HZ (99000*KHz) +#define PERILP0_HCLK_HZ (99000*KHz) +#define PERILP0_PCLK_HZ (49500*KHz) + +#define PERILP1_HCLK_HZ (99000*KHz) +#define PERILP1_PCLK_HZ (49500*KHz) + +#define PWM_CLOCK_HZ PMU_PCLK_HZ + +enum apll_l_frequencies { + APLL_L_1600_MHZ, + APLL_L_600_MHZ, +}; + +#endif /* __ASM_ARCH_CRU_RK3399_H_ */ diff --git a/arch/arm/include/asm/arch-rockchip/sdram.h b/arch/arm/include/asm/arch-rockchip/sdram.h index d3de42d2977..e08e28f4f0c 100644 --- a/arch/arm/include/asm/arch-rockchip/sdram.h +++ b/arch/arm/include/asm/arch-rockchip/sdram.h @@ -24,6 +24,12 @@ struct rk3288_sdram_channel { u8 row_3_4; u8 cs0_row; u8 cs1_row; + /* + * For of-platdata, which would otherwise convert this into two + * byte-swapped integers. With a size of 9 bytes, this struct will + * appear in of-platdata as a byte array. + */ + u8 dummy; }; struct rk3288_sdram_pctl_timing { @@ -81,12 +87,4 @@ struct rk3288_base_params { u32 odt; }; -struct rk3288_sdram_params { - struct rk3288_sdram_channel ch[2]; - struct rk3288_sdram_pctl_timing pctl_timing; - struct rk3288_sdram_phy_timing phy_timing; - struct rk3288_base_params base; - int num_channels; -}; - #endif diff --git a/arch/arm/include/asm/arch-stm32f7/fmc.h b/arch/arm/include/asm/arch-stm32f7/fmc.h new file mode 100644 index 00000000000..7dd5077d0c3 --- /dev/null +++ b/arch/arm/include/asm/arch-stm32f7/fmc.h @@ -0,0 +1,75 @@ +/* + * (C) Copyright 2013 + * Pavel Boldin, Emcraft Systems, paboldin@emcraft.com + * + * (C) Copyright 2015 + * Kamil Lulko, <kamil.lulko@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _MACH_FMC_H_ +#define _MACH_FMC_H_ + +struct stm32_fmc_regs { + u32 sdcr1; /* Control register 1 */ + u32 sdcr2; /* Control register 2 */ + u32 sdtr1; /* Timing register 1 */ + u32 sdtr2; /* Timing register 2 */ + u32 sdcmr; /* Mode register */ + u32 sdrtr; /* Refresh timing register */ + u32 sdsr; /* Status register */ +}; + +/* + * FMC registers base + */ +#define STM32_SDRAM_FMC_BASE 0xA0000140 +#define STM32_SDRAM_FMC ((struct stm32_fmc_regs *)STM32_SDRAM_FMC_BASE) + +/* Control register SDCR */ +#define FMC_SDCR_RPIPE_SHIFT 13 /* RPIPE bit shift */ +#define FMC_SDCR_RBURST_SHIFT 12 /* RBURST bit shift */ +#define FMC_SDCR_SDCLK_SHIFT 10 /* SDRAM clock divisor shift */ +#define FMC_SDCR_WP_SHIFT 9 /* Write protection shift */ +#define FMC_SDCR_CAS_SHIFT 7 /* CAS latency shift */ +#define FMC_SDCR_NB_SHIFT 6 /* Number of banks shift */ +#define FMC_SDCR_MWID_SHIFT 4 /* Memory width shift */ +#define FMC_SDCR_NR_SHIFT 2 /* Number of row address bits shift */ +#define FMC_SDCR_NC_SHIFT 0 /* Number of col address bits shift */ + +/* Timings register SDTR */ +#define FMC_SDTR_TMRD_SHIFT 0 /* Load mode register to active */ +#define FMC_SDTR_TXSR_SHIFT 4 /* Exit self-refresh time */ +#define FMC_SDTR_TRAS_SHIFT 8 /* Self-refresh time */ +#define FMC_SDTR_TRC_SHIFT 12 /* Row cycle delay */ +#define FMC_SDTR_TWR_SHIFT 16 /* Recovery delay */ +#define FMC_SDTR_TRP_SHIFT 20 /* Row precharge delay */ +#define FMC_SDTR_TRCD_SHIFT 24 /* Row-to-column delay */ + + +#define FMC_SDCMR_NRFS_SHIFT 5 + +#define FMC_SDCMR_MODE_NORMAL 0 +#define FMC_SDCMR_MODE_START_CLOCK 1 +#define FMC_SDCMR_MODE_PRECHARGE 2 +#define FMC_SDCMR_MODE_AUTOREFRESH 3 +#define FMC_SDCMR_MODE_WRITE_MODE 4 +#define FMC_SDCMR_MODE_SELFREFRESH 5 +#define FMC_SDCMR_MODE_POWERDOWN 6 + +#define FMC_SDCMR_BANK_1 (1 << 4) +#define FMC_SDCMR_BANK_2 (1 << 3) + +#define FMC_SDCMR_MODE_REGISTER_SHIFT 9 + +#define FMC_SDSR_BUSY (1 << 5) + +#define FMC_BUSY_WAIT() do { \ + __asm__ __volatile__ ("dsb" : : : "memory"); \ + while (STM32_SDRAM_FMC->sdsr & FMC_SDSR_BUSY) \ + ; \ + } while (0) + + +#endif /* _MACH_FMC_H_ */ diff --git a/arch/arm/include/asm/arch-stm32f7/stm32.h b/arch/arm/include/asm/arch-stm32f7/stm32.h index 68bdab069d4..de55ae5df15 100644 --- a/arch/arm/include/asm/arch-stm32f7/stm32.h +++ b/arch/arm/include/asm/arch-stm32f7/stm32.h @@ -64,6 +64,52 @@ enum clock { }; #define STM32_BUS_MASK 0xFFFF0000 +struct stm32_rcc_regs { + u32 cr; /* RCC clock control */ + u32 pllcfgr; /* RCC PLL configuration */ + u32 cfgr; /* RCC clock configuration */ + u32 cir; /* RCC clock interrupt */ + u32 ahb1rstr; /* RCC AHB1 peripheral reset */ + u32 ahb2rstr; /* RCC AHB2 peripheral reset */ + u32 ahb3rstr; /* RCC AHB3 peripheral reset */ + u32 rsv0; + u32 apb1rstr; /* RCC APB1 peripheral reset */ + u32 apb2rstr; /* RCC APB2 peripheral reset */ + u32 rsv1[2]; + u32 ahb1enr; /* RCC AHB1 peripheral clock enable */ + u32 ahb2enr; /* RCC AHB2 peripheral clock enable */ + u32 ahb3enr; /* RCC AHB3 peripheral clock enable */ + u32 rsv2; + u32 apb1enr; /* RCC APB1 peripheral clock enable */ + u32 apb2enr; /* RCC APB2 peripheral clock enable */ + u32 rsv3[2]; + u32 ahb1lpenr; /* RCC AHB1 periph clk enable in low pwr mode */ + u32 ahb2lpenr; /* RCC AHB2 periph clk enable in low pwr mode */ + u32 ahb3lpenr; /* RCC AHB3 periph clk enable in low pwr mode */ + u32 rsv4; + u32 apb1lpenr; /* RCC APB1 periph clk enable in low pwr mode */ + u32 apb2lpenr; /* RCC APB2 periph clk enable in low pwr mode */ + u32 rsv5[2]; + u32 bdcr; /* RCC Backup domain control */ + u32 csr; /* RCC clock control & status */ + u32 rsv6[2]; + u32 sscgr; /* RCC spread spectrum clock generation */ + u32 plli2scfgr; /* RCC PLLI2S configuration */ + u32 pllsaicfgr; + u32 dckcfgr; +}; +#define STM32_RCC ((struct stm32_rcc_regs *)RCC_BASE) + +struct stm32_pwr_regs { + u32 cr1; /* power control register 1 */ + u32 csr1; /* power control/status register 2 */ + u32 cr2; /* power control register 2 */ + u32 csr2; /* power control/status register 2 */ +}; +#define STM32_PWR ((struct stm32_pwr_regs *)PWR_BASE) + int configure_clocks(void); +unsigned long clock_get(enum clock clck); +void stm32_flash_latency_cfg(int latency); #endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h index 0088bb9d0b4..d1c5ad0a739 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h @@ -269,6 +269,11 @@ struct sunxi_ccm_reg { #define CCM_MBUS_CTRL_CLK_SRC_PLL5 0x2 #define CCM_MBUS_CTRL_GATE (0x1 << 31) +#define CCM_NAND_CTRL_M(x) ((x) - 1) +#define CCM_NAND_CTRL_N(x) ((x) << 16) +#define CCM_NAND_CTRL_OSCM24 (0x0 << 24) +#define CCM_NAND_CTRL_PLL6 (0x1 << 24) +#define CCM_NAND_CTRL_PLL5 (0x2 << 24) #define CCM_NAND_CTRL_ENABLE (0x1 << 31) #define CCM_MMC_CTRL_M(x) ((x) - 1) diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h index c2e72f5a86b..d4dff1e3463 100644 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h @@ -40,7 +40,8 @@ struct sunxi_ccm_reg { u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */ u32 apb1_gate; /* 0x68 apb1 module clock gating */ u32 apb2_gate; /* 0x6c apb2 module clock gating */ - u32 reserved9[4]; + u32 bus_gate4; /* 0x70 gate 4 module clock gating */ + u8 res3[0xc]; u32 nand0_clk_cfg; /* 0x80 nand0 clock control */ u32 nand1_clk_cfg; /* 0x84 nand1 clock control */ u32 sd0_clk_cfg; /* 0x88 sd0 clock control */ @@ -387,6 +388,7 @@ struct sunxi_ccm_reg { #define AHB_RESET_OFFSET_LCD0 4 /* ahb_reset2 offsets */ +#define AHB_RESET_OFFSET_EPHY 2 #define AHB_RESET_OFFSET_LVDS 0 /* apb2 reset */ diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h index c5e9d88bab5..cd009d7ccc2 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h @@ -87,7 +87,8 @@ #define SUNXI_KEYPAD_BASE 0x01c23000 #define SUNXI_TZPC_BASE 0x01c23400 -#if defined(CONFIG_MACH_SUN8I_A83T) || defined(CONFIG_MACH_SUN8I_H3) +#if defined(CONFIG_MACH_SUN8I_A83T) || defined(CONFIG_MACH_SUN8I_H3) || \ +defined(CONFIG_MACH_SUN50I) /* SID address space starts at 0x01c1400, but e-fuse is at offset 0x200 */ #define SUNXI_SID_BASE 0x01c14200 #else diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index 1ace5480227..bff7d1453f1 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -141,6 +141,7 @@ enum sunxi_gpio_number { /* GPIO pin function config */ #define SUNXI_GPIO_INPUT 0 #define SUNXI_GPIO_OUTPUT 1 +#define SUNXI_GPIO_DISABLE 7 #define SUNXI_GPA_EMAC 2 #define SUN6I_GPA_GMAC 2 @@ -162,8 +163,10 @@ enum sunxi_gpio_number { #define SUN50I_GPB_UART0 4 #define SUNXI_GPC_NAND 2 +#define SUNXI_GPC_SPI0 3 #define SUNXI_GPC_SDC2 3 #define SUN6I_GPC_SDC3 4 +#define SUN50I_GPC_SPI0 4 #define SUN8I_GPD_SDC1 3 #define SUNXI_GPD_LCD0 2 diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h index 3da360b177d..cb52e648731 100644 --- a/arch/arm/include/asm/arch-sunxi/mmc.h +++ b/arch/arm/include/asm/arch-sunxi/mmc.h @@ -127,5 +127,4 @@ struct sunxi_mmc { #define SUNXI_MMC_COMMON_RESET (1 << 18) struct mmc *sunxi_mmc_init(int sdc_no); -int sunxi_mmc_has_egon_boot_signature(struct mmc *mmc); #endif /* _SUNXI_MMC_H */ diff --git a/arch/arm/include/asm/arch-sunxi/spl.h b/arch/arm/include/asm/arch-sunxi/spl.h index ec73379735c..5d7ab559ef9 100644 --- a/arch/arm/include/asm/arch-sunxi/spl.h +++ b/arch/arm/include/asm/arch-sunxi/spl.h @@ -51,7 +51,14 @@ struct boot_file_head { uint8_t spl_signature[4]; }; uint32_t fel_script_address; - uint32_t reserved1[3]; + /* + * If the fel_uEnv_length member below is set to a non-zero value, + * it specifies the size (byte count) of data at fel_script_address. + * At the same time this indicates that the data is in uEnv.txt + * compatible format, ready to be imported via "env import -t". + */ + uint32_t fel_uEnv_length; + uint32_t reserved1[2]; uint32_t boot_media; /* written here by the boot ROM */ uint32_t reserved2[5]; /* padding, align to 64 bytes */ }; diff --git a/arch/arm/include/asm/arch-tegra/board.h b/arch/arm/include/asm/arch-tegra/board.h index 783bb3c0fa1..a3db7ed6044 100644 --- a/arch/arm/include/asm/arch-tegra/board.h +++ b/arch/arm/include/asm/arch-tegra/board.h @@ -20,7 +20,7 @@ void gpio_early_init(void); /* overrideable GPIO config */ /* * Hooks to allow boards to set up the pinmux for a specific function. * Has to be implemented in the board files as we don't yet support pinmux - * setup from FTD. If a board file does not implement one of those functions + * setup from FDT. If a board file does not implement one of those functions * an empty stub function will be called. */ diff --git a/arch/arm/include/asm/arch-tegra/bpmp_abi.h b/arch/arm/include/asm/arch-tegra/bpmp_abi.h new file mode 100644 index 00000000000..7b6ad899cf6 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra/bpmp_abi.h @@ -0,0 +1,1591 @@ +/* + * Copyright (c) 2014-2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _ABI_BPMP_ABI_H_ +#define _ABI_BPMP_ABI_H_ + +#ifdef LK +#include <stdint.h> +#endif + +#ifndef __ABI_PACKED +#define __ABI_PACKED __attribute__((packed)) +#endif + +#ifdef NO_GCC_EXTENSIONS +#define EMPTY char empty; +#define EMPTY_ARRAY 1 +#else +#define EMPTY +#define EMPTY_ARRAY 0 +#endif + +#ifndef __UNION_ANON +#define __UNION_ANON +#endif +/** + * @file + */ + + +/** + * @defgroup MRQ MRQ Messages + * @brief Messages sent to/from BPMP via IPC + * @{ + * @defgroup MRQ_Format Message Format + * @defgroup MRQ_Codes Message Request (MRQ) Codes + * @defgroup MRQ_Payloads Message Payloads + * @defgroup Error_Codes Error Codes + * @} + */ + +/** + * @addtogroup MRQ_Format Message Format + * @{ + * The CPU requests the BPMP to perform a particular service by + * sending it an IVC frame containing a single MRQ message. An MRQ + * message consists of a @ref mrq_request followed by a payload whose + * format depends on mrq_request::mrq. + * + * The BPMP processes the data and replies with an IVC frame (on the + * same IVC channel) containing and MRQ response. An MRQ response + * consists of a @ref mrq_response followed by a payload whose format + * depends on the associated mrq_request::mrq. + * + * A well-defined subset of the MRQ messages that the CPU sends to the + * BPMP can lead to BPMP eventually sending an MRQ message to the + * CPU. For example, when the CPU uses an #MRQ_THERMAL message to set + * a thermal trip point, the BPMP may eventually send a single + * #MRQ_THERMAL message of its own to the CPU indicating that the trip + * point has been crossed. + * @} + */ + +/** + * @ingroup MRQ_Format + * @brief header for an MRQ message + * + * Provides the MRQ number for the MRQ message: #mrq. The remainder of + * the MRQ message is a payload (immediately following the + * mrq_request) whose format depends on mrq. + * + * @todo document the flags + */ +struct mrq_request { + /** @brief MRQ number of the request */ + uint32_t mrq; + /** @brief flags for the request */ + uint32_t flags; +} __ABI_PACKED; + +/** + * @ingroup MRQ_Format + * @brief header for an MRQ response + * + * Provides an error code for the associated MRQ message. The + * remainder of the MRQ response is a payload (immediately following + * the mrq_response) whose format depends on the associated + * mrq_request::mrq + * + * @todo document the flags + */ +struct mrq_response { + /** @brief error code for the MRQ request itself */ + int32_t err; + /** @brief flags for the response */ + uint32_t flags; +} __ABI_PACKED; + +/** + * @ingroup MRQ_Format + * Minimum needed size for an IPC message buffer + */ +#define MSG_MIN_SZ 128 +/** + * @ingroup MRQ_Format + * Minimum size guaranteed for data in an IPC message buffer + */ +#define MSG_DATA_MIN_SZ 120 + +/** + * @ingroup MRQ_Codes + * @name Legal MRQ codes + * These are the legal values for mrq_request::mrq + * @{ + */ + +#define MRQ_PING 0 +#define MRQ_QUERY_TAG 1 +#define MRQ_MODULE_LOAD 4 +#define MRQ_MODULE_UNLOAD 5 +#define MRQ_TRACE_MODIFY 7 +#define MRQ_WRITE_TRACE 8 +#define MRQ_THREADED_PING 9 +#define MRQ_MODULE_MAIL 11 +#define MRQ_DEBUGFS 19 +#define MRQ_RESET 20 +#define MRQ_I2C 21 +#define MRQ_CLK 22 +#define MRQ_QUERY_ABI 23 +#define MRQ_PG_READ_STATE 25 +#define MRQ_PG_UPDATE_STATE 26 +#define MRQ_THERMAL 27 +#define MRQ_CPU_VHINT 28 +#define MRQ_ABI_RATCHET 29 +#define MRQ_EMC_DVFS_LATENCY 31 +#define MRQ_TRACE_ITER 64 + +/** @} */ + +/** + * @ingroup MRQ_Codes + * @brief Maximum MRQ code to be sent by CPU software to + * BPMP. Subject to change in future + */ +#define MAX_CPU_MRQ_ID 64 + +/** + * @addtogroup MRQ_Payloads Message Payloads + * @{ + * @defgroup Ping + * @defgroup Query_Tag Query Tag + * @defgroup Module Loadable Modules + * @defgroup Trace + * @defgroup Debugfs + * @defgroup Reset + * @defgroup I2C + * @defgroup Clocks + * @defgroup ABI_info ABI Info + * @defgroup MC_Flush MC Flush + * @defgroup Powergating + * @defgroup Thermal + * @defgroup Vhint CPU Voltage hint + * @defgroup MRQ_Deprecated Deprecated MRQ messages + * @defgroup EMC + * @} + */ + + +/** + * @ingroup MRQ_Codes + * @def MRQ_PING + * @brief A simple ping + * + * * Platforms: All + * * Initiators: Any + * * Targets: Any + * * Request Payload: @ref mrq_ping_request + * * Response Payload: @ref mrq_ping_response + * + * @ingroup MRQ_Codes + * @def MRQ_THREADED_PING + * @brief A deeper ping + * + * * Platforms: All + * * Initiators: Any + * * Targets: BPMP + * * Request Payload: @ref mrq_ping_request + * * Response Payload: @ref mrq_ping_response + * + * Behavior is equivalent to a simple #MRQ_PING except that BPMP + * responds from a thread context (providing a slightly more robust + * sign of life). + * + */ + +/** + * @ingroup Ping + * @brief request with #MRQ_PING + * + * Used by the sender of an #MRQ_PING message to request a pong from + * recipient. The response from the recipient is computed based on + * #challenge. + */ +struct mrq_ping_request { +/** @brief arbitrarily chosen value */ + uint32_t challenge; +} __ABI_PACKED; + +/** + * @ingroup Ping + * @brief response to #MRQ_PING + * + * Sent in response to an #MRQ_PING message. #reply should be the + * mrq_ping_request challenge left shifted by 1 with the carry-bit + * dropped. + * + */ +struct mrq_ping_response { + /** @brief response to the MRQ_PING challege */ + uint32_t reply; +} __ABI_PACKED; + +/** + * @ingroup MRQ_Codes + * @def MRQ_QUERY_TAG + * @brief Query BPMP firmware's tag (i.e. version information) + * + * * Platforms: All + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: @ref mrq_query_tag_request + * * Response Payload: N/A + * + */ + +/** + * @ingroup Query_Tag + * @brief request with #MRQ_QUERY_TAG + * + * Used by #MRQ_QUERY_TAG call to ask BPMP to fill in the memory + * pointed by #addr with BPMP firmware header. + * + * The sender is reponsible for ensuring that #addr is mapped in to + * the recipient's address map. + */ +struct mrq_query_tag_request { + /** @brief base address to store the firmware header */ + uint32_t addr; +} __ABI_PACKED; + +/** + * @ingroup MRQ_Codes + * @def MRQ_MODULE_LOAD + * @brief dynamically load a BPMP code module + * + * * Platforms: All + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: @ref mrq_module_load_request + * * Response Payload: @ref mrq_module_load_response + * + * @note This MRQ is disabled on production systems + * + */ + +/** + * @ingroup Module + * @brief request with #MRQ_MODULE_LOAD + * + * Used by #MRQ_MODULE_LOAD calls to ask the recipient to dynamically + * load the code located at #phys_addr and having size #size + * bytes. #phys_addr is treated as a void pointer. + * + * The recipient copies the code from #phys_addr to locally allocated + * memory prior to responding to this message. + * + * @todo document the module header format + * + * The sender is responsible for ensuring that the code is mapped in + * the recipient's address map. + * + */ +struct mrq_module_load_request { + /** @brief base address of the code to load. Treated as (void *) */ + uint32_t phys_addr; /* (void *) */ + /** @brief size in bytes of code to load */ + uint32_t size; +} __ABI_PACKED; + +/** + * @ingroup Module + * @brief response to #MRQ_MODULE_LOAD + * + * @todo document mrq_response::err + */ +struct mrq_module_load_response { + /** @brief handle to the loaded module */ + uint32_t base; +} __ABI_PACKED; + +/** + * @ingroup MRQ_Codes + * @def MRQ_MODULE_UNLOAD + * @brief unload a previously loaded code module + * + * * Platforms: All + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: @ref mrq_module_unload_request + * * Response Payload: N/A + * + * @note This MRQ is disabled on production systems + */ + +/** + * @ingroup Module + * @brief request with #MRQ_MODULE_UNLOAD + * + * Used by #MRQ_MODULE_UNLOAD calls to request that a previously loaded + * module be unloaded. + */ +struct mrq_module_unload_request { + /** @brief handle of the module to unload */ + uint32_t base; +} __ABI_PACKED; + +/** + * @ingroup MRQ_Codes + * @def MRQ_TRACE_MODIFY + * @brief modify the set of enabled trace events + * + * * Platforms: All + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: @ref mrq_trace_modify_request + * * Response Payload: @ref mrq_trace_modify_response + * + * @note This MRQ is disabled on production systems + */ + +/** + * @ingroup Trace + * @brief request with #MRQ_TRACE_MODIFY + * + * Used by %MRQ_TRACE_MODIFY calls to enable or disable specify trace + * events. #set takes precedence for any bit set in both #set and + * #clr. + */ +struct mrq_trace_modify_request { + /** @brief bit mask of trace events to disable */ + uint32_t clr; + /** @brief bit mask of trace events to enable */ + uint32_t set; +} __ABI_PACKED; + +/** + * @ingroup Trace + * @brief response to #MRQ_TRACE_MODIFY + * + * Sent in repsonse to an #MRQ_TRACE_MODIFY message. #mask reflects the + * state of which events are enabled after the recipient acted on the + * message. + * + */ +struct mrq_trace_modify_response { + /** @brief bit mask of trace event enable states */ + uint32_t mask; +} __ABI_PACKED; + +/** + * @ingroup MRQ_Codes + * @def MRQ_WRITE_TRACE + * @brief Write trace data to a buffer + * + * * Platforms: All + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: @ref mrq_write_trace_request + * * Response Payload: @ref mrq_write_trace_response + * + * mrq_response::err depends on the @ref mrq_write_trace_request field + * values. err is -#BPMP_EINVAL if size is zero or area is NULL or + * area is in an illegal range. A positive value for err indicates the + * number of bytes written to area. + * + * @note This MRQ is disabled on production systems + */ + +/** + * @ingroup Trace + * @brief request with #MRQ_WRITE_TRACE + * + * Used by MRQ_WRITE_TRACE calls to ask the recipient to copy trace + * data from the recipient's local buffer to the output buffer. #area + * is treated as a byte-aligned pointer in the recipient's address + * space. + * + * The sender is responsible for ensuring that the output + * buffer is mapped in the recipient's address map. The recipient is + * responsible for protecting its own code and data from accidental + * overwrites. + */ +struct mrq_write_trace_request { + /** @brief base address of output buffer */ + uint32_t area; + /** @brief size in bytes of the output buffer */ + uint32_t size; +} __ABI_PACKED; + +/** + * @ingroup Trace + * @brief response to #MRQ_WRITE_TRACE + * + * Once this response is sent, the respondent will not access the + * output buffer further. + */ +struct mrq_write_trace_response { + /** + * @brief flag whether more data remains in local buffer + * + * Value is 1 if the entire local trace buffer has been + * drained to the outputbuffer. Value is 0 otherwise. + */ + uint32_t eof; +} __ABI_PACKED; + +/** @private */ +struct mrq_threaded_ping_request { + uint32_t challenge; +} __ABI_PACKED; + +/** @private */ +struct mrq_threaded_ping_response { + uint32_t reply; +} __ABI_PACKED; + +/** + * @ingroup MRQ_Codes + * @def MRQ_MODULE_MAIL + * @brief send a message to a loadable module + * + * * Platforms: All + * * Initiators: Any + * * Targets: BPMP + * * Request Payload: @ref mrq_module_mail_request + * * Response Payload: @ref mrq_module_mail_response + * + * @note This MRQ is disabled on production systems + */ + +/** + * @ingroup Module + * @brief request with #MRQ_MODULE_MAIL + */ +struct mrq_module_mail_request { + /** @brief handle to the previously loaded module */ + uint32_t base; + /** @brief module-specific mail payload + * + * The length of data[ ] is unknown to the BPMP core firmware + * but it is limited to the size of an IPC message. + */ + uint8_t data[EMPTY_ARRAY]; +} __ABI_PACKED; + +/** + * @ingroup Module + * @brief response to #MRQ_MODULE_MAIL + */ +struct mrq_module_mail_response { + /** @brief module-specific mail payload + * + * The length of data[ ] is unknown to the BPMP core firmware + * but it is limited to the size of an IPC message. + */ + uint8_t data[EMPTY_ARRAY]; +} __ABI_PACKED; + +/** + * @ingroup MRQ_Codes + * @def MRQ_DEBUGFS + * @brief Interact with BPMP's debugfs file nodes + * + * * Platforms: T186 + * * Initiators: Any + * * Targets: BPMP + * * Request Payload: @ref mrq_debugfs_request + * * Response Payload: @ref mrq_debugfs_response + */ + +/** + * @addtogroup Debugfs + * @{ + * + * The BPMP firmware implements a pseudo-filesystem called + * debugfs. Any driver within the firmware may register with debugfs + * to expose an arbitrary set of "files" in the filesystem. When + * software on the CPU writes to a debugfs file, debugfs passes the + * written data to a callback provided by the driver. When software on + * the CPU reads a debugfs file, debugfs queries the driver for the + * data to return to the CPU. The intention of the debugfs filesystem + * is to provide information useful for debugging the system at + * runtime. + * + * @note The files exposed via debugfs are not part of the + * BPMP firmware's ABI. debugfs files may be added or removed in any + * given version of the firmware. Typically the semantics of a debugfs + * file are consistent from version to version but even that is not + * guaranteed. + * + * @} + */ +/** @ingroup Debugfs */ +enum mrq_debugfs_commands { + CMD_DEBUGFS_READ = 1, + CMD_DEBUGFS_WRITE = 2, + CMD_DEBUGFS_DUMPDIR = 3, + CMD_DEBUGFS_MAX +}; + +/** + * @ingroup Debugfs + * @brief parameters for CMD_DEBUGFS_READ/WRITE command + */ +struct cmd_debugfs_fileop_request { + /** @brief physical address pointing at filename */ + uint32_t fnameaddr; + /** @brief length in bytes of filename buffer */ + uint32_t fnamelen; + /** @brief physical address pointing to data buffer */ + uint32_t dataaddr; + /** @brief length in bytes of data buffer */ + uint32_t datalen; +} __ABI_PACKED; + +/** + * @ingroup Debugfs + * @brief parameters for CMD_DEBUGFS_READ/WRITE command + */ +struct cmd_debugfs_dumpdir_request { + /** @brief physical address pointing to data buffer */ + uint32_t dataaddr; + /** @brief length in bytes of data buffer */ + uint32_t datalen; +} __ABI_PACKED; + +/** + * @ingroup Debugfs + * @brief response data for CMD_DEBUGFS_READ/WRITE command + */ +struct cmd_debugfs_fileop_response { + /** @brief always 0 */ + uint32_t reserved; + /** @brief number of bytes read from or written to data buffer */ + uint32_t nbytes; +} __ABI_PACKED; + +/** + * @ingroup Debugfs + * @brief response data for CMD_DEBUGFS_DUMPDIR command + */ +struct cmd_debugfs_dumpdir_response { + /** @brief always 0 */ + uint32_t reserved; + /** @brief number of bytes read from or written to data buffer */ + uint32_t nbytes; +} __ABI_PACKED; + +/** + * @ingroup Debugfs + * @brief request with #MRQ_DEBUGFS. + * + * The sender of an MRQ_DEBUGFS message uses #cmd to specify a debugfs + * command to execute. Legal commands are the values of @ref + * mrq_debugfs_commands. Each command requires a specific additional + * payload of data. + * + * |command |payload| + * |-------------------|-------| + * |CMD_DEBUGFS_READ |fop | + * |CMD_DEBUGFS_WRITE |fop | + * |CMD_DEBUGFS_DUMPDIR|dumpdir| + */ +struct mrq_debugfs_request { + uint32_t cmd; + union { + struct cmd_debugfs_fileop_request fop; + struct cmd_debugfs_dumpdir_request dumpdir; + } __UNION_ANON; +} __ABI_PACKED; + +/** + * @ingroup Debugfs + */ +struct mrq_debugfs_response { + /** @brief always 0 */ + int32_t reserved; + union { + /** @brief response data for CMD_DEBUGFS_READ OR + * CMD_DEBUGFS_WRITE command + */ + struct cmd_debugfs_fileop_response fop; + /** @brief response data for CMD_DEBUGFS_DUMPDIR command */ + struct cmd_debugfs_dumpdir_response dumpdir; + } __UNION_ANON; +} __ABI_PACKED; + +/** + * @addtogroup Debugfs + * @{ + */ +#define DEBUGFS_S_ISDIR (1 << 9) +#define DEBUGFS_S_IRUSR (1 << 8) +#define DEBUGFS_S_IWUSR (1 << 7) +/** @} */ + + +/** + * @ingroup MRQ_Codes + * @def MRQ_RESET + * @brief reset an IP block + * + * * Platforms: T186 + * * Initiators: Any + * * Targets: BPMP + * * Request Payload: @ref mrq_reset_request + * * Response Payload: N/A + */ + +/** + * @ingroup Reset + */ +enum mrq_reset_commands { + CMD_RESET_ASSERT = 1, + CMD_RESET_DEASSERT = 2, + CMD_RESET_MODULE = 3, + CMD_RESET_MAX, /* not part of ABI and subject to change */ +}; + +/** + * @ingroup Reset + * @brief request with MRQ_RESET + * + * Used by the sender of an #MRQ_RESET message to request BPMP to + * assert or or deassert a given reset line. + */ +struct mrq_reset_request { + /** @brief reset action to perform (@enum mrq_reset_commands) */ + uint32_t cmd; + /** @brief id of the reset to affected */ + uint32_t reset_id; +} __ABI_PACKED; + +/** + * @ingroup MRQ_Codes + * @def MRQ_I2C + * @brief issue an i2c transaction + * + * * Platforms: T186 + * * Initiators: Any + * * Targets: BPMP + * * Request Payload: @ref mrq_i2c_request + * * Response Payload: @ref mrq_i2c_response + */ + +/** + * @addtogroup I2C + * @{ + */ +#define TEGRA_I2C_IPC_MAX_IN_BUF_SIZE (MSG_DATA_MIN_SZ - 12) +#define TEGRA_I2C_IPC_MAX_OUT_BUF_SIZE (MSG_DATA_MIN_SZ - 4) +/** @} */ + +/** + * @ingroup I2C + * @name Serial I2C flags + * Use these flags with serial_i2c_request::flags + * @{ + */ +#define SERIALI2C_TEN 0x0010 +#define SERIALI2C_RD 0x0001 +#define SERIALI2C_STOP 0x8000 +#define SERIALI2C_NOSTART 0x4000 +#define SERIALI2C_REV_DIR_ADDR 0x2000 +#define SERIALI2C_IGNORE_NAK 0x1000 +#define SERIALI2C_NO_RD_ACK 0x0800 +#define SERIALI2C_RECV_LEN 0x0400 +/** @} */ +/** @ingroup I2C */ +enum { + CMD_I2C_XFER = 1 +}; + +/** + * @ingroup I2C + * @brief serializable i2c request + * + * Instances of this structure are packed (little-endian) into + * cmd_i2c_xfer_request::data_buf. Each instance represents a single + * transaction (or a portion of a transaction with repeated starts) on + * an i2c bus. + * + * Because these structures are packed, some instances are likely to + * be misaligned. Additionally because #data is variable length, it is + * not possible to iterate through a serialized list of these + * structures without inspecting #len in each instance. It may be + * easier to serialize or deserialize cmd_i2c_xfer_request::data_buf + * manually rather than using this structure definition. +*/ +struct serial_i2c_request { + /** @brief I2C slave address */ + uint16_t addr; + /** @brief bitmask of SERIALI2C_ flags */ + uint16_t flags; + /** @brief length of I2C transaction in bytes */ + uint16_t len; + /** @brief for write transactions only, #len bytes of data */ + uint8_t data[]; +} __ABI_PACKED; + +/** + * @ingroup I2C + * @brief trigger one or more i2c transactions + */ +struct cmd_i2c_xfer_request { + /** @brief valid bus number from mach-t186/i2c-t186.h*/ + uint32_t bus_id; + + /** @brief count of valid bytes in #data_buf*/ + uint32_t data_size; + + /** @brief serialized packed instances of @ref serial_i2c_request*/ + uint8_t data_buf[TEGRA_I2C_IPC_MAX_IN_BUF_SIZE]; +} __ABI_PACKED; + +/** + * @ingroup I2C + * @brief container for data read from the i2c bus + * + * Processing an cmd_i2c_xfer_request::data_buf causes BPMP to execute + * zero or more I2C reads. The data read from the bus is serialized + * into #data_buf. + */ +struct cmd_i2c_xfer_response { + /** @brief count of valid bytes in #data_buf*/ + uint32_t data_size; + /** @brief i2c read data */ + uint8_t data_buf[TEGRA_I2C_IPC_MAX_OUT_BUF_SIZE]; +} __ABI_PACKED; + +/** + * @ingroup I2C + * @brief request with #MRQ_I2C + */ +struct mrq_i2c_request { + /** @brief always CMD_I2C_XFER (i.e. 1) */ + uint32_t cmd; + /** @brief parameters of the transfer request */ + struct cmd_i2c_xfer_request xfer; +} __ABI_PACKED; + +/** + * @ingroup I2C + * @brief response to #MRQ_I2C + */ +struct mrq_i2c_response { + struct cmd_i2c_xfer_response xfer; +} __ABI_PACKED; + +/** + * @ingroup MRQ_Codes + * @def MRQ_CLK + * + * * Platforms: T186 + * * Initiators: Any + * * Targets: BPMP + * * Request Payload: @ref mrq_clk_request + * * Response Payload: @ref mrq_clk_response + * @addtogroup Clocks + * @{ + */ + +/** + * @name MRQ_CLK sub-commands + * @{ + */ +enum { + CMD_CLK_GET_RATE = 1, + CMD_CLK_SET_RATE = 2, + CMD_CLK_ROUND_RATE = 3, + CMD_CLK_GET_PARENT = 4, + CMD_CLK_SET_PARENT = 5, + CMD_CLK_IS_ENABLED = 6, + CMD_CLK_ENABLE = 7, + CMD_CLK_DISABLE = 8, + CMD_CLK_GET_ALL_INFO = 14, + CMD_CLK_GET_MAX_CLK_ID = 15, + CMD_CLK_MAX, +}; +/** @} */ + +#define MRQ_CLK_NAME_MAXLEN 40 +#define MRQ_CLK_MAX_PARENTS 16 + +/** @private */ +struct cmd_clk_get_rate_request { + EMPTY +} __ABI_PACKED; + +struct cmd_clk_get_rate_response { + int64_t rate; +} __ABI_PACKED; + +struct cmd_clk_set_rate_request { + int32_t unused; + int64_t rate; +} __ABI_PACKED; + +struct cmd_clk_set_rate_response { + int64_t rate; +} __ABI_PACKED; + +struct cmd_clk_round_rate_request { + int32_t unused; + int64_t rate; +} __ABI_PACKED; + +struct cmd_clk_round_rate_response { + int64_t rate; +} __ABI_PACKED; + +/** @private */ +struct cmd_clk_get_parent_request { + EMPTY +} __ABI_PACKED; + +struct cmd_clk_get_parent_response { + uint32_t parent_id; +} __ABI_PACKED; + +struct cmd_clk_set_parent_request { + uint32_t parent_id; +} __ABI_PACKED; + +struct cmd_clk_set_parent_response { + uint32_t parent_id; +} __ABI_PACKED; + +/** @private */ +struct cmd_clk_is_enabled_request { + EMPTY +} __ABI_PACKED; + +struct cmd_clk_is_enabled_response { + int32_t state; +} __ABI_PACKED; + +/** @private */ +struct cmd_clk_enable_request { + EMPTY +} __ABI_PACKED; + +/** @private */ +struct cmd_clk_enable_response { + EMPTY +} __ABI_PACKED; + +/** @private */ +struct cmd_clk_disable_request { + EMPTY +} __ABI_PACKED; + +/** @private */ +struct cmd_clk_disable_response { + EMPTY +} __ABI_PACKED; + +/** @private */ +struct cmd_clk_get_all_info_request { + EMPTY +} __ABI_PACKED; + +struct cmd_clk_get_all_info_response { + uint32_t flags; + uint32_t parent; + uint32_t parents[MRQ_CLK_MAX_PARENTS]; + uint8_t num_parents; + uint8_t name[MRQ_CLK_NAME_MAXLEN]; +} __ABI_PACKED; + +/** @private */ +struct cmd_clk_get_max_clk_id_request { + EMPTY +} __ABI_PACKED; + +struct cmd_clk_get_max_clk_id_response { + uint32_t max_id; +} __ABI_PACKED; +/** @} */ + +/** + * @ingroup Clocks + * @brief request with #MRQ_CLK + * + * Used by the sender of an #MRQ_CLK message to control clocks. The + * clk_request is split into several sub-commands. Some sub-commands + * require no additional data. Others have a sub-command specific + * payload + * + * |sub-command |payload | + * |----------------------------|-----------------------| + * |CMD_CLK_GET_RATE |- | + * |CMD_CLK_SET_RATE |clk_set_rate | + * |CMD_CLK_ROUND_RATE |clk_round_rate | + * |CMD_CLK_GET_PARENT |- | + * |CMD_CLK_SET_PARENT |clk_set_parent | + * |CMD_CLK_IS_ENABLED |- | + * |CMD_CLK_ENABLE |- | + * |CMD_CLK_DISABLE |- | + * |CMD_CLK_GET_ALL_INFO |- | + * |CMD_CLK_GET_MAX_CLK_ID |- | + * + */ + +struct mrq_clk_request { + /** @brief sub-command and clock id concatenated to 32-bit word. + * - bits[31..24] is the sub-cmd. + * - bits[23..0] is the clock id + */ + uint32_t cmd_and_id; + + union { + /** @private */ + struct cmd_clk_get_rate_request clk_get_rate; + struct cmd_clk_set_rate_request clk_set_rate; + struct cmd_clk_round_rate_request clk_round_rate; + /** @private */ + struct cmd_clk_get_parent_request clk_get_parent; + struct cmd_clk_set_parent_request clk_set_parent; + /** @private */ + struct cmd_clk_enable_request clk_enable; + /** @private */ + struct cmd_clk_disable_request clk_disable; + /** @private */ + struct cmd_clk_is_enabled_request clk_is_enabled; + /** @private */ + struct cmd_clk_get_all_info_request clk_get_all_info; + /** @private */ + struct cmd_clk_get_max_clk_id_request clk_get_max_clk_id; + } __UNION_ANON; +} __ABI_PACKED; + +/** + * @ingroup Clocks + * @brief response to MRQ_CLK + * + * Each sub-command supported by @ref mrq_clk_request may return + * sub-command-specific data. Some do and some do not as indicated in + * the following table + * + * |sub-command |payload | + * |----------------------------|------------------------| + * |CMD_CLK_GET_RATE |clk_get_rate | + * |CMD_CLK_SET_RATE |clk_set_rate | + * |CMD_CLK_ROUND_RATE |clk_round_rate | + * |CMD_CLK_GET_PARENT |clk_get_parent | + * |CMD_CLK_SET_PARENT |clk_set_parent | + * |CMD_CLK_IS_ENABLED |clk_is_enabled | + * |CMD_CLK_ENABLE |- | + * |CMD_CLK_DISABLE |- | + * |CMD_CLK_GET_ALL_INFO |clk_get_all_info | + * |CMD_CLK_GET_MAX_CLK_ID |clk_get_max_id | + * + */ + +struct mrq_clk_response { + union { + struct cmd_clk_get_rate_response clk_get_rate; + struct cmd_clk_set_rate_response clk_set_rate; + struct cmd_clk_round_rate_response clk_round_rate; + struct cmd_clk_get_parent_response clk_get_parent; + struct cmd_clk_set_parent_response clk_set_parent; + /** @private */ + struct cmd_clk_enable_response clk_enable; + /** @private */ + struct cmd_clk_disable_response clk_disable; + struct cmd_clk_is_enabled_response clk_is_enabled; + struct cmd_clk_get_all_info_response clk_get_all_info; + struct cmd_clk_get_max_clk_id_response clk_get_max_clk_id; + } __UNION_ANON; +} __ABI_PACKED; + +/** + * @ingroup MRQ_Codes + * @def MRQ_QUERY_ABI + * @brief check if an MRQ is implemented + * + * * Platforms: All + * * Initiators: Any + * * Targets: Any + * * Request Payload: @ref mrq_query_abi_request + * * Response Payload: @ref mrq_query_abi_response + */ + +/** + * @ingroup ABI_info + * @brief request with MRQ_QUERY_ABI + * + * Used by #MRQ_QUERY_ABI call to check if MRQ code #mrq is supported + * by the recipient. + */ +struct mrq_query_abi_request { + /** @brief MRQ code to query */ + uint32_t mrq; +} __ABI_PACKED; + +/** + * @ingroup ABI_info + * @brief response to MRQ_QUERY_ABI + */ +struct mrq_query_abi_response { + /** @brief 0 if queried MRQ is supported. Else, -#BPMP_ENODEV */ + int32_t status; +} __ABI_PACKED; + +/** + * @ingroup MRQ_Codes + * @def MRQ_PG_READ_STATE + * @brief read the power-gating state of a partition + * + * * Platforms: T186 + * * Initiators: Any + * * Targets: BPMP + * * Request Payload: @ref mrq_pg_read_state_request + * * Response Payload: @ref mrq_pg_read_state_response + * @addtogroup Powergating + * @{ + */ + +/** + * @brief request with #MRQ_PG_READ_STATE + * + * Used by MRQ_PG_READ_STATE call to read the current state of a + * partition. + */ +struct mrq_pg_read_state_request { + /** @brief ID of partition */ + uint32_t partition_id; +} __ABI_PACKED; + +/** + * @brief response to MRQ_PG_READ_STATE + * @todo define possible errors. + */ +struct mrq_pg_read_state_response { + /** @brief read as don't care */ + uint32_t sram_state; + /** @brief state of power partition + * * 0 : off + * * 1 : on + */ + uint32_t logic_state; +} __ABI_PACKED; + +/** @} */ + +/** + * @ingroup MRQ_Codes + * @def MRQ_PG_UPDATE_STATE + * @brief modify the power-gating state of a partition + * + * * Platforms: T186 + * * Initiators: Any + * * Targets: BPMP + * * Request Payload: @ref mrq_pg_update_state_request + * * Response Payload: N/A + * @addtogroup Powergating + * @{ + */ + +/** + * @brief request with mrq_pg_update_state_request + * + * Used by #MRQ_PG_UPDATE_STATE call to request BPMP to change the + * state of a power partition #partition_id. + */ +struct mrq_pg_update_state_request { + /** @brief ID of partition */ + uint32_t partition_id; + /** @brief secondary control of power partition + * @details Ignored by many versions of the BPMP + * firmware. For maximum compatibility, set the value + * according to @logic_state + * * 0x1: power ON partition (@ref logic_state == 0x3) + * * 0x3: power OFF partition (@ref logic_state == 0x1) + */ + uint32_t sram_state; + /** @brief controls state of power partition, legal values are + * * 0x1 : power OFF partition + * * 0x3 : power ON partition + */ + uint32_t logic_state; + /** @brief change state of clocks of the power partition, legal values + * * 0x0 : do not change clock state + * * 0x1 : disable partition clocks (only applicable when + * @ref logic_state == 0x1) + * * 0x3 : enable partition clocks (only applicable when + * @ref logic_state == 0x3) + */ + uint32_t clock_state; +} __ABI_PACKED; +/** @} */ + +/** + * @ingroup MRQ_Codes + * @def MRQ_THERMAL + * @brief interact with BPMP thermal framework + * + * * Platforms: T186 + * * Initiators: Any + * * Targets: Any + * * Request Payload: TODO + * * Response Payload: TODO + * + * @addtogroup Thermal + * + * The BPMP firmware includes a thermal framework. Drivers within the + * bpmp firmware register with the framework to provide thermal + * zones. Each thermal zone corresponds to an entity whose temperature + * can be measured. The framework also has a notion of trip points. A + * trip point consists of a thermal zone id, a temperature, and a + * callback routine. The framework invokes the callback when the zone + * hits the indicated temperature. The BPMP firmware uses this thermal + * framework interally to implement various temperature-dependent + * functions. + * + * Software on the CPU can use #MRQ_THERMAL (with payload @ref + * mrq_thermal_host_to_bpmp_request) to interact with the BPMP thermal + * framework. The CPU must It can query the number of supported zones, + * query zone temperatures, and set trip points. + * + * When a trip point set by the CPU gets crossed, BPMP firmware issues + * an IPC to the CPU having mrq_request::mrq = #MRQ_THERMAL and a + * payload of @ref mrq_thermal_bpmp_to_host_request. + * @{ + */ +enum mrq_thermal_host_to_bpmp_cmd { + /** + * @brief Check whether the BPMP driver supports the specified + * request type. + * + * Host needs to supply request parameters. + * + * mrq_response::err is 0 if the specified request is + * supported and -#BPMP_ENODEV otherwise. + */ + CMD_THERMAL_QUERY_ABI = 0, + + /** + * @brief Get the current temperature of the specified zone. + * + * Host needs to supply request parameters. + * + * mrq_response::err is + * * 0: Temperature query succeeded. + * * -#BPMP_EINVAL: Invalid request parameters. + * * -#BPMP_ENOENT: No driver registered for thermal zone.. + * * -#BPMP_EFAULT: Problem reading temperature measurement. + */ + CMD_THERMAL_GET_TEMP = 1, + + /** + * @brief Enable or disable and set the lower and upper + * thermal limits for a thermal trip point. Each zone has + * one trip point. + * + * Host needs to supply request parameters. Once the + * temperature hits a trip point, the BPMP will send a message + * to the CPU having MRQ=MRQ_THERMAL and + * type=CMD_THERMAL_HOST_TRIP_REACHED + * + * mrq_response::err is + * * 0: Trip successfully set. + * * -#BPMP_EINVAL: Invalid request parameters. + * * -#BPMP_ENOENT: No driver registered for thermal zone. + * * -#BPMP_EFAULT: Problem setting trip point. + */ + CMD_THERMAL_SET_TRIP = 2, + + /** + * @brief Get the number of supported thermal zones. + * + * No request parameters required. + * + * mrq_response::err is always 0, indicating success. + */ + CMD_THERMAL_GET_NUM_ZONES = 3, + + /** @brief: number of supported host-to-bpmp commands. May + * increase in future + */ + CMD_THERMAL_HOST_TO_BPMP_NUM +}; + +enum mrq_thermal_bpmp_to_host_cmd { + /** + * @brief Indication that the temperature for a zone has + * exceeded the range indicated in the thermal trip point + * for the zone. + * + * BPMP needs to supply request parameters. Host only needs to + * acknowledge. + */ + CMD_THERMAL_HOST_TRIP_REACHED = 100, + + /** @brief: number of supported bpmp-to-host commands. May + * increase in future + */ + CMD_THERMAL_BPMP_TO_HOST_NUM +}; + +/* + * Host->BPMP request data for request type CMD_THERMAL_QUERY_ABI + * + * zone: Request type for which to check existence. + */ +struct cmd_thermal_query_abi_request { + uint32_t type; +} __ABI_PACKED; + +/* + * Host->BPMP request data for request type CMD_THERMAL_GET_TEMP + * + * zone: Number of thermal zone. + */ +struct cmd_thermal_get_temp_request { + uint32_t zone; +} __ABI_PACKED; + +/* + * BPMP->Host reply data for request CMD_THERMAL_GET_TEMP + * + * error: 0 if request succeeded. + * -BPMP_EINVAL if request parameters were invalid. + * -BPMP_ENOENT if no driver was registered for the specified thermal zone. + * -BPMP_EFAULT for other thermal zone driver errors. + * temp: Current temperature in millicelsius. + */ +struct cmd_thermal_get_temp_response { + int32_t temp; +} __ABI_PACKED; + +/* + * Host->BPMP request data for request type CMD_THERMAL_SET_TRIP + * + * zone: Number of thermal zone. + * low: Temperature of lower trip point in millicelsius + * high: Temperature of upper trip point in millicelsius + * enabled: 1 to enable trip point, 0 to disable trip point + */ +struct cmd_thermal_set_trip_request { + uint32_t zone; + int32_t low; + int32_t high; + uint32_t enabled; +} __ABI_PACKED; + +/* + * BPMP->Host request data for request type CMD_THERMAL_HOST_TRIP_REACHED + * + * zone: Number of thermal zone where trip point was reached. + */ +struct cmd_thermal_host_trip_reached_request { + uint32_t zone; +} __ABI_PACKED; + +/* + * BPMP->Host reply data for request type CMD_THERMAL_GET_NUM_ZONES + * + * num: Number of supported thermal zones. The thermal zones are indexed + * starting from zero. + */ +struct cmd_thermal_get_num_zones_response { + uint32_t num; +} __ABI_PACKED; + +/* + * Host->BPMP request data. + * + * Reply type is union mrq_thermal_bpmp_to_host_response. + * + * type: Type of request. Values listed in enum mrq_thermal_type. + * data: Request type specific parameters. + */ +struct mrq_thermal_host_to_bpmp_request { + uint32_t type; + union { + struct cmd_thermal_query_abi_request query_abi; + struct cmd_thermal_get_temp_request get_temp; + struct cmd_thermal_set_trip_request set_trip; + } __UNION_ANON; +} __ABI_PACKED; + +/* + * BPMP->Host request data. + * + * type: Type of request. Values listed in enum mrq_thermal_type. + * data: Request type specific parameters. + */ +struct mrq_thermal_bpmp_to_host_request { + uint32_t type; + union { + struct cmd_thermal_host_trip_reached_request host_trip_reached; + } __UNION_ANON; +} __ABI_PACKED; + +/* + * Data in reply to a Host->BPMP request. + */ +union mrq_thermal_bpmp_to_host_response { + struct cmd_thermal_get_temp_response get_temp; + struct cmd_thermal_get_num_zones_response get_num_zones; +} __ABI_PACKED; +/** @} */ + +/** + * @ingroup MRQ_Codes + * @def MRQ_CPU_VHINT + * @brief Query CPU voltage hint data + * + * * Platforms: T186 + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: @ref mrq_cpu_vhint_request + * * Response Payload: N/A + * + * @addtogroup Vhint CPU Voltage hint + * @{ + */ + +/** + * @brief request with #MRQ_CPU_VHINT + * + * Used by #MRQ_CPU_VHINT call by CCPLEX to retrieve voltage hint data + * from BPMP to memory space pointed by #addr. CCPLEX is responsible + * to allocate sizeof(cpu_vhint_data) sized block of memory and + * appropriately map it for BPMP before sending the request. + */ +struct mrq_cpu_vhint_request { + /** @brief IOVA address for the #cpu_vhint_data */ + uint32_t addr; /* struct cpu_vhint_data * */ + /** @brief ID of the cluster whose data is requested */ + uint32_t cluster_id; /* enum cluster_id */ +} __ABI_PACKED; + +/** + * @brief description of the CPU v/f relation + * + * Used by #MRQ_CPU_VHINT call to carry data pointed by #addr of + * struct mrq_cpu_vhint_request + */ +struct cpu_vhint_data { + uint32_t ref_clk_hz; /**< reference frequency in Hz */ + uint16_t pdiv; /**< post divider value */ + uint16_t mdiv; /**< input divider value */ + uint16_t ndiv_max; /**< fMAX expressed with max NDIV value */ + /** table of ndiv values as a function of vINDEX (voltage index) */ + uint16_t ndiv[80]; + /** minimum allowed NDIV value */ + uint16_t ndiv_min; + /** minimum allowed voltage hint value (as in vINDEX) */ + uint16_t vfloor; + /** maximum allowed voltage hint value (as in vINDEX) */ + uint16_t vceil; + /** post-multiplier for vindex value */ + uint16_t vindex_mult; + /** post-divider for vindex value */ + uint16_t vindex_div; + /** reserved for future use */ + uint16_t reserved[328]; +} __ABI_PACKED; + +/** @} */ + +/** + * @ingroup MRQ_Codes + * @def MRQ_ABI_RATCHET + * @brief ABI ratchet value query + * + * * Platforms: T186 + * * Initiators: Any + * * Targets: BPMP + * * Request Payload: @ref mrq_abi_ratchet_request + * * Response Payload: @ref mrq_abi_ratchet_response + * @addtogroup ABI_info + * @{ + */ + +/** + * @brief an ABI compatibility mechanism + * + * BPMP_ABI_RATCHET_VALUE may increase for various reasons in a future + * revision of this header file. + * 1. That future revision deprecates some MRQ + * 2. That future revision introduces a breaking change to an existing + * MRQ or + * 3. A bug is discovered in an existing implementation of the BPMP-FW + * (or possibly one of its clients) which warrants deprecating that + * implementation. + */ +#define BPMP_ABI_RATCHET_VALUE 3 + +/** + * @brief request with #MRQ_ABI_RATCHET. + * + * #ratchet should be #BPMP_ABI_RATCHET_VALUE from the ABI header + * against which the requester was compiled. + * + * If ratchet is less than BPMP's #BPMP_ABI_RATCHET_VALUE, BPMP may + * reply with mrq_response::err = -#BPMP_ERANGE to indicate that + * BPMP-FW cannot interoperate correctly with the requester. Requester + * should cease further communication with BPMP. + * + * Otherwise, err shall be 0. + */ +struct mrq_abi_ratchet_request { + /** @brief requester's ratchet value */ + uint16_t ratchet; +}; + +/** + * @brief response to #MRQ_ABI_RATCHET + * + * #ratchet shall be #BPMP_ABI_RATCHET_VALUE from the ABI header + * against which BPMP firwmare was compiled. + * + * If #ratchet is less than the requester's #BPMP_ABI_RATCHET_VALUE, + * the requster must either interoperate with BPMP according to an ABI + * header version with BPMP_ABI_RATCHET_VALUE = ratchet or cease + * communication with BPMP. + * + * If mrq_response::err is 0 and ratchet is greater than or equal to the + * requester's BPMP_ABI_RATCHET_VALUE, the requester should continue + * normal operation. + */ +struct mrq_abi_ratchet_response { + /** @brief BPMP's ratchet value */ + uint16_t ratchet; +}; +/** @} */ + +/** + * @ingroup MRQ_Codes + * @def MRQ_EMC_DVFS_LATENCY + * @brief query frequency dependent EMC DVFS latency + * + * * Platforms: T186 + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: N/A + * * Response Payload: @ref mrq_emc_dvfs_latency_response + * @addtogroup EMC + * @{ + */ + +/** + * @brief used by @ref mrq_emc_dvfs_latency_response + */ +struct emc_dvfs_latency { + /** @brief EMC frequency in kHz */ + uint32_t freq; + /** @brief EMC DVFS latency in nanoseconds */ + uint32_t latency; +} __ABI_PACKED; + +#define EMC_DVFS_LATENCY_MAX_SIZE 14 +/** + * @brief response to #MRQ_EMC_DVFS_LATENCY + */ +struct mrq_emc_dvfs_latency_response { + /** @brief the number valid entries in #pairs */ + uint32_t num_pairs; + /** @brief EMC <frequency, latency> information */ + struct emc_dvfs_latency pairs[EMC_DVFS_LATENCY_MAX_SIZE]; +} __ABI_PACKED; + +/** @} */ + +/** + * @ingroup MRQ_Codes + * @def MRQ_TRACE_ITER + * @brief manage the trace iterator + * + * * Platforms: All + * * Initiators: CCPLEX + * * Targets: BPMP + * * Request Payload: N/A + * * Response Payload: @ref mrq_trace_iter_request + * @addtogroup Trace + * @{ + */ +enum { + /** @brief (re)start the tracing now. Ignore older events */ + TRACE_ITER_INIT = 0, + /** @brief clobber all events in the trace buffer */ + TRACE_ITER_CLEAN = 1 +}; + +/** + * @brief request with #MRQ_TRACE_ITER + */ +struct mrq_trace_iter_request { + /** @brief TRACE_ITER_INIT or TRACE_ITER_CLEAN */ + uint32_t cmd; +} __ABI_PACKED; + +/** @} */ + +/* + * 4. Enumerations + */ + +/* + * 4.1 CPU enumerations + * + * See <mach-t186/system-t186.h> + * + * 4.2 CPU Cluster enumerations + * + * See <mach-t186/system-t186.h> + * + * 4.3 System low power state enumerations + * + * See <mach-t186/system-t186.h> + */ + +/* + * 4.4 Clock enumerations + * + * For clock enumerations, see <mach-t186/clk-t186.h> + */ + +/* + * 4.5 Reset enumerations + * + * For reset enumerations, see <mach-t186/reset-t186.h> + */ + +/* + * 4.6 Thermal sensor enumerations + * + * For thermal sensor enumerations, see <mach-t186/thermal-t186.h> + */ + +/** + * @defgroup Error_Codes + * Negative values for mrq_response::err generally indicate some + * error. The ABI defines the following error codes. Negating these + * defines is an exercise left to the user. + * @{ + */ +/** @brief No such file or directory */ +#define BPMP_ENOENT 2 +/** @brief No MRQ handler */ +#define BPMP_ENOHANDLER 3 +/** @brief I/O error */ +#define BPMP_EIO 5 +/** @brief Bad sub-MRQ command */ +#define BPMP_EBADCMD 6 +/** @brief Not enough memory */ +#define BPMP_ENOMEM 12 +/** @brief Permission denied */ +#define BPMP_EACCES 13 +/** @brief Bad address */ +#define BPMP_EFAULT 14 +/** @brief No such device */ +#define BPMP_ENODEV 19 +/** @brief Argument is a directory */ +#define BPMP_EISDIR 21 +/** @brief Invalid argument */ +#define BPMP_EINVAL 22 +/** @brief Timeout during operation */ +#define BPMP_ETIMEDOUT 23 +/** @brief Out of range */ +#define BPMP_ERANGE 34 +/** @} */ +/** @} */ +#endif diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h index e56031d1afa..7daf8bc1632 100644 --- a/arch/arm/include/asm/arch-tegra/clock.h +++ b/arch/arm/include/asm/arch-tegra/clock.h @@ -324,7 +324,7 @@ enum periph_id clk_id_to_periph_id(int clk_id); * @param p post divider(DIVP) * @param cpcon base PLL charge pump(CPCON) * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot - * be overriden), 1 if PLL is already correct + * be overridden), 1 if PLL is already correct */ int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon); diff --git a/arch/arm/include/asm/arch-tegra/ivc.h b/arch/arm/include/asm/arch-tegra/ivc.h new file mode 100644 index 00000000000..7f2287ae280 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra/ivc.h @@ -0,0 +1,179 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _ASM_ARCH_TEGRA_IVC_H +#define _ASM_ARCH_TEGRA_IVC_H + +#include <common.h> + +/* + * Tegra IVC is a communication protocol that transfers fixed-size frames + * bi-directionally and in-order between the local CPU and some remote entity. + * Communication is via a statically sized and allocated buffer in shared + * memory and a notification mechanism. + * + * This API handles all aspects of the shared memory buffer's metadata, and + * leaves all aspects of the frame content to the calling code; frames + * typically contain some higher-level protocol. The notification mechanism is + * also handled externally to this API, since it can vary from instance to + * instance. + * + * The client model is to first find some free (for TX) or filled (for RX) + * frame, process that frame's memory buffer (fill or read it), and then + * inform the protocol that the frame has been filled/read, i.e. advance the + * write/read pointer. If the channel is full, there may be no available frames + * to fill/read. In this case, client code may either poll for an available + * frame, or wait for the remote entity to send a notification to the local + * CPU. + */ + +/** + * struct tegra_ivc - In-memory shared memory layout. + * + * This is described in detail in ivc.c. + */ +struct tegra_ivc_channel_header; + +/** + * struct tegra_ivc - Software state of an IVC channel. + * + * This state is internal to the IVC code and should not be accessed directly + * by clients. It is public solely so clients can allocate storage for the + * structure. + */ +struct tegra_ivc { + /** + * rx_channel - Pointer to the shared memory region used to receive + * messages from the remote entity. + */ + struct tegra_ivc_channel_header *rx_channel; + /** + * tx_channel - Pointer to the shared memory region used to send + * messages to the remote entity. + */ + struct tegra_ivc_channel_header *tx_channel; + /** + * r_pos - The position in list of frames in rx_channel that we are + * reading from. + */ + uint32_t r_pos; + /** + * w_pos - The position in list of frames in tx_channel that we are + * writing to. + */ + uint32_t w_pos; + /** + * nframes - The number of frames allocated (in each direction) in + * shared memory. + */ + uint32_t nframes; + /** + * frame_size - The size of each frame in shared memory. + */ + uint32_t frame_size; + /** + * notify - Function to call to notify the remote processor of a + * change in channel state. + */ + void (*notify)(struct tegra_ivc *); +}; + +/** + * tegra_ivc_read_get_next_frame - Locate the next frame to receive. + * + * Locate the next frame to be received/processed, return the address of the + * frame, and do not remove it from the queue. Repeated calls to this function + * will return the same address until tegra_ivc_read_advance() is called. + * + * @ivc The IVC channel. + * @frame Pointer to be filled with the address of the frame to receive. + * + * @return 0 if a frame is available, else a negative error code. + */ +int tegra_ivc_read_get_next_frame(struct tegra_ivc *ivc, void **frame); + +/** + * tegra_ivc_read_advance - Advance the read queue. + * + * Inform the protocol and remote entity that the frame returned by + * tegra_ivc_read_get_next_frame() has been processed. The remote end may then + * re-use it to transmit further data. Subsequent to this function returning, + * tegra_ivc_read_get_next_frame() will return a different frame. + * + * @ivc The IVC channel. + * + * @return 0 if OK, else a negative error code. + */ +int tegra_ivc_read_advance(struct tegra_ivc *ivc); + +/** + * tegra_ivc_write_get_next_frame - Locate the next frame to fill for transmit. + * + * Locate the next frame to be filled for transmit, return the address of the + * frame, and do not add it to the queue. Repeated calls to this function + * will return the same address until tegra_ivc_read_advance() is called. + * + * @ivc The IVC channel. + * @frame Pointer to be filled with the address of the frame to fill. + * + * @return 0 if a frame is available, else a negative error code. + */ +int tegra_ivc_write_get_next_frame(struct tegra_ivc *ivc, void **frame); + +/** + * tegra_ivc_write_advance - Advance the write queue. + * + * Inform the protocol and remote entity that the frame returned by + * tegra_ivc_write_get_next_frame() has been filled and should be transmitted. + * The remote end may then read data from it. Subsequent to this function + * returning, tegra_ivc_write_get_next_frame() will return a different frame. + * + * @ivc The IVC channel. + * + * @return 0 if OK, else a negative error code. + */ +int tegra_ivc_write_advance(struct tegra_ivc *ivc); + +/** + * tegra_ivc_channel_notified - handle internal messages + * + * This function must be called following every notification. + * + * @ivc The IVC channel. + * + * @return 0 if the channel is ready for communication, or -EAGAIN if a + * channel reset is in progress. + */ +int tegra_ivc_channel_notified(struct tegra_ivc *ivc); + +/** + * tegra_ivc_channel_reset - initiates a reset of the shared memory state + * + * This function must be called after a channel is initialized but before it + * is used for communication. The channel will be ready for use when a + * subsequent call to notify the remote of the channel reset indicates the + * reset operation is complete. + * + * @ivc The IVC channel. + */ +void tegra_ivc_channel_reset(struct tegra_ivc *ivc); + +/** + * tegra_ivc_init - Initialize a channel's software state. + * + * @ivc The IVC channel. + * @rx_base Address of the the RX shared memory buffer. + * @tx_base Address of the the TX shared memory buffer. + * @nframes Number of frames in each shared memory buffer. + * @frame_size Size of each frame. + * + * @return 0 if OK, else a negative error code. + */ +int tegra_ivc_init(struct tegra_ivc *ivc, ulong rx_base, ulong tx_base, + uint32_t nframes, uint32_t frame_size, + void (*notify)(struct tegra_ivc *)); + +#endif diff --git a/arch/arm/include/asm/arch-tegra/tegra_mmc.h b/arch/arm/include/asm/arch-tegra/tegra_mmc.h index 75e56c4ea78..07ef4c04c85 100644 --- a/arch/arm/include/asm/arch-tegra/tegra_mmc.h +++ b/arch/arm/include/asm/arch-tegra/tegra_mmc.h @@ -9,6 +9,9 @@ #ifndef __TEGRA_MMC_H_ #define __TEGRA_MMC_H_ +#include <common.h> +#include <clk.h> +#include <reset.h> #include <fdtdec.h> #include <asm/gpio.h> @@ -134,7 +137,10 @@ struct mmc_host { int id; /* device id/number, 0-3 */ int enabled; /* 1 to enable, 0 to disable */ int width; /* Bus Width, 1, 4 or 8 */ -#ifndef CONFIG_TEGRA186 +#ifdef CONFIG_TEGRA186 + struct reset_ctl reset_ctl; + struct clk clk; +#else enum periph_id mmc_id; /* Peripheral ID: PERIPH_ID_... */ #endif struct gpio_desc cd_gpio; /* Change Detect GPIO */ diff --git a/arch/arm/include/asm/arch-tegra124/display.h b/arch/arm/include/asm/arch-tegra124/display.h index ca6644af345..c522faa9367 100644 --- a/arch/arm/include/asm/arch-tegra124/display.h +++ b/arch/arm/include/asm/arch-tegra124/display.h @@ -11,7 +11,7 @@ /** * Register a new display based on device tree configuration. * - * The frame buffer can be positioned by U-Boot or overriden by the fdt. + * The frame buffer can be positioned by U-Boot or overridden by the fdt. * You should pass in the U-Boot address here, and check the contents of * struct fdt_disp_config to see what was actually chosen. * diff --git a/arch/arm/include/asm/arch-zynqmp/clk.h b/arch/arm/include/asm/arch-zynqmp/clk.h index b18333d1ca2..bfd53b53058 100644 --- a/arch/arm/include/asm/arch-zynqmp/clk.h +++ b/arch/arm/include/asm/arch-zynqmp/clk.h @@ -8,7 +8,6 @@ #ifndef _ASM_ARCH_CLK_H_ #define _ASM_ARCH_CLK_H_ -unsigned long get_uart_clk(int dev_id); unsigned long zynqmp_get_system_timer_freq(void); #endif /* _ASM_ARCH_CLK_H_ */ diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h index 423fc701116..a20702e612b 100644 --- a/arch/arm/include/asm/armv7.h +++ b/arch/arm/include/asm/armv7.h @@ -126,6 +126,8 @@ void _smp_pen(void); extern char __secure_start[]; extern char __secure_end[]; +extern char __secure_stack_start[]; +extern char __secure_stack_end[]; #endif /* CONFIG_ARMV7_NONSEC */ diff --git a/arch/arm/include/asm/armv7m.h b/arch/arm/include/asm/armv7m.h index 200444dda14..54d8a2bdff6 100644 --- a/arch/arm/include/asm/armv7m.h +++ b/arch/arm/include/asm/armv7m.h @@ -51,10 +51,21 @@ struct v7m_mpu { #define V7M_MPU_CTRL_ENABLE (1 << 0) #define V7M_MPU_CTRL_HFNMIENA (1 << 1) +#define V7M_MPU_CTRL_ENABLE (1 << 0) +#define V7M_MPU_CTRL_DISABLE (0 << 0) +#define V7M_MPU_CTRL_HFNMIENA (1 << 1) + #define V7M_MPU_RASR_EN (1 << 0) #define V7M_MPU_RASR_SIZE_BITS 1 #define V7M_MPU_RASR_SIZE_4GB (31 << V7M_MPU_RASR_SIZE_BITS) +#define V7M_MPU_RASR_SIZE_8MB (24 << V7M_MPU_RASR_SIZE_BITS) +#define V7M_MPU_RASR_TEX_SHIFT 19 +#define V7M_MPU_RASR_S_SHIFT 18 +#define V7M_MPU_RASR_C_SHIFT 17 +#define V7M_MPU_RASR_B_SHIFT 16 #define V7M_MPU_RASR_AP_RW_RW (3 << 24) +#define V7M_MPU_RASR_XN_ENABLE (0 << 28) +#define V7M_MPU_RASR_XN_DISABLE (1 << 28) #endif /* !defined(__ASSEMBLY__) */ #endif /* ARMV7M_H */ diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 0d08ed3ba81..aa0f3c42f63 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -135,12 +135,15 @@ static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr) } struct mm_region { - u64 base; + u64 virt; + u64 phys; u64 size; u64 attrs; }; extern struct mm_region *mem_map; +void setup_pgtables(void); +u64 get_tcr(int el, u64 *pips, u64 *pva_bits); #endif #endif /* _ASM_ARMV8_MMU_H_ */ diff --git a/arch/arm/include/asm/armv8/sec_firmware.h b/arch/arm/include/asm/armv8/sec_firmware.h new file mode 100644 index 00000000000..eb68185feda --- /dev/null +++ b/arch/arm/include/asm/armv8/sec_firmware.h @@ -0,0 +1,22 @@ +/* + * Copyright 2016 NXP Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __SEC_FIRMWARE_H_ +#define __SEC_FIRMWARE_H_ + +#ifdef CONFIG_FSL_LS_PPA +#include <asm/arch/ppa.h> +#endif + +int sec_firmware_init(const void *, u32 *, u32 *); +int _sec_firmware_entry(const void *, u32 *, u32 *); +bool sec_firmware_is_valid(const void *); +#ifdef CONFIG_ARMV8_PSCI +unsigned int sec_firmware_support_psci_version(void); +unsigned int _sec_firmware_support_psci_version(void); +#endif + +#endif /* __SEC_FIRMWARE_H_ */ diff --git a/arch/arm/include/asm/barriers.h b/arch/arm/include/asm/barriers.h index 37870f9d717..04784b7cb62 100644 --- a/arch/arm/include/asm/barriers.h +++ b/arch/arm/include/asm/barriers.h @@ -30,15 +30,22 @@ #endif /* !CONFIG_ARM64 */ -#if defined(__ARM_ARCH_7A__) || defined(CONFIG_ARM64) +#if __LINUX_ARM_ARCH__ >= 7 #define ISB asm volatile ("isb sy" : : : "memory") #define DSB asm volatile ("dsb sy" : : : "memory") #define DMB asm volatile ("dmb sy" : : : "memory") -#else +#elif __LINUX_ARM_ARCH__ == 6 #define ISB CP15ISB #define DSB CP15DSB #define DMB CP15DMB +#else +#define ISB asm volatile ("" : : : "memory") +#define DSB CP15DSB +#define DMB asm volatile ("" : : : "memory") #endif +#define isb() ISB +#define dsb() DSB +#define dmb() DMB #endif /* __ASSEMBLY__ */ #endif /* __BARRIERS_H__ */ diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index 1f63127bdc8..16e65c36a9a 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -29,6 +29,8 @@ static inline void invalidate_l2_cache(void) } #endif +int check_cache_range(unsigned long start, unsigned long stop); + void l2_cache_enable(void); void l2_cache_disable(void); void set_section_dcache(int section, enum dcache_option option); diff --git a/arch/arm/include/asm/config.h b/arch/arm/include/asm/config.h index 435fc4521c2..1ad221a9876 100644 --- a/arch/arm/include/asm/config.h +++ b/arch/arm/include/asm/config.h @@ -11,7 +11,6 @@ #define CONFIG_SYS_BOOT_RAMDISK_HIGH #ifdef CONFIG_ARM64 -#define CONFIG_PHYS_64BIT #define CONFIG_STATIC_RELA #endif diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 53cd7550a06..b35c271bba1 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -17,8 +17,6 @@ #ifdef CONFIG_CHAIN_OF_TRUST #define CONFIG_CMD_ESBC_VALIDATE -#define CONFIG_CMD_BLOB -#define CONFIG_CMD_HASH #define CONFIG_FSL_SEC_MON #define CONFIG_SHA_HW_ACCEL #define CONFIG_SHA_PROG_HW_ACCEL @@ -28,6 +26,28 @@ #define CONFIG_FSL_CAAM #endif +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_DM 1 +#define CONFIG_SPL_CRYPTO_SUPPORT +#define CONFIG_SPL_HASH_SUPPORT +#define CONFIG_SPL_RSA +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +/* + * Define the key hash for U-Boot here if public/private key pair used to + * sign U-boot are different from the SRK hash put in the fuse + * Example of defining KEY_HASH is + * #define CONFIG_SPL_UBOOT_KEY_HASH \ + * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" + * else leave it defined as NULL + */ + +#define CONFIG_SPL_UBOOT_KEY_HASH NULL +#endif /* ifdef CONFIG_SPL_BUILD */ + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_CMD_BLOB +#define CONFIG_CMD_HASH #define CONFIG_KEY_REVOCATION #ifndef CONFIG_SYS_RAMBOOT /* The key used for verification of next level images @@ -58,39 +78,55 @@ "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" #else #define CONFIG_EXTRA_ENV \ - "setenv fdt_high 0xcfffffff;" \ - "setenv initrd_high 0xcfffffff;" \ + "setenv fdt_high 0xffffffff;" \ + "setenv initrd_high 0xffffffff;" \ "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" #endif /* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from * Non-XIP Memory (Nand/SD)*/ -#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A) +#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A) || \ + defined(CONFIG_SD_BOOT) #define CONFIG_BOOTSCRIPT_COPY_RAM #endif -/* The address needs to be modified according to NOR and DDR memory map */ +/* The address needs to be modified according to NOR, NAND, SD and + * DDR memory map + */ #ifdef CONFIG_LS2080A -#define CONFIG_BS_HDR_ADDR_FLASH 0x583920000 -#define CONFIG_BS_ADDR_FLASH 0x583900000 +#define CONFIG_BS_HDR_ADDR_DEVICE 0x583920000 +#define CONFIG_BS_ADDR_DEVICE 0x583900000 #define CONFIG_BS_HDR_ADDR_RAM 0xa3920000 #define CONFIG_BS_ADDR_RAM 0xa3900000 +#define CONFIG_BS_HDR_SIZE 0x00002000 +#define CONFIG_BS_SIZE 0x00001000 +#else +#ifdef CONFIG_SD_BOOT +/* For SD boot address and size are assigned in terms of sector + * offset and no. of sectors respectively. + */ +#define CONFIG_BS_HDR_ADDR_DEVICE 0x00000800 +#define CONFIG_BS_ADDR_DEVICE 0x00000840 +#define CONFIG_BS_HDR_SIZE 0x00000010 +#define CONFIG_BS_SIZE 0x00000008 #else -#define CONFIG_BS_HDR_ADDR_FLASH 0x600a0000 -#define CONFIG_BS_ADDR_FLASH 0x60060000 -#define CONFIG_BS_HDR_ADDR_RAM 0xa0060000 -#define CONFIG_BS_ADDR_RAM 0xa0060000 +#define CONFIG_BS_HDR_ADDR_DEVICE 0x600a0000 +#define CONFIG_BS_ADDR_DEVICE 0x60060000 +#define CONFIG_BS_HDR_SIZE 0x00002000 +#define CONFIG_BS_SIZE 0x00001000 +#endif /* #ifdef CONFIG_SD_BOOT */ +#define CONFIG_BS_HDR_ADDR_RAM 0x81000000 +#define CONFIG_BS_ADDR_RAM 0x81020000 #endif #ifdef CONFIG_BOOTSCRIPT_COPY_RAM #define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM -#define CONFIG_BS_HDR_SIZE 0x00002000 #define CONFIG_BOOTSCRIPT_ADDR CONFIG_BS_ADDR_RAM -#define CONFIG_BS_SIZE 0x00001000 #else -#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_FLASH -/* BS_HDR_SIZE, BOOTSCRIPT_ADDR and BS_SIZE are not required */ +#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_DEVICE +/* BOOTSCRIPT_ADDR is not required */ #endif #include <config_fsl_chain_trust.h> +#endif /* #ifndef CONFIG_SPL_BUILD */ #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */ #endif diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 77d2653e27a..10550174df4 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -44,6 +44,21 @@ struct arch_global_data { unsigned long tlb_emerg; #endif #endif +#ifdef CONFIG_SYS_MEM_RESERVE_SECURE +#define MEM_RESERVE_SECURE_SECURED 0x1 +#define MEM_RESERVE_SECURE_MAINTAINED 0x2 +#define MEM_RESERVE_SECURE_ADDR_MASK (~0x3) + /* + * Secure memory addr + * This variable needs maintenance if the RAM base is not zero, + * or if RAM splits into non-consecutive banks. It also has a + * flag indicating the secure memory is marked as secure by MMU. + * Flags used: 0x1 secured + * 0x2 maintained + */ + phys_addr_t secure_ram; + unsigned long tlb_allocated; +#endif #ifdef CONFIG_OMAP_COMMON u32 omap_boot_device; diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 9d185a61223..5834f5b3dc9 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -25,6 +25,7 @@ #include <linux/types.h> #include <asm/byteorder.h> #include <asm/memory.h> +#include <asm/barriers.h> #if 0 /* XXX###XXX */ #include <asm/arch/hardware.h> #endif /* XXX###XXX */ @@ -136,8 +137,7 @@ static inline void __raw_readsl(unsigned long addr, void *data, int longlen) * TODO: The kernel offers some more advanced versions of barriers, it might * have some advantages to use them instead of the simple one here. */ -#define mb() asm volatile("dsb sy" : : : "memory") -#define dmb() __asm__ __volatile__ ("" : : : "memory") +#define mb() dsb() #define __iormb() dmb() #define __iowmb() dmb() @@ -292,40 +292,6 @@ static inline void __raw_readsl(unsigned long addr, void *data, int longlen) #define readsb(a, d, s) __raw_readsb((unsigned long)a, d, s) /* - * ioremap and friends. - * - * ioremap takes a PCI memory address, as specified in - * linux/Documentation/IO-mapping.txt. If you want a - * physical address, use __ioremap instead. - */ -extern void * __ioremap(unsigned long offset, size_t size, unsigned long flags); -extern void __iounmap(void *addr); - -/* - * Generic ioremap support. - * - * Define: - * iomem_valid_addr(off,size) - * iomem_to_phys(off) - */ -#ifdef iomem_valid_addr -#define __arch_ioremap(off,sz,nocache) \ - ({ \ - unsigned long _off = (off), _size = (sz); \ - void *_ret = (void *)0; \ - if (iomem_valid_addr(_off, _size)) \ - _ret = __ioremap(iomem_to_phys(_off),_size,nocache); \ - _ret; \ - }) - -#define __arch_iounmap __iounmap -#endif - -#define ioremap(off,sz) __arch_ioremap((off),(sz),0) -#define ioremap_nocache(off,sz) __arch_ioremap((off),(sz),1) -#define iounmap(_addr) __arch_iounmap(_addr) - -/* * DMA-consistent mapping functions. These allocate/free a region of * uncached, unwrite-buffered mapped memory space for use with DMA * devices. This is the "generic" version. The PCI specific version diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 07f384867eb..605c549f0a5 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -627,6 +627,12 @@ void recalibrate_iodelay(void); void omap_smc1(u32 service, u32 val); +/* + * Low-level helper function used when performing secure ROM calls on high- + * security (HS) device variants by doing a specially-formed smc entry. + */ +u32 omap_smc_sec(u32 service, u32 proc_id, u32 flag, u32 *params); + void enable_edma3_clocks(void); void disable_edma3_clocks(void); diff --git a/arch/arm/include/asm/omap_sec_common.h b/arch/arm/include/asm/omap_sec_common.h new file mode 100644 index 00000000000..842f2af8d12 --- /dev/null +++ b/arch/arm/include/asm/omap_sec_common.h @@ -0,0 +1,30 @@ +/* + * (C) Copyright 2016 + * Texas Instruments, <www.ti.com> + * + * Andreas Dannenberg <dannenberg@ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _OMAP_SEC_COMMON_H_ +#define _OMAP_SEC_COMMON_H_ + +#include <common.h> + +/* + * Invoke secure ROM API on high-security (HS) device variants. It formats + * the variable argument list into the format expected by the ROM code before + * triggering the actual low-level smc entry. + */ +u32 secure_rom_call(u32 service, u32 proc_id, u32 flag, ...); + +/* + * Invoke a secure ROM API on high-secure (HS) device variants that can be used + * to verify a secure blob by authenticating and optionally decrypting it. The + * exact operation performed depends on how the certificate that was embedded + * into the blob during the signing/encryption step when the secure blob was + * first created. + */ +int secure_boot_verify_image(void **p_image, size_t *p_size); + +#endif /* _OMAP_SEC_COMMON_H_ */ diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h index bc5edda73f0..5b8ce4d31bd 100644 --- a/arch/arm/include/asm/psci.h +++ b/arch/arm/include/asm/psci.h @@ -18,6 +18,9 @@ #ifndef __ARM_PSCI_H__ #define __ARM_PSCI_H__ +#define ARM_PSCI_VER_1_0 (0x00010000) +#define ARM_PSCI_VER_0_2 (0x00000002) + /* PSCI 0.1 interface */ #define ARM_PSCI_FN_BASE 0x95c1ba5e #define ARM_PSCI_FN(n) (ARM_PSCI_FN_BASE + (n)) @@ -31,6 +34,12 @@ #define ARM_PSCI_RET_NI (-1) #define ARM_PSCI_RET_INVAL (-2) #define ARM_PSCI_RET_DENIED (-3) +#define ARM_PSCI_RET_ALREADY_ON (-4) +#define ARM_PSCI_RET_ON_PENDING (-5) +#define ARM_PSCI_RET_INTERNAL_FAILURE (-6) +#define ARM_PSCI_RET_NOT_PRESENT (-7) +#define ARM_PSCI_RET_DISABLED (-8) +#define ARM_PSCI_RET_INVALID_ADDRESS (-9) /* PSCI 0.2 interface */ #define ARM_PSCI_0_2_FN_BASE 0x84000000 @@ -47,16 +56,39 @@ #define ARM_PSCI_0_2_FN_SYSTEM_OFF ARM_PSCI_0_2_FN(8) #define ARM_PSCI_0_2_FN_SYSTEM_RESET ARM_PSCI_0_2_FN(9) +/* PSCI 1.0 interface */ +#define ARM_PSCI_1_0_FN_PSCI_FEATURES ARM_PSCI_0_2_FN(10) +#define ARM_PSCI_1_0_FN_CPU_FREEZE ARM_PSCI_0_2_FN(11) +#define ARM_PSCI_1_0_FN_CPU_DEFAULT_SUSPEND ARM_PSCI_0_2_FN(12) +#define ARM_PSCI_1_0_FN_NODE_HW_STATE ARM_PSCI_0_2_FN(13) +#define ARM_PSCI_1_0_FN_SYSTEM_SUSPEND ARM_PSCI_0_2_FN(14) +#define ARM_PSCI_1_0_FN_SET_SUSPEND_MODE ARM_PSCI_0_2_FN(15) +#define ARM_PSCI_1_0_FN_STAT_RESIDENCY ARM_PSCI_0_2_FN(16) +#define ARM_PSCI_1_0_FN_STAT_COUNT ARM_PSCI_0_2_FN(17) + +/* 1KB stack per core */ +#define ARM_PSCI_STACK_SHIFT 10 +#define ARM_PSCI_STACK_SIZE (1 << ARM_PSCI_STACK_SHIFT) + +/* PSCI affinity level state returned by AFFINITY_INFO */ +#define PSCI_AFFINITY_LEVEL_ON 0 +#define PSCI_AFFINITY_LEVEL_OFF 1 +#define PSCI_AFFINITY_LEVEL_ON_PENDING 2 + #ifndef __ASSEMBLY__ #include <asm/types.h> +/* These 2 helper functions assume cpu < CONFIG_ARMV7_PSCI_NR_CPUS */ +u32 psci_get_target_pc(int cpu); +void psci_save_target_pc(int cpu, u32 pc); + void psci_cpu_entry(void); u32 psci_get_cpu_id(void); -u32 psci_get_cpu_stack_top(int cpu); void psci_cpu_off_common(void); int psci_update_dt(void *fdt); void psci_board_init(void); +int fdt_psci(void *fdt); #endif /* ! __ASSEMBLY__ */ #endif /* __ARM_PSCI_H__ */ diff --git a/arch/arm/include/asm/secure.h b/arch/arm/include/asm/secure.h index effdb1858d8..5a403bc0f15 100644 --- a/arch/arm/include/asm/secure.h +++ b/arch/arm/include/asm/secure.h @@ -3,6 +3,9 @@ #include <config.h> +#define __secure __attribute__ ((section ("._secure.text"))) +#define __secure_data __attribute__ ((section ("._secure.data"))) + #ifdef CONFIG_ARMV7_SECURE_BASE /* * Warning, horror ahead. diff --git a/arch/arm/include/asm/setjmp.h b/arch/arm/include/asm/setjmp.h index ae738b2457b..f7b97efc59d 100644 --- a/arch/arm/include/asm/setjmp.h +++ b/arch/arm/include/asm/setjmp.h @@ -43,6 +43,7 @@ static inline int setjmp(jmp_buf jmp) #else asm volatile( #ifdef CONFIG_SYS_THUMB_BUILD + ".align 2\n" "adr r0, jmp_target\n" "add r0, r0, $1\n" #else @@ -52,7 +53,8 @@ static inline int setjmp(jmp_buf jmp) "mov r2, sp\n" "stm r1!, {r0, r2, r4, r5, r6, r7}\n" "b 2f\n" - "jmp_target: " + ".align 2\n" + "jmp_target: \n" "mov %0, #1\n" "2:\n" : "+l" (r) diff --git a/arch/arm/include/asm/spin_table.h b/arch/arm/include/asm/spin_table.h new file mode 100644 index 00000000000..8b57539f8d0 --- /dev/null +++ b/arch/arm/include/asm/spin_table.h @@ -0,0 +1,14 @@ +/* + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_SPIN_TABLE_H__ +#define __ASM_SPIN_TABLE_H__ + +extern u64 spin_table_cpu_release_addr; +extern char spin_table_reserve_begin; +extern char spin_table_reserve_end; + +int spin_table_update_dt(void *fdt); + +#endif /* __ASM_SPIN_TABLE_H__ */ diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 2bdc0bec824..7b7b8675215 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -3,6 +3,7 @@ #include <common.h> #include <linux/compiler.h> +#include <asm/barriers.h> #ifdef CONFIG_ARM64 @@ -34,11 +35,6 @@ enum dcache_option { DCACHE_WRITEALLOC = 4 << 2, }; -#define isb() \ - ({asm volatile( \ - "isb" : : : "memory"); \ - }) - #define wfi() \ ({asm volatile( \ "wfi" : : : "memory"); \ @@ -227,8 +223,6 @@ void __noreturn psci_system_reset(bool smc); */ void save_boot_params_ret(void); -#define isb() __asm__ __volatile__ ("" : : : "memory") - #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t"); #ifdef __ARM_ARCH_7A__ diff --git a/arch/arm/include/asm/types.h b/arch/arm/include/asm/types.h index d108915ff5c..9af7353f086 100644 --- a/arch/arm/include/asm/types.h +++ b/arch/arm/include/asm/types.h @@ -71,5 +71,4 @@ typedef u32 dma_addr_t; #endif /* __KERNEL__ */ -typedef unsigned long resource_size_t; #endif diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 0e05e87deaf..caa62c63558 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -26,12 +26,15 @@ endif obj-$(CONFIG_CPU_V7M) += cmd_boot.o obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o +obj-$(CONFIG_CMD_BOOTI) += bootm.o obj-$(CONFIG_CMD_BOOTM) += bootm.o +obj-$(CONFIG_CMD_BOOTZ) += bootm.o zimage.o obj-$(CONFIG_SYS_L2_PL310) += cache-pl310.o obj-$(CONFIG_USE_ARCH_MEMSET) += memset.o obj-$(CONFIG_USE_ARCH_MEMCPY) += memcpy.o else obj-$(CONFIG_SPL_FRAMEWORK) += spl.o +obj-$(CONFIG_SPL_FRAMEWORK) += zimage.o endif obj-$(CONFIG_SEMIHOSTING) += semihosting.o @@ -55,6 +58,8 @@ ifndef CONFIG_ARM64 obj-y += cache-cp15.o endif +obj-y += psci-dt.o + obj-$(CONFIG_DEBUG_LL) += debug.o # For EABI conformant tool chains, provide eabi_compat() @@ -63,11 +68,6 @@ extra-y += eabi_compat.o endif asflags-y += -DCONFIG_ARM_ASM_UNIFIED -ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TEGRA),yy) -asflags-y += -D__LINUX_ARM_ARCH__=4 -else -asflags-y += -D__LINUX_ARM_ARCH__=$(CONFIG_SYS_ARM_ARCH) -endif # some files can only build in ARM or THUMB2, not THUMB1 diff --git a/arch/arm/lib/bootm-fdt.c b/arch/arm/lib/bootm-fdt.c index 76b75d8e464..a51755070bc 100644 --- a/arch/arm/lib/bootm-fdt.c +++ b/arch/arm/lib/bootm-fdt.c @@ -21,9 +21,11 @@ #include <asm/armv7.h> #endif #include <asm/psci.h> +#include <asm/spin_table.h> DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_ARCH_FIXUP_FDT int arch_fixup_fdt(void *blob) { bd_t *bd = gd->bd; @@ -45,7 +47,13 @@ int arch_fixup_fdt(void *blob) if (ret) return ret; -#ifdef CONFIG_ARMV7_NONSEC +#ifdef CONFIG_ARMV8_SPIN_TABLE + ret = spin_table_update_dt(blob); + if (ret) + return ret; +#endif + +#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV8_PSCI) ret = psci_update_dt(blob); if (ret) return ret; @@ -53,3 +61,4 @@ int arch_fixup_fdt(void *blob) return 0; } +#endif diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 0838d89907b..53c3141322a 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -248,15 +248,20 @@ static void boot_prep_linux(bootm_headers_t *images) } } -#ifdef CONFIG_ARMV7_NONSEC -bool armv7_boot_nonsec(void) +__weak bool armv7_boot_nonsec_default(void) { - char *s = getenv("bootm_boot_mode"); #ifdef CONFIG_ARMV7_BOOT_SEC_DEFAULT - bool nonsec = false; + return false; #else - bool nonsec = true; + return true; #endif +} + +#ifdef CONFIG_ARMV7_NONSEC +bool armv7_boot_nonsec(void) +{ + char *s = getenv("bootm_boot_mode"); + bool nonsec = armv7_boot_nonsec_default(); if (s && !strcmp(s, "sec")) nonsec = false; @@ -358,38 +363,6 @@ int do_bootm_linux(int flag, int argc, char * const argv[], return 0; } -#ifdef CONFIG_CMD_BOOTZ - -struct zimage_header { - uint32_t code[9]; - uint32_t zi_magic; - uint32_t zi_start; - uint32_t zi_end; -}; - -#define LINUX_ARM_ZIMAGE_MAGIC 0x016f2818 - -int bootz_setup(ulong image, ulong *start, ulong *end) -{ - struct zimage_header *zi; - - zi = (struct zimage_header *)map_sysmem(image, 0); - if (zi->zi_magic != LINUX_ARM_ZIMAGE_MAGIC) { - puts("Bad Linux ARM zImage magic!\n"); - return 1; - } - - *start = zi->zi_start; - *end = zi->zi_end; - - printf("Kernel image @ %#08lx [ %#08lx - %#08lx ]\n", image, *start, - *end); - - return 0; -} - -#endif /* CONFIG_CMD_BOOTZ */ - #if defined(CONFIG_BOOTM_VXWORKS) void boot_prep_vxworks(bootm_headers_t *images) { @@ -399,8 +372,10 @@ void boot_prep_vxworks(bootm_headers_t *images) if (images->ft_addr) { off = fdt_path_offset(images->ft_addr, "/memory"); if (off < 0) { +#ifdef CONFIG_ARCH_FIXUP_FDT if (arch_fixup_fdt(images->ft_addr)) puts("## WARNING: fixup memory failed!\n"); +#endif } } #endif diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 3bd87105c58..d330b09434a 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -10,6 +10,10 @@ #include <common.h> #include <malloc.h> +#ifndef CONFIG_SYS_CACHELINE_SIZE +#define CONFIG_SYS_CACHELINE_SIZE 32 +#endif + /* * Flush range from all levels of d-cache/unified-cache. * Affects the range [start, start + size - 1]. @@ -46,6 +50,24 @@ __weak void flush_dcache_range(unsigned long start, unsigned long stop) /* An empty stub, real implementation should be in platform code */ } +int check_cache_range(unsigned long start, unsigned long stop) +{ + int ok = 1; + + if (start & (CONFIG_SYS_CACHELINE_SIZE - 1)) + ok = 0; + + if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1)) + ok = 0; + + if (!ok) { + warn_non_spl("CACHE: Misaligned operation at range [%08lx, %08lx]\n", + start, stop); + } + + return ok; +} + #ifdef CONFIG_SYS_NONCACHED_MEMORY /* * Reserve one MMU section worth of address space below the malloc() area that diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S index cad22c7b41f..91b19e00da2 100644 --- a/arch/arm/lib/crt0_64.S +++ b/arch/arm/lib/crt0_64.S @@ -108,6 +108,7 @@ relocation_return: * Set up final (full) environment */ bl c_runtime_cpu_setup /* still call old routine */ +#endif /* !CONFIG_SPL_BUILD */ /* TODO: For SPL, call spl_relocate_stack_gd() to alloc stack relocation */ @@ -130,6 +131,4 @@ clear_loop: /* NOTREACHED - board_init_r() does not return */ -#endif /* !CONFIG_SPL_BUILD */ - ENDPROC(_main) diff --git a/arch/arm/lib/psci-dt.c b/arch/arm/lib/psci-dt.c new file mode 100644 index 00000000000..baf6d7083f0 --- /dev/null +++ b/arch/arm/lib/psci-dt.c @@ -0,0 +1,117 @@ +/* + * Copyright 2016 NXP Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <linux/sizes.h> +#include <linux/kernel.h> +#include <asm/psci.h> +#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT +#include <asm/armv8/sec_firmware.h> +#endif + +int fdt_psci(void *fdt) +{ +#if defined(CONFIG_ARMV8_PSCI) || defined(CONFIG_ARMV7_PSCI) + int nodeoff; + unsigned int psci_ver = 0; + int tmp; + + nodeoff = fdt_path_offset(fdt, "/cpus"); + if (nodeoff < 0) { + printf("couldn't find /cpus\n"); + return nodeoff; + } + + /* add 'enable-method = "psci"' to each cpu node */ + for (tmp = fdt_first_subnode(fdt, nodeoff); + tmp >= 0; + tmp = fdt_next_subnode(fdt, tmp)) { + const struct fdt_property *prop; + int len; + + prop = fdt_get_property(fdt, tmp, "device_type", &len); + if (!prop) + continue; + if (len < 4) + continue; + if (strcmp(prop->data, "cpu")) + continue; + + /* + * Not checking rv here, our approach is to skip over errors in + * individual cpu nodes, hopefully some of the nodes are + * processed correctly and those will boot + */ + fdt_setprop_string(fdt, tmp, "enable-method", "psci"); + } + + nodeoff = fdt_path_offset(fdt, "/psci"); + if (nodeoff >= 0) + goto init_psci_node; + + nodeoff = fdt_path_offset(fdt, "/"); + if (nodeoff < 0) + return nodeoff; + + nodeoff = fdt_add_subnode(fdt, nodeoff, "psci"); + if (nodeoff < 0) + return nodeoff; + +init_psci_node: +#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT + psci_ver = sec_firmware_support_psci_version(); +#elif defined(CONFIG_ARMV7_PSCI_1_0) + psci_ver = ARM_PSCI_VER_1_0; +#endif + switch (psci_ver) { + case ARM_PSCI_VER_1_0: + tmp = fdt_setprop_string(fdt, nodeoff, + "compatible", "arm,psci-1.0"); + if (tmp) + return tmp; + case ARM_PSCI_VER_0_2: + tmp = fdt_appendprop_string(fdt, nodeoff, + "compatible", "arm,psci-0.2"); + if (tmp) + return tmp; + default: + /* + * The Secure firmware framework isn't able to support PSCI version 0.1. + */ +#ifndef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT + tmp = fdt_appendprop_string(fdt, nodeoff, + "compatible", "arm,psci"); + if (tmp) + return tmp; + tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_suspend", + ARM_PSCI_FN_CPU_SUSPEND); + if (tmp) + return tmp; + tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_off", + ARM_PSCI_FN_CPU_OFF); + if (tmp) + return tmp; + tmp = fdt_setprop_u32(fdt, nodeoff, "cpu_on", + ARM_PSCI_FN_CPU_ON); + if (tmp) + return tmp; + tmp = fdt_setprop_u32(fdt, nodeoff, "migrate", + ARM_PSCI_FN_MIGRATE); + if (tmp) + return tmp; +#endif + break; + } + + tmp = fdt_setprop_string(fdt, nodeoff, "method", "smc"); + if (tmp) + return tmp; + +#endif + return 0; +} diff --git a/arch/arm/lib/sections.c b/arch/arm/lib/sections.c index 6a945224183..952e8ae49bf 100644 --- a/arch/arm/lib/sections.c +++ b/arch/arm/lib/sections.c @@ -27,6 +27,8 @@ char __rel_dyn_start[0] __attribute__((section(".__rel_dyn_start"))); char __rel_dyn_end[0] __attribute__((section(".__rel_dyn_end"))); char __secure_start[0] __attribute__((section(".__secure_start"))); char __secure_end[0] __attribute__((section(".__secure_end"))); +char __secure_stack_start[0] __attribute__((section(".__secure_stack_start"))); +char __secure_stack_end[0] __attribute__((section(".__secure_stack_end"))); char __efi_runtime_start[0] __attribute__((section(".__efi_runtime_start"))); char __efi_runtime_stop[0] __attribute__((section(".__efi_runtime_stop"))); char __efi_runtime_rel_start[0] __attribute__((section(".__efi_runtime_rel_start"))); diff --git a/arch/arm/lib/spl.c b/arch/arm/lib/spl.c index e42886840ed..3587ad68129 100644 --- a/arch/arm/lib/spl.c +++ b/arch/arm/lib/spl.c @@ -25,22 +25,20 @@ gd_t gdata __attribute__ ((section(".data"))); #endif /* - * In the context of SPL, board_init_f must ensure that any clocks/etc for - * DDR are enabled, ensure that the stack pointer is valid, clear the BSS - * and call board_init_r. We provide this version by default but mark it - * as __weak to allow for platforms to do this in their own way if needed. + * In the context of SPL, board_init_f() prepares the hardware for execution + * from system RAM (DRAM, DDR...). As system RAM may not be available yet, + * board_init_f() must use the current GD to store any data which must be + * passed on to later stages. These data include the relocation destination, + * the future stack, and the future GD location. BSS is cleared after this + * function (and therefore must be accessible). + * + * We provide this version by default but mark it as __weak to allow for + * platforms to do this in their own way if needed. Please see the top + * level U-Boot README "Board Initialization Flow" section for info on what + * to put in this function. */ void __weak board_init_f(ulong dummy) { - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - -#ifndef CONFIG_SPL_DM - /* TODO: Remove settings of the global data pointer here */ - gd = &gdata; -#endif - - board_init_r(NULL, 0); } /* @@ -60,7 +58,7 @@ void __noreturn jump_to_image_linux(void *arg) typedef void (*image_entry_arg_t)(int, int, void *) __attribute__ ((noreturn)); image_entry_arg_t image_entry = - (image_entry_arg_t) spl_image.entry_point; + (image_entry_arg_t)(uintptr_t) spl_image.entry_point; cleanup_before_linux(); image_entry(0, machid, arg); } diff --git a/arch/arm/lib/zimage.c b/arch/arm/lib/zimage.c new file mode 100644 index 00000000000..1e811a87ddd --- /dev/null +++ b/arch/arm/lib/zimage.c @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2016 + * Ladislav Michl <ladis@linux-mips.org> + * + * bootz code: + * Copyright (C) 2012 Marek Vasut <marek.vasut@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> + +#define LINUX_ARM_ZIMAGE_MAGIC 0x016f2818 + +struct arm_z_header { + uint32_t code[9]; + uint32_t zi_magic; + uint32_t zi_start; + uint32_t zi_end; +} __attribute__ ((__packed__)); + +int bootz_setup(ulong image, ulong *start, ulong *end) +{ + struct arm_z_header *zi = (struct arm_z_header *)image; + + if (zi->zi_magic != LINUX_ARM_ZIMAGE_MAGIC) { +#ifndef CONFIG_SPL_FRAMEWORK + puts("Bad Linux ARM zImage magic!\n"); +#endif + return 1; + } + + *start = zi->zi_start; + *end = zi->zi_end; +#ifndef CONFIG_SPL_FRAMEWORK + printf("Kernel image @ %#08lx [ %#08lx - %#08lx ]\n", + image, *start, *end); +#endif + + return 0; +} diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h index 680ceb03145..2875ff20b19 100644 --- a/arch/arm/mach-at91/include/mach/at91_pmc.h +++ b/arch/arm/mach-at91/include/mach/at91_pmc.h @@ -149,6 +149,9 @@ typedef struct at91_pmc { #define AT91_PMC_PCR_PID_MASK (0x3f) #define AT91_PMC_PCR_GCKCSS (0x7 << 8) +#define AT91_PMC_PCR_GCKCSS_MASK 0x07 +#define AT91_PMC_PCR_GCKCSS_OFFSET 8 +#define AT91_PMC_PCR_GCKCSS_(x) ((x & 0x07) << 8) #define AT91_PMC_PCR_GCKCSS_SLOW_CLK (0x0 << 8) #define AT91_PMC_PCR_GCKCSS_MAIN_CLK (0x1 << 8) #define AT91_PMC_PCR_GCKCSS_PLLA_CLK (0x2 << 8) @@ -158,8 +161,9 @@ typedef struct at91_pmc { #define AT91_PMC_PCR_CMD_WRITE (0x1 << 12) #define AT91_PMC_PCR_DIV (0x3 << 16) #define AT91_PMC_PCR_GCKDIV (0xff << 20) -#define AT91_PMC_PCR_GCKDIV_(x) (((x) & 0xff) << 20) -#define AT91_PMC_PCR_GCKDIV_OFFSET 20 +#define AT91_PMC_PCR_GCKDIV_MASK 0xff +#define AT91_PMC_PCR_GCKDIV_OFFSET 20 +#define AT91_PMC_PCR_GCKDIV_(x) ((x & 0xff) << 20) #define AT91_PMC_PCR_EN (0x1 << 28) #define AT91_PMC_PCR_GCKEN (0x1 << 29) @@ -243,8 +247,9 @@ typedef struct at91_pmc { #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ #define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ #define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ +#define AT91_PMC_MOSCSELS BIT(16) /* Main Oscillator Selection Status */ +#define AT91_PMC_MOSCRCS BIT(17) /* 12 MHz RC Oscillator Status */ #define AT91_PMC_GCKRDY (1 << 24) - #define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */ /* PLL Charge Pump Current Register (PMC_PLLICPR) */ diff --git a/arch/arm/mach-at91/include/mach/atmel_pio4.h b/arch/arm/mach-at91/include/mach/atmel_pio4.h index 8bb4b12b269..6760bec4523 100644 --- a/arch/arm/mach-at91/include/mach/atmel_pio4.h +++ b/arch/arm/mach-at91/include/mach/atmel_pio4.h @@ -29,6 +29,41 @@ struct atmel_pio4_port { #endif +/* + * PIO Configuration Register Fields + */ +#define ATMEL_PIO_CFGR_FUNC_MASK GENMASK(2, 0) +#define ATMEL_PIO_CFGR_FUNC_GPIO (0x0 << 0) +#define ATMEL_PIO_CFGR_FUNC_PERIPH_A (0x1 << 0) +#define ATMEL_PIO_CFGR_FUNC_PERIPH_B (0x2 << 0) +#define ATMEL_PIO_CFGR_FUNC_PERIPH_C (0x3 << 0) +#define ATMEL_PIO_CFGR_FUNC_PERIPH_D (0x4 << 0) +#define ATMEL_PIO_CFGR_FUNC_PERIPH_E (0x5 << 0) +#define ATMEL_PIO_CFGR_FUNC_PERIPH_F (0x6 << 0) +#define ATMEL_PIO_CFGR_FUNC_PERIPH_G (0x7 << 0) +#define ATMEL_PIO_DIR_MASK BIT(8) +#define ATMEL_PIO_PUEN_MASK BIT(9) +#define ATMEL_PIO_PDEN_MASK BIT(10) +#define ATMEL_PIO_IFEN_MASK BIT(12) +#define ATMEL_PIO_IFSCEN_MASK BIT(13) +#define ATMEL_PIO_OPD_MASK BIT(14) +#define ATMEL_PIO_SCHMITT_MASK BIT(15) +#define ATMEL_PIO_CFGR_EVTSEL_MASK GENMASK(26, 24) +#define ATMEL_PIO_CFGR_EVTSEL_FALLING (0 << 24) +#define ATMEL_PIO_CFGR_EVTSEL_RISING (1 << 24) +#define ATMEL_PIO_CFGR_EVTSEL_BOTH (2 << 24) +#define ATMEL_PIO_CFGR_EVTSEL_LOW (3 << 24) +#define ATMEL_PIO_CFGR_EVTSEL_HIGH (4 << 24) + +#define ATMEL_PIO_NPINS_PER_BANK 32 +#define ATMEL_PIO_BANK(pin_id) (pin_id / ATMEL_PIO_NPINS_PER_BANK) +#define ATMEL_PIO_LINE(pin_id) (pin_id % ATMEL_PIO_NPINS_PER_BANK) +#define ATMEL_PIO_BANK_OFFSET 0x40 + +#define ATMEL_GET_PIN_NO(pinfunc) ((pinfunc) & 0xff) +#define ATMEL_GET_PIN_FUNC(pinfunc) ((pinfunc >> 16) & 0xf) +#define ATMEL_GET_PIN_IOSET(pinfunc) ((pinfunc >> 20) & 0xf) + #define AT91_PIO_PORTA 0x0 #define AT91_PIO_PORTB 0x1 #define AT91_PIO_PORTC 0x2 diff --git a/arch/arm/mach-exynos/include/mach/dwmmc.h b/arch/arm/mach-exynos/include/mach/dwmmc.h index bd997ad47e3..ab8361f4a8b 100644 --- a/arch/arm/mach-exynos/include/mach/dwmmc.h +++ b/arch/arm/mach-exynos/include/mach/dwmmc.h @@ -28,4 +28,3 @@ #define DWMCI_DIVRATIO_MASK 0x7 int exynos_dwmmc_init(const void *blob); -int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel); diff --git a/arch/arm/mach-exynos/include/mach/system.h b/arch/arm/mach-exynos/include/mach/system.h index 3ffb296a57f..2c94a6bea0b 100644 --- a/arch/arm/mach-exynos/include/mach/system.h +++ b/arch/arm/mach-exynos/include/mach/system.h @@ -38,16 +38,6 @@ struct exynos5_sysreg { #define USB20_PHY_CFG_HOST_LINK_EN (1 << 0) /* - * Data Synchronization Barrier acts as a special kind of memory barrier. - * No instruction in program order after this instruction executes until - * this instruction completes. This instruction completes when: - * - All explicit memory accesses before this instruction complete. - * - All Cache, Branch predictor and TLB maintenance operations before - * this instruction complete. - */ -#define dsb() __asm__ __volatile__ ("dsb\n\t" : : ); - -/* * This instruction causes an event to be signaled to all cores * within a multiprocessor system. If SEV is implemented, * WFE must also be implemented. diff --git a/arch/arm/mach-exynos/mmu-arm64.c b/arch/arm/mach-exynos/mmu-arm64.c index ba6d99d329d..23814222d82 100644 --- a/arch/arm/mach-exynos/mmu-arm64.c +++ b/arch/arm/mach-exynos/mmu-arm64.c @@ -13,21 +13,20 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_EXYNOS7420 static struct mm_region exynos7420_mem_map[] = { { - .base = 0x10000000UL, + .virt = 0x10000000UL, + .phys = 0x10000000UL, .size = 0x10000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN, }, { - .base = 0x40000000UL, + .virt = 0x40000000UL, + .phys = 0x40000000UL, .size = 0x80000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE, }, { /* List terminator */ - .base = 0, - .size = 0, - .attrs = 0, }, }; diff --git a/arch/arm/mach-keystone/init.c b/arch/arm/mach-keystone/init.c index 3b6d5efce1a..6e5a1e1af17 100644 --- a/arch/arm/mach-keystone/init.c +++ b/arch/arm/mach-keystone/init.c @@ -101,9 +101,7 @@ static void msmc_k2hkle_common_setup(void) msmc_share_all_segments(KS2_MSMC_SEGMENT_C6X_0); msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_ARM); msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_NETCP); -#ifdef KS2_MSMC_SEGMENT_QM_PDSP msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_QM_PDSP); -#endif msmc_share_all_segments(K2HKLE_MSMC_SEGMENT_PCIE0); msmc_share_all_segments(KS2_MSMC_SEGMENT_DEBUG); } diff --git a/arch/arm/mach-meson/board.c b/arch/arm/mach-meson/board.c index 64fa3c191ee..1dd53e2313f 100644 --- a/arch/arm/mach-meson/board.c +++ b/arch/arm/mach-meson/board.c @@ -48,12 +48,14 @@ void reset_cpu(ulong addr) static struct mm_region gxbb_mem_map[] = { { - .base = 0x0UL, + .virt = 0x0UL, + .phys = 0x0UL, .size = 0x80000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { - .base = 0x80000000UL, + .virt = 0x80000000UL, + .phys = 0x80000000UL, .size = 0x80000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 2a8afac5e12..1aac3c85ba5 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -1,7 +1,21 @@ if ARCH_ROCKCHIP +config ROCKCHIP_RK3036 + bool "Support Rockchip RK3036" + select CPU_V7 + select SUPPORT_SPL + select SPL + help + The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7 + including NEON and GPU, Mali-400 graphics, several DDR3 options + and video codec support. Peripherals include Gigabit Ethernet, + USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. + config ROCKCHIP_RK3288 bool "Support Rockchip RK3288" + select CPU_V7 + select SUPPORT_SPL + select SPL help The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two @@ -9,41 +23,26 @@ config ROCKCHIP_RK3288 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UART,s, SPI, I2C and PWMs. -config ROCKCHIP_RK3036 - bool "Support Rockchip RK3036" +config ROCKCHIP_RK3399 + bool "Support Rockchip RK3399" + select ARM64 help - The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7 - including NEON and GPU, Mali-400 graphics, several DDR3 options + The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72 + and quad-core Cortex-A53. + including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two + video interfaces supporting HDMI and eDP, several DDR3 options and video codec support. Peripherals include Gigabit Ethernet, - USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. - -config SYS_MALLOC_F - default y - -config SPL_SYS_MALLOC_SIMPLE - default y - -config SPL_DM - default y - -config DM_SERIAL - default y - -config DM_SPI - default y + USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. -config DM_SPI_FLASH - default y - -config DM_I2C - default y - -config DM_GPIO - default y - -config BLK - default y +config ROCKCHIP_SPL_BACK_TO_BROM + bool "SPL returns to bootrom" + default y if ROCKCHIP_RK3036 + help + Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled, + SPL will return to the boot rom, which will then load the U-Boot + binary to keep going on. -source "arch/arm/mach-rockchip/rk3288/Kconfig" source "arch/arm/mach-rockchip/rk3036/Kconfig" +source "arch/arm/mach-rockchip/rk3288/Kconfig" +source "arch/arm/mach-rockchip/rk3399/Kconfig" endif diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 55567cb131b..157d42fe960 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -5,11 +5,15 @@ # ifdef CONFIG_SPL_BUILD -obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o +obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o +obj-$(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) += save_boot_param.o else obj-$(CONFIG_ROCKCHIP_RK3288) += board.o endif +ifndef CONFIG_ARM64 obj-y += rk_timer.o -obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/ +endif obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/ +obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/ +obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/ diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c index 816540e5821..bec756d7ac0 100644 --- a/arch/arm/mach-rockchip/board.c +++ b/arch/arm/mach-rockchip/board.c @@ -10,12 +10,45 @@ #include <ram.h> #include <asm/io.h> #include <asm/arch/clock.h> +#include <asm/arch/periph.h> +#include <asm/gpio.h> +#include <dm/pinctrl.h> DECLARE_GLOBAL_DATA_PTR; int board_init(void) { +#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM + struct udevice *pinctrl; + int ret; + + /* + * We need to implement sdcard iomux here for the further + * initlization, otherwise, it'll hit sdcard command sending + * timeout exception. + */ + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); + if (ret) { + debug("%s: Cannot find pinctrl device\n", __func__); + goto err; + } + ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD); + if (ret) { + debug("%s: Failed to set up SD card\n", __func__); + goto err; + } + + return 0; +err: + printf("board_init: Error %d\n", ret); + + /* No way to report error here */ + hang(); + + return -1; +#else return 0; +#endif } int dram_init(void) @@ -52,6 +85,78 @@ void lowlevel_init(void) { } +#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) +#include <usb.h> +#include <usb/dwc2_udc.h> + +static struct dwc2_plat_otg_data rk3288_otg_data = { + .rx_fifo_sz = 512, + .np_tx_fifo_sz = 16, + .tx_fifo_sz = 128, +}; + +int board_usb_init(int index, enum usb_init_type init) +{ + int node, phy_node; + const char *mode; + bool matched = false; + const void *blob = gd->fdt_blob; + u32 grf_phy_offset; + + /* find the usb_otg node */ + node = fdt_node_offset_by_compatible(blob, -1, + "rockchip,rk3288-usb"); + + while (node > 0) { + mode = fdt_getprop(blob, node, "dr_mode", NULL); + if (mode && strcmp(mode, "otg") == 0) { + matched = true; + break; + } + + node = fdt_node_offset_by_compatible(blob, node, + "rockchip,rk3288-usb"); + } + if (!matched) { + debug("Not found usb_otg device\n"); + return -ENODEV; + } + rk3288_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg"); + + node = fdtdec_lookup_phandle(blob, node, "phys"); + if (node <= 0) { + debug("Not found usb phy device\n"); + return -ENODEV; + } + + phy_node = fdt_parent_offset(blob, node); + if (phy_node <= 0) { + debug("Not found usb phy device\n"); + return -ENODEV; + } + + rk3288_otg_data.phy_of_node = phy_node; + grf_phy_offset = fdtdec_get_addr(blob, node, "reg"); + + /* find the grf node */ + node = fdt_node_offset_by_compatible(blob, -1, + "rockchip,rk3288-grf"); + if (node <= 0) { + debug("Not found grf device\n"); + return -ENODEV; + } + rk3288_otg_data.regs_phy = grf_phy_offset + + fdtdec_get_addr(blob, node, "reg"); + + return dwc2_udc_probe(&rk3288_otg_data); +} + +int board_usb_cleanup(int index, enum usb_init_type init) +{ + return 0; +} +#endif + static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { @@ -73,7 +178,7 @@ static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc, int ret, i; struct udevice *dev; - ret = uclass_get_device(UCLASS_CLK, 0, &dev); + ret = rockchip_get_clk(&dev); if (ret) { printf("clk-uclass not found\n"); return 0; diff --git a/arch/arm/mach-rockchip/rk3036/Kconfig b/arch/arm/mach-rockchip/rk3036/Kconfig index cc038088472..08047144f6e 100644 --- a/arch/arm/mach-rockchip/rk3036/Kconfig +++ b/arch/arm/mach-rockchip/rk3036/Kconfig @@ -12,10 +12,7 @@ config SYS_SOC config SYS_MALLOC_F_LEN default 0x400 -config ROCKCHIP_COMMON - bool "Support rk common fuction" - -source "board/evb_rk3036/evb_rk3036/Kconfig" -source "board/kylin/kylin_rk3036/Kconfig" +source "board/rockchip/evb_rk3036/Kconfig" +source "board/rockchip/kylin_rk3036/Kconfig" endif diff --git a/arch/arm/mach-rockchip/rk3036/Makefile b/arch/arm/mach-rockchip/rk3036/Makefile index 97d299d6cc6..916a7a43784 100644 --- a/arch/arm/mach-rockchip/rk3036/Makefile +++ b/arch/arm/mach-rockchip/rk3036/Makefile @@ -5,9 +5,7 @@ # ifndef CONFIG_SPL_BUILD -obj-y += reset_rk3036.o obj-y += syscon_rk3036.o endif obj-y += sdram_rk3036.o -obj-y += save_boot_param.o diff --git a/arch/arm/mach-rockchip/rk3036/reset_rk3036.c b/arch/arm/mach-rockchip/rk3036/reset_rk3036.c deleted file mode 100644 index b3d21132399..00000000000 --- a/arch/arm/mach-rockchip/rk3036/reset_rk3036.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * (C) Copyright 2015 Rockchip Electronics Co., Ltd - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <dm.h> -#include <errno.h> -#include <sysreset.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3036.h> -#include <asm/arch/hardware.h> -#include <linux/err.h> - -int rk3036_sysreset_request(struct udevice *dev, enum sysreset_t type) -{ - struct rk3036_cru *cru = rockchip_get_cru(); - - if (IS_ERR(cru)) - return PTR_ERR(cru); - switch (type) { - case SYSRESET_WARM: - writel(0xeca8, &cru->cru_glb_srst_snd_value); - break; - case SYSRESET_COLD: - writel(0xfdb9, &cru->cru_glb_srst_fst_value); - break; - default: - return -EPROTONOSUPPORT; - } - - return -EINPROGRESS; -} - -static struct sysreset_ops rk3036_sysreset = { - .request = rk3036_sysreset_request, -}; - -U_BOOT_DRIVER(sysreset_rk3036) = { - .name = "rk3036_sysreset", - .id = UCLASS_SYSRESET, - .ops = &rk3036_sysreset, -}; diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c index 15f1266a7bf..e0d92a66b39 100644 --- a/arch/arm/mach-rockchip/rk3288-board-spl.c +++ b/arch/arm/mach-rockchip/rk3288-board-spl.c @@ -29,6 +29,7 @@ DECLARE_GLOBAL_DATA_PTR; u32 spl_boot_device(void) { +#if !CONFIG_IS_ENABLED(OF_PLATDATA) const void *blob = gd->fdt_blob; struct udevice *dev; const char *bootdev; @@ -63,6 +64,7 @@ u32 spl_boot_device(void) } fallback: +#endif return BOOT_DEVICE_MMC1; } @@ -114,7 +116,8 @@ static void configure_l2ctlr(void) #ifdef CONFIG_SPL_MMC_SUPPORT static int configure_emmc(struct udevice *pinctrl) { -#if !defined(CONFIG_TARGET_ROCK2) && !defined(CONFIG_TARGET_FIREFLY_RK3288) +#if defined(CONFIG_TARGET_CHROMEBOOK_JERRY) + struct gpio_desc desc; int ret; @@ -145,11 +148,10 @@ static int configure_emmc(struct udevice *pinctrl) return ret; } #endif - return 0; } #endif - +extern void back_to_bootrom(void); void board_init_f(ulong dummy) { struct udevice *pinctrl; @@ -187,7 +189,7 @@ void board_init_f(ulong dummy) rockchip_timer_init(); configure_l2ctlr(); - ret = uclass_get_device(UCLASS_CLK, 0, &dev); + ret = rockchip_get_clk(&dev); if (ret) { debug("CLK init failed: %d\n", ret); return; @@ -204,6 +206,9 @@ void board_init_f(ulong dummy) debug("DRAM init failed: %d\n", ret); return; } +#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM + back_to_bootrom(); +#endif } static int setup_led(void) @@ -246,6 +251,7 @@ void spl_board_init(void) debug("%s: Cannot find pinctrl device\n", __func__); goto err; } + #ifdef CONFIG_SPL_MMC_SUPPORT ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD); if (ret) { diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index 72156245bd3..b4113e085b0 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -8,6 +8,39 @@ config TARGET_FIREFLY_RK3288 also includes on-board eMMC and 1GB of SDRAM. Expansion connectors provide access to display pins, I2C, SPI, UART and GPIOs. +config TARGET_EVB_RK3288 + bool "Evb-RK3288" + help + EVB-RK3288 is a RK3288-based development board with 2 USB ports, + HDMI, VGA, micro-SD card, audio, WiFi and Gigabit Ethernet, It + also includes on-board eMMC and 2GB of SDRAM. Expansion connectors + provide access to display pins, I2C, SPI, UART and GPIOs. + +config TARGET_FENNEC_RK3288 + bool "Fennec-RK3288" + help + Fennec is a RK3288-based development board with 2 USB ports, + HDMI, micro-SD card, audio, WiFi and Gigabit Ethernet. It also + includes on-board eMMC and 2GB of SDRAM. Expansion connectors + provide access to display pins, I2C, SPI, UART and GPIOs. + +config TARGET_POPMETAL_RK3288 + bool "PopMetal-RK3288" + help + PopMetal is a RK3288-based development board with 3 USB host ports, + 1 micro USB OTG port, HDMI, VGA, micro-SD card, audio, WiFi, Gigabit + Ethernet and lots of sensors. It also includes on-board 8 GeMMC and + 2GB DDR3. Expansion connectors provide access to I2C, SPI, UART, + GPIOs and display interface. + +config TARGET_MINIARM_RK3288 + bool "miniarm-RK3288" + help + Miniarm is a RK3288-based development board with 2 USB ports, HDMI, + micro-SD card, audio, Gigabit Ethernet. It also includes on-board + 8GB eMMC and 2GB of SDRAM. Expansion connectors provide access to + I2C, SPI, UART, GPIOs. + config TARGET_CHROMEBOOK_JERRY bool "Google/Rockchip Veyron-Jerry Chromebook" help @@ -39,10 +72,18 @@ config SYS_SOC config SYS_MALLOC_F_LEN default 0x0800 -source "board/google/chromebook_jerry/Kconfig" +source "board/chipspark/popmetal_rk3288/Kconfig" source "board/firefly/firefly-rk3288/Kconfig" +source "board/google/chromebook_jerry/Kconfig" + source "board/radxa/rock2/Kconfig" +source "board/rockchip/evb_rk3288/Kconfig" + +source "board/rockchip/fennec_rk3288/Kconfig" + +source "board/rockchip/miniarm_rk3288/Kconfig" + endif diff --git a/arch/arm/mach-rockchip/rk3288/Makefile b/arch/arm/mach-rockchip/rk3288/Makefile index 6f62375f464..5ec3f0d7e2b 100644 --- a/arch/arm/mach-rockchip/rk3288/Makefile +++ b/arch/arm/mach-rockchip/rk3288/Makefile @@ -4,6 +4,6 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += reset_rk3288.o +obj-y += clk_rk3288.o obj-y += sdram_rk3288.o obj-y += syscon_rk3288.o diff --git a/arch/arm/mach-rockchip/rk3288/clk_rk3288.c b/arch/arm/mach-rockchip/rk3288/clk_rk3288.c new file mode 100644 index 00000000000..2099e349c16 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3288/clk_rk3288.c @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2015 Google, Inc + * Written by Simon Glass <sjg@chromium.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <syscon.h> +#include <asm/arch/clock.h> + +int rockchip_get_clk(struct udevice **devp) +{ + return uclass_get_device_by_driver(UCLASS_CLK, + DM_GET_DRIVER(rockchip_rk3288_cru), devp); +} diff --git a/arch/arm/mach-rockchip/rk3288/reset_rk3288.c b/arch/arm/mach-rockchip/rk3288/reset_rk3288.c deleted file mode 100644 index 0aad1c21601..00000000000 --- a/arch/arm/mach-rockchip/rk3288/reset_rk3288.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * (C) Copyright 2015 Google, Inc - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#include <common.h> -#include <dm.h> -#include <errno.h> -#include <sysreset.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/cru_rk3288.h> -#include <asm/arch/hardware.h> -#include <linux/err.h> - -int rk3288_sysreset_request(struct udevice *dev, enum sysreset_t type) -{ - struct rk3288_cru *cru = rockchip_get_cru(); - - if (IS_ERR(cru)) - return PTR_ERR(cru); - switch (type) { - case SYSRESET_WARM: - rk_clrreg(&cru->cru_mode_con, 0xffff); - writel(0xeca8, &cru->cru_glb_srst_snd_value); - break; - case SYSRESET_COLD: - rk_clrreg(&cru->cru_mode_con, 0xffff); - writel(0xfdb9, &cru->cru_glb_srst_fst_value); - break; - default: - return -EPROTONOSUPPORT; - } - - return -EINPROGRESS; -} - -static struct sysreset_ops rk3288_sysreset = { - .request = rk3288_sysreset_request, -}; - -U_BOOT_DRIVER(sysreset_rk3288) = { - .name = "rk3288_sysreset", - .id = UCLASS_SYSRESET, - .ops = &rk3288_sysreset, -}; diff --git a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c index 55ac73e9d25..cf9ef2e8451 100644 --- a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c @@ -10,6 +10,7 @@ #include <common.h> #include <clk.h> #include <dm.h> +#include <dt-structs.h> #include <errno.h> #include <ram.h> #include <regmap.h> @@ -41,6 +42,19 @@ struct dram_info { struct rk3288_grf *grf; struct rk3288_sgrf *sgrf; struct rk3288_pmu *pmu; + bool is_veyron; +}; + +struct rk3288_sdram_params { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_rockchip_rk3288_dmc of_plat; +#endif + struct rk3288_sdram_channel ch[2]; + struct rk3288_sdram_pctl_timing pctl_timing; + struct rk3288_sdram_phy_timing phy_timing; + struct rk3288_base_params base; + int num_channels; + struct regmap *map; }; #ifdef CONFIG_SPL_BUILD @@ -561,14 +575,14 @@ static void dram_all_config(const struct dram_info *dram, &sdram_params->ch[chan]; sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan); - sys_reg |= chan << SYS_REG_CHINFO_SHIFT(chan); + sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan); sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan); sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan); - sys_reg |= info->bk == 3 ? 1 << SYS_REG_BK_SHIFT(chan) : 0; + sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan); sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan); sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan); - sys_reg |= info->bw << SYS_REG_BW_SHIFT(chan); - sys_reg |= info->dbw << SYS_REG_DBW_SHIFT(chan); + sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan); + sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan); dram_cfg_rbc(&dram->chan[chan], chan, sdram_params); } @@ -703,7 +717,7 @@ static int sdram_init(struct dram_info *dram, return 0; } -#endif +#endif /* CONFIG_SPL_BUILD */ size_t sdram_size_mb(struct rk3288_pmu *pmu) { @@ -720,13 +734,13 @@ size_t sdram_size_mb(struct rk3288_pmu *pmu) rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) & SYS_REG_RANK_MASK); col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK); - bk = sys_reg & (1 << SYS_REG_BK_SHIFT(ch)) ? 3 : 0; + bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK); cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) & SYS_REG_CS0_ROW_MASK); cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) & SYS_REG_CS1_ROW_MASK); - bw = (sys_reg >> SYS_REG_BW_SHIFT(ch)) & - SYS_REG_BW_MASK; + bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) & + SYS_REG_BW_MASK)); row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) & SYS_REG_ROW_3_4_MASK; @@ -770,7 +784,7 @@ static int veyron_init(struct dram_info *priv) return ret; udelay(100);/* Must wait for voltage to stabilize, 2mV/us */ - rkclk_configure_cpu(priv->cru, priv->grf); + rk3288_clk_configure_cpu(priv->cru, priv->grf); return 0; } @@ -779,18 +793,36 @@ static int veyron_init(struct dram_info *priv) static int setup_sdram(struct udevice *dev) { struct dram_info *priv = dev_get_priv(dev); - struct rk3288_sdram_params params; + struct rk3288_sdram_params *params = dev_get_platdata(dev); + +# ifdef CONFIG_ROCKCHIP_FAST_SPL + if (priv->is_veyron) { + int ret; + + ret = veyron_init(priv); + if (ret) + return ret; + } +# endif + + return sdram_init(priv, params); +} + +static int rk3288_dmc_ofdata_to_platdata(struct udevice *dev) +{ +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct rk3288_sdram_params *params = dev_get_platdata(dev); const void *blob = gd->fdt_blob; int node = dev->of_offset; int i, ret; - params.num_channels = fdtdec_get_int(blob, node, - "rockchip,num-channels", 1); - for (i = 0; i < params.num_channels; i++) { + params->num_channels = fdtdec_get_int(blob, node, + "rockchip,num-channels", 1); + for (i = 0; i < params->num_channels; i++) { ret = fdtdec_get_byte_array(blob, node, "rockchip,sdram-channel", - (u8 *)¶ms.ch[i], - sizeof(params.ch[i])); + (u8 *)¶ms->ch[i], + sizeof(params->ch[i])); if (ret) { debug("%s: Cannot read rockchip,sdram-channel\n", __func__); @@ -798,46 +830,82 @@ static int setup_sdram(struct udevice *dev) } } ret = fdtdec_get_int_array(blob, node, "rockchip,pctl-timing", - (u32 *)¶ms.pctl_timing, - sizeof(params.pctl_timing) / sizeof(u32)); + (u32 *)¶ms->pctl_timing, + sizeof(params->pctl_timing) / sizeof(u32)); if (ret) { debug("%s: Cannot read rockchip,pctl-timing\n", __func__); return -EINVAL; } ret = fdtdec_get_int_array(blob, node, "rockchip,phy-timing", - (u32 *)¶ms.phy_timing, - sizeof(params.phy_timing) / sizeof(u32)); + (u32 *)¶ms->phy_timing, + sizeof(params->phy_timing) / sizeof(u32)); if (ret) { debug("%s: Cannot read rockchip,phy-timing\n", __func__); return -EINVAL; } ret = fdtdec_get_int_array(blob, node, "rockchip,sdram-params", - (u32 *)¶ms.base, - sizeof(params.base) / sizeof(u32)); + (u32 *)¶ms->base, + sizeof(params->base) / sizeof(u32)); if (ret) { debug("%s: Cannot read rockchip,sdram-params\n", __func__); return -EINVAL; } +#ifdef CONFIG_ROCKCHIP_FAST_SPL + struct dram_info *priv = dev_get_priv(dev); -# ifdef CONFIG_ROCKCHIP_FAST_SPL - if (!fdt_node_check_compatible(blob, 0, "google,veyron")) { - ret = veyron_init(priv); - if (ret) - return ret; + priv->is_veyron = !fdt_node_check_compatible(blob, 0, "google,veyron"); +#endif + ret = regmap_init_mem(dev, ¶ms->map); + if (ret) + return ret; +#endif + + return 0; +} +#endif /* CONFIG_SPL_BUILD */ + +#if CONFIG_IS_ENABLED(OF_PLATDATA) +static int conv_of_platdata(struct udevice *dev) +{ + struct rk3288_sdram_params *plat = dev_get_platdata(dev); + struct dtd_rockchip_rk3288_dmc *of_plat = &plat->of_plat; + int i, ret; + + for (i = 0; i < 2; i++) { + memcpy(&plat->ch[i], of_plat->rockchip_sdram_channel, + sizeof(plat->ch[i])); } -# endif + memcpy(&plat->pctl_timing, of_plat->rockchip_pctl_timing, + sizeof(plat->pctl_timing)); + memcpy(&plat->phy_timing, of_plat->rockchip_phy_timing, + sizeof(plat->phy_timing)); + memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base)); + plat->num_channels = of_plat->rockchip_num_channels; + ret = regmap_init_mem_platdata(dev, of_plat->reg, + ARRAY_SIZE(of_plat->reg) / 2, + &plat->map); + if (ret) + return ret; - return sdram_init(priv, ¶ms); + return 0; } #endif static int rk3288_dmc_probe(struct udevice *dev) { +#ifdef CONFIG_SPL_BUILD + struct rk3288_sdram_params *plat = dev_get_platdata(dev); +#endif struct dram_info *priv = dev_get_priv(dev); struct regmap *map; int ret; struct udevice *dev_clk; +#if CONFIG_IS_ENABLED(OF_PLATDATA) + ret = conv_of_platdata(dev); + if (ret) + return ret; +#endif map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_NOC); if (IS_ERR(map)) return PTR_ERR(map); @@ -849,15 +917,13 @@ static int rk3288_dmc_probe(struct udevice *dev) priv->sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_SGRF); priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); - ret = regmap_init_mem(dev, &map); - if (ret) - return ret; - priv->chan[0].pctl = regmap_get_range(map, 0); - priv->chan[0].publ = regmap_get_range(map, 1); - priv->chan[1].pctl = regmap_get_range(map, 2); - priv->chan[1].publ = regmap_get_range(map, 3); - - ret = uclass_get_device(UCLASS_CLK, 0, &dev_clk); +#ifdef CONFIG_SPL_BUILD + priv->chan[0].pctl = regmap_get_range(plat->map, 0); + priv->chan[0].publ = regmap_get_range(plat->map, 1); + priv->chan[1].pctl = regmap_get_range(plat->map, 2); + priv->chan[1].publ = regmap_get_range(plat->map, 3); +#endif + ret = rockchip_get_clk(&dev_clk); if (ret) return ret; priv->ddr_clk.id = CLK_DDR; @@ -898,10 +964,16 @@ static const struct udevice_id rk3288_dmc_ids[] = { }; U_BOOT_DRIVER(dmc_rk3288) = { - .name = "rk3288_dmc", + .name = "rockchip_rk3288_dmc", .id = UCLASS_RAM, .of_match = rk3288_dmc_ids, .ops = &rk3288_dmc_ops, +#ifdef CONFIG_SPL_BUILD + .ofdata_to_platdata = rk3288_dmc_ofdata_to_platdata, +#endif .probe = rk3288_dmc_probe, .priv_auto_alloc_size = sizeof(struct dram_info), +#ifdef CONFIG_SPL_BUILD + .platdata_auto_alloc_size = sizeof(struct rk3288_sdram_params), +#endif }; diff --git a/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c b/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c index c9f7c4e32f4..be4b2b00c30 100644 --- a/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c @@ -23,3 +23,41 @@ U_BOOT_DRIVER(syscon_rk3288) = { .id = UCLASS_SYSCON, .of_match = rk3288_syscon_ids, }; + +#if CONFIG_IS_ENABLED(OF_PLATDATA) +static int rk3288_syscon_bind_of_platdata(struct udevice *dev) +{ + dev->driver_data = dev->driver->of_match->data; + debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data); + + return 0; +} + +U_BOOT_DRIVER(rockchip_rk3288_noc) = { + .name = "rockchip_rk3288_noc", + .id = UCLASS_SYSCON, + .of_match = rk3288_syscon_ids, + .bind = rk3288_syscon_bind_of_platdata, +}; + +U_BOOT_DRIVER(rockchip_rk3288_grf) = { + .name = "rockchip_rk3288_grf", + .id = UCLASS_SYSCON, + .of_match = rk3288_syscon_ids + 1, + .bind = rk3288_syscon_bind_of_platdata, +}; + +U_BOOT_DRIVER(rockchip_rk3288_sgrf) = { + .name = "rockchip_rk3288_sgrf", + .id = UCLASS_SYSCON, + .of_match = rk3288_syscon_ids + 2, + .bind = rk3288_syscon_bind_of_platdata, +}; + +U_BOOT_DRIVER(rockchip_rk3288_pmu) = { + .name = "rockchip_rk3288_pmu", + .id = UCLASS_SYSCON, + .of_match = rk3288_syscon_ids + 3, + .bind = rk3288_syscon_bind_of_platdata, +}; +#endif diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig new file mode 100644 index 00000000000..83bd04add24 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -0,0 +1,23 @@ +if ROCKCHIP_RK3399 + +choice + prompt "RK3399 board select" + +config TARGET_EVB_RK3399 + bool "RK3399 evaluation board" + help + RK3399evb is a evaluation board for Rockchp rk3399, + with full function and phisical connectors support like type-C ports, + usb2.0 host ports, LVDS, JTAG, MAC, SDcard, HDMI, USB-2-serial... + +endchoice + +config SYS_SOC + default "rockchip" + +config SYS_MALLOC_F_LEN + default 0x0800 + +source "board/rockchip/evb_rk3399/Kconfig" + +endif diff --git a/arch/arm/mach-rockchip/rk3399/Makefile b/arch/arm/mach-rockchip/rk3399/Makefile new file mode 100644 index 00000000000..607f9c96129 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3399/Makefile @@ -0,0 +1,8 @@ +# +# (C) Copyright 2016 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += rk3399.o +obj-y += syscon_rk3399.o diff --git a/arch/arm/mach-rockchip/rk3399/rk3399.c b/arch/arm/mach-rockchip/rk3399/rk3399.c new file mode 100644 index 00000000000..b9d76294078 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3399/rk3399.c @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/armv8/mmu.h> + +static struct mm_region rk3399_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xf0000000UL, + .phys = 0xf0000000UL, + .size = 0x10000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = rk3399_mem_map; diff --git a/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c new file mode 100644 index 00000000000..2d81c55cd23 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3399/syscon_rk3399.c @@ -0,0 +1,20 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <syscon.h> +#include <asm/arch/clock.h> + +static const struct udevice_id rk3399_syscon_ids[] = { + { .compatible = "rockchip,rk3399-grf", .data = ROCKCHIP_SYSCON_GRF }, +}; + +U_BOOT_DRIVER(syscon_rk3399) = { + .name = "rk3399_syscon", + .id = UCLASS_SYSCON, + .of_match = rk3399_syscon_ids, +}; diff --git a/arch/arm/mach-rockchip/rk3036/save_boot_param.S b/arch/arm/mach-rockchip/save_boot_param.S index 778ec83c2c8..85b407b4d3b 100644 --- a/arch/arm/mach-rockchip/rk3036/save_boot_param.S +++ b/arch/arm/mach-rockchip/save_boot_param.S @@ -1,5 +1,5 @@ /* - * (C) Copyright 2015 Google, Inc + * (C) Copyright 2016 Rockchip Electronics Co., Ltd * * SPDX-License-Identifier: GPL-2.0+ */ diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile index 4735844b752..d82a04dda60 100644 --- a/arch/arm/mach-snapdragon/Makefile +++ b/arch/arm/mach-snapdragon/Makefile @@ -6,4 +6,3 @@ obj-y += clock-apq8016.o obj-y += sysmap-apq8016.o -obj-y += reset.o diff --git a/arch/arm/mach-snapdragon/reset.c b/arch/arm/mach-snapdragon/reset.c deleted file mode 100644 index a6cabfb8b01..00000000000 --- a/arch/arm/mach-snapdragon/reset.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Qualcomm APQ8016 reset controller driver - * - * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <dm.h> -#include <errno.h> -#include <sysreset.h> -#include <asm/io.h> - -DECLARE_GLOBAL_DATA_PTR; - -static int msm_sysreset_request(struct udevice *dev, enum sysreset_t type) -{ - phys_addr_t addr = dev_get_addr(dev); - if (!addr) - return -EINVAL; - writel(0, addr); - return -EINPROGRESS; -} - -static struct sysreset_ops msm_sysreset_ops = { - .request = msm_sysreset_request, -}; - -static const struct udevice_id msm_sysreset_ids[] = { - { .compatible = "qcom,pshold" }, - { } -}; - -U_BOOT_DRIVER(msm_reset) = { - .name = "msm_sysreset", - .id = UCLASS_SYSRESET, - .of_match = msm_sysreset_ids, - .ops = &msm_sysreset_ops, -}; diff --git a/arch/arm/mach-snapdragon/sysmap-apq8016.c b/arch/arm/mach-snapdragon/sysmap-apq8016.c index ef0db2ab5f4..580b9c7e615 100644 --- a/arch/arm/mach-snapdragon/sysmap-apq8016.c +++ b/arch/arm/mach-snapdragon/sysmap-apq8016.c @@ -11,13 +11,15 @@ static struct mm_region apq8016_mem_map[] = { { - .base = 0x0UL, /* Peripheral block */ + .virt = 0x0UL, /* Peripheral block */ + .phys = 0x0UL, /* Peripheral block */ .size = 0x8000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { - .base = 0x80000000UL, /* DDR */ + .virt = 0x80000000UL, /* DDR */ + .phys = 0x80000000UL, /* DDR */ .size = 0x80000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE diff --git a/arch/arm/mach-stm32/stm32f7/Makefile b/arch/arm/mach-stm32/stm32f7/Makefile index 40f1ad35b7e..643d4d919c2 100644 --- a/arch/arm/mach-stm32/stm32f7/Makefile +++ b/arch/arm/mach-stm32/stm32f7/Makefile @@ -5,4 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += timer.o clock.o +obj-y += timer.o clock.o soc.o diff --git a/arch/arm/mach-stm32/stm32f7/clock.c b/arch/arm/mach-stm32/stm32f7/clock.c index 17a715bac92..78d22d40fd8 100644 --- a/arch/arm/mach-stm32/stm32f7/clock.c +++ b/arch/arm/mach-stm32/stm32f7/clock.c @@ -11,6 +11,234 @@ #include <asm/arch/stm32.h> #include <asm/arch/stm32_periph.h> +#define RCC_CR_HSION (1 << 0) +#define RCC_CR_HSEON (1 << 16) +#define RCC_CR_HSERDY (1 << 17) +#define RCC_CR_HSEBYP (1 << 18) +#define RCC_CR_CSSON (1 << 19) +#define RCC_CR_PLLON (1 << 24) +#define RCC_CR_PLLRDY (1 << 25) + +#define RCC_PLLCFGR_PLLM_MASK 0x3F +#define RCC_PLLCFGR_PLLN_MASK 0x7FC0 +#define RCC_PLLCFGR_PLLP_MASK 0x30000 +#define RCC_PLLCFGR_PLLQ_MASK 0xF000000 +#define RCC_PLLCFGR_PLLSRC (1 << 22) +#define RCC_PLLCFGR_PLLM_SHIFT 0 +#define RCC_PLLCFGR_PLLN_SHIFT 6 +#define RCC_PLLCFGR_PLLP_SHIFT 16 +#define RCC_PLLCFGR_PLLQ_SHIFT 24 + +#define RCC_CFGR_AHB_PSC_MASK 0xF0 +#define RCC_CFGR_APB1_PSC_MASK 0x1C00 +#define RCC_CFGR_APB2_PSC_MASK 0xE000 +#define RCC_CFGR_SW0 (1 << 0) +#define RCC_CFGR_SW1 (1 << 1) +#define RCC_CFGR_SW_MASK 0x3 +#define RCC_CFGR_SW_HSI 0 +#define RCC_CFGR_SW_HSE RCC_CFGR_SW0 +#define RCC_CFGR_SW_PLL RCC_CFGR_SW1 +#define RCC_CFGR_SWS0 (1 << 2) +#define RCC_CFGR_SWS1 (1 << 3) +#define RCC_CFGR_SWS_MASK 0xC +#define RCC_CFGR_SWS_HSI 0 +#define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0 +#define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1 +#define RCC_CFGR_HPRE_SHIFT 4 +#define RCC_CFGR_PPRE1_SHIFT 10 +#define RCC_CFGR_PPRE2_SHIFT 13 + +#define RCC_APB1ENR_PWREN (1 << 28) + +/* + * RCC USART specific definitions + */ +#define RCC_ENR_USART1EN (1 << 4) +#define RCC_ENR_USART2EN (1 << 17) +#define RCC_ENR_USART3EN (1 << 18) +#define RCC_ENR_USART6EN (1 << 5) + +/* + * Offsets of some PWR registers + */ +#define PWR_CR1_ODEN (1 << 16) +#define PWR_CR1_ODSWEN (1 << 17) +#define PWR_CSR1_ODRDY (1 << 16) +#define PWR_CSR1_ODSWRDY (1 << 17) + + +/* + * RCC GPIO specific definitions + */ +#define RCC_ENR_GPIO_A_EN (1 << 0) +#define RCC_ENR_GPIO_B_EN (1 << 1) +#define RCC_ENR_GPIO_C_EN (1 << 2) +#define RCC_ENR_GPIO_D_EN (1 << 3) +#define RCC_ENR_GPIO_E_EN (1 << 4) +#define RCC_ENR_GPIO_F_EN (1 << 5) +#define RCC_ENR_GPIO_G_EN (1 << 6) +#define RCC_ENR_GPIO_H_EN (1 << 7) +#define RCC_ENR_GPIO_I_EN (1 << 8) +#define RCC_ENR_GPIO_J_EN (1 << 9) +#define RCC_ENR_GPIO_K_EN (1 << 10) + +struct pll_psc { + u8 pll_m; + u16 pll_n; + u8 pll_p; + u8 pll_q; + u8 ahb_psc; + u8 apb1_psc; + u8 apb2_psc; +}; + +#define AHB_PSC_1 0 +#define AHB_PSC_2 0x8 +#define AHB_PSC_4 0x9 +#define AHB_PSC_8 0xA +#define AHB_PSC_16 0xB +#define AHB_PSC_64 0xC +#define AHB_PSC_128 0xD +#define AHB_PSC_256 0xE +#define AHB_PSC_512 0xF + +#define APB_PSC_1 0 +#define APB_PSC_2 0x4 +#define APB_PSC_4 0x5 +#define APB_PSC_8 0x6 +#define APB_PSC_16 0x7 + +#if !defined(CONFIG_STM32_HSE_HZ) +#error "CONFIG_STM32_HSE_HZ not defined!" +#else +#if (CONFIG_STM32_HSE_HZ == 25000000) +#if (CONFIG_SYS_CLK_FREQ == 200000000) +/* 200 MHz */ +struct pll_psc sys_pll_psc = { + .pll_m = 25, + .pll_n = 400, + .pll_p = 2, + .pll_q = 8, + .ahb_psc = AHB_PSC_1, + .apb1_psc = APB_PSC_4, + .apb2_psc = APB_PSC_2 +}; +#endif +#else +#error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists" +#endif +#endif + +int configure_clocks(void) +{ + /* Reset RCC configuration */ + setbits_le32(&STM32_RCC->cr, RCC_CR_HSION); + writel(0, &STM32_RCC->cfgr); /* Reset CFGR */ + clrbits_le32(&STM32_RCC->cr, (RCC_CR_HSEON | RCC_CR_CSSON + | RCC_CR_PLLON)); + writel(0x24003010, &STM32_RCC->pllcfgr); /* Reset value from RM */ + clrbits_le32(&STM32_RCC->cr, RCC_CR_HSEBYP); + writel(0, &STM32_RCC->cir); /* Disable all interrupts */ + + /* Configure for HSE+PLL operation */ + setbits_le32(&STM32_RCC->cr, RCC_CR_HSEON); + while (!(readl(&STM32_RCC->cr) & RCC_CR_HSERDY)) + ; + + setbits_le32(&STM32_RCC->cfgr, (( + sys_pll_psc.ahb_psc << RCC_CFGR_HPRE_SHIFT) + | (sys_pll_psc.apb1_psc << RCC_CFGR_PPRE1_SHIFT) + | (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT))); + + /* Configure the main PLL */ + uint32_t pllcfgr = 0; + pllcfgr = RCC_PLLCFGR_PLLSRC; /* pll source HSE */ + pllcfgr |= sys_pll_psc.pll_m << RCC_PLLCFGR_PLLM_SHIFT; + pllcfgr |= sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT; + pllcfgr |= ((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT; + pllcfgr |= sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT; + writel(pllcfgr, &STM32_RCC->pllcfgr); + + /* Enable the main PLL */ + setbits_le32(&STM32_RCC->cr, RCC_CR_PLLON); + while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY)) + ; + + /* Enable high performance mode, System frequency up to 200 MHz */ + setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_PWREN); + setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODEN); + /* Infinite wait! */ + while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODRDY)) + ; + /* Enable the Over-drive switch */ + setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODSWEN); + /* Infinite wait! */ + while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODSWRDY)) + ; + + stm32_flash_latency_cfg(5); + clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1)); + setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL); + + while ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) != + RCC_CFGR_SWS_PLL) + ; + + return 0; +} + +unsigned long clock_get(enum clock clck) +{ + u32 sysclk = 0; + u32 shift = 0; + /* Prescaler table lookups for clock computation */ + u8 ahb_psc_table[16] = { + 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9 + }; + u8 apb_psc_table[8] = { + 0, 0, 0, 0, 1, 2, 3, 4 + }; + + if ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) == + RCC_CFGR_SWS_PLL) { + u16 pllm, plln, pllp; + pllm = (readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLM_MASK); + plln = ((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLN_MASK) + >> RCC_PLLCFGR_PLLN_SHIFT); + pllp = ((((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLP_MASK) + >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1); + sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp; + } + + switch (clck) { + case CLOCK_CORE: + return sysclk; + break; + case CLOCK_AHB: + shift = ahb_psc_table[( + (readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK) + >> RCC_CFGR_HPRE_SHIFT)]; + return sysclk >>= shift; + break; + case CLOCK_APB1: + shift = apb_psc_table[( + (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB1_PSC_MASK) + >> RCC_CFGR_PPRE1_SHIFT)]; + return sysclk >>= shift; + break; + case CLOCK_APB2: + shift = apb_psc_table[( + (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB2_PSC_MASK) + >> RCC_CFGR_PPRE2_SHIFT)]; + return sysclk >>= shift; + break; + default: + return 0; + break; + } +} + + void clock_setup(int peripheral) { switch (peripheral) { diff --git a/arch/arm/mach-stm32/stm32f7/soc.c b/arch/arm/mach-stm32/stm32f7/soc.c new file mode 100644 index 00000000000..8baee99a4f7 --- /dev/null +++ b/arch/arm/mach-stm32/stm32f7/soc.c @@ -0,0 +1,76 @@ +/* + * (C) Copyright 2015 + * Kamil Lulko, <kamil.lulko@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/armv7m.h> +#include <asm/arch/stm32.h> + +u32 get_cpu_rev(void) +{ + return 0; +} + +int arch_cpu_init(void) +{ + configure_clocks(); + + /* + * Configure the memory protection unit (MPU) + * 0x00000000 - 0xffffffff: Strong-order, Shareable + * 0xC0000000 - 0xC0800000: Normal, Outer and inner Non-cacheable + */ + + /* Disable MPU */ + writel(0, &V7M_MPU->ctrl); + + writel( + 0x00000000 /* address */ + | 1 << 4 /* VALID */ + | 0 << 0 /* REGION */ + , &V7M_MPU->rbar + ); + + /* Strong-order, Shareable */ + /* TEX=000, S=1, C=0, B=0*/ + writel( + (V7M_MPU_RASR_XN_ENABLE + | V7M_MPU_RASR_AP_RW_RW + | 0x01 << V7M_MPU_RASR_S_SHIFT + | 0x00 << V7M_MPU_RASR_TEX_SHIFT + | V7M_MPU_RASR_SIZE_4GB + | V7M_MPU_RASR_EN) + , &V7M_MPU->rasr + ); + + writel( + 0xC0000000 /* address */ + | 1 << 4 /* VALID */ + | 1 << 0 /* REGION */ + , &V7M_MPU->rbar + ); + + /* Normal, Outer and inner Non-cacheable */ + /* TEX=001, S=0, C=0, B=0*/ + writel( + (V7M_MPU_RASR_XN_ENABLE + | V7M_MPU_RASR_AP_RW_RW + | 0x01 << V7M_MPU_RASR_TEX_SHIFT + | V7M_MPU_RASR_SIZE_8MB + | V7M_MPU_RASR_EN) + , &V7M_MPU->rasr + ); + + /* Enable MPU */ + writel(V7M_MPU_CTRL_ENABLE | V7M_MPU_CTRL_HFNMIENA, &V7M_MPU->ctrl); + + return 0; +} + +void s_init(void) +{ +} diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 66e028ec146..6d9518d4c60 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -46,13 +46,15 @@ struct fel_stash fel_stash __attribute__((section(".data"))); static struct mm_region sunxi_mem_map[] = { { /* SRAM, MMIO regions */ - .base = 0x0UL, + .virt = 0x0UL, + .phys = 0x0UL, .size = 0x40000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE }, { /* RAM */ - .base = 0x40000000UL, + .virt = 0x40000000UL, + .phys = 0x40000000UL, .size = 0x80000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE @@ -203,7 +205,8 @@ DECLARE_GLOBAL_DATA_PTR; */ u32 spl_boot_device(void) { - __maybe_unused struct mmc *mmc0, *mmc1; + int boot_source; + /* * When booting from the SD card or NAND memory, the "eGON.BT0" * signature is expected to be found in memory at the address 0x0004 @@ -223,27 +226,19 @@ u32 spl_boot_device(void) if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */ return BOOT_DEVICE_BOARD; - /* The BROM will try to boot from mmc0 first, so try that first. */ -#ifdef CONFIG_MMC - mmc_initialize(gd->bd); - mmc0 = find_mmc_device(0); - if (sunxi_mmc_has_egon_boot_signature(mmc0)) + boot_source = readb(SPL_ADDR + 0x28); + switch (boot_source) { + case SUNXI_BOOTED_FROM_MMC0: return BOOT_DEVICE_MMC1; -#endif - - /* Fallback to booting NAND if enabled. */ - if (IS_ENABLED(CONFIG_SPL_NAND_SUPPORT)) + case SUNXI_BOOTED_FROM_NAND: return BOOT_DEVICE_NAND; - -#ifdef CONFIG_MMC - if (CONFIG_MMC_SUNXI_SLOT_EXTRA == 2) { - mmc1 = find_mmc_device(1); - if (sunxi_mmc_has_egon_boot_signature(mmc1)) - return BOOT_DEVICE_MMC2; + case SUNXI_BOOTED_FROM_MMC2: + return BOOT_DEVICE_MMC2; + case SUNXI_BOOTED_FROM_SPI: + return BOOT_DEVICE_SPI; } -#endif - panic("Could not determine boot source\n"); + panic("Unknown boot source %d\n", boot_source); return -1; /* Never reached */ } diff --git a/arch/arm/mach-sunxi/dram_helpers.c b/arch/arm/mach-sunxi/dram_helpers.c index 20b430f859a..95143d19ab5 100644 --- a/arch/arm/mach-sunxi/dram_helpers.c +++ b/arch/arm/mach-sunxi/dram_helpers.c @@ -32,7 +32,7 @@ bool mctl_mem_matches(u32 offset) /* Try to write different values to RAM at two addresses */ writel(0, CONFIG_SYS_SDRAM_BASE); writel(0xaa55aa55, (ulong)CONFIG_SYS_SDRAM_BASE + offset); - DSB; + dsb(); /* Check if the same value is actually observed when reading back */ return readl(CONFIG_SYS_SDRAM_BASE) == readl((ulong)CONFIG_SYS_SDRAM_BASE + offset); diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index f4affa5512b..1eaf4062725 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -1,5 +1,13 @@ if TEGRA +config TEGRA_IVC + bool "Tegra IVC protocol" + help + IVC (Inter-VM Communication) protocol is a Tegra-specific IPC + (Inter Processor Communication) framework. Within the context of + U-Boot, it is typically used for communication between the main CPU + and various auxiliary processors. + config TEGRA_COMMON bool "Tegra common options" select DM @@ -56,10 +64,17 @@ config TEGRA210 config TEGRA186 bool "Tegra186 family" + select CLK select DM_MAILBOX + select DM_RESET + select MISC + select TEGRA186_BPMP + select TEGRA186_CLOCK select TEGRA186_GPIO + select TEGRA186_RESET select TEGRA_ARMV8_COMMON select TEGRA_HSP + select TEGRA_IVC endchoice diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 12ee1cd7495..b978fec0754 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -15,23 +15,25 @@ else obj-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o endif -obj-$(CONFIG_ARM64) += arm64-mmu.o obj-y += ap.o obj-y += board.o board2.o obj-y += cache.o obj-y += clock.o -obj-y += lowlevel_init.o obj-y += pinmux-common.o obj-y += powergate.o obj-y += xusb-padctl-dummy.o -obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o -obj-$(CONFIG_TEGRA_GPU) += gpu.o -obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o +endif +obj-$(CONFIG_ARM64) += arm64-mmu.o +obj-y += dt-setup.o +obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o +obj-$(CONFIG_TEGRA_GPU) += gpu.o +obj-$(CONFIG_TEGRA_IVC) += ivc.o +obj-y += lowlevel_init.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_ARMV7_PSCI) += psci.o endif -endif +obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o obj-$(CONFIG_TEGRA20) += tegra20/ obj-$(CONFIG_TEGRA30) += tegra30/ diff --git a/arch/arm/mach-tegra/arm64-mmu.c b/arch/arm/mach-tegra/arm64-mmu.c index 501c4f00c4e..7b1d258ed84 100644 --- a/arch/arm/mach-tegra/arm64-mmu.c +++ b/arch/arm/mach-tegra/arm64-mmu.c @@ -14,13 +14,15 @@ static struct mm_region tegra_mem_map[] = { { - .base = 0x0UL, + .virt = 0x0UL, + .phys = 0x0UL, .size = 0x80000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { - .base = 0x80000000UL, + .virt = 0x80000000UL, + .phys = 0x80000000UL, .size = 0xff80000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE diff --git a/arch/arm/mach-tegra/board186.c b/arch/arm/mach-tegra/board186.c index f4b6152a793..1b9799fd80c 100644 --- a/arch/arm/mach-tegra/board186.c +++ b/arch/arm/mach-tegra/board186.c @@ -11,20 +11,19 @@ DECLARE_GLOBAL_DATA_PTR; -int dram_init(void) +int board_early_init_f(void) { - gd->ram_size = (1.5 * 1024 * 1024 * 1024); return 0; } -int board_early_init_f(void) +__weak int tegra_board_init(void) { return 0; } int board_init(void) { - return 0; + return tegra_board_init(); } int board_late_init(void) @@ -32,12 +31,6 @@ int board_late_init(void) return 0; } -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; - gd->bd->bi_dram[0].size = gd->ram_size; -} - void pad_init_mmc(struct mmc_host *host) { } @@ -48,8 +41,3 @@ int board_mmc_init(bd_t *bd) return 0; } - -int ft_system_setup(void *blob, bd_t *bd) -{ - return 0; -} diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 141d6e1cb55..9158ace44c4 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -397,29 +397,3 @@ ulong board_get_usable_ram_top(ulong total_size) { return CONFIG_SYS_SDRAM_BASE + usable_ram_size_below_4g(); } - -/* - * This function is called right before the kernel is booted. "blob" is the - * device tree that will be passed to the kernel. - */ -int ft_system_setup(void *blob, bd_t *bd) -{ - const char *gpu_compats[] = { -#if defined(CONFIG_TEGRA124) - "nvidia,gk20a", -#endif -#if defined(CONFIG_TEGRA210) - "nvidia,gm20b", -#endif - }; - int i, ret; - - /* Enable GPU node if GPU setup has been performed */ - for (i = 0; i < ARRAY_SIZE(gpu_compats); i++) { - ret = tegra_gpu_enable_node(blob, gpu_compats[i]); - if (ret) - return ret; - } - - return 0; -} diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index c50d56dc888..36eabc8f572 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -510,7 +510,7 @@ unsigned clock_get_rate(enum clock_id clkid) * @param p post divider(DIVP) * @param cpcon base PLL charge pump(CPCON) * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot - * be overriden), 1 if PLL is already correct + * be overridden), 1 if PLL is already correct */ int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon) { diff --git a/arch/arm/mach-tegra/cpu.h b/arch/arm/mach-tegra/cpu.h index 3f38969a44f..1154f8b37ef 100644 --- a/arch/arm/mach-tegra/cpu.h +++ b/arch/arm/mach-tegra/cpu.h @@ -16,7 +16,7 @@ #elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114) || \ defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210) #define NVBL_PLLP_KHZ 408000 -#define CSITE_KHZ 204000 +#define CSITE_KHZ 136000 #else #error "Unknown Tegra chip!" #endif diff --git a/arch/arm/mach-tegra/dt-setup.c b/arch/arm/mach-tegra/dt-setup.c new file mode 100644 index 00000000000..f44d9cb04d6 --- /dev/null +++ b/arch/arm/mach-tegra/dt-setup.c @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2010-2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch-tegra/gpu.h> + +/* + * This function is called right before the kernel is booted. "blob" is the + * device tree that will be passed to the kernel. + */ +int ft_system_setup(void *blob, bd_t *bd) +{ + const char *gpu_compats[] = { +#if defined(CONFIG_TEGRA124) + "nvidia,gk20a", +#endif +#if defined(CONFIG_TEGRA210) + "nvidia,gm20b", +#endif + }; + int i, ret; + + /* Enable GPU node if GPU setup has been performed */ + for (i = 0; i < ARRAY_SIZE(gpu_compats); i++) { + ret = tegra_gpu_enable_node(blob, gpu_compats[i]); + if (ret) + return ret; + } + + return 0; +} diff --git a/arch/arm/mach-tegra/ivc.c b/arch/arm/mach-tegra/ivc.c new file mode 100644 index 00000000000..cf6626fb12c --- /dev/null +++ b/arch/arm/mach-tegra/ivc.c @@ -0,0 +1,553 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch-tegra/ivc.h> + +#define TEGRA_IVC_ALIGN 64 + +/* + * IVC channel reset protocol. + * + * Each end uses its tx_channel.state to indicate its synchronization state. + */ +enum ivc_state { + /* + * This value is zero for backwards compatibility with services that + * assume channels to be initially zeroed. Such channels are in an + * initially valid state, but cannot be asynchronously reset, and must + * maintain a valid state at all times. + * + * The transmitting end can enter the established state from the sync or + * ack state when it observes the receiving endpoint in the ack or + * established state, indicating that has cleared the counters in our + * rx_channel. + */ + ivc_state_established = 0, + + /* + * If an endpoint is observed in the sync state, the remote endpoint is + * allowed to clear the counters it owns asynchronously with respect to + * the current endpoint. Therefore, the current endpoint is no longer + * allowed to communicate. + */ + ivc_state_sync, + + /* + * When the transmitting end observes the receiving end in the sync + * state, it can clear the w_count and r_count and transition to the ack + * state. If the remote endpoint observes us in the ack state, it can + * return to the established state once it has cleared its counters. + */ + ivc_state_ack +}; + +/* + * This structure is divided into two-cache aligned parts, the first is only + * written through the tx_channel pointer, while the second is only written + * through the rx_channel pointer. This delineates ownership of the cache lines, + * which is critical to performance and necessary in non-cache coherent + * implementations. + */ +struct tegra_ivc_channel_header { + union { + /* fields owned by the transmitting end */ + struct { + uint32_t w_count; + uint32_t state; + }; + uint8_t w_align[TEGRA_IVC_ALIGN]; + }; + union { + /* fields owned by the receiving end */ + uint32_t r_count; + uint8_t r_align[TEGRA_IVC_ALIGN]; + }; +}; + +static inline void tegra_ivc_invalidate_counter(struct tegra_ivc *ivc, + struct tegra_ivc_channel_header *h, + ulong offset) +{ + ulong base = ((ulong)h) + offset; + invalidate_dcache_range(base, base + TEGRA_IVC_ALIGN); +} + +static inline void tegra_ivc_flush_counter(struct tegra_ivc *ivc, + struct tegra_ivc_channel_header *h, + ulong offset) +{ + ulong base = ((ulong)h) + offset; + flush_dcache_range(base, base + TEGRA_IVC_ALIGN); +} + +static inline ulong tegra_ivc_frame_addr(struct tegra_ivc *ivc, + struct tegra_ivc_channel_header *h, + uint32_t frame) +{ + BUG_ON(frame >= ivc->nframes); + + return ((ulong)h) + sizeof(struct tegra_ivc_channel_header) + + (ivc->frame_size * frame); +} + +static inline void *tegra_ivc_frame_pointer(struct tegra_ivc *ivc, + struct tegra_ivc_channel_header *ch, + uint32_t frame) +{ + return (void *)tegra_ivc_frame_addr(ivc, ch, frame); +} + +static inline void tegra_ivc_invalidate_frame(struct tegra_ivc *ivc, + struct tegra_ivc_channel_header *h, + unsigned frame) +{ + ulong base = tegra_ivc_frame_addr(ivc, h, frame); + invalidate_dcache_range(base, base + ivc->frame_size); +} + +static inline void tegra_ivc_flush_frame(struct tegra_ivc *ivc, + struct tegra_ivc_channel_header *h, + unsigned frame) +{ + ulong base = tegra_ivc_frame_addr(ivc, h, frame); + flush_dcache_range(base, base + ivc->frame_size); +} + +static inline int tegra_ivc_channel_empty(struct tegra_ivc *ivc, + struct tegra_ivc_channel_header *ch) +{ + /* + * This function performs multiple checks on the same values with + * security implications, so create snapshots with ACCESS_ONCE() to + * ensure that these checks use the same values. + */ + uint32_t w_count = ACCESS_ONCE(ch->w_count); + uint32_t r_count = ACCESS_ONCE(ch->r_count); + + /* + * Perform an over-full check to prevent denial of service attacks where + * a server could be easily fooled into believing that there's an + * extremely large number of frames ready, since receivers are not + * expected to check for full or over-full conditions. + * + * Although the channel isn't empty, this is an invalid case caused by + * a potentially malicious peer, so returning empty is safer, because it + * gives the impression that the channel has gone silent. + */ + if (w_count - r_count > ivc->nframes) + return 1; + + return w_count == r_count; +} + +static inline int tegra_ivc_channel_full(struct tegra_ivc *ivc, + struct tegra_ivc_channel_header *ch) +{ + /* + * Invalid cases where the counters indicate that the queue is over + * capacity also appear full. + */ + return (ACCESS_ONCE(ch->w_count) - ACCESS_ONCE(ch->r_count)) >= + ivc->nframes; +} + +static inline void tegra_ivc_advance_rx(struct tegra_ivc *ivc) +{ + ACCESS_ONCE(ivc->rx_channel->r_count) = + ACCESS_ONCE(ivc->rx_channel->r_count) + 1; + + if (ivc->r_pos == ivc->nframes - 1) + ivc->r_pos = 0; + else + ivc->r_pos++; +} + +static inline void tegra_ivc_advance_tx(struct tegra_ivc *ivc) +{ + ACCESS_ONCE(ivc->tx_channel->w_count) = + ACCESS_ONCE(ivc->tx_channel->w_count) + 1; + + if (ivc->w_pos == ivc->nframes - 1) + ivc->w_pos = 0; + else + ivc->w_pos++; +} + +static inline int tegra_ivc_check_read(struct tegra_ivc *ivc) +{ + ulong offset; + + /* + * tx_channel->state is set locally, so it is not synchronized with + * state from the remote peer. The remote peer cannot reset its + * transmit counters until we've acknowledged its synchronization + * request, so no additional synchronization is required because an + * asynchronous transition of rx_channel->state to ivc_state_ack is not + * allowed. + */ + if (ivc->tx_channel->state != ivc_state_established) + return -ECONNRESET; + + /* + * Avoid unnecessary invalidations when performing repeated accesses to + * an IVC channel by checking the old queue pointers first. + * Synchronization is only necessary when these pointers indicate empty + * or full. + */ + if (!tegra_ivc_channel_empty(ivc, ivc->rx_channel)) + return 0; + + offset = offsetof(struct tegra_ivc_channel_header, w_count); + tegra_ivc_invalidate_counter(ivc, ivc->rx_channel, offset); + return tegra_ivc_channel_empty(ivc, ivc->rx_channel) ? -ENOMEM : 0; +} + +static inline int tegra_ivc_check_write(struct tegra_ivc *ivc) +{ + ulong offset; + + if (ivc->tx_channel->state != ivc_state_established) + return -ECONNRESET; + + if (!tegra_ivc_channel_full(ivc, ivc->tx_channel)) + return 0; + + offset = offsetof(struct tegra_ivc_channel_header, r_count); + tegra_ivc_invalidate_counter(ivc, ivc->tx_channel, offset); + return tegra_ivc_channel_full(ivc, ivc->tx_channel) ? -ENOMEM : 0; +} + +static inline uint32_t tegra_ivc_channel_avail_count(struct tegra_ivc *ivc, + struct tegra_ivc_channel_header *ch) +{ + /* + * This function isn't expected to be used in scenarios where an + * over-full situation can lead to denial of service attacks. See the + * comment in tegra_ivc_channel_empty() for an explanation about + * special over-full considerations. + */ + return ACCESS_ONCE(ch->w_count) - ACCESS_ONCE(ch->r_count); +} + +int tegra_ivc_read_get_next_frame(struct tegra_ivc *ivc, void **frame) +{ + int result = tegra_ivc_check_read(ivc); + if (result < 0) + return result; + + /* + * Order observation of w_pos potentially indicating new data before + * data read. + */ + mb(); + + tegra_ivc_invalidate_frame(ivc, ivc->rx_channel, ivc->r_pos); + *frame = tegra_ivc_frame_pointer(ivc, ivc->rx_channel, ivc->r_pos); + + return 0; +} + +int tegra_ivc_read_advance(struct tegra_ivc *ivc) +{ + ulong offset; + int result; + + /* + * No read barriers or synchronization here: the caller is expected to + * have already observed the channel non-empty. This check is just to + * catch programming errors. + */ + result = tegra_ivc_check_read(ivc); + if (result) + return result; + + tegra_ivc_advance_rx(ivc); + offset = offsetof(struct tegra_ivc_channel_header, r_count); + tegra_ivc_flush_counter(ivc, ivc->rx_channel, offset); + + /* + * Ensure our write to r_pos occurs before our read from w_pos. + */ + mb(); + + offset = offsetof(struct tegra_ivc_channel_header, w_count); + tegra_ivc_invalidate_counter(ivc, ivc->rx_channel, offset); + + if (tegra_ivc_channel_avail_count(ivc, ivc->rx_channel) == + ivc->nframes - 1) + ivc->notify(ivc); + + return 0; +} + +int tegra_ivc_write_get_next_frame(struct tegra_ivc *ivc, void **frame) +{ + int result = tegra_ivc_check_write(ivc); + if (result) + return result; + + *frame = tegra_ivc_frame_pointer(ivc, ivc->tx_channel, ivc->w_pos); + + return 0; +} + +int tegra_ivc_write_advance(struct tegra_ivc *ivc) +{ + ulong offset; + int result; + + result = tegra_ivc_check_write(ivc); + if (result) + return result; + + tegra_ivc_flush_frame(ivc, ivc->tx_channel, ivc->w_pos); + + /* + * Order any possible stores to the frame before update of w_pos. + */ + mb(); + + tegra_ivc_advance_tx(ivc); + offset = offsetof(struct tegra_ivc_channel_header, w_count); + tegra_ivc_flush_counter(ivc, ivc->tx_channel, offset); + + /* + * Ensure our write to w_pos occurs before our read from r_pos. + */ + mb(); + + offset = offsetof(struct tegra_ivc_channel_header, r_count); + tegra_ivc_invalidate_counter(ivc, ivc->tx_channel, offset); + + if (tegra_ivc_channel_avail_count(ivc, ivc->tx_channel) == 1) + ivc->notify(ivc); + + return 0; +} + +/* + * =============================================================== + * IVC State Transition Table - see tegra_ivc_channel_notified() + * =============================================================== + * + * local remote action + * ----- ------ ----------------------------------- + * SYNC EST <none> + * SYNC ACK reset counters; move to EST; notify + * SYNC SYNC reset counters; move to ACK; notify + * ACK EST move to EST; notify + * ACK ACK move to EST; notify + * ACK SYNC reset counters; move to ACK; notify + * EST EST <none> + * EST ACK <none> + * EST SYNC reset counters; move to ACK; notify + * + * =============================================================== + */ +int tegra_ivc_channel_notified(struct tegra_ivc *ivc) +{ + ulong offset; + enum ivc_state peer_state; + + /* Copy the receiver's state out of shared memory. */ + offset = offsetof(struct tegra_ivc_channel_header, w_count); + tegra_ivc_invalidate_counter(ivc, ivc->rx_channel, offset); + peer_state = ACCESS_ONCE(ivc->rx_channel->state); + + if (peer_state == ivc_state_sync) { + /* + * Order observation of ivc_state_sync before stores clearing + * tx_channel. + */ + mb(); + + /* + * Reset tx_channel counters. The remote end is in the SYNC + * state and won't make progress until we change our state, + * so the counters are not in use at this time. + */ + ivc->tx_channel->w_count = 0; + ivc->rx_channel->r_count = 0; + + ivc->w_pos = 0; + ivc->r_pos = 0; + + /* + * Ensure that counters appear cleared before new state can be + * observed. + */ + mb(); + + /* + * Move to ACK state. We have just cleared our counters, so it + * is now safe for the remote end to start using these values. + */ + ivc->tx_channel->state = ivc_state_ack; + offset = offsetof(struct tegra_ivc_channel_header, w_count); + tegra_ivc_flush_counter(ivc, ivc->tx_channel, offset); + + /* + * Notify remote end to observe state transition. + */ + ivc->notify(ivc); + } else if (ivc->tx_channel->state == ivc_state_sync && + peer_state == ivc_state_ack) { + /* + * Order observation of ivc_state_sync before stores clearing + * tx_channel. + */ + mb(); + + /* + * Reset tx_channel counters. The remote end is in the ACK + * state and won't make progress until we change our state, + * so the counters are not in use at this time. + */ + ivc->tx_channel->w_count = 0; + ivc->rx_channel->r_count = 0; + + ivc->w_pos = 0; + ivc->r_pos = 0; + + /* + * Ensure that counters appear cleared before new state can be + * observed. + */ + mb(); + + /* + * Move to ESTABLISHED state. We know that the remote end has + * already cleared its counters, so it is safe to start + * writing/reading on this channel. + */ + ivc->tx_channel->state = ivc_state_established; + offset = offsetof(struct tegra_ivc_channel_header, w_count); + tegra_ivc_flush_counter(ivc, ivc->tx_channel, offset); + + /* + * Notify remote end to observe state transition. + */ + ivc->notify(ivc); + } else if (ivc->tx_channel->state == ivc_state_ack) { + /* + * At this point, we have observed the peer to be in either + * the ACK or ESTABLISHED state. Next, order observation of + * peer state before storing to tx_channel. + */ + mb(); + + /* + * Move to ESTABLISHED state. We know that we have previously + * cleared our counters, and we know that the remote end has + * cleared its counters, so it is safe to start writing/reading + * on this channel. + */ + ivc->tx_channel->state = ivc_state_established; + offset = offsetof(struct tegra_ivc_channel_header, w_count); + tegra_ivc_flush_counter(ivc, ivc->tx_channel, offset); + + /* + * Notify remote end to observe state transition. + */ + ivc->notify(ivc); + } else { + /* + * There is no need to handle any further action. Either the + * channel is already fully established, or we are waiting for + * the remote end to catch up with our current state. Refer + * to the diagram in "IVC State Transition Table" above. + */ + } + + if (ivc->tx_channel->state != ivc_state_established) + return -EAGAIN; + + return 0; +} + +void tegra_ivc_channel_reset(struct tegra_ivc *ivc) +{ + ulong offset; + + ivc->tx_channel->state = ivc_state_sync; + offset = offsetof(struct tegra_ivc_channel_header, w_count); + tegra_ivc_flush_counter(ivc, ivc->tx_channel, offset); + ivc->notify(ivc); +} + +static int check_ivc_params(ulong qbase1, ulong qbase2, uint32_t nframes, + uint32_t frame_size) +{ + int ret = 0; + + BUG_ON(offsetof(struct tegra_ivc_channel_header, w_count) & + (TEGRA_IVC_ALIGN - 1)); + BUG_ON(offsetof(struct tegra_ivc_channel_header, r_count) & + (TEGRA_IVC_ALIGN - 1)); + BUG_ON(sizeof(struct tegra_ivc_channel_header) & + (TEGRA_IVC_ALIGN - 1)); + + if ((uint64_t)nframes * (uint64_t)frame_size >= 0x100000000) { + error("tegra_ivc: nframes * frame_size overflows\n"); + return -EINVAL; + } + + /* + * The headers must at least be aligned enough for counters + * to be accessed atomically. + */ + if ((qbase1 & (TEGRA_IVC_ALIGN - 1)) || + (qbase2 & (TEGRA_IVC_ALIGN - 1))) { + error("tegra_ivc: channel start not aligned\n"); + return -EINVAL; + } + + if (frame_size & (TEGRA_IVC_ALIGN - 1)) { + error("tegra_ivc: frame size not adequately aligned\n"); + return -EINVAL; + } + + if (qbase1 < qbase2) { + if (qbase1 + frame_size * nframes > qbase2) + ret = -EINVAL; + } else { + if (qbase2 + frame_size * nframes > qbase1) + ret = -EINVAL; + } + + if (ret) { + error("tegra_ivc: queue regions overlap\n"); + return ret; + } + + return 0; +} + +int tegra_ivc_init(struct tegra_ivc *ivc, ulong rx_base, ulong tx_base, + uint32_t nframes, uint32_t frame_size, + void (*notify)(struct tegra_ivc *)) +{ + int ret; + + if (!ivc) + return -EINVAL; + + ret = check_ivc_params(rx_base, tx_base, nframes, frame_size); + if (ret) + return ret; + + ivc->rx_channel = (struct tegra_ivc_channel_header *)rx_base; + ivc->tx_channel = (struct tegra_ivc_channel_header *)tx_base; + ivc->w_pos = 0; + ivc->r_pos = 0; + ivc->nframes = nframes; + ivc->frame_size = frame_size; + ivc->notify = notify; + + return 0; +} diff --git a/arch/arm/mach-tegra/psci.S b/arch/arm/mach-tegra/psci.S index b836da1c0ed..645d08fa0bd 100644 --- a/arch/arm/mach-tegra/psci.S +++ b/arch/arm/mach-tegra/psci.S @@ -61,9 +61,6 @@ ENTRY(psci_arch_init) ldrne r7, [r5] mcrne p15, 0, r7, c14, c0, 0 @ write CNTFRQ to CPU1..3 - bl psci_get_cpu_stack_top @ stack top => r0 - mov sp, r0 - bx r6 ENDPROC(psci_arch_init) @@ -88,12 +85,13 @@ _loop: wfi ENDPROC(psci_cpu_off) ENTRY(psci_cpu_on) - push {lr} + push {r4, r5, r6, lr} + mov r4, r1 mov r0, r1 - bl psci_get_cpu_stack_top @ get stack top of target CPU - str r2, [r0] @ store target PC at stack top - dsb + mov r1, r2 + bl psci_save_target_pc @ store target PC + mov r1, r4 ldr r6, =TEGRA_RESET_EXCEPTION_VECTOR ldr r5, =psci_cpu_entry @@ -106,9 +104,7 @@ ENTRY(psci_cpu_on) str r5, [r6, r2] mov r0, #ARM_PSCI_RET_SUCCESS @ Return PSCI_RET_SUCCESS - pop {pc} + pop {r4, r5, r6, pc} ENDPROC(psci_cpu_on) - .globl psci_text_end -psci_text_end: .popsection diff --git a/arch/arm/mach-tegra/tegra186/Makefile b/arch/arm/mach-tegra/tegra186/Makefile index ce4610d8f80..033d6005fb4 100644 --- a/arch/arm/mach-tegra/tegra186/Makefile +++ b/arch/arm/mach-tegra/tegra186/Makefile @@ -2,7 +2,6 @@ # # SPDX-License-Identifier: GPL-2.0 -obj-y += ../arm64-mmu.o obj-y += ../board186.o -obj-y += ../lowlevel_init.o -obj-$(CONFIG_DISPLAY_CPUINFO) += ../sys_info.o +obj-y += nvtboot_ll.o +obj-y += nvtboot_mem.o diff --git a/arch/arm/mach-tegra/tegra186/nvtboot_ll.S b/arch/arm/mach-tegra/tegra186/nvtboot_ll.S new file mode 100644 index 00000000000..1eab890958c --- /dev/null +++ b/arch/arm/mach-tegra/tegra186/nvtboot_ll.S @@ -0,0 +1,20 @@ +/* + * Save nvtboot-related boot-time CPU state + * + * (C) Copyright 2015-2016 NVIDIA Corporation <www.nvidia.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <linux/linkage.h> + +.globl nvtboot_boot_x0 +nvtboot_boot_x0: + .dword 0 + +ENTRY(save_boot_params) + adr x8, nvtboot_boot_x0 + str x0, [x8] + b save_boot_params_ret +ENDPROC(save_boot_params) diff --git a/arch/arm/mach-tegra/tegra186/nvtboot_mem.c b/arch/arm/mach-tegra/tegra186/nvtboot_mem.c new file mode 100644 index 00000000000..37dd8d43348 --- /dev/null +++ b/arch/arm/mach-tegra/tegra186/nvtboot_mem.c @@ -0,0 +1,88 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <fdt_support.h> +#include <fdtdec.h> +#include <asm/arch/tegra.h> + +DECLARE_GLOBAL_DATA_PTR; + +extern unsigned long nvtboot_boot_x0; + +/* + * A parsed version of /memory/reg from the DTB that is passed to U-Boot in x0. + * + * We only support up to two banks since that's all the binary bootloader + * ever sets. We assume bank 0 is RAM below 4G and bank 1 is RAM above 4G. + * This is all a fairly safe assumption, since the L4T kernel makes the same + * assumptions, so the bootloader is unlikely to change. + * + * This is written to before relocation, and hence cannot be in .bss, since + * .bss overlaps the DTB that's appended to the U-Boot binary. The initializer + * forces this into .data and avoids this issue. This also has the nice side- + * effect of the content being valid after relocation. + */ +static struct { + u64 start; + u64 size; +} ram_banks[2] = {{1}}; + +int dram_init(void) +{ + unsigned int na, ns; + const void *nvtboot_blob = (void *)nvtboot_boot_x0; + int node, len, i; + const u32 *prop; + + memset(ram_banks, 0, sizeof(ram_banks)); + + na = fdtdec_get_uint(nvtboot_blob, 0, "#address-cells", 2); + ns = fdtdec_get_uint(nvtboot_blob, 0, "#size-cells", 2); + + node = fdt_path_offset(nvtboot_blob, "/memory"); + if (node < 0) { + error("Can't find /memory node in nvtboot DTB"); + hang(); + } + prop = fdt_getprop(nvtboot_blob, node, "reg", &len); + if (!prop) { + error("Can't find /memory/reg property in nvtboot DTB"); + hang(); + } + + len /= (na + ns); + if (len > ARRAY_SIZE(ram_banks)) + len = ARRAY_SIZE(ram_banks); + + gd->ram_size = 0; + for (i = 0; i < len; i++) { + ram_banks[i].start = of_read_number(prop, na); + prop += na; + ram_banks[i].size = of_read_number(prop, ns); + prop += ns; + gd->ram_size += ram_banks[i].size; + } + + return 0; +} + +extern unsigned long nvtboot_boot_x0; + +void dram_init_banksize(void) +{ + int i; + + for (i = 0; i < 2; i++) { + gd->bd->bi_dram[i].start = ram_banks[i].start; + gd->bd->bi_dram[i].size = ram_banks[i].size; + } +} + +ulong board_get_usable_ram_top(ulong total_size) +{ + return ram_banks[0].start + ram_banks[0].size; +} diff --git a/arch/arm/mach-tegra/tegra20/Makefile b/arch/arm/mach-tegra/tegra20/Makefile index 17c19900e21..72d82a5218f 100644 --- a/arch/arm/mach-tegra/tegra20/Makefile +++ b/arch/arm/mach-tegra/tegra20/Makefile @@ -10,7 +10,8 @@ endif # The AVP is ARMv4T architecture so we must use special compiler # flags for any startup files it might use. -CFLAGS_warmboot_avp.o += -march=armv4t +CFLAGS_warmboot_avp.o = -march=armv4t -U__LINUX_ARM_ARCH__ \ + -D__LINUX_ARM_ARCH__=4 obj-y += clock.o funcmux.o pinmux.o obj-$(CONFIG_TEGRA_LP0) += warmboot.o crypto.o warmboot_avp.o diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig index e256eeb6686..a8a0b90c39b 100644 --- a/arch/arm/mach-uniphier/Kconfig +++ b/arch/arm/mach-uniphier/Kconfig @@ -6,12 +6,15 @@ config SYS_CONFIG_NAME config ARCH_UNIPHIER_32BIT bool select CPU_V7 + select CPU_V7_HAS_NONSEC + select ARMV7_NONSEC config ARCH_UNIPHIER_64BIT bool select ARM64 select SPL_SEPARATE_BSS select ARMV8_MULTIENTRY + select ARMV8_SPIN_TABLE choice prompt "UniPhier SoC select" @@ -69,6 +72,13 @@ config ARCH_UNIPHIER_LD6B depends on ARCH_UNIPHIER_PRO5_PXS2_LD6B default y +config CACHE_UNIPHIER + bool "Enable the UniPhier L2 cache controller" + depends on ARCH_UNIPHIER_32BIT + default y + help + This option allows to use the UniPhier System Cache as L2 cache. + config MICRO_SUPPORT_CARD bool "Use Micro Support Card" help diff --git a/arch/arm/mach-uniphier/arm32/Makefile b/arch/arm/mach-uniphier/arm32/Makefile index 376c06b5975..6f05d727e02 100644 --- a/arch/arm/mach-uniphier/arm32/Makefile +++ b/arch/arm/mach-uniphier/arm32/Makefile @@ -7,7 +7,8 @@ obj-y += lowlevel_init.o obj-$(CONFIG_DEBUG_LL) += debug_ll.o else obj-y += late_lowlevel_init.o -obj-y += cache_uniphier.o +obj-y += cache-uniphier.o +obj-$(CONFIG_ARMV7_PSCI) += psci.o psci_smp.o endif obj-y += timer.o diff --git a/arch/arm/mach-uniphier/arm32/arm-mpcore.h b/arch/arm/mach-uniphier/arm32/arm-mpcore.h index cf7cd46c10c..1a856641dec 100644 --- a/arch/arm/mach-uniphier/arm32/arm-mpcore.h +++ b/arch/arm/mach-uniphier/arm32/arm-mpcore.h @@ -12,6 +12,9 @@ /* SCU Control Register */ #define SCU_CTRL 0x00 +#define SCU_ENABLE (1 << 0) +#define SCU_STANDBY_ENABLE (1 << 5) + /* SCU Configuration Register */ #define SCU_CONF 0x04 /* SCU CPU Power Status Register */ diff --git a/arch/arm/mach-uniphier/arm32/cache-uniphier.c b/arch/arm/mach-uniphier/arm32/cache-uniphier.c new file mode 100644 index 00000000000..658969b0491 --- /dev/null +++ b/arch/arm/mach-uniphier/arm32/cache-uniphier.c @@ -0,0 +1,296 @@ +/* + * Copyright (C) 2012-2014 Panasonic Corporation + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <asm/armv7.h> +#include <asm/processor.h> + +#include "cache-uniphier.h" + +/* control registers */ +#define UNIPHIER_SSCC 0x500c0000 /* Control Register */ +#define UNIPHIER_SSCC_BST (0x1 << 20) /* UCWG burst read */ +#define UNIPHIER_SSCC_ACT (0x1 << 19) /* Inst-Data separate */ +#define UNIPHIER_SSCC_WTG (0x1 << 18) /* WT gathering on */ +#define UNIPHIER_SSCC_PRD (0x1 << 17) /* enable pre-fetch */ +#define UNIPHIER_SSCC_ON (0x1 << 0) /* enable cache */ +#define UNIPHIER_SSCLPDAWCR 0x500c0030 /* Unified/Data Active Way Control */ +#define UNIPHIER_SSCLPIAWCR 0x500c0034 /* Instruction Active Way Control */ + +/* revision registers */ +#define UNIPHIER_SSCID 0x503c0100 /* ID Register */ + +/* operation registers */ +#define UNIPHIER_SSCOPE 0x506c0244 /* Cache Operation Primitive Entry */ +#define UNIPHIER_SSCOPE_CM_INV 0x0 /* invalidate */ +#define UNIPHIER_SSCOPE_CM_CLEAN 0x1 /* clean */ +#define UNIPHIER_SSCOPE_CM_FLUSH 0x2 /* flush */ +#define UNIPHIER_SSCOPE_CM_SYNC 0x8 /* sync (drain bufs) */ +#define UNIPHIER_SSCOPE_CM_FLUSH_PREFETCH 0x9 /* flush p-fetch buf */ +#define UNIPHIER_SSCOQM 0x506c0248 +#define UNIPHIER_SSCOQM_TID_MASK (0x3 << 21) +#define UNIPHIER_SSCOQM_TID_LRU_DATA (0x0 << 21) +#define UNIPHIER_SSCOQM_TID_LRU_INST (0x1 << 21) +#define UNIPHIER_SSCOQM_TID_WAY (0x2 << 21) +#define UNIPHIER_SSCOQM_S_MASK (0x3 << 17) +#define UNIPHIER_SSCOQM_S_RANGE (0x0 << 17) +#define UNIPHIER_SSCOQM_S_ALL (0x1 << 17) +#define UNIPHIER_SSCOQM_S_WAY (0x2 << 17) +#define UNIPHIER_SSCOQM_CE (0x1 << 15) /* notify completion */ +#define UNIPHIER_SSCOQM_CW (0x1 << 14) +#define UNIPHIER_SSCOQM_CM_MASK (0x7) +#define UNIPHIER_SSCOQM_CM_INV 0x0 /* invalidate */ +#define UNIPHIER_SSCOQM_CM_CLEAN 0x1 /* clean */ +#define UNIPHIER_SSCOQM_CM_FLUSH 0x2 /* flush */ +#define UNIPHIER_SSCOQM_CM_PREFETCH 0x3 /* prefetch to cache */ +#define UNIPHIER_SSCOQM_CM_PREFETCH_BUF 0x4 /* prefetch to pf-buf */ +#define UNIPHIER_SSCOQM_CM_TOUCH 0x5 /* touch */ +#define UNIPHIER_SSCOQM_CM_TOUCH_ZERO 0x6 /* touch to zero */ +#define UNIPHIER_SSCOQM_CM_TOUCH_DIRTY 0x7 /* touch with dirty */ +#define UNIPHIER_SSCOQAD 0x506c024c /* Cache Operation Queue Address */ +#define UNIPHIER_SSCOQSZ 0x506c0250 /* Cache Operation Queue Size */ +#define UNIPHIER_SSCOQMASK 0x506c0254 /* Cache Operation Queue Address Mask */ +#define UNIPHIER_SSCOQWN 0x506c0258 /* Cache Operation Queue Way Number */ +#define UNIPHIER_SSCOPPQSEF 0x506c025c /* Cache Operation Queue Set Complete */ +#define UNIPHIER_SSCOPPQSEF_FE (0x1 << 1) +#define UNIPHIER_SSCOPPQSEF_OE (0x1 << 0) +#define UNIPHIER_SSCOLPQS 0x506c0260 /* Cache Operation Queue Status */ +#define UNIPHIER_SSCOLPQS_EF (0x1 << 2) +#define UNIPHIER_SSCOLPQS_EST (0x1 << 1) +#define UNIPHIER_SSCOLPQS_QST (0x1 << 0) + +#define UNIPHIER_SSC_LINE_SIZE 128 +#define UNIPHIER_SSC_RANGE_OP_MAX_SIZE (0x00400000 - (UNIPHIER_SSC_LINE_SIZE)) + +#define UNIPHIER_SSCOQAD_IS_NEEDED(op) \ + ((op & UNIPHIER_SSCOQM_S_MASK) == UNIPHIER_SSCOQM_S_RANGE) +#define UNIPHIER_SSCOQWM_IS_NEEDED(op) \ + (((op & UNIPHIER_SSCOQM_S_MASK) == UNIPHIER_SSCOQM_S_WAY) || \ + ((op & UNIPHIER_SSCOQM_TID_MASK) == UNIPHIER_SSCOQM_TID_WAY)) + +/* uniphier_cache_sync - perform a sync point for a particular cache level */ +static void uniphier_cache_sync(void) +{ + /* drain internal buffers */ + writel(UNIPHIER_SSCOPE_CM_SYNC, UNIPHIER_SSCOPE); + /* need a read back to confirm */ + readl(UNIPHIER_SSCOPE); +} + +/** + * uniphier_cache_maint_common - run a queue operation + * + * @start: start address of range operation (don't care for "all" operation) + * @size: data size of range operation (don't care for "all" operation) + * @ways: target ways (don't care for operations other than pre-fetch, touch + * @operation: flags to specify the desired cache operation + */ +static void uniphier_cache_maint_common(u32 start, u32 size, u32 ways, + u32 operation) +{ + /* clear the complete notification flag */ + writel(UNIPHIER_SSCOLPQS_EF, UNIPHIER_SSCOLPQS); + + do { + /* set cache operation */ + writel(UNIPHIER_SSCOQM_CE | operation, UNIPHIER_SSCOQM); + + /* set address range if needed */ + if (likely(UNIPHIER_SSCOQAD_IS_NEEDED(operation))) { + writel(start, UNIPHIER_SSCOQAD); + writel(size, UNIPHIER_SSCOQSZ); + } + + /* set target ways if needed */ + if (unlikely(UNIPHIER_SSCOQWM_IS_NEEDED(operation))) + writel(ways, UNIPHIER_SSCOQWN); + } while (unlikely(readl(UNIPHIER_SSCOPPQSEF) & + (UNIPHIER_SSCOPPQSEF_FE | UNIPHIER_SSCOPPQSEF_OE))); + + /* wait until the operation is completed */ + while (likely(readl(UNIPHIER_SSCOLPQS) != UNIPHIER_SSCOLPQS_EF)) + cpu_relax(); +} + +static void uniphier_cache_maint_all(u32 operation) +{ + uniphier_cache_maint_common(0, 0, 0, UNIPHIER_SSCOQM_S_ALL | operation); + + uniphier_cache_sync(); +} + +static void uniphier_cache_maint_range(u32 start, u32 end, u32 ways, + u32 operation) +{ + u32 size; + + /* + * If the start address is not aligned, + * perform a cache operation for the first cache-line + */ + start = start & ~(UNIPHIER_SSC_LINE_SIZE - 1); + + size = end - start; + + if (unlikely(size >= (u32)(-UNIPHIER_SSC_LINE_SIZE))) { + /* this means cache operation for all range */ + uniphier_cache_maint_all(operation); + return; + } + + /* + * If the end address is not aligned, + * perform a cache operation for the last cache-line + */ + size = ALIGN(size, UNIPHIER_SSC_LINE_SIZE); + + while (size) { + u32 chunk_size = min_t(u32, size, UNIPHIER_SSC_RANGE_OP_MAX_SIZE); + + uniphier_cache_maint_common(start, chunk_size, ways, + UNIPHIER_SSCOQM_S_RANGE | operation); + + start += chunk_size; + size -= chunk_size; + } + + uniphier_cache_sync(); +} + +void uniphier_cache_prefetch_range(u32 start, u32 end, u32 ways) +{ + uniphier_cache_maint_range(start, end, ways, + UNIPHIER_SSCOQM_TID_WAY | + UNIPHIER_SSCOQM_CM_PREFETCH); +} + +void uniphier_cache_touch_range(u32 start, u32 end, u32 ways) +{ + uniphier_cache_maint_range(start, end, ways, + UNIPHIER_SSCOQM_TID_WAY | + UNIPHIER_SSCOQM_CM_TOUCH); +} + +void uniphier_cache_touch_zero_range(u32 start, u32 end, u32 ways) +{ + uniphier_cache_maint_range(start, end, ways, + UNIPHIER_SSCOQM_TID_WAY | + UNIPHIER_SSCOQM_CM_TOUCH_ZERO); +} + +void uniphier_cache_inv_way(u32 ways) +{ + uniphier_cache_maint_common(0, 0, ways, + UNIPHIER_SSCOQM_S_WAY | + UNIPHIER_SSCOQM_CM_INV); +} + +void uniphier_cache_set_active_ways(int cpu, u32 active_ways) +{ + void __iomem *base = (void __iomem *)UNIPHIER_SSCC + 0xc00; + + switch (readl(UNIPHIER_SSCID)) { /* revision */ + case 0x11: /* sLD3 */ + base = (void __iomem *)UNIPHIER_SSCC + 0x870; + break; + case 0x12: /* LD4 */ + case 0x16: /* sld8 */ + base = (void __iomem *)UNIPHIER_SSCC + 0x840; + break; + default: + base = (void __iomem *)UNIPHIER_SSCC + 0xc00; + break; + } + + writel(active_ways, base + 4 * cpu); +} + +static void uniphier_cache_endisable(int enable) +{ + u32 tmp; + + tmp = readl(UNIPHIER_SSCC); + if (enable) + tmp |= UNIPHIER_SSCC_ON; + else + tmp &= ~UNIPHIER_SSCC_ON; + writel(tmp, UNIPHIER_SSCC); +} + +void uniphier_cache_enable(void) +{ + uniphier_cache_endisable(1); +} + +void uniphier_cache_disable(void) +{ + uniphier_cache_endisable(0); +} + +#ifdef CONFIG_CACHE_UNIPHIER +void v7_outer_cache_flush_all(void) +{ + uniphier_cache_maint_all(UNIPHIER_SSCOQM_CM_FLUSH); +} + +void v7_outer_cache_inval_all(void) +{ + uniphier_cache_maint_all(UNIPHIER_SSCOQM_CM_INV); +} + +void v7_outer_cache_flush_range(u32 start, u32 end) +{ + uniphier_cache_maint_range(start, end, 0, UNIPHIER_SSCOQM_CM_FLUSH); +} + +void v7_outer_cache_inval_range(u32 start, u32 end) +{ + if (start & (UNIPHIER_SSC_LINE_SIZE - 1)) { + start &= ~(UNIPHIER_SSC_LINE_SIZE - 1); + uniphier_cache_maint_range(start, UNIPHIER_SSC_LINE_SIZE, 0, + UNIPHIER_SSCOQM_CM_FLUSH); + start += UNIPHIER_SSC_LINE_SIZE; + } + + if (start >= end) { + uniphier_cache_sync(); + return; + } + + if (end & (UNIPHIER_SSC_LINE_SIZE - 1)) { + end &= ~(UNIPHIER_SSC_LINE_SIZE - 1); + uniphier_cache_maint_range(end, UNIPHIER_SSC_LINE_SIZE, 0, + UNIPHIER_SSCOQM_CM_FLUSH); + } + + if (start >= end) { + uniphier_cache_sync(); + return; + } + + uniphier_cache_maint_range(start, end, 0, UNIPHIER_SSCOQM_CM_INV); +} + +void v7_outer_cache_enable(void) +{ + uniphier_cache_set_active_ways(0, U32_MAX); /* activate all ways */ + uniphier_cache_enable(); +} + +void v7_outer_cache_disable(void) +{ + uniphier_cache_disable(); +} +#endif + +void enable_caches(void) +{ + dcache_enable(); +} diff --git a/arch/arm/mach-uniphier/arm32/cache-uniphier.h b/arch/arm/mach-uniphier/arm32/cache-uniphier.h new file mode 100644 index 00000000000..493d66c1897 --- /dev/null +++ b/arch/arm/mach-uniphier/arm32/cache-uniphier.h @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CACHE_UNIPHIER_H +#define __CACHE_UNIPHIER_H + +#include <linux/types.h> + +void uniphier_cache_prefetch_range(u32 start, u32 end, u32 ways); +void uniphier_cache_touch_range(u32 start, u32 end, u32 ways); +void uniphier_cache_touch_zero_range(u32 start, u32 end, u32 ways); +void uniphier_cache_inv_way(u32 ways); +void uniphier_cache_set_active_ways(int cpu, u32 active_ways); +void uniphier_cache_enable(void); +void uniphier_cache_disable(void); + +#endif /* __CACHE_UNIPHIER_H */ diff --git a/arch/arm/mach-uniphier/arm32/cache_uniphier.c b/arch/arm/mach-uniphier/arm32/cache_uniphier.c deleted file mode 100644 index 43981146585..00000000000 --- a/arch/arm/mach-uniphier/arm32/cache_uniphier.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <linux/io.h> -#include <asm/armv7.h> - -#include "ssc-regs.h" - -#ifdef CONFIG_UNIPHIER_L2CACHE_ON -static void uniphier_cache_sync(void) -{ - writel(SSCOPE_CM_SYNC, SSCOPE); /* drain internal buffers */ - readl(SSCOPE); /* need a read back to confirm */ -} - -static void uniphier_cache_maint_all(u32 operation) -{ - /* try until the command is successfully set */ - do { - writel(SSCOQM_S_ALL | SSCOQM_CE | operation, SSCOQM); - } while (readl(SSCOPPQSEF) & (SSCOPPQSEF_FE | SSCOPPQSEF_OE)); - - /* wait until the operation is completed */ - while (readl(SSCOLPQS) != SSCOLPQS_EF) - ; - - /* clear the complete notification flag */ - writel(SSCOLPQS_EF, SSCOLPQS); - - uniphier_cache_sync(); -} - -void v7_outer_cache_flush_all(void) -{ - uniphier_cache_maint_all(SSCOQM_CM_WB_INV); -} - -void v7_outer_cache_inval_all(void) -{ - uniphier_cache_maint_all(SSCOQM_CM_INV); -} - -static void __uniphier_cache_maint_range(u32 start, u32 size, u32 operation) -{ - /* try until the command is successfully set */ - do { - writel(SSCOQM_S_ADDRESS | SSCOQM_CE | operation, SSCOQM); - writel(start, SSCOQAD); - writel(size, SSCOQSZ); - - } while (readl(SSCOPPQSEF) & (SSCOPPQSEF_FE | SSCOPPQSEF_OE)); - - /* wait until the operation is completed */ - while (readl(SSCOLPQS) != SSCOLPQS_EF) - ; - - /* clear the complete notification flag */ - writel(SSCOLPQS_EF, SSCOLPQS); -} - -static void uniphier_cache_maint_range(u32 start, u32 end, u32 operation) -{ - u32 size; - - /* - * If start address is not aligned to cache-line, - * do cache operation for the first cache-line - */ - start = start & ~(SSC_LINE_SIZE - 1); - - size = end - start; - - if (unlikely(size >= (u32)(-SSC_LINE_SIZE))) { - /* this means cache operation for all range */ - uniphier_cache_maint_all(operation); - return; - } - - /* - * If end address is not aligned to cache-line, - * do cache operation for the last cache-line - */ - size = ALIGN(size, SSC_LINE_SIZE); - - while (size) { - u32 chunk_size = size > SSC_RANGE_OP_MAX_SIZE ? - SSC_RANGE_OP_MAX_SIZE : size; - __uniphier_cache_maint_range(start, chunk_size, operation); - - start += chunk_size; - size -= chunk_size; - } - - uniphier_cache_sync(); -} - -void v7_outer_cache_flush_range(u32 start, u32 end) -{ - uniphier_cache_maint_range(start, end, SSCOQM_CM_WB_INV); -} - -void v7_outer_cache_inval_range(u32 start, u32 end) -{ - if (start & (SSC_LINE_SIZE - 1)) { - start &= ~(SSC_LINE_SIZE - 1); - __uniphier_cache_maint_range(start, SSC_LINE_SIZE, - SSCOQM_CM_WB_INV); - start += SSC_LINE_SIZE; - } - - if (start >= end) { - uniphier_cache_sync(); - return; - } - - if (end & (SSC_LINE_SIZE - 1)) { - end &= ~(SSC_LINE_SIZE - 1); - __uniphier_cache_maint_range(end, SSC_LINE_SIZE, - SSCOQM_CM_WB_INV); - } - - if (start >= end) { - uniphier_cache_sync(); - return; - } - - uniphier_cache_maint_range(start, end, SSCOQM_CM_INV); -} - -void v7_outer_cache_enable(void) -{ - u32 tmp; - - writel(U32_MAX, SSCLPDAWCR); /* activate all ways */ - tmp = readl(SSCC); - tmp |= SSCC_ON; - writel(tmp, SSCC); -} -#endif - -void v7_outer_cache_disable(void) -{ - u32 tmp; - tmp = readl(SSCC); - tmp &= ~SSCC_ON; - writel(tmp, SSCC); -} - -void enable_caches(void) -{ - dcache_enable(); -} diff --git a/arch/arm/mach-uniphier/arm32/late_lowlevel_init.S b/arch/arm/mach-uniphier/arm32/late_lowlevel_init.S index cce91dfac7b..6f40362cc96 100644 --- a/arch/arm/mach-uniphier/arm32/late_lowlevel_init.S +++ b/arch/arm/mach-uniphier/arm32/late_lowlevel_init.S @@ -5,14 +5,10 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include <config.h> #include <linux/linkage.h> -#include "ssc-regs.h" - ENTRY(lowlevel_init) - ldr r1, = SSCC - ldr r0, [r1] - bic r0, r0, #SSCC_ON @ L2 disable - str r0, [r1] - mov pc, lr + ldr sp, = CONFIG_SYS_INIT_SP_ADDR + b uniphier_cache_disable ENDPROC(lowlevel_init) diff --git a/arch/arm/mach-uniphier/arm32/lowlevel_init.S b/arch/arm/mach-uniphier/arm32/lowlevel_init.S index cc34116baae..af5ed1c050f 100644 --- a/arch/arm/mach-uniphier/arm32/lowlevel_init.S +++ b/arch/arm/mach-uniphier/arm32/lowlevel_init.S @@ -1,5 +1,7 @@ /* - * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2012-2015 Panasonic Corporation + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -9,8 +11,6 @@ #include <linux/sizes.h> #include <asm/system.h> -#include "ssc-regs.h" - ENTRY(lowlevel_init) mov r8, lr @ persevere link reg across call @@ -25,10 +25,6 @@ ENTRY(lowlevel_init) orr r0, r0, #(CR_C | CR_M) @ enable MMU and Dcache mcr p15, 0, r0, c1, c0, 0 -#ifdef CONFIG_DEBUG_LL - bl debug_ll_init -#endif - bl setup_init_ram @ RAM area for stack and page table /* @@ -47,6 +43,10 @@ ENTRY(lowlevel_init) bl enable_mmu +#ifdef CONFIG_DEBUG_LL + bl debug_ll_init +#endif + mov lr, r8 @ restore link mov pc, lr @ back to my caller ENDPROC(lowlevel_init) @@ -86,39 +86,42 @@ ENDPROC(enable_mmu) */ #define BOOT_RAM_SIZE (SZ_32K) #define BOOT_RAM_BASE ((CONFIG_SPL_STACK) - (BOOT_RAM_SIZE)) -#define BOOT_WAY_BITS (0x00000100) /* way 8 */ +#define BOOT_RAM_WAYS (0x00000100) @ way 8 + +#define SSCO_BASE 0x506c0000 +#define SSCOPE 0x244 +#define SSCOQM 0x248 +#define SSCOQAD 0x24c +#define SSCOQSZ 0x250 +#define SSCOQWN 0x258 +#define SSCOPPQSEF 0x25c +#define SSCOLPQS 0x260 ENTRY(setup_init_ram) - /* - * Touch to zero for the boot way - */ -0: - /* - * set SSCOQM, SSCOQAD, SSCOQSZ, SSCOQWN in this order - */ - ldr r0, = 0x00408006 @ touch to zero with address range - ldr r1, = SSCOQM - str r0, [r1] + ldr r1, = SSCO_BASE + mrc p15, 0, r0, c2, c0, 0 @ TTBR0 + ldr r0, [r0, #0x400] @ entry for virtual address 0x100***** + bfc r0, #0, #20 + cmp r0, #0x50000000 @ is sLD3 page table? + biceq r1, r1, #0xc0000000 @ sLD3 ROM maps 0x5******* to 0x1******* + + /* Touch to zero for the boot way */ +0: ldr r0, = 0x00408006 @ touch to zero with address range + str r0, [r1, #SSCOQM] ldr r0, = BOOT_RAM_BASE - ldr r1, = SSCOQAD - str r0, [r1] + str r0, [r1, #SSCOQAD] ldr r0, = BOOT_RAM_SIZE - ldr r1, = SSCOQSZ - str r0, [r1] - ldr r0, = BOOT_WAY_BITS - ldr r1, = SSCOQWN - str r0, [r1] - ldr r1, = SSCOPPQSEF - ldr r0, [r1] + str r0, [r1, #SSCOQSZ] + ldr r0, = BOOT_RAM_WAYS + str r0, [r1, #SSCOQWN] + ldr r0, [r1, #SSCOPPQSEF] cmp r0, #0 @ check if the command is successfully set bne 0b @ try again if an error occurs - ldr r1, = SSCOLPQS -1: - ldr r0, [r1] +1: ldr r0, [r1, #SSCOLPQS] cmp r0, #0x4 bne 1b @ wait until the operation is completed - str r0, [r1] @ clear the complete notification flag + str r0, [r1, #SSCOLPQS] @ clear the complete notification flag mov pc, lr ENDPROC(setup_init_ram) diff --git a/arch/arm/mach-uniphier/arm32/psci.c b/arch/arm/mach-uniphier/arm32/psci.c new file mode 100644 index 00000000000..633a3e08402 --- /dev/null +++ b/arch/arm/mach-uniphier/arm32/psci.c @@ -0,0 +1,153 @@ +/* + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <linux/bitops.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/psci.h> +#include <linux/sizes.h> +#include <asm/processor.h> +#include <asm/psci.h> +#include <asm/secure.h> + +#include "../debug.h" +#include "../soc-info.h" +#include "arm-mpcore.h" +#include "cache-uniphier.h" + +#define UNIPHIER_SMPCTRL_ROM_RSV2 0x59801208 + +void uniphier_smp_trampoline(void); +void uniphier_smp_trampoline_end(void); +u32 uniphier_smp_booted[CONFIG_ARMV7_PSCI_NR_CPUS]; + +static int uniphier_get_nr_cpus(void) +{ + switch (uniphier_get_soc_type()) { + case SOC_UNIPHIER_SLD3: + case SOC_UNIPHIER_PRO4: + case SOC_UNIPHIER_PRO5: + return 2; + case SOC_UNIPHIER_PXS2: + case SOC_UNIPHIER_LD6B: + return 4; + default: + return 1; + } +} + +static void uniphier_smp_kick_all_cpus(void) +{ + const u32 target_ways = BIT(0); + size_t trmp_size; + u32 trmp_src = (unsigned long)uniphier_smp_trampoline; + u32 trmp_src_end = (unsigned long)uniphier_smp_trampoline_end; + u32 trmp_dest, trmp_dest_end; + int nr_cpus, i; + int timeout = 1000; + + nr_cpus = uniphier_get_nr_cpus(); + if (nr_cpus == 1) + return; + + for (i = 0; i < nr_cpus; i++) /* lock ways for all CPUs */ + uniphier_cache_set_active_ways(i, 0); + uniphier_cache_inv_way(target_ways); + uniphier_cache_enable(); + + /* copy trampoline code */ + uniphier_cache_prefetch_range(trmp_src, trmp_src_end, target_ways); + + trmp_size = trmp_src_end - trmp_src; + + trmp_dest = trmp_src & (SZ_64K - 1); + trmp_dest += SZ_1M - SZ_64K * 2; + + trmp_dest_end = trmp_dest + trmp_size; + + uniphier_cache_touch_range(trmp_dest, trmp_dest_end, target_ways); + + writel(trmp_dest, UNIPHIER_SMPCTRL_ROM_RSV2); + + asm("dsb ishst\n" /* Ensure the write to ROM_RSV2 is visible */ + "sev"); /* Bring up all secondary CPUs from Boot ROM into U-Boot */ + + while (--timeout) { + int all_booted = 1; + + for (i = 1; i < nr_cpus; i++) + if (!uniphier_smp_booted[i]) + all_booted = 0; + if (all_booted) + break; + udelay(1); + + /* barrier here because uniphier_smp_booted[] may be updated */ + cpu_relax(); + } + + if (!timeout) + printf("warning: some of secondary CPUs may not boot\n"); + + uniphier_cache_disable(); +} + +void psci_board_init(void) +{ + unsigned long scu_base; + u32 scu_ctrl, tmp; + + asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (scu_base)); + + scu_ctrl = readl(scu_base + 0x30); + if (!(scu_ctrl & 1)) + writel(scu_ctrl | 0x1, scu_base + 0x30); + + scu_ctrl = readl(scu_base + SCU_CTRL); + scu_ctrl |= SCU_ENABLE | SCU_STANDBY_ENABLE; + writel(scu_ctrl, scu_base + SCU_CTRL); + + tmp = readl(scu_base + SCU_SNSAC); + tmp |= 0xfff; + writel(tmp, scu_base + SCU_SNSAC); + + uniphier_smp_kick_all_cpus(); +} + +void psci_arch_init(void) +{ + u32 actlr; + + asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (actlr)); + actlr |= 0x41; /* set SMP and FW bits */ + asm("mcr p15, 0, %0, c1, c0, 1" : : "r" (actlr)); +} + +u32 uniphier_psci_holding_pen_release __secure_data = 0xffffffff; + +int __secure psci_cpu_on(u32 function_id, u32 cpuid, u32 entry_point) +{ + u32 cpu = cpuid & 0xff; + + debug_puts("[U-Boot PSCI] psci_cpu_on: cpuid="); + debug_puth(cpuid); + debug_puts(", entry_point="); + debug_puth(entry_point); + debug_puts("\n"); + + psci_save_target_pc(cpu, entry_point); + + /* We assume D-cache is off, so do not call flush_dcache() here */ + uniphier_psci_holding_pen_release = cpu; + + /* Send an event to wake up the secondary CPU. */ + asm("dsb ishst\n" + "sev"); + + return PSCI_RET_SUCCESS; +} diff --git a/arch/arm/mach-uniphier/arm32/psci_smp.S b/arch/arm/mach-uniphier/arm32/psci_smp.S new file mode 100644 index 00000000000..aa2fa5f3fc2 --- /dev/null +++ b/arch/arm/mach-uniphier/arm32/psci_smp.S @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/linkage.h> +#include <asm/system.h> + + .section ._secure.text, "ax" + +ENTRY(uniphier_smp_trampoline) + ldr r0, 0f + mrc p15, 0, r1, c1, c0, 0 @ SCTLR (System Control Register) + orr r1, r1, #CR_I @ Enable ICache + bic r1, r1, #(CR_C | CR_M) @ Disable MMU and Dcache + mcr p15, 0, r1, c1, c0, 0 + + bx r0 +0: .word uniphier_secondary_startup + .globl uniphier_smp_trampoline_end +uniphier_smp_trampoline_end: +ENDPROC(uniphier_smp_trampoline) + +LENTRY(uniphier_secondary_startup) + mrc p15, 0, r1, c0, c0, 5 @ MPIDR (Multiprocessor Affinity Reg) + and r1, r1, #0xff + + ldr r2, =uniphier_smp_booted + mov r0, #1 + str r0, [r2, r1, lsl #2] + + ldr r2, =uniphier_psci_holding_pen_release +pen: ldr r0, [r2] + cmp r0, r1 + beq psci_cpu_entry + wfe + b pen +ENDPROC(uniphier_secondary_startup) diff --git a/arch/arm/mach-uniphier/arm32/ssc-regs.h b/arch/arm/mach-uniphier/arm32/ssc-regs.h deleted file mode 100644 index 02fca3b6f61..00000000000 --- a/arch/arm/mach-uniphier/arm32/ssc-regs.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * UniPhier System Cache (L2 Cache) registers - * - * Copyright (C) 2011-2014 Panasonic Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef ARCH_SSC_REGS_H -#define ARCH_SSC_REGS_H - -#define SSCC 0x500c0000 -#define SSCC_BST (0x1 << 20) -#define SSCC_ACT (0x1 << 19) -#define SSCC_WTG (0x1 << 18) -#define SSCC_PRD (0x1 << 17) -#define SSCC_WBWA (0x1 << 16) -#define SSCC_EX (0x1 << 13) -#define SSCC_ON (0x1 << 0) - -#define SSCLPDAWCR 0x500c0030 - -#define SSCOPE 0x506c0244 -#define SSCOPE_CM_SYNC 0x00000008 - -#define SSCOQM 0x506c0248 -#define SSCOQM_TID_MASK (0x3 << 21) -#define SSCOQM_TID_BY_WAY (0x2 << 21) -#define SSCOQM_TID_BY_INST_WAY (0x1 << 21) -#define SSCOQM_TID_BY_DATA_WAY (0x0 << 21) -#define SSCOQM_S_MASK (0x3 << 17) -#define SSCOQM_S_WAY (0x2 << 17) -#define SSCOQM_S_ALL (0x1 << 17) -#define SSCOQM_S_ADDRESS (0x0 << 17) -#define SSCOQM_CE (0x1 << 15) -#define SSCOQM_CW (0x1 << 14) -#define SSCOQM_CM_MASK (0x7) -#define SSCOQM_CM_DIRT_TOUCH (0x7) -#define SSCOQM_CM_ZERO_TOUCH (0x6) -#define SSCOQM_CM_NORM_TOUCH (0x5) -#define SSCOQM_CM_PREF_FETCH (0x4) -#define SSCOQM_CM_SSC_FETCH (0x3) -#define SSCOQM_CM_WB_INV (0x2) -#define SSCOQM_CM_WB (0x1) -#define SSCOQM_CM_INV (0x0) - -#define SSCOQAD 0x506c024c -#define SSCOQSZ 0x506c0250 -#define SSCOQWN 0x506c0258 - -#define SSCOPPQSEF 0x506c025c -#define SSCOPPQSEF_FE (0x1 << 1) -#define SSCOPPQSEF_OE (0x1 << 0) - -#define SSCOLPQS 0x506c0260 -#define SSCOLPQS_EF (0x1 << 2) -#define SSCOLPQS_EST (0x1 << 1) -#define SSCOLPQS_QST (0x1 << 0) - -#define SSCOQCE0 0x506c0270 - -#define SSC_LINE_SIZE 128 -#define SSC_RANGE_OP_MAX_SIZE (0x00400000 - (SSC_LINE_SIZE)) - -#endif /* ARCH_SSC_REGS_H */ diff --git a/arch/arm/mach-uniphier/arm64/arm-cci500.c b/arch/arm/mach-uniphier/arm64/arm-cci500.c index 607f96a58de..f18595dc131 100644 --- a/arch/arm/mach-uniphier/arm64/arm-cci500.c +++ b/arch/arm/mach-uniphier/arm64/arm-cci500.c @@ -1,13 +1,12 @@ /* * Initialization of ARM Corelink CCI-500 Cache Coherency Interconnect * - * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ -#include <common.h> -#include <mapmem.h> #include <linux/bitops.h> #include <linux/io.h> #include <linux/sizes.h> @@ -28,13 +27,13 @@ void cci500_init(unsigned int nr_slaves) void __iomem *base; u32 tmp; - base = map_sysmem(slave_base, SZ_4K); + base = ioremap(slave_base, SZ_4K); tmp = readl(base); tmp |= CCI500_SNOOP_CTRL_EN_DVM | CCI500_SNOOP_CTRL_EN_SNOOP; writel(tmp, base); - unmap_sysmem(base); + iounmap(base); slave_base += CCI500_SLAVE_OFFSET; } diff --git a/arch/arm/mach-uniphier/arm64/mem_map.c b/arch/arm/mach-uniphier/arm64/mem_map.c index 74ef91984ca..67bc4f1209b 100644 --- a/arch/arm/mach-uniphier/arm64/mem_map.c +++ b/arch/arm/mach-uniphier/arm64/mem_map.c @@ -10,14 +10,16 @@ static struct mm_region uniphier_mem_map[] = { { - .base = 0x00000000, + .virt = 0x00000000, + .phys = 0x00000000, .size = 0x80000000, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { - .base = 0x80000000, + .virt = 0x80000000, + .phys = 0x80000000, .size = 0xc0000000, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE diff --git a/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c b/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c index 5971ad256b8..4f08963118a 100644 --- a/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c +++ b/arch/arm/mach-uniphier/arm64/smp_kick_cpus.c @@ -1,11 +1,10 @@ /* - * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ -#include <common.h> -#include <mapmem.h> #include <linux/io.h> #include <linux/sizes.h> @@ -18,11 +17,11 @@ void uniphier_smp_kick_all_cpus(void) { void __iomem *rom_boot_rsv0; - rom_boot_rsv0 = map_sysmem(UNIPHIER_SMPCTRL_ROM_RSV0, SZ_8); + rom_boot_rsv0 = ioremap(UNIPHIER_SMPCTRL_ROM_RSV0, SZ_8); writeq((u64)uniphier_secondary_startup, rom_boot_rsv0); - unmap_sysmem(rom_boot_rsv0); + iounmap(rom_boot_rsv0); uniphier_smp_setup(); diff --git a/arch/arm/mach-uniphier/arm64/timer.c b/arch/arm/mach-uniphier/arm64/timer.c index 4beab9dca87..c10903ae58f 100644 --- a/arch/arm/mach-uniphier/arm64/timer.c +++ b/arch/arm/mach-uniphier/arm64/timer.c @@ -1,11 +1,10 @@ /* - * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ -#include <common.h> -#include <mapmem.h> #include <linux/bitops.h> #include <linux/io.h> #include <linux/sizes.h> @@ -21,7 +20,7 @@ int timer_init(void) void __iomem *base; u32 tmp; - base = map_sysmem(CNT_CONTROL_BASE, SZ_4K); + base = ioremap(CNT_CONTROL_BASE, SZ_4K); /* * Note: @@ -32,7 +31,7 @@ int timer_init(void) tmp |= CNTCR_EN; writel(tmp, base + CNTCR); - unmap_sysmem(base); + iounmap(base); return 0; } diff --git a/arch/arm/mach-uniphier/boards.c b/arch/arm/mach-uniphier/boards.c index ed308f3ecba..20093d8178a 100644 --- a/arch/arm/mach-uniphier/boards.c +++ b/arch/arm/mach-uniphier/boards.c @@ -1,5 +1,6 @@ /* - * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -38,7 +39,6 @@ static const struct uniphier_board_data uniphier_sld3_data = { static const struct uniphier_board_data uniphier_ld4_data = { .dram_freq = 1600, .dram_nr_ch = 2, - .dram_ddr3plus = true, .dram_ch[0] = { .base = 0x80000000, .size = 0x10000000, @@ -49,6 +49,7 @@ static const struct uniphier_board_data uniphier_ld4_data = { .size = 0x10000000, .width = 16, }, + .flags = UNIPHIER_BD_DDR3PLUS, }; #endif @@ -90,7 +91,6 @@ static const struct uniphier_board_data uniphier_pro4_2g_data = { static const struct uniphier_board_data uniphier_sld8_data = { .dram_freq = 1333, .dram_nr_ch = 2, - .dram_ddr3plus = true, .dram_ch[0] = { .base = 0x80000000, .size = 0x10000000, @@ -101,6 +101,7 @@ static const struct uniphier_board_data uniphier_sld8_data = { .size = 0x10000000, .width = 16, }, + .flags = UNIPHIER_BD_DDR3PLUS, }; #endif @@ -202,6 +203,22 @@ static const struct uniphier_board_data uniphier_ld20_data = { .width = 32, }, }; + +static const struct uniphier_board_data uniphier_ld21_data = { + .dram_freq = 1866, + .dram_nr_ch = 2, + .dram_ch[0] = { + .base = 0x80000000, + .size = 0x40000000, + .width = 32, + }, + .dram_ch[1] = { + .base = 0xc0000000, + .size = 0x40000000, + .width = 32, + }, + .flags = UNIPHIER_BD_PACKAGE_LD21, +}; #endif struct uniphier_board_id { @@ -237,6 +254,7 @@ static const struct uniphier_board_id uniphier_boards[] = { { "socionext,ph1-ld11", &uniphier_ld11_data, }, #endif #if defined(CONFIG_ARCH_UNIPHIER_LD20) + { "socionext,ph1-ld21", &uniphier_ld21_data, }, { "socionext,ph1-ld20", &uniphier_ld20_data, }, #endif }; diff --git a/arch/arm/mach-uniphier/clk/clk-pxs2.c b/arch/arm/mach-uniphier/clk/clk-pxs2.c index 76bf856c9e9..0d9240519c2 100644 --- a/arch/arm/mach-uniphier/clk/clk-pxs2.c +++ b/arch/arm/mach-uniphier/clk/clk-pxs2.c @@ -4,6 +4,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include <linux/bitops.h> #include <linux/io.h> #include "../init.h" @@ -32,12 +33,16 @@ void uniphier_pxs2_clk_init(void) tmp |= SC_RSTCTRL2_NRST_USB3B1; writel(tmp, SC_RSTCTRL2); readl(SC_RSTCTRL2); /* dummy read */ + + tmp = readl(SC_RSTCTRL6); + tmp |= 0x37; + writel(tmp, SC_RSTCTRL6); #endif /* provide clocks */ tmp = readl(SC_CLKCTRL); #ifdef CONFIG_USB_XHCI_UNIPHIER - tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 | + tmp |= BIT(20) | BIT(19) | SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 | SC_CLKCTRL_CEN_GIO; #endif #ifdef CONFIG_UNIPHIER_ETH diff --git a/arch/arm/mach-uniphier/debug.h b/arch/arm/mach-uniphier/debug.h new file mode 100644 index 00000000000..bc16f77b961 --- /dev/null +++ b/arch/arm/mach-uniphier/debug.h @@ -0,0 +1,68 @@ +/* + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DEBUG_H__ +#define __DEBUG_H__ + +#include <linux/io.h> +#include <linux/serial_reg.h> + +#define DEBUG_UART_BASE 0x54006800 +#define UART_SHIFT 2 + +#define UNIPHIER_UART_TX 0 +#define UNIPHIER_UART_LSR (5 * 4) + +/* All functions are inline so that they can be called from .secure section. */ + +#ifdef DEBUG +static inline void debug_putc(int c) +{ + void __iomem *base = (void __iomem *)DEBUG_UART_BASE; + + while (!(readl(base + UNIPHIER_UART_LSR) & UART_LSR_THRE)) + ; + + writel(c, base + UNIPHIER_UART_TX); +} + +static inline void debug_puts(const char *s) +{ + while (*s) { + if (*s == '\n') + debug_putc('\r'); + + debug_putc(*s++); + } +} + +static inline void debug_puth(unsigned long val) +{ + int i; + unsigned char c; + + for (i = 8; i--; ) { + c = ((val >> (i * 4)) & 0xf); + c += (c >= 10) ? 'a' - 10 : '0'; + debug_putc(c); + } +} +#else +static inline void debug_putc(int c) +{ +} + +static inline void debug_puts(const char *s) +{ +} + +static inline void debug_puth(unsigned long val) +{ +} +#endif + +#endif /* __DEBUG_H__ */ diff --git a/arch/arm/mach-uniphier/dram/cmd_ddrphy.c b/arch/arm/mach-uniphier/dram/cmd_ddrphy.c index 7a9f76caeb7..0a5a73d8eea 100644 --- a/arch/arm/mach-uniphier/dram/cmd_ddrphy.c +++ b/arch/arm/mach-uniphier/dram/cmd_ddrphy.c @@ -1,11 +1,12 @@ /* - * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2014 Panasonic Corporation + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> -#include <mapmem.h> #include <linux/io.h> #include <linux/sizes.h> @@ -51,7 +52,7 @@ static void dump_loop(unsigned long *base, int p, dx; for (p = 0; *base; base++, p++) { - phy = map_sysmem(*base, SZ_4K); + phy = ioremap(*base, SZ_4K); for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) { printf("PHY%dDX%d:", p, dx); @@ -59,7 +60,7 @@ static void dump_loop(unsigned long *base, printf("\n"); } - unmap_sysmem(phy); + iounmap(phy); } } @@ -172,7 +173,7 @@ static void reg_dump(unsigned long *base) printf("\n--- DDR PHY registers ---\n"); for (p = 0; *base; base++, p++) { - phy = map_sysmem(*base, SZ_4K); + phy = ioremap(*base, SZ_4K); printf("== PHY%d (base: %p) ==\n", p, phy); printf(" No: Name : Address : Data\n"); @@ -206,7 +207,7 @@ static void reg_dump(unsigned long *base) REG_DUMP(dx[1].gcr); REG_DUMP(dx[1].gtr); - unmap_sysmem(phy); + iounmap(phy); } } diff --git a/arch/arm/mach-uniphier/dram/umc-ld4.c b/arch/arm/mach-uniphier/dram/umc-ld4.c index fc75864a105..1ea6193f88f 100644 --- a/arch/arm/mach-uniphier/dram/umc-ld4.c +++ b/arch/arm/mach-uniphier/dram/umc-ld4.c @@ -1,5 +1,7 @@ /* - * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2011-2014 Panasonic Corporation + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -175,7 +177,7 @@ int uniphier_ld4_umc_init(const struct uniphier_board_data *bd) for (ch = 0; ch < DRAM_CH_NR; ch++) { ret = umc_ch_init(dc_base, ca_base, bd->dram_freq, bd->dram_ch[ch].size, - bd->dram_ddr3plus, ch); + !!(bd->flags & UNIPHIER_BD_DDR3PLUS), ch); if (ret) { pr_err("failed to initialize UMC ch%d\n", ch); return ret; diff --git a/arch/arm/mach-uniphier/dram/umc-pro4.c b/arch/arm/mach-uniphier/dram/umc-pro4.c index 853f561cb23..f6c2d7f145f 100644 --- a/arch/arm/mach-uniphier/dram/umc-pro4.c +++ b/arch/arm/mach-uniphier/dram/umc-pro4.c @@ -1,5 +1,7 @@ /* - * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2011-2014 Panasonic Corporation + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -170,7 +172,7 @@ int uniphier_pro4_umc_init(const struct uniphier_board_data *bd) ret = umc_ch_init(dc_base, ca_base, bd->dram_freq, bd->dram_ch[ch].size, bd->dram_ch[ch].width, - bd->dram_ddr3plus); + !!(bd->flags & UNIPHIER_BD_DDR3PLUS)); if (ret) { pr_err("failed to initialize UMC ch%d\n", ch); return ret; diff --git a/arch/arm/mach-uniphier/dram/umc-sld8.c b/arch/arm/mach-uniphier/dram/umc-sld8.c index e8317665836..61b1dc1a3a2 100644 --- a/arch/arm/mach-uniphier/dram/umc-sld8.c +++ b/arch/arm/mach-uniphier/dram/umc-sld8.c @@ -1,5 +1,7 @@ /* - * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2011-2014 Panasonic Corporation + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -178,7 +180,7 @@ int uniphier_sld8_umc_init(const struct uniphier_board_data *bd) for (ch = 0; ch < DRAM_CH_NR; ch++) { ret = umc_ch_init(dc_base, ca_base, bd->dram_freq, bd->dram_ch[ch].size, - bd->dram_ddr3plus, ch); + !!(bd->flags & UNIPHIER_BD_DDR3PLUS), ch); if (ret) { pr_err("failed to initialize UMC ch%d\n", ch); return ret; diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h index cba0bc9d374..db80074fc9e 100644 --- a/arch/arm/mach-uniphier/init.h +++ b/arch/arm/mach-uniphier/init.h @@ -1,5 +1,6 @@ /* - * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -20,8 +21,11 @@ struct uniphier_dram_ch { struct uniphier_board_data { unsigned int dram_freq; unsigned int dram_nr_ch; - bool dram_ddr3plus; struct uniphier_dram_ch dram_ch[UNIPHIER_MAX_NR_DRAM_CH]; + unsigned int flags; +#define UNIPHIER_BD_DDR3PLUS BIT(2) +#define UNIPHIER_BD_PACKAGE_LD21 1 +#define UNIPHIER_BD_PACKAGE_TYPE(f) ((f) & 0x3) }; const struct uniphier_board_data *uniphier_get_board_param(void); diff --git a/arch/arm/mach-uniphier/sbc/sbc-regs.h b/arch/arm/mach-uniphier/sbc/sbc-regs.h index a5dca74a55b..673fb75bcab 100644 --- a/arch/arm/mach-uniphier/sbc/sbc-regs.h +++ b/arch/arm/mach-uniphier/sbc/sbc-regs.h @@ -1,7 +1,8 @@ /* * UniPhier SBC (System Bus Controller) registers * - * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2011-2014 Panasonic Corporation + * Copyright (C) 2015-2016 Socionext Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -75,7 +76,6 @@ #define SBCTRL74 (SBCTRL_BASE + 0x170) #define PC0CTRL 0x598000c0 -#define ROM_BOOT_ROMRSV2 0x59801208 #ifndef __ASSEMBLY__ #include <linux/io.h> diff --git a/arch/arm/mach-uniphier/sc-regs.h b/arch/arm/mach-uniphier/sc-regs.h index a0955893ef7..ad58e10e23d 100644 --- a/arch/arm/mach-uniphier/sc-regs.h +++ b/arch/arm/mach-uniphier/sc-regs.h @@ -1,7 +1,9 @@ /* * UniPhier SC (System Control) block registers * - * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> + * Copyright (C) 2011-2015 Panasonic Corporation + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada <yamada.masahiro@socionext.com> * * SPDX-License-Identifier: GPL-2.0+ */ @@ -68,6 +70,10 @@ #define SC_RSTCTRL4_NRST_UMC31 (0x1 << 5) /* UMC ch1 */ #define SC_RSTCTRL4_NRST_UMC30 (0x1 << 4) /* UMC ch0 */ +#define SC_RSTCTRL5 (SC_BASE_ADDR | 0x2010) + +#define SC_RSTCTRL6 (SC_BASE_ADDR | 0x2014) + #define SC_CLKCTRL (SC_BASE_ADDR | 0x2104) #define SC_CLKCTRL_CEN_USB31 (0x1 << 17) /* USB3 #1 */ #define SC_CLKCTRL_CEN_USB30 (0x1 << 16) /* USB3 #0 */ diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig index db3c5792939..a98232097b2 100644 --- a/arch/arm/mach-zynq/Kconfig +++ b/arch/arm/mach-zynq/Kconfig @@ -17,4 +17,7 @@ config SYS_CONFIG_NAME Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header will be used for board configuration. +config SYS_MALLOC_F_LEN + default 0x600 + endif diff --git a/arch/m68k/cpu/mcf5227x/start.S b/arch/m68k/cpu/mcf5227x/start.S index 13c036f746e..b5d51bdee78 100644 --- a/arch/m68k/cpu/mcf5227x/start.S +++ b/arch/m68k/cpu/mcf5227x/start.S @@ -28,52 +28,37 @@ rte; #if defined(CONFIG_CF_SBF) -#define ASM_DRAMINIT (asm_dram_init - CONFIG_SYS_TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR) -#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - CONFIG_SYS_TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR) +#define ASM_DRAMINIT (asm_dram_init - CONFIG_SYS_TEXT_BASE + \ + CONFIG_SYS_INIT_RAM_ADDR) +#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - CONFIG_SYS_TEXT_BASE + \ + CONFIG_SYS_INIT_RAM_ADDR) #endif .text + /* - * Vector table. This is used for initial platform startup. - * These vectors are to catch any un-intended traps. + * Vector table. This is used for initial platform startup. + * These vectors are to catch any un-intended traps. */ _vectors: - #if defined(CONFIG_CF_SBF) -INITSP: .long 0 /* Initial SP */ -INITPC: .long ASM_DRAMINIT /* Initial PC */ +INITSP: .long 0 /* Initial SP */ +INITPC: .long ASM_DRAMINIT /* Initial PC */ #else -INITSP: .long 0 /* Initial SP */ -INITPC: .long _START /* Initial PC */ +INITSP: .long 0 /* Initial SP */ +INITPC: .long _START /* Initial PC */ #endif -vector02: .long _FAULT /* Access Error */ -vector03: .long _FAULT /* Address Error */ -vector04: .long _FAULT /* Illegal Instruction */ -vector05: .long _FAULT /* Reserved */ -vector06: .long _FAULT /* Reserved */ -vector07: .long _FAULT /* Reserved */ -vector08: .long _FAULT /* Privilege Violation */ -vector09: .long _FAULT /* Trace */ -vector0A: .long _FAULT /* Unimplemented A-Line */ -vector0B: .long _FAULT /* Unimplemented F-Line */ -vector0C: .long _FAULT /* Debug Interrupt */ -vector0D: .long _FAULT /* Reserved */ -vector0E: .long _FAULT /* Format Error */ -vector0F: .long _FAULT /* Unitialized Int. */ +vector02_0F: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT /* Reserved */ vector10_17: .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -vector18: .long _FAULT /* Spurious Interrupt */ -vector19: .long _FAULT /* Autovector Level 1 */ -vector1A: .long _FAULT /* Autovector Level 2 */ -vector1B: .long _FAULT /* Autovector Level 3 */ -vector1C: .long _FAULT /* Autovector Level 4 */ -vector1D: .long _FAULT /* Autovector Level 5 */ -vector1E: .long _FAULT /* Autovector Level 6 */ -vector1F: .long _FAULT /* Autovector Level 7 */ +vector18_1F: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT #if !defined(CONFIG_CF_SBF) /* TRAP #0 - #15 */ @@ -120,15 +105,16 @@ vector192_255: #if defined(CONFIG_CF_SBF) /* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */ asm_sbf_img_hdr: - .long 0x00000000 /* checksum, not yet implemented */ - .long 0x00020000 /* image length */ + .long 0x00000000 /* checksum, not yet implemented */ + .long 0x00020000 /* image length */ .long CONFIG_SYS_TEXT_BASE /* image to be relocated at */ asm_dram_init: move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0 - movec %d0, %RAMBAR1 /* init Rambar */ + movec %d0, %RAMBAR1 /* init Rambar */ + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp - clr.l %sp@- + clr.l %sp@- /* Must disable global address */ move.l #0xFC008000, %a1 @@ -142,7 +128,6 @@ asm_dram_init: * Dram Initialization * a1, a2, and d0 */ - /* mscr sdram */ move.l #0xFC0A4074, %a1 move.b #(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1) nop @@ -336,15 +321,15 @@ asm_dspi_rd_status: move.b (%a3), %d1 rts -#endif /* CONFIG_CF_SBF */ +#endif /* CONFIG_CF_SBF */ - .text +.text . = 0x400 - .globl _start +.globl _start _start: nop nop - move.w #0x2700,%sr /* Mask off Interrupt */ + move.w #0x2700,%sr /* Mask off Interrupt */ /* Set vector base register at the beginning of the Flash */ #if defined(CONFIG_CF_SBF) @@ -366,17 +351,17 @@ _start: movec %d0, %ACR1 /* initialize general use internal ram */ - move.l #0, %d0 - move.l #(ICACHE_STATUS), %a1 /* icache */ - move.l #(DCACHE_STATUS), %a2 /* icache */ - move.l %d0, (%a1) - move.l %d0, (%a2) + move.l #0, %d0 + move.l #(ICACHE_STATUS), %a1 /* icache */ + move.l #(DCACHE_STATUS), %a2 /* icache */ + move.l %d0, (%a1) + move.l %d0, (%a2) /* put relocation table address to a5 */ - move.l #__got_start, %a5 + move.l #__got_start, %a5 /* setup stack initially on top of internal static ram */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp /* * if configured, malloc_f arena will be reserved first, @@ -386,20 +371,23 @@ _start: bsr board_init_f_alloc_reserve /* update stack and frame-pointers */ - move.l %d0, %sp - move.l %sp, %fp + move.l %d0, %sp + move.l %sp, %fp /* initialize reserved area */ - move.l %d0, -(%sp) - bsr board_init_f_init_reserve + move.l %d0, -(%sp) + bsr board_init_f_init_reserve + + /* run low-level CPU init code (from flash) */ + bsr cpu_init_f + clr.l %sp@- - bsr cpu_init_f /* run low-level CPU init code (from flash) */ - clr.l %sp@- - bsr board_init_f /* run low-level board init code (from flash) */ + /* run low-level board init code (from flash) */ + bsr board_init_f /* board_init_f() does not return */ -/*------------------------------------------------------------------------------*/ +/******************************************************************************/ /* * void relocate_code (addr_sp, gd, addr_moni) @@ -412,23 +400,23 @@ _start: * r5 = length in bytes * r6 = cachelinesize */ - .globl relocate_code +.globl relocate_code relocate_code: - link.w %a6,#0 - move.l 8(%a6), %sp /* set new stack pointer */ + link.w %a6,#0 + move.l 8(%a6), %sp /* set new stack pointer */ - move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ - move.l 16(%a6), %a0 /* Save copy of Destination Address */ + move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ + move.l 16(%a6), %a0 /* Save copy of Destination Address */ - move.l #CONFIG_SYS_MONITOR_BASE, %a1 - move.l #__init_end, %a2 - move.l %a0, %a3 + move.l #CONFIG_SYS_MONITOR_BASE, %a1 + move.l #__init_end, %a2 + move.l %a0, %a3 /* copy the code to RAM */ 1: - move.l (%a1)+, (%a3)+ - cmp.l %a1,%a2 - bgt.s 1b + move.l (%a1)+, (%a3)+ + cmp.l %a1,%a2 + bgt.s 1b /* * We are done. Do not return, instead branch to second part of board @@ -458,7 +446,7 @@ clear_bss: */ move.l %a0, %a1 add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1 - move.l %a1,%a5 /* * fix got pointer register a5 */ + move.l %a1,%a5 /* fix got pointer register a5 */ move.l %a0, %a2 add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2 @@ -472,39 +460,40 @@ clear_bss: bne 7b /* calculate relative jump to board_init_r in ram */ - move.l %a0, %a1 - add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1 + move.l %a0, %a1 + add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1 /* set parameters for board_init_r */ - move.l %a0,-(%sp) /* dest_addr */ - move.l %d0,-(%sp) /* gd */ + move.l %a0,-(%sp) /* dest_addr */ + move.l %d0,-(%sp) /* gd */ jsr (%a1) -/*------------------------------------------------------------------------------*/ +/******************************************************************************/ + /* exception code */ - .globl _fault +.globl _fault _fault: - bra _fault - .globl _exc_handler + bra _fault +.globl _exc_handler _exc_handler: SAVE_ALL movel %sp,%sp@- - bsr exc_handler + bsr exc_handler addql #4,%sp RESTORE_ALL - .globl _int_handler +.globl _int_handler _int_handler: SAVE_ALL movel %sp,%sp@- - bsr int_handler + bsr int_handler addql #4,%sp RESTORE_ALL -/*------------------------------------------------------------------------------*/ +/******************************************************************************/ - .globl version_string +.globl version_string version_string: - .ascii U_BOOT_VERSION_STRING, "\0" - .align 4 +.ascii U_BOOT_VERSION_STRING, "\0" +.align 4 diff --git a/arch/m68k/cpu/mcf523x/start.S b/arch/m68k/cpu/mcf523x/start.S index 3aa4dd61faa..c4f608230df 100644 --- a/arch/m68k/cpu/mcf523x/start.S +++ b/arch/m68k/cpu/mcf523x/start.S @@ -28,41 +28,25 @@ rte; .text + /* - * Vector table. This is used for initial platform startup. - * These vectors are to catch any un-intended traps. + * Vector table. This is used for initial platform startup. + * These vectors are to catch any un-intended traps. */ _vectors: +INITSP: .long 0x00000000 /* Initial SP */ +INITPC: .long _START /* Initial PC */ -INITSP: .long 0x00000000 /* Initial SP */ -INITPC: .long _START /* Initial PC */ -vector02: .long _FAULT /* Access Error */ -vector03: .long _FAULT /* Address Error */ -vector04: .long _FAULT /* Illegal Instruction */ -vector05: .long _FAULT /* Reserved */ -vector06: .long _FAULT /* Reserved */ -vector07: .long _FAULT /* Reserved */ -vector08: .long _FAULT /* Privilege Violation */ -vector09: .long _FAULT /* Trace */ -vector0A: .long _FAULT /* Unimplemented A-Line */ -vector0B: .long _FAULT /* Unimplemented F-Line */ -vector0C: .long _FAULT /* Debug Interrupt */ -vector0D: .long _FAULT /* Reserved */ -vector0E: .long _FAULT /* Format Error */ -vector0F: .long _FAULT /* Unitialized Int. */ +vector02_0F: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT /* Reserved */ vector10_17: .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -vector18: .long _FAULT /* Spurious Interrupt */ -vector19: .long _FAULT /* Autovector Level 1 */ -vector1A: .long _FAULT /* Autovector Level 2 */ -vector1B: .long _FAULT /* Autovector Level 3 */ -vector1C: .long _FAULT /* Autovector Level 4 */ -vector1D: .long _FAULT /* Autovector Level 5 */ -vector1E: .long _FAULT /* Autovector Level 6 */ -vector1F: .long _FAULT /* Autovector Level 7 */ +vector18_1F: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT /* TRAP #0 - #15 */ vector20_2F: @@ -104,13 +88,13 @@ vector192_255: .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - .text +.text - .globl _start +.globl _start _start: nop nop - move.w #0x2700,%sr /* Mask off Interrupt */ + move.w #0x2700,%sr /* Mask off Interrupt */ /* Set vector base register at the beginning of the Flash */ move.l #CONFIG_SYS_FLASH_BASE, %d0 @@ -120,22 +104,22 @@ _start: movec %d0, %RAMBAR1 /* invalidate and disable cache */ - move.l #CF_CACR_CINV, %d0 /* Invalidate cache cmd */ - movec %d0, %CACR /* Invalidate cache */ + move.l #CF_CACR_CINV, %d0 /* Invalidate cache cmd */ + movec %d0, %CACR /* Invalidate cache */ nop move.l #0, %d0 movec %d0, %ACR0 movec %d0, %ACR1 /* initialize general use internal ram */ - move.l #0, %d0 - move.l #(ICACHE_STATUS), %a1 /* icache */ - move.l #(DCACHE_STATUS), %a2 /* icache */ - move.l %d0, (%a1) - move.l %d0, (%a2) + move.l #0, %d0 + move.l #(ICACHE_STATUS), %a1 /* icache */ + move.l #(DCACHE_STATUS), %a2 /* icache */ + move.l %d0, (%a1) + move.l %d0, (%a2) /* put relocation table address to a5 */ - move.l #__got_start, %a5 + move.l #__got_start, %a5 /* setup stack initially on top of internal static ram */ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp @@ -149,25 +133,26 @@ _start: jsr (%a1) /* update stack and frame-pointers */ - move.l %d0, %sp - move.l %sp, %fp + move.l %d0, %sp + move.l %sp, %fp /* initialize reserved area */ - move.l %d0, -(%sp) + move.l %d0, -(%sp) move.l #board_init_f_init_reserve, %a1 jsr (%a1) /* run low-level CPU init code (from flash) */ - move.l #cpu_init_f, %a1 - jsr (%a1) + move.l #cpu_init_f, %a1 + jsr (%a1) + /* run low-level board init code (from flash) */ - clr.l %sp@- - move.l #board_init_f, %a1 - jsr (%a1) + clr.l %sp@- + move.l #board_init_f, %a1 + jsr (%a1) /* board_init_f() does not return */ -/*------------------------------------------------------------------------------*/ +/******************************************************************************/ /* * void relocate_code (addr_sp, gd, addr_moni) @@ -180,23 +165,23 @@ _start: * r5 = length in bytes * r6 = cachelinesize */ - .globl relocate_code +.globl relocate_code relocate_code: - link.w %a6,#0 - move.l 8(%a6), %sp /* set new stack pointer */ + link.w %a6,#0 + move.l 8(%a6), %sp /* set new stack pointer */ - move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ - move.l 16(%a6), %a0 /* Save copy of Destination Address */ + move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ + move.l 16(%a6), %a0 /* Save copy of Destination Address */ - move.l #CONFIG_SYS_MONITOR_BASE, %a1 - move.l #__init_end, %a2 - move.l %a0, %a3 + move.l #CONFIG_SYS_MONITOR_BASE, %a1 + move.l #__init_end, %a2 + move.l %a0, %a3 /* copy the code to RAM */ 1: - move.l (%a1)+, (%a3)+ - cmp.l %a1,%a2 - bgt.s 1b + move.l (%a1)+, (%a3)+ + cmp.l %a1,%a2 + bgt.s 1b /* * We are done. Do not return, instead branch to second part of board @@ -240,39 +225,40 @@ clear_bss: bne 7b /* calculate relative jump to board_init_r in ram */ - move.l %a0, %a1 - add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1 + move.l %a0, %a1 + add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1 /* set parameters for board_init_r */ - move.l %a0,-(%sp) /* dest_addr */ - move.l %d0,-(%sp) /* gd */ + move.l %a0,-(%sp) /* dest_addr */ + move.l %d0,-(%sp) /* gd */ jsr (%a1) -/*------------------------------------------------------------------------------*/ +/******************************************************************************/ + /* exception code */ - .globl _fault +.globl _fault _fault: - bra _fault - .globl _exc_handler + bra _fault +.globl _exc_handler _exc_handler: SAVE_ALL movel %sp,%sp@- - bsr exc_handler + bsr exc_handler addql #4,%sp RESTORE_ALL - .globl _int_handler +.globl _int_handler _int_handler: SAVE_ALL movel %sp,%sp@- - bsr int_handler + bsr int_handler addql #4,%sp RESTORE_ALL -/*------------------------------------------------------------------------------*/ +/******************************************************************************/ - .globl version_string +.globl version_string version_string: - .ascii U_BOOT_VERSION_STRING, "\0" - .align 4 +.ascii U_BOOT_VERSION_STRING, "\0" +.align 4 diff --git a/arch/m68k/cpu/mcf52x2/start.S b/arch/m68k/cpu/mcf52x2/start.S index a048884f6ce..9837c41894c 100644 --- a/arch/m68k/cpu/mcf52x2/start.S +++ b/arch/m68k/cpu/mcf52x2/start.S @@ -34,12 +34,12 @@ #if !defined(CONFIG_MONITOR_IS_IN_RAM) .text + /* - * Vector table. This is used for initial platform startup. - * These vectors are to catch any un-intended traps. + * Vector table. This is used for initial platform startup. + * These vectors are to catch any un-intended traps. */ _vectors: - .long 0x00000000 /* Flash offset is 0 until we setup CS0 */ #if defined(CONFIG_M5282) && (CONFIG_SYS_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) .long _start - CONFIG_SYS_TEXT_BASE @@ -85,24 +85,24 @@ _vectors: #endif - .text - +.text #if defined(CONFIG_SYS_INT_FLASH_BASE) && \ (defined(CONFIG_M5282) || defined(CONFIG_M5281)) - #if (CONFIG_SYS_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) - .long 0x55AA55AA,0xAA55AA55 /* CFM Backdoorkey */ - .long 0xFFFFFFFF /* all sectors protected */ - .long 0x00000000 /* supervisor/User restriction */ - .long 0x00000000 /* programm/data space restriction */ - .long 0x00000000 /* Flash security */ - #endif +#if (CONFIG_SYS_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) +.long 0x55AA55AA,0xAA55AA55 /* CFM Backdoorkey */ +.long 0xFFFFFFFF /* all sectors protected */ +.long 0x00000000 /* supervisor/User restriction */ +.long 0x00000000 /* programm/data space restriction */ +.long 0x00000000 /* Flash security */ #endif - .globl _start +#endif + +.globl _start _start: nop nop - move.w #0x2700,%sr + move.w #0x2700,%sr #if defined(CONFIG_M5208) /* Initialize RAMBAR: locate SRAM and validate it */ @@ -111,22 +111,24 @@ _start: #endif #if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5253) - move.l #(CONFIG_SYS_MBAR + 1), %d0 /* set MBAR address + valid flag */ + /* set MBAR address + valid flag */ + move.l #(CONFIG_SYS_MBAR + 1), %d0 move.c %d0, %MBAR /*** The 5249 has MBAR2 as well ***/ #ifdef CONFIG_SYS_MBAR2 - move.l #(CONFIG_SYS_MBAR2 + 1), %d0 /* Get MBAR2 address */ - movec %d0, #0xc0e /* Set MBAR2 */ + /* Get MBAR2 address */ + move.l #(CONFIG_SYS_MBAR2 + 1), %d0 + /* Set MBAR2 */ + movec %d0, #0xc0e #endif - move.l #(CONFIG_SYS_INIT_RAM_ADDR + 1), %d0 movec %d0, %RAMBAR0 #endif /* CONFIG_M5272 || CONFIG_M5249 || CONFIG_M5253 */ #if defined(CONFIG_M5282) || defined(CONFIG_M5271) - /* Initialize IPSBAR */ - move.l #(CONFIG_SYS_MBAR + 1), %d0 /* set IPSBAR address + valid flag */ + /* set MBAR address + valid flag */ + move.l #(CONFIG_SYS_MBAR + 1), %d0 move.l %d0, 0x40000000 /* Initialize RAMBAR1: locate SRAM and validate it */ @@ -135,22 +137,24 @@ _start: #if defined(CONFIG_M5282) #if (CONFIG_SYS_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) - /* Setup code in SRAM to initialize FLASHBAR, if start from internal Flash */ - - move.l #(_flashbar_setup-CONFIG_SYS_INT_FLASH_BASE), %a0 - move.l #(_flashbar_setup_end-CONFIG_SYS_INT_FLASH_BASE), %a1 - move.l #(CONFIG_SYS_INIT_RAM_ADDR), %a2 + /* + * Setup code in SRAM to initialize FLASHBAR, + * if start from internal Flash + */ + move.l #(_flashbar_setup-CONFIG_SYS_INT_FLASH_BASE), %a0 + move.l #(_flashbar_setup_end-CONFIG_SYS_INT_FLASH_BASE), %a1 + move.l #(CONFIG_SYS_INIT_RAM_ADDR), %a2 _copy_flash: - move.l (%a0)+, (%a2)+ - cmp.l %a0, %a1 - bgt.s _copy_flash - jmp CONFIG_SYS_INIT_RAM_ADDR + move.l (%a0)+, (%a2)+ + cmp.l %a0, %a1 + bgt.s _copy_flash + jmp CONFIG_SYS_INIT_RAM_ADDR _flashbar_setup: /* Initialize FLASHBAR: locate internal Flash and validate it */ move.l #(CONFIG_SYS_INT_FLASH_BASE + CONFIG_SYS_INT_FLASH_ENABLE), %d0 movec %d0, %FLASHBAR - jmp _after_flashbar_copy.L /* Force jump to absolute address */ + jmp _after_flashbar_copy.L /* Force jump to absolute address */ _flashbar_setup_end: nop _after_flashbar_copy: @@ -162,7 +166,8 @@ _after_flashbar_copy: #endif #endif - /* if we come from a pre-loader we have no exception table and + /* + * if we come from a pre-loader we have no exception table and * therefore no VBR to set */ #if !defined(CONFIG_MONITOR_IS_IN_RAM) @@ -175,8 +180,8 @@ _after_flashbar_copy: #endif #ifdef CONFIG_M5275 - /* Initialize IPSBAR */ - move.l #(CONFIG_SYS_MBAR + 1), %d0 /* set IPSBAR address + valid flag */ + /* set MBAR address + valid flag */ + move.l #(CONFIG_SYS_MBAR + 1), %d0 move.l %d0, 0x40000000 /* movec %d0, %MBAR */ @@ -186,17 +191,17 @@ _after_flashbar_copy: #endif /* initialize general use internal ram */ - move.l #0, %d0 - move.l #(ICACHE_STATUS), %a1 /* icache */ - move.l #(DCACHE_STATUS), %a2 /* icache */ - move.l %d0, (%a1) - move.l %d0, (%a2) + move.l #0, %d0 + move.l #(ICACHE_STATUS), %a1 /* icache */ + move.l #(DCACHE_STATUS), %a2 /* icache */ + move.l %d0, (%a1) + move.l %d0, (%a2) /* put relocation table address to a5 */ - move.l #__got_start, %a5 + move.l #__got_start, %a5 /* setup stack initially on top of internal static ram */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp /* * if configured, malloc_f arena will be reserved first, @@ -204,28 +209,29 @@ _after_flashbar_copy: */ move.l %sp, -(%sp) move.l #board_init_f_alloc_reserve, %a1 - jsr (%a1) + jsr (%a1) /* update stack and frame-pointers */ - move.l %d0, %sp - move.l %sp, %fp + move.l %d0, %sp + move.l %sp, %fp /* initialize reserved area */ - move.l %d0, -(%sp) + move.l %d0, -(%sp) move.l #board_init_f_init_reserve, %a1 - jsr (%a1) + jsr (%a1) /* run low-level CPU init code (from flash) */ - move.l #cpu_init_f, %a1 - jsr (%a1) + move.l #cpu_init_f, %a1 + jsr (%a1) + /* run low-level board init code (from flash) */ - clr.l %sp@- - move.l #board_init_f, %a1 - jsr (%a1) + clr.l %sp@- + move.l #board_init_f, %a1 + jsr (%a1) /* board_init_f() does not return */ -/*------------------------------------------------------------------------------*/ +/******************************************************************************/ /* * void relocate_code (addr_sp, gd, addr_moni) @@ -238,22 +244,22 @@ _after_flashbar_copy: * r5 = length in bytes * r6 = cachelinesize */ - .globl relocate_code +.globl relocate_code relocate_code: - link.w %a6,#0 - move.l 8(%a6), %sp /* set new stack pointer */ + link.w %a6,#0 + move.l 8(%a6), %sp /* set new stack pointer */ - move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ - move.l 16(%a6), %a0 /* Save copy of Destination Address */ + move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ + move.l 16(%a6), %a0 /* Save copy of Destination Address */ - move.l #CONFIG_SYS_MONITOR_BASE, %a1 - move.l #__init_end, %a2 - move.l %a0, %a3 + move.l #CONFIG_SYS_MONITOR_BASE, %a1 + move.l #__init_end, %a2 + move.l %a0, %a3 /* copy the code to RAM */ 1: - move.l (%a1)+, (%a3)+ - cmp.l %a1,%a2 - bgt.s 1b + move.l (%a1)+, (%a3)+ + cmp.l %a1,%a2 + bgt.s 1b /* * We are done. Do not return, instead branch to second part of board @@ -283,7 +289,7 @@ clear_bss: */ move.l %a0, %a1 add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1 - move.l %a1,%a5 /* * fix got pointer register a5 */ + move.l %a1,%a5 /* fix got pointer register a5 */ move.l %a0, %a2 add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2 @@ -297,43 +303,44 @@ clear_bss: bne 7b /* calculate relative jump to board_init_r in ram */ - move.l %a0, %a1 - add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1 + move.l %a0, %a1 + add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1 /* set parameters for board_init_r */ - move.l %a0,-(%sp) /* dest_addr */ - move.l %d0,-(%sp) /* gd */ + move.l %a0,-(%sp) /* dest_addr */ + move.l %d0,-(%sp) /* gd */ #if defined(DEBUG) && (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE) && \ defined(CONFIG_SYS_HALT_BEFOR_RAM_JUMP) halt #endif jsr (%a1) -/*------------------------------------------------------------------------------*/ +/******************************************************************************/ + /* exception code */ - .globl _fault +.globl _fault _fault: - bra _fault + bra _fault - .globl _exc_handler +.globl _exc_handler _exc_handler: SAVE_ALL movel %sp,%sp@- - bsr exc_handler + bsr exc_handler addql #4,%sp RESTORE_ALL - .globl _int_handler +.globl _int_handler _int_handler: SAVE_ALL movel %sp,%sp@- - bsr int_handler + bsr int_handler addql #4,%sp RESTORE_ALL -/*------------------------------------------------------------------------------*/ +/******************************************************************************/ - .globl version_string +.globl version_string version_string: - .ascii U_BOOT_VERSION_STRING, "\0" - .align 4 +.ascii U_BOOT_VERSION_STRING, "\0" +.align 4 diff --git a/arch/m68k/cpu/mcf530x/start.S b/arch/m68k/cpu/mcf530x/start.S index ca8bb320630..da41c9af34b 100644 --- a/arch/m68k/cpu/mcf530x/start.S +++ b/arch/m68k/cpu/mcf530x/start.S @@ -36,12 +36,12 @@ #if !defined(CONFIG_MONITOR_IS_IN_RAM) .text + /* - * Vector table. This is used for initial platform startup. - * These vectors are to catch any un-intended traps. + * Vector table. This is used for initial platform startup. + * These vectors are to catch any un-intended traps. */ _vectors: - /* Flash offset is 0 until we setup CS0 */ .long 0x00000000 #if defined(CONFIG_M5307) && \ @@ -89,12 +89,13 @@ _vectors: #endif - .text - .globl _start +.text + +.globl _start _start: nop nop - move.w #0x2700,%sr + move.w #0x2700,%sr /* set MBAR address + valid flag */ move.l #(CONFIG_SYS_MBAR + 1), %d0 @@ -104,11 +105,11 @@ _start: move.c %d0, %RAMBAR /* DS 4.8.2 (Cache Organization) invalidate and disable cache */ - move.l #CF_CACR_CINVA, %d0 - movec %d0, %CACR - move.l #0, %d0 - movec %d0, %ACR0 - movec %d0, %ACR1 + move.l #CF_CACR_CINVA, %d0 + movec %d0, %CACR + move.l #0, %d0 + movec %d0, %ACR0 + movec %d0, %ACR1 /* * if we come from a pre-loader we have no exception table and @@ -127,10 +128,10 @@ _start: move.l %d0, (%a2) /* put relocation table address to a5 */ - move.l #__got_start, %a5 + move.l #__got_start, %a5 /* setup stack initially on top of internal static ram */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp /* * if configured, malloc_f arena will be reserved first, @@ -140,23 +141,23 @@ _start: bsr board_init_f_alloc_reserve /* update stack and frame-pointers */ - move.l %d0, %sp - move.l %sp, %fp + move.l %d0, %sp + move.l %sp, %fp /* initialize reserved area */ - move.l %d0, -(%sp) - bsr board_init_f_init_reserve + move.l %d0, -(%sp) + bsr board_init_f_init_reserve /* run low-level CPU init code (from flash) */ - bsr cpu_init_f + bsr cpu_init_f /* run low-level board init code (from flash) */ - clr.l %sp@- - bsr board_init_f + clr.l %sp@- + bsr board_init_f /* board_init_f() does not return */ -/*--------------------------------------------------------------------------*/ +/******************************************************************************/ /* * void relocate_code (addr_sp, gd, addr_moni) @@ -165,7 +166,7 @@ _start: * after relocating the monitor code. * */ - .globl relocate_code +.globl relocate_code relocate_code: link.w %a6,#0 move.l 8(%a6), %sp /* set new stack pointer */ @@ -209,7 +210,8 @@ clear_bss: */ move.l %a0, %a1 add.l #(__got_start - CONFIG_SYS_MONITOR_BASE), %a1 - /* * fix got pointer register a5 */ + + /* fix got pointer register a5 */ move.l %a1,%a5 move.l %a0, %a2 @@ -236,33 +238,34 @@ clear_bss: #endif jsr (%a1) -/*--------------------------------------------------------------------------*/ +/******************************************************************************/ + /* exception code */ - .globl _fault +.globl _fault _fault: bra _fault - .globl _exc_handler +.globl _exc_handler _exc_handler: SAVE_ALL movel %sp,%sp@- - bsr exc_handler + bsr exc_handler addql #4,%sp RESTORE_ALL - .globl _int_handler +.globl _int_handler _int_handler: SAVE_ALL movel %sp,%sp@- - bsr int_handler + bsr int_handler addql #4,%sp RESTORE_ALL -/*--------------------------------------------------------------------------*/ +/******************************************************************************/ - .globl version_string +.globl version_string version_string: - .ascii U_BOOT_VERSION - .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" - .ascii CONFIG_IDENT_STRING, "\0" - .align 4 +.ascii U_BOOT_VERSION +.ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" +.ascii CONFIG_IDENT_STRING, "\0" +.align 4 diff --git a/arch/m68k/cpu/mcf532x/start.S b/arch/m68k/cpu/mcf532x/start.S index f25bc541be7..302fca52451 100644 --- a/arch/m68k/cpu/mcf532x/start.S +++ b/arch/m68k/cpu/mcf532x/start.S @@ -31,42 +31,27 @@ rte; #if !defined(CONFIG_MONITOR_IS_IN_RAM) + .text + /* - * Vector table. This is used for initial platform startup. - * These vectors are to catch any un-intended traps. + * Vector table. This is used for initial platform startup. + * These vectors are to catch any un-intended traps. */ _vectors: +INITSP: .long 0x00000000 /* Initial SP */ +INITPC: .long _START /* Initial PC */ -INITSP: .long 0x00000000 /* Initial SP */ -INITPC: .long _START /* Initial PC */ -vector02: .long _FAULT /* Access Error */ -vector03: .long _FAULT /* Address Error */ -vector04: .long _FAULT /* Illegal Instruction */ -vector05: .long _FAULT /* Reserved */ -vector06: .long _FAULT /* Reserved */ -vector07: .long _FAULT /* Reserved */ -vector08: .long _FAULT /* Privilege Violation */ -vector09: .long _FAULT /* Trace */ -vector0A: .long _FAULT /* Unimplemented A-Line */ -vector0B: .long _FAULT /* Unimplemented F-Line */ -vector0C: .long _FAULT /* Debug Interrupt */ -vector0D: .long _FAULT /* Reserved */ -vector0E: .long _FAULT /* Format Error */ -vector0F: .long _FAULT /* Unitialized Int. */ +vector02_0F: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT /* Reserved */ vector10_17: .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -vector18: .long _FAULT /* Spurious Interrupt */ -vector19: .long _FAULT /* Autovector Level 1 */ -vector1A: .long _FAULT /* Autovector Level 2 */ -vector1B: .long _FAULT /* Autovector Level 3 */ -vector1C: .long _FAULT /* Autovector Level 4 */ -vector1D: .long _FAULT /* Autovector Level 5 */ -vector1E: .long _FAULT /* Autovector Level 6 */ -vector1F: .long _FAULT /* Autovector Level 7 */ +vector18_1F: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT /* TRAP #0 - #15 */ vector20_2F: @@ -109,13 +94,13 @@ vector192_255: .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT #endif /* !defined(CONFIG_MONITOR_IS_IN_RAM) */ - .text +.text - .globl _start +.globl _start _start: nop nop - move.w #0x2700,%sr /* Mask off Interrupt */ + move.w #0x2700,%sr /* Mask off Interrupt */ #if !defined(CONFIG_MONITOR_IS_IN_RAM) /* Set vector base register at the beginning of the Flash */ @@ -142,14 +127,14 @@ _start: #endif /* initialize general use internal ram */ - move.l #0, %d0 - move.l #(ICACHE_STATUS), %a1 /* icache */ - move.l #(DCACHE_STATUS), %a2 /* icache */ - move.l %d0, (%a1) - move.l %d0, (%a2) + move.l #0, %d0 + move.l #(ICACHE_STATUS), %a1 /* icache */ + move.l #(DCACHE_STATUS), %a2 /* icache */ + move.l %d0, (%a1) + move.l %d0, (%a2) /* put relocation table address to a5 */ - move.l #__got_start, %a5 + move.l #__got_start, %a5 /* setup stack initially on top of internal static ram */ move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp @@ -167,13 +152,14 @@ _start: move.l %sp, %fp /* initialize reserved area */ - move.l %d0, -(%sp) + move.l %d0, -(%sp) move.l #board_init_f_init_reserve, %a1 jsr (%a1) /* run low-level CPU init code (from flash) */ - move.l #cpu_init_f, %a1 - jsr (%a1) + move.l #cpu_init_f, %a1 + jsr (%a1) + /* run low-level board init code (from flash) */ clr.l %sp@- move.l #board_init_f, %a1 @@ -181,7 +167,7 @@ _start: /* board_init_f() does not return */ -/*------------------------------------------------------------------------------*/ +/******************************************************************************/ /* * void relocate_code (addr_sp, gd, addr_moni) @@ -194,23 +180,23 @@ _start: * r5 = length in bytes * r6 = cachelinesize */ - .globl relocate_code +.globl relocate_code relocate_code: - link.w %a6,#0 - move.l 8(%a6), %sp /* set new stack pointer */ + link.w %a6,#0 + move.l 8(%a6), %sp /* set new stack pointer */ - move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ - move.l 16(%a6), %a0 /* Save copy of Destination Address */ + move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ + move.l 16(%a6), %a0 /* Save copy of Destination Address */ - move.l #CONFIG_SYS_MONITOR_BASE, %a1 - move.l #__init_end, %a2 - move.l %a0, %a3 + move.l #CONFIG_SYS_MONITOR_BASE, %a1 + move.l #__init_end, %a2 + move.l %a0, %a3 /* copy the code to RAM */ 1: - move.l (%a1)+, (%a3)+ - cmp.l %a1,%a2 - bgt.s 1b + move.l (%a1)+, (%a3)+ + cmp.l %a1,%a2 + bgt.s 1b /* * We are done. Do not return, instead branch to second part of board @@ -240,7 +226,7 @@ clear_bss: */ move.l %a0, %a1 add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1 - move.l %a1,%a5 /* * fix got pointer register a5 */ + move.l %a1,%a5 /* fix got pointer register a5 */ move.l %a0, %a2 add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2 @@ -254,38 +240,40 @@ clear_bss: bne 7b /* calculate relative jump to board_init_r in ram */ - move.l %a0, %a1 - add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1 + move.l %a0, %a1 + add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1 /* set parameters for board_init_r */ - move.l %a0,-(%sp) /* dest_addr */ - move.l %d0,-(%sp) /* gd */ + move.l %a0,-(%sp) /* dest_addr */ + move.l %d0,-(%sp) /* gd */ jsr (%a1) -/*------------------------------------------------------------------------------*/ +/******************************************************************************/ + /* exception code */ - .globl _fault +.globl _fault _fault: bra _fault - .globl _exc_handler +.globl _exc_handler _exc_handler: SAVE_ALL movel %sp,%sp@- - bsr exc_handler + bsr exc_handler addql #4,%sp RESTORE_ALL - .globl _int_handler +.globl _int_handler _int_handler: SAVE_ALL movel %sp,%sp@- - bsr int_handler + bsr int_handler addql #4,%sp RESTORE_ALL -/*------------------------------------------------------------------------------*/ - .globl version_string +/******************************************************************************/ + +.globl version_string version_string: - .ascii U_BOOT_VERSION_STRING, "\0" - .align 4 +.ascii U_BOOT_VERSION_STRING, "\0" +.align 4 diff --git a/arch/m68k/cpu/mcf5445x/start.S b/arch/m68k/cpu/mcf5445x/start.S index ba38678be3c..bc48ca0f5b0 100644 --- a/arch/m68k/cpu/mcf5445x/start.S +++ b/arch/m68k/cpu/mcf5445x/start.S @@ -33,62 +33,47 @@ rte; #if defined(CONFIG_SERIAL_BOOT) -#define ASM_DRAMINIT (asm_dram_init - CONFIG_SYS_TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR) +#define ASM_DRAMINIT (asm_dram_init - CONFIG_SYS_TEXT_BASE + \ + CONFIG_SYS_INIT_RAM_ADDR) #define ASM_DRAMINIT_N (asm_dram_init - CONFIG_SYS_TEXT_BASE) -#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - CONFIG_SYS_TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR) +#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - CONFIG_SYS_TEXT_BASE + \ + CONFIG_SYS_INIT_RAM_ADDR) #endif .text /* - * Vector table. This is used for initial platform startup. - * These vectors are to catch any un-intended traps. + * Vector table. This is used for initial platform startup. + * These vectors are to catch any un-intended traps. */ _vectors: #if defined(CONFIG_SERIAL_BOOT) -INITSP: .long 0 /* Initial SP */ +INITSP: .long 0 /* Initial SP */ #ifdef CONFIG_CF_SBF -INITPC: .long ASM_DRAMINIT /* Initial PC */ +INITPC: .long ASM_DRAMINIT /* Initial PC */ #endif #ifdef CONFIG_SYS_NAND_BOOT -INITPC: .long ASM_DRAMINIT_N /* Initial PC */ +INITPC: .long ASM_DRAMINIT_N /* Initial PC */ #endif #else -INITSP: .long 0 /* Initial SP */ -INITPC: .long _START /* Initial PC */ +INITSP: .long 0 /* Initial SP */ +INITPC: .long _START /* Initial PC */ #endif -vector02: .long _FAULT /* Access Error */ -vector03: .long _FAULT /* Address Error */ -vector04: .long _FAULT /* Illegal Instruction */ -vector05: .long _FAULT /* Reserved */ -vector06: .long _FAULT /* Reserved */ -vector07: .long _FAULT /* Reserved */ -vector08: .long _FAULT /* Privilege Violation */ -vector09: .long _FAULT /* Trace */ -vector0A: .long _FAULT /* Unimplemented A-Line */ -vector0B: .long _FAULT /* Unimplemented F-Line */ -vector0C: .long _FAULT /* Debug Interrupt */ -vector0D: .long _FAULT /* Reserved */ -vector0E: .long _FAULT /* Format Error */ -vector0F: .long _FAULT /* Unitialized Int. */ +vector02_0F: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT /* Reserved */ vector10_17: .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -vector18: .long _FAULT /* Spurious Interrupt */ -vector19: .long _FAULT /* Autovector Level 1 */ -vector1A: .long _FAULT /* Autovector Level 2 */ -vector1B: .long _FAULT /* Autovector Level 3 */ -vector1C: .long _FAULT /* Autovector Level 4 */ -vector1D: .long _FAULT /* Autovector Level 5 */ -vector1E: .long _FAULT /* Autovector Level 6 */ -vector1F: .long _FAULT /* Autovector Level 7 */ +vector18_1F: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT #if !defined(CONFIG_SERIAL_BOOT) @@ -136,12 +121,12 @@ vector192_255: #if defined(CONFIG_SERIAL_BOOT) /* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */ asm_sbf_img_hdr: - .long 0x00000000 /* checksum, not yet implemented */ - .long 0x00040000 /* image length */ + .long 0x00000000 /* checksum, not yet implemented */ + .long 0x00040000 /* image length */ .long CONFIG_SYS_TEXT_BASE /* image to be relocated at */ asm_dram_init: - move.w #0x2700,%sr /* Mask off Interrupt */ + move.w #0x2700,%sr /* Mask off Interrupt */ #ifdef CONFIG_SYS_NAND_BOOT /* for assembly stack */ @@ -149,7 +134,7 @@ asm_dram_init: movec %d0, %RAMBAR1 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp - clr.l %sp@- + clr.l %sp@- #endif #ifdef CONFIG_CF_SBF @@ -160,11 +145,11 @@ asm_dram_init: movec %d0, %RAMBAR1 /* initialize general use internal ram */ - move.l #0, %d0 - move.l #(ICACHE_STATUS), %a1 /* icache */ - move.l #(DCACHE_STATUS), %a2 /* dcache */ - move.l %d0, (%a1) - move.l %d0, (%a2) + move.l #0, %d0 + move.l #(ICACHE_STATUS), %a1 /* icache */ + move.l #(DCACHE_STATUS), %a2 /* dcache */ + move.l %d0, (%a1) + move.l %d0, (%a2) /* invalidate and disable cache */ move.l #(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0 @@ -176,7 +161,7 @@ asm_dram_init: movec %d0, %ACR3 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp - clr.l %sp@- + clr.l %sp@- /* Must disable global address */ move.l #0xFC008000, %a1 @@ -185,7 +170,7 @@ asm_dram_init: move.l #(CONFIG_SYS_CS0_CTRL), (%a1) move.l #0xFC008004, %a1 move.l #(CONFIG_SYS_CS0_MASK), (%a1) -#endif /* CONFIG_CF_SBF */ +#endif /* CONFIG_CF_SBF */ #ifdef CONFIG_MCF5441x /* TC: enable all peripherals, @@ -193,9 +178,9 @@ asm_dram_init: move.l #0xFC04002D, %a1 #if defined(CONFIG_CF_SBF) - move.b #23, (%a1) /* dspi */ + move.b #23, (%a1) /* dspi */ #endif - move.b #46, (%a1) /* DDR */ + move.b #46, (%a1) /* DDR */ /* slew settings */ move.l #0xEC094060, %a1 @@ -365,7 +350,7 @@ dramsz_loop: move.l #2000, %d1 jsr asm_delay -#endif /* CONFIG_MCF5445x */ +#endif /* CONFIG_MCF5445x */ #ifdef CONFIG_CF_SBF /* @@ -484,7 +469,7 @@ asm_dspi_rd_status: move.b (%a3), %d1 rts -#endif /* CONFIG_CF_SBF */ +#endif /* CONFIG_CF_SBF */ #ifdef CONFIG_SYS_NAND_BOOT /* copy 4 boot pages to dram as soon as possible */ @@ -509,13 +494,13 @@ asm_nand_init: move.l %d1, (%a1) /* initialize general use internal ram */ - move.l #0, %d0 - move.l #(CACR_STATUS), %a1 /* CACR */ - move.l #(ICACHE_STATUS), %a2 /* icache */ - move.l #(DCACHE_STATUS), %a3 /* dcache */ - move.l %d0, (%a1) - move.l %d0, (%a2) - move.l %d0, (%a3) + move.l #0, %d0 + move.l #(CACR_STATUS), %a1 /* CACR */ + move.l #(ICACHE_STATUS), %a2 /* icache */ + move.l #(DCACHE_STATUS), %a3 /* dcache */ + move.l %d0, (%a1) + move.l %d0, (%a2) + move.l %d0, (%a3) /* invalidate and disable cache */ move.l #0x01004100, %d0 /* Invalidate cache cmd */ @@ -571,7 +556,7 @@ asm_nand_init: move.l #4, %d2 /* start at 4 */ move.l #0xFC0FFF04, %a0 /* cmd2 */ move.l #0xFC0FFF0C, %a1 /* rar */ - move.l #(CONFIG_SYS_TEXT_BASE + 0xF80), %a2 /* dst */ + move.l #(CONFIG_SYS_TEXT_BASE + 0xF80), %a2 asm_nand_read: move.l #0x11000000, %d0 /* rar */ @@ -621,14 +606,14 @@ asm_delay: rts #endif /* CONFIG_CF_SBF || CONFIG_NAND_U_BOOT */ - .text +.text . = 0x400 - .globl _start +.globl _start _start: #if !defined(CONFIG_SERIAL_BOOT) nop nop - move.w #0x2700,%sr /* Mask off Interrupt */ + move.w #0x2700,%sr /* Mask off Interrupt */ /* Set vector base register at the beginning of the Flash */ move.l #CONFIG_SYS_FLASH_BASE, %d0 @@ -638,11 +623,11 @@ _start: movec %d0, %RAMBAR1 /* initialize general use internal ram */ - move.l #0, %d0 - move.l #(ICACHE_STATUS), %a1 /* icache */ - move.l #(DCACHE_STATUS), %a2 /* dcache */ - move.l %d0, (%a1) - move.l %d0, (%a2) + move.l #0, %d0 + move.l #(ICACHE_STATUS), %a1 /* icache */ + move.l #(DCACHE_STATUS), %a2 /* dcache */ + move.l %d0, (%a1) + move.l %d0, (%a2) /* invalidate and disable cache */ move.l #(CONFIG_SYS_ICACHE_INV + CONFIG_SYS_DCACHE_INV), %d0 @@ -658,10 +643,10 @@ _start: #endif /* put relocation table address to a5 */ - move.l #__got_start, %a5 + move.l #__got_start, %a5 /* setup stack initially on top of internal static ram */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp /* * if configured, malloc_f arena will be reserved first, @@ -672,25 +657,26 @@ _start: jsr (%a1) /* update stack and frame-pointers */ - move.l %d0, %sp - move.l %sp, %fp + move.l %d0, %sp + move.l %sp, %fp /* initialize reserved area */ - move.l %d0, -(%sp) + move.l %d0, -(%sp) move.l #board_init_f_init_reserve, %a1 jsr (%a1) /* run low-level CPU init code (from flash) */ - move.l #cpu_init_f, %a1 - jsr (%a1) + move.l #cpu_init_f, %a1 + jsr (%a1) + /* run low-level board init code (from flash) */ clr.l %sp@- - move.l #board_init_f, %a1 - jsr (%a1) + move.l #board_init_f, %a1 + jsr (%a1) /* board_init_f() does not return */ -/*------------------------------------------------------------------------------*/ +/******************************************************************************/ /* * void relocate_code (addr_sp, gd, addr_moni) @@ -703,23 +689,23 @@ _start: * r5 = length in bytes * r6 = cachelinesize */ - .globl relocate_code +.globl relocate_code relocate_code: - link.w %a6,#0 - move.l 8(%a6), %sp /* set new stack pointer */ + link.w %a6,#0 + move.l 8(%a6), %sp /* set new stack pointer */ - move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ - move.l 16(%a6), %a0 /* Save copy of Destination Address */ + move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ + move.l 16(%a6), %a0 /* Save copy of Destination Address */ - move.l #CONFIG_SYS_MONITOR_BASE, %a1 - move.l #__init_end, %a2 - move.l %a0, %a3 + move.l #CONFIG_SYS_MONITOR_BASE, %a1 + move.l #__init_end, %a2 + move.l %a0, %a3 /* copy the code to RAM */ 1: - move.l (%a1)+, (%a3)+ - cmp.l %a1,%a2 - bgt.s 1b + move.l (%a1)+, (%a3)+ + cmp.l %a1,%a2 + bgt.s 1b /* * We are done. Do not return, instead branch to second part of board @@ -749,7 +735,7 @@ clear_bss: */ move.l %a0, %a1 add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1 - move.l %a1,%a5 /* * fix got pointer register a5 */ + move.l %a1,%a5 /* fix got pointer register a5 */ move.l %a0, %a2 add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2 @@ -763,39 +749,40 @@ clear_bss: bne 7b /* calculate relative jump to board_init_r in ram */ - move.l %a0, %a1 - add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1 + move.l %a0, %a1 + add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1 /* set parameters for board_init_r */ - move.l %a0,-(%sp) /* dest_addr */ - move.l %d0,-(%sp) /* gd */ + move.l %a0,-(%sp) /* dest_addr */ + move.l %d0,-(%sp) /* gd */ jsr (%a1) -/*------------------------------------------------------------------------------*/ +/******************************************************************************/ + /* exception code */ - .globl _fault +.globl _fault _fault: - bra _fault - .globl _exc_handler + bra _fault +.globl _exc_handler _exc_handler: SAVE_ALL movel %sp,%sp@- - bsr exc_handler + bsr exc_handler addql #4,%sp RESTORE_ALL - .globl _int_handler +.globl _int_handler _int_handler: SAVE_ALL movel %sp,%sp@- - bsr int_handler + bsr int_handler addql #4,%sp RESTORE_ALL -/*------------------------------------------------------------------------------*/ +/******************************************************************************/ - .globl version_string +.globl version_string version_string: - .ascii U_BOOT_VERSION_STRING, "\0" - .align 4 +.ascii U_BOOT_VERSION_STRING, "\0" +.align 4 diff --git a/arch/m68k/cpu/mcf547x_8x/start.S b/arch/m68k/cpu/mcf547x_8x/start.S index 9a87a0da230..fecf253d4bb 100644 --- a/arch/m68k/cpu/mcf547x_8x/start.S +++ b/arch/m68k/cpu/mcf547x_8x/start.S @@ -28,41 +28,25 @@ rte; .text + /* - * Vector table. This is used for initial platform startup. - * These vectors are to catch any un-intended traps. + * Vector table. This is used for initial platform startup. + * These vectors are to catch any un-intended traps. */ _vectors: +INITSP: .long 0x00000000 /* Initial SP */ +INITPC: .long _START /* Initial PC */ -INITSP: .long 0x00000000 /* Initial SP */ -INITPC: .long _START /* Initial PC */ -vector02: .long _FAULT /* Access Error */ -vector03: .long _FAULT /* Address Error */ -vector04: .long _FAULT /* Illegal Instruction */ -vector05: .long _FAULT /* Reserved */ -vector06: .long _FAULT /* Reserved */ -vector07: .long _FAULT /* Reserved */ -vector08: .long _FAULT /* Privilege Violation */ -vector09: .long _FAULT /* Trace */ -vector0A: .long _FAULT /* Unimplemented A-Line */ -vector0B: .long _FAULT /* Unimplemented F-Line */ -vector0C: .long _FAULT /* Debug Interrupt */ -vector0D: .long _FAULT /* Reserved */ -vector0E: .long _FAULT /* Format Error */ -vector0F: .long _FAULT /* Unitialized Int. */ +vector02_0F: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT /* Reserved */ vector10_17: .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT -vector18: .long _FAULT /* Spurious Interrupt */ -vector19: .long _FAULT /* Autovector Level 1 */ -vector1A: .long _FAULT /* Autovector Level 2 */ -vector1B: .long _FAULT /* Autovector Level 3 */ -vector1C: .long _FAULT /* Autovector Level 4 */ -vector1D: .long _FAULT /* Autovector Level 5 */ -vector1E: .long _FAULT /* Autovector Level 6 */ -vector1F: .long _FAULT /* Autovector Level 7 */ +vector18_1F: +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT /* TRAP #0 - #15 */ vector20_2F: @@ -104,13 +88,13 @@ vector192_255: .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT - .text +.text - .globl _start +.globl _start _start: nop nop - move.w #0x2700,%sr /* Mask off Interrupt */ + move.w #0x2700,%sr /* Mask off Interrupt */ /* Set vector base register at the beginning of the Flash */ move.l #CONFIG_SYS_FLASH_BASE, %d0 @@ -122,7 +106,7 @@ _start: move.l #(CONFIG_SYS_INIT_RAM1_ADDR + CONFIG_SYS_INIT_RAM1_CTRL), %d0 movec %d0, %RAMBAR1 - move.l #CONFIG_SYS_MBAR, %d0 /* set MBAR address */ + move.l #CONFIG_SYS_MBAR, %d0 /* set MBAR address */ move.c %d0, %MBAR /* invalidate and disable cache */ @@ -135,17 +119,17 @@ _start: movec %d0, %ACR3 /* initialize general use internal ram */ - move.l #0, %d0 - move.l #(ICACHE_STATUS), %a1 /* icache */ - move.l #(DCACHE_STATUS), %a2 /* icache */ - move.l %d0, (%a1) - move.l %d0, (%a2) + move.l #0, %d0 + move.l #(ICACHE_STATUS), %a1 /* icache */ + move.l #(DCACHE_STATUS), %a2 /* icache */ + move.l %d0, (%a1) + move.l %d0, (%a2) /* put relocation table address to a5 */ - move.l #__got_start, %a5 + move.l #__got_start, %a5 /* setup stack initially on top of internal static ram */ - move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp /* * if configured, malloc_f arena will be reserved first, @@ -159,16 +143,19 @@ _start: move.l %sp, %fp /* initialize reserved area */ - move.l %d0, -(%sp) - bsr board_init_f_init_reserve + move.l %d0, -(%sp) + bsr board_init_f_init_reserve + + /* run low-level CPU init code (from flash) */ + jbsr cpu_init_f - jbsr cpu_init_f /* run low-level CPU init code (from flash) */ - clr.l %sp@- - jbsr board_init_f /* run low-level board init code (from flash) */ + /* run low-level board init code (from flash) */ + clr.l %sp@- + jbsr board_init_f /* board_init_f() does not return */ -/*------------------------------------------------------------------------------*/ +/******************************************************************************/ /* * void relocate_code (addr_sp, gd, addr_moni) @@ -181,23 +168,23 @@ _start: * r5 = length in bytes * r6 = cachelinesize */ - .globl relocate_code +.globl relocate_code relocate_code: - link.w %a6,#0 - move.l 8(%a6), %sp /* set new stack pointer */ + link.w %a6,#0 + move.l 8(%a6), %sp /* set new stack pointer */ - move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ - move.l 16(%a6), %a0 /* Save copy of Destination Address */ + move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ + move.l 16(%a6), %a0 /* Save copy of Destination Address */ - move.l #CONFIG_SYS_MONITOR_BASE, %a1 - move.l #__init_end, %a2 - move.l %a0, %a3 + move.l #CONFIG_SYS_MONITOR_BASE, %a1 + move.l #__init_end, %a2 + move.l %a0, %a3 /* copy the code to RAM */ 1: - move.l (%a1)+, (%a3)+ - cmp.l %a1,%a2 - bgt.s 1b + move.l (%a1)+, (%a3)+ + cmp.l %a1,%a2 + bgt.s 1b /* * We are done. Do not return, instead branch to second part of board @@ -227,7 +214,7 @@ clear_bss: */ move.l %a0, %a1 add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1 - move.l %a1,%a5 /* * fix got pointer register a5 */ + move.l %a1,%a5 /* fix got pointer register a5 */ move.l %a0, %a2 add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2 @@ -241,39 +228,40 @@ clear_bss: bne 7b /* calculate relative jump to board_init_r in ram */ - move.l %a0, %a1 - add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1 + move.l %a0, %a1 + add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1 /* set parameters for board_init_r */ - move.l %a0,-(%sp) /* dest_addr */ - move.l %d0,-(%sp) /* gd */ + move.l %a0,-(%sp) /* dest_addr */ + move.l %d0,-(%sp) /* gd */ jsr (%a1) -/*------------------------------------------------------------------------------*/ +/******************************************************************************/ + /* exception code */ - .globl _fault +.globl _fault _fault: - bra _fault - .globl _exc_handler + bra _fault +.globl _exc_handler _exc_handler: SAVE_ALL movel %sp,%sp@- - bsr exc_handler + bsr exc_handler addql #4,%sp RESTORE_ALL - .globl _int_handler +.globl _int_handler _int_handler: SAVE_ALL movel %sp,%sp@- - bsr int_handler + bsr int_handler addql #4,%sp RESTORE_ALL -/*------------------------------------------------------------------------------*/ +/******************************************************************************/ - .globl version_string +.globl version_string version_string: - .ascii U_BOOT_VERSION_STRING, "\0" - .align 4 +.ascii U_BOOT_VERSION_STRING, "\0" +.align 4 diff --git a/arch/m68k/include/asm/fec.h b/arch/m68k/include/asm/fec.h index 6856aac82df..2799293e9a9 100644 --- a/arch/m68k/include/asm/fec.h +++ b/arch/m68k/include/asm/fec.h @@ -15,6 +15,8 @@ #ifndef fec_h #define fec_h +#include <phy.h> + /* Buffer descriptors used FEC. */ typedef struct cpm_buf_desc { @@ -341,10 +343,9 @@ int fecpin_setclear(struct eth_device *dev, int setclear); void __mii_init(void); uint mii_send(uint mii_cmd); int mii_discover_phy(struct eth_device *dev); -int mcffec_miiphy_read(const char *devname, unsigned char addr, - unsigned char reg, unsigned short *value); -int mcffec_miiphy_write(const char *devname, unsigned char addr, - unsigned char reg, unsigned short value); +int mcffec_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg); +int mcffec_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg, + u16 value); #endif #endif /* fec_h */ diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c index aa0475a4954..0c6a4ab3b32 100644 --- a/arch/mips/lib/bootm.c +++ b/arch/mips/lib/bootm.c @@ -253,6 +253,7 @@ static int boot_reloc_fdt(bootm_headers_t *images) #endif } +#ifdef CONFIG_ARCH_FIXUP_FDT int arch_fixup_fdt(void *blob) { #if CONFIG_IS_ENABLED(MIPS_BOOT_FDT) && CONFIG_IS_ENABLED(OF_LIBFDT) @@ -264,6 +265,7 @@ int arch_fixup_fdt(void *blob) return 0; #endif } +#endif static int boot_setup_fdt(bootm_headers_t *images) { diff --git a/arch/mips/mach-au1x00/au1x00_eth.c b/arch/mips/mach-au1x00/au1x00_eth.c index 921686081ff..67f49535158 100644 --- a/arch/mips/mach-au1x00/au1x00_eth.c +++ b/arch/mips/mach-au1x00/au1x00_eth.c @@ -73,9 +73,9 @@ mac_fifo_t mac_fifo[NO_OF_FIFOS]; #define MAX_WAIT 1000 #if defined(CONFIG_CMD_MII) -int au1x00_miiphy_read(const char *devname, unsigned char addr, - unsigned char reg, unsigned short * value) +int au1x00_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg) { + unsigned short value = 0; volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL); volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA); u32 mii_control; @@ -102,12 +102,12 @@ int au1x00_miiphy_read(const char *devname, unsigned char addr, return -1; } } - *value = *mii_data_reg; - return 0; + value = *mii_data_reg; + return value; } -int au1x00_miiphy_write(const char *devname, unsigned char addr, - unsigned char reg, unsigned short value) +int au1x00_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg, + u16 value) { volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL); volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA); @@ -290,8 +290,17 @@ int au1x00_enet_initialize(bd_t *bis){ eth_register(dev); #if defined(CONFIG_CMD_MII) - miiphy_register(dev->name, - au1x00_miiphy_read, au1x00_miiphy_write); + int retval; + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; + strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); + mdiodev->read = au1x00_miiphy_read; + mdiodev->write = au1x00_miiphy_write; + + retval = mdio_register(mdiodev); + if (retval < 0) + return retval; #endif return 1; diff --git a/arch/nds32/include/asm/io.h b/arch/nds32/include/asm/io.h index 04708e93594..b2c4d0ef8cf 100644 --- a/arch/nds32/include/asm/io.h +++ b/arch/nds32/include/asm/io.h @@ -344,40 +344,6 @@ static inline void writesl(unsigned int *addr, const void * data, int longlen) #define insl_p(port, to, len) insl(port, to, len) /* - * ioremap and friends. - * - * ioremap takes a PCI memory address, as specified in - * linux/Documentation/IO-mapping.txt. If you want a - * physical address, use __ioremap instead. - */ -extern void *__ioremap(unsigned long offset, size_t size, unsigned long flags); -extern void __iounmap(void *addr); - -/* - * Generic ioremap support. - * - * Define: - * iomem_valid_addr(off,size) - * iomem_to_phys(off) - */ -#ifdef iomem_valid_addr -#define __arch_ioremap(off, sz, nocache) \ -({ \ - unsigned long _off = (off), _size = (sz); \ - void *_ret = (void *)0; \ - if (iomem_valid_addr(_off, _size)) \ - _ret = __ioremap(iomem_to_phys(_off), _size, 0); \ - _ret; \ -}) - -#define __arch_iounmap __iounmap -#endif - -#define ioremap(off, sz) __arch_ioremap((off), (sz), 0) -#define ioremap_nocache(off, sz) __arch_ioremap((off), (sz), 1) -#define iounmap(_addr) __arch_iounmap(_addr) - -/* * DMA-consistent mapping functions. These allocate/free a region of * uncached, unwrite-buffered mapped memory space for use with DMA * devices. This is the "generic" version. The PCI specific version diff --git a/arch/powerpc/cpu/mpc8260/ether_fcc.c b/arch/powerpc/cpu/mpc8260/ether_fcc.c index a11ad1e9d06..072eb76150b 100644 --- a/arch/powerpc/cpu/mpc8260/ether_fcc.c +++ b/arch/powerpc/cpu/mpc8260/ether_fcc.c @@ -379,8 +379,17 @@ int fec_initialize(bd_t *bis) #if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) \ && defined(CONFIG_BITBANGMII) - miiphy_register(dev->name, - bb_miiphy_read, bb_miiphy_write); + int retval; + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; + strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); + mdiodev->read = bb_miiphy_read; + mdiodev->write = bb_miiphy_write; + + retval = mdio_register(mdiodev); + if (retval < 0) + return retval; #endif } diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 0b89157fcaa..9bcbda006d1 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -17,6 +17,7 @@ config TARGET_SOCRATES config TARGET_B4860QDS bool "Support B4860QDS" select SUPPORT_SPL + select PHYS_64BIT config TARGET_BSC9131RDB bool "Support BSC9131RDB" @@ -30,18 +31,23 @@ config TARGET_C29XPCIE bool "Support C29XPCIE" select SUPPORT_SPL select SUPPORT_TPL + select PHYS_64BIT config TARGET_P3041DS bool "Support P3041DS" + select PHYS_64BIT config TARGET_P4080DS bool "Support P4080DS" + select PHYS_64BIT config TARGET_P5020DS bool "Support P5020DS" + select PHYS_64BIT config TARGET_P5040DS bool "Support P5040DS" + select PHYS_64BIT config TARGET_MPC8536DS bool "Support MPC8536DS" @@ -96,46 +102,57 @@ config TARGET_P1_TWR config TARGET_P2041RDB bool "Support P2041RDB" + select PHYS_64BIT config TARGET_QEMU_PPCE500 bool "Support qemu-ppce500" + select PHYS_64BIT config TARGET_T102XQDS bool "Support T102xQDS" select SUPPORT_SPL + select PHYS_64BIT config TARGET_T102XRDB bool "Support T102xRDB" select SUPPORT_SPL + select PHYS_64BIT config TARGET_T1040QDS bool "Support T1040QDS" + select PHYS_64BIT config TARGET_T104XRDB bool "Support T104xRDB" select SUPPORT_SPL + select PHYS_64BIT config TARGET_T208XQDS bool "Support T208xQDS" select SUPPORT_SPL + select PHYS_64BIT config TARGET_T208XRDB bool "Support T208xRDB" select SUPPORT_SPL + select PHYS_64BIT config TARGET_T4240QDS bool "Support T4240QDS" select SUPPORT_SPL + select PHYS_64BIT config TARGET_T4240RDB bool "Support T4240RDB" select SUPPORT_SPL + select PHYS_64BIT config TARGET_CONTROLCENTERD bool "Support controlcenterd" config TARGET_KMP204X bool "Support kmp204x" + select PHYS_64BIT config TARGET_XPEDITE520X bool "Support xpedite520x" @@ -151,6 +168,7 @@ config TARGET_UCP1020 config TARGET_CYRUS bool "Support Varisys Cyrus" + select PHYS_64BIT endchoice diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 61f5639e0de..ace42799f7a 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -439,7 +439,7 @@ ulong cpu_init_f(void) #ifdef CONFIG_SYS_DCSRBAR_PHYS ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif -#if defined(CONFIG_SECURE_BOOT) +#if defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SYS_RAMBOOT) struct law_entry law; #endif #ifdef CONFIG_MPC8548 @@ -459,7 +459,7 @@ ulong cpu_init_f(void) disable_tlb(14); disable_tlb(15); -#if defined(CONFIG_SECURE_BOOT) +#if defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SYS_RAMBOOT) /* Disable the LAW created for NOR flash by the PBI commands */ law = find_law(CONFIG_SYS_PBI_FLASH_BASE); if (law.index != -1) diff --git a/arch/powerpc/cpu/mpc85xx/ether_fcc.c b/arch/powerpc/cpu/mpc85xx/ether_fcc.c index 51f1beef519..7708f059ca2 100644 --- a/arch/powerpc/cpu/mpc85xx/ether_fcc.c +++ b/arch/powerpc/cpu/mpc85xx/ether_fcc.c @@ -441,8 +441,17 @@ int fec_initialize(bd_t *bis) #if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) \ && defined(CONFIG_BITBANGMII) - miiphy_register(dev->name, - bb_miiphy_read, bb_miiphy_write); + int retval; + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; + strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); + mdiodev->read = bb_miiphy_read; + mdiodev->write = bb_miiphy_write; + + retval = mdio_register(mdiodev); + if (retval < 0) + return retval; #endif } diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c index 88c8e65930e..0addf8493c2 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.c +++ b/arch/powerpc/cpu/mpc85xx/mp.c @@ -30,7 +30,7 @@ u32 get_my_id() */ int hold_cores_in_reset(int verbose) { - /* Default to no, overriden by 'y', 'yes', 'Y', 'Yes', or '1' */ + /* Default to no, overridden by 'y', 'yes', 'Y', 'Yes', or '1' */ if (getenv_yesno("mp_holdoff") == 1) { if (verbose) { puts("Secondary cores are being held in reset.\n"); diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 4c512258685..c3e12349f7f 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -1069,17 +1069,23 @@ create_init_ram_area: #elif !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) /* create a temp mapping in AS = 1 for Flash mapping * created by PBL for ISBC code - */ + */ create_tlb1_entry 15, \ 1, BOOKE_PAGESZ_1M, \ CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \ CONFIG_SYS_PBI_FLASH_WINDOW & 0xfff00000, MAS3_SX|MAS3_SW|MAS3_SR, \ 0, r6 -#elif defined(CONFIG_RAMBOOT_PBL) && defined(CONFIG_SECURE_BOOT) +/* + * For Targets without CONFIG_SPL like P3, P5 + * and for targets with CONFIG_SPL like T1, T2, T4, only for + * u-boot-spl i.e. CONFIG_SPL_BUILD + */ +#elif defined(CONFIG_RAMBOOT_PBL) && defined(CONFIG_SECURE_BOOT) && \ + (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) /* create a temp mapping in AS = 1 for mapping CONFIG_SYS_MONITOR_BASE * to L3 Address configured by PBL for ISBC code - */ + */ create_tlb1_entry 15, \ 1, BOOKE_PAGESZ_1M, \ CONFIG_SYS_MONITOR_BASE & 0xfff00000, MAS2_I|MAS2_G, \ diff --git a/arch/powerpc/cpu/mpc86xx/config.mk b/arch/powerpc/cpu/mpc86xx/config.mk index 69a0b96eadb..aefb0f1fb4f 100644 --- a/arch/powerpc/cpu/mpc86xx/config.mk +++ b/arch/powerpc/cpu/mpc86xx/config.mk @@ -5,4 +5,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -PLATFORM_CPPFLAGS += -mstring -maltivec -mabi=altivec -msoft-float +PLATFORM_CPPFLAGS += -mcpu=7400 -mstring -maltivec -mabi=altivec -msoft-float diff --git a/arch/powerpc/cpu/mpc8xx/fec.c b/arch/powerpc/cpu/mpc8xx/fec.c index f1ae3584660..0940906b1d4 100644 --- a/arch/powerpc/cpu/mpc8xx/fec.c +++ b/arch/powerpc/cpu/mpc8xx/fec.c @@ -6,10 +6,12 @@ */ #include <common.h> -#include <malloc.h> +#include <command.h> #include <commproc.h> +#include <malloc.h> #include <net.h> -#include <command.h> + +#include <phy.h> DECLARE_GLOBAL_DATA_PTR; @@ -47,10 +49,9 @@ DECLARE_GLOBAL_DATA_PTR; static int mii_discover_phy(struct eth_device *dev); #endif -int fec8xx_miiphy_read(const char *devname, unsigned char addr, - unsigned char reg, unsigned short *value); -int fec8xx_miiphy_write(const char *devname, unsigned char addr, - unsigned char reg, unsigned short value); +int fec8xx_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg); +int fec8xx_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg, + u16 value); static struct ether_fcc_info_s { @@ -170,8 +171,17 @@ int fec_initialize(bd_t *bis) eth_register(dev); #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - miiphy_register(dev->name, - fec8xx_miiphy_read, fec8xx_miiphy_write); + int retval; + struct mii_dev *mdiodev = mdio_alloc(); + if (!mdiodev) + return -ENOMEM; + strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN); + mdiodev->read = fec8xx_miiphy_read; + mdiodev->write = fec8xx_miiphy_write; + + retval = mdio_register(mdiodev); + if (retval < 0) + return retval; #endif } return 1; @@ -894,9 +904,9 @@ void mii_init (void) * Otherwise they hang in mii_send() !!! Sorry! *****************************************************************************/ -int fec8xx_miiphy_read(const char *devname, unsigned char addr, - unsigned char reg, unsigned short *value) +int fec8xx_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg) { + unsigned short value = 0; short rdreg; /* register working value */ #ifdef MII_DEBUG @@ -904,15 +914,15 @@ int fec8xx_miiphy_read(const char *devname, unsigned char addr, #endif rdreg = mii_send(mk_mii_read(addr, reg)); - *value = rdreg; + value = rdreg; #ifdef MII_DEBUG - printf ("0x%04x\n", *value); + printf ("0x%04x\n", value); #endif - return 0; + return value; } -int fec8xx_miiphy_write(const char *devname, unsigned char addr, - unsigned char reg, unsigned short value) +int fec8xx_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg, + u16 value) { #ifdef MII_DEBUG printf ("miiphy_write(0x%x) @ 0x%x = ", reg, addr); diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c index 9421f1ebf6f..ede8e662104 100644 --- a/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c +++ b/arch/powerpc/cpu/mpc8xxx/fsl_pamu.c @@ -239,15 +239,23 @@ int pamu_init(void) spaact_size = sizeof(struct paace) * NUM_SPAACT_ENTRIES; /* Allocate space for Primary PAACT Table */ +#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_PPAACT_ADDR)) + ppaact = (void *)CONFIG_SPL_PPAACT_ADDR; +#else ppaact = memalign(PAMU_TABLE_ALIGNMENT, ppaact_size); if (!ppaact) return -1; +#endif memset(ppaact, 0, ppaact_size); /* Allocate space for Secondary PAACT Table */ +#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SPAACT_ADDR)) + sec = (void *)CONFIG_SPL_SPAACT_ADDR; +#else sec = memalign(PAMU_TABLE_ALIGNMENT, spaact_size); if (!sec) return -1; +#endif memset(sec, 0, spaact_size); ppaact_phys = virt_to_phys((void *)ppaact); diff --git a/arch/powerpc/cpu/mpc8xxx/pamu_table.c b/arch/powerpc/cpu/mpc8xxx/pamu_table.c index 26c5ea4fd7a..a8e6f517771 100644 --- a/arch/powerpc/cpu/mpc8xxx/pamu_table.c +++ b/arch/powerpc/cpu/mpc8xxx/pamu_table.c @@ -28,6 +28,14 @@ void construct_pamu_addr_table(struct pamu_addr_tbl *tbl, int *num_entries) i++; #endif +#if (defined(CONFIG_SPL_BUILD) && (CONFIG_SYS_INIT_L3_VADDR)) + tbl->start_addr[i] = + (uint64_t)virt_to_phys((void *)CONFIG_SYS_INIT_L3_VADDR); + tbl->size[i] = 256 * 1024; /* 256K CPC flash */ + tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1; + + i++; +#endif debug("PAMU address\t\t\tsize\n"); for (j = 0; j < i ; j++) debug("%llx \t\t\t%llx\n", tbl->start_addr[j], tbl->size[j]); diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig index 36af1b9419b..92a330dc635 100644 --- a/arch/powerpc/cpu/ppc4xx/Kconfig +++ b/arch/powerpc/cpu/ppc4xx/Kconfig @@ -30,6 +30,7 @@ config TARGET_CANYONLANDS config TARGET_KATMAI bool "Support katmai" + select PHYS_64BIT config TARGET_KILAUEA bool "Support kilauea" diff --git a/arch/powerpc/cpu/ppc4xx/miiphy.c b/arch/powerpc/cpu/ppc4xx/miiphy.c index 10147de0897..f0fc098059e 100644 --- a/arch/powerpc/cpu/ppc4xx/miiphy.c +++ b/arch/powerpc/cpu/ppc4xx/miiphy.c @@ -318,8 +318,7 @@ static int emac_miiphy_command(u8 addr, u8 reg, int cmd, u16 value) return 0; } -int emac4xx_miiphy_read (const char *devname, unsigned char addr, unsigned char reg, - unsigned short *value) +int emac4xx_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg) { unsigned long sta_reg; unsigned long emac_reg; @@ -330,17 +329,15 @@ int emac4xx_miiphy_read (const char *devname, unsigned char addr, unsigned char return -1; sta_reg = in_be32((void *)EMAC0_STACR + emac_reg); - *value = sta_reg >> 16; - - return 0; + return sta_reg >> 16; } /***********************************************************/ /* write a phy reg and return the value with a rc */ /***********************************************************/ -int emac4xx_miiphy_write (const char *devname, unsigned char addr, unsigned char reg, - unsigned short value) +int emac4xx_miiphy_write(struct mii_dev *bus, int addr, int devad, int reg, + u16 value) { return emac_miiphy_command(addr, reg, EMAC_STACR_WRITE, value); } diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S index b432b18c74d..7633abc1a16 100644 --- a/arch/powerpc/cpu/ppc4xx/start.S +++ b/arch/powerpc/cpu/ppc4xx/start.S @@ -144,7 +144,7 @@ #endif /* - * Unless otherwise overriden, enable two 128MB cachable instruction regions + * Unless otherwise overridden, enable two 128MB cachable instruction regions * at CONFIG_SYS_SDRAM_BASE and another 128MB cacheable instruction region covering * NOR flash at CONFIG_SYS_FLASH_BASE. Disable all cacheable data regions. */ @@ -743,8 +743,16 @@ _start: /*----------------------------------------------------------------*/ /* Setup the stack in internal SRAM */ /*----------------------------------------------------------------*/ - lis r1,CONFIG_SYS_INIT_RAM_ADDR@h - ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l + lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@h + ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@l + /* + * Reserve space for globals and store address for initialization + * with board_init_f_init_reserve() in r14 + */ + mr r3, r1 + bl board_init_f_alloc_reserve + mr r1, r3 + mr r14, r3 li r0,0 stwu r0,-4(r1) stwu r0,-4(r1) /* Terminate call chain */ @@ -760,13 +768,9 @@ _start: #endif bl cpu_init_f /* run low-level CPU init code (from Flash) */ - mr r3, r1 - bl board_init_f_alloc_reserve - mr r1, r3 + /* address for globals was stored in r14 */ + mr r3, r14 bl board_init_f_init_reserve - li r0,0 - stwu r0, -4(r1) - stwu r0, -4(r1) li r3, 0 bl board_init_f /* NOTREACHED - board_init_f() does not return */ @@ -831,8 +835,16 @@ _start: * for their primordial stack, setup stack here directly after the * SDRAM is initialized in ext_bus_cntlr_init. */ - lis r1, CONFIG_SYS_INIT_RAM_ADDR@h - ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in SDRAM */ + lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@h + ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@l + /* + * Reserve space for globals and store address for initialization + * with board_init_f_init_reserve() in r14 + */ + mr r3, r1 + bl board_init_f_alloc_reserve + mr r1, r3 + mr r14, r3 li r0, 0 /* Make room for stack frame header and */ stwu r0, -4(r1) /* clear final stack frame so that */ @@ -972,8 +984,16 @@ _start: * Load the initial stack pointer and data area and convert the size, * in bytes, to the number of words to initialize to a known value. */ - lis r1, CONFIG_SYS_INIT_RAM_ADDR@h - ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l + lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@h + ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@l + /* + * Reserve space for globals and store address for initialization + * with board_init_f_init_reserve() in r14 + */ + mr r3, r1 + bl board_init_f_alloc_reserve + mr r1, r3 + mr r14, r3 lis r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@h ori r4, r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@l @@ -993,6 +1013,7 @@ _start: * Make room for stack frame header and clear final stack frame so * that stack backtraces terminate cleanly. */ + li r0, 0 stwu r0, -4(r1) stwu r0, -4(r1) @@ -1011,10 +1032,16 @@ _start: /* * Stack in OCM. */ - - /* Set up Stack at top of OCM */ - lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@h - ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@l + lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@h + ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)@l + /* + * Reserve space for globals and store address for initialization + * with board_init_f_init_reserve() in r14 + */ + mr r3, r1 + bl board_init_f_alloc_reserve + mr r1, r3 + mr r14, r3 /* Set up a zeroized stack frame so that backtrace works right */ li r0, 0 @@ -1035,12 +1062,9 @@ _start: GET_GOT /* initialize GOT access */ bl cpu_init_f /* run low-level CPU init code (from Flash) */ - mr r3, r1 - bl board_init_f_alloc_reserve - mr r1, r3 + /* address for globals was stored in r14 */ + mr r3, r14 bl board_init_f_init_reserve - stwu r0, -4(r1) - stwu r0, -4(r1) li r3, 0 bl board_init_f /* run first part of init code (from Flash) */ /* NOTREACHED - board_init_f() does not return */ diff --git a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h index 41b6677bba3..76faa22c8b4 100644 --- a/arch/powerpc/include/asm/arch-mpc85xx/gpio.h +++ b/arch/powerpc/include/asm/arch-mpc85xx/gpio.h @@ -18,4 +18,10 @@ #include <asm/mpc85xx_gpio.h> #endif +struct mpc85xx_gpio_plat { + ulong addr; + unsigned long size; + uint ngpios; +}; + #endif diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 826f9c960e9..2e937f0364b 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -35,7 +35,9 @@ defined(CONFIG_T104xD4RDB) || \ defined(CONFIG_PPC_T1023) || \ defined(CONFIG_PPC_T1024) +#ifndef CONFIG_SYS_RAMBOOT #define CONFIG_SYS_CPC_REINIT_F +#endif #define CONFIG_KEY_REVOCATION #undef CONFIG_SYS_INIT_L3_ADDR #define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 @@ -43,7 +45,13 @@ #if defined(CONFIG_RAMBOOT_PBL) #undef CONFIG_SYS_INIT_L3_ADDR -#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 +#ifdef CONFIG_SYS_INIT_L3_VADDR +#define CONFIG_SYS_INIT_L3_ADDR \ + (CONFIG_SYS_INIT_L3_VADDR & ~0xFFF00000) | \ + 0xbff00000 +#else +#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000 +#endif #endif #if defined(CONFIG_C29XPCIE) @@ -72,6 +80,32 @@ #ifdef CONFIG_CHAIN_OF_TRUST +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_DM 1 +#define CONFIG_SPL_CRYPTO_SUPPORT +#define CONFIG_SPL_HASH_SUPPORT +#define CONFIG_SPL_RSA +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +/* + * PPAACT and SPAACT table for PAMU must be placed on DDR after DDR init + * due to space crunch on CPC and thus malloc will not work. + */ +#define CONFIG_SPL_PPAACT_ADDR 0x2e000000 +#define CONFIG_SPL_SPAACT_ADDR 0x2f000000 +#define CONFIG_SPL_JR0_LIODN_S 454 +#define CONFIG_SPL_JR0_LIODN_NS 458 +/* + * Define the key hash for U-Boot here if public/private key pair used to + * sign U-boot are different from the SRK hash put in the fuse + * Example of defining KEY_HASH is + * #define CONFIG_SPL_UBOOT_KEY_HASH \ + * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" + * else leave it defined as NULL + */ + +#define CONFIG_SPL_UBOOT_KEY_HASH NULL +#endif /* ifdef CONFIG_SPL_BUILD */ + #define CONFIG_CMD_ESBC_VALIDATE #define CONFIG_CMD_BLOB #define CONFIG_FSL_SEC_MON @@ -82,7 +116,9 @@ #define CONFIG_FSL_CAAM #endif -/* fsl_setenv_chain_of_trust() must be called from +#ifndef CONFIG_SPL_BUILD +/* + * fsl_setenv_chain_of_trust() must be called from * board_late_init() */ #ifndef CONFIG_BOARD_LATE_INIT @@ -92,10 +128,10 @@ /* If Boot Script is not on NOR and is required to be copied on RAM */ #ifdef CONFIG_BOOTSCRIPT_COPY_RAM #define CONFIG_BS_HDR_ADDR_RAM 0x00010000 -#define CONFIG_BS_HDR_ADDR_FLASH 0x00800000 +#define CONFIG_BS_HDR_ADDR_DEVICE 0x00800000 #define CONFIG_BS_HDR_SIZE 0x00002000 #define CONFIG_BS_ADDR_RAM 0x00012000 -#define CONFIG_BS_ADDR_FLASH 0x00802000 +#define CONFIG_BS_ADDR_DEVICE 0x00802000 #define CONFIG_BS_SIZE 0x00001000 #define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM @@ -119,5 +155,6 @@ #endif /* #ifdef CONFIG_BOOTSCRIPT_COPY_RAM */ #include <config_fsl_chain_trust.h> +#endif /* #ifndef CONFIG_SPL_BUILD */ #endif /* #ifdef CONFIG_CHAIN_OF_TRUST */ #endif diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index c045a24d1ab..7a878be3e9e 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1579,7 +1579,7 @@ typedef struct cpc_corenet { #define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000 #define CPC_HDBCR0_TAG_ECC_SCRUB_DIS 0x01000000 #define CPC_HDBCR0_DATA_ECC_SCRUB_DIS 0x00400000 -#define CPC_HDBCR0_SPLRU_LEVEL_EN 0x003c0000 +#define CPC_HDBCR0_SPLRU_LEVEL_EN 0x001e0000 #endif /* CONFIG_SYS_FSL_CPC */ /* Global Utilities Block */ diff --git a/arch/powerpc/include/asm/status_led.h b/arch/powerpc/include/asm/status_led.h index 441619042d2..260a8319ce3 100644 --- a/arch/powerpc/include/asm/status_led.h +++ b/arch/powerpc/include/asm/status_led.h @@ -7,7 +7,7 @@ #ifndef __ASM_STATUS_LED_H__ #define __ASM_STATUS_LED_H__ -/* if not overriden */ +/* if not overridden */ #ifndef CONFIG_BOARD_SPECIFIC_LED # if defined(CONFIG_8xx) # include <mpc8xx.h> diff --git a/arch/sandbox/Kconfig b/arch/sandbox/Kconfig index a8a90cb7a4d..d4c1ee0662c 100644 --- a/arch/sandbox/Kconfig +++ b/arch/sandbox/Kconfig @@ -10,8 +10,13 @@ config SYS_BOARD config SYS_CPU default "sandbox" +config SANDBOX_SPL + bool "Enable SPL for sandbox" + select SUPPORT_SPL + config SYS_CONFIG_NAME - default "sandbox" + default "sandbox_spl" if SANDBOX_SPL + default "sandbox" if !SANDBOX_SPL config PCI bool "PCI support" diff --git a/arch/sandbox/config.mk b/arch/sandbox/config.mk index 16fd6d508a9..6d62abb0352 100644 --- a/arch/sandbox/config.mk +++ b/arch/sandbox/config.mk @@ -20,4 +20,9 @@ cmd_u-boot__ = $(CC) -o $@ -Wl,-T u-boot.lds \ -Wl,--start-group $(u-boot-main) -Wl,--end-group \ $(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map +cmd_u-boot-spl = (cd $(obj) && $(CC) -o $(SPL_BIN) -Wl,-T u-boot-spl.lds \ + -Wl,--start-group $(patsubst $(obj)/%,%,$(u-boot-spl-main)) \ + $(patsubst $(obj)/%,%,$(u-boot-spl-platdata)) -Wl,--end-group \ + $(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot-spl.map -Wl,--gc-sections) + CONFIG_ARCH_DEVICE_TREE := sandbox diff --git a/arch/sandbox/cpu/Makefile b/arch/sandbox/cpu/Makefile index 1b42fee1412..db4363358a8 100644 --- a/arch/sandbox/cpu/Makefile +++ b/arch/sandbox/cpu/Makefile @@ -8,6 +8,7 @@ # obj-y := cpu.o os.o start.o state.o +obj-$(CONFIG_SPL_BUILD) += spl.o obj-$(CONFIG_ETH_SANDBOX_RAW) += eth-raw-os.o obj-$(CONFIG_SANDBOX_SDL) += sdl.o diff --git a/arch/sandbox/cpu/cpu.c b/arch/sandbox/cpu/cpu.c index 196f3e1191e..2def72212d1 100644 --- a/arch/sandbox/cpu/cpu.c +++ b/arch/sandbox/cpu/cpu.c @@ -4,10 +4,12 @@ */ #define DEBUG #include <common.h> -#include <dm/root.h> +#include <errno.h> +#include <libfdt.h> #include <os.h> #include <asm/io.h> #include <asm/state.h> +#include <dm/root.h> DECLARE_GLOBAL_DATA_PTR; @@ -55,7 +57,7 @@ int cleanup_before_linux_select(int flags) void *map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) { -#ifdef CONFIG_PCI +#if defined(CONFIG_PCI) && !defined(CONFIG_SPL_BUILD) unsigned long plen = len; void *ptr; diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c index 8a4d719835c..2d63dd88f12 100644 --- a/arch/sandbox/cpu/os.c +++ b/arch/sandbox/cpu/os.c @@ -541,6 +541,57 @@ int os_jump_to_image(const void *dest, int size) return unlink(fname); } +int os_find_u_boot(char *fname, int maxlen) +{ + struct sandbox_state *state = state_get_current(); + const char *progname = state->argv[0]; + int len = strlen(progname); + char *p; + int fd; + + if (len >= maxlen || len < 4) + return -ENOSPC; + + /* Look for 'u-boot' in the same directory as 'u-boot-spl' */ + strcpy(fname, progname); + if (!strcmp(fname + len - 4, "-spl")) { + fname[len - 4] = '\0'; + fd = os_open(fname, O_RDONLY); + if (fd >= 0) { + close(fd); + return 0; + } + } + + /* Look for 'u-boot' in the parent directory of spl/ */ + p = strstr(fname, "/spl/"); + if (p) { + strcpy(p, p + 4); + fd = os_open(fname, O_RDONLY); + if (fd >= 0) { + close(fd); + return 0; + } + } + + return -ENOENT; +} + +int os_spl_to_uboot(const char *fname) +{ + struct sandbox_state *state = state_get_current(); + char *argv[state->argc + 1]; + int ret; + + memcpy(argv, state->argv, sizeof(char *) * (state->argc + 1)); + argv[0] = (char *)fname; + ret = execv(fname, argv); + if (ret) + return ret; + + return unlink(fname); +} + void os_localtime(struct rtc_time *rt) { time_t t = time(NULL); diff --git a/arch/sandbox/cpu/spl.c b/arch/sandbox/cpu/spl.c new file mode 100644 index 00000000000..e8349c0b932 --- /dev/null +++ b/arch/sandbox/cpu/spl.c @@ -0,0 +1,68 @@ +/* + * Copyright (c) 2016 Google, Inc + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <os.h> +#include <spl.h> +#include <asm/spl.h> +#include <asm/state.h> + +DECLARE_GLOBAL_DATA_PTR; + +void board_init_f(ulong flag) +{ + struct sandbox_state *state = state_get_current(); + + gd->arch.ram_buf = state->ram_buf; + gd->ram_size = state->ram_size; +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_BOARD; +} + +void spl_board_announce_boot_device(void) +{ + char fname[256]; + int ret; + + ret = os_find_u_boot(fname, sizeof(fname)); + if (ret) { + printf("(%s not found, error %d)\n", fname, ret); + return; + } + printf("%s\n", fname); +} + +int spl_board_load_image(void) +{ + char fname[256]; + int ret; + + ret = os_find_u_boot(fname, sizeof(fname)); + if (ret) + return ret; + + /* Hopefully this will not return */ + return os_spl_to_uboot(fname); +} + +void spl_board_init(void) +{ + struct udevice *dev; + + preloader_console_init(); + + /* + * Scan all the devices so that we can output their platform data. See + * sandbox_spl_probe(). + */ + for (uclass_first_device(UCLASS_MISC, &dev); + dev; + uclass_next_device(&dev)) + ; +} diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c index 969618ef875..6e4ec017ccd 100644 --- a/arch/sandbox/cpu/start.c +++ b/arch/sandbox/cpu/start.c @@ -73,6 +73,7 @@ static int sandbox_cmdline_cb_help(struct sandbox_state *state, const char *arg) } SANDBOX_CMDLINE_OPT_SHORT(help, 'h', 0, "Display help"); +#ifndef CONFIG_SPL_BUILD int sandbox_main_loop_init(void) { struct sandbox_state *state = state_get_current(); @@ -97,6 +98,7 @@ int sandbox_main_loop_init(void) return 0; } +#endif static int sandbox_cmdline_cb_boot(struct sandbox_state *state, const char *arg) diff --git a/arch/sandbox/cpu/u-boot-spl.lds b/arch/sandbox/cpu/u-boot-spl.lds new file mode 100644 index 00000000000..7e92b4ac66c --- /dev/null +++ b/arch/sandbox/cpu/u-boot-spl.lds @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2011-2012 The Chromium OS Authors. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +SECTIONS +{ + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + __u_boot_sandbox_option_start = .; + _u_boot_sandbox_getopt : { *(.u_boot_sandbox_getopt) } + __u_boot_sandbox_option_end = .; + + __bss_start = .; +} + +INSERT BEFORE .data; diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts index 2ae40148b09..e6d336f16ab 100644 --- a/arch/sandbox/dts/sandbox.dts +++ b/arch/sandbox/dts/sandbox.dts @@ -172,6 +172,37 @@ }; }; + spl-test { + u-boot,dm-pre-reloc; + compatible = "sandbox,spl-test"; + boolval; + intval = <1>; + intarray = <2 3 4>; + byteval = [05]; + bytearray = [06]; + longbytearray = [09 0a 0b 0c 0d 0e 0f 10 11]; + stringval = "message"; + stringarray = "multi-word", "message"; + }; + + spl-test2 { + u-boot,dm-pre-reloc; + compatible = "sandbox,spl-test"; + intval = <3>; + intarray = <5>; + byteval = [08]; + bytearray = [01 23 34]; + longbytearray = [09 0a 0b 0c]; + stringval = "message2"; + stringarray = "another", "multi-word", "message"; + }; + + spl-test3 { + u-boot,dm-pre-reloc; + compatible = "sandbox,spl-test"; + stringarray = "one"; + }; + square { compatible = "demo-shape"; colour = "blue"; diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 9e46f9e815a..fff175d1b7a 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -262,6 +262,16 @@ }; }; + pwrdom: power-domain { + compatible = "sandbox,power-domain"; + #power-domain-cells = <1>; + }; + + power-domain-test { + compatible = "sandbox,power-domain-test"; + power-domains = <&pwrdom 2>; + }; + ram { compatible = "sandbox,ram"; }; diff --git a/arch/sandbox/include/asm/power-domain.h b/arch/sandbox/include/asm/power-domain.h new file mode 100644 index 00000000000..cad388549ee --- /dev/null +++ b/arch/sandbox/include/asm/power-domain.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __SANDBOX_POWER_DOMAIN_H +#define __SANDBOX_POWER_DOMAIN_H + +#include <common.h> + +struct udevice; + +int sandbox_power_domain_query(struct udevice *dev, unsigned long id); + +int sandbox_power_domain_test_get(struct udevice *dev); +int sandbox_power_domain_test_on(struct udevice *dev); +int sandbox_power_domain_test_off(struct udevice *dev); +int sandbox_power_domain_test_free(struct udevice *dev); + +#endif diff --git a/arch/sandbox/include/asm/spl.h b/arch/sandbox/include/asm/spl.h new file mode 100644 index 00000000000..59f24011703 --- /dev/null +++ b/arch/sandbox/include/asm/spl.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2016 Google, Inc + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __asm_spl_h +#define __asm_spl_h + +#define CONFIG_SPL_BOARD_LOAD_IMAGE + +/** + * Board-specific load method for boards that have a special way of loading + * U-Boot, which does not fit with the existing SPL code. + * + * @return 0 on success, negative errno value on failure. + */ +int spl_board_load_image(void); + +enum { + BOOT_DEVICE_BOARD, +}; + +#endif diff --git a/arch/sandbox/lib/Makefile b/arch/sandbox/lib/Makefile index 96761e27f7a..2e7802feac8 100644 --- a/arch/sandbox/lib/Makefile +++ b/arch/sandbox/lib/Makefile @@ -8,5 +8,8 @@ # obj-y += interrupts.o +ifndef CONFIG_SPL_BUILD obj-$(CONFIG_PCI) += pci_io.o +endif obj-$(CONFIG_CMD_BOOTM) += bootm.o +obj-$(CONFIG_CMD_BOOTZ) += bootm.o diff --git a/arch/sandbox/lib/bootm.c b/arch/sandbox/lib/bootm.c index d49c927b346..0c9a7979d23 100644 --- a/arch/sandbox/lib/bootm.c +++ b/arch/sandbox/lib/bootm.c @@ -56,7 +56,7 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) bootstage_mark(BOOTSTAGE_ID_RUN_OS); printf("## Transferring control to Linux (at address %08lx)...\n", images->ep); - reset_cpu(0); + printf("sandbox: continuing, as we cannot run Linux\n"); } return 0; diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h index 0a00db36179..5dc27bebd50 100644 --- a/arch/sh/include/asm/io.h +++ b/arch/sh/include/asm/io.h @@ -128,39 +128,6 @@ extern void __raw_readsl(unsigned int addr, void *data, int longlen); #define in_8(port) inb(port) #define in_le16(port) inw(port) #define in_le32(port) inl(port) -/* - * ioremap and friends. - * - * ioremap takes a PCI memory address, as specified in - * linux/Documentation/IO-mapping.txt. If you want a - * physical address, use __ioremap instead. - */ -extern void *__ioremap(unsigned long offset, size_t size, unsigned long flags); -extern void __iounmap(void *addr); - -/* - * Generic ioremap support. - * - * Define: - * iomem_valid_addr(off,size) - * iomem_to_phys(off) - */ -#ifdef iomem_valid_addr -#define __arch_ioremap(off, sz, nocache) \ -({ \ - unsigned long _off = (off), _size = (sz); \ - void *_ret = (void *)0; \ - if (iomem_valid_addr(_off, _size)) \ - _ret = __ioremap(iomem_to_phys(_off), _size, 0); \ - _ret; \ -}) - -#define __arch_iounmap __iounmap -#endif - -#define ioremap(off, sz) __arch_ioremap((off), (sz), 0) -#define ioremap_nocache(off, sz) __arch_ioremap((off), (sz), 1) -#define iounmap(_addr) __arch_iounmap(_addr) /* * DMA-consistent mapping functions. These allocate/free a region of diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 29d2307fa56..5193ee71591 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -8,12 +8,18 @@ choice prompt "Mainboard vendor" default VENDOR_EMULATION +config VENDOR_ADVANTECH + bool "advantech" + config VENDOR_CONGATEC bool "congatec" config VENDOR_COREBOOT bool "coreboot" +config VENDOR_DFI + bool "dfi" + config VENDOR_EFI bool "efi" @@ -29,8 +35,10 @@ config VENDOR_INTEL endchoice # board-specific options below +source "board/advantech/Kconfig" source "board/congatec/Kconfig" source "board/coreboot/Kconfig" +source "board/dfi/Kconfig" source "board/efi/Kconfig" source "board/emulation/Kconfig" source "board/google/Kconfig" diff --git a/arch/x86/cpu/baytrail/Kconfig b/arch/x86/cpu/baytrail/Kconfig index 407feb214bf..1c8ac370b30 100644 --- a/arch/x86/cpu/baytrail/Kconfig +++ b/arch/x86/cpu/baytrail/Kconfig @@ -7,3 +7,14 @@ config INTEL_BAYTRAIL bool select HAVE_FSP if !EFI + +if INTEL_BAYTRAIL +config INTERNAL_UART + bool "Enable the SoC integrated legacy UART" + help + There is a legacy UART integrated into the Bay Trail SoC. + A maximum baud rate of 115200 bps is supported. For this + reason, it is recommended that the UART port be used for + debug purposes only, eg: U-Boot console. + +endif diff --git a/arch/x86/cpu/baytrail/acpi.c b/arch/x86/cpu/baytrail/acpi.c index 5ee4868cf82..fa92d8852ea 100644 --- a/arch/x86/cpu/baytrail/acpi.c +++ b/arch/x86/cpu/baytrail/acpi.c @@ -5,10 +5,14 @@ */ #include <common.h> +#include <cpu.h> +#include <dm.h> +#include <dm/uclass-internal.h> #include <asm/acpi_table.h> #include <asm/ioapic.h> #include <asm/mpspec.h> #include <asm/tables.h> +#include <asm/arch/global_nvs.h> #include <asm/arch/iomap.h> void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs, @@ -161,3 +165,25 @@ u32 acpi_fill_madt(u32 current) return current; } + +void acpi_create_gnvs(struct acpi_global_nvs *gnvs) +{ + struct udevice *dev; + int ret; + + /* at least we have one processor */ + gnvs->pcnt = 1; + /* override the processor count with actual number */ + ret = uclass_find_first_device(UCLASS_CPU, &dev); + if (ret == 0 && dev != NULL) { + ret = cpu_get_count(dev); + if (ret > 0) + gnvs->pcnt = ret; + } + + /* determine whether internal uart is on */ + if (IS_ENABLED(CONFIG_INTERNAL_UART)) + gnvs->iuart_en = 1; + else + gnvs->iuart_en = 0; +} diff --git a/arch/x86/cpu/baytrail/cpu.c b/arch/x86/cpu/baytrail/cpu.c index b1faf8ca326..2837709d6d1 100644 --- a/arch/x86/cpu/baytrail/cpu.c +++ b/arch/x86/cpu/baytrail/cpu.c @@ -9,12 +9,60 @@ #include <common.h> #include <cpu.h> #include <dm.h> +#include <pci.h> #include <asm/cpu.h> #include <asm/cpu_x86.h> +#include <asm/io.h> #include <asm/lapic.h> #include <asm/msr.h> #include <asm/turbo.h> +#define BYT_PRV_CLK 0x800 +#define BYT_PRV_CLK_EN (1 << 0) +#define BYT_PRV_CLK_M_VAL_SHIFT 1 +#define BYT_PRV_CLK_N_VAL_SHIFT 16 +#define BYT_PRV_CLK_UPDATE (1 << 31) + +static void hsuart_clock_set(void *base) +{ + u32 m, n, reg; + + /* + * Configure the BayTrail UART clock for the internal HS UARTs + * (PCI devices) to 58982400 Hz + */ + m = 0x2400; + n = 0x3d09; + reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT); + writel(reg, base + BYT_PRV_CLK); + reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE; + writel(reg, base + BYT_PRV_CLK); +} + +/* + * Configure the internal clock of both SIO HS-UARTs, if they are enabled + * via FSP + */ +int arch_cpu_init_dm(void) +{ + struct udevice *dev; + void *base; + int ret; + int i; + + /* Loop over the 2 HS-UARTs */ + for (i = 0; i < 2; i++) { + ret = dm_pci_bus_find_bdf(PCI_BDF(0, 0x1e, 3 + i), &dev); + if (!ret) { + base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, + PCI_REGION_MEM); + hsuart_clock_set(base); + } + } + + return 0; +} + static void set_max_freq(void) { msr_t perf_ctl; diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c index ff1faa50147..4e0be2a88b9 100644 --- a/arch/x86/cpu/ivybridge/lpc.c +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -424,8 +424,6 @@ static void set_spi_speed(void) static int lpc_init_extra(struct udevice *dev) { struct udevice *pch = dev->parent; - const void *blob = gd->fdt_blob; - int node; debug("pch: lpc_init\n"); dm_pci_write_bar32(pch, 0, 0); @@ -434,10 +432,6 @@ static int lpc_init_extra(struct udevice *dev) dm_pci_write_bar32(pch, 3, 0x800); dm_pci_write_bar32(pch, 4, 0x900); - node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH); - if (node < 0) - return -ENOENT; - /* Set the value for PCI command register. */ dm_pci_write_config16(pch, PCI_COMMAND, 0x000f); diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index 9d9f63d70c6..e0b06b5ada5 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -458,6 +458,11 @@ int dram_init(void) struct udevice *dev, *me_dev; int ret; + /* We need the pinctrl set up early */ + ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev); + if (ret) + return ret; + ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &dev); if (ret) return ret; diff --git a/arch/x86/cpu/quark/acpi.c b/arch/x86/cpu/quark/acpi.c index 8f698296083..3968f7a8bfe 100644 --- a/arch/x86/cpu/quark/acpi.c +++ b/arch/x86/cpu/quark/acpi.c @@ -9,6 +9,7 @@ #include <asm/ioapic.h> #include <asm/mpspec.h> #include <asm/tables.h> +#include <asm/arch/global_nvs.h> #include <asm/arch/iomap.h> void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs, @@ -161,3 +162,9 @@ u32 acpi_fill_madt(u32 current) return current; } + +void acpi_create_gnvs(struct acpi_global_nvs *gnvs) +{ + /* quark is a uni-processor */ + gnvs->pcnt = 1; +} diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile index 23156bb2314..3f534ad40a6 100644 --- a/arch/x86/dts/Makefile +++ b/arch/x86/dts/Makefile @@ -9,12 +9,15 @@ dtb-y += bayleybay.dtb \ conga-qeval20-qa3-e3845.dtb \ cougarcanyon2.dtb \ crownbay.dtb \ + dfi-bt700-q7x-151.dtb \ efi.dtb \ galileo.dtb \ minnowmax.dtb \ qemu-x86_i440fx.dtb \ qemu-x86_q35.dtb \ - broadwell_som-6896.dtb + theadorable-x86-dfi-bt700.dtb \ + broadwell_som-6896.dtb \ + baytrail_som-db5800-som-6867.dtb targets += $(dtb-y) diff --git a/arch/x86/dts/baytrail_som-db5800-som-6867.dts b/arch/x86/dts/baytrail_som-db5800-som-6867.dts new file mode 100644 index 00000000000..e1d81a7283a --- /dev/null +++ b/arch/x86/dts/baytrail_som-db5800-som-6867.dts @@ -0,0 +1,295 @@ +/* + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> + * Copyright (C) 2016, George McCollister <george.mccollister@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include <dt-bindings/gpio/x86-gpio.h> +#include <dt-bindings/interrupt-router/intel-irq.h> + +/include/ "skeleton.dtsi" +/include/ "serial.dtsi" +/include/ "rtc.dtsi" +/include/ "tsc_timer.dtsi" + +/ { + model = "Advantech SOM-DB5800-SOM-6867"; + compatible = "advantech,som-db5800-som-6867", "intel,baytrail"; + + aliases { + serial0 = &serial; + spi0 = &spi; + }; + + config { + silent_console = <0>; + }; + + pch_pinctrl { + compatible = "intel,x86-pinctrl"; + reg = <0 0>; + + /* HDA_RSTB */ + soc_gpio_s0_8@0 { + pad-offset = <0x220>; + mode-func = <2>; + }; + + /* HDA_SYNC */ + soc_gpio_s0_9@0 { + pad-offset = <0x250>; + mode-func = <2>; + pull-assign = <1>; + }; + + /* HDA_CLK */ + soc_gpio_s0_10@0 { + pad-offset = <0x240>; + mode-func = <2>; + }; + + /* HDA_SDO */ + soc_gpio_s0_11@0 { + pad-offset = <0x260>; + mode-func = <2>; + pull-assign = <1>; + }; + + /* HDA_SDI0 */ + soc_gpio_s0_12@0 { + pad-offset = <0x270>; + mode-func = <2>; + }; + + /* SERIRQ */ + soc_gpio_s0_50@0 { + pad-offset = <0x560>; + mode-func = <1>; + }; + }; + + chosen { + stdout-path = "/serial"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "intel,baytrail-cpu"; + reg = <0>; + intel,apic-id = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "intel,baytrail-cpu"; + reg = <1>; + intel,apic-id = <2>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "intel,baytrail-cpu"; + reg = <2>; + intel,apic-id = <4>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "intel,baytrail-cpu"; + reg = <3>; + intel,apic-id = <6>; + }; + + }; + + pci { + compatible = "intel,pci-baytrail", "pci-x86"; + #address-cells = <3>; + #size-cells = <2>; + u-boot,dm-pre-reloc; + ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000 + 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 + 0x01000000 0x0 0x2000 0x2000 0 0xe000>; + + pch@1f,0 { + reg = <0x0000f800 0 0 0 0>; + compatible = "pci8086,0f1c", "intel,pch9"; + #address-cells = <1>; + #size-cells = <1>; + + irq-router { + compatible = "intel,irq-router"; + intel,pirq-config = "ibase"; + intel,ibase-offset = <0x50>; + intel,actl-addr = <0>; + intel,pirq-link = <8 8>; + intel,pirq-mask = <0xdee0>; + intel,pirq-routing = < + /* BayTrail PCI devices */ + PCI_BDF(0, 2, 0) INTA PIRQA + PCI_BDF(0, 3, 0) INTA PIRQA + PCI_BDF(0, 16, 0) INTA PIRQA + PCI_BDF(0, 17, 0) INTA PIRQA + PCI_BDF(0, 18, 0) INTA PIRQA + PCI_BDF(0, 19, 0) INTA PIRQA + PCI_BDF(0, 20, 0) INTA PIRQA + PCI_BDF(0, 21, 0) INTA PIRQA + PCI_BDF(0, 22, 0) INTA PIRQA + PCI_BDF(0, 23, 0) INTA PIRQA + PCI_BDF(0, 24, 0) INTA PIRQA + PCI_BDF(0, 24, 1) INTC PIRQC + PCI_BDF(0, 24, 2) INTD PIRQD + PCI_BDF(0, 24, 3) INTB PIRQB + PCI_BDF(0, 24, 4) INTA PIRQA + PCI_BDF(0, 24, 5) INTC PIRQC + PCI_BDF(0, 24, 6) INTD PIRQD + PCI_BDF(0, 24, 7) INTB PIRQB + PCI_BDF(0, 26, 0) INTA PIRQA + PCI_BDF(0, 27, 0) INTA PIRQA + PCI_BDF(0, 28, 0) INTA PIRQA + PCI_BDF(0, 28, 1) INTB PIRQB + PCI_BDF(0, 28, 2) INTC PIRQC + PCI_BDF(0, 28, 3) INTD PIRQD + PCI_BDF(0, 29, 0) INTA PIRQA + PCI_BDF(0, 30, 0) INTA PIRQA + PCI_BDF(0, 30, 1) INTD PIRQD + PCI_BDF(0, 30, 2) INTB PIRQB + PCI_BDF(0, 30, 3) INTC PIRQC + PCI_BDF(0, 30, 4) INTD PIRQD + PCI_BDF(0, 30, 5) INTB PIRQB + PCI_BDF(0, 31, 3) INTB PIRQB + + /* + * PCIe root ports downstream + * interrupts + */ + PCI_BDF(1, 0, 0) INTA PIRQA + PCI_BDF(1, 0, 0) INTB PIRQB + PCI_BDF(1, 0, 0) INTC PIRQC + PCI_BDF(1, 0, 0) INTD PIRQD + PCI_BDF(2, 0, 0) INTA PIRQB + PCI_BDF(2, 0, 0) INTB PIRQC + PCI_BDF(2, 0, 0) INTC PIRQD + PCI_BDF(2, 0, 0) INTD PIRQA + PCI_BDF(3, 0, 0) INTA PIRQC + PCI_BDF(3, 0, 0) INTB PIRQD + PCI_BDF(3, 0, 0) INTC PIRQA + PCI_BDF(3, 0, 0) INTD PIRQB + PCI_BDF(4, 0, 0) INTA PIRQD + PCI_BDF(4, 0, 0) INTB PIRQA + PCI_BDF(4, 0, 0) INTC PIRQB + PCI_BDF(4, 0, 0) INTD PIRQC + >; + }; + + spi: spi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,ich9-spi"; + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + compatible = "macronix,mx25l6405d", + "spi-flash"; + memory-map = <0xff800000 0x00800000>; + rw-mrc-cache { + label = "rw-mrc-cache"; + reg = <0x006f0000 0x00010000>; + }; + }; + }; + + gpioa { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0 0x20>; + bank-name = "A"; + }; + + gpiob { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x20 0x20>; + bank-name = "B"; + }; + + gpioc { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x40 0x20>; + bank-name = "C"; + }; + + gpiod { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x60 0x20>; + bank-name = "D"; + }; + + gpioe { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x80 0x20>; + bank-name = "E"; + }; + + gpiof { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0xA0 0x20>; + bank-name = "F"; + }; + }; + }; + + fsp { + compatible = "intel,baytrail-fsp"; + fsp,mrc-init-tseg-size = <0>; + fsp,mrc-init-mmio-size = <0x800>; + fsp,mrc-init-spd-addr1 = <0xa0>; + fsp,mrc-init-spd-addr2 = <0xa2>; + fsp,enable-spi; + fsp,enable-sata; + fsp,sata-mode = <1>; + fsp,enable-azalia; + fsp,lpss-sio-enable-pci-mode; + fsp,enable-dma0; + fsp,enable-dma1; + fsp,enable-i2c0; + fsp,enable-i2c1; + fsp,enable-i2c2; + fsp,enable-i2c3; + fsp,enable-i2c4; + fsp,enable-i2c5; + fsp,enable-i2c6; + fsp,enable-pwm0; + fsp,enable-pwm1; + fsp,igd-dvmt50-pre-alloc = <2>; + fsp,aperture-size = <2>; + fsp,gtt-size = <2>; + fsp,scc-enable-pci-mode; + fsp,os-selection = <4>; + fsp,enable-igd; + fsp,serial-debug-port-address = <0x3f8>; + fsp,serial-debug-port-type = <1>; + }; + + microcode { + update@0 { +#include "microcode/m0130673325.dtsi" + }; + update@1 { +#include "microcode/m0130679907.dtsi" + }; + }; + +}; diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts index fba089d6668..f0efe908e2c 100644 --- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts +++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts @@ -46,6 +46,17 @@ pad-offset = <0x3a0>; mode-func = <1>; }; + + /* Add SMBus PAD configuration */ + smbus_clk@0 { + pad-offset = <0x580>; + mode-func = <1>; + }; + + smbus_data@0 { + pad-offset = <0x5a0>; + mode-func = <1>; + }; }; chosen { @@ -244,13 +255,6 @@ fsp,lpss-sio-enable-pci-mode; fsp,enable-dma0; fsp,enable-dma1; - fsp,enable-i2c0; - fsp,enable-i2c1; - fsp,enable-i2c2; - fsp,enable-i2c3; - fsp,enable-i2c4; - fsp,enable-i2c5; - fsp,enable-i2c6; fsp,enable-pwm0; fsp,enable-pwm1; fsp,igd-dvmt50-pre-alloc = <2>; diff --git a/arch/x86/dts/dfi-bt700-q7x-151.dts b/arch/x86/dts/dfi-bt700-q7x-151.dts new file mode 100644 index 00000000000..31d96790598 --- /dev/null +++ b/arch/x86/dts/dfi-bt700-q7x-151.dts @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> + * Copyright (C) 2016 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "dfi-bt700.dtsi" + +#include "serial.dtsi" + +/ { + model = "DFI-BT700"; + compatible = "dfi,bt700", "intel,baytrail"; + + aliases { + serial0 = &serial; + spi0 = &spi; + }; +}; diff --git a/arch/x86/dts/dfi-bt700.dtsi b/arch/x86/dts/dfi-bt700.dtsi new file mode 100644 index 00000000000..75ee6ade7c1 --- /dev/null +++ b/arch/x86/dts/dfi-bt700.dtsi @@ -0,0 +1,308 @@ +/* + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> + * Copyright (C) 2016 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dt-bindings/gpio/x86-gpio.h> +#include <dt-bindings/interrupt-router/intel-irq.h> + +#include "skeleton.dtsi" +#include "rtc.dtsi" +#include "tsc_timer.dtsi" + +/ { + config { + silent_console = <0>; + }; + + pch_pinctrl { + compatible = "intel,x86-pinctrl"; + reg = <0 0>; + + /* Add UART1 PAD configuration (SIO HS-UART) */ + uart1_txd@0 { + pad-offset = <0x10>; + mode-func = <1>; + }; + + uart1_rxd@0 { + pad-offset = <0x20>; + mode-func = <1>; + }; + + /* + * As of today, the latest version FSP (gold4) for BayTrail + * misses the PAD configuration of the SD controller's Card + * Detect signal. The default PAD value for the CD pin sets + * the pin to work in GPIO mode, which causes card detect + * status cannot be reflected by the Present State register + * in the SD controller (bit 16 & bit 18 are always zero). + * + * Configure this pin to function 1 (SD controller). + */ + sdmmc3_cd@0 { + pad-offset = <0x3a0>; + mode-func = <1>; + }; + }; + + chosen { + stdout-path = "/serial"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "intel,baytrail-cpu"; + reg = <0>; + intel,apic-id = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "intel,baytrail-cpu"; + reg = <1>; + intel,apic-id = <2>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "intel,baytrail-cpu"; + reg = <2>; + intel,apic-id = <4>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "intel,baytrail-cpu"; + reg = <3>; + intel,apic-id = <6>; + }; + }; + + pci { + compatible = "intel,pci-baytrail", "pci-x86"; + #address-cells = <3>; + #size-cells = <2>; + u-boot,dm-pre-reloc; + ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000 + 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 + 0x01000000 0x0 0x2000 0x2000 0 0xe000>; + + pciuart0: uart@1e,3 { + compatible = "pci8086,0f0a.00", + "pci8086,0f0a", + "pciclass,070002", + "pciclass,0700", + "ns16550"; + u-boot,dm-pre-reloc; + reg = <0x0200f310 0x0 0x0 0x0 0x0>; + reg-shift = <2>; + clock-frequency = <58982400>; + current-speed = <115200>; + }; + + pch@1f,0 { + reg = <0x0000f800 0 0 0 0>; + compatible = "pci8086,0f1c", "intel,pch9"; + #address-cells = <1>; + #size-cells = <1>; + + irq-router { + compatible = "intel,irq-router"; + intel,pirq-config = "ibase"; + intel,ibase-offset = <0x50>; + intel,actl-addr = <0>; + intel,pirq-link = <8 8>; + intel,pirq-mask = <0xdee0>; + intel,pirq-routing = < + /* BayTrail PCI devices */ + PCI_BDF(0, 2, 0) INTA PIRQA + PCI_BDF(0, 3, 0) INTA PIRQA + PCI_BDF(0, 16, 0) INTA PIRQA + PCI_BDF(0, 17, 0) INTA PIRQA + PCI_BDF(0, 18, 0) INTA PIRQA + PCI_BDF(0, 19, 0) INTA PIRQA + PCI_BDF(0, 20, 0) INTA PIRQA + PCI_BDF(0, 21, 0) INTA PIRQA + PCI_BDF(0, 22, 0) INTA PIRQA + PCI_BDF(0, 23, 0) INTA PIRQA + PCI_BDF(0, 24, 0) INTA PIRQA + PCI_BDF(0, 24, 1) INTC PIRQC + PCI_BDF(0, 24, 2) INTD PIRQD + PCI_BDF(0, 24, 3) INTB PIRQB + PCI_BDF(0, 24, 4) INTA PIRQA + PCI_BDF(0, 24, 5) INTC PIRQC + PCI_BDF(0, 24, 6) INTD PIRQD + PCI_BDF(0, 24, 7) INTB PIRQB + PCI_BDF(0, 26, 0) INTA PIRQA + PCI_BDF(0, 27, 0) INTA PIRQA + PCI_BDF(0, 28, 0) INTA PIRQA + PCI_BDF(0, 28, 1) INTB PIRQB + PCI_BDF(0, 28, 2) INTC PIRQC + PCI_BDF(0, 28, 3) INTD PIRQD + PCI_BDF(0, 29, 0) INTA PIRQA + PCI_BDF(0, 30, 0) INTA PIRQA + PCI_BDF(0, 30, 1) INTD PIRQD + PCI_BDF(0, 30, 2) INTB PIRQB + PCI_BDF(0, 30, 3) INTC PIRQC + PCI_BDF(0, 30, 4) INTD PIRQD + PCI_BDF(0, 30, 5) INTB PIRQB + PCI_BDF(0, 31, 3) INTB PIRQB + + /* + * PCIe root ports downstream + * interrupts + */ + PCI_BDF(1, 0, 0) INTA PIRQA + PCI_BDF(1, 0, 0) INTB PIRQB + PCI_BDF(1, 0, 0) INTC PIRQC + PCI_BDF(1, 0, 0) INTD PIRQD + PCI_BDF(2, 0, 0) INTA PIRQB + PCI_BDF(2, 0, 0) INTB PIRQC + PCI_BDF(2, 0, 0) INTC PIRQD + PCI_BDF(2, 0, 0) INTD PIRQA + PCI_BDF(3, 0, 0) INTA PIRQC + PCI_BDF(3, 0, 0) INTB PIRQD + PCI_BDF(3, 0, 0) INTC PIRQA + PCI_BDF(3, 0, 0) INTD PIRQB + PCI_BDF(4, 0, 0) INTA PIRQD + PCI_BDF(4, 0, 0) INTB PIRQA + PCI_BDF(4, 0, 0) INTC PIRQB + PCI_BDF(4, 0, 0) INTD PIRQC + >; + }; + + spi: spi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,ich9-spi"; + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + compatible = "stmicro,n25q064a", + "spi-flash"; + memory-map = <0xff800000 0x00800000>; + rw-mrc-cache { + label = "rw-mrc-cache"; + reg = <0x006f0000 0x00010000>; + }; + }; + }; + + gpioa { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0 0x20>; + bank-name = "A"; + }; + + gpiob { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x20 0x20>; + bank-name = "B"; + }; + + gpioc { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x40 0x20>; + bank-name = "C"; + }; + + gpiod { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x60 0x20>; + bank-name = "D"; + }; + + gpioe { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x80 0x20>; + bank-name = "E"; + }; + + gpiof { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0xA0 0x20>; + bank-name = "F"; + }; + }; + }; + + fsp { + compatible = "intel,baytrail-fsp"; + fsp,mrc-init-tseg-size = <0>; + fsp,mrc-init-mmio-size = <0x800>; + fsp,mrc-init-spd-addr1 = <0xa0>; + fsp,mrc-init-spd-addr2 = <0xa2>; + fsp,emmc-boot-mode = <1>; + fsp,enable-sdio; + fsp,enable-sdcard; + fsp,enable-hsuart0; + fsp,enable-hsuart1; + fsp,enable-spi; + fsp,enable-sata; + fsp,sata-mode = <1>; + fsp,enable-lpe; + fsp,lpss-sio-enable-pci-mode; + fsp,enable-dma0; + fsp,enable-dma1; + fsp,enable-i2c0; + fsp,enable-i2c1; + fsp,enable-i2c2; + fsp,enable-i2c3; + fsp,enable-i2c4; + fsp,enable-i2c5; + fsp,enable-i2c6; + fsp,enable-pwm0; + fsp,enable-pwm1; + fsp,igd-dvmt50-pre-alloc = <2>; + fsp,aperture-size = <2>; + fsp,gtt-size = <2>; + fsp,scc-enable-pci-mode; + fsp,os-selection = <4>; + fsp,emmc45-ddr50-enabled; + fsp,emmc45-retune-timer-value = <8>; + fsp,enable-igd; + fsp,enable-memory-down; + fsp,memory-down-params { + compatible = "intel,baytrail-fsp-mdp"; + fsp,dram-speed = <2>; /* 2=1333MHz */ + fsp,dram-type = <1>; /* 1=DDR3L */ + fsp,dimm-0-enable; + fsp,dimm-width = <1>; /* 1=x16, 2=x32 */ + fsp,dimm-density = <3>; /* 3=8Gbit */ + fsp,dimm-bus-width = <3>; /* 3=64bits */ + fsp,dimm-sides = <0>; /* 0=1 ranks -> 0x2b */ + + /* These following values might need a re-visit */ + fsp,dimm-tcl = <8>; + fsp,dimm-trpt-rcd = <8>; + fsp,dimm-twr = <8>; + fsp,dimm-twtr = <4>; + fsp,dimm-trrd = <6>; + fsp,dimm-trtp = <4>; + fsp,dimm-tfaw = <22>; + }; + }; + + microcode { + update@0 { +#include "microcode/m0130673325.dtsi" + }; + update@1 { +#include "microcode/m0130679907.dtsi" + }; + }; +}; diff --git a/arch/x86/dts/theadorable-x86-dfi-bt700.dts b/arch/x86/dts/theadorable-x86-dfi-bt700.dts new file mode 100644 index 00000000000..75f9ffa8f3b --- /dev/null +++ b/arch/x86/dts/theadorable-x86-dfi-bt700.dts @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> + * Copyright (C) 2016 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "dfi-bt700.dtsi" + +/ { + model = "theadorable-x86-DFI-BT700"; + compatible = "anonymous,theadorable-x86-dfi-bt700", "dfi,bt700", + "intel,baytrail"; + + aliases { + serial0 = &pciuart0; + spi0 = &spi; + }; +}; diff --git a/arch/x86/include/asm/acpi/global_nvs.h b/arch/x86/include/asm/acpi/global_nvs.h new file mode 100644 index 00000000000..7f2ffd49ecf --- /dev/null +++ b/arch/x86/include/asm/acpi/global_nvs.h @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ACPI_GNVS_H_ +#define _ACPI_GNVS_H_ + +/* + * This file provides two ACPI global NVS macros: ACPI_GNVS_ADDR and + * ACPI_GNVS_SIZE. They are to be used in platform's global_nvs.asl file + * to declare the GNVS OperationRegion, as well as write_acpi_tables() + * for the GNVS address runtime fix up. + */ +#define ACPI_GNVS_ADDR 0xdeadbeef +#define ACPI_GNVS_SIZE 0x100 + +#endif /* _ACPI_GNVS_H_ */ diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h index 56aa2821277..caff4d8a1e0 100644 --- a/arch/x86/include/asm/acpi_table.h +++ b/arch/x86/include/asm/acpi_table.h @@ -299,6 +299,9 @@ struct acpi_mcfg_mmconfig { /* PM1_CNT bit defines */ #define PM1_CNT_SCI_EN (1 << 0) +/* ACPI global NVS structure */ +struct acpi_global_nvs; + /* These can be used by the target port */ void acpi_fill_header(struct acpi_table_header *header, char *signature); @@ -312,4 +315,5 @@ int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride, int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi, u8 cpu, u16 flags, u8 lint); u32 acpi_fill_madt(u32 current); +void acpi_create_gnvs(struct acpi_global_nvs *gnvs); u32 write_acpi_tables(u32 start); diff --git a/arch/x86/include/asm/arch-baytrail/acpi/global_nvs.asl b/arch/x86/include/asm/arch-baytrail/acpi/global_nvs.asl new file mode 100644 index 00000000000..a28d4dfade7 --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/acpi/global_nvs.asl @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/acpi/global_nvs.h> + +OperationRegion(GNVS, SystemMemory, ACPI_GNVS_ADDR, ACPI_GNVS_SIZE) +Field(GNVS, ByteAcc, NoLock, Preserve) +{ + Offset (0x00), + PCNT, 8, /* processor count */ + IURE, 8, /* internal UART enabled */ +} diff --git a/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl b/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl index 22f0d68f4dd..fe34d3271c8 100644 --- a/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl +++ b/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl @@ -119,17 +119,14 @@ Device (LPCB) Method(_STA, 0, Serialized) { - /* - * TODO: - * - * Need to hide the internal UART depending on whether - * internal UART is enabled or not so that external - * SuperIO UART can be exposed to system. - */ - Store(1, UI3E) - Store(1, UI4E) - Store(1, C1EN) - Return (STA_VISIBLE) + If (LEqual(IURE, 1)) { + Store(1, UI3E) + Store(1, UI4E) + Store(1, C1EN) + Return (STA_VISIBLE) + } Else { + Return (STA_MISSING) + } } diff --git a/arch/x86/include/asm/arch-baytrail/acpi/platform.asl b/arch/x86/include/asm/arch-baytrail/acpi/platform.asl index 6bc82ecfe19..a80d2c0e515 100644 --- a/arch/x86/include/asm/arch-baytrail/acpi/platform.asl +++ b/arch/x86/include/asm/arch-baytrail/acpi/platform.asl @@ -22,6 +22,9 @@ Method(_WAK, 1) Return (Package() {0, 0}) } +/* ACPI global NVS */ +#include "global_nvs.asl" + /* TODO: add CPU ASL support */ Scope (\_SB) diff --git a/arch/x86/include/asm/arch-baytrail/global_nvs.h b/arch/x86/include/asm/arch-baytrail/global_nvs.h new file mode 100644 index 00000000000..56e362633fd --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/global_nvs.h @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _GLOBAL_NVS_H_ +#define _GLOBAL_NVS_H_ + +struct __packed acpi_global_nvs { + u8 pcnt; /* processor count */ + u8 iuart_en; /* internal UART enabled */ + + /* + * Add padding so sizeof(struct acpi_global_nvs) == 0x100. + * This must match the size defined in the global_nvs.asl. + */ + u8 rsvd[254]; +}; + +#endif /* _GLOBAL_NVS_H_ */ diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h index 4725250d918..9c51f63ca44 100644 --- a/arch/x86/include/asm/arch-ivybridge/pch.h +++ b/arch/x86/include/asm/arch-ivybridge/pch.h @@ -134,32 +134,6 @@ #define SATA_IOBP_SP0G3IR 0xea000151 #define SATA_IOBP_SP1G3IR 0xea000051 -/* PCI Configuration Space (D31:F3): SMBus */ -#define PCH_SMBUS_DEV PCI_BDF(0, 0x1f, 3) -#define SMB_BASE 0x20 -#define HOSTC 0x40 -#define SMB_RCV_SLVA 0x09 - -/* HOSTC bits */ -#define I2C_EN (1 << 2) -#define SMB_SMI_EN (1 << 1) -#define HST_EN (1 << 0) - -/* SMBus I/O bits. */ -#define SMBHSTSTAT 0x0 -#define SMBHSTCTL 0x2 -#define SMBHSTCMD 0x3 -#define SMBXMITADD 0x4 -#define SMBHSTDAT0 0x5 -#define SMBHSTDAT1 0x6 -#define SMBBLKDAT 0x7 -#define SMBTRNSADD 0x9 -#define SMBSLVDATA 0xa -#define SMLINK_PIN_CTL 0xe -#define SMBUS_PIN_CTL 0xf - -#define SMBUS_TIMEOUT (10 * 1000 * 100) - #define VCH 0x0000 /* 32bit */ #define VCAP1 0x0004 /* 32bit */ #define VCAP2 0x0008 /* 32bit */ diff --git a/arch/x86/include/asm/arch-quark/acpi/global_nvs.asl b/arch/x86/include/asm/arch-quark/acpi/global_nvs.asl new file mode 100644 index 00000000000..6f0435e1ded --- /dev/null +++ b/arch/x86/include/asm/arch-quark/acpi/global_nvs.asl @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/acpi/global_nvs.h> + +OperationRegion(GNVS, SystemMemory, ACPI_GNVS_ADDR, ACPI_GNVS_SIZE) +Field(GNVS, ByteAcc, NoLock, Preserve) +{ + Offset (0x00), + PCNT, 8, /* processor count */ +} diff --git a/arch/x86/include/asm/arch-quark/acpi/platform.asl b/arch/x86/include/asm/arch-quark/acpi/platform.asl index bd72842dd6b..1ecf153c0f9 100644 --- a/arch/x86/include/asm/arch-quark/acpi/platform.asl +++ b/arch/x86/include/asm/arch-quark/acpi/platform.asl @@ -22,6 +22,9 @@ Method(_WAK, 1) Return (Package() {0, 0}) } +/* ACPI global NVS */ +#include "global_nvs.asl" + /* TODO: add CPU ASL support */ Scope (\_SB) diff --git a/arch/x86/include/asm/arch-quark/global_nvs.h b/arch/x86/include/asm/arch-quark/global_nvs.h new file mode 100644 index 00000000000..0231da0bcd9 --- /dev/null +++ b/arch/x86/include/asm/arch-quark/global_nvs.h @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _GLOBAL_NVS_H_ +#define _GLOBAL_NVS_H_ + +struct __packed acpi_global_nvs { + u8 pcnt; /* processor count */ + + /* + * Add padding so sizeof(struct acpi_global_nvs) == 0x100. + * This must match the size defined in the global_nvs.asl. + */ + u8 rsvd[255]; +}; + +#endif /* _GLOBAL_NVS_H_ */ diff --git a/arch/x86/include/asm/cache.h b/arch/x86/include/asm/cache.h index 508b63f5ab3..4ff63c33317 100644 --- a/arch/x86/include/asm/cache.h +++ b/arch/x86/include/asm/cache.h @@ -11,12 +11,12 @@ * If CONFIG_SYS_CACHELINE_SIZE is defined use it for DMA alignment. Otherwise * use 64-bytes, a safe default for x86. */ -#ifdef CONFIG_SYS_CACHELINE_SIZE -#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE -#else -#define ARCH_DMA_MINALIGN 64 +#ifndef CONFIG_SYS_CACHELINE_SIZE +#define CONFIG_SYS_CACHELINE_SIZE 64 #endif +#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE + static inline void wbinvd(void) { asm volatile ("wbinvd" : : : "memory"); diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index bb71286dba8..7001e8ba348 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -11,10 +11,12 @@ #include <cpu.h> #include <dm.h> #include <dm/uclass-internal.h> +#include <asm/acpi/global_nvs.h> #include <asm/acpi_table.h> #include <asm/io.h> #include <asm/lapic.h> #include <asm/tables.h> +#include <asm/arch/global_nvs.h> /* * IASL compiles the dsdt entries and writes the hex values @@ -336,6 +338,7 @@ u32 write_acpi_tables(u32 start) struct acpi_fadt *fadt; struct acpi_mcfg *mcfg; struct acpi_madt *madt; + int i; current = start; @@ -383,6 +386,25 @@ u32 write_acpi_tables(u32 start) current += dsdt->length - sizeof(struct acpi_table_header); current = ALIGN(current, 16); + /* Pack GNVS into the ACPI table area */ + for (i = 0; i < dsdt->length; i++) { + u32 *gnvs = (u32 *)((u32)dsdt + i); + if (*gnvs == ACPI_GNVS_ADDR) { + debug("Fix up global NVS in DSDT to 0x%08x\n", current); + *gnvs = current; + break; + } + } + + /* Update DSDT checksum since we patched the GNVS address */ + dsdt->checksum = 0; + dsdt->checksum = table_compute_checksum((void *)dsdt, dsdt->length); + + /* Fill in platform-specific global NVS variables */ + acpi_create_gnvs((struct acpi_global_nvs *)current); + current += sizeof(struct acpi_global_nvs); + current = ALIGN(current, 16); + debug("ACPI: * FADT\n"); fadt = (struct acpi_fadt *)current; current += sizeof(struct acpi_fadt); diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c index b05dcede0c4..a4803612111 100644 --- a/arch/x86/lib/fsp/fsp_support.c +++ b/arch/x86/lib/fsp/fsp_support.c @@ -110,7 +110,7 @@ void fsp_init(u32 stack_top, u32 boot_mode, void *nvs_buf) struct upd_region *fsp_upd; #endif -#ifdef CONFIG_DEBUG_UART +#ifdef CONFIG_INTERNAL_UART setup_internal_uart(1); #endif diff --git a/arch/x86/lib/lpc-uclass.c b/arch/x86/lib/lpc-uclass.c index c6e8f73d225..eb033e6b3f6 100644 --- a/arch/x86/lib/lpc-uclass.c +++ b/arch/x86/lib/lpc-uclass.c @@ -7,24 +7,11 @@ #include <common.h> #include <dm.h> -#include <dm/root.h> DECLARE_GLOBAL_DATA_PTR; -static int lpc_uclass_post_bind(struct udevice *bus) -{ - /* - * Scan the device tree for devices - * - * Before relocation, only bind devices marked for pre-relocation - * use. - */ - return dm_scan_fdt_node(bus, gd->fdt_blob, bus->of_offset, - gd->flags & GD_FLG_RELOC ? false : true); -} - UCLASS_DRIVER(lpc) = { .id = UCLASS_LPC, .name = "lpc", - .post_bind = lpc_uclass_post_bind, + .post_bind = dm_scan_fdt_dev, }; diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig new file mode 100644 index 00000000000..2ba7132c20c --- /dev/null +++ b/arch/xtensa/Kconfig @@ -0,0 +1,21 @@ +menu "Xtensa architecture" + depends on XTENSA + +config SYS_ARCH + string + default "xtensa" + +config SYS_CPU + string "Xtensa Core Variant" + +choice + prompt "Target select" + +config TARGET_XTFPGA + bool "Support XTFPGA" + +endchoice + +source "board/cadence/xtfpga/Kconfig" + +endmenu diff --git a/arch/xtensa/Makefile b/arch/xtensa/Makefile new file mode 100644 index 00000000000..130d76f6be5 --- /dev/null +++ b/arch/xtensa/Makefile @@ -0,0 +1,8 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +head-y := arch/xtensa/cpu/start.o + +libs-y += arch/xtensa/cpu/ +libs-y += arch/xtensa/lib/ diff --git a/arch/xtensa/config.mk b/arch/xtensa/config.mk new file mode 100644 index 00000000000..7dd8d8a741f --- /dev/null +++ b/arch/xtensa/config.mk @@ -0,0 +1,12 @@ +# +# (C) Copyright 2007 - 2013 Tensilica, Inc. +# (C) Copyright 2014 - 2016 Cadence Design Systems Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +CROSS_COMPILE ?= xtensa-linux- +PLATFORM_CPPFLAGS += -D__XTENSA__ -mlongcalls -mforce-no-pic \ + -ffunction-sections -fdata-sections + +LDFLAGS_FINAL += --gc-sections diff --git a/arch/xtensa/cpu/Makefile b/arch/xtensa/cpu/Makefile new file mode 100644 index 00000000000..e83f6207d8c --- /dev/null +++ b/arch/xtensa/cpu/Makefile @@ -0,0 +1,9 @@ +# +# (C) Copyright 2007 - 2013 Tensilica, Inc. +# (C) Copyright 2014 - 2016 Cadence Design Systems Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y = cpu.o exceptions.o +extra-y = start.o diff --git a/arch/xtensa/cpu/cpu.c b/arch/xtensa/cpu/cpu.c new file mode 100644 index 00000000000..6787a6182c8 --- /dev/null +++ b/arch/xtensa/cpu/cpu.c @@ -0,0 +1,49 @@ +/* + * (C) Copyright 2008 - 2013 Tensilica Inc. + * (C) Copyright 2014 - 2016 Cadence Design Systems Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * CPU specific code + */ + +#include <common.h> +#include <command.h> +#include <linux/stringify.h> +#include <asm/global_data.h> +#include <asm/cache.h> +#include <asm/string.h> +#include <asm/misc.h> + +DECLARE_GLOBAL_DATA_PTR; + +gd_t *gd __attribute__((section(".data"))); + +#if defined(CONFIG_DISPLAY_CPUINFO) +/* + * Print information about the CPU. + */ + +int print_cpuinfo(void) +{ + char buf[120], mhz[8]; + uint32_t id0, id1; + + asm volatile ("rsr %0, 176\n" + "rsr %1, 208\n" + : "=r"(id0), "=r"(id1)); + + sprintf(buf, "CPU: Xtensa %s (id: %08x:%08x) at %s MHz\n", + XCHAL_CORE_ID, id0, id1, strmhz(mhz, gd->cpu_clk)); + puts(buf); + return 0; +} +#endif + +int arch_cpu_init(void) +{ + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + return 0; +} diff --git a/arch/xtensa/cpu/exceptions.c b/arch/xtensa/cpu/exceptions.c new file mode 100644 index 00000000000..16639a08e8b --- /dev/null +++ b/arch/xtensa/cpu/exceptions.c @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2008 - 2013 Tensilica Inc. + * (C) Copyright 2014 - 2016 Cadence Design Systems Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Exception handling. + * We currently don't handle any exception and force a reset. + * (Note that alloca is a special case and handled in start.S) + */ + +#include <common.h> +#include <command.h> +#include <asm/string.h> +#include <asm/regs.h> + +typedef void (*handler_t)(struct pt_regs *); + +void unhandled_exception(struct pt_regs *regs) +{ + printf("Unhandled Exception: EXCCAUSE = %ld, EXCVADDR = %lx, pc = %lx\n", + regs->exccause, regs->excvaddr, regs->pc); + panic("*** PANIC\n"); +} + +handler_t exc_table[EXCCAUSE_LAST] = { + [0 ... EXCCAUSE_LAST-1] = unhandled_exception, +}; + +int interrupt_init(void) +{ + return 0; +} + +void enable_interrupts(void) +{ +} + +int disable_interrupts(void) +{ + return 0; +} diff --git a/arch/xtensa/cpu/start.S b/arch/xtensa/cpu/start.S new file mode 100644 index 00000000000..8e4bc99e429 --- /dev/null +++ b/arch/xtensa/cpu/start.S @@ -0,0 +1,677 @@ +/* + * (C) Copyright 2008 - 2013 Tensilica Inc. + * (C) Copyright 2014 - 2016 Cadence Design Systems Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <asm/asmmacro.h> +#include <asm/cacheasm.h> +#include <asm/regs.h> +#include <asm/arch/tie.h> +#include <asm-offsets.h> + +/* + * Offsets into the the pt_regs struture. + * Make sure these always match with the structure defined in ptrace.h! + */ + +#define PT_PC 0 +#define PT_PS 4 +#define PT_DEPC 8 +#define PT_EXCCAUSE 12 +#define PT_EXCVADDR 16 +#define PT_DEBUGCAUSE 20 +#define PT_WMASK 24 +#define PT_LBEG 28 +#define PT_LEND 32 +#define PT_LCOUNT 36 +#define PT_SAR 40 +#define PT_WINDOWBASE 44 +#define PT_WINDOWSTART 48 +#define PT_SYSCALL 52 +#define PT_ICOUNTLEVEL 56 +#define PT_RESERVED 60 +#define PT_AREG 64 +#define PT_SIZE (64 + 64) + +/* + * Cache attributes are different for full MMU and region protection. + */ + +#if XCHAL_HAVE_PTP_MMU +#define CA_WRITEBACK (0x7) +#else +#define CA_WRITEBACK (0x4) +#endif + +/* + * Reset vector. + * Only a trampoline to jump to _start + * (Note that we have to mark the section writable as the section contains + * a relocatable literal) + */ + + .section .ResetVector.text, "awx" + .global _ResetVector +_ResetVector: + + j 1f + .align 4 +2: .long _start +1: l32r a2, 2b + jx a2 + + +/* + * Processor initialization. We still run in rom space. + * + * NOTE: Running in ROM + * For Xtensa, we currently don't allow to run some code from ROM but + * unpack the data immediately to memory. This requires, for example, + * that DDR has been set up before running U-Boot. (See also comments + * inline for ways to change it) + */ + + .section .reset.text, "ax" + .global _start + .align 4 +_start: + /* Keep a0 = 0 for various initializations */ + + movi a0, 0 + + /* + * For full MMU cores, put page table at unmapped virtual address. + * This ensures that accesses outside the static maps result + * in miss exceptions rather than random behaviour. + */ + +#if XCHAL_HAVE_PTP_MMU + wsr a0, PTEVADDR +#endif + + /* Disable dbreak debug exceptions */ + +#if XCHAL_HAVE_DEBUG && XCHAL_NUM_DBREAK > 0 + .set _index, 0 + .rept XCHAL_NUM_DBREAK + wsr a0, DBREAKC + _index + .set _index, _index + 1 + .endr +#endif + + /* Reset windowbase and windowstart */ + +#if XCHAL_HAVE_WINDOWED + movi a3, 1 + wsr a3, windowstart + wsr a0, windowbase + rsync + movi a0, 0 /* windowbase might have changed */ +#endif + + /* + * Vecbase in bitstream may differ from header files + * set or check it. + */ + +#if XCHAL_HAVE_VECBASE + movi a3, XCHAL_VECBASE_RESET_VADDR /* VECBASE reset value */ + wsr a3, VECBASE +#endif + +#if XCHAL_HAVE_LOOPS + /* Disable loops */ + + wsr a0, LCOUNT +#endif + + /* Set PS.WOE = 0, PS.EXCM = 0 (for loop), PS.INTLEVEL = EXCM level */ + +#if XCHAL_HAVE_XEA1 + movi a2, 1 +#else + movi a2, XCHAL_EXCM_LEVEL +#endif + wsr a2, PS + rsync + + /* Unlock and invalidate caches */ + + ___unlock_dcache_all a2, a3 + ___invalidate_dcache_all a2, a3 + ___unlock_icache_all a2, a3 + ___invalidate_icache_all a2, a3 + + isync + + /* Unpack data sections */ + + movi a2, __reloc_table_start + movi a3, __reloc_table_end + +1: beq a2, a3, 3f # no more entries? + l32i a4, a2, 0 # start destination (in RAM) + l32i a5, a2, 4 # end destination (in RAM) + l32i a6, a2, 8 # start source (in ROM) + addi a2, a2, 12 # next entry + beq a4, a5, 1b # skip, empty entry + beq a4, a6, 1b # skip, source and destination are the same + + /* If there's memory protection option with 512MB TLB regions and + * cache attributes in TLB entries and caching is not inhibited, + * enable data/instruction cache for relocated image. + */ +#if XCHAL_HAVE_SPANNING_WAY && \ + (!defined(CONFIG_SYS_DCACHE_OFF) || \ + !defined(CONFIG_SYS_ICACHE_OFF)) + srli a7, a4, 29 + slli a7, a7, 29 + addi a7, a7, XCHAL_SPANNING_WAY +#ifndef CONFIG_SYS_DCACHE_OFF + rdtlb1 a8, a7 + srli a8, a8, 4 + slli a8, a8, 4 + addi a8, a8, CA_WRITEBACK + wdtlb a8, a7 +#endif +#ifndef CONFIG_SYS_ICACHE_OFF + ritlb1 a8, a7 + srli a8, a8, 4 + slli a8, a8, 4 + addi a8, a8, CA_WRITEBACK + witlb a8, a7 +#endif + isync +#endif + +2: l32i a7, a6, 0 + addi a6, a6, 4 + s32i a7, a4, 0 + addi a4, a4, 4 + bltu a4, a5, 2b + j 1b + +3: /* All code and initalized data segments have been copied */ + + /* Setup PS, PS.WOE = 1, PS.EXCM = 0, PS.INTLEVEL = EXCM level. */ + +#if __XTENSA_CALL0_ABI__ + movi a2, XCHAL_EXCM_LEVEL +#else + movi a2, (1<<PS_WOE_BIT) | XCHAL_EXCM_LEVEL +#endif + wsr a2, PS + rsync + + /* Writeback */ + + ___flush_dcache_all a2, a3 + +#ifdef __XTENSA_WINDOWED_ABI__ + /* + * In windowed ABI caller and call target need to be within the same + * gigabyte. Put the rest of the code into the text segment and jump + * there. + */ + + movi a4, .Lboard_init_code + jx a4 + + .text + .align 4 +.Lboard_init_code: +#endif + + movi a0, 0 + movi sp, (CONFIG_SYS_TEXT_ADDR - 16) & 0xfffffff0 + +#ifdef CONFIG_DEBUG_UART + movi a4, debug_uart_init +#ifdef __XTENSA_CALL0_ABI__ + callx0 a4 +#else + callx4 a4 +#endif +#endif + + movi a4, board_init_f_alloc_reserve + +#ifdef __XTENSA_CALL0_ABI__ + mov a2, sp + callx0 a4 + mov sp, a2 +#else + mov a6, sp + callx4 a4 + movsp sp, a6 +#endif + + movi a4, board_init_f_init_reserve + +#ifdef __XTENSA_CALL0_ABI__ + callx0 a4 +#else + callx4 a4 +#endif + + /* + * Call board initialization routine (never returns). + */ + + movi a4, board_init_f + +#ifdef __XTENSA_CALL0_ABI__ + movi a2, 0 + callx0 a4 +#else + movi a6, 0 + callx4 a4 +#endif + /* Never Returns */ + ill + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * a2 = addr_sp + * a3 = gd + * a4 = destination address + */ + .text + .globl relocate_code + .align 4 +relocate_code: + abi_entry + +#ifdef __XTENSA_CALL0_ABI__ + mov a1, a2 + mov a2, a3 + mov a3, a4 + movi a0, board_init_r + callx0 a0 +#else + /* We can't movsp here, because the chain of stack frames may cross + * the now reserved memory. We need to toss all window frames except + * the current, create new pristine stack frame and start from scratch. + */ + rsr a0, windowbase + ssl a0 + movi a0, 1 + sll a0, a0 + wsr a0, windowstart + rsync + + movi a0, 0 + + /* Reserve 16-byte save area */ + addi sp, a2, -16 + mov a6, a3 + mov a7, a4 + movi a4, board_init_r + callx4 a4 +#endif + ill + +#if XCHAL_HAVE_EXCEPTIONS + +/* + * Exception vectors. + * + * Various notes: + * - We currently don't use the user exception vector (PS.UM is always 0), + * but do define such a vector, just in case. They both jump to the + * same exception handler, though. + * - We currently only save the bare minimum number of registers: + * a0...a15, sar, loop-registers, exception register (epc1, excvaddr, + * exccause, depc) + * - WINDOWSTART is only saved to identify if registers have been spilled + * to the wrong stack (exception stack) while executing the exception + * handler. + */ + + .section .KernelExceptionVector.text, "ax" + .global _KernelExceptionVector +_KernelExceptionVector: + + wsr a2, EXCSAVE1 + movi a2, ExceptionHandler + jx a2 + + .section .UserExceptionVector.text, "ax" + .global _UserExceptionVector +_UserExceptionVector: + + wsr a2, EXCSAVE1 + movi a2, ExceptionHandler + jx a2 + +#if !XCHAL_HAVE_XEA1 + .section .DoubleExceptionVector.text, "ax" + .global _DoubleExceptionVector +_DoubleExceptionVector: + +#ifdef __XTENSA_CALL0_ABI__ + wsr a0, EXCSAVE1 + movi a0, hang # report and ask user to reset board + callx0 a0 +#else + wsr a4, EXCSAVE1 + movi a4, hang # report and ask user to reset board + callx4 a4 +#endif +#endif + /* Does not return here */ + + + .text + .align 4 +ExceptionHandler: + + rsr a2, EXCCAUSE # find handler + +#if XCHAL_HAVE_WINDOWED + /* Special case for alloca handler */ + + bnei a2, 5, 1f # jump if not alloca exception + + addi a1, a1, -16 - 4 # create a small stack frame + s32i a3, a1, 0 # and save a3 (a2 still in excsave1) + movi a2, fast_alloca_exception + jx a2 # jump to fast_alloca_exception +#endif + /* All other exceptions go here: */ + + /* Create ptrace stack and save a0...a3 */ + +1: addi a2, a1, - PT_SIZE - 16 + s32i a0, a2, PT_AREG + 0 * 4 + s32i a1, a2, PT_AREG + 1 * 4 + s32i a3, a2, PT_AREG + 3 * 4 + rsr a3, EXCSAVE1 + s32i a3, a2, PT_AREG + 2 * 4 + mov a1, a2 + + /* Save remaining AR registers */ + + s32i a4, a1, PT_AREG + 4 * 4 + s32i a5, a1, PT_AREG + 5 * 4 + s32i a6, a1, PT_AREG + 6 * 4 + s32i a7, a1, PT_AREG + 7 * 4 + s32i a8, a1, PT_AREG + 8 * 4 + s32i a9, a1, PT_AREG + 9 * 4 + s32i a10, a1, PT_AREG + 10 * 4 + s32i a11, a1, PT_AREG + 11 * 4 + s32i a12, a1, PT_AREG + 12 * 4 + s32i a13, a1, PT_AREG + 13 * 4 + s32i a14, a1, PT_AREG + 14 * 4 + s32i a15, a1, PT_AREG + 15 * 4 + + /* Save SRs */ + +#if XCHAL_HAVE_WINDOWED + rsr a2, WINDOWSTART + s32i a2, a1, PT_WINDOWSTART +#endif + + rsr a2, SAR + rsr a3, EPC1 + rsr a4, EXCVADDR + s32i a2, a1, PT_SAR + s32i a3, a1, PT_PC + s32i a4, a1, PT_EXCVADDR + +#if XCHAL_HAVE_LOOPS + movi a2, 0 + rsr a3, LBEG + xsr a2, LCOUNT + s32i a3, a1, PT_LBEG + rsr a3, LEND + s32i a2, a1, PT_LCOUNT + s32i a3, a1, PT_LEND +#endif + + /* Set up C environment and call registered handler */ + /* Setup stack, PS.WOE = 1, PS.EXCM = 0, PS.INTLEVEL = EXCM level. */ + + rsr a2, EXCCAUSE +#if XCHAL_HAVE_XEA1 + movi a3, (1<<PS_WOE_BIT) | 1 +#elif __XTENSA_CALL0_ABI__ + movi a3, XCHAL_EXCM_LEVEL +#else + movi a3, (1<<PS_WOE_BIT) | XCHAL_EXCM_LEVEL +#endif + xsr a3, PS + rsync + s32i a2, a1, PT_EXCCAUSE + s32i a3, a1, PT_PS + + movi a0, exc_table + addx4 a0, a2, a0 + l32i a0, a0, 0 +#ifdef __XTENSA_CALL0_ABI__ + mov a2, a1 # Provide stack frame as only argument + callx0 a0 + l32i a3, a1, PT_PS +#else + mov a6, a1 # Provide stack frame as only argument + callx4 a0 +#endif + + /* Restore PS and go to exception mode (PS.EXCM=1) */ + + wsr a3, PS + + /* Restore SR registers */ + +#if XCHAL_HAVE_LOOPS + l32i a2, a1, PT_LBEG + l32i a3, a1, PT_LEND + l32i a4, a1, PT_LCOUNT + wsr a2, LBEG + wsr a3, LEND + wsr a4, LCOUNT +#endif + + l32i a2, a1, PT_SAR + l32i a3, a1, PT_PC + wsr a2, SAR + wsr a3, EPC1 + +#if XCHAL_HAVE_WINDOWED + /* Do we need to simulate a MOVSP? */ + + l32i a2, a1, PT_WINDOWSTART + addi a3, a2, -1 + and a2, a2, a3 + beqz a2, 1f # Skip if regs were spilled before exc. + + rsr a2, WINDOWSTART + addi a3, a2, -1 + and a2, a2, a3 + bnez a2, 1f # Skip if registers aren't spilled now + + addi a2, a1, -16 + l32i a4, a2, 0 + l32i a5, a2, 4 + s32i a4, a1, PT_SIZE + 0 + s32i a5, a1, PT_SIZE + 4 + l32i a4, a2, 8 + l32i a5, a2, 12 + s32i a4, a1, PT_SIZE + 8 + s32i a5, a1, PT_SIZE + 12 +#endif + + /* Restore address register */ + +1: l32i a15, a1, PT_AREG + 15 * 4 + l32i a14, a1, PT_AREG + 14 * 4 + l32i a13, a1, PT_AREG + 13 * 4 + l32i a12, a1, PT_AREG + 12 * 4 + l32i a11, a1, PT_AREG + 11 * 4 + l32i a10, a1, PT_AREG + 10 * 4 + l32i a9, a1, PT_AREG + 9 * 4 + l32i a8, a1, PT_AREG + 8 * 4 + l32i a7, a1, PT_AREG + 7 * 4 + l32i a6, a1, PT_AREG + 6 * 4 + l32i a5, a1, PT_AREG + 5 * 4 + l32i a4, a1, PT_AREG + 4 * 4 + l32i a3, a1, PT_AREG + 3 * 4 + l32i a2, a1, PT_AREG + 2 * 4 + l32i a0, a1, PT_AREG + 0 * 4 + + l32i a1, a1, PT_AREG + 1 * 4 # Remove ptrace stack frame + + rfe + +#endif /* XCHAL_HAVE_EXCEPTIONS */ + +#if XCHAL_HAVE_WINDOWED + +/* + * Window overflow and underflow handlers. + * The handlers must be 64 bytes apart, first starting with the underflow + * handlers underflow-4 to underflow-12, then the overflow handlers + * overflow-4 to overflow-12. + * + * Note: We rerun the underflow handlers if we hit an exception, so + * we try to access any page that would cause a page fault early. + */ + + .section .WindowVectors.text, "ax" + +/* 4-Register Window Overflow Vector (Handler) */ + + .align 64 +.global _WindowOverflow4 +_WindowOverflow4: + s32e a0, a5, -16 + s32e a1, a5, -12 + s32e a2, a5, -8 + s32e a3, a5, -4 + rfwo + + +/* 4-Register Window Underflow Vector (Handler) */ + + .align 64 +.global _WindowUnderflow4 +_WindowUnderflow4: + l32e a0, a5, -16 + l32e a1, a5, -12 + l32e a2, a5, -8 + l32e a3, a5, -4 + rfwu + +/* + * a0: a0 + * a1: new stack pointer = a1 - 16 - 4 + * a2: available, saved in excsave1 + * a3: available, saved on stack *a1 + */ + +/* 15*/ .byte 0xff + +fast_alloca_exception: /* must be at _WindowUnderflow4 + 16 */ + +/* 16*/ rsr a2, PS +/* 19*/ rsr a3, WINDOWBASE +/* 22*/ extui a2, a2, PS_OWB_SHIFT, PS_OWB_SHIFT +/* 25*/ xor a2, a2, a3 +/* 28*/ rsr a3, PS +/* 31*/ slli a2, a2, PS_OWB_SHIFT +/* 34*/ xor a2, a3, a2 +/* 37*/ wsr a2, PS + +/* 40*/ _l32i a3, a1, 0 +/* 43*/ addi a1, a1, 16 + 4 +/* 46*/ rsr a2, EXCSAVE1 + +/* 49*/ rotw -1 +/* 52*/ _bbci.l a4, 31, _WindowUnderflow4 /* 0x: call4 */ +/* 55*/ rotw -1 +/* 58*/ _bbci.l a8, 30, _WindowUnderflow8 /* 10: call8 */ +/* 61*/ _j __WindowUnderflow12 /* 11: call12 */ +/* 64*/ + +/* 8-Register Window Overflow Vector (Handler) */ + + .align 64 +.global _WindowOverflow8 +_WindowOverflow8: + s32e a0, a9, -16 + l32e a0, a1, -12 + s32e a2, a9, -8 + s32e a1, a9, -12 + s32e a3, a9, -4 + s32e a4, a0, -32 + s32e a5, a0, -28 + s32e a6, a0, -24 + s32e a7, a0, -20 + rfwo + +/* 8-Register Window Underflow Vector (Handler) */ + + .align 64 +.global _WindowUnderflow8 +_WindowUnderflow8: + l32e a1, a9, -12 + l32e a0, a9, -16 + l32e a7, a1, -12 + l32e a2, a9, -8 + l32e a4, a7, -32 + l32e a3, a9, -4 + l32e a5, a7, -28 + l32e a6, a7, -24 + l32e a7, a7, -20 + rfwu + +/* 12-Register Window Overflow Vector (Handler) */ + + .align 64 +.global _WindowOverflow12 +_WindowOverflow12: + s32e a0, a13, -16 + l32e a0, a1, -12 + s32e a1, a13, -12 + s32e a2, a13, -8 + s32e a3, a13, -4 + s32e a4, a0, -48 + s32e a5, a0, -44 + s32e a6, a0, -40 + s32e a7, a0, -36 + s32e a8, a0, -32 + s32e a9, a0, -28 + s32e a10, a0, -24 + s32e a11, a0, -20 + rfwo + +/* 12-Register Window Underflow Vector (Handler) */ + + .org _WindowOverflow12 + 64 - 3 +__WindowUnderflow12: + rotw -1 +.global _WindowUnderflow12 +_WindowUnderflow12: + l32e a1, a13, -12 + l32e a0, a13, -16 + l32e a11, a1, -12 + l32e a2, a13, -8 + l32e a4, a11, -48 + l32e a8, a11, -32 + l32e a3, a13, -4 + l32e a5, a11, -44 + l32e a6, a11, -40 + l32e a7, a11, -36 + l32e a9, a11, -28 + l32e a10, a11, -24 + l32e a11, a11, -20 + rfwu + +#endif /* XCHAL_HAVE_WINDOWED */ diff --git a/arch/xtensa/cpu/u-boot.lds b/arch/xtensa/cpu/u-boot.lds new file mode 100644 index 00000000000..853ae5a9489 --- /dev/null +++ b/arch/xtensa/cpu/u-boot.lds @@ -0,0 +1,116 @@ +/* + * (C) Copyright 2008 - 2013 Tensilica, Inc. + * (C) Copyright 2014 - 2016 Cadence Design Systems Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <asm/ldscript.h> +#include <asm/arch/core.h> +#include <asm/addrspace.h> +#include <asm-offsets.h> + +OUTPUT_ARCH(xtensa) +ENTRY(_start) + +/* + * U-Boot resets from SYSROM and unpacks itself from a ROM store to RAM. + * The reset vector is usually near the base of SYSROM and has room + * above it for the ROM store into which the rest of U-Boot is packed. + * The ROM store also needs to be above any other vectors that are in ROM. + * If a core has its vectors near the top of ROM, this must be edited. + * + * Note that to run C code out of ROM, the processor would have to support + * 'relocatable' exception vectors and provide a scratch memory for the + * initial stack. Not all Xtensa processor configurations support that, so + * we can simplify the boot process and unpack U-Boot to RAM immediately. + * This, however, requires that memory have been initialized throug some + * other means (serial ROM, for example) or are initialized early (requiring + * an assembler function. See start.S for more details) + */ + +SECTIONS +{ + . = + SIZEOF_HEADERS; + SECTION_ResetVector(XCHAL_RESET_VECTOR_VADDR, LMA_EQ_VMA) + + .reloc_table ALIGN(4) : FOLLOWING(.ResetVector.text) + { + __reloc_table_start = ABSOLUTE(.); +#if XCHAL_HAVE_WINDOWED + RELOCATE2(WindowVectors,text); +#endif + RELOCATE2(KernelExceptionVector,literal); + RELOCATE2(KernelExceptionVector,text); + RELOCATE2(UserExceptionVector,literal); + RELOCATE2(UserExceptionVector,text); + RELOCATE2(DoubleExceptionVector,literal); + RELOCATE2(DoubleExceptionVector,text); + RELOCATE1(text); + RELOCATE1(rodata); + RELOCATE1(data); + RELOCATE1(u_boot_list); + __reloc_table_end = ABSOLUTE(.); + } + +#if XCHAL_HAVE_WINDOWED + SECTION_VECTOR(WindowVectors,text,XCHAL_WINDOW_VECTORS_VADDR, + FOLLOWING(.reloc_table)) + SECTION_VECTOR(KernelExceptionVector,literal,XCHAL_KERNEL_VECTOR_VADDR-8, + FOLLOWING(.WindowVectors.text)) +#else + SECTION_VECTOR(KernelExceptionVector,literal,XCHAL_KERNEL_VECTOR_VADDR-8, + FOLLOWING(.reloc_table)) +#endif + SECTION_VECTOR(KernelExceptionVector,text,XCHAL_KERNEL_VECTOR_VADDR, + FOLLOWING(.KernelExceptionVector.literal)) + SECTION_VECTOR(UserExceptionVector,literal,XCHAL_USER_VECTOR_VADDR-8, + FOLLOWING(.KernelExceptionVector.text)) + SECTION_VECTOR(UserExceptionVector,text,XCHAL_USER_VECTOR_VADDR, + FOLLOWING(.UserExceptionVector.literal)) + SECTION_VECTOR(DoubleExceptionVector,literal,XCHAL_DOUBLEEXC_VECTOR_VADDR-8, + FOLLOWING(.UserExceptionVector.text)) + SECTION_VECTOR(DoubleExceptionVector,text,XCHAL_DOUBLEEXC_VECTOR_VADDR, + FOLLOWING(.DoubleExceptionVector.literal)) + + __monitor_start = CONFIG_SYS_TEXT_ADDR; + + SECTION_text(CONFIG_SYS_TEXT_ADDR, FOLLOWING(.DoubleExceptionVector.text)) + SECTION_rodata(ALIGN(16), FOLLOWING(.text)) + SECTION_u_boot_list(ALIGN(16), FOLLOWING(.rodata)) + SECTION_data(ALIGN(16), FOLLOWING(.u_boot_list)) + + __reloc_end = .; + __init_end = .; + + SECTION_bss(__init_end (OVERLAY),) + + __monitor_end = .; + + /* + * On many Xtensa boards a region of RAM may be mapped to the ROM address + * space to facilitate on-chip-debug, and U-Boot must fit with that region. + * The config variables CONFIG_SYS_MONITOR_* define the region. + * If U-Boot extends beyond this region it will appear discontiguous in the + * address space and is in danger of overwriting itself during unpacking + * ("relocation"). + * This causes U-Boot to crash in a way that is difficult to debug. On some + * boards (such as xtav60) the region is small enough that U-Boot will not + * fit if compiled entirely with -O0 (a common scenario). To avoid a lengthy + * debugging session when this happens, ensure a link-time error occurs. + * + */ + + ASSERT(__monitor_end - __monitor_start <= CONFIG_SYS_MONITOR_LEN, + "U-Boot ROM image is too large. Check optimization level.") + + SECTION_xtensa + SECTION_debug + + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.hash*) } + /DISCARD/ : { *(.interp) } + /DISCARD/ : { *(.got*) } + /DISCARD/ : { *(.dynsym) } +} diff --git a/arch/xtensa/dts/Makefile b/arch/xtensa/dts/Makefile new file mode 100644 index 00000000000..e14cdac0fc1 --- /dev/null +++ b/arch/xtensa/dts/Makefile @@ -0,0 +1,15 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +dtb-$(CONFIG_XTFPGA) += ml605.dtb ml605_nommu.dtb kc705.dtb kc705_nommu.dtb + +targets += $(dtb-y) + +DTC_FLAGS += + +PHONY += dtbs +dtbs: $(addprefix $(obj)/, $(dtb-y)) + @: + +clean-files := *.dtb diff --git a/arch/xtensa/dts/include/dt-bindings b/arch/xtensa/dts/include/dt-bindings new file mode 120000 index 00000000000..0cecb3d0805 --- /dev/null +++ b/arch/xtensa/dts/include/dt-bindings @@ -0,0 +1 @@ +../../../../include/dt-bindings
\ No newline at end of file diff --git a/arch/xtensa/dts/kc705.dts b/arch/xtensa/dts/kc705.dts new file mode 100644 index 00000000000..3b89e83b30e --- /dev/null +++ b/arch/xtensa/dts/kc705.dts @@ -0,0 +1,15 @@ +/dts-v1/; +/include/ "xtfpga.dtsi" +/include/ "xtfpga-flash-128m.dtsi" + +/ { + compatible = "cdns,xtensa-kc705"; + chosen { + bootargs = "earlycon=uart8250,mmio32native,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug"; + stdout-path = &serial0; + }; + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x38000000>; + }; +}; diff --git a/arch/xtensa/dts/kc705_nommu.dts b/arch/xtensa/dts/kc705_nommu.dts new file mode 100644 index 00000000000..57f0dab87cf --- /dev/null +++ b/arch/xtensa/dts/kc705_nommu.dts @@ -0,0 +1,17 @@ +/dts-v1/; +/include/ "xtfpga.dtsi" +/include/ "xtfpga-flash-128m.dtsi" + +/ { + compatible = "cdns,xtensa-kc705"; + chosen { + bootargs = "earlycon=uart8250,mmio32native,0x9d050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug"; + }; + memory@0 { + device_type = "memory"; + reg = <0x60000000 0x10000000>; + }; + soc { + ranges = <0x00000000 0x90000000 0x10000000>; + }; +}; diff --git a/arch/xtensa/dts/ml605.dts b/arch/xtensa/dts/ml605.dts new file mode 100644 index 00000000000..f323f96f986 --- /dev/null +++ b/arch/xtensa/dts/ml605.dts @@ -0,0 +1,15 @@ +/dts-v1/; +/include/ "xtfpga.dtsi" +/include/ "xtfpga-flash-16m.dtsi" + +/ { + compatible = "cdns,xtensa-ml605"; + chosen { + bootargs = "earlycon=uart8250,mmio32native,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug"; + stdout-path = &serial0; + }; + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x18000000>; + }; +}; diff --git a/arch/xtensa/dts/ml605_nommu.dts b/arch/xtensa/dts/ml605_nommu.dts new file mode 100644 index 00000000000..6bdf40055bb --- /dev/null +++ b/arch/xtensa/dts/ml605_nommu.dts @@ -0,0 +1,18 @@ +/dts-v1/; +/include/ "xtfpga.dtsi" +/include/ "xtfpga-flash-16m.dtsi" + +/ { + compatible = "cdns,xtensa-ml605"; + chosen { + bootargs = "earlycon=uart8250,mmio32native,0x9d050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug"; + stdout-path = &serial0; + }; + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + soc { + ranges = <0x00000000 0x90000000 0x10000000>; + }; +}; diff --git a/arch/xtensa/dts/xtfpga-flash-128m.dtsi b/arch/xtensa/dts/xtfpga-flash-128m.dtsi new file mode 100644 index 00000000000..d3a88e02987 --- /dev/null +++ b/arch/xtensa/dts/xtfpga-flash-128m.dtsi @@ -0,0 +1,28 @@ +/ { + soc { + flash: flash@00000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x00000000 0x08000000>; + bank-width = <2>; + device-width = <2>; + partition@0x0 { + label = "data"; + reg = <0x00000000 0x06000000>; + }; + partition@0x6000000 { + label = "boot loader area"; + reg = <0x06000000 0x00800000>; + }; + partition@0x6800000 { + label = "kernel image"; + reg = <0x06800000 0x017e0000>; + }; + partition@0x7fe0000 { + label = "boot environment"; + reg = <0x07fe0000 0x00020000>; + }; + }; + }; +}; diff --git a/arch/xtensa/dts/xtfpga-flash-16m.dtsi b/arch/xtensa/dts/xtfpga-flash-16m.dtsi new file mode 100644 index 00000000000..1d97203c18e --- /dev/null +++ b/arch/xtensa/dts/xtfpga-flash-16m.dtsi @@ -0,0 +1,28 @@ +/ { + soc { + flash: flash@08000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x08000000 0x01000000>; + bank-width = <2>; + device-width = <2>; + partition@0x0 { + label = "boot loader area"; + reg = <0x00000000 0x00400000>; + }; + partition@0x400000 { + label = "kernel image"; + reg = <0x00400000 0x00600000>; + }; + partition@0xa00000 { + label = "data"; + reg = <0x00a00000 0x005e0000>; + }; + partition@0xfe0000 { + label = "boot environment"; + reg = <0x00fe0000 0x00020000>; + }; + }; + }; +}; diff --git a/arch/xtensa/dts/xtfpga.dtsi b/arch/xtensa/dts/xtfpga.dtsi new file mode 100644 index 00000000000..cd45f9c2c44 --- /dev/null +++ b/arch/xtensa/dts/xtfpga.dtsi @@ -0,0 +1,137 @@ +/ { + compatible = "cdns,xtensa-xtfpga"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&pic>; + + chosen { + bootargs = "earlycon=uart8250,mmio32native,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x00000000 0x06000000>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + compatible = "cdns,xtensa-cpu"; + reg = <0>; + /* Filled in by platform_setup from FPGA register + * clock-frequency = <100000000>; + */ + }; + }; + + pic: pic { + compatible = "cdns,xtensa-pic"; + /* one cell: internal irq number, + * two cells: second cell == 0: internal irq number + * second cell == 1: external irq number + */ + #interrupt-cells = <2>; + interrupt-controller; + }; + + clocks { + osc: main-oscillator { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + clk54: clk54 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <54000000>; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x00000000 0xf0000000 0x10000000>; + + serial0: serial@0d050020 { + device_type = "serial"; + compatible = "ns16550a"; + no-loopback-test; + reg = <0x0d050020 0x20>; + reg-shift = <2>; + reg-io-width = <4>; + native-endian; + interrupts = <0 1>; /* external irq 0 */ + clocks = <&osc>; + }; + + enet0: ethoc@0d030000 { + compatible = "opencores,ethoc"; + reg = <0x0d030000 0x4000 0x0d800000 0x4000>; + native-endian; + interrupts = <1 1>; /* external irq 1 */ + local-mac-address = [00 50 c2 13 6f 00]; + clocks = <&osc>; + }; + + i2s0: xtfpga-i2s@0d080000 { + #sound-dai-cells = <0>; + compatible = "cdns,xtfpga-i2s"; + reg = <0x0d080000 0x40>; + interrupts = <2 1>; /* external irq 2 */ + clocks = <&cdce706 4>; + }; + + i2c0: i2c-master@0d090000 { + compatible = "opencores,i2c-ocores"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0d090000 0x20>; + reg-shift = <2>; + reg-io-width = <4>; + native-endian; + interrupts = <4 1>; + clocks = <&osc>; + + cdce706: clock-synth@69 { + compatible = "ti,cdce706"; + #clock-cells = <1>; + reg = <0x69>; + clocks = <&clk54>; + clock-names = "clk_in0"; + }; + }; + + spi0: spi-master@0d0a0000 { + compatible = "cdns,xtfpga-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0d0a0000 0xc>; + + tlv320aic23: sound-codec@0 { + #sound-dai-cells = <0>; + compatible = "tlv320aic23"; + reg = <0>; + spi-max-frequency = <12500000>; + }; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&i2s0>; + }; + + simple-audio-card,codec { + sound-dai = <&tlv320aic23>; + simple-audio-card,bitclock-master = <0>; + simple-audio-card,frame-master = <0>; + clocks = <&cdce706 4>; + }; + }; +}; diff --git a/arch/xtensa/include/asm/addrspace.h b/arch/xtensa/include/asm/addrspace.h new file mode 100644 index 00000000000..1d62259fd5b --- /dev/null +++ b/arch/xtensa/include/asm/addrspace.h @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2008-2013 Tensilica Inc. + * Copyright (C) 2016 Cadence Design Systems Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _XTENSA_ADDRSPACE_H +#define _XTENSA_ADDRSPACE_H + +#include <asm/arch/core.h> + +/* + * MMU Memory Map + * + * noMMU and v3 MMU have identity mapped address space on reset. + * V2 MMU: + * IO (uncached) f0000000..ffffffff -> f000000 + * IO (cached) e0000000..efffffff -> f000000 + * MEM (uncached) d8000000..dfffffff -> 0000000 + * MEM (cached) d0000000..d7ffffff -> 0000000 + * + * The actual location of memory and IO is the board property. + */ + +#define IOADDR(x) (CONFIG_SYS_IO_BASE + (x)) +#define MEMADDR(x) (CONFIG_SYS_MEMORY_BASE + (x)) +#define PHYSADDR(x) ((x) - XCHAL_VECBASE_RESET_VADDR + \ + XCHAL_VECBASE_RESET_PADDR) + +#endif /* _XTENSA_ADDRSPACE_H */ diff --git a/arch/xtensa/include/asm/arch-dc232b/core.h b/arch/xtensa/include/asm/arch-dc232b/core.h new file mode 100644 index 00000000000..548c971f266 --- /dev/null +++ b/arch/xtensa/include/asm/arch-dc232b/core.h @@ -0,0 +1,423 @@ +/* + * Xtensa processor core configuration information. + * This file is autogenerated, please do not edit. + * + * Copyright (C) 1999-2007 Tensilica Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _XTENSA_CORE_CONFIGURATION_H +#define _XTENSA_CORE_CONFIGURATION_H + + +/**************************************************************************** + Parameters Useful for Any Code, USER or PRIVILEGED + ****************************************************************************/ + +/* + * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is + * configured, and a value of 0 otherwise. These macros are always defined. + */ + + +/*---------------------------------------------------------------------- + ISA + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ +#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ +#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */ +#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */ +#define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */ +#define XCHAL_HAVE_DEBUG 1 /* debug option */ +#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ +#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ +#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ +#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ +#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ +#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ +#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ +#define XCHAL_HAVE_MUL32 1 /* MULL instruction */ +#define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */ +#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */ +#define XCHAL_HAVE_L32R 1 /* L32R instruction */ +#define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */ +#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ +#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ +#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ +#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ +#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ +#define XCHAL_HAVE_ABS 1 /* ABS instruction */ +/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */ +/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */ +#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ +#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ +#define XCHAL_HAVE_SPECULATION 0 /* speculation */ +#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ +#define XCHAL_NUM_CONTEXTS 1 /* */ +#define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */ +#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ +#define XCHAL_HAVE_PRID 1 /* processor ID register */ +#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */ +#define XCHAL_HAVE_BOOLEANS 0 /* boolean registers */ +#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ +#define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */ +#define XCHAL_HAVE_MAC16 1 /* MAC16 package */ +#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */ +#define XCHAL_HAVE_FP 0 /* floating point pkg */ +#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ +#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ +#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ + + +/*---------------------------------------------------------------------- + MISC + ----------------------------------------------------------------------*/ + +#define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */ +#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */ +#define XCHAL_DATA_WIDTH 4 /* data width in bytes */ +/* In T1050, applies to selected core load and store instructions (see ISA): */ +#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ +#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/ + +#define XCHAL_SW_VERSION 701001 /* sw version of this header */ + +#define XCHAL_CORE_ID "dc232b" /* alphanum core name + (CoreID) set in the Xtensa + Processor Generator */ + +#define XCHAL_CORE_DESCRIPTION "Diamond 232L Standard Core Rev.B (LE)" +#define XCHAL_BUILD_UNIQUE_ID 0x0000BEEF /* 22-bit sw build ID */ + +/* + * These definitions describe the hardware targeted by this software. + */ +#define XCHAL_HW_CONFIGID0 0xC56307FE /* ConfigID hi 32 bits*/ +#define XCHAL_HW_CONFIGID1 0x0D40BEEF /* ConfigID lo 32 bits*/ +#define XCHAL_HW_VERSION_NAME "LX2.1.1" /* full version name */ +#define XCHAL_HW_VERSION_MAJOR 2210 /* major ver# of targeted hw */ +#define XCHAL_HW_VERSION_MINOR 1 /* minor ver# of targeted hw */ +#define XCHAL_HW_VERSION 221001 /* major*100+minor */ +#define XCHAL_HW_REL_LX2 1 +#define XCHAL_HW_REL_LX2_1 1 +#define XCHAL_HW_REL_LX2_1_1 1 +#define XCHAL_HW_CONFIGID_RELIABLE 1 +/* If software targets a *range* of hardware versions, these are the bounds: */ +#define XCHAL_HW_MIN_VERSION_MAJOR 2210 /* major v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION_MINOR 1 /* minor v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION 221001 /* earliest targeted hw */ +#define XCHAL_HW_MAX_VERSION_MAJOR 2210 /* major v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION_MINOR 1 /* minor v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION 221001 /* latest targeted hw */ + + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + +#define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */ +#define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */ +#define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ +#define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ + +#define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */ +#define XCHAL_DCACHE_SIZE 16384 /* D-cache size in bytes or 0 */ + +#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */ + + + + +/**************************************************************************** + Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code + ****************************************************************************/ + + +#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */ + +/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ + +/* Number of cache sets in log2(lines per way): */ +#define XCHAL_ICACHE_SETWIDTH 7 +#define XCHAL_DCACHE_SETWIDTH 7 + +/* Cache set associativity (number of ways): */ +#define XCHAL_ICACHE_WAYS 4 +#define XCHAL_DCACHE_WAYS 4 + +/* Cache features: */ +#define XCHAL_ICACHE_LINE_LOCKABLE 1 +#define XCHAL_DCACHE_LINE_LOCKABLE 1 +#define XCHAL_ICACHE_ECC_PARITY 0 +#define XCHAL_DCACHE_ECC_PARITY 0 + +/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */ +#define XCHAL_CA_BITS 4 + + +/*---------------------------------------------------------------------- + INTERNAL I/D RAM/ROMs and XLMI + ----------------------------------------------------------------------*/ + +#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */ +#define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */ +#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */ +#define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */ +#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ +#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */ + + +/*---------------------------------------------------------------------- + INTERRUPTS and TIMERS + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ +#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ +#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ +#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ +#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ +#define XCHAL_NUM_INTERRUPTS 22 /* number of interrupts */ +#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ +#define XCHAL_NUM_EXTINTERRUPTS 17 /* num of external interrupts */ +#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels + (not including level zero) */ +#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */ + /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ + +/* Masks of interrupts at each interrupt level: */ +#define XCHAL_INTLEVEL1_MASK 0x001F80FF +#define XCHAL_INTLEVEL2_MASK 0x00000100 +#define XCHAL_INTLEVEL3_MASK 0x00200E00 +#define XCHAL_INTLEVEL4_MASK 0x00001000 +#define XCHAL_INTLEVEL5_MASK 0x00002000 +#define XCHAL_INTLEVEL6_MASK 0x00000000 +#define XCHAL_INTLEVEL7_MASK 0x00004000 + +/* Masks of interrupts at each range 1..n of interrupt levels: */ +#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x001F80FF +#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x001F81FF +#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x003F8FFF +#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x003F9FFF +#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x003FBFFF +#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x003FBFFF +#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x003FFFFF + +/* Level of each interrupt: */ +#define XCHAL_INT0_LEVEL 1 +#define XCHAL_INT1_LEVEL 1 +#define XCHAL_INT2_LEVEL 1 +#define XCHAL_INT3_LEVEL 1 +#define XCHAL_INT4_LEVEL 1 +#define XCHAL_INT5_LEVEL 1 +#define XCHAL_INT6_LEVEL 1 +#define XCHAL_INT7_LEVEL 1 +#define XCHAL_INT8_LEVEL 2 +#define XCHAL_INT9_LEVEL 3 +#define XCHAL_INT10_LEVEL 3 +#define XCHAL_INT11_LEVEL 3 +#define XCHAL_INT12_LEVEL 4 +#define XCHAL_INT13_LEVEL 5 +#define XCHAL_INT14_LEVEL 7 +#define XCHAL_INT15_LEVEL 1 +#define XCHAL_INT16_LEVEL 1 +#define XCHAL_INT17_LEVEL 1 +#define XCHAL_INT18_LEVEL 1 +#define XCHAL_INT19_LEVEL 1 +#define XCHAL_INT20_LEVEL 1 +#define XCHAL_INT21_LEVEL 3 +#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */ +#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ +#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with + EXCSAVE/EPS/EPC_n, RFI n) */ + +/* Type of each interrupt: */ +#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI +#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE + +/* Masks of interrupts for each type of interrupt: */ +#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000 +#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000880 +#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x003F8000 +#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000133F +#define XCHAL_INTTYPE_MASK_TIMER 0x00002440 +#define XCHAL_INTTYPE_MASK_NMI 0x00004000 +#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000 + +/* Interrupt numbers assigned to specific interrupt sources: */ +#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */ +#define XCHAL_TIMER1_INTERRUPT 10 /* CCOMPARE1 */ +#define XCHAL_TIMER2_INTERRUPT 13 /* CCOMPARE2 */ +#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED +#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */ + +/* Interrupt numbers for levels at which only one interrupt is configured: */ +#define XCHAL_INTLEVEL2_NUM 8 +#define XCHAL_INTLEVEL4_NUM 12 +#define XCHAL_INTLEVEL5_NUM 13 +#define XCHAL_INTLEVEL7_NUM 14 +/* (There are many interrupts each at level(s) 1, 3.) */ + + +/* + * External interrupt vectors/levels. + * These macros describe how Xtensa processor interrupt numbers + * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) + * map to external BInterrupt<n> pins, for those interrupts + * configured as external (level-triggered, edge-triggered, or NMI). + * See the Xtensa processor databook for more details. + */ + +/* Core interrupt numbers mapped to each EXTERNAL interrupt number: */ +#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */ +#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */ +#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */ +#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */ +#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */ +#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */ +#define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */ +#define XCHAL_EXTINT7_NUM 9 /* (intlevel 3) */ +#define XCHAL_EXTINT8_NUM 12 /* (intlevel 4) */ +#define XCHAL_EXTINT9_NUM 14 /* (intlevel 7) */ +#define XCHAL_EXTINT10_NUM 15 /* (intlevel 1) */ +#define XCHAL_EXTINT11_NUM 16 /* (intlevel 1) */ +#define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */ +#define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */ +#define XCHAL_EXTINT14_NUM 19 /* (intlevel 1) */ +#define XCHAL_EXTINT15_NUM 20 /* (intlevel 1) */ +#define XCHAL_EXTINT16_NUM 21 /* (intlevel 3) */ + + +/*---------------------------------------------------------------------- + EXCEPTIONS and VECTORS + ----------------------------------------------------------------------*/ + +#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture + number: 1 == XEA1 (old) + 2 == XEA2 (new) + 0 == XEAX (extern) */ +#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ +#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ +#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ +#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ +#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ +#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ +#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ +#define XCHAL_VECBASE_RESET_VADDR 0xD0000000 /* VECBASE reset value */ +#define XCHAL_VECBASE_RESET_PADDR 0x00000000 +#define XCHAL_RESET_VECBASE_OVERLAP 0 + +#define XCHAL_RESET_VECTOR0_VADDR 0xFE000000 +#define XCHAL_RESET_VECTOR0_PADDR 0xFE000000 +#define XCHAL_RESET_VECTOR1_VADDR 0xD8000500 +#define XCHAL_RESET_VECTOR1_PADDR 0x00000500 +#define XCHAL_RESET_VECTOR_VADDR 0xFE000000 +#define XCHAL_RESET_VECTOR_PADDR 0xFE000000 +#define XCHAL_USER_VECOFS 0x00000340 +#define XCHAL_USER_VECTOR_VADDR 0xD0000340 +#define XCHAL_USER_VECTOR_PADDR 0x00000340 +#define XCHAL_KERNEL_VECOFS 0x00000300 +#define XCHAL_KERNEL_VECTOR_VADDR 0xD0000300 +#define XCHAL_KERNEL_VECTOR_PADDR 0x00000300 +#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0 +#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0xD00003C0 +#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x000003C0 +#define XCHAL_WINDOW_OF4_VECOFS 0x00000000 +#define XCHAL_WINDOW_UF4_VECOFS 0x00000040 +#define XCHAL_WINDOW_OF8_VECOFS 0x00000080 +#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 +#define XCHAL_WINDOW_OF12_VECOFS 0x00000100 +#define XCHAL_WINDOW_UF12_VECOFS 0x00000140 +#define XCHAL_WINDOW_VECTORS_VADDR 0xD0000000 +#define XCHAL_WINDOW_VECTORS_PADDR 0x00000000 +#define XCHAL_INTLEVEL2_VECOFS 0x00000180 +#define XCHAL_INTLEVEL2_VECTOR_VADDR 0xD0000180 +#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x00000180 +#define XCHAL_INTLEVEL3_VECOFS 0x000001C0 +#define XCHAL_INTLEVEL3_VECTOR_VADDR 0xD00001C0 +#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x000001C0 +#define XCHAL_INTLEVEL4_VECOFS 0x00000200 +#define XCHAL_INTLEVEL4_VECTOR_VADDR 0xD0000200 +#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x00000200 +#define XCHAL_INTLEVEL5_VECOFS 0x00000240 +#define XCHAL_INTLEVEL5_VECTOR_VADDR 0xD0000240 +#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x00000240 +#define XCHAL_INTLEVEL6_VECOFS 0x00000280 +#define XCHAL_INTLEVEL6_VECTOR_VADDR 0xD0000280 +#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x00000280 +#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS +#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR +#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR +#define XCHAL_NMI_VECOFS 0x000002C0 +#define XCHAL_NMI_VECTOR_VADDR 0xD00002C0 +#define XCHAL_NMI_VECTOR_PADDR 0x000002C0 +#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS +#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR +#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR + + +/*---------------------------------------------------------------------- + DEBUG + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ +#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ +#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ +#define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option */ + + +/*---------------------------------------------------------------------- + MMU + ----------------------------------------------------------------------*/ + +/* See core-matmap.h header file for more details. */ + +#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ +#define XCHAL_HAVE_SPANNING_WAY 0 /* one way maps I+D 4GB vaddr */ +#define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */ +#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ +#define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */ +#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ +#define XCHAL_HAVE_PTP_MMU 1 /* full MMU (with page table + [autorefill] and protection) + usable for an MMU-based OS */ +/* If none of the above last 4 are set, it's a custom TLB configuration. */ +#define XCHAL_ITLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */ +#define XCHAL_DTLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */ + +#define XCHAL_MMU_ASID_BITS 8 /* number of bits in ASIDs */ +#define XCHAL_MMU_RINGS 4 /* number of rings (1..4) */ +#define XCHAL_MMU_RING_BITS 2 /* num of bits in RING field */ + +#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ + + +#endif /* _XTENSA_CORE_CONFIGURATION_H */ + diff --git a/arch/xtensa/include/asm/arch-dc232b/tie-asm.h b/arch/xtensa/include/asm/arch-dc232b/tie-asm.h new file mode 100644 index 00000000000..501d885e68f --- /dev/null +++ b/arch/xtensa/include/asm/arch-dc232b/tie-asm.h @@ -0,0 +1,121 @@ +/* + * This header file contains assembly-language definitions (assembly + * macros, etc.) for this specific Xtensa processor's TIE extensions + * and options. It is customized to this Xtensa processor configuration. + * This file is autogenerated, please do not edit. + * + * Copyright (C) 1999-2007 Tensilica Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _XTENSA_CORE_TIE_ASM_H +#define _XTENSA_CORE_TIE_ASM_H + +/* Selection parameter values for save-area save/restore macros: */ +/* Option vs. TIE: */ +#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */ +#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */ +/* Whether used automatically by compiler: */ +#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */ +#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */ +/* ABI handling across function calls: */ +#define XTHAL_SAS_CALR 0x0010 /* caller-saved */ +#define XTHAL_SAS_CALE 0x0020 /* callee-saved */ +#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */ +/* Misc */ +#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */ + + + +/* Macro to save all non-coprocessor (extra) custom TIE and optional state + * (not including zero-overhead loop registers). + * Save area ptr (clobbered): ptr (1 byte aligned) + * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed) + */ + .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL + xchal_sa_start \continue, \ofs + .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~\select + xchal_sa_align \ptr, 0, 1024-8, 4, 4 + rsr \at1, ACCLO // MAC16 accumulator + rsr \at2, ACCHI + s32i \at1, \ptr, .Lxchal_ofs_ + 0 + s32i \at2, \ptr, .Lxchal_ofs_ + 4 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 + .endif + .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select + xchal_sa_align \ptr, 0, 1024-16, 4, 4 + rsr \at1, M0 // MAC16 registers + rsr \at2, M1 + s32i \at1, \ptr, .Lxchal_ofs_ + 0 + s32i \at2, \ptr, .Lxchal_ofs_ + 4 + rsr \at1, M2 + rsr \at2, M3 + s32i \at1, \ptr, .Lxchal_ofs_ + 8 + s32i \at2, \ptr, .Lxchal_ofs_ + 12 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 16 + .endif + .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select + xchal_sa_align \ptr, 0, 1024-4, 4, 4 + rsr \at1, SCOMPARE1 // conditional store option + s32i \at1, \ptr, .Lxchal_ofs_ + 0 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 + .endif + .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select + xchal_sa_align \ptr, 0, 1024-4, 4, 4 + rur \at1, THREADPTR // threadptr option + s32i \at1, \ptr, .Lxchal_ofs_ + 0 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 + .endif + .endm // xchal_ncp_store + +/* Macro to save all non-coprocessor (extra) custom TIE and optional state + * (not including zero-overhead loop registers). + * Save area ptr (clobbered): ptr (1 byte aligned) + * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed) + */ + .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL + xchal_sa_start \continue, \ofs + .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~\select + xchal_sa_align \ptr, 0, 1024-8, 4, 4 + l32i \at1, \ptr, .Lxchal_ofs_ + 0 + l32i \at2, \ptr, .Lxchal_ofs_ + 4 + wsr \at1, ACCLO // MAC16 accumulator + wsr \at2, ACCHI + .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 + .endif + .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select + xchal_sa_align \ptr, 0, 1024-16, 4, 4 + l32i \at1, \ptr, .Lxchal_ofs_ + 0 + l32i \at2, \ptr, .Lxchal_ofs_ + 4 + wsr \at1, M0 // MAC16 registers + wsr \at2, M1 + l32i \at1, \ptr, .Lxchal_ofs_ + 8 + l32i \at2, \ptr, .Lxchal_ofs_ + 12 + wsr \at1, M2 + wsr \at2, M3 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 16 + .endif + .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select + xchal_sa_align \ptr, 0, 1024-4, 4, 4 + l32i \at1, \ptr, .Lxchal_ofs_ + 0 + wsr \at1, SCOMPARE1 // conditional store option + .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 + .endif + .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select + xchal_sa_align \ptr, 0, 1024-4, 4, 4 + l32i \at1, \ptr, .Lxchal_ofs_ + 0 + wur \at1, THREADPTR // threadptr option + .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 + .endif + .endm // xchal_ncp_load + + + +#define XCHAL_NCP_NUM_ATMPS 2 + + +#define XCHAL_SA_NUM_ATMPS 2 + +#endif /*_XTENSA_CORE_TIE_ASM_H*/ + diff --git a/arch/xtensa/include/asm/arch-dc232b/tie.h b/arch/xtensa/include/asm/arch-dc232b/tie.h new file mode 100644 index 00000000000..8479a0137d5 --- /dev/null +++ b/arch/xtensa/include/asm/arch-dc232b/tie.h @@ -0,0 +1,130 @@ +/* + * This header file describes this specific Xtensa processor's TIE extensions + * that extend basic Xtensa core functionality. It is customized to this + * Xtensa processor configuration. + * This file is autogenerated, please do not edit. + * + * Copyright (C) 1999-2007 Tensilica Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _XTENSA_CORE_TIE_H +#define _XTENSA_CORE_TIE_H + +#define XCHAL_CP_NUM 1 /* number of coprocessors */ +#define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */ +#define XCHAL_CP_MASK 0x80 /* bitmask of all CPs by ID */ +#define XCHAL_CP_PORT_MASK 0x80 /* bitmask of only port CPs */ + +/* Basic parameters of each coprocessor: */ +#define XCHAL_CP7_NAME "XTIOP" +#define XCHAL_CP7_IDENT XTIOP +#define XCHAL_CP7_SA_SIZE 0 /* size of state save area */ +#define XCHAL_CP7_SA_ALIGN 1 /* min alignment of save area */ +#define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */ + +/* Filler info for unassigned coprocessors, to simplify arrays etc: */ +#define XCHAL_CP0_SA_SIZE 0 +#define XCHAL_CP0_SA_ALIGN 1 +#define XCHAL_CP1_SA_SIZE 0 +#define XCHAL_CP1_SA_ALIGN 1 +#define XCHAL_CP2_SA_SIZE 0 +#define XCHAL_CP2_SA_ALIGN 1 +#define XCHAL_CP3_SA_SIZE 0 +#define XCHAL_CP3_SA_ALIGN 1 +#define XCHAL_CP4_SA_SIZE 0 +#define XCHAL_CP4_SA_ALIGN 1 +#define XCHAL_CP5_SA_SIZE 0 +#define XCHAL_CP5_SA_ALIGN 1 +#define XCHAL_CP6_SA_SIZE 0 +#define XCHAL_CP6_SA_ALIGN 1 + +/* Save area for non-coprocessor optional and custom (TIE) state: */ +#define XCHAL_NCP_SA_SIZE 32 +#define XCHAL_NCP_SA_ALIGN 4 + +/* Total save area for optional and custom state (NCP + CPn): */ +#define XCHAL_TOTAL_SA_SIZE 32 /* with 16-byte align padding */ +#define XCHAL_TOTAL_SA_ALIGN 4 /* actual minimum alignment */ + +/* + * Detailed contents of save areas. + * NOTE: caller must define the XCHAL_SA_REG macro (not defined here) + * before expanding the XCHAL_xxx_SA_LIST() macros. + * + * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize, + * dbnum,base,regnum,bitsz,gapsz,reset,x...) + * + * s = passed from XCHAL_*_LIST(s), eg. to select how to expand + * ccused = set if used by compiler without special options or code + * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global) + * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg) + * opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg) + * name = lowercase reg name (no quotes) + * galign = group byte alignment (power of 2) (galign >= align) + * align = register byte alignment (power of 2) + * asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz) + * (not including any pad bytes required to galign this or next reg) + * dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>) + * base = reg shortname w/o index (or sr=special, ur=TIE user reg) + * regnum = reg index in regfile, or special/TIE-user reg number + * bitsz = number of significant bits (regfile width, or ur/sr mask bits) + * gapsz = intervening bits, if bitsz bits not stored contiguously + * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize) + * reset = register reset value (or 0 if undefined at reset) + * x = reserved for future use (0 until then) + * + * To filter out certain registers, e.g. to expand only the non-global + * registers used by the compiler, you can do something like this: + * + * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p) + * #define SELCC0(p...) + * #define SELCC1(abikind,p...) SELAK##abikind(p) + * #define SELAK0(p...) REG(p) + * #define SELAK1(p...) REG(p) + * #define SELAK2(p...) + * #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \ + * ...what you want to expand... + */ + +#define XCHAL_NCP_SA_NUM 8 +#define XCHAL_NCP_SA_LIST(s) \ + XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \ + XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \ + XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \ + XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) + +#define XCHAL_CP0_SA_NUM 0 +#define XCHAL_CP0_SA_LIST(s) /* empty */ + +#define XCHAL_CP1_SA_NUM 0 +#define XCHAL_CP1_SA_LIST(s) /* empty */ + +#define XCHAL_CP2_SA_NUM 0 +#define XCHAL_CP2_SA_LIST(s) /* empty */ + +#define XCHAL_CP3_SA_NUM 0 +#define XCHAL_CP3_SA_LIST(s) /* empty */ + +#define XCHAL_CP4_SA_NUM 0 +#define XCHAL_CP4_SA_LIST(s) /* empty */ + +#define XCHAL_CP5_SA_NUM 0 +#define XCHAL_CP5_SA_LIST(s) /* empty */ + +#define XCHAL_CP6_SA_NUM 0 +#define XCHAL_CP6_SA_LIST(s) /* empty */ + +#define XCHAL_CP7_SA_NUM 0 +#define XCHAL_CP7_SA_LIST(s) /* empty */ + +/* Byte length of instruction from its first nibble (op0 field), per FLIX. */ +#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3 + +#endif /*_XTENSA_CORE_TIE_H*/ + diff --git a/arch/xtensa/include/asm/arch-dc233c/core.h b/arch/xtensa/include/asm/arch-dc233c/core.h new file mode 100644 index 00000000000..fd2c0e8d0b5 --- /dev/null +++ b/arch/xtensa/include/asm/arch-dc233c/core.h @@ -0,0 +1,454 @@ +/* + * Xtensa processor core configuration information. + * This file is autogenerated, please do not edit. + * + * Copyright (C) 1999-2010 Tensilica Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _XTENSA_CORE_CONFIGURATION_H +#define _XTENSA_CORE_CONFIGURATION_H + + +/**************************************************************************** + Parameters Useful for Any Code, USER or PRIVILEGED + ****************************************************************************/ + +/* + * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is + * configured, and a value of 0 otherwise. These macros are always defined. + */ + + +/*---------------------------------------------------------------------- + ISA + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ +#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ +#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */ +#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */ +#define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */ +#define XCHAL_HAVE_DEBUG 1 /* debug option */ +#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ +#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ +#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ +#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ +#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ +#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ +#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ +#define XCHAL_HAVE_MUL32 1 /* MULL instruction */ +#define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */ +#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */ +#define XCHAL_HAVE_L32R 1 /* L32R instruction */ +#define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */ +#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ +#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ +#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ +#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ +#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ +#define XCHAL_HAVE_ABS 1 /* ABS instruction */ +/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */ +/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */ +#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ +#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ +#define XCHAL_HAVE_SPECULATION 0 /* speculation */ +#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ +#define XCHAL_NUM_CONTEXTS 1 /* */ +#define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */ +#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ +#define XCHAL_HAVE_PRID 1 /* processor ID register */ +#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ +#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ +#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ +#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */ +#define XCHAL_HAVE_BOOLEANS 0 /* boolean registers */ +#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ +#define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */ +#define XCHAL_HAVE_MAC16 1 /* MAC16 package */ +#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */ +#define XCHAL_HAVE_FP 0 /* floating point pkg */ +#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ +#define XCHAL_HAVE_DFP_accel 0 /* double precision FP acceleration pkg */ +#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ +#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ +#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ +#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */ +#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ +#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */ +#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ +#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ +#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ +#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */ +#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */ +#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ +#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ +#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ + + +/*---------------------------------------------------------------------- + MISC + ----------------------------------------------------------------------*/ + +#define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */ +#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */ +#define XCHAL_DATA_WIDTH 4 /* data width in bytes */ +/* In T1050, applies to selected core load and store instructions (see ISA): */ +#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ +#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/ +#define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */ +#define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/ + +#define XCHAL_SW_VERSION 900001 /* sw version of this header */ + +#define XCHAL_CORE_ID "dc233c" /* alphanum core name + (CoreID) set in the Xtensa + Processor Generator */ + +#define XCHAL_CORE_DESCRIPTION "dc233c" +#define XCHAL_BUILD_UNIQUE_ID 0x00004B21 /* 22-bit sw build ID */ + +/* + * These definitions describe the hardware targeted by this software. + */ +#define XCHAL_HW_CONFIGID0 0xC56707FE /* ConfigID hi 32 bits*/ +#define XCHAL_HW_CONFIGID1 0x14404B21 /* ConfigID lo 32 bits*/ +#define XCHAL_HW_VERSION_NAME "LX4.0.1" /* full version name */ +#define XCHAL_HW_VERSION_MAJOR 2400 /* major ver# of targeted hw */ +#define XCHAL_HW_VERSION_MINOR 1 /* minor ver# of targeted hw */ +#define XCHAL_HW_VERSION 240001 /* major*100+minor */ +#define XCHAL_HW_REL_LX4 1 +#define XCHAL_HW_REL_LX4_0 1 +#define XCHAL_HW_REL_LX4_0_1 1 +#define XCHAL_HW_CONFIGID_RELIABLE 1 +/* If software targets a *range* of hardware versions, these are the bounds: */ +#define XCHAL_HW_MIN_VERSION_MAJOR 2400 /* major v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION_MINOR 1 /* minor v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION 240001 /* earliest targeted hw */ +#define XCHAL_HW_MAX_VERSION_MAJOR 2400 /* major v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION_MINOR 1 /* minor v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION 240001 /* latest targeted hw */ + + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + +#define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */ +#define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */ +#define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ +#define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ + +#define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */ +#define XCHAL_DCACHE_SIZE 16384 /* D-cache size in bytes or 0 */ + +#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */ +#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ + +#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */ + + + + +/**************************************************************************** + Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code + ****************************************************************************/ + + +#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */ + +/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ + +/* Number of cache sets in log2(lines per way): */ +#define XCHAL_ICACHE_SETWIDTH 7 +#define XCHAL_DCACHE_SETWIDTH 7 + +/* Cache set associativity (number of ways): */ +#define XCHAL_ICACHE_WAYS 4 +#define XCHAL_DCACHE_WAYS 4 + +/* Cache features: */ +#define XCHAL_ICACHE_LINE_LOCKABLE 1 +#define XCHAL_DCACHE_LINE_LOCKABLE 1 +#define XCHAL_ICACHE_ECC_PARITY 0 +#define XCHAL_DCACHE_ECC_PARITY 0 + +/* Cache access size in bytes (affects operation of SICW instruction): */ +#define XCHAL_ICACHE_ACCESS_SIZE 4 +#define XCHAL_DCACHE_ACCESS_SIZE 4 + +/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */ +#define XCHAL_CA_BITS 4 + + +/*---------------------------------------------------------------------- + INTERNAL I/D RAM/ROMs and XLMI + ----------------------------------------------------------------------*/ + +#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */ +#define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */ +#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */ +#define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */ +#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ +#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */ + +#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ + + +/*---------------------------------------------------------------------- + INTERRUPTS and TIMERS + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ +#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ +#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ +#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ +#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ +#define XCHAL_NUM_INTERRUPTS 22 /* number of interrupts */ +#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ +#define XCHAL_NUM_EXTINTERRUPTS 17 /* num of external interrupts */ +#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels + (not including level zero) */ +#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */ + /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ + +/* Masks of interrupts at each interrupt level: */ +#define XCHAL_INTLEVEL1_MASK 0x001F80FF +#define XCHAL_INTLEVEL2_MASK 0x00000100 +#define XCHAL_INTLEVEL3_MASK 0x00200E00 +#define XCHAL_INTLEVEL4_MASK 0x00001000 +#define XCHAL_INTLEVEL5_MASK 0x00002000 +#define XCHAL_INTLEVEL6_MASK 0x00000000 +#define XCHAL_INTLEVEL7_MASK 0x00004000 + +/* Masks of interrupts at each range 1..n of interrupt levels: */ +#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x001F80FF +#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x001F81FF +#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x003F8FFF +#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x003F9FFF +#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x003FBFFF +#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x003FBFFF +#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x003FFFFF + +/* Level of each interrupt: */ +#define XCHAL_INT0_LEVEL 1 +#define XCHAL_INT1_LEVEL 1 +#define XCHAL_INT2_LEVEL 1 +#define XCHAL_INT3_LEVEL 1 +#define XCHAL_INT4_LEVEL 1 +#define XCHAL_INT5_LEVEL 1 +#define XCHAL_INT6_LEVEL 1 +#define XCHAL_INT7_LEVEL 1 +#define XCHAL_INT8_LEVEL 2 +#define XCHAL_INT9_LEVEL 3 +#define XCHAL_INT10_LEVEL 3 +#define XCHAL_INT11_LEVEL 3 +#define XCHAL_INT12_LEVEL 4 +#define XCHAL_INT13_LEVEL 5 +#define XCHAL_INT14_LEVEL 7 +#define XCHAL_INT15_LEVEL 1 +#define XCHAL_INT16_LEVEL 1 +#define XCHAL_INT17_LEVEL 1 +#define XCHAL_INT18_LEVEL 1 +#define XCHAL_INT19_LEVEL 1 +#define XCHAL_INT20_LEVEL 1 +#define XCHAL_INT21_LEVEL 3 +#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */ +#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ +#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with + EXCSAVE/EPS/EPC_n, RFI n) */ + +/* Type of each interrupt: */ +#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI +#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE + +/* Masks of interrupts for each type of interrupt: */ +#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000 +#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000880 +#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x003F8000 +#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000133F +#define XCHAL_INTTYPE_MASK_TIMER 0x00002440 +#define XCHAL_INTTYPE_MASK_NMI 0x00004000 +#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000 + +/* Interrupt numbers assigned to specific interrupt sources: */ +#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */ +#define XCHAL_TIMER1_INTERRUPT 10 /* CCOMPARE1 */ +#define XCHAL_TIMER2_INTERRUPT 13 /* CCOMPARE2 */ +#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED +#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */ + +/* Interrupt numbers for levels at which only one interrupt is configured: */ +#define XCHAL_INTLEVEL2_NUM 8 +#define XCHAL_INTLEVEL4_NUM 12 +#define XCHAL_INTLEVEL5_NUM 13 +#define XCHAL_INTLEVEL7_NUM 14 +/* (There are many interrupts each at level(s) 1, 3.) */ + + +/* + * External interrupt vectors/levels. + * These macros describe how Xtensa processor interrupt numbers + * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) + * map to external BInterrupt<n> pins, for those interrupts + * configured as external (level-triggered, edge-triggered, or NMI). + * See the Xtensa processor databook for more details. + */ + +/* Core interrupt numbers mapped to each EXTERNAL interrupt number: */ +#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */ +#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */ +#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */ +#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */ +#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */ +#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */ +#define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */ +#define XCHAL_EXTINT7_NUM 9 /* (intlevel 3) */ +#define XCHAL_EXTINT8_NUM 12 /* (intlevel 4) */ +#define XCHAL_EXTINT9_NUM 14 /* (intlevel 7) */ +#define XCHAL_EXTINT10_NUM 15 /* (intlevel 1) */ +#define XCHAL_EXTINT11_NUM 16 /* (intlevel 1) */ +#define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */ +#define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */ +#define XCHAL_EXTINT14_NUM 19 /* (intlevel 1) */ +#define XCHAL_EXTINT15_NUM 20 /* (intlevel 1) */ +#define XCHAL_EXTINT16_NUM 21 /* (intlevel 3) */ + + +/*---------------------------------------------------------------------- + EXCEPTIONS and VECTORS + ----------------------------------------------------------------------*/ + +#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture + number: 1 == XEA1 (old) + 2 == XEA2 (new) + 0 == XEAX (extern) or TX */ +#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ +#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ +#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ +#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ +#define XCHAL_HAVE_HALT 0 /* halt architecture option */ +#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */ +#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ +#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ +#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ +#define XCHAL_VECBASE_RESET_VADDR 0x00002000 /* VECBASE reset value */ +#define XCHAL_VECBASE_RESET_PADDR 0x00002000 +#define XCHAL_RESET_VECBASE_OVERLAP 0 + +#define XCHAL_RESET_VECTOR0_VADDR 0xFE000000 +#define XCHAL_RESET_VECTOR0_PADDR 0xFE000000 +#define XCHAL_RESET_VECTOR1_VADDR 0x00001000 +#define XCHAL_RESET_VECTOR1_PADDR 0x00001000 +#define XCHAL_RESET_VECTOR_VADDR 0xFE000000 +#define XCHAL_RESET_VECTOR_PADDR 0xFE000000 +#define XCHAL_USER_VECOFS 0x00000340 +#define XCHAL_USER_VECTOR_VADDR 0x00002340 +#define XCHAL_USER_VECTOR_PADDR 0x00002340 +#define XCHAL_KERNEL_VECOFS 0x00000300 +#define XCHAL_KERNEL_VECTOR_VADDR 0x00002300 +#define XCHAL_KERNEL_VECTOR_PADDR 0x00002300 +#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0 +#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x000023C0 +#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x000023C0 +#define XCHAL_WINDOW_OF4_VECOFS 0x00000000 +#define XCHAL_WINDOW_UF4_VECOFS 0x00000040 +#define XCHAL_WINDOW_OF8_VECOFS 0x00000080 +#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 +#define XCHAL_WINDOW_OF12_VECOFS 0x00000100 +#define XCHAL_WINDOW_UF12_VECOFS 0x00000140 +#define XCHAL_WINDOW_VECTORS_VADDR 0x00002000 +#define XCHAL_WINDOW_VECTORS_PADDR 0x00002000 +#define XCHAL_INTLEVEL2_VECOFS 0x00000180 +#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x00002180 +#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x00002180 +#define XCHAL_INTLEVEL3_VECOFS 0x000001C0 +#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x000021C0 +#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x000021C0 +#define XCHAL_INTLEVEL4_VECOFS 0x00000200 +#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x00002200 +#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x00002200 +#define XCHAL_INTLEVEL5_VECOFS 0x00000240 +#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x00002240 +#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x00002240 +#define XCHAL_INTLEVEL6_VECOFS 0x00000280 +#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x00002280 +#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x00002280 +#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS +#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR +#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR +#define XCHAL_NMI_VECOFS 0x000002C0 +#define XCHAL_NMI_VECTOR_VADDR 0x000022C0 +#define XCHAL_NMI_VECTOR_PADDR 0x000022C0 +#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS +#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR +#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR + + +/*---------------------------------------------------------------------- + DEBUG + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ +#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ +#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ +#define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option */ + + +/*---------------------------------------------------------------------- + MMU + ----------------------------------------------------------------------*/ + +/* See core-matmap.h header file for more details. */ + +#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ +#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */ +#define XCHAL_SPANNING_WAY 6 /* TLB spanning way number */ +#define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */ +#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ +#define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */ +#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ +#define XCHAL_HAVE_PTP_MMU 1 /* full MMU (with page table + [autorefill] and protection) + usable for an MMU-based OS */ +/* If none of the above last 4 are set, it's a custom TLB configuration. */ +#define XCHAL_ITLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */ +#define XCHAL_DTLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */ + +#define XCHAL_MMU_ASID_BITS 8 /* number of bits in ASIDs */ +#define XCHAL_MMU_RINGS 4 /* number of rings (1..4) */ +#define XCHAL_MMU_RING_BITS 2 /* num of bits in RING field */ + +#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ + + +#endif /* _XTENSA_CORE_CONFIGURATION_H */ + diff --git a/arch/xtensa/include/asm/arch-dc233c/tie-asm.h b/arch/xtensa/include/asm/arch-dc233c/tie-asm.h new file mode 100644 index 00000000000..38217ec69e3 --- /dev/null +++ b/arch/xtensa/include/asm/arch-dc233c/tie-asm.h @@ -0,0 +1,173 @@ +/* + * This header file contains assembly-language definitions (assembly + * macros, etc.) for this specific Xtensa processor's TIE extensions + * and options. It is customized to this Xtensa processor configuration. + * This file is autogenerated, please do not edit. + * + * Copyright (C) 1999-2010 Tensilica Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _XTENSA_CORE_TIE_ASM_H +#define _XTENSA_CORE_TIE_ASM_H + +/* Selection parameter values for save-area save/restore macros: */ +/* Option vs. TIE: */ +#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */ +#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */ +#define XTHAL_SAS_ANYOT 0x0003 /* both of the above */ +/* Whether used automatically by compiler: */ +#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */ +#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */ +#define XTHAL_SAS_ANYCC 0x000C /* both of the above */ +/* ABI handling across function calls: */ +#define XTHAL_SAS_CALR 0x0010 /* caller-saved */ +#define XTHAL_SAS_CALE 0x0020 /* callee-saved */ +#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */ +#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */ +/* Misc */ +#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */ +#define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \ + | ((ccuse) & XTHAL_SAS_ANYCC) \ + | ((abi) & XTHAL_SAS_ANYABI) ) + + + + /* + * Macro to save all non-coprocessor (extra) custom TIE and optional state + * (not including zero-overhead loop registers). + * Required parameters: + * ptr Save area pointer address register (clobbered) + * (register must contain a 4 byte aligned address). + * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS + * registers are clobbered, the remaining are unused). + * Optional parameters: + * continue If macro invoked as part of a larger store sequence, set to 1 + * if this is not the first in the sequence. Defaults to 0. + * ofs Offset from start of larger sequence (from value of first ptr + * in sequence) at which to store. Defaults to next available space + * (or 0 if <continue> is 0). + * select Select what category(ies) of registers to store, as a bitmask + * (see XTHAL_SAS_xxx constants). Defaults to all registers. + * alloc Select what category(ies) of registers to allocate; if any + * category is selected here that is not in <select>, space for + * the corresponding registers is skipped without doing any store. + */ + .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 + xchal_sa_start \continue, \ofs + // Optional global register used by default by the compiler: + .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select) + xchal_sa_align \ptr, 0, 1020, 4, 4 + rur.THREADPTR \at1 // threadptr option + s32i \at1, \ptr, .Lxchal_ofs_+0 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 + .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0 + xchal_sa_align \ptr, 0, 1020, 4, 4 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 + .endif + // Optional caller-saved registers used by default by the compiler: + .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select) + xchal_sa_align \ptr, 0, 1016, 4, 4 + rsr \at1, ACCLO // MAC16 option + s32i \at1, \ptr, .Lxchal_ofs_+0 + rsr \at1, ACCHI // MAC16 option + s32i \at1, \ptr, .Lxchal_ofs_+4 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 + .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 + xchal_sa_align \ptr, 0, 1016, 4, 4 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 + .endif + // Optional caller-saved registers not used by default by the compiler: + .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) + xchal_sa_align \ptr, 0, 1004, 4, 4 + rsr \at1, M0 // MAC16 option + s32i \at1, \ptr, .Lxchal_ofs_+0 + rsr \at1, M1 // MAC16 option + s32i \at1, \ptr, .Lxchal_ofs_+4 + rsr \at1, M2 // MAC16 option + s32i \at1, \ptr, .Lxchal_ofs_+8 + rsr \at1, M3 // MAC16 option + s32i \at1, \ptr, .Lxchal_ofs_+12 + rsr \at1, SCOMPARE1 // conditional store option + s32i \at1, \ptr, .Lxchal_ofs_+16 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 20 + .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 + xchal_sa_align \ptr, 0, 1004, 4, 4 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 20 + .endif + .endm // xchal_ncp_store + + /* + * Macro to restore all non-coprocessor (extra) custom TIE and optional state + * (not including zero-overhead loop registers). + * Required parameters: + * ptr Save area pointer address register (clobbered) + * (register must contain a 4 byte aligned address). + * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS + * registers are clobbered, the remaining are unused). + * Optional parameters: + * continue If macro invoked as part of a larger load sequence, set to 1 + * if this is not the first in the sequence. Defaults to 0. + * ofs Offset from start of larger sequence (from value of first ptr + * in sequence) at which to load. Defaults to next available space + * (or 0 if <continue> is 0). + * select Select what category(ies) of registers to load, as a bitmask + * (see XTHAL_SAS_xxx constants). Defaults to all registers. + * alloc Select what category(ies) of registers to allocate; if any + * category is selected here that is not in <select>, space for + * the corresponding registers is skipped without doing any load. + */ + .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 + xchal_sa_start \continue, \ofs + // Optional global register used by default by the compiler: + .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select) + xchal_sa_align \ptr, 0, 1020, 4, 4 + l32i \at1, \ptr, .Lxchal_ofs_+0 + wur.THREADPTR \at1 // threadptr option + .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 + .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0 + xchal_sa_align \ptr, 0, 1020, 4, 4 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 + .endif + // Optional caller-saved registers used by default by the compiler: + .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select) + xchal_sa_align \ptr, 0, 1016, 4, 4 + l32i \at1, \ptr, .Lxchal_ofs_+0 + wsr \at1, ACCLO // MAC16 option + l32i \at1, \ptr, .Lxchal_ofs_+4 + wsr \at1, ACCHI // MAC16 option + .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 + .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 + xchal_sa_align \ptr, 0, 1016, 4, 4 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 + .endif + // Optional caller-saved registers not used by default by the compiler: + .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) + xchal_sa_align \ptr, 0, 1004, 4, 4 + l32i \at1, \ptr, .Lxchal_ofs_+0 + wsr \at1, M0 // MAC16 option + l32i \at1, \ptr, .Lxchal_ofs_+4 + wsr \at1, M1 // MAC16 option + l32i \at1, \ptr, .Lxchal_ofs_+8 + wsr \at1, M2 // MAC16 option + l32i \at1, \ptr, .Lxchal_ofs_+12 + wsr \at1, M3 // MAC16 option + l32i \at1, \ptr, .Lxchal_ofs_+16 + wsr \at1, SCOMPARE1 // conditional store option + .set .Lxchal_ofs_, .Lxchal_ofs_ + 20 + .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 + xchal_sa_align \ptr, 0, 1004, 4, 4 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 20 + .endif + .endm // xchal_ncp_load + + +#define XCHAL_NCP_NUM_ATMPS 1 + + + +#define XCHAL_SA_NUM_ATMPS 1 + +#endif /*_XTENSA_CORE_TIE_ASM_H*/ + diff --git a/arch/xtensa/include/asm/arch-dc233c/tie.h b/arch/xtensa/include/asm/arch-dc233c/tie.h new file mode 100644 index 00000000000..32a714f77dc --- /dev/null +++ b/arch/xtensa/include/asm/arch-dc233c/tie.h @@ -0,0 +1,130 @@ +/* + * This header file describes this specific Xtensa processor's TIE extensions + * that extend basic Xtensa core functionality. It is customized to this + * Xtensa processor configuration. + * This file is autogenerated, please do not edit. + * + * Copyright (C) 1999-2010 Tensilica Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _XTENSA_CORE_TIE_H +#define _XTENSA_CORE_TIE_H + +#define XCHAL_CP_NUM 1 /* number of coprocessors */ +#define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */ +#define XCHAL_CP_MASK 0x80 /* bitmask of all CPs by ID */ +#define XCHAL_CP_PORT_MASK 0x80 /* bitmask of only port CPs */ + +/* Basic parameters of each coprocessor: */ +#define XCHAL_CP7_NAME "XTIOP" +#define XCHAL_CP7_IDENT XTIOP +#define XCHAL_CP7_SA_SIZE 0 /* size of state save area */ +#define XCHAL_CP7_SA_ALIGN 1 /* min alignment of save area */ +#define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */ + +/* Filler info for unassigned coprocessors, to simplify arrays etc: */ +#define XCHAL_CP0_SA_SIZE 0 +#define XCHAL_CP0_SA_ALIGN 1 +#define XCHAL_CP1_SA_SIZE 0 +#define XCHAL_CP1_SA_ALIGN 1 +#define XCHAL_CP2_SA_SIZE 0 +#define XCHAL_CP2_SA_ALIGN 1 +#define XCHAL_CP3_SA_SIZE 0 +#define XCHAL_CP3_SA_ALIGN 1 +#define XCHAL_CP4_SA_SIZE 0 +#define XCHAL_CP4_SA_ALIGN 1 +#define XCHAL_CP5_SA_SIZE 0 +#define XCHAL_CP5_SA_ALIGN 1 +#define XCHAL_CP6_SA_SIZE 0 +#define XCHAL_CP6_SA_ALIGN 1 + +/* Save area for non-coprocessor optional and custom (TIE) state: */ +#define XCHAL_NCP_SA_SIZE 32 +#define XCHAL_NCP_SA_ALIGN 4 + +/* Total save area for optional and custom state (NCP + CPn): */ +#define XCHAL_TOTAL_SA_SIZE 32 /* with 16-byte align padding */ +#define XCHAL_TOTAL_SA_ALIGN 4 /* actual minimum alignment */ + +/* + * Detailed contents of save areas. + * NOTE: caller must define the XCHAL_SA_REG macro (not defined here) + * before expanding the XCHAL_xxx_SA_LIST() macros. + * + * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize, + * dbnum,base,regnum,bitsz,gapsz,reset,x...) + * + * s = passed from XCHAL_*_LIST(s), eg. to select how to expand + * ccused = set if used by compiler without special options or code + * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global) + * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg) + * opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg) + * name = lowercase reg name (no quotes) + * galign = group byte alignment (power of 2) (galign >= align) + * align = register byte alignment (power of 2) + * asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz) + * (not including any pad bytes required to galign this or next reg) + * dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>) + * base = reg shortname w/o index (or sr=special, ur=TIE user reg) + * regnum = reg index in regfile, or special/TIE-user reg number + * bitsz = number of significant bits (regfile width, or ur/sr mask bits) + * gapsz = intervening bits, if bitsz bits not stored contiguously + * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize) + * reset = register reset value (or 0 if undefined at reset) + * x = reserved for future use (0 until then) + * + * To filter out certain registers, e.g. to expand only the non-global + * registers used by the compiler, you can do something like this: + * + * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p) + * #define SELCC0(p...) + * #define SELCC1(abikind,p...) SELAK##abikind(p) + * #define SELAK0(p...) REG(p) + * #define SELAK1(p...) REG(p) + * #define SELAK2(p...) + * #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \ + * ...what you want to expand... + */ + +#define XCHAL_NCP_SA_NUM 8 +#define XCHAL_NCP_SA_LIST(s) \ + XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \ + XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \ + XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \ + XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) + +#define XCHAL_CP0_SA_NUM 0 +#define XCHAL_CP0_SA_LIST(s) /* empty */ + +#define XCHAL_CP1_SA_NUM 0 +#define XCHAL_CP1_SA_LIST(s) /* empty */ + +#define XCHAL_CP2_SA_NUM 0 +#define XCHAL_CP2_SA_LIST(s) /* empty */ + +#define XCHAL_CP3_SA_NUM 0 +#define XCHAL_CP3_SA_LIST(s) /* empty */ + +#define XCHAL_CP4_SA_NUM 0 +#define XCHAL_CP4_SA_LIST(s) /* empty */ + +#define XCHAL_CP5_SA_NUM 0 +#define XCHAL_CP5_SA_LIST(s) /* empty */ + +#define XCHAL_CP6_SA_NUM 0 +#define XCHAL_CP6_SA_LIST(s) /* empty */ + +#define XCHAL_CP7_SA_NUM 0 +#define XCHAL_CP7_SA_LIST(s) /* empty */ + +/* Byte length of instruction from its first nibble (op0 field), per FLIX. */ +#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3 + +#endif /*_XTENSA_CORE_TIE_H*/ + diff --git a/arch/xtensa/include/asm/arch-de212/core.h b/arch/xtensa/include/asm/arch-de212/core.h new file mode 100644 index 00000000000..be135016843 --- /dev/null +++ b/arch/xtensa/include/asm/arch-de212/core.h @@ -0,0 +1,573 @@ +/* + * Xtensa processor core configuration information. + * This file is autogenerated, please do not edit. + * + * Copyright (C) 1999-2015 Tensilica Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _XTENSA_CORE_CONFIGURATION_H +#define _XTENSA_CORE_CONFIGURATION_H + + +/**************************************************************************** + Parameters Useful for Any Code, USER or PRIVILEGED + ****************************************************************************/ + +/* + * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is + * configured, and a value of 0 otherwise. These macros are always defined. + */ + + +/*---------------------------------------------------------------------- + ISA + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ +#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ +#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */ +#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */ +#define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */ +#define XCHAL_HAVE_DEBUG 1 /* debug option */ +#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ +#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ +#define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */ +#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ +#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ +#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ +#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */ +#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ +#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ +#define XCHAL_HAVE_MUL32 1 /* MULL instruction */ +#define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */ +#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */ +#define XCHAL_HAVE_L32R 1 /* L32R instruction */ +#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */ +#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ +#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ +#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ +#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ +#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ +#define XCHAL_HAVE_ABS 1 /* ABS instruction */ +/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */ +/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */ +#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ +#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ +#define XCHAL_HAVE_SPECULATION 0 /* speculation */ +#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ +#define XCHAL_NUM_CONTEXTS 1 /* */ +#define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */ +#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ +#define XCHAL_HAVE_PRID 1 /* processor ID register */ +#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ +#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */ +#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ +#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ +#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */ +#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */ +#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */ +#define XCHAL_HAVE_THREADPTR 0 /* THREADPTR register */ +#define XCHAL_HAVE_BOOLEANS 0 /* boolean registers */ +#define XCHAL_HAVE_CP 0 /* CPENABLE reg (coprocessor) */ +#define XCHAL_CP_MAXCFG 0 /* max allowed cp id plus one */ +#define XCHAL_HAVE_MAC16 1 /* MAC16 package */ + +#define XCHAL_HAVE_FUSION 0 /* Fusion*/ +#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */ +#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */ +#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */ +#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */ +#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */ +#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */ +#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */ +#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */ +#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ +#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */ +#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ +#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */ +#define XCHAL_HAVE_HIFI_MINI 0 + + +#define XCHAL_HAVE_VECTORFPU2005 0 /* vector or user floating-point pkg */ +#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */ +#define XCHAL_HAVE_USER_SPFPU 0 /* user DP floating-point pkg */ +#define XCHAL_HAVE_FP 0 /* single prec floating point */ +#define XCHAL_HAVE_FP_DIV 0 /* FP with DIV instructions */ +#define XCHAL_HAVE_FP_RECIP 0 /* FP with RECIP instructions */ +#define XCHAL_HAVE_FP_SQRT 0 /* FP with SQRT instructions */ +#define XCHAL_HAVE_FP_RSQRT 0 /* FP with RSQRT instructions */ +#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ +#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */ +#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/ +#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */ +#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/ +#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */ +#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */ + +#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */ +#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */ +#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ +#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ +#define XCHAL_HAVE_PDX4 0 /* PDX4 */ +#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ +#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */ +#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */ +#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ +#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ +#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ +#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */ +#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */ +#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */ +#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */ +#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ +#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ +#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ +#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */ +#define XCHAL_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */ +#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */ + + +/*---------------------------------------------------------------------- + MISC + ----------------------------------------------------------------------*/ + +#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */ +#define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */ +#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */ +#define XCHAL_DATA_WIDTH 4 /* data width in bytes */ +#define XCHAL_DATA_PIPE_DELAY 1 /* d-side pipeline delay + (1 = 5-stage, 2 = 7-stage) */ +#define XCHAL_CLOCK_GATING_GLOBAL 0 /* global clock gating */ +#define XCHAL_CLOCK_GATING_FUNCUNIT 0 /* funct. unit clock gating */ +/* In T1050, applies to selected core load and store instructions (see ISA): */ +#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ +#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/ +#define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */ +#define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/ + +#define XCHAL_SW_VERSION 1100002 /* sw version of this header */ + +#define XCHAL_CORE_ID "de212" /* alphanum core name + (CoreID) set in the Xtensa + Processor Generator */ + +#define XCHAL_BUILD_UNIQUE_ID 0x0005A985 /* 22-bit sw build ID */ + +/* + * These definitions describe the hardware targeted by this software. + */ +#define XCHAL_HW_CONFIGID0 0xC283DFFE /* ConfigID hi 32 bits*/ +#define XCHAL_HW_CONFIGID1 0x1C85A985 /* ConfigID lo 32 bits*/ +#define XCHAL_HW_VERSION_NAME "LX6.0.2" /* full version name */ +#define XCHAL_HW_VERSION_MAJOR 2600 /* major ver# of targeted hw */ +#define XCHAL_HW_VERSION_MINOR 2 /* minor ver# of targeted hw */ +#define XCHAL_HW_VERSION 260002 /* major*100+minor */ +#define XCHAL_HW_REL_LX6 1 +#define XCHAL_HW_REL_LX6_0 1 +#define XCHAL_HW_REL_LX6_0_2 1 +#define XCHAL_HW_CONFIGID_RELIABLE 1 +/* If software targets a *range* of hardware versions, these are the bounds: */ +#define XCHAL_HW_MIN_VERSION_MAJOR 2600 /* major v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION_MINOR 2 /* minor v of earliest tgt hw */ +#define XCHAL_HW_MIN_VERSION 260002 /* earliest targeted hw */ +#define XCHAL_HW_MAX_VERSION_MAJOR 2600 /* major v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION_MINOR 2 /* minor v of latest tgt hw */ +#define XCHAL_HW_MAX_VERSION 260002 /* latest targeted hw */ + + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + +#define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */ +#define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */ +#define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */ +#define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */ + +#define XCHAL_ICACHE_SIZE 8192 /* I-cache size in bytes or 0 */ +#define XCHAL_DCACHE_SIZE 8192 /* D-cache size in bytes or 0 */ + +#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */ +#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ + +#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */ +#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */ +#define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */ +#define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */ +#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */ +#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */ +#define XCHAL_HAVE_ICACHE_TEST 1 /* Icache test instructions */ +#define XCHAL_HAVE_DCACHE_TEST 1 /* Dcache test instructions */ +#define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */ +#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */ + + + + +/**************************************************************************** + Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code + ****************************************************************************/ + + +#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY + +/*---------------------------------------------------------------------- + CACHE + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */ + +/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ + +/* Number of cache sets in log2(lines per way): */ +#define XCHAL_ICACHE_SETWIDTH 7 +#define XCHAL_DCACHE_SETWIDTH 7 + +/* Cache set associativity (number of ways): */ +#define XCHAL_ICACHE_WAYS 2 +#define XCHAL_DCACHE_WAYS 2 + +/* Cache features: */ +#define XCHAL_ICACHE_LINE_LOCKABLE 1 +#define XCHAL_DCACHE_LINE_LOCKABLE 1 +#define XCHAL_ICACHE_ECC_PARITY 0 +#define XCHAL_DCACHE_ECC_PARITY 0 + +/* Cache access size in bytes (affects operation of SICW instruction): */ +#define XCHAL_ICACHE_ACCESS_SIZE 4 +#define XCHAL_DCACHE_ACCESS_SIZE 4 + +#define XCHAL_DCACHE_BANKS 1 /* number of banks */ + +/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */ +#define XCHAL_CA_BITS 4 + +/* Whether MEMCTL register has anything useful */ +#define XCHAL_USE_MEMCTL (((XCHAL_LOOP_BUFFER_SIZE > 0) || \ + XCHAL_DCACHE_IS_COHERENT || \ + XCHAL_HAVE_ICACHE_DYN_WAYS || \ + XCHAL_HAVE_DCACHE_DYN_WAYS) && \ + (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0)) + + +/*---------------------------------------------------------------------- + INTERNAL I/D RAM/ROMs and XLMI + ----------------------------------------------------------------------*/ + +#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */ +#define XCHAL_NUM_INSTRAM 1 /* number of core instr. RAMs */ +#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */ +#define XCHAL_NUM_DATARAM 1 /* number of core data RAMs */ +#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ +#define XCHAL_NUM_XLMI 1 /* number of core XLMI ports */ + +/* Instruction RAM 0: */ +#define XCHAL_INSTRAM0_VADDR 0x40000000 /* virtual address */ +#define XCHAL_INSTRAM0_PADDR 0x40000000 /* physical address */ +#define XCHAL_INSTRAM0_SIZE 131072 /* size in bytes */ +#define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ + +/* Data RAM 0: */ +#define XCHAL_DATARAM0_VADDR 0x3FFE0000 /* virtual address */ +#define XCHAL_DATARAM0_PADDR 0x3FFE0000 /* physical address */ +#define XCHAL_DATARAM0_SIZE 131072 /* size in bytes */ +#define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ +#define XCHAL_DATARAM0_BANKS 1 /* number of banks */ + +/* XLMI Port 0: */ +#define XCHAL_XLMI0_VADDR 0x3FFC0000 /* virtual address */ +#define XCHAL_XLMI0_PADDR 0x3FFC0000 /* physical address */ +#define XCHAL_XLMI0_SIZE 131072 /* size in bytes */ +#define XCHAL_XLMI0_ECC_PARITY 0 /* ECC/parity type, 0=none */ + +#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ + + +/*---------------------------------------------------------------------- + INTERRUPTS and TIMERS + ----------------------------------------------------------------------*/ + +#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ +#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ +#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ +#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ +#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */ +#define XCHAL_NUM_INTERRUPTS 22 /* number of interrupts */ +#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ +#define XCHAL_NUM_EXTINTERRUPTS 17 /* num of external interrupts */ +#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels + (not including level zero) */ +#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */ + /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ + +/* Masks of interrupts at each interrupt level: */ +#define XCHAL_INTLEVEL1_MASK 0x001F80FF +#define XCHAL_INTLEVEL2_MASK 0x00000100 +#define XCHAL_INTLEVEL3_MASK 0x00200E00 +#define XCHAL_INTLEVEL4_MASK 0x00001000 +#define XCHAL_INTLEVEL5_MASK 0x00002000 +#define XCHAL_INTLEVEL6_MASK 0x00000000 +#define XCHAL_INTLEVEL7_MASK 0x00004000 + +/* Masks of interrupts at each range 1..n of interrupt levels: */ +#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x001F80FF +#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x001F81FF +#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x003F8FFF +#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x003F9FFF +#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x003FBFFF +#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x003FBFFF +#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x003FFFFF + +/* Level of each interrupt: */ +#define XCHAL_INT0_LEVEL 1 +#define XCHAL_INT1_LEVEL 1 +#define XCHAL_INT2_LEVEL 1 +#define XCHAL_INT3_LEVEL 1 +#define XCHAL_INT4_LEVEL 1 +#define XCHAL_INT5_LEVEL 1 +#define XCHAL_INT6_LEVEL 1 +#define XCHAL_INT7_LEVEL 1 +#define XCHAL_INT8_LEVEL 2 +#define XCHAL_INT9_LEVEL 3 +#define XCHAL_INT10_LEVEL 3 +#define XCHAL_INT11_LEVEL 3 +#define XCHAL_INT12_LEVEL 4 +#define XCHAL_INT13_LEVEL 5 +#define XCHAL_INT14_LEVEL 7 +#define XCHAL_INT15_LEVEL 1 +#define XCHAL_INT16_LEVEL 1 +#define XCHAL_INT17_LEVEL 1 +#define XCHAL_INT18_LEVEL 1 +#define XCHAL_INT19_LEVEL 1 +#define XCHAL_INT20_LEVEL 1 +#define XCHAL_INT21_LEVEL 3 +#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */ +#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ +#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with + EXCSAVE/EPS/EPC_n, RFI n) */ + +/* Type of each interrupt: */ +#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE +#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL +#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER +#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI +#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE +#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE + +/* Masks of interrupts for each type of interrupt: */ +#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000 +#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000880 +#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x003F8000 +#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000133F +#define XCHAL_INTTYPE_MASK_TIMER 0x00002440 +#define XCHAL_INTTYPE_MASK_NMI 0x00004000 +#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000 +#define XCHAL_INTTYPE_MASK_PROFILING 0x00000000 + +/* Interrupt numbers assigned to specific interrupt sources: */ +#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */ +#define XCHAL_TIMER1_INTERRUPT 10 /* CCOMPARE1 */ +#define XCHAL_TIMER2_INTERRUPT 13 /* CCOMPARE2 */ +#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED +#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */ + +/* Interrupt numbers for levels at which only one interrupt is configured: */ +#define XCHAL_INTLEVEL2_NUM 8 +#define XCHAL_INTLEVEL4_NUM 12 +#define XCHAL_INTLEVEL5_NUM 13 +#define XCHAL_INTLEVEL7_NUM 14 +/* (There are many interrupts each at level(s) 1, 3.) */ + + +/* + * External interrupt mapping. + * These macros describe how Xtensa processor interrupt numbers + * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) + * map to external BInterrupt<n> pins, for those interrupts + * configured as external (level-triggered, edge-triggered, or NMI). + * See the Xtensa processor databook for more details. + */ + +/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */ +#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */ +#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */ +#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */ +#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */ +#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */ +#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */ +#define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */ +#define XCHAL_EXTINT7_NUM 9 /* (intlevel 3) */ +#define XCHAL_EXTINT8_NUM 12 /* (intlevel 4) */ +#define XCHAL_EXTINT9_NUM 14 /* (intlevel 7) */ +#define XCHAL_EXTINT10_NUM 15 /* (intlevel 1) */ +#define XCHAL_EXTINT11_NUM 16 /* (intlevel 1) */ +#define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */ +#define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */ +#define XCHAL_EXTINT14_NUM 19 /* (intlevel 1) */ +#define XCHAL_EXTINT15_NUM 20 /* (intlevel 1) */ +#define XCHAL_EXTINT16_NUM 21 /* (intlevel 3) */ +/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */ +#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */ +#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */ +#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */ +#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */ +#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */ +#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */ +#define XCHAL_INT8_EXTNUM 6 /* (intlevel 2) */ +#define XCHAL_INT9_EXTNUM 7 /* (intlevel 3) */ +#define XCHAL_INT12_EXTNUM 8 /* (intlevel 4) */ +#define XCHAL_INT14_EXTNUM 9 /* (intlevel 7) */ +#define XCHAL_INT15_EXTNUM 10 /* (intlevel 1) */ +#define XCHAL_INT16_EXTNUM 11 /* (intlevel 1) */ +#define XCHAL_INT17_EXTNUM 12 /* (intlevel 1) */ +#define XCHAL_INT18_EXTNUM 13 /* (intlevel 1) */ +#define XCHAL_INT19_EXTNUM 14 /* (intlevel 1) */ +#define XCHAL_INT20_EXTNUM 15 /* (intlevel 1) */ +#define XCHAL_INT21_EXTNUM 16 /* (intlevel 3) */ + + +/*---------------------------------------------------------------------- + EXCEPTIONS and VECTORS + ----------------------------------------------------------------------*/ + +#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture + number: 1 == XEA1 (old) + 2 == XEA2 (new) + 0 == XEAX (extern) or TX */ +#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ +#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ +#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ +#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ +#define XCHAL_HAVE_HALT 0 /* halt architecture option */ +#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */ +#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ +#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ +#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ +#define XCHAL_VECBASE_RESET_VADDR 0x60000000 /* VECBASE reset value */ +#define XCHAL_VECBASE_RESET_PADDR 0x60000000 +#define XCHAL_RESET_VECBASE_OVERLAP 0 + +#define XCHAL_RESET_VECTOR0_VADDR 0x50000000 +#define XCHAL_RESET_VECTOR0_PADDR 0x50000000 +#define XCHAL_RESET_VECTOR1_VADDR 0x40000400 +#define XCHAL_RESET_VECTOR1_PADDR 0x40000400 +#define XCHAL_RESET_VECTOR_VADDR 0x50000000 +#define XCHAL_RESET_VECTOR_PADDR 0x50000000 +#define XCHAL_USER_VECOFS 0x00000340 +#define XCHAL_USER_VECTOR_VADDR 0x60000340 +#define XCHAL_USER_VECTOR_PADDR 0x60000340 +#define XCHAL_KERNEL_VECOFS 0x00000300 +#define XCHAL_KERNEL_VECTOR_VADDR 0x60000300 +#define XCHAL_KERNEL_VECTOR_PADDR 0x60000300 +#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0 +#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x600003C0 +#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x600003C0 +#define XCHAL_WINDOW_OF4_VECOFS 0x00000000 +#define XCHAL_WINDOW_UF4_VECOFS 0x00000040 +#define XCHAL_WINDOW_OF8_VECOFS 0x00000080 +#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 +#define XCHAL_WINDOW_OF12_VECOFS 0x00000100 +#define XCHAL_WINDOW_UF12_VECOFS 0x00000140 +#define XCHAL_WINDOW_VECTORS_VADDR 0x60000000 +#define XCHAL_WINDOW_VECTORS_PADDR 0x60000000 +#define XCHAL_INTLEVEL2_VECOFS 0x00000180 +#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x60000180 +#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x60000180 +#define XCHAL_INTLEVEL3_VECOFS 0x000001C0 +#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x600001C0 +#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x600001C0 +#define XCHAL_INTLEVEL4_VECOFS 0x00000200 +#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x60000200 +#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x60000200 +#define XCHAL_INTLEVEL5_VECOFS 0x00000240 +#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x60000240 +#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x60000240 +#define XCHAL_INTLEVEL6_VECOFS 0x00000280 +#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x60000280 +#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x60000280 +#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS +#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR +#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR +#define XCHAL_NMI_VECOFS 0x000002C0 +#define XCHAL_NMI_VECTOR_VADDR 0x600002C0 +#define XCHAL_NMI_VECTOR_PADDR 0x600002C0 +#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS +#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR +#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR + + +/*---------------------------------------------------------------------- + DEBUG MODULE + ----------------------------------------------------------------------*/ + +/* Misc */ +#define XCHAL_HAVE_DEBUG_ERI 1 /* ERI to debug module */ +#define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */ +#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */ + +/* On-Chip Debug (OCD) */ +#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ +#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ +#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ +#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */ +#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */ + +/* TRAX (in core) */ +#define XCHAL_HAVE_TRAX 1 /* TRAX in debug module */ +#define XCHAL_TRAX_MEM_SIZE 262144 /* TRAX memory size in bytes */ +#define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */ +#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */ +#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ + +/* Perf counters */ +#define XCHAL_NUM_PERF_COUNTERS 0 /* performance counters */ + + +/*---------------------------------------------------------------------- + MMU + ----------------------------------------------------------------------*/ + +/* See core-matmap.h header file for more details. */ + +#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ +#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */ +#define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */ +#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */ +#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ +#define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */ +#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ +#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table + [autorefill] and protection) + usable for an MMU-based OS */ +/* If none of the above last 4 are set, it's a custom TLB configuration. */ + +#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ +#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ +#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */ + +#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ + + +#endif /* _XTENSA_CORE_CONFIGURATION_H */ + diff --git a/arch/xtensa/include/asm/arch-de212/tie-asm.h b/arch/xtensa/include/asm/arch-de212/tie-asm.h new file mode 100644 index 00000000000..7213550b8a8 --- /dev/null +++ b/arch/xtensa/include/asm/arch-de212/tie-asm.h @@ -0,0 +1,150 @@ +/* + * This header file contains assembly-language definitions (assembly + * macros, etc.) for this specific Xtensa processor's TIE extensions + * and options. It is customized to this Xtensa processor configuration. + * This file is autogenerated, please do not edit. + * + * Copyright (C) 1999-2015 Cadence Design Systems Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _XTENSA_CORE_TIE_ASM_H +#define _XTENSA_CORE_TIE_ASM_H + +/* Selection parameter values for save-area save/restore macros: */ +/* Option vs. TIE: */ +#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */ +#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */ +#define XTHAL_SAS_ANYOT 0x0003 /* both of the above */ +/* Whether used automatically by compiler: */ +#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */ +#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */ +#define XTHAL_SAS_ANYCC 0x000C /* both of the above */ +/* ABI handling across function calls: */ +#define XTHAL_SAS_CALR 0x0010 /* caller-saved */ +#define XTHAL_SAS_CALE 0x0020 /* callee-saved */ +#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */ +#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */ +/* Misc */ +#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */ +#define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \ + | ((ccuse) & XTHAL_SAS_ANYCC) \ + | ((abi) & XTHAL_SAS_ANYABI) ) + + + /* + * Macro to store all non-coprocessor (extra) custom TIE and optional state + * (not including zero-overhead loop registers). + * Required parameters: + * ptr Save area pointer address register (clobbered) + * (register must contain a 4 byte aligned address). + * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS + * registers are clobbered, the remaining are unused). + * Optional parameters: + * continue If macro invoked as part of a larger store sequence, set to 1 + * if this is not the first in the sequence. Defaults to 0. + * ofs Offset from start of larger sequence (from value of first ptr + * in sequence) at which to store. Defaults to next available space + * (or 0 if <continue> is 0). + * select Select what category(ies) of registers to store, as a bitmask + * (see XTHAL_SAS_xxx constants). Defaults to all registers. + * alloc Select what category(ies) of registers to allocate; if any + * category is selected here that is not in <select>, space for + * the corresponding registers is skipped without doing any store. + */ + .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 + xchal_sa_start \continue, \ofs + // Optional caller-saved registers used by default by the compiler: + .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select) + xchal_sa_align \ptr, 0, 1016, 4, 4 + rsr.ACCLO \at1 // MAC16 option + s32i \at1, \ptr, .Lxchal_ofs_+0 + rsr.ACCHI \at1 // MAC16 option + s32i \at1, \ptr, .Lxchal_ofs_+4 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 + .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 + xchal_sa_align \ptr, 0, 1016, 4, 4 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 + .endif + // Optional caller-saved registers not used by default by the compiler: + .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) + xchal_sa_align \ptr, 0, 1004, 4, 4 + rsr.SCOMPARE1 \at1 // conditional store option + s32i \at1, \ptr, .Lxchal_ofs_+0 + rsr.M0 \at1 // MAC16 option + s32i \at1, \ptr, .Lxchal_ofs_+4 + rsr.M1 \at1 // MAC16 option + s32i \at1, \ptr, .Lxchal_ofs_+8 + rsr.M2 \at1 // MAC16 option + s32i \at1, \ptr, .Lxchal_ofs_+12 + rsr.M3 \at1 // MAC16 option + s32i \at1, \ptr, .Lxchal_ofs_+16 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 20 + .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 + xchal_sa_align \ptr, 0, 1004, 4, 4 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 20 + .endif + .endm // xchal_ncp_store + + /* + * Macro to load all non-coprocessor (extra) custom TIE and optional state + * (not including zero-overhead loop registers). + * Required parameters: + * ptr Save area pointer address register (clobbered) + * (register must contain a 4 byte aligned address). + * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS + * registers are clobbered, the remaining are unused). + * Optional parameters: + * continue If macro invoked as part of a larger load sequence, set to 1 + * if this is not the first in the sequence. Defaults to 0. + * ofs Offset from start of larger sequence (from value of first ptr + * in sequence) at which to load. Defaults to next available space + * (or 0 if <continue> is 0). + * select Select what category(ies) of registers to load, as a bitmask + * (see XTHAL_SAS_xxx constants). Defaults to all registers. + * alloc Select what category(ies) of registers to allocate; if any + * category is selected here that is not in <select>, space for + * the corresponding registers is skipped without doing any load. + */ + .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 + xchal_sa_start \continue, \ofs + // Optional caller-saved registers used by default by the compiler: + .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select) + xchal_sa_align \ptr, 0, 1016, 4, 4 + l32i \at1, \ptr, .Lxchal_ofs_+0 + wsr.ACCLO \at1 // MAC16 option + l32i \at1, \ptr, .Lxchal_ofs_+4 + wsr.ACCHI \at1 // MAC16 option + .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 + .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 + xchal_sa_align \ptr, 0, 1016, 4, 4 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 + .endif + // Optional caller-saved registers not used by default by the compiler: + .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) + xchal_sa_align \ptr, 0, 1004, 4, 4 + l32i \at1, \ptr, .Lxchal_ofs_+0 + wsr.SCOMPARE1 \at1 // conditional store option + l32i \at1, \ptr, .Lxchal_ofs_+4 + wsr.M0 \at1 // MAC16 option + l32i \at1, \ptr, .Lxchal_ofs_+8 + wsr.M1 \at1 // MAC16 option + l32i \at1, \ptr, .Lxchal_ofs_+12 + wsr.M2 \at1 // MAC16 option + l32i \at1, \ptr, .Lxchal_ofs_+16 + wsr.M3 \at1 // MAC16 option + .set .Lxchal_ofs_, .Lxchal_ofs_ + 20 + .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 + xchal_sa_align \ptr, 0, 1004, 4, 4 + .set .Lxchal_ofs_, .Lxchal_ofs_ + 20 + .endif + .endm // xchal_ncp_load + + +#define XCHAL_NCP_NUM_ATMPS 1 + +#define XCHAL_SA_NUM_ATMPS 1 + +#endif /*_XTENSA_CORE_TIE_ASM_H*/ + diff --git a/arch/xtensa/include/asm/arch-de212/tie.h b/arch/xtensa/include/asm/arch-de212/tie.h new file mode 100644 index 00000000000..fd0fbfe6e7d --- /dev/null +++ b/arch/xtensa/include/asm/arch-de212/tie.h @@ -0,0 +1,116 @@ +/* + * This header file describes this specific Xtensa processor's TIE extensions + * that extend basic Xtensa core functionality. It is customized to this + * Xtensa processor configuration. + * This file is autogenerated, please do not edit. + * + * Copyright (C) 1999-2015 Cadence Design Systems Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _XTENSA_CORE_TIE_H +#define _XTENSA_CORE_TIE_H + +#define XCHAL_CP_NUM 0 /* number of coprocessors */ +#define XCHAL_CP_MAX 0 /* max CP ID + 1 (0 if none) */ +#define XCHAL_CP_MASK 0x00 /* bitmask of all CPs by ID */ +#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */ + +/* Save area for non-coprocessor optional and custom (TIE) state: */ +#define XCHAL_NCP_SA_SIZE 28 +#define XCHAL_NCP_SA_ALIGN 4 + +/* Total save area for optional and custom state (NCP + CPn): */ +#define XCHAL_TOTAL_SA_SIZE 32 /* with 16-byte align padding */ +#define XCHAL_TOTAL_SA_ALIGN 4 /* actual minimum alignment */ + +/* + * Detailed contents of save areas. + * NOTE: caller must define the XCHAL_SA_REG macro (not defined here) + * before expanding the XCHAL_xxx_SA_LIST() macros. + * + * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize, + * dbnum,base,regnum,bitsz,gapsz,reset,x...) + * + * s = passed from XCHAL_*_LIST(s), eg. to select how to expand + * ccused = set if used by compiler without special options or code + * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global) + * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg) + * opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg) + * name = lowercase reg name (no quotes) + * galign = group byte alignment (power of 2) (galign >= align) + * align = register byte alignment (power of 2) + * asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz) + * (not including any pad bytes required to galign this or next reg) + * dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>) + * base = reg shortname w/o index (or sr=special, ur=TIE user reg) + * regnum = reg index in regfile, or special/TIE-user reg number + * bitsz = number of significant bits (regfile width, or ur/sr mask bits) + * gapsz = intervening bits, if bitsz bits not stored contiguously + * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize) + * reset = register reset value (or 0 if undefined at reset) + * x = reserved for future use (0 until then) + * + * To filter out certain registers, e.g. to expand only the non-global + * registers used by the compiler, you can do something like this: + * + * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p) + * #define SELCC0(p...) + * #define SELCC1(abikind,p...) SELAK##abikind(p) + * #define SELAK0(p...) REG(p) + * #define SELAK1(p...) REG(p) + * #define SELAK2(p...) + * #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \ + * ...what you want to expand... + */ + +#define XCHAL_NCP_SA_NUM 7 +#define XCHAL_NCP_SA_LIST(s) \ + XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \ + XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \ + XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \ + XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) + +#define XCHAL_CP0_SA_NUM 0 +#define XCHAL_CP0_SA_LIST(s) /* empty */ + +#define XCHAL_CP1_SA_NUM 0 +#define XCHAL_CP1_SA_LIST(s) /* empty */ + +#define XCHAL_CP2_SA_NUM 0 +#define XCHAL_CP2_SA_LIST(s) /* empty */ + +#define XCHAL_CP3_SA_NUM 0 +#define XCHAL_CP3_SA_LIST(s) /* empty */ + +#define XCHAL_CP4_SA_NUM 0 +#define XCHAL_CP4_SA_LIST(s) /* empty */ + +#define XCHAL_CP5_SA_NUM 0 +#define XCHAL_CP5_SA_LIST(s) /* empty */ + +#define XCHAL_CP6_SA_NUM 0 +#define XCHAL_CP6_SA_LIST(s) /* empty */ + +#define XCHAL_CP7_SA_NUM 0 +#define XCHAL_CP7_SA_LIST(s) /* empty */ + +/* Byte length of instruction from its first nibble (op0 field), per FLIX. */ +#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3 +/* Byte length of instruction from its first byte, per FLIX. */ +#define XCHAL_BYTE0_FORMAT_LENGTHS \ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3,\ + 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,3 + +#endif /*_XTENSA_CORE_TIE_H*/ + diff --git a/arch/xtensa/include/asm/asmmacro.h b/arch/xtensa/include/asm/asmmacro.h new file mode 100644 index 00000000000..b7adc7e1980 --- /dev/null +++ b/arch/xtensa/include/asm/asmmacro.h @@ -0,0 +1,152 @@ +/* + * Copyright (C) 2005 - 2013 Tensilica Inc. + * Copyright (C) 2014 - 2016 Cadence Design Systems Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _XTENSA_ASMMACRO_H +#define _XTENSA_ASMMACRO_H + +#include <asm/arch/core.h> + +/* + * Function entry and return macros for supported ABIs. + */ + +#if defined(__XTENSA_WINDOWED_ABI__) +#define abi_entry entry sp, 16 +#define abi_ret retw +#elif defined(__XTENSA_CALL0_ABI__) +#define abi_entry +#define abi_ret ret +#else +#error Unsupported Xtensa ABI +#endif + +/* + * Some little helpers for loops. Use zero-overhead-loops + * where applicable and if supported by the processor. + * + * __loopi ar, at, size, inc + * ar register initialized with the start address + * at scratch register used by macro + * size size immediate value + * inc increment + * + * __loops ar, as, at, inc_log2[, mask_log2][, cond][, ncond] + * ar register initialized with the start address + * as register initialized with the size + * at scratch register use by macro + * inc_log2 increment [in log2] + * mask_log2 mask [in log2] + * cond true condition (used in loop'cond') + * ncond false condition (used in b'ncond') + * + * __loop as + * restart loop. 'as' register must not have been modified! + * + * __endla ar, as, incr + * ar start address (modified) + * as scratch register used by __loops/__loopi macros or + * end address used by __loopt macro + * inc increment + */ + +#if XCHAL_HAVE_LOOPS + +.macro __loopi ar, at, size, incr + movi \at, ((\size + \incr - 1) / (\incr)) + loop \at, 99f +.endm + + +.macro __loops ar, as, at, incr_log2, mask_log2, cond, ncond + .ifgt \incr_log2 - 1 + addi \at, \as, (1 << \incr_log2) - 1 + .ifnc \mask_log2, + extui \at, \at, \incr_log2, \mask_log2 + .else + srli \at, \at, \incr_log2 + .endif + .endif + loop\cond \at, 99f +.endm + + +.macro __loopt ar, as, at, incr_log2 + sub \at, \as, \ar + .ifgt \incr_log2 - 1 + addi \at, \at, (1 << \incr_log2) - 1 + srli \at, \at, \incr_log2 + .endif + loop \at, 99f +.endm + + +.macro __loop as + loop \as, 99f +.endm + + +.macro __endl ar, as +99: +.endm + + +#else + +.macro __loopi ar, at, size, incr + movi \at, ((\size + \incr - 1) / (\incr)) + addi \at, \ar, \size +98: +.endm + + +.macro __loops ar, as, at, incr_log2, mask_log2, cond, ncond + .ifnc \mask_log2, + extui \at, \as, \incr_log2, \mask_log2 + .else + .ifnc \ncond, + srli \at, \as, \incr_log2 + .endif + .endif + .ifnc \ncond, + b\ncond \at, 99f + + .endif + .ifnc \mask_log2, + slli \at, \at, \incr_log2 + add \at, \ar, \at + .else + add \at, \ar, \as + .endif +98: +.endm + +.macro __loopt ar, as, at, incr_log2 +98: +.endm + + +.macro __loop as +98: +.endm + + +.macro __endl ar, as + bltu \ar, \as, 98b +99: +.endm + + +#endif + + +.macro __endla ar, as, incr + addi \ar, \ar, \incr + __endl \ar \as +.endm + + +#endif /* _XTENSA_ASMMACRO_H */ diff --git a/arch/xtensa/include/asm/atomic.h b/arch/xtensa/include/asm/atomic.h new file mode 100644 index 00000000000..a75baa09e0a --- /dev/null +++ b/arch/xtensa/include/asm/atomic.h @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2016 Cadence Design Systems Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _XTENSA_ATOMIC_H +#define _XTENSA_ATOMIC_H + +#include <asm/system.h> + +typedef struct { volatile int counter; } atomic_t; + +#define ATOMIC_INIT(i) { (i) } + +#define atomic_read(v) ((v)->counter) +#define atomic_set(v, i) ((v)->counter = (i)) + +static inline void atomic_add(int i, atomic_t *v) +{ + unsigned long flags; + + local_irq_save(flags); + v->counter += i; + local_irq_restore(flags); +} + +static inline void atomic_sub(int i, atomic_t *v) +{ + unsigned long flags; + + local_irq_save(flags); + v->counter -= i; + local_irq_restore(flags); +} + +static inline void atomic_inc(atomic_t *v) +{ + unsigned long flags; + + local_irq_save(flags); + ++v->counter; + local_irq_restore(flags); +} + +static inline void atomic_dec(atomic_t *v) +{ + unsigned long flags; + + local_irq_save(flags); + --v->counter; + local_irq_restore(flags); +} + +#endif diff --git a/arch/xtensa/include/asm/bitops.h b/arch/xtensa/include/asm/bitops.h new file mode 100644 index 00000000000..550d12f4986 --- /dev/null +++ b/arch/xtensa/include/asm/bitops.h @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2001 - 2012 Tensilica Inc. + * Copyright (C) 2014 - 2016 Cadence Design Systems Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _XTENSA_BITOPS_H +#define _XTENSA_BITOPS_H + +#include <asm/system.h> +#include <asm-generic/bitops/fls.h> +#include <asm-generic/bitops/__fls.h> +#include <asm-generic/bitops/fls64.h> +#include <asm-generic/bitops/__ffs.h> + +static inline int test_bit(int nr, const void *addr) +{ + return ((unsigned char *)addr)[nr >> 3] & (1u << (nr & 7)); +} + +static inline int test_and_set_bit(int nr, volatile void *addr) +{ + unsigned long flags; + unsigned char tmp; + unsigned char mask = 1u << (nr & 7); + + local_irq_save(flags); + tmp = ((unsigned char *)addr)[nr >> 3]; + ((unsigned char *)addr)[nr >> 3] |= mask; + local_irq_restore(flags); + + return tmp & mask; +} + +#endif /* _XTENSA_BITOPS_H */ diff --git a/arch/xtensa/include/asm/bootparam.h b/arch/xtensa/include/asm/bootparam.h new file mode 100644 index 00000000000..a2a9013ebf1 --- /dev/null +++ b/arch/xtensa/include/asm/bootparam.h @@ -0,0 +1,54 @@ +/* + * Definition of the Linux/Xtensa boot parameter structure + * + * Copyright (C) 2001 - 2009 Tensilica Inc. + * + * (Concept borrowed from the 68K port) + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _XTENSA_BOOTPARAM_H +#define _XTENSA_BOOTPARAM_H + +#define BP_VERSION 0x0001 + +#define BP_TAG_COMMAND_LINE 0x1001 /* command line (0-terminated string)*/ +#define BP_TAG_INITRD 0x1002 /* ramdisk addr and size (bp_meminfo) */ +#define BP_TAG_MEMORY 0x1003 /* memory addr and size (bp_meminfo) */ +#define BP_TAG_SERIAL_BAUDRATE 0x1004 /* baud rate of current console */ +#define BP_TAG_SERIAL_PORT 0x1005 /* serial device of current console */ +#define BP_TAG_FDT 0x1006 /* flat device tree */ + +#define BP_TAG_FIRST 0x7B0B /* first tag with a version number */ +#define BP_TAG_LAST 0x7E0B /* last tag */ + +#ifndef __ASSEMBLY__ + +/* All records are aligned to 4 bytes */ + +struct bp_tag { + unsigned short id; /* tag id */ + unsigned short size; /* size of this record excluding the structure*/ + unsigned long data[0]; /* data */ +}; + +#define bp_tag_next(tag) \ + ((struct bp_tag *)((unsigned long)((tag) + 1) + (tag)->size)) + +struct meminfo { + unsigned long type; + unsigned long start; + unsigned long end; +}; + +#define MEMORY_TYPE_CONVENTIONAL 0x1000 +#define MEMORY_TYPE_NONE 0x2000 + +struct sysmem_info { + int nr_banks; + struct meminfo bank[0]; +}; + +#endif +#endif diff --git a/arch/xtensa/include/asm/byteorder.h b/arch/xtensa/include/asm/byteorder.h new file mode 100644 index 00000000000..278653ce481 --- /dev/null +++ b/arch/xtensa/include/asm/byteorder.h @@ -0,0 +1,83 @@ +/* + * Based on Linux/Xtensa kernel version + * + * Copyright (C) 2001 - 2007 Tensilica Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _XTENSA_BYTEORDER_H +#define _XTENSA_BYTEORDER_H + +#include <asm/types.h> + +static inline __attribute__((const)) __u32 ___arch__swab32(__u32 x) +{ + __u32 res; + + /* instruction sequence from Xtensa ISA release 2/2000 */ + __asm__("ssai 8\n\t" + "srli %0, %1, 16\n\t" + "src %0, %0, %1\n\t" + "src %0, %0, %0\n\t" + "src %0, %1, %0\n" + : "=&a" (res) + : "a" (x) + ); + return res; +} + +static inline __attribute__((const)) __u16 ___arch__swab16(__u16 x) +{ + /* + * Given that 'short' values are signed (i.e., can be negative), + * we cannot assume that the upper 16-bits of the register are + * zero. We are careful to mask values after shifting. + */ + + /* + * There exists an anomaly between xt-gcc and xt-xcc. xt-gcc + * inserts an extui instruction after putting this function inline + * to ensure that it uses only the least-significant 16 bits of + * the result. xt-xcc doesn't use an extui, but assumes the + * __asm__ macro follows convention that the upper 16 bits of an + * 'unsigned short' result are still zero. This macro doesn't + * follow convention; indeed, it leaves garbage in the upport 16 + * bits of the register. + * + * Declaring the temporary variables 'res' and 'tmp' to be 32-bit + * types while the return type of the function is a 16-bit type + * forces both compilers to insert exactly one extui instruction + * (or equivalent) to mask off the upper 16 bits. + */ + + __u32 res; + __u32 tmp; + + __asm__("extui %1, %2, 8, 8\n\t" + "slli %0, %2, 8\n\t" + "or %0, %0, %1\n" + : "=&a" (res), "=&a" (tmp) + : "a" (x) + ); + + return res; +} + +#define __arch__swab32(x) ___arch__swab32(x) +#define __arch__swab16(x) ___arch__swab16(x) + +#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) +# define __BYTEORDER_HAS_U64__ +# define __SWAB_64_THRU_32__ +#endif + +#ifdef __XTENSA_EL__ +# include <linux/byteorder/little_endian.h> +#elif defined(__XTENSA_EB__) +# include <linux/byteorder/big_endian.h> +#else +# error processor byte order undefined! +#endif + +#endif /* _XTENSA_BYTEORDER_H */ diff --git a/arch/xtensa/include/asm/cache.h b/arch/xtensa/include/asm/cache.h new file mode 100644 index 00000000000..08c534ca014 --- /dev/null +++ b/arch/xtensa/include/asm/cache.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2009 Tensilica Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _XTENSA_CACHE_H +#define _XTENSA_CACHE_H + +#include <asm/arch/core.h> + +#define ARCH_DMA_MINALIGN XCHAL_DCACHE_LINESIZE + +#ifndef __ASSEMBLY__ + +void __flush_dcache_all(void); +void __flush_invalidate_dcache_range(unsigned long addr, unsigned long size); +void __invalidate_dcache_all(void); +void __invalidate_dcache_range(unsigned long addr, unsigned long size); + +void __invalidate_icache_all(void); +void __invalidate_icache_range(unsigned long addr, unsigned long size); + +#endif + +#endif /* _XTENSA_CACHE_H */ diff --git a/arch/xtensa/include/asm/cacheasm.h b/arch/xtensa/include/asm/cacheasm.h new file mode 100644 index 00000000000..342a8177e41 --- /dev/null +++ b/arch/xtensa/include/asm/cacheasm.h @@ -0,0 +1,211 @@ +/* + * Copyright (C) 2006 Tensilica Inc. + * Copyright (C) 2014 - 2016 Cadence Design Systems Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _XTENSA_CACHEASM_H +#define _XTENSA_CACHEASM_H + +#include <asm/cache.h> +#include <asm/asmmacro.h> +#include <linux/stringify.h> + +#define PAGE_SIZE 4096 +#define DCACHE_WAY_SIZE (XCHAL_DCACHE_SIZE/XCHAL_DCACHE_WAYS) +#define ICACHE_WAY_SIZE (XCHAL_ICACHE_SIZE/XCHAL_ICACHE_WAYS) +#define DCACHE_WAY_SHIFT (XCHAL_DCACHE_SETWIDTH + XCHAL_DCACHE_LINEWIDTH) +#define ICACHE_WAY_SHIFT (XCHAL_ICACHE_SETWIDTH + XCHAL_ICACHE_LINEWIDTH) + +/* + * Define cache functions as macros here so that they can be used + * by the kernel and boot loader. We should consider moving them to a + * library that can be linked by both. + * + * Locking + * + * ___unlock_dcache_all + * ___unlock_icache_all + * + * Flush and invaldating + * + * ___flush_invalidate_dcache_{all|range|page} + * ___flush_dcache_{all|range|page} + * ___invalidate_dcache_{all|range|page} + * ___invalidate_icache_{all|range|page} + * + */ + + .macro __loop_cache_all ar at insn size line_width + + movi \ar, 0 + + __loopi \ar, \at, \size, (4 << (\line_width)) + + \insn \ar, 0 << (\line_width) + \insn \ar, 1 << (\line_width) + \insn \ar, 2 << (\line_width) + \insn \ar, 3 << (\line_width) + + __endla \ar, \at, 4 << (\line_width) + + .endm + + + .macro __loop_cache_range ar as at insn line_width + + extui \at, \ar, 0, \line_width + add \as, \as, \at + + __loops \ar, \as, \at, \line_width + \insn \ar, 0 + __endla \ar, \at, (1 << (\line_width)) + + .endm + + + .macro __loop_cache_page ar at insn line_width + + __loopi \ar, \at, PAGE_SIZE, 4 << (\line_width) + + \insn \ar, 0 << (\line_width) + \insn \ar, 1 << (\line_width) + \insn \ar, 2 << (\line_width) + \insn \ar, 3 << (\line_width) + + __endla \ar, \at, 4 << (\line_width) + + .endm + + + .macro ___unlock_dcache_all ar at + +#if XCHAL_DCACHE_LINE_LOCKABLE && XCHAL_DCACHE_SIZE + __loop_cache_all \ar \at diu XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH +#endif + + .endm + + + .macro ___unlock_icache_all ar at + +#if XCHAL_ICACHE_LINE_LOCKABLE && XCHAL_ICACHE_SIZE + __loop_cache_all \ar \at iiu XCHAL_ICACHE_SIZE XCHAL_ICACHE_LINEWIDTH +#endif + + .endm + + + .macro ___flush_invalidate_dcache_all ar at + +#if XCHAL_DCACHE_SIZE + __loop_cache_all \ar \at diwbi XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH +#endif + + .endm + + + .macro ___flush_dcache_all ar at + +#if XCHAL_DCACHE_SIZE + __loop_cache_all \ar \at diwb XCHAL_DCACHE_SIZE XCHAL_DCACHE_LINEWIDTH +#endif + + .endm + + + .macro ___invalidate_dcache_all ar at + +#if XCHAL_DCACHE_SIZE + __loop_cache_all \ar \at dii __stringify(DCACHE_WAY_SIZE) \ + XCHAL_DCACHE_LINEWIDTH +#endif + + .endm + + + .macro ___invalidate_icache_all ar at + +#if XCHAL_ICACHE_SIZE + __loop_cache_all \ar \at iii __stringify(ICACHE_WAY_SIZE) \ + XCHAL_ICACHE_LINEWIDTH +#endif + + .endm + + + + .macro ___flush_invalidate_dcache_range ar as at + +#if XCHAL_DCACHE_SIZE + __loop_cache_range \ar \as \at dhwbi XCHAL_DCACHE_LINEWIDTH +#endif + + .endm + + + .macro ___flush_dcache_range ar as at + +#if XCHAL_DCACHE_SIZE + __loop_cache_range \ar \as \at dhwb XCHAL_DCACHE_LINEWIDTH +#endif + + .endm + + + .macro ___invalidate_dcache_range ar as at + +#if XCHAL_DCACHE_SIZE + __loop_cache_range \ar \as \at dhi XCHAL_DCACHE_LINEWIDTH +#endif + + .endm + + + .macro ___invalidate_icache_range ar as at + +#if XCHAL_ICACHE_SIZE + __loop_cache_range \ar \as \at ihi XCHAL_ICACHE_LINEWIDTH +#endif + + .endm + + + + .macro ___flush_invalidate_dcache_page ar as + +#if XCHAL_DCACHE_SIZE + __loop_cache_page \ar \as dhwbi XCHAL_DCACHE_LINEWIDTH +#endif + + .endm + + + .macro ___flush_dcache_page ar as + +#if XCHAL_DCACHE_SIZE + __loop_cache_page \ar \as dhwb XCHAL_DCACHE_LINEWIDTH +#endif + + .endm + + + .macro ___invalidate_dcache_page ar as + +#if XCHAL_DCACHE_SIZE + __loop_cache_page \ar \as dhi XCHAL_DCACHE_LINEWIDTH +#endif + + .endm + + + .macro ___invalidate_icache_page ar as + +#if XCHAL_ICACHE_SIZE + __loop_cache_page \ar \as ihi XCHAL_ICACHE_LINEWIDTH +#endif + + .endm + +#endif /* _XTENSA_CACHEASM_H */ diff --git a/arch/xtensa/include/asm/config.h b/arch/xtensa/include/asm/config.h new file mode 100644 index 00000000000..db1ea87c30b --- /dev/null +++ b/arch/xtensa/include/asm/config.h @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2009 Tensilica Inc. + * Copyright (C) 2014 - 2016 Cadence Design Systems Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_CONFIG_H_ +#define _ASM_CONFIG_H_ + +#include <asm/arch/core.h> + +#define CONFIG_LMB + +/* + * Make boot parameters available in the MMUv2 virtual memory layout by + * restricting used physical memory to the first 128MB. + */ +#if XCHAL_HAVE_PTP_MMU +#define CONFIG_VERY_BIG_RAM +#define CONFIG_MAX_MEM_MAPPED (128 << 20) +#endif + +#endif diff --git a/arch/xtensa/include/asm/errno.h b/arch/xtensa/include/asm/errno.h new file mode 100644 index 00000000000..4c82b503d92 --- /dev/null +++ b/arch/xtensa/include/asm/errno.h @@ -0,0 +1 @@ +#include <asm-generic/errno.h> diff --git a/arch/xtensa/include/asm/global_data.h b/arch/xtensa/include/asm/global_data.h new file mode 100644 index 00000000000..45693457ad3 --- /dev/null +++ b/arch/xtensa/include/asm/global_data.h @@ -0,0 +1,20 @@ +/* + * (C) Copyright 2007, Tensilica Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _XTENSA_GBL_DATA_H +#define _XTENSA_GBL_DATA_H + +/* Architecture-specific global data */ + +struct arch_global_data { + unsigned long cpu_clk; +}; + +#include <asm-generic/global_data.h> + +#define DECLARE_GLOBAL_DATA_PTR extern gd_t *gd + +#endif /* _XTENSA_GBL_DATA_H */ diff --git a/arch/xtensa/include/asm/io.h b/arch/xtensa/include/asm/io.h new file mode 100644 index 00000000000..e34d6e1d7fa --- /dev/null +++ b/arch/xtensa/include/asm/io.h @@ -0,0 +1,148 @@ +/* + * IO header file + * + * Copyright (C) 2001-2007 Tensilica Inc. + * Based on the Linux/Xtensa version of this header. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _XTENSA_IO_H +#define _XTENSA_IO_H + +#include <linux/types.h> +#include <asm/byteorder.h> + +/* + * swap functions to change byte order from little-endian to big-endian and + * vice versa. + */ + +static inline unsigned short _swapw(unsigned short v) +{ + return (v << 8) | (v >> 8); +} + +static inline unsigned int _swapl(unsigned int v) +{ + return (v << 24) | ((v & 0xff00) << 8) | + ((v >> 8) & 0xff00) | (v >> 24); +} + +/* + * Generic I/O + */ + +#define readb(addr) \ + ({ unsigned char __v = (*(volatile unsigned char *)(addr)); __v; }) +#define readw(addr) \ + ({ unsigned short __v = (*(volatile unsigned short *)(addr)); __v; }) +#define readl(addr) \ + ({ unsigned int __v = (*(volatile unsigned int *)(addr)); __v; }) +#define writeb(b, addr) (void)((*(volatile unsigned char *)(addr)) = (b)) +#define writew(b, addr) (void)((*(volatile unsigned short *)(addr)) = (b)) +#define writel(b, addr) (void)((*(volatile unsigned int *)(addr)) = (b)) + +#define __raw_readb readb +#define __raw_readw readw +#define __raw_readl readl +#define __raw_writeb writeb +#define __raw_writew writew +#define __raw_writel writel + +/* These are the definitions for the x86 IO instructions + * inb/inw/inl/outb/outw/outl, the "string" versions + * insb/insw/insl/outsb/outsw/outsl, and the "pausing" versions + * inb_p/inw_p/... + * The macros don't do byte-swapping. + */ + +#define inb(port) readb((u8 *)((port))) +#define outb(val, port) writeb((val), (u8 *)((unsigned long)(port))) +#define inw(port) readw((u16 *)((port))) +#define outw(val, port) writew((val), (u16 *)((unsigned long)(port))) +#define inl(port) readl((u32 *)((port))) +#define outl(val, port) writel((val), (u32 *)((unsigned long)(port))) + +#define inb_p(port) inb((port)) +#define outb_p(val, port) outb((val), (port)) +#define inw_p(port) inw((port)) +#define outw_p(val, port) outw((val), (port)) +#define inl_p(port) inl((port)) +#define outl_p(val, port) outl((val), (port)) + +void insb(unsigned long port, void *dst, unsigned long count); +void insw(unsigned long port, void *dst, unsigned long count); +void insl(unsigned long port, void *dst, unsigned long count); +void outsb(unsigned long port, const void *src, unsigned long count); +void outsw(unsigned long port, const void *src, unsigned long count); +void outsl(unsigned long port, const void *src, unsigned long count); + +#define IO_SPACE_LIMIT ~0 + +#define memset_io(a, b, c) memset((void *)(a), (b), (c)) +#define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c)) +#define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c)) + +/* At this point the Xtensa doesn't provide byte swap instructions */ + +#ifdef __XTENSA_EB__ +# define in_8(addr) (*(u8 *)(addr)) +# define in_le16(addr) _swapw(*(u16 *)(addr)) +# define in_le32(addr) _swapl(*(u32 *)(addr)) +# define out_8(b, addr) *(u8 *)(addr) = (b) +# define out_le16(b, addr) *(u16 *)(addr) = _swapw(b) +# define out_le32(b, addr) *(u32 *)(addr) = _swapl(b) +#elif defined(__XTENSA_EL__) +# define in_8(addr) (*(u8 *)(addr)) +# define in_le16(addr) (*(u16 *)(addr)) +# define in_le32(addr) (*(u32 *)(addr)) +# define out_8(b, addr) *(u8 *)(addr) = (b) +# define out_le16(b, addr) *(u16 *)(addr) = (b) +# define out_le32(b, addr) *(u32 *)(addr) = (b) +#else +# error processor byte order undefined! +#endif + + +/* + * Convert a physical pointer to a virtual kernel pointer for /dev/mem access + */ +#define xlate_dev_mem_ptr(p) __va(p) + +/* + * Convert a virtual cached pointer to an uncached pointer + */ +#define xlate_dev_kmem_ptr(p) p + +#define MAP_NOCACHE (0) +#define MAP_WRCOMBINE (0) +#define MAP_WRBACK (0) +#define MAP_WRTHROUGH (0) + +static inline void * +map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) +{ + return (void *)paddr; +} + +/* + * Take down a mapping set up by map_physmem(). + */ +static inline void unmap_physmem(void *vaddr, unsigned long flags) +{ +} + +static inline phys_addr_t virt_to_phys(void *vaddr) +{ + return (phys_addr_t)((unsigned long)vaddr); +} + +/* + * Dummy function to keep U-Boot's cfi_flash.c driver happy. + */ +static inline void sync(void) +{ +} + +#endif /* _XTENSA_IO_H */ diff --git a/arch/xtensa/include/asm/ldscript.h b/arch/xtensa/include/asm/ldscript.h new file mode 100644 index 00000000000..62a1c052685 --- /dev/null +++ b/arch/xtensa/include/asm/ldscript.h @@ -0,0 +1,222 @@ +/* + * (C) Copyright 2007 Tensilica, Inc. + * (C) Copyright 2014 - 2016 Cadence Design Systems Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _XTENSA_LDSCRIPT_H +#define _XTENSA_LDSCRIPT_H + +/* + * This linker script is pre-processed with CPP to avoid hard-coding + * addresses that depend on the Xtensa core configuration, because + * this FPGA board can be used with a huge variety of Xtensa cores. + */ + +#include <asm/arch/core.h> +#include <asm/addrspace.h> + +#define ALIGN_LMA 4 +#define LMA_EQ_VMA +#define FORCE_OUTPUT . = . +#define FOLLOWING(sec) \ + AT(((LOADADDR(sec) + SIZEOF(sec) + ALIGN_LMA-1)) & ~(ALIGN_LMA-1)) + +/* + * Specify an output section that will be added to the ROM store table + * (PACKED_SECTION) or one that will be resident in ROM (RESIDENT_SECTION). + * 'symname' is a base name for section boundary symbols *_start & *_end. + * 'lma' is the load address at which a section will be packed in ROM. + * 'region' is the basename identifying a memory region and program header. + * 'keep' prevents removal of empty sections (must be 'KEEP' or 'NOKEEP'). + */ + +#define RELOCATE1(_sec_) \ + LONG(_##_sec_##_start); \ + LONG(_##_sec_##_end); \ + LONG(LOADADDR(.##_sec_)); + +#define RELOCATE2(_sym_, _sec_) \ + LONG(_##_sym_##_##_sec_##_start); \ + LONG(_##_sym_##_##_sec_##_end); \ + LONG(LOADADDR(.##_sym_##.##_sec_)); + +#define SECTION_VECTOR(_sym_, _sec_, _vma_, _lma_) \ +.##_sym_##.##_sec_ _vma_ : _lma_ \ +{ \ + . = ALIGN(4); \ + _##_sym_##_##_sec_##_start = ABSOLUTE(.); \ + KEEP(*(.##_sym_##.##_sec_)) \ + _##_sym_##_##_sec_##_end = ABSOLUTE(.); \ +} + +/* In MMU configs there are two aliases of SYSROM, cached and uncached. + * For various reasons it is simpler to use the uncached mapping for load + * addresses, so ROM sections end up contiguous with the reset vector and + * we get a compact binary image. However we can gain performance by doing + * the unpacking from the cached ROM mapping. So we adjust all the load + * addresses in the ROM store table with an offset to the cached mapping, + * including the symbols referring to the ROM store table itself. + */ + +#define SECTION_ResetVector(_vma_, _lma_) \ + .ResetVector.text _vma_ : _lma_ \ + { \ + FORCE_OUTPUT; \ + KEEP(*(.ResetVector.text)); \ + KEEP(*(.reset.literal .reset.text)) \ + } + +#define SECTION_text(_vma_, _lma_) \ + .text _vma_ : _lma_ \ + { \ + _text_start = ABSOLUTE(.); \ + *(.literal .text) \ + *(.literal.* .text.* .stub) \ + *(.gnu.warning .gnu.linkonce.literal.*) \ + *(.gnu.linkonce.t.*.literal .gnu.linkonce.t.*) \ + *(.fini.literal) \ + *(.fini) \ + *(.gnu.version) \ + _text_end = ABSOLUTE(.); \ + } + +#define SECTION_rodata(_vma_, _lma_) \ + .rodata _vma_ : _lma_ \ + { \ + _rodata_start = ABSOLUTE(.); \ + *(.rodata) \ + *(.rodata.*) \ + *(.dtb.init.rodata) \ + *(.gnu.linkonce.r.*) \ + *(.rodata1) \ + __XT_EXCEPTION_TABLE__ = ABSOLUTE(.); \ + *(.xt_except_table) \ + *(.gcc_except_table) \ + *(.gnu.linkonce.e.*) \ + *(.gnu.version_r) \ + . = ALIGN(16); \ + _rodata_end = ABSOLUTE(.); \ + } + +#define SECTION_u_boot_list(_vma_, _lma_) \ + .u_boot_list _vma_ : _lma_ \ + { \ + _u_boot_list_start = ABSOLUTE(.); \ + KEEP(*(SORT(.u_boot_list*))); \ + _u_boot_list_end = ABSOLUTE(.); \ + } + +#define SECTION_data(_vma_, _lma_) \ + .data _vma_ : _lma_ \ + { \ + _data_start = ABSOLUTE(.); \ + *(.data) \ + *(.data.*) \ + *(.gnu.linkonce.d.*) \ + *(.data1) \ + *(.sdata) \ + *(.sdata.*) \ + *(.gnu.linkonce.s.*) \ + *(.sdata2) \ + *(.sdata2.*) \ + *(.gnu.linkonce.s2.*) \ + *(.jcr) \ + *(.eh_frame) \ + *(.dynamic) \ + *(.gnu.version_d) \ + _data_end = ABSOLUTE(.); \ + } + +#define SECTION_lit4(_vma_, _lma_) \ + .lit4 _vma_ : _lma_ \ + { \ + _lit4_start = ABSOLUTE(.); \ + *(*.lit4) \ + *(.gnu.linkonce.lit4.*) \ + _lit4_end = ABSOLUTE(.); \ + } + +#define SECTION_bss(_vma_, _lma_) \ + .bss _vma_ : _lma_ \ + { \ + . = ALIGN(8); \ + _bss_start = ABSOLUTE(.); \ + __bss_start = ABSOLUTE(.); \ + *(.dynsbss) \ + *(.sbss) \ + *(.sbss.*) \ + *(.gnu.linkonce.sb.*) \ + *(.scommon) \ + *(.sbss2) \ + *(.sbss2.*) \ + *(.gnu.linkonce.sb2.*) \ + *(.dynbss) \ + *(.bss) \ + *(.bss.*) \ + *(.gnu.linkonce.b.*) \ + *(COMMON) \ + *(.sram.bss) \ + . = ALIGN(8); \ + _bss_end = ABSOLUTE(.); \ + __bss_end = ABSOLUTE(.); \ + _end = ALIGN(0x8); \ + PROVIDE(end = ALIGN(0x8)); \ + _stack_sentry = ALIGN(0x8); \ + } + +#define SECTION_debug \ + .debug 0 : { *(.debug) } \ + .line 0 : { *(.line) } \ + .debug_srcinfo 0 : { *(.debug_srcinfo) } \ + .debug_sfnames 0 : { *(.debug_sfnames) } \ + .debug_aranges 0 : { *(.debug_aranges) } \ + .debug_pubnames 0 : { *(.debug_pubnames) } \ + .debug_info 0 : { *(.debug_info) } \ + .debug_abbrev 0 : { *(.debug_abbrev) } \ + .debug_line 0 : { *(.debug_line) } \ + .debug_frame 0 : { *(.debug_frame) } \ + .debug_str 0 : { *(.debug_str) } \ + .debug_loc 0 : { *(.debug_loc) } \ + .debug_macinfo 0 : { *(.debug_macinfo) } \ + .debug_weaknames 0 : { *(.debug_weaknames) } \ + .debug_funcnames 0 : { *(.debug_funcnames) } \ + .debug_typenames 0 : { *(.debug_typenames) } \ + .debug_varnames 0 : { *(.debug_varnames) } + +#define SECTION_xtensa \ + .xt.insn 0 : \ + { \ + KEEP (*(.xt.insn)) \ + KEEP (*(.gnu.linkonce.x.*)) \ + } \ + .xt.prop 0 : \ + { \ + KEEP (*(.xt.prop)) \ + KEEP (*(.xt.prop.*)) \ + KEEP (*(.gnu.linkonce.prop.*)) \ + } \ + .xt.lit 0 : \ + { \ + KEEP (*(.xt.lit)) \ + KEEP (*(.xt.lit.*)) \ + KEEP (*(.gnu.linkonce.p.*)) \ + } \ + .xt.profile_range 0 : \ + { \ + KEEP (*(.xt.profile_range)) \ + KEEP (*(.gnu.linkonce.profile_range.*)) \ + } \ + .xt.profile_ranges 0 : \ + { \ + KEEP (*(.xt.profile_ranges)) \ + KEEP (*(.gnu.linkonce.xt.profile_ranges.*)) \ + } \ + .xt.profile_files 0 : \ + { \ + KEEP (*(.xt.profile_files)) \ + KEEP (*(.gnu.linkonce.xt.profile_files.*)) \ + } + +#endif /* _XTENSA_LDSCRIPT_H */ diff --git a/arch/xtensa/include/asm/linkage.h b/arch/xtensa/include/asm/linkage.h new file mode 100644 index 00000000000..3f46161a9fb --- /dev/null +++ b/arch/xtensa/include/asm/linkage.h @@ -0,0 +1,4 @@ +#ifndef __ASM_LINKAGE_H +#define __ASM_LINKAGE_H + +#endif diff --git a/arch/xtensa/include/asm/misc.h b/arch/xtensa/include/asm/misc.h new file mode 100644 index 00000000000..5a2708fbeff --- /dev/null +++ b/arch/xtensa/include/asm/misc.h @@ -0,0 +1,20 @@ +/* + * (C) Copyright 2008, Tensilica Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + ******************************************************************** + * NOTE: This header file defines an interface to U-Boot. Including + * this (unmodified) header file in another file is considered normal + * use of U-Boot, and does *not* fall under the heading of "derived + * work". + ******************************************************************** + */ + +#ifndef _XTENSA_MISC_H +#define _XTENSA_MISC_H + +/* Used in cpu/xtensa/cpu.c */ +void board_reset(void); + +#endif /* _XTENSA_MISC_H */ diff --git a/arch/xtensa/include/asm/posix_types.h b/arch/xtensa/include/asm/posix_types.h new file mode 100644 index 00000000000..821115c0066 --- /dev/null +++ b/arch/xtensa/include/asm/posix_types.h @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2007, Tensilica Inc. + * + * Based on the ARM version: Copyright (C) 1996-1998 Russell King. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _XTENSA_POSIX_TYPES_H +#define _XTENSA_POSIX_TYPES_H + +/* + * This file is generally used by user-level software, so you need to + * be a little careful about namespace pollution etc. Also, we cannot + * assume GCC is being used. + */ + +typedef unsigned short __kernel_dev_t; +typedef unsigned long __kernel_ino_t; +typedef unsigned short __kernel_mode_t; +typedef unsigned short __kernel_nlink_t; +typedef long __kernel_off_t; +typedef int __kernel_pid_t; +typedef unsigned short __kernel_ipc_pid_t; +typedef unsigned short __kernel_uid_t; +typedef unsigned short __kernel_gid_t; +typedef unsigned int __kernel_size_t; +typedef int __kernel_ssize_t; +typedef int __kernel_ptrdiff_t; +typedef long __kernel_time_t; +typedef long __kernel_suseconds_t; +typedef long __kernel_clock_t; +typedef int __kernel_daddr_t; +typedef char * __kernel_caddr_t; +typedef unsigned short __kernel_uid16_t; +typedef unsigned short __kernel_gid16_t; +typedef unsigned int __kernel_uid32_t; +typedef unsigned int __kernel_gid32_t; + +typedef unsigned short __kernel_old_uid_t; +typedef unsigned short __kernel_old_gid_t; + +#ifdef __GNUC__ +typedef long long __kernel_loff_t; +#endif + +typedef struct { +#if defined(__KERNEL__) || defined(__USE_ALL) + int val[2]; +#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ + int __val[2]; +#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ +} __kernel_fsid_t; + +#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) + +#undef __FD_SET +#define __FD_SET(fd, fdsetp) \ + (((fd_set *)fdsetp)->fds_bits[fd >> 5] |= (1<<(fd & 31))) + +#undef __FD_CLR +#define __FD_CLR(fd, fdsetp) \ + (((fd_set *)fdsetp)->fds_bits[fd >> 5] &= ~(1<<(fd & 31))) + +#undef __FD_ISSET +#define __FD_ISSET(fd, fdsetp) \ + ((((fd_set *)fdsetp)->fds_bits[fd >> 5] & (1<<(fd & 31))) != 0) + +#undef __FD_ZERO +#define __FD_ZERO(fdsetp) \ + (memset(fdsetp, 0, sizeof(*(fd_set *)fdsetp))) + +#endif + +#endif /* _XTENSA_POSIX_TYPES_H */ diff --git a/arch/xtensa/include/asm/processor.h b/arch/xtensa/include/asm/processor.h new file mode 100644 index 00000000000..8822f80f8dc --- /dev/null +++ b/arch/xtensa/include/asm/processor.h @@ -0,0 +1,11 @@ +/* + * Copyright (C) 1997 Tensilica Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _XTENSA_PROCESSOR_H +#define _XTENSA_PROCESSOR_H + + +#endif /* _XTENSA_PROCESSOR_H */ diff --git a/arch/xtensa/include/asm/ptrace.h b/arch/xtensa/include/asm/ptrace.h new file mode 100644 index 00000000000..d187dbf4c98 --- /dev/null +++ b/arch/xtensa/include/asm/ptrace.h @@ -0,0 +1,133 @@ +/* + * Copyright (C) 2001 - 2007 Tensilica Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _XTENSA_PTRACE_H +#define _XTENSA_PTRACE_H + +#include <compiler.h> + +/* + * Kernel stack + * + * +-----------------------+ -------- STACK_SIZE + * | register file | | + * +-----------------------+ | + * | struct pt_regs | | + * +-----------------------+ | ------ PT_REGS_OFFSET + * double : 16 bytes spill area : | ^ + * exception :- - - - - - - - - - - -: | | + * frame : struct pt_regs : | | + * :- - - - - - - - - - - -: | | + * | | | | + * | memory stack | | | + * | | | | + * ~ ~ ~ ~ + * ~ ~ ~ ~ + * | | | | + * | | | | + * +-----------------------+ | | --- STACK_BIAS + * | struct task_struct | | | ^ + * current --> +-----------------------+ | | | + * | struct thread_info | | | | + * +-----------------------+ -------- + */ + +#define KERNEL_STACK_SIZE (2 * PAGE_SIZE) + +/* Offsets for exception_handlers[] (3 x 64-entries x 4-byte tables) */ + +#define EXC_TABLE_KSTK 0x004 /* Kernel Stack */ +#define EXC_TABLE_DOUBLE_SAVE 0x008 /* Double exception save area for a0 */ +#define EXC_TABLE_FIXUP 0x00c /* Fixup handler */ +#define EXC_TABLE_PARAM 0x010 /* For passing a parameter to fixup */ +#define EXC_TABLE_SYSCALL_SAVE 0x014 /* For fast syscall handler */ +#define EXC_TABLE_FAST_USER 0x100 /* Fast user exception handler */ +#define EXC_TABLE_FAST_KERNEL 0x200 /* Fast kernel exception handler */ +#define EXC_TABLE_DEFAULT 0x300 /* Default C-Handler */ +#define EXC_TABLE_SIZE 0x400 + +/* Registers used by strace */ + +#define REG_A_BASE 0xfc000000 +#define REG_AR_BASE 0x04000000 +#define REG_PC 0x14000000 +#define REG_PS 0x080000e6 +#define REG_WB 0x08000048 +#define REG_WS 0x08000049 +#define REG_LBEG 0x08000000 +#define REG_LEND 0x08000001 +#define REG_LCOUNT 0x08000002 +#define REG_SAR 0x08000003 +#define REG_DEPC 0x080000c0 +#define REG_EXCCAUSE 0x080000e8 +#define REG_EXCVADDR 0x080000ee +#define SYSCALL_NR 0x1 + +#define AR_REGNO_TO_A_REGNO(ar, wb) (ar - wb*4) & ~(XCHAL_NUM_AREGS - 1) + +/* Other PTRACE_ values defined in <linux/ptrace.h> using values 0-9,16,17,24 */ + +#define PTRACE_GETREGS 12 +#define PTRACE_SETREGS 13 +#define PTRACE_GETFPREGS 14 +#define PTRACE_SETFPREGS 15 +#define PTRACE_GETFPREGSIZE 18 + +#ifndef __ASSEMBLY__ + +/* + * This struct defines the way the registers are stored on the + * kernel stack during a system call or other kernel entry. + */ +struct pt_regs { + unsigned long pc; /* 4 */ + unsigned long ps; /* 8 */ + unsigned long depc; /* 12 */ + unsigned long exccause; /* 16 */ + unsigned long excvaddr; /* 20 */ + unsigned long debugcause; /* 24 */ + unsigned long wmask; /* 28 */ + unsigned long lbeg; /* 32 */ + unsigned long lend; /* 36 */ + unsigned long lcount; /* 40 */ + unsigned long sar; /* 44 */ + unsigned long windowbase; /* 48 */ + unsigned long windowstart; /* 52 */ + unsigned long syscall; /* 56 */ + unsigned long icountlevel; /* 60 */ + int reserved[1]; /* 64 */ + + /* Make sure the areg field is 16 bytes aligned */ + int align[0] __aligned(16); + + /* current register frame. + * Note: The ESF for kernel exceptions ends after 16 registers! + */ + unsigned long areg[16]; /* 128 (64) */ +}; + +#ifdef __KERNEL__ + +# define task_pt_regs(tsk) ((struct pt_regs *) \ + (task_stack_page(tsk) + KERNEL_STACK_SIZE - (XCHAL_NUM_AREGS-16)*4) - 1) +# define user_mode(regs) (((regs)->ps & 0x00000020) != 0) +# define instruction_pointer(regs) ((regs)->pc) +void show_regs(struct pt_regs *); + +# ifndef CONFIG_SMP +# define profile_pc(regs) instruction_pointer(regs) +# endif +#endif /* __KERNEL__ */ + +#else /* __ASSEMBLY__ */ + +#ifdef __KERNEL__ +# include <asm/asm-offsets.h> +#define PT_REGS_OFFSET (KERNEL_STACK_SIZE - PT_USER_SIZE) +#endif + +#endif /* !__ASSEMBLY__ */ +#endif /* _XTENSA_PTRACE_H */ diff --git a/arch/xtensa/include/asm/regs.h b/arch/xtensa/include/asm/regs.h new file mode 100644 index 00000000000..0a82a221dda --- /dev/null +++ b/arch/xtensa/include/asm/regs.h @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2006 Tensilica, Inc. All Rights Reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _XTENSA_REGS_H +#define _XTENSA_REGS_H + +/* Special registers */ + +#define IBREAKA 128 +#define DBREAKA 144 +#define DBREAKC 160 + +/* Special names for read-only and write-only interrupt registers */ + +#define INTREAD 226 +#define INTSET 226 +#define INTCLEAR 227 + +/* EXCCAUSE register fields */ + +#define EXCCAUSE_EXCCAUSE_SHIFT 0 +#define EXCCAUSE_EXCCAUSE_MASK 0x3F + +#define EXCCAUSE_ILLEGAL_INSTRUCTION 0 +#define EXCCAUSE_SYSTEM_CALL 1 +#define EXCCAUSE_INSTRUCTION_FETCH_ERROR 2 +#define EXCCAUSE_LOAD_STORE_ERROR 3 +#define EXCCAUSE_LEVEL1_INTERRUPT 4 +#define EXCCAUSE_ALLOCA 5 +#define EXCCAUSE_INTEGER_DIVIDE_BY_ZERO 6 +#define EXCCAUSE_SPECULATION 7 +#define EXCCAUSE_PRIVILEGED 8 +#define EXCCAUSE_UNALIGNED 9 +#define EXCCAUSE_INSTR_DATA_ERROR 12 +#define EXCCAUSE_LOAD_STORE_DATA_ERROR 13 +#define EXCCAUSE_INSTR_ADDR_ERROR 14 +#define EXCCAUSE_LOAD_STORE_ADDR_ERROR 15 +#define EXCCAUSE_ITLB_MISS 16 +#define EXCCAUSE_ITLB_MULTIHIT 17 +#define EXCCAUSE_ITLB_PRIVILEGE 18 +#define EXCCAUSE_ITLB_SIZE_RESTRICTION 19 +#define EXCCAUSE_FETCH_CACHE_ATTRIBUTE 20 +#define EXCCAUSE_DTLB_MISS 24 +#define EXCCAUSE_DTLB_MULTIHIT 25 +#define EXCCAUSE_DTLB_PRIVILEGE 26 +#define EXCCAUSE_DTLB_SIZE_RESTRICTION 27 +#define EXCCAUSE_LOAD_CACHE_ATTRIBUTE 28 +#define EXCCAUSE_STORE_CACHE_ATTRIBUTE 29 +#define EXCCAUSE_COPROCESSOR0_DISABLED 32 +#define EXCCAUSE_COPROCESSOR1_DISABLED 33 +#define EXCCAUSE_COPROCESSOR2_DISABLED 34 +#define EXCCAUSE_COPROCESSOR3_DISABLED 35 +#define EXCCAUSE_COPROCESSOR4_DISABLED 36 +#define EXCCAUSE_COPROCESSOR5_DISABLED 37 +#define EXCCAUSE_COPROCESSOR6_DISABLED 38 +#define EXCCAUSE_COPROCESSOR7_DISABLED 39 +#define EXCCAUSE_LAST 63 + +/* PS register fields */ + +#define PS_WOE_BIT 18 +#define PS_CALLINC_SHIFT 16 +#define PS_CALLINC_MASK 0x00030000 +#define PS_OWB_SHIFT 8 +#define PS_OWB_MASK 0x00000F00 +#define PS_RING_SHIFT 6 +#define PS_RING_MASK 0x000000C0 +#define PS_UM_BIT 5 +#define PS_EXCM_BIT 4 +#define PS_INTLEVEL_SHIFT 0 +#define PS_INTLEVEL_MASK 0x0000000F + +/* DBREAKCn register fields */ + +#define DBREAKC_MASK_BIT 0 +#define DBREAKC_MASK_MASK 0x0000003F +#define DBREAKC_LOAD_BIT 30 +#define DBREAKC_LOAD_MASK 0x40000000 +#define DBREAKC_STOR_BIT 31 +#define DBREAKC_STOR_MASK 0x80000000 + +/* DEBUGCAUSE register fields */ + +#define DEBUGCAUSE_DEBUGINT_BIT 5 /* External debug interrupt */ +#define DEBUGCAUSE_BREAKN_BIT 4 /* BREAK.N instruction */ +#define DEBUGCAUSE_BREAK_BIT 3 /* BREAK instruction */ +#define DEBUGCAUSE_DBREAK_BIT 2 /* DBREAK match */ +#define DEBUGCAUSE_IBREAK_BIT 1 /* IBREAK match */ +#define DEBUGCAUSE_ICOUNT_BIT 0 /* ICOUNT would incr. to zero */ + +#endif /* _XTENSA_SPECREG_H */ + diff --git a/arch/xtensa/include/asm/relocate.h b/arch/xtensa/include/asm/relocate.h new file mode 100644 index 00000000000..9c4ce239885 --- /dev/null +++ b/arch/xtensa/include/asm/relocate.h @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2016 Cadence Design Systems Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_XTENSA_RELOCATE_H +#define _ASM_XTENSA_RELOCATE_H + +#include <common.h> + +int clear_bss(void); + +#endif /* _ASM_XTENSA_RELOCATE_H */ diff --git a/arch/xtensa/include/asm/sections.h b/arch/xtensa/include/asm/sections.h new file mode 100644 index 00000000000..2309b146388 --- /dev/null +++ b/arch/xtensa/include/asm/sections.h @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2012 The Chromium OS Authors. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_XTENSA_SECTIONS_H +#define __ASM_XTENSA_SECTIONS_H + +#include <asm-generic/sections.h> + +#endif diff --git a/arch/xtensa/include/asm/string.h b/arch/xtensa/include/asm/string.h new file mode 100644 index 00000000000..65a36016741 --- /dev/null +++ b/arch/xtensa/include/asm/string.h @@ -0,0 +1,10 @@ +#ifndef _XTENSA_STRING_H +#define _XTENSA_STRING_H + +/* + * Use the generic string functions in U-Boot's lib_generic. + * In the boot loader we care about compactness more than performance. + * Prototypes will be taken from <linux/string.h> + */ + +#endif /* _XTENSA_STRING_H */ diff --git a/arch/xtensa/include/asm/system.h b/arch/xtensa/include/asm/system.h new file mode 100644 index 00000000000..5b710089c11 --- /dev/null +++ b/arch/xtensa/include/asm/system.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2016 Cadence Design Systems Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _XTENSA_SYSTEM_H +#define _XTENSA_SYSTEM_H + +#include <asm/arch/core.h> + +#if XCHAL_HAVE_INTERRUPTS +#define local_irq_save(flags) \ + __asm__ __volatile__ ("rsil %0, %1" \ + : "=a"(flags) \ + : "I"(XCHAL_EXCM_LEVEL) \ + : "memory") +#define local_irq_restore(flags) \ + __asm__ __volatile__ ("wsr %0, ps\n\t" \ + "rsync" \ + :: "a"(flags) : "memory") +#else +#define local_irq_save(flags) ((void)(flags)) +#define local_irq_restore(flags) ((void)(flags)) +#endif + +#endif diff --git a/arch/xtensa/include/asm/types.h b/arch/xtensa/include/asm/types.h new file mode 100644 index 00000000000..f7eda9dc590 --- /dev/null +++ b/arch/xtensa/include/asm/types.h @@ -0,0 +1,60 @@ +/* + * Copyright (C) 1997 Tensilica Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _XTENSA_TYPES_H +#define _XTENSA_TYPES_H + +typedef unsigned short umode_t; + +/* + * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the + * header files exported to user space + */ + +typedef __signed__ char __s8; +typedef unsigned char __u8; + +typedef __signed__ short __s16; +typedef unsigned short __u16; + +typedef __signed__ int __s32; +typedef unsigned int __u32; + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long __s64; +typedef unsigned long long __u64; +#endif + +/* + * These aren't exported outside the kernel to avoid name space clashes + */ +#ifdef __KERNEL__ + +typedef signed char s8; +typedef unsigned char u8; + +typedef signed short s16; +typedef unsigned short u16; + +typedef signed int s32; +typedef unsigned int u32; + +typedef signed long long s64; +typedef unsigned long long u64; + +#define BITS_PER_LONG 32 + +/* Dma addresses are 32-bits wide */ + +typedef u32 dma_addr_t; + +typedef unsigned long phys_addr_t; +typedef unsigned long phys_size_t; + + +#endif /* __KERNEL__ */ + +#endif /* _XTENSA_TYPES_H */ diff --git a/arch/xtensa/include/asm/u-boot.h b/arch/xtensa/include/asm/u-boot.h new file mode 100644 index 00000000000..cfdc0367b33 --- /dev/null +++ b/arch/xtensa/include/asm/u-boot.h @@ -0,0 +1,41 @@ +/* + * (C) Copyright 2007, Tensilica Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + ******************************************************************** + * NOTE: This header file defines an interface to U-Boot. Including + * this (unmodified) header file in another file is considered normal + * use of U-Boot, and does *not* fall under the heading of "derived + * work". + ******************************************************************** + */ + +#ifndef _XTENSA_U_BOOT_H +#define _XTENSA_U_BOOT_H + +#ifdef CONFIG_SYS_GENERIC_BOARD +/* Use the generic board which requires a unified bd_info */ +#include <asm-generic/u-boot.h> +#else + +#ifndef __ASSEMBLY__ +typedef struct bd_info { + int bi_baudrate; /* serial console baudrate */ + unsigned long bi_ip_addr; /* IP Address */ + unsigned char bi_enetaddr[6]; /* Ethernet adress */ + unsigned long bi_boot_params; /* where this board expects params */ + unsigned long bi_memstart; /* start of DRAM memory VA */ + unsigned long bi_memsize; /* size of DRAM memory in bytes */ + unsigned long bi_flashstart; /* start of FLASH memory */ + unsigned long bi_flashsize; /* size of FLASH memory */ + unsigned long bi_flashoffset; /* offset to skip UBoot image */ +} bd_t; +#endif /* __ ASSEMBLY__ */ + +#endif /* CONFIG_SYS_GENERIC_BOARD */ + +/* For image.h:image_check_target_arch() */ +#define IH_ARCH_DEFAULT IH_ARCH_XTENSA + +#endif /* _XTENSA_U_BOOT_H */ diff --git a/arch/xtensa/include/asm/unaligned.h b/arch/xtensa/include/asm/unaligned.h new file mode 100644 index 00000000000..536f3642e39 --- /dev/null +++ b/arch/xtensa/include/asm/unaligned.h @@ -0,0 +1,6 @@ +#ifndef _ASM_XTENSA_UNALIGNED_H +#define _ASM_XTENSA_UNALIGNED_H + +#include <asm-generic/unaligned.h> + +#endif /* _ASM_XTENSA_UNALIGNED_H */ diff --git a/arch/xtensa/lib/Makefile b/arch/xtensa/lib/Makefile new file mode 100644 index 00000000000..7c7d8d59bca --- /dev/null +++ b/arch/xtensa/lib/Makefile @@ -0,0 +1,10 @@ +# +# (C) Copyright 2007 - 2013 Tensilica Inc. +# (C) Copyright 2014 - 2016 Cadence Design Systems Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_CMD_BOOTM) += bootm.o + +obj-y += cache.o misc.o relocate.o time.o diff --git a/arch/xtensa/lib/bootm.c b/arch/xtensa/lib/bootm.c new file mode 100644 index 00000000000..1604bb95368 --- /dev/null +++ b/arch/xtensa/lib/bootm.c @@ -0,0 +1,197 @@ +/* + * (C) Copyright 2008 - 2013 Tensilica Inc. + * (C) Copyright 2014 Cadence Design Systems Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <command.h> +#include <u-boot/zlib.h> +#include <asm/byteorder.h> +#include <asm/addrspace.h> +#include <asm/bootparam.h> +#include <asm/cache.h> +#include <image.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Setup boot-parameters. + */ + +static struct bp_tag *setup_first_tag(struct bp_tag *params) +{ + params->id = BP_TAG_FIRST; + params->size = sizeof(long); + *(unsigned long *)¶ms->data = BP_VERSION; + + return bp_tag_next(params); +} + +static struct bp_tag *setup_last_tag(struct bp_tag *params) +{ + params->id = BP_TAG_LAST; + params->size = 0; + + return bp_tag_next(params); +} + +static struct bp_tag *setup_memory_tag(struct bp_tag *params) +{ + struct bd_info *bd = gd->bd; + struct meminfo *mem; + + params->id = BP_TAG_MEMORY; + params->size = sizeof(struct meminfo); + mem = (struct meminfo *)params->data; + mem->type = MEMORY_TYPE_CONVENTIONAL; + mem->start = bd->bi_memstart; + mem->end = bd->bi_memstart + bd->bi_memsize; + + printf(" MEMORY: tag:0x%04x, type:0X%lx, start:0X%lx, end:0X%lx\n", + BP_TAG_MEMORY, mem->type, mem->start, mem->end); + + return bp_tag_next(params); +} + +static struct bp_tag *setup_commandline_tag(struct bp_tag *params, + char *cmdline) +{ + int len; + + if (!cmdline) + return params; + + len = strlen(cmdline); + + params->id = BP_TAG_COMMAND_LINE; + params->size = (len + 3) & -4; + strcpy((char *)params->data, cmdline); + + printf(" COMMAND_LINE: tag:0x%04x, size:%u, data:'%s'\n", + BP_TAG_COMMAND_LINE, params->size, cmdline); + + return bp_tag_next(params); +} + +static struct bp_tag *setup_ramdisk_tag(struct bp_tag *params, + unsigned long rd_start, + unsigned long rd_end) +{ + struct meminfo *mem; + + if (rd_start == rd_end) + return params; + + /* Add a single banked memory */ + + params->id = BP_TAG_INITRD; + params->size = sizeof(struct meminfo); + + mem = (struct meminfo *)params->data; + mem->type = MEMORY_TYPE_CONVENTIONAL; + mem->start = PHYSADDR(rd_start); + mem->end = PHYSADDR(rd_end); + + printf(" INITRD: tag:0x%x, type:0X%04lx, start:0X%lx, end:0X%lx\n", + BP_TAG_INITRD, mem->type, mem->start, mem->end); + + return bp_tag_next(params); +} + +static struct bp_tag *setup_serial_tag(struct bp_tag *params) +{ + params->id = BP_TAG_SERIAL_BAUDRATE; + params->size = sizeof(unsigned long); + params->data[0] = gd->baudrate; + + printf(" SERIAL_BAUDRATE: tag:0x%04x, size:%u, baudrate:%lu\n", + BP_TAG_SERIAL_BAUDRATE, params->size, params->data[0]); + + return bp_tag_next(params); +} + +#ifdef CONFIG_OF_LIBFDT + +static struct bp_tag *setup_fdt_tag(struct bp_tag *params, void *fdt_start) +{ + params->id = BP_TAG_FDT; + params->size = sizeof(unsigned long); + params->data[0] = (unsigned long)fdt_start; + + printf(" FDT: tag:0x%04x, size:%u, start:0x%lx\n", + BP_TAG_FDT, params->size, params->data[0]); + + return bp_tag_next(params); +} + +#endif + +/* + * Boot Linux. + */ + +int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) +{ + struct bp_tag *params, *params_start; + ulong initrd_start, initrd_end; + char *commandline = getenv("bootargs"); + + if (!(flag & (BOOTM_STATE_OS_GO | BOOTM_STATE_OS_FAKE_GO))) + return 0; + + show_boot_progress(15); + + if (images->rd_start) { + initrd_start = images->rd_start; + initrd_end = images->rd_end; + } else { + initrd_start = 0; + initrd_end = 0; + } + + params_start = (struct bp_tag *)gd->bd->bi_boot_params; + params = params_start; + params = setup_first_tag(params); + params = setup_memory_tag(params); + params = setup_commandline_tag(params, commandline); + params = setup_serial_tag(params); + + if (initrd_start) + params = setup_ramdisk_tag(params, initrd_start, initrd_end); + +#ifdef CONFIG_OF_LIBFDT + if (images->ft_addr) + params = setup_fdt_tag(params, images->ft_addr); +#endif + + printf("\n"); + + params = setup_last_tag(params); + + show_boot_progress(15); + + printf("Transferring Control to Linux @0x%08lx ...\n\n", + (ulong)images->ep); + + flush_dcache_range((unsigned long)params_start, (unsigned long)params); + + if (flag & BOOTM_STATE_OS_FAKE_GO) + return 0; + + /* + * _start() in vmlinux expects boot params in register a2. + * NOTE: + * Disable/delete your u-boot breakpoints before stepping into linux. + */ + asm volatile ("mov a2, %0\n\t" + "jx %1\n\t" + : : "a" (params_start), "a" (images->ep) + : "a2"); + + /* Does not return */ + + return 1; +} + diff --git a/arch/xtensa/lib/cache.c b/arch/xtensa/lib/cache.c new file mode 100644 index 00000000000..26808390926 --- /dev/null +++ b/arch/xtensa/lib/cache.c @@ -0,0 +1,60 @@ +/* + * (C) Copyright 2008 - 2013 Tensilica Inc. + * (C) Copyright 2014 - 2016 Cadence Design Systems Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/cache.h> + +/* + * We currently run always with caches enabled when running from memory. + * Xtensa version D or later will support changing cache behavior, so + * we could implement it if necessary. + */ + +int dcache_status(void) +{ + return 1; +} + +void dcache_enable(void) +{ +} + +void dcache_disable(void) +{ +} + +void flush_cache(ulong start_addr, ulong size) +{ + __flush_invalidate_dcache_range(start_addr, size); + __invalidate_icache_range(start_addr, size); +} + +void flush_dcache_all(void) +{ + __flush_dcache_all(); + __invalidate_icache_all(); +} + +void flush_dcache_range(ulong start_addr, ulong end_addr) +{ + __flush_invalidate_dcache_range(start_addr, end_addr - start_addr); +} + +void invalidate_dcache_range(ulong start, ulong stop) +{ + __invalidate_dcache_range(start, stop - start); +} + +void invalidate_dcache_all(void) +{ + __invalidate_dcache_all(); +} + +void invalidate_icache_all(void) +{ + __invalidate_icache_all(); +} diff --git a/arch/xtensa/lib/misc.S b/arch/xtensa/lib/misc.S new file mode 100644 index 00000000000..449a6db8fd6 --- /dev/null +++ b/arch/xtensa/lib/misc.S @@ -0,0 +1,179 @@ +/* + * Miscellaneous assembly functions. + * + * Copyright (C) 2001 - 2007 Tensilica Inc. + * Copyright (C) 2014 - 2016 Cadence Design Systems Inc. + * + * Chris Zankel <chris@zankel.net> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + + +#include <linux/linkage.h> +#include <asm/asmmacro.h> +#include <asm/cacheasm.h> + +/* + * void __invalidate_icache_page(ulong start) + */ + +ENTRY(__invalidate_icache_page) + + abi_entry + + ___invalidate_icache_page a2 a3 + isync + + abi_ret + +ENDPROC(__invalidate_icache_page) + +/* + * void __invalidate_dcache_page(ulong start) + */ + +ENTRY(__invalidate_dcache_page) + + abi_entry + + ___invalidate_dcache_page a2 a3 + dsync + + abi_ret + +ENDPROC(__invalidate_dcache_page) + +/* + * void __flush_invalidate_dcache_page(ulong start) + */ + +ENTRY(__flush_invalidate_dcache_page) + + abi_entry + + ___flush_invalidate_dcache_page a2 a3 + + dsync + abi_ret + +ENDPROC(__flush_invalidate_dcache_page) + +/* + * void __flush_dcache_page(ulong start) + */ + +ENTRY(__flush_dcache_page) + + abi_entry + + ___flush_dcache_page a2 a3 + + dsync + abi_ret + +ENDPROC(__flush_dcache_page) + +/* + * void __invalidate_icache_range(ulong start, ulong size) + */ + +ENTRY(__invalidate_icache_range) + + abi_entry + + ___invalidate_icache_range a2 a3 a4 + isync + + abi_ret + +ENDPROC(__invalidate_icache_range) + +/* + * void __flush_invalidate_dcache_range(ulong start, ulong size) + */ + +ENTRY(__flush_invalidate_dcache_range) + + abi_entry + + ___flush_invalidate_dcache_range a2 a3 a4 + dsync + + abi_ret + +ENDPROC(__flush_invalidate_dcache_range) + +/* + * void _flush_dcache_range(ulong start, ulong size) + */ + +ENTRY(__flush_dcache_range) + + abi_entry + + ___flush_dcache_range a2 a3 a4 + dsync + + abi_ret + +ENDPROC(__flush_dcache_range) + +/* + * void _invalidate_dcache_range(ulong start, ulong size) + */ + +ENTRY(__invalidate_dcache_range) + + abi_entry + + ___invalidate_dcache_range a2 a3 a4 + + abi_ret + +ENDPROC(__invalidate_dcache_range) + +/* + * void _invalidate_icache_all(void) + */ + +ENTRY(__invalidate_icache_all) + + abi_entry + + ___invalidate_icache_all a2 a3 + isync + + abi_ret + +ENDPROC(__invalidate_icache_all) + +/* + * void _flush_invalidate_dcache_all(void) + */ + +ENTRY(__flush_invalidate_dcache_all) + + abi_entry + + ___flush_invalidate_dcache_all a2 a3 + dsync + + abi_ret + +ENDPROC(__flush_invalidate_dcache_all) + +/* + * void _invalidate_dcache_all(void) + */ + +ENTRY(__invalidate_dcache_all) + + abi_entry + + ___invalidate_dcache_all a2 a3 + dsync + + abi_ret + +ENDPROC(__invalidate_dcache_all) diff --git a/arch/xtensa/lib/relocate.c b/arch/xtensa/lib/relocate.c new file mode 100644 index 00000000000..3f747ec55a1 --- /dev/null +++ b/arch/xtensa/lib/relocate.c @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2016 Cadence Design Systems Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/relocate.h> +#include <asm/sections.h> +#include <asm/string.h> + +int clear_bss(void) +{ + size_t len = (size_t)&__bss_end - (size_t)&__bss_start; + + memset((void *)&__bss_start, 0x00, len); + return 0; +} + diff --git a/arch/xtensa/lib/time.c b/arch/xtensa/lib/time.c new file mode 100644 index 00000000000..1332072ffe3 --- /dev/null +++ b/arch/xtensa/lib/time.c @@ -0,0 +1,121 @@ +/* + * (C) Copyright 2008 - 2013 Tensilica Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/global_data.h> +#include <linux/stringify.h> + +DECLARE_GLOBAL_DATA_PTR; + +#if XCHAL_HAVE_CCOUNT +static ulong get_ccount(void) +{ + ulong ccount; + asm volatile ("rsr %0,"__stringify(CCOUNT) : "=a" (ccount)); + return ccount; +} +#else +static ulong fake_ccount; +#define get_ccount() fake_ccount +#endif + +static void delay_cycles(unsigned cycles) +{ +#if XCHAL_HAVE_CCOUNT + unsigned expiry = get_ccount() + cycles; + while ((signed)(expiry - get_ccount()) > 0) + ; +#else +#warning "Without Xtensa timer option, timing will not be accurate." + + /* + * Approximate the cycle count by a loop iteration count. + * This is highly dependent on config and optimization. + */ + + volatile unsigned i; + for (i = cycles >> 4U; i > 0; --i) + ; + fake_ccount += cycles; +#endif +} + +/* + * Delay (busy-wait) for a number of microseconds. + */ + +void __udelay(unsigned long usec) +{ + ulong lo, hi, i; + ulong mhz = CONFIG_SYS_CLK_FREQ / 1000000; + + /* Scale to support full 32-bit usec range */ + + lo = usec & ((1<<22)-1); + hi = usec >> 22UL; + for (i = 0; i < hi; ++i) + delay_cycles(mhz << 22); + delay_cycles(mhz * lo); +} + + +/* + * Return the elapsed time (ticks) since 'base'. + */ + +ulong get_timer(ulong base) +{ + /* Don't tie up a timer; use cycle counter if available (or fake it) */ + +#if XCHAL_HAVE_CCOUNT + register ulong ccount; + __asm__ volatile ("rsr %0, CCOUNT" : "=a"(ccount)); + return ccount / (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ) - base; +#else + /* + * Add at least the overhead of this call (in cycles). + * Avoids hanging in case caller doesn't use udelay(). + * Note that functions that don't call udelay() (such as + * the "sleep" command) will not get a significant delay + * because there is no time reference. + */ + + fake_ccount += 20; + return fake_ccount / (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ) - base; +#endif +} + + +/* + * This function is derived from ARM/PowerPC code (read timebase as long long). + * On Xtensa it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from ARM/PowerPC code (timebase clock frequency). + * On Xtensa it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + ulong tbclk; + + tbclk = CONFIG_SYS_HZ; + return tbclk; +} + +#if XCHAL_HAVE_CCOUNT +unsigned long timer_get_us(void) +{ + unsigned long ccount; + + __asm__ volatile ("rsr %0, CCOUNT" : "=a"(ccount)); + return ccount / (CONFIG_SYS_CLK_FREQ / 1000000); +} +#endif |