diff options
Diffstat (limited to 'arch')
239 files changed, 7886 insertions, 2028 deletions
diff --git a/arch/Kconfig b/arch/Kconfig index d8e3263f83..78532f56ca 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -78,6 +78,7 @@ config SANDBOX imply LZMA imply SCSI imply CMD_SATA + imply CMD_SF_TEST config SH bool "SuperH architecture" @@ -87,18 +88,32 @@ config X86 bool "x86 architecture" select CREATE_ARCH_SYMLINK select HAVE_PRIVATE_LIBGCC + select USE_PRIVATE_LIBGCC select SUPPORT_OF_CONTROL + select OF_CONTROL select DM - select DM_KEYBOARD - select DM_SERIAL - select DM_GPIO - select DM_SPI - select DM_SPI_FLASH - select USB_EHCI_HCD + select DM_PCI + select PCI + select TIMER + select X86_TSC_TIMER + imply BLK + imply DM_ETH + imply DM_GPIO + imply DM_KEYBOARD + imply DM_MMC + imply DM_RTC + imply DM_SERIAL + imply DM_SCSI + imply DM_SPI + imply DM_SPI_FLASH + imply DM_USB + imply DM_VIDEO imply CMD_FPGA_LOADMK imply CMD_GETTIME imply CMD_IO imply CMD_IRQ + imply CMD_SF_TEST + imply CMD_ZBOOT config XTENSA bool "Xtensa architecture" diff --git a/arch/arc/lib/bootm.c b/arch/arc/lib/bootm.c index 5798149046..a498ce5b29 100644 --- a/arch/arc/lib/bootm.c +++ b/arch/arc/lib/bootm.c @@ -85,7 +85,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) r2 = (unsigned int)images->ft_addr; } else { r0 = 1; - r2 = (unsigned int)getenv("bootargs"); + r2 = (unsigned int)env_get("bootargs"); } smp_set_core_boot_addr((unsigned long)kernel_entry, -1); diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 787f2b14a8..da9324b43c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -311,6 +311,7 @@ config TARGET_GPLUGD config ARCH_DAVINCI bool "TI DaVinci" select CPU_ARM926EJS + imply CMD_SAVES help Support for TI's DaVinci platform. @@ -412,21 +413,25 @@ config TARGET_SPEAR300 bool "Support spear300" select CPU_ARM926EJS select BOARD_EARLY_INIT_F + imply CMD_SAVES config TARGET_SPEAR310 bool "Support spear310" select CPU_ARM926EJS select BOARD_EARLY_INIT_F + imply CMD_SAVES config TARGET_SPEAR320 bool "Support spear320" select CPU_ARM926EJS select BOARD_EARLY_INIT_F + imply CMD_SAVES config TARGET_SPEAR600 bool "Support spear600" select CPU_ARM926EJS select BOARD_EARLY_INIT_F + imply CMD_SAVES config TARGET_STV0991 bool "Support stv0991" @@ -491,7 +496,6 @@ config ARCH_BCM283X select DM_GPIO select OF_CONTROL imply FAT_WRITE - imply ENV_IS_IN_FAT config TARGET_VEXPRESS_CA15_TC2 bool "Support vexpress_ca15_tc2" @@ -526,6 +530,9 @@ config TARGET_BCMCYGNUS imply CMD_HASH imply FAT_WRITE imply HASH_VERIFY + imply NETDEVICES + imply BCM_SF2_ETH + imply BCM_SF2_ETH_GMAC config TARGET_BCMNSP bool "Support bcmnsp" @@ -575,6 +582,7 @@ config ARCH_KEYSTONE select CMD_POWEROFF imply CMD_MTDPARTS imply FIT + imply CMD_SAVES config ARCH_OMAP2PLUS bool "TI OMAP2+" @@ -612,6 +620,11 @@ config ARCH_MX6 select SYS_FSL_SEC_LE select SYS_THUMB_BUILD if SPL +if ARCH_MX6 +config SPL_LDSCRIPT + default "arch/arm/mach-omap2/u-boot-spl.lds" +endif + config ARCH_MX5 bool "Freescale MX5" select CPU_V7 @@ -700,6 +713,7 @@ config ARCH_VF610 select CPU_V7 select SYS_FSL_ERRATUM_ESDHC111 imply CMD_MTDPARTS + imply NAND config ARCH_ZYNQ bool "Xilinx Zynq Platform" @@ -726,6 +740,7 @@ config ARCH_ZYNQ select CLK_ZYNQ imply CMD_CLK imply FAT_WRITE + imply CMD_SPL config ARCH_ZYNQMP bool "Support Xilinx ZynqMP Platform" @@ -1026,7 +1041,6 @@ config ARCH_UNIPHIER select SPL_PINCTRL if SPL select SUPPORT_SPL imply FAT_WRITE - imply ENV_IS_IN_MMC help Support for UniPhier SoC family developed by Socionext Inc. (formerly, System LSI Business Division of Panasonic Corporation) @@ -1225,3 +1239,10 @@ source "board/zipitz2/Kconfig" source "arch/arm/Kconfig.debug" endmenu + +config SPL_LDSCRIPT + default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if TARGET_APX4DEVKIT || TARGET_BG0900 || TARGET_M28EVK || TARGET_MX23_OLINUXINO || TARGET_MX23EVK || TARGET_MX28EVK || TARGET_SANSA_FUZE_PLUS || TARGET_SC_SPS_1 || TARGET_TS4600 || TARGET_XFI3 + default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136 + default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64 + + diff --git a/arch/arm/cpu/arm926ejs/spear/spl.c b/arch/arm/cpu/arm926ejs/spear/spl.c index a60f5838de..ba1e559157 100644 --- a/arch/arm/cpu/arm926ejs/spear/spl.c +++ b/arch/arm/cpu/arm926ejs/spear/spl.c @@ -222,7 +222,7 @@ static void snor_init(void) u32 spl_boot_device(void) { - u32 mode; + u32 mode = 0; /* Currently only SNOR is supported as the only */ if (snor_boot_selected()) { diff --git a/arch/arm/cpu/armv7/bcm235xx/clk-core.c b/arch/arm/cpu/armv7/bcm235xx/clk-core.c index 79fafa08ed..89e367be82 100644 --- a/arch/arm/cpu/armv7/bcm235xx/clk-core.c +++ b/arch/arm/cpu/armv7/bcm235xx/clk-core.c @@ -479,9 +479,9 @@ unsigned long clk_get_rate(struct clk *c) { unsigned long rate; - debug("%s: %s\n", __func__, c->name); if (!c || !c->ops || !c->ops->get_rate) return 0; + debug("%s: %s\n", __func__, c->name); rate = c->ops->get_rate(c); debug("%s: rate = %ld\n", __func__, rate); @@ -493,9 +493,9 @@ int clk_set_rate(struct clk *c, unsigned long rate) { int ret; - debug("%s: %s rate=%ld\n", __func__, c->name, rate); if (!c || !c->ops || !c->ops->set_rate) return -EINVAL; + debug("%s: %s rate=%ld\n", __func__, c->name, rate); if (c->use_cnt) return -EINVAL; diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-core.c b/arch/arm/cpu/armv7/bcm281xx/clk-core.c index cdc1264d7c..b061c20648 100644 --- a/arch/arm/cpu/armv7/bcm281xx/clk-core.c +++ b/arch/arm/cpu/armv7/bcm281xx/clk-core.c @@ -479,9 +479,9 @@ unsigned long clk_get_rate(struct clk *c) { unsigned long rate; - debug("%s: %s\n", __func__, c->name); if (!c || !c->ops || !c->ops->get_rate) return 0; + debug("%s: %s\n", __func__, c->name); rate = c->ops->get_rate(c); debug("%s: rate = %ld\n", __func__, rate); @@ -493,9 +493,9 @@ int clk_set_rate(struct clk *c, unsigned long rate) { int ret; - debug("%s: %s rate=%ld\n", __func__, c->name, rate); if (!c || !c->ops || !c->ops->set_rate) return -EINVAL; + debug("%s: %s rate=%ld\n", __func__, c->name, rate); if (c->use_cnt) return -EINVAL; diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 6a013b2183..fadfce4f05 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -15,6 +15,7 @@ config ARCH_LS1021A select SYS_FSL_SEC_COMPAT_5 select SYS_FSL_SEC_LE imply SCSI + imply CMD_PCI menu "LS102xA architecture" depends on ARCH_LS1021A diff --git a/arch/arm/cpu/armv7/vf610/generic.c b/arch/arm/cpu/armv7/vf610/generic.c index ac2d8d1a3f..88f3f4dd16 100644 --- a/arch/arm/cpu/armv7/vf610/generic.c +++ b/arch/arm/cpu/armv7/vf610/generic.c @@ -329,7 +329,7 @@ int arch_misc_init(void) strcpy(soc, "vf"); strcat(soc, soc_type); - setenv("soc", soc); + env_set("soc", soc); return 0; } diff --git a/arch/arm/cpu/armv7m/mpu.c b/arch/arm/cpu/armv7m/mpu.c index 31a243b49a..4622aa4826 100644 --- a/arch/arm/cpu/armv7m/mpu.c +++ b/arch/arm/cpu/armv7m/mpu.c @@ -68,6 +68,7 @@ void mpu_config(struct mpu_region_config *reg_config) break; case DEVICE_NON_SHARED: attr = (2 << TEX_SHIFT) | BUFFERABLE; + break; default: attr = 0; /* strongly ordered */ break; diff --git a/arch/arm/cpu/armv8/Makefile b/arch/arm/cpu/armv8/Makefile index c447085fe4..1249547436 100644 --- a/arch/arm/cpu/armv8/Makefile +++ b/arch/arm/cpu/armv8/Makefile @@ -8,7 +8,9 @@ extra-y := start.o obj-y += cpu.o +ifndef CONFIG_$(SPL_TPL_)TIMER obj-y += generic_timer.o +endif obj-y += cache_v8.o obj-y += exceptions.o obj-y += cache.o diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S index 7cba308ee7..ea845d1809 100644 --- a/arch/arm/cpu/armv8/cache.S +++ b/arch/arm/cpu/armv8/cache.S @@ -22,6 +22,7 @@ * x1: 0 clean & invalidate, 1 invalidate only * x2~x9: clobbered */ +.pushsection .text.__asm_dcache_level, "ax" ENTRY(__asm_dcache_level) lsl x12, x0, #1 msr csselr_el1, x12 /* select cache level */ @@ -58,6 +59,7 @@ loop_way: ret ENDPROC(__asm_dcache_level) +.popsection /* * void __asm_flush_dcache_all(int invalidate_only) @@ -66,6 +68,7 @@ ENDPROC(__asm_dcache_level) * * flush or invalidate all data cache by SET/WAY. */ +.pushsection .text.__asm_dcache_all, "ax" ENTRY(__asm_dcache_all) mov x1, x0 dsb sy @@ -102,16 +105,21 @@ skip: finished: ret ENDPROC(__asm_dcache_all) +.popsection +.pushsection .text.__asm_flush_dcache_all, "ax" ENTRY(__asm_flush_dcache_all) mov x0, #0 b __asm_dcache_all ENDPROC(__asm_flush_dcache_all) +.popsection +.pushsection .text.__asm_invalidate_dcache_all, "ax" ENTRY(__asm_invalidate_dcache_all) mov x0, #0x1 b __asm_dcache_all ENDPROC(__asm_invalidate_dcache_all) +.popsection /* * void __asm_flush_dcache_range(start, end) @@ -121,6 +129,7 @@ ENDPROC(__asm_invalidate_dcache_all) * x0: start address * x1: end address */ +.pushsection .text.__asm_flush_dcache_range, "ax" ENTRY(__asm_flush_dcache_range) mrs x3, ctr_el0 lsr x3, x3, #16 @@ -138,6 +147,7 @@ ENTRY(__asm_flush_dcache_range) dsb sy ret ENDPROC(__asm_flush_dcache_range) +.popsection /* * void __asm_invalidate_dcache_range(start, end) * @@ -146,6 +156,7 @@ ENDPROC(__asm_flush_dcache_range) * x0: start address * x1: end address */ +.pushsection .text.__asm_invalidate_dcache_range, "ax" ENTRY(__asm_invalidate_dcache_range) mrs x3, ctr_el0 ubfm x3, x3, #16, #19 @@ -162,41 +173,51 @@ ENTRY(__asm_invalidate_dcache_range) dsb sy ret ENDPROC(__asm_invalidate_dcache_range) +.popsection /* * void __asm_invalidate_icache_all(void) * * invalidate all tlb entries. */ +.pushsection .text.__asm_invalidate_icache_all, "ax" ENTRY(__asm_invalidate_icache_all) ic ialluis isb sy ret ENDPROC(__asm_invalidate_icache_all) +.popsection +.pushsection .text.__asm_invalidate_l3_dcache, "ax" ENTRY(__asm_invalidate_l3_dcache) mov x0, #0 /* return status as success */ ret ENDPROC(__asm_invalidate_l3_dcache) .weak __asm_invalidate_l3_dcache +.popsection +.pushsection .text.__asm_flush_l3_dcache, "ax" ENTRY(__asm_flush_l3_dcache) mov x0, #0 /* return status as success */ ret ENDPROC(__asm_flush_l3_dcache) .weak __asm_flush_l3_dcache +.popsection +.pushsection .text.__asm_invalidate_l3_icache, "ax" ENTRY(__asm_invalidate_l3_icache) mov x0, #0 /* return status as success */ ret ENDPROC(__asm_invalidate_l3_icache) .weak __asm_invalidate_l3_icache +.popsection /* * void __asm_switch_ttbr(ulong new_ttbr) * * Safely switches to a new page table. */ +.pushsection .text.__asm_switch_ttbr, "ax" ENTRY(__asm_switch_ttbr) /* x2 = SCTLR (alive throghout the function) */ switch_el x4, 3f, 2f, 1f @@ -244,3 +265,4 @@ ENTRY(__asm_switch_ttbr) ret x3 ENDPROC(__asm_switch_ttbr) +.popsection diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 5825f9b726..cdeef26fe5 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -27,6 +27,7 @@ config ARCH_LS1043A select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F imply SCSI + imply CMD_PCI config ARCH_LS1046A bool @@ -307,7 +308,7 @@ config SYS_FSL_DSPI_CLK_DIV default 2 help This is the divider that is used to derive DSPI clock from Platform - PLL, in another word DSPI_clk = Platform_PLL_freq / this_divider. + clock, in another word DSPI_clk = Platform_clk / this_divider. config SYS_FSL_DUART_CLK_DIV int "DUART clock divider" @@ -392,3 +393,6 @@ config SYS_MC_RSV_MEM_ALIGN help Reserved memory needs to be aligned for MC to use. Default value is 512MB. + +config SPL_LDSCRIPT + default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 619d9b7a0e..3136e3f3a2 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -497,9 +497,7 @@ slave_cpu: rev x0, x0 /* BE to LE conversion */ cpu_is_le: ldr x5, [x11, #24] - ldr x6, =IH_ARCH_DEFAULT - cmp x6, x5 - b.eq 1f + cbz x5, 1f #ifdef CONFIG_ARMV8_SWITCH_TO_EL1 adr x4, secondary_switch_to_el1 @@ -541,9 +539,7 @@ ENTRY(secondary_switch_to_el1) ldr x4, [x11] ldr x5, [x11, #24] - ldr x6, =IH_ARCH_DEFAULT - cmp x6, x5 - b.eq 2f + cbz x5, 2f ldr x5, =ES_TO_AARCH32 bl switch_to_el1 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c index 80fe1ade2e..ab61ac3662 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c @@ -29,9 +29,14 @@ void update_os_arch_secondary_cores(uint8_t os_arch) u64 *table = get_spin_tbl_addr(); int i; - for (i = 1; i < CONFIG_MAX_CPUS; i++) - table[i * WORDS_PER_SPIN_TABLE_ENTRY + - SPIN_TABLE_ELEM_OS_ARCH_IDX] = os_arch; + for (i = 1; i < CONFIG_MAX_CPUS; i++) { + if (os_arch == IH_ARCH_DEFAULT) + table[i * WORDS_PER_SPIN_TABLE_ENTRY + + SPIN_TABLE_ELEM_ARCH_COMP_IDX] = OS_ARCH_SAME; + else + table[i * WORDS_PER_SPIN_TABLE_ENTRY + + SPIN_TABLE_ELEM_ARCH_COMP_IDX] = OS_ARCH_DIFF; + } } #ifdef CONFIG_FSL_LSCH3 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index aee1ffa7d4..639e9d2ddc 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -95,7 +95,7 @@ static void erratum_a008514(void) static unsigned long get_internval_val_mhz(void) { - char *interval = getenv(PLATFORM_CYCLE_ENV_VAR); + char *interval = env_get(PLATFORM_CYCLE_ENV_VAR); /* * interval is the number of platform cycles(MHz) between * wake up events generated by EPU. diff --git a/arch/arm/cpu/armv8/tlb.S b/arch/arm/cpu/armv8/tlb.S index 945445bc37..6743111b6a 100644 --- a/arch/arm/cpu/armv8/tlb.S +++ b/arch/arm/cpu/armv8/tlb.S @@ -14,7 +14,8 @@ * void __asm_invalidate_tlb_all(void) * * invalidate all tlb entries. - */ +*/ +.pushsection .text.__asm_invalidate_tlb_all, "ax" ENTRY(__asm_invalidate_tlb_all) switch_el x9, 3f, 2f, 1f 3: tlbi alle3 @@ -31,3 +32,4 @@ ENTRY(__asm_invalidate_tlb_all) 0: ret ENDPROC(__asm_invalidate_tlb_all) +.popsection diff --git a/arch/arm/cpu/armv8/transition.S b/arch/arm/cpu/armv8/transition.S index ca07465376..7aa6935318 100644 --- a/arch/arm/cpu/armv8/transition.S +++ b/arch/arm/cpu/armv8/transition.S @@ -10,6 +10,7 @@ #include <linux/linkage.h> #include <asm/macro.h> +.pushsection .text.armv8_switch_to_el2, "ax" ENTRY(armv8_switch_to_el2) switch_el x6, 1f, 0f, 0f 0: @@ -30,7 +31,9 @@ ENTRY(armv8_switch_to_el2) br x4 1: armv8_switch_to_el2_m x4, x5, x6 ENDPROC(armv8_switch_to_el2) +.popsection +.pushsection .text.armv8_switch_to_el1, "ax" ENTRY(armv8_switch_to_el1) switch_el x6, 0f, 1f, 0f 0: @@ -40,7 +43,10 @@ ENTRY(armv8_switch_to_el1) br x4 1: armv8_switch_to_el1_m x4, x5, x6 ENDPROC(armv8_switch_to_el1) +.popsection +.pushsection .text.armv8_el2_to_aarch32, "ax" WEAK(armv8_el2_to_aarch32) ret ENDPROC(armv8_el2_to_aarch32) +.popsection diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig b/arch/arm/cpu/armv8/zynqmp/Kconfig index 5ac48ebc4d..5ffc9f6c86 100644 --- a/arch/arm/cpu/armv8/zynqmp/Kconfig +++ b/arch/arm/cpu/armv8/zynqmp/Kconfig @@ -56,6 +56,17 @@ config ZYNQMP_USB config SYS_MALLOC_F_LEN default 0x600 +config DEFINE_TCM_OCM_MMAP + bool "Define TCM and OCM memory in MMU Table" + help + This option if enabled defines the TCM and OCM memory and its + memory attributes in MMU table entry. + +config ZYNQMP_PSU_INIT_ENABLED + bool "Include psu_init" + help + Include psu_init to full u-boot. SPL include psu_init by default. + config SPL_ZYNQMP_ALT_BOOTMODE_ENABLED bool "Overwrite SPL bootmode" depends on SPL diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c index 94ecf90660..1b5066a826 100644 --- a/arch/arm/cpu/armv8/zynqmp/cpu.c +++ b/arch/arm/cpu/armv8/zynqmp/cpu.c @@ -38,6 +38,14 @@ static struct mm_region zynqmp_mem_map[] = { PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { +#if defined(CONFIG_DEFINE_TCM_OCM_MMAP) + .virt = 0xffe00000UL, + .phys = 0xffe00000UL, + .size = 0x00200000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { +#endif .virt = 0x400000000UL, .phys = 0x400000000UL, .size = 0x200000000UL, @@ -102,9 +110,8 @@ unsigned int zynqmp_get_silicon_version(void) #define ZYNQMP_MMIO_READ 0xC2000014 #define ZYNQMP_MMIO_WRITE 0xC2000013 -#ifndef CONFIG_SPL_BUILD -int invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3, - u32 *ret_payload) +int __maybe_unused invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, + u32 arg3, u32 *ret_payload) { /* * Added SIP service call Function Identifier @@ -164,28 +171,7 @@ void zynqmp_pmufw_version(void) } #endif -int zynqmp_mmio_write(const u32 address, - const u32 mask, - const u32 value) -{ - return invoke_smc(ZYNQMP_MMIO_WRITE, address, mask, value, 0, NULL); -} - -int zynqmp_mmio_read(const u32 address, u32 *value) -{ - u32 ret_payload[PAYLOAD_ARG_CNT]; - u32 ret; - - if (!value) - return -EINVAL; - - ret = invoke_smc(ZYNQMP_MMIO_READ, address, 0, 0, 0, ret_payload); - *value = ret_payload[1]; - - return ret; -} -#else -int zynqmp_mmio_write(const u32 address, +static int zynqmp_mmio_rawwrite(const u32 address, const u32 mask, const u32 value) { @@ -200,9 +186,40 @@ int zynqmp_mmio_write(const u32 address, return 0; } -int zynqmp_mmio_read(const u32 address, u32 *value) +static int zynqmp_mmio_rawread(const u32 address, u32 *value) { *value = readl((ulong)address); return 0; } -#endif + +int zynqmp_mmio_write(const u32 address, + const u32 mask, + const u32 value) +{ + if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) + return zynqmp_mmio_rawwrite(address, mask, value); + else if (!IS_ENABLED(CONFIG_SPL_BUILD)) + return invoke_smc(ZYNQMP_MMIO_WRITE, address, mask, + value, 0, NULL); + + return -EINVAL; +} + +int zynqmp_mmio_read(const u32 address, u32 *value) +{ + u32 ret_payload[PAYLOAD_ARG_CNT]; + u32 ret; + + if (!value) + return -EINVAL; + + if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) { + ret = zynqmp_mmio_rawread(address, value); + } else if (!IS_ENABLED(CONFIG_SPL_BUILD)) { + ret = invoke_smc(ZYNQMP_MMIO_READ, address, 0, 0, + 0, ret_payload); + *value = ret_payload[1]; + } + + return ret; +} diff --git a/arch/arm/cpu/armv8/zynqmp/mp.c b/arch/arm/cpu/armv8/zynqmp/mp.c index e10fc3136c..76f889ba7d 100644 --- a/arch/arm/cpu/armv8/zynqmp/mp.c +++ b/arch/arm/cpu/armv8/zynqmp/mp.c @@ -206,6 +206,21 @@ static void write_tcm_boot_trampoline(u32 boot_addr) } } +void initialize_tcm(bool mode) +{ + if (!mode) { + set_r5_tcm_mode(LOCK); + set_r5_halt_mode(HALT, LOCK); + enable_clock_r5(); + release_r5_reset(LOCK); + } else { + set_r5_tcm_mode(SPLIT); + set_r5_halt_mode(HALT, SPLIT); + enable_clock_r5(); + release_r5_reset(SPLIT); + } +} + int cpu_release(int nr, int argc, char * const argv[]) { if (nr >= ZYNQMP_CORE_APU0 && nr <= ZYNQMP_CORE_APU3) { diff --git a/arch/arm/cpu/armv8/zynqmp/spl.c b/arch/arm/cpu/armv8/zynqmp/spl.c index 26bf80ec52..468dc1dc4d 100644 --- a/arch/arm/cpu/armv8/zynqmp/spl.c +++ b/arch/arm/cpu/armv8/zynqmp/spl.c @@ -17,7 +17,7 @@ void board_init_f(ulong dummy) { - psu_init(); + board_early_init_f(); board_early_init_r(); #ifdef CONFIG_DEBUG_UART diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 132fa69fe5..2cbdb17ca5 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -42,6 +42,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-veyron-mickey.dtb \ rk3288-veyron-minnie.dtb \ rk3328-evb.dtb \ + rk3368-lion.dtb \ rk3368-sheep.dtb \ rk3368-geekbox.dtb \ rk3368-px5-evb.dtb \ @@ -132,13 +133,14 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \ zynq-topic-miami.dtb \ zynq-topic-miamilite.dtb \ zynq-topic-miamiplus.dtb \ + zynq-zturn-myir.dtb \ zynq-zc770-xm010.dtb \ zynq-zc770-xm011.dtb \ zynq-zc770-xm012.dtb \ zynq-zc770-xm013.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-ep108.dtb \ - zynqmp-zcu102.dtb \ + zynqmp-zcu102-revA.dtb \ zynqmp-zcu102-revB.dtb \ zynqmp-zc1751-xm015-dc1.dtb \ zynqmp-zc1751-xm016-dc2.dtb \ @@ -370,6 +372,12 @@ dtb-$(CONFIG_MX7) += imx7-colibri.dtb \ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb +dtb-$(CONFIG_RCAR_GEN3) += \ + r8a7795-h3ulcb.dtb \ + r8a7795-salvator-x.dtb \ + r8a7796-m3ulcb.dtb \ + r8a7796-salvator-x.dtb + dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \ keystone-k2l-evm.dtb \ keystone-k2e-evm.dtb \ @@ -377,6 +385,10 @@ dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \ keystone-k2g-generic.dtb \ keystone-k2g-ice.dtb +dtb-$(CONFIG_TARGET_AT91SAM9261EK) += at91sam9261ek.dtb + +dtb-$(CONFIG_TARGET_PM9263) += at91sam9263ek.dtb + dtb-$(CONFIG_TARGET_AT91SAM9263EK) += at91sam9263ek.dtb dtb-$(CONFIG_TARGET_AT91SAM9RLEK) += at91sam9rlek.dtb diff --git a/arch/arm/dts/at91sam9260.dtsi b/arch/arm/dts/at91sam9260.dtsi index 0f25e336da..69d9ceadaf 100644 --- a/arch/arm/dts/at91sam9260.dtsi +++ b/arch/arm/dts/at91sam9260.dtsi @@ -34,6 +34,7 @@ tcb1 = &tcb1; i2c0 = &i2c0; ssc0 = &ssc0; + spi0 = &spi0; }; cpus { #address-cells = <0>; diff --git a/arch/arm/dts/at91sam9260ek.dts b/arch/arm/dts/at91sam9260ek.dts index 086c8eae1c..67a2660c80 100644 --- a/arch/arm/dts/at91sam9260ek.dts +++ b/arch/arm/dts/at91sam9260ek.dts @@ -118,7 +118,7 @@ cs-gpios = <0>, <&pioC 11 0>, <0>, <0>; mtd_dataflash@0 { compatible = "atmel,at45", "atmel,dataflash"; - spi-max-frequency = <50000000>; + spi-max-frequency = <15000000>; reg = <1>; }; }; diff --git a/arch/arm/dts/at91sam9261.dtsi b/arch/arm/dts/at91sam9261.dtsi index 5e09de4eb9..69c2d6e416 100644 --- a/arch/arm/dts/at91sam9261.dtsi +++ b/arch/arm/dts/at91sam9261.dtsi @@ -30,6 +30,7 @@ ssc0 = &ssc0; ssc1 = &ssc1; ssc2 = &ssc2; + spi0 = &spi0; }; cpus { @@ -70,6 +71,7 @@ #address-cells = <1>; #size-cells = <1>; ranges; + u-boot,dm-pre-reloc; usb0: ohci@00500000 { compatible = "atmel,at91rm9200-ohci", "usb-ohci"; @@ -112,6 +114,7 @@ #address-cells = <1>; #size-cells = <1>; ranges; + u-boot,dm-pre-reloc; tcb0: timer@fffa0000 { compatible = "atmel,at91rm9200-tcb"; @@ -286,20 +289,61 @@ status = "disabled"; }; + pioA: gpio@fffff400 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff400 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioA_clk>; + u-boot,dm-pre-reloc; + }; + + pioB: gpio@fffff600 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff600 0x200>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioB_clk>; + u-boot,dm-pre-reloc; + }; + + pioC: gpio@fffff800 { + compatible = "atmel,at91rm9200-gpio"; + reg = <0xfffff800 0x200>; + interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioC_clk>; + u-boot,dm-pre-reloc; + }; + pinctrl@fffff400 { #address-cells = <1>; #size-cells = <1>; compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; ranges = <0xfffff400 0xfffff400 0x600>; - + reg = <0xfffff400 0x200 /* pioA */ + 0xfffff600 0x200 /* pioB */ + 0xfffff800 0x200 /* pioC */ + >; atmel,mux-mask = /* A B */ <0xffffffff 0xfffffff7>, /* pioA */ <0xffffffff 0xfffffff4>, /* pioB */ <0xffffffff 0xffffff07>; /* pioC */ + u-boot,dm-pre-reloc; /* shared pinctrl settings */ dbgu { + u-boot,dm-pre-reloc; pinctrl_dbgu: dbgu-0 { atmel,pins = <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE>, @@ -532,39 +576,6 @@ <AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; }; }; - - pioA: gpio@fffff400 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff400 0x200>; - interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioA_clk>; - }; - - pioB: gpio@fffff600 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff600 0x200>; - interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioB_clk>; - }; - - pioC: gpio@fffff800 { - compatible = "atmel,at91rm9200-gpio"; - reg = <0xfffff800 0x200>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; - #gpio-cells = <2>; - gpio-controller; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&pioC_clk>; - }; }; pmc: pmc@fffffc00 { @@ -575,6 +586,7 @@ #address-cells = <1>; #size-cells = <0>; #interrupt-cells = <1>; + u-boot,dm-pre-reloc; main_osc: main_osc { compatible = "atmel,at91rm9200-clk-main-osc"; @@ -589,7 +601,7 @@ clocks = <&main_osc>; }; - plla: pllack { + plla: pllack@0 { compatible = "atmel,at91rm9200-clk-pll"; #clock-cells = <0>; interrupts-extended = <&pmc AT91_PMC_LOCKA>; @@ -601,7 +613,7 @@ <190000000 240000000 2 1>; }; - pllb: pllbck { + pllb: pllbck@1 { compatible = "atmel,at91rm9200-clk-pll"; #clock-cells = <0>; interrupts-extended = <&pmc AT91_PMC_LOCKB>; @@ -619,6 +631,7 @@ clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>; atmel,clk-output-range = <0 94000000>; atmel,clk-divisors = <1 2 4 0>; + u-boot,dm-pre-reloc; }; usb: usbck { @@ -635,25 +648,25 @@ interrupt-parent = <&pmc>; clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>; - prog0: prog0 { + prog0: progi@0 { #clock-cells = <0>; reg = <0>; interrupts = <AT91_PMC_PCKRDY(0)>; }; - prog1: prog1 { + prog1: prog@1 { #clock-cells = <0>; reg = <1>; interrupts = <AT91_PMC_PCKRDY(1)>; }; - prog2: prog2 { + prog2: prog@2 { #clock-cells = <0>; reg = <2>; interrupts = <AT91_PMC_PCKRDY(2)>; }; - prog3: prog3 { + prog3: prog@3 { #clock-cells = <0>; reg = <3>; interrupts = <AT91_PMC_PCKRDY(3)>; @@ -665,49 +678,49 @@ #address-cells = <1>; #size-cells = <0>; - uhpck: uhpck { + uhpck: uhpck@6 { #clock-cells = <0>; reg = <6>; clocks = <&usb>; }; - udpck: udpck { + udpck: udpck@7 { #clock-cells = <0>; reg = <7>; clocks = <&usb>; }; - pck0: pck0 { + pck0: pck@8 { #clock-cells = <0>; reg = <8>; clocks = <&prog0>; }; - pck1: pck1 { + pck1: pck@9 { #clock-cells = <0>; reg = <9>; clocks = <&prog1>; }; - pck2: pck2 { + pck2: pck@10 { #clock-cells = <0>; reg = <10>; clocks = <&prog2>; }; - pck3: pck3 { + pck3: pck@11 { #clock-cells = <0>; reg = <11>; clocks = <&prog3>; }; - hclk0: hclk0 { + hclk0: hclk@16 { #clock-cells = <0>; reg = <16>; clocks = <&mck>; }; - hclk1: hclk1 { + hclk1: hclk@17 { #clock-cells = <0>; reg = <17>; clocks = <&mck>; @@ -719,98 +732,102 @@ #address-cells = <1>; #size-cells = <0>; clocks = <&mck>; + u-boot,dm-pre-reloc; - pioA_clk: pioA_clk { + pioA_clk: pioA_clk@2 { #clock-cells = <0>; reg = <2>; + u-boot,dm-pre-reloc; }; - pioB_clk: pioB_clk { + pioB_clk: pioB_clk@3 { #clock-cells = <0>; reg = <3>; + u-boot,dm-pre-reloc; }; - pioC_clk: pioC_clk { + pioC_clk: pioC_clk@4 { #clock-cells = <0>; reg = <4>; + u-boot,dm-pre-reloc; }; - usart0_clk: usart0_clk { + usart0_clk: usart0_clk@6 { #clock-cells = <0>; reg = <6>; }; - usart1_clk: usart1_clk { + usart1_clk: usart1_clk@7 { #clock-cells = <0>; reg = <7>; }; - usart2_clk: usart2_clk { + usart2_clk: usart2_clk@8 { #clock-cells = <0>; reg = <8>; }; - mci0_clk: mci0_clk { + mci0_clk: mci0_clk@9 { #clock-cells = <0>; reg = <9>; }; - udc_clk: udc_clk { + udc_clk: udc_clk@10 { #clock-cells = <0>; reg = <10>; }; - twi0_clk: twi0_clk { + twi0_clk: twi0_clk@11 { reg = <11>; #clock-cells = <0>; }; - spi0_clk: spi0_clk { + spi0_clk: spi0_clk@12 { #clock-cells = <0>; reg = <12>; }; - spi1_clk: spi1_clk { + spi1_clk: spi1_clk@13 { #clock-cells = <0>; reg = <13>; }; - ssc0_clk: ssc0_clk { + ssc0_clk: ssc0_clk@14 { #clock-cells = <0>; reg = <14>; }; - ssc1_clk: ssc1_clk { + ssc1_clk: ssc1_clk@15 { #clock-cells = <0>; reg = <15>; }; - ssc2_clk: ssc2_clk { + ssc2_clk: ssc2_clk@16 { #clock-cells = <0>; reg = <16>; }; - tc0_clk: tc0_clk { + tc0_clk: tc0_clk@17 { #clock-cells = <0>; reg = <17>; }; - tc1_clk: tc1_clk { + tc1_clk: tc1_clk@18 { #clock-cells = <0>; reg = <18>; }; - tc2_clk: tc2_clk { + tc2_clk: tc2_clk@19 { #clock-cells = <0>; reg = <19>; }; - ohci_clk: ohci_clk { + ohci_clk: ohci_clk@20 { #clock-cells = <0>; reg = <20>; }; - lcd_clk: lcd_clk { + lcd_clk: lcd_clk@21 { #clock-cells = <0>; reg = <21>; }; diff --git a/arch/arm/dts/at91sam9261ek.dts b/arch/arm/dts/at91sam9261ek.dts new file mode 100644 index 0000000000..55bd51f07f --- /dev/null +++ b/arch/arm/dts/at91sam9261ek.dts @@ -0,0 +1,211 @@ +/* + * at91sam9261ek.dts - Device Tree file for Atmel at91sam9261 reference board + * + * Copyright (C) 2013 Jean-Jacques Hiblot <jjhiblot@traphandler.com> + * + * Licensed under GPLv2 only. + */ +/dts-v1/; +#include "at91sam9261.dtsi" + +/ { + model = "Atmel at91sam9261ek"; + compatible = "atmel,at91sam9261ek", "atmel,at91sam9261", "atmel,at91sam9"; + + chosen { + bootargs = "rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs rw"; + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0x20000000 0x4000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <18432000>; + }; + }; + + ahb { + usb0: ohci@00500000 { + status = "okay"; + }; + + fb0: fb@0x00600000 { + display = <&display0>; + atmel,power-control-gpio = <&pioA 12 GPIO_ACTIVE_LOW>; + status = "okay"; + + display0: display { + bits-per-pixel = <16>; + atmel,lcdcon-backlight; + atmel,dmacon = <0x1>; + atmel,lcdcon2 = <0x80008002>; + atmel,guard-time = <1>; + atmel,lcd-wiring-mode = "BRG"; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <4965000>; + hactive = <240>; + vactive = <320>; + hback-porch = <1>; + hfront-porch = <33>; + vback-porch = <1>; + vfront-porch = <0>; + hsync-len = <5>; + vsync-len = <1>; + hsync-active = <1>; + vsync-active = <1>; + }; + }; + }; + }; + + nand0: nand@40000000 { + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + status = "okay"; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "bootloader"; + reg = <0x40000 0x80000>; + }; + + bootloaderenv@c0000 { + label = "bootloader env"; + reg = <0xc0000 0xc0000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x0f800000>; + }; + }; + + apb { + usb1: gadget@fffa4000 { + atmel,vbus-gpio = <&pioB 29 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + spi0: spi@fffc8000 { + cs-gpios = <&pioA 3 0>, <0>, <&pioA 28 0>, <0>; + status = "okay"; + + mtd_dataflash@0 { + compatible = "atmel,at45", "atmel,dataflash"; + reg = <0>; + spi-max-frequency = <15000000>; + }; + + tsc2046@0 { + reg = <2>; + compatible = "ti,ads7843"; + interrupts-extended = <&pioC 2 IRQ_TYPE_EDGE_BOTH>; + spi-max-frequency = <3000000>; + pendown-gpio = <&pioC 2 GPIO_ACTIVE_HIGH>; + + ti,x-min = /bits/ 16 <150>; + ti,x-max = /bits/ 16 <3830>; + ti,y-min = /bits/ 16 <190>; + ti,y-max = /bits/ 16 <3830>; + ti,vref-delay-usecs = /bits/ 16 <450>; + ti,x-plate-ohms = /bits/ 16 <450>; + ti,y-plate-ohms = /bits/ 16 <250>; + ti,pressure-max = /bits/ 16 <15000>; + ti,debounce-rep = /bits/ 16 <0>; + ti,debounce-tol = /bits/ 16 <65535>; + ti,debounce-max = /bits/ 16 <1>; + + wakeup-source; + }; + }; + + dbgu: serial@fffff200 { + status = "okay"; + }; + + watchdog@fffffd40 { + status = "okay"; + }; + + }; + }; + + leds { + compatible = "gpio-leds"; + + ds8 { + label = "ds8"; + gpios = <&pioA 13 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + }; + + ds7 { + label = "ds7"; + gpios = <&pioA 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "nand-disk"; + }; + + ds1 { + label = "ds1"; + gpios = <&pioA 23 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + button_0 { + label = "button_0"; + gpios = <&pioA 27 GPIO_ACTIVE_LOW>; + linux,code = <256>; + wakeup-source; + }; + + button_1 { + label = "button_1"; + gpios = <&pioA 26 GPIO_ACTIVE_LOW>; + linux,code = <257>; + wakeup-source; + }; + + button_2 { + label = "button_2"; + gpios = <&pioA 25 GPIO_ACTIVE_LOW>; + linux,code = <258>; + wakeup-source; + }; + + button_3 { + label = "button_3"; + gpios = <&pioA 24 GPIO_ACTIVE_LOW>; + linux,code = <259>; + wakeup-source; + }; + }; +}; diff --git a/arch/arm/dts/at91sam9263.dtsi b/arch/arm/dts/at91sam9263.dtsi index e899fd3f6a..0b594be221 100644 --- a/arch/arm/dts/at91sam9263.dtsi +++ b/arch/arm/dts/at91sam9263.dtsi @@ -32,6 +32,7 @@ ssc0 = &ssc0; ssc1 = &ssc1; pwm0 = &pwm0; + spi0 = &spi0; }; cpus { diff --git a/arch/arm/dts/at91sam9263ek.dts b/arch/arm/dts/at91sam9263ek.dts index 8cd7fada4f..35799b8a5e 100644 --- a/arch/arm/dts/at91sam9263ek.dts +++ b/arch/arm/dts/at91sam9263ek.dts @@ -87,7 +87,7 @@ cs-gpios = <&pioA 5 0>, <0>, <0>, <0>; mtd_dataflash@0 { compatible = "atmel,at45", "atmel,dataflash"; - spi-max-frequency = <50000000>; + spi-max-frequency = <15000000>; reg = <0>; }; }; diff --git a/arch/arm/dts/at91sam9g20ek_common.dtsi b/arch/arm/dts/at91sam9g20ek_common.dtsi index 65ae099119..9db245e442 100644 --- a/arch/arm/dts/at91sam9g20ek_common.dtsi +++ b/arch/arm/dts/at91sam9g20ek_common.dtsi @@ -99,7 +99,7 @@ cs-gpios = <0>, <&pioC 11 0>, <0>, <0>; mtd_dataflash@0 { compatible = "atmel,at45", "atmel,dataflash"; - spi-max-frequency = <50000000>; + spi-max-frequency = <15000000>; reg = <1>; }; }; diff --git a/arch/arm/dts/at91sam9rl.dtsi b/arch/arm/dts/at91sam9rl.dtsi index 8249994878..4602cd21e1 100644 --- a/arch/arm/dts/at91sam9rl.dtsi +++ b/arch/arm/dts/at91sam9rl.dtsi @@ -34,6 +34,7 @@ ssc0 = &ssc0; ssc1 = &ssc1; pwm0 = &pwm0; + spi0 = &spi0; }; cpus { diff --git a/arch/arm/dts/at91sam9xe.dtsi b/arch/arm/dts/at91sam9xe.dtsi new file mode 100644 index 0000000000..0278f63b2d --- /dev/null +++ b/arch/arm/dts/at91sam9xe.dtsi @@ -0,0 +1,60 @@ +/* + * at91sam9xe.dtsi - Device Tree Include file for AT91SAM9XE family SoC + * + * Copyright (C) 2015 Atmel, + * 2015 Alexandre Belloni <alexandre.Belloni@free-electrons.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "at91sam9260.dtsi" + +/ { + model = "Atmel AT91SAM9XE family SoC"; + compatible = "atmel,at91sam9xe", "atmel,at91sam9260"; + + sram0: sram@002ff000 { + status = "disabled"; + }; + + sram1: sram@00300000 { + compatible = "mmio-sram"; + reg = <0x00300000 0x4000>; + }; +}; diff --git a/arch/arm/dts/ethernut5.dts b/arch/arm/dts/ethernut5.dts new file mode 100644 index 0000000000..e07715225f --- /dev/null +++ b/arch/arm/dts/ethernut5.dts @@ -0,0 +1,94 @@ +/* + * ethernut5.dts - Device Tree file for Ethernut 5 board + * + * Copyright (C) 2012 egnite GmbH <info@egnite.de> + * + * Licensed under GPLv2. + */ +/dts-v1/; +#include "at91sam9xe.dtsi" + +/ { + model = "Ethernut 5"; + compatible = "egnite,ethernut5", "atmel,at91sam9260", "atmel,at91sam9"; + + chosen { + bootargs = "console=ttyS0,115200 root=/dev/mtdblock0 rw rootfstype=jffs2"; + }; + + memory { + reg = <0x20000000 0x08000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <18432000>; + }; + }; + + ahb { + apb { + dbgu: serial@fffff200 { + status = "okay"; + }; + + usart0: serial@fffb0000 { + status = "okay"; + }; + + usart1: serial@fffb4000 { + status = "okay"; + }; + + macb0: ethernet@fffc4000 { + phy-mode = "rmii"; + status = "okay"; + }; + + usb1: gadget@fffa4000 { + atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + }; + + nand0: nand@40000000 { + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + status = "okay"; + + gpios = <0 + &pioC 14 GPIO_ACTIVE_HIGH + 0 + >; + + root@0 { + label = "root"; + reg = <0x0 0x08000000>; + }; + + data@20000 { + label = "data"; + reg = <0x08000000 0x38000000>; + }; + }; + + usb0: ohci@00500000 { + num-ports = <2>; + status = "okay"; + }; + }; + + i2c-gpio-0 { + status = "okay"; + + pcf8563@50 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + }; +}; diff --git a/arch/arm/dts/r8a7795-h3ulcb.dts b/arch/arm/dts/r8a7795-h3ulcb.dts new file mode 100644 index 0000000000..ab352159de --- /dev/null +++ b/arch/arm/dts/r8a7795-h3ulcb.dts @@ -0,0 +1,376 @@ +/* + * Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) board + * + * Copyright (C) 2016 Renesas Electronics Corp. + * Copyright (C) 2016 Cogent Embedded, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r8a7795.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + model = "Renesas H3ULCB board based on r8a7795"; + compatible = "renesas,h3ulcb", "renesas,r8a7795"; + + aliases { + serial0 = &scif2; + ethernet0 = &avb; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x38000000>; + }; + + memory@500000000 { + device_type = "memory"; + reg = <0x5 0x00000000 0x0 0x40000000>; + }; + + memory@600000000 { + device_type = "memory"; + reg = <0x6 0x00000000 0x0 0x40000000>; + }; + + memory@700000000 { + device_type = "memory"; + reg = <0x7 0x00000000 0x0 0x40000000>; + }; + + leds { + compatible = "gpio-leds"; + + led5 { + gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; + }; + led6 { + gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; + }; + }; + + keyboard { + compatible = "gpio-keys"; + + key-1 { + linux,code = <KEY_1>; + label = "SW3"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + }; + }; + + x12_clk: x12 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + + reg_1p8v: regulator0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator1 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_sdhi0: regulator-vcc-sdhi0 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; + + audio_clkout: audio-clkout { + /* + * This is same as <&rcar_sound 0> + * but needed to avoid cs2000/rcar_sound probe dead-lock + */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <11289600>; + }; + + rsnd_ak4613: sound { + compatible = "simple-audio-card"; + + simple-audio-card,format = "left_j"; + simple-audio-card,bitclock-master = <&sndcpu>; + simple-audio-card,frame-master = <&sndcpu>; + + sndcpu: simple-audio-card,cpu { + sound-dai = <&rcar_sound>; + }; + + sndcodec: simple-audio-card,codec { + sound-dai = <&ak4613>; + }; + }; +}; + +&extal_clk { + clock-frequency = <16666666>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + scif2_pins: scif2 { + groups = "scif2_data_a"; + function = "scif2"; + }; + + scif_clk_pins: scif_clk { + groups = "scif_clk_a"; + function = "scif_clk"; + }; + + i2c2_pins: i2c2 { + groups = "i2c2_a"; + function = "i2c2"; + }; + + avb_pins: avb { + groups = "avb_mdc"; + function = "avb"; + }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <3300>; + }; + + sdhi0_pins_uhs: sd0_uhs { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <1800>; + }; + + sdhi2_pins: sd2 { + groups = "sdhi2_data8", "sdhi2_ctrl"; + function = "sdhi2"; + power-source = <3300>; + }; + + sdhi2_pins_uhs: sd2_uhs { + groups = "sdhi2_data8", "sdhi2_ctrl"; + function = "sdhi2"; + power-source = <1800>; + }; + + sound_pins: sound { + groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a"; + function = "ssi"; + }; + + sound_clk_pins: sound-clk { + groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a", + "audio_clkout_a", "audio_clkout3_a"; + function = "audio_clk"; + }; + + usb1_pins: usb1 { + groups = "usb1"; + function = "usb1"; + }; +}; + +&scif2 { + pinctrl-0 = <&scif2_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&scif_clk { + clock-frequency = <14745600>; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + + status = "okay"; + + clock-frequency = <100000>; + + ak4613: codec@10 { + compatible = "asahi-kasei,ak4613"; + #sound-dai-cells = <0>; + reg = <0x10>; + clocks = <&rcar_sound 3>; + + asahi-kasei,in1-single-end; + asahi-kasei,in2-single-end; + asahi-kasei,out1-single-end; + asahi-kasei,out2-single-end; + asahi-kasei,out3-single-end; + asahi-kasei,out4-single-end; + asahi-kasei,out5-single-end; + asahi-kasei,out6-single-end; + }; + + cs2000: clk-multiplier@4f { + #clock-cells = <0>; + compatible = "cirrus,cs2000-cp"; + reg = <0x4f>; + clocks = <&audio_clkout>, <&x12_clk>; + clock-names = "clk_in", "ref_clk"; + + assigned-clocks = <&cs2000>; + assigned-clock-rates = <24576000>; /* 1/1 divide */ + }; +}; + +&rcar_sound { + pinctrl-0 = <&sound_pins &sound_clk_pins>; + pinctrl-names = "default"; + + /* Single DAI */ + #sound-dai-cells = <0>; + + /* audio_clkout0/1/2/3 */ + #clock-cells = <1>; + clock-frequency = <11289600>; + + status = "okay"; + + /* update <audio_clk_b> to <cs2000> */ + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&cs2000>, + <&audio_clk_c>, + <&cpg CPG_CORE R8A7795_CLK_S0D4>; + + rcar_sound,dai { + dai0 { + playback = <&ssi0 &src0 &dvc0>; + capture = <&ssi1 &src1 &dvc1>; + }; + }; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi0>; + vqmmc-supply = <&vccq_sdhi0>; + cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + sd-uhs-sdr50; + status = "okay"; +}; + +&sdhi2 { + /* used for on-board 8bit eMMC */ + pinctrl-0 = <&sdhi2_pins>; + pinctrl-1 = <&sdhi2_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&ssi1 { + shared-pin; +}; + +&wdt0 { + timeout-sec = <60>; + status = "okay"; +}; + +&audio_clk_a { + clock-frequency = <22579200>; +}; + +&avb { + pinctrl-0 = <&avb_pins>; + pinctrl-names = "default"; + renesas,no-ether-link; + phy-handle = <&phy0>; + status = "okay"; + + phy0: ethernet-phy@0 { + rxc-skew-ps = <1500>; + reg = <0>; + interrupt-parent = <&gpio2>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&usb2_phy1 { + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; diff --git a/arch/arm/dts/r8a7795-salvator-x.dts b/arch/arm/dts/r8a7795-salvator-x.dts new file mode 100644 index 0000000000..639aa085d9 --- /dev/null +++ b/arch/arm/dts/r8a7795-salvator-x.dts @@ -0,0 +1,584 @@ +/* + * Device Tree Source for the Salvator-X board + * + * Copyright (C) 2015 Renesas Electronics Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/* + * SSI-AK4613 + * + * This command is required when Playback/Capture + * + * amixer set "DVC Out" 100% + * amixer set "DVC In" 100% + * + * You can use Mute + * + * amixer set "DVC Out Mute" on + * amixer set "DVC In Mute" on + * + * You can use Volume Ramp + * + * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps" + * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps" + * amixer set "DVC Out Ramp" on + * aplay xxx.wav & + * amixer set "DVC Out" 80% // Volume Down + * amixer set "DVC Out" 100% // Volume Up + */ + +/dts-v1/; +#include "r8a7795.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Renesas Salvator-X board based on r8a7795"; + compatible = "renesas,salvator-x", "renesas,r8a7795"; + + aliases { + serial0 = &scif2; + serial1 = &scif1; + ethernet0 = &avb; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + stdout-path = "serial0:115200n8"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x38000000>; + }; + + x12_clk: x12 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + + reg_1p8v: regulator0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator1 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_sdhi0: regulator-vcc-sdhi0 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; + + vcc_sdhi3: regulator-vcc-sdhi3 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI3 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi3: regulator-vccq-sdhi3 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI3 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; + + vbus0_usb2: regulator-vbus0-usb2 { + compatible = "regulator-fixed"; + + regulator-name = "USB20_VBUS0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio6 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + audio_clkout: audio_clkout { + /* + * This is same as <&rcar_sound 0> + * but needed to avoid cs2000/rcar_sound probe dead-lock + */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <11289600>; + }; + + rsnd_ak4613: sound { + compatible = "simple-audio-card"; + + simple-audio-card,format = "left_j"; + simple-audio-card,bitclock-master = <&sndcpu>; + simple-audio-card,frame-master = <&sndcpu>; + + sndcpu: simple-audio-card,cpu { + sound-dai = <&rcar_sound>; + }; + + sndcodec: simple-audio-card,codec { + sound-dai = <&ak4613>; + }; + }; + + vga-encoder { + compatible = "adi,adv7123"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7123_in: endpoint { + remote-endpoint = <&du_out_rgb>; + }; + }; + port@1 { + reg = <1>; + adv7123_out: endpoint { + remote-endpoint = <&vga_in>; + }; + }; + }; + }; + + vga { + compatible = "vga-connector"; + + port { + vga_in: endpoint { + remote-endpoint = <&adv7123_out>; + }; + }; + }; +}; + +&du { + pinctrl-0 = <&du_pins>; + pinctrl-names = "default"; + status = "okay"; + + ports { + port@0 { + endpoint { + remote-endpoint = <&adv7123_in>; + }; + }; + port@3 { + lvds_connector: endpoint { + }; + }; + }; +}; + +&extal_clk { + clock-frequency = <16666666>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + scif1_pins: scif1 { + groups = "scif1_data_a", "scif1_ctrl"; + function = "scif1"; + }; + scif2_pins: scif2 { + groups = "scif2_data_a"; + function = "scif2"; + }; + scif_clk_pins: scif_clk { + groups = "scif_clk_a"; + function = "scif_clk"; + }; + + i2c2_pins: i2c2 { + groups = "i2c2_a"; + function = "i2c2"; + }; + + avb_pins: avb { + mux { + groups = "avb_link", "avb_phy_int", "avb_mdc", + "avb_mii"; + function = "avb"; + }; + + pins_mdc { + groups = "avb_mdc"; + drive-strength = <24>; + }; + + pins_mii_tx { + pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0", + "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3"; + drive-strength = <12>; + }; + }; + + du_pins: du { + groups = "du_rgb888", "du_sync", "du_oddf", "du_clk_out_0"; + function = "du"; + }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <3300>; + }; + + sdhi0_pins_uhs: sd0_uhs { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <1800>; + }; + + sdhi2_pins: sd2 { + groups = "sdhi2_data8", "sdhi2_ctrl"; + function = "sdhi2"; + power-source = <3300>; + }; + + sdhi2_pins_uhs: sd2_uhs { + groups = "sdhi2_data8", "sdhi2_ctrl"; + function = "sdhi2"; + power-source = <1800>; + }; + + sdhi3_pins: sd3 { + groups = "sdhi3_data4", "sdhi3_ctrl"; + function = "sdhi3"; + power-source = <3300>; + }; + + sdhi3_pins_uhs: sd3_uhs { + groups = "sdhi3_data4", "sdhi3_ctrl"; + function = "sdhi3"; + power-source = <1800>; + }; + + sound_pins: sound { + groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a"; + function = "ssi"; + }; + + sound_clk_pins: sound_clk { + groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a", + "audio_clkout_a", "audio_clkout3_a"; + function = "audio_clk"; + }; + + usb0_pins: usb0 { + groups = "usb0"; + function = "usb0"; + }; + + usb1_pins: usb1 { + mux { + groups = "usb1"; + function = "usb1"; + }; + + ovc { + pins = "GP_6_27"; + bias-pull-up; + }; + + pwen { + pins = "GP_6_26"; + bias-pull-down; + }; + }; + + usb2_pins: usb2 { + groups = "usb2"; + function = "usb2"; + }; +}; + +&scif1 { + pinctrl-0 = <&scif1_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; +}; + +&scif2 { + pinctrl-0 = <&scif2_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&scif_clk { + clock-frequency = <14745600>; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + + status = "okay"; + + clock-frequency = <100000>; + + ak4613: codec@10 { + compatible = "asahi-kasei,ak4613"; + #sound-dai-cells = <0>; + reg = <0x10>; + clocks = <&rcar_sound 3>; + + asahi-kasei,in1-single-end; + asahi-kasei,in2-single-end; + asahi-kasei,out1-single-end; + asahi-kasei,out2-single-end; + asahi-kasei,out3-single-end; + asahi-kasei,out4-single-end; + asahi-kasei,out5-single-end; + asahi-kasei,out6-single-end; + }; + + cs2000: clk_multiplier@4f { + #clock-cells = <0>; + compatible = "cirrus,cs2000-cp"; + reg = <0x4f>; + clocks = <&audio_clkout>, <&x12_clk>; + clock-names = "clk_in", "ref_clk"; + + assigned-clocks = <&cs2000>; + assigned-clock-rates = <24576000>; /* 1/1 divide */ + }; +}; + +&rcar_sound { + pinctrl-0 = <&sound_pins &sound_clk_pins>; + pinctrl-names = "default"; + + /* Single DAI */ + #sound-dai-cells = <0>; + + /* audio_clkout0/1/2/3 */ + #clock-cells = <1>; + clock-frequency = <11289600>; + + status = "okay"; + + /* update <audio_clk_b> to <cs2000> */ + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&cs2000>, + <&audio_clk_c>, + <&cpg CPG_CORE R8A7795_CLK_S0D4>; + + rcar_sound,dai { + dai0 { + playback = <&ssi0 &src0 &dvc0>; + capture = <&ssi1 &src1 &dvc1>; + }; + }; +}; + +&sata { + status = "okay"; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi0>; + vqmmc-supply = <&vccq_sdhi0>; + cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; + bus-width = <4>; + sd-uhs-sdr50; + status = "okay"; +}; + +&sdhi2 { + /* used for on-board 8bit eMMC */ + pinctrl-0 = <&sdhi2_pins>; + pinctrl-1 = <&sdhi2_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&sdhi3 { + pinctrl-0 = <&sdhi3_pins>; + pinctrl-1 = <&sdhi3_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi3>; + vqmmc-supply = <&vccq_sdhi3>; + cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; + bus-width = <4>; + sd-uhs-sdr50; + status = "okay"; +}; + +&ssi1 { + shared-pin; +}; + +&wdt0 { + timeout-sec = <60>; + status = "okay"; +}; + +&audio_clk_a { + clock-frequency = <22579200>; +}; + +&i2c_dvfs { + status = "okay"; +}; + +&avb { + pinctrl-0 = <&avb_pins>; + pinctrl-names = "default"; + renesas,no-ether-link; + phy-handle = <&phy0>; + status = "okay"; + + phy0: ethernet-phy@0 { + rxc-skew-ps = <1500>; + reg = <0>; + interrupt-parent = <&gpio2>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&xhci0 { + status = "okay"; +}; + +&usb2_phy0 { + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; + + vbus-supply = <&vbus0_usb2>; + status = "okay"; +}; + +&usb2_phy1 { + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&usb2_phy2 { + pinctrl-0 = <&usb2_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +&hsusb { + status = "okay"; +}; + +&pcie_bus_clk { + clock-frequency = <100000000>; +}; + +&pciec0 { + status = "okay"; +}; + +&pciec1 { + status = "okay"; +}; diff --git a/arch/arm/dts/r8a7795.dtsi b/arch/arm/dts/r8a7795.dtsi new file mode 100644 index 0000000000..e99d6443b3 --- /dev/null +++ b/arch/arm/dts/r8a7795.dtsi @@ -0,0 +1,1866 @@ +/* + * Device Tree Source for the r8a7795 SoC + * + * Copyright (C) 2015 Renesas Electronics Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include <dt-bindings/clock/r8a7795-cpg-mssr.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/power/r8a7795-sysc.h> + +/ { + compatible = "renesas,r8a7795"; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c_dvfs; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + a57_0: cpu@0 { + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x0>; + device_type = "cpu"; + power-domains = <&sysc R8A7795_PD_CA57_CPU0>; + next-level-cache = <&L2_CA57>; + enable-method = "psci"; + }; + + a57_1: cpu@1 { + compatible = "arm,cortex-a57","arm,armv8"; + reg = <0x1>; + device_type = "cpu"; + power-domains = <&sysc R8A7795_PD_CA57_CPU1>; + next-level-cache = <&L2_CA57>; + enable-method = "psci"; + }; + + a57_2: cpu@2 { + compatible = "arm,cortex-a57","arm,armv8"; + reg = <0x2>; + device_type = "cpu"; + power-domains = <&sysc R8A7795_PD_CA57_CPU2>; + next-level-cache = <&L2_CA57>; + enable-method = "psci"; + }; + + a57_3: cpu@3 { + compatible = "arm,cortex-a57","arm,armv8"; + reg = <0x3>; + device_type = "cpu"; + power-domains = <&sysc R8A7795_PD_CA57_CPU3>; + next-level-cache = <&L2_CA57>; + enable-method = "psci"; + }; + + a53_0: cpu@100 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x100>; + device_type = "cpu"; + power-domains = <&sysc R8A7795_PD_CA53_CPU0>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + + a53_1: cpu@101 { + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x101>; + device_type = "cpu"; + power-domains = <&sysc R8A7795_PD_CA53_CPU1>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + + a53_2: cpu@102 { + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x102>; + device_type = "cpu"; + power-domains = <&sysc R8A7795_PD_CA53_CPU2>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + + a53_3: cpu@103 { + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x103>; + device_type = "cpu"; + power-domains = <&sysc R8A7795_PD_CA53_CPU3>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + + L2_CA57: cache-controller-0 { + compatible = "cache"; + power-domains = <&sysc R8A7795_PD_CA57_SCU>; + cache-unified; + cache-level = <2>; + }; + + L2_CA53: cache-controller-1 { + compatible = "cache"; + power-domains = <&sysc R8A7795_PD_CA53_SCU>; + cache-unified; + cache-level = <2>; + }; + }; + + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + extalr_clk: extalr { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + /* + * The external audio clocks are configured as 0 Hz fixed frequency + * clocks by default. + * Boards that provide audio clocks should override them. + */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* External CAN clock - to be overridden by boards that provide it */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* External SCIF clock - to be overridden by boards that provide it */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@f1010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1010000 0 0x1000>, + <0x0 0xf1020000 0 0x20000>, + <0x0 0xf1040000 0 0x20000>, + <0x0 0xf1060000 0 0x20000>; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; + + wdt0: watchdog@e6020000 { + compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt"; + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; + }; + + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a7795", + "renesas,gpio-rcar"; + reg = <0 0xe6050000 0 0x50>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 16>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 912>; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a7795", + "renesas,gpio-rcar"; + reg = <0 0xe6051000 0 0x50>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 28>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 911>; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a7795", + "renesas,gpio-rcar"; + reg = <0 0xe6052000 0 0x50>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 15>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 910>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a7795", + "renesas,gpio-rcar"; + reg = <0 0xe6053000 0 0x50>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 16>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 909>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a7795", + "renesas,gpio-rcar"; + reg = <0 0xe6054000 0 0x50>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 18>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 908>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a7795", + "renesas,gpio-rcar"; + reg = <0 0xe6055000 0 0x50>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 907>; + }; + + gpio6: gpio@e6055400 { + compatible = "renesas,gpio-r8a7795", + "renesas,gpio-rcar"; + reg = <0 0xe6055400 0 0x50>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 906>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 906>; + }; + + gpio7: gpio@e6055800 { + compatible = "renesas,gpio-r8a7795", + "renesas,gpio-rcar"; + reg = <0 0xe6055800 0 0x50>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 224 4>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 905>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 905>; + }; + + pmu_a57 { + compatible = "arm,cortex-a57-pmu"; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&a57_0>, + <&a57_1>, + <&a57_2>, + <&a57_3>; + }; + + pmu_a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&a53_0>, + <&a53_1>, + <&a53_2>, + <&a53_3>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7795-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a7795-rst"; + reg = <0 0xe6160000 0 0x0200>; + }; + + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7795-sysc"; + reg = <0 0xe6180000 0 0x0400>; + #power-domain-cells = <1>; + }; + + pfc: pfc@e6060000 { + compatible = "renesas,pfc-r8a7795"; + reg = <0 0xe6060000 0 0x50c>; + }; + + intc_ex: interrupt-controller@e61c0000 { + compatible = "renesas,intc-ex-r8a7795", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 407>; + }; + + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a7795", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x10000>; + interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <16>; + }; + + dmac1: dma-controller@e7300000 { + compatible = "renesas,dmac-r8a7795", + "renesas,rcar-dmac"; + reg = <0 0xe7300000 0 0x10000>; + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <16>; + }; + + dmac2: dma-controller@e7310000 { + compatible = "renesas,dmac-r8a7795", + "renesas,rcar-dmac"; + reg = <0 0xe7310000 0 0x10000>; + interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 217>; + clock-names = "fck"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 217>; + #dma-cells = <1>; + dma-channels = <16>; + }; + + audma0: dma-controller@ec700000 { + compatible = "renesas,dmac-r8a7795", + "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 502>; + clock-names = "fck"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 502>; + #dma-cells = <1>; + dma-channels = <16>; + }; + + audma1: dma-controller@ec720000 { + compatible = "renesas,dmac-r8a7795", + "renesas,rcar-dmac"; + reg = <0 0xec720000 0 0x10000>; + interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 501>; + clock-names = "fck"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 501>; + #dma-cells = <1>; + dma-channels = <16>; + }; + + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a7795", + "renesas,etheravb-rcar-gen3"; + reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 812>; + phy-mode = "rgmii-txid"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + can0: can@e6c30000 { + compatible = "renesas,can-r8a7795", + "renesas,rcar-gen3-can"; + reg = <0 0xe6c30000 0 0x1000>; + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A7795_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 916>; + status = "disabled"; + }; + + can1: can@e6c38000 { + compatible = "renesas,can-r8a7795", + "renesas,rcar-gen3-can"; + reg = <0 0xe6c38000 0 0x1000>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A7795_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 915>; + status = "disabled"; + }; + + canfd: can@e66c0000 { + compatible = "renesas,r8a7795-canfd", + "renesas,rcar-gen3-canfd"; + reg = <0 0xe66c0000 0 0x8000>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 914>, + <&cpg CPG_CORE R8A7795_CLK_CANFD>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 914>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + + channel1 { + status = "disabled"; + }; + }; + + hscif0: serial@e6540000 { + compatible = "renesas,hscif-r8a7795", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6540000 0 96>; + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 520>, + <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x31>, <&dmac1 0x30>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 520>; + status = "disabled"; + }; + + hscif1: serial@e6550000 { + compatible = "renesas,hscif-r8a7795", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6550000 0 96>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 519>, + <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x33>, <&dmac1 0x32>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 519>; + status = "disabled"; + }; + + hscif2: serial@e6560000 { + compatible = "renesas,hscif-r8a7795", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6560000 0 96>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 518>, + <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x35>, <&dmac1 0x34>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 518>; + status = "disabled"; + }; + + hscif3: serial@e66a0000 { + compatible = "renesas,hscif-r8a7795", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe66a0000 0 96>; + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 517>, + <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x37>, <&dmac0 0x36>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 517>; + status = "disabled"; + }; + + hscif4: serial@e66b0000 { + compatible = "renesas,hscif-r8a7795", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe66b0000 0 96>; + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 516>, + <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x38>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 516>; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7795", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 207>, + <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x51>, <&dmac1 0x50>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 207>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7795", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 206>, + <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x53>, <&dmac1 0x52>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 206>; + status = "disabled"; + }; + + scif2: serial@e6e88000 { + compatible = "renesas,scif-r8a7795", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e88000 0 64>; + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 310>, + <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x13>, <&dmac1 0x12>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 310>; + status = "disabled"; + }; + + scif3: serial@e6c50000 { + compatible = "renesas,scif-r8a7795", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c50000 0 64>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 204>, + <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x57>, <&dmac0 0x56>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 204>; + status = "disabled"; + }; + + scif4: serial@e6c40000 { + compatible = "renesas,scif-r8a7795", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c40000 0 64>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 203>, + <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x59>, <&dmac0 0x58>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 203>; + status = "disabled"; + }; + + scif5: serial@e6f30000 { + compatible = "renesas,scif-r8a7795", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6f30000 0 64>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 202>, + <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x5b>, <&dmac1 0x5a>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 202>; + status = "disabled"; + }; + + i2c_dvfs: i2c@e60b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7795", + "renesas,rcar-gen3-iic", + "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 926>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 926>; + status = "disabled"; + }; + + i2c0: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7795", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6500000 0 0x40>; + interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 931>; + dmas = <&dmac1 0x91>, <&dmac1 0x90>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c1: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7795", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 930>; + dmas = <&dmac1 0x93>, <&dmac1 0x92>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c2: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7795", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6510000 0 0x40>; + interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 929>; + dmas = <&dmac1 0x95>, <&dmac1 0x94>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c3: i2c@e66d0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7795", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d0000 0 0x40>; + interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 928>; + dmas = <&dmac0 0x97>, <&dmac0 0x96>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c4: i2c@e66d8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7795", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d8000 0 0x40>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 927>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 927>; + dmas = <&dmac0 0x99>, <&dmac0 0x98>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c5: i2c@e66e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7795", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66e0000 0 0x40>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 919>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 919>; + dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c6: i2c@e66e8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7795", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66e8000 0 0x40>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 918>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 918>; + dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; + reg = <0 0xe6e31000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; + reg = <0 0xe6e34000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm5: pwm@e6e35000 { + compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; + reg = <0 0xe6e35000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm6: pwm@e6e36000 { + compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; + reg = <0 0xe6e36000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + rcar_sound: sound@ec500000 { + /* + * #sound-dai-cells is required + * + * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; + * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; + */ + /* + * #clock-cells is required for audio_clkout0/1/2/3 + * + * clkout : #clock-cells = <0>; <&rcar_sound>; + * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; + */ + compatible = "renesas,rcar_sound-r8a7795", "renesas,rcar_sound-gen3"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; + + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&audio_clk_b>, + <&audio_clk_c>, + <&cpg CPG_CORE R8A7795_CLK_S0D4>; + clock-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0", + "src.9", "src.8", "src.7", "src.6", + "src.5", "src.4", "src.3", "src.2", + "src.1", "src.0", + "mix.1", "mix.0", + "ctu.1", "ctu.0", + "dvc.0", "dvc.1", + "clk_a", "clk_b", "clk_c", "clk_i"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + status = "disabled"; + + rcar_sound,dvc { + dvc0: dvc-0 { + dmas = <&audma1 0xbc>; + dma-names = "tx"; + }; + dvc1: dvc-1 { + dmas = <&audma1 0xbe>; + dma-names = "tx"; + }; + }; + + rcar_sound,mix { + mix0: mix-0 { }; + mix1: mix-1 { }; + }; + + rcar_sound,ctu { + ctu00: ctu-0 { }; + ctu01: ctu-1 { }; + ctu02: ctu-2 { }; + ctu03: ctu-3 { }; + ctu10: ctu-4 { }; + ctu11: ctu-5 { }; + ctu12: ctu-6 { }; + ctu13: ctu-7 { }; + }; + + rcar_sound,src { + src0: src-0 { + interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x85>, <&audma1 0x9a>; + dma-names = "rx", "tx"; + }; + src1: src-1 { + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x87>, <&audma1 0x9c>; + dma-names = "rx", "tx"; + }; + src2: src-2 { + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x89>, <&audma1 0x9e>; + dma-names = "rx", "tx"; + }; + src3: src-3 { + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8b>, <&audma1 0xa0>; + dma-names = "rx", "tx"; + }; + src4: src-4 { + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8d>, <&audma1 0xb0>; + dma-names = "rx", "tx"; + }; + src5: src-5 { + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8f>, <&audma1 0xb2>; + dma-names = "rx", "tx"; + }; + src6: src-6 { + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x91>, <&audma1 0xb4>; + dma-names = "rx", "tx"; + }; + src7: src-7 { + interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x93>, <&audma1 0xb6>; + dma-names = "rx", "tx"; + }; + src8: src-8 { + interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x95>, <&audma1 0xb8>; + dma-names = "rx", "tx"; + }; + src9: src-9 { + interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x97>, <&audma1 0xba>; + dma-names = "rx", "tx"; + }; + }; + + rcar_sound,ssi { + ssi0: ssi-0 { + interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi1: ssi-1 { + interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi2: ssi-2 { + interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi3: ssi-3 { + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi4: ssi-4 { + interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi5: ssi-5 { + interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi6: ssi-6 { + interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi7: ssi-7 { + interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi8: ssi-8 { + interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi9: ssi-9 { + interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + }; + }; + + sata: sata@ee300000 { + compatible = "renesas,sata-r8a7795"; + reg = <0 0xee300000 0 0x200000>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 815>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 815>; + status = "disabled"; + }; + + xhci0: usb@ee000000 { + compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci"; + reg = <0 0xee000000 0 0xc00>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 328>; + status = "disabled"; + }; + + xhci1: usb@ee0400000 { + compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci"; + reg = <0 0xee040000 0 0xc00>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 327>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 327>; + status = "disabled"; + }; + + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,r8a7795-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac1: dma-controller@e65b0000 { + compatible = "renesas,r8a7795-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 331>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a7795"; + reg = <0 0xee100000 0 0x2000>; + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 314>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; + + sdhi1: sd@ee120000 { + compatible = "renesas,sdhi-r8a7795"; + reg = <0 0xee120000 0 0x2000>; + interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 313>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 313>; + status = "disabled"; + }; + + sdhi2: sd@ee140000 { + compatible = "renesas,sdhi-r8a7795"; + reg = <0 0xee140000 0 0x2000>; + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 312>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; + }; + + sdhi3: sd@ee160000 { + compatible = "renesas,sdhi-r8a7795"; + reg = <0 0xee160000 0 0x2000>; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 311>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 311>; + status = "disabled"; + }; + + usb2_phy0: usb-phy@ee080200 { + compatible = "renesas,usb2-phy-r8a7795", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee080200 0 0x700>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 703>; + #phy-cells = <0>; + status = "disabled"; + }; + + usb2_phy1: usb-phy@ee0a0200 { + compatible = "renesas,usb2-phy-r8a7795", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee0a0200 0 0x700>; + clocks = <&cpg CPG_MOD 702>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 702>; + #phy-cells = <0>; + status = "disabled"; + }; + + usb2_phy2: usb-phy@ee0c0200 { + compatible = "renesas,usb2-phy-r8a7795", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee0c0200 0 0x700>; + clocks = <&cpg CPG_MOD 701>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 701>; + #phy-cells = <0>; + status = "disabled"; + }; + + ehci0: usb@ee080100 { + compatible = "generic-ehci"; + reg = <0 0xee080100 0 0x100>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>; + phys = <&usb2_phy0>; + phy-names = "usb"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + }; + + ehci1: usb@ee0a0100 { + compatible = "generic-ehci"; + reg = <0 0xee0a0100 0 0x100>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 702>; + phys = <&usb2_phy1>; + phy-names = "usb"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 702>; + status = "disabled"; + }; + + ehci2: usb@ee0c0100 { + compatible = "generic-ehci"; + reg = <0 0xee0c0100 0 0x100>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 701>; + phys = <&usb2_phy2>; + phy-names = "usb"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 701>; + status = "disabled"; + }; + + ohci0: usb@ee080000 { + compatible = "generic-ohci"; + reg = <0 0xee080000 0 0x100>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>; + phys = <&usb2_phy0>; + phy-names = "usb"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + }; + + ohci1: usb@ee0a0000 { + compatible = "generic-ohci"; + reg = <0 0xee0a0000 0 0x100>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 702>; + phys = <&usb2_phy1>; + phy-names = "usb"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 702>; + status = "disabled"; + }; + + ohci2: usb@ee0c0000 { + compatible = "generic-ohci"; + reg = <0 0xee0c0000 0 0x100>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 701>; + phys = <&usb2_phy2>; + phy-names = "usb"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 701>; + status = "disabled"; + }; + + hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a7795", + "renesas,rcar-gen3-usbhs"; + reg = <0 0xe6590000 0 0x100>; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 704>; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + renesas,buswait = <11>; + phys = <&usb2_phy0>; + phy-names = "usb"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 704>; + status = "disabled"; + }; + + pciec0: pcie@fe000000 { + compatible = "renesas,pcie-r8a7795", + "renesas,pcie-rcar-gen3"; + reg = <0 0xfe000000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 + 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 + 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 + 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 319>; + status = "disabled"; + }; + + pciec1: pcie@ee800000 { + compatible = "renesas,pcie-r8a7795", + "renesas,pcie-rcar-gen3"; + reg = <0 0xee800000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000 + 0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000 + 0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000 + 0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 318>; + status = "disabled"; + }; + + vspbc: vsp@fe920000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe920000 0 0x8000>; + interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 624>; + power-domains = <&sysc R8A7795_PD_A3VP>; + resets = <&cpg 624>; + + renesas,fcp = <&fcpvb1>; + }; + + fcpvb1: fcp@fe92f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe92f000 0 0x200>; + clocks = <&cpg CPG_MOD 606>; + power-domains = <&sysc R8A7795_PD_A3VP>; + resets = <&cpg 606>; + }; + + fcpf0: fcp@fe950000 { + compatible = "renesas,fcpf"; + reg = <0 0xfe950000 0 0x200>; + clocks = <&cpg CPG_MOD 615>; + power-domains = <&sysc R8A7795_PD_A3VP>; + resets = <&cpg 615>; + }; + + fcpf1: fcp@fe951000 { + compatible = "renesas,fcpf"; + reg = <0 0xfe951000 0 0x200>; + clocks = <&cpg CPG_MOD 614>; + power-domains = <&sysc R8A7795_PD_A3VP>; + resets = <&cpg 614>; + }; + + fcpf2: fcp@fe952000 { + compatible = "renesas,fcpf"; + reg = <0 0xfe952000 0 0x200>; + clocks = <&cpg CPG_MOD 613>; + power-domains = <&sysc R8A7795_PD_A3VP>; + resets = <&cpg 613>; + }; + + vspbd: vsp@fe960000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe960000 0 0x8000>; + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 626>; + power-domains = <&sysc R8A7795_PD_A3VP>; + resets = <&cpg 626>; + + renesas,fcp = <&fcpvb0>; + }; + + fcpvb0: fcp@fe96f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe96f000 0 0x200>; + clocks = <&cpg CPG_MOD 607>; + power-domains = <&sysc R8A7795_PD_A3VP>; + resets = <&cpg 607>; + }; + + vspi0: vsp@fe9a0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe9a0000 0 0x8000>; + interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 631>; + power-domains = <&sysc R8A7795_PD_A3VP>; + resets = <&cpg 631>; + + renesas,fcp = <&fcpvi0>; + }; + + fcpvi0: fcp@fe9af000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe9af000 0 0x200>; + clocks = <&cpg CPG_MOD 611>; + power-domains = <&sysc R8A7795_PD_A3VP>; + resets = <&cpg 611>; + }; + + vspi1: vsp@fe9b0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe9b0000 0 0x8000>; + interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 630>; + power-domains = <&sysc R8A7795_PD_A3VP>; + resets = <&cpg 630>; + + renesas,fcp = <&fcpvi1>; + }; + + fcpvi1: fcp@fe9bf000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe9bf000 0 0x200>; + clocks = <&cpg CPG_MOD 610>; + power-domains = <&sysc R8A7795_PD_A3VP>; + resets = <&cpg 610>; + }; + + vspi2: vsp@fe9c0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe9c0000 0 0x8000>; + interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 629>; + power-domains = <&sysc R8A7795_PD_A3VP>; + resets = <&cpg 629>; + + renesas,fcp = <&fcpvi2>; + }; + + fcpvi2: fcp@fe9cf000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe9cf000 0 0x200>; + clocks = <&cpg CPG_MOD 609>; + power-domains = <&sysc R8A7795_PD_A3VP>; + resets = <&cpg 609>; + }; + + vspd0: vsp@fea20000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea20000 0 0x4000>; + interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 623>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 623>; + + renesas,fcp = <&fcpvd0>; + }; + + fcpvd0: fcp@fea27000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea27000 0 0x200>; + clocks = <&cpg CPG_MOD 603>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 603>; + }; + + vspd1: vsp@fea28000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea28000 0 0x4000>; + interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 622>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 622>; + + renesas,fcp = <&fcpvd1>; + }; + + fcpvd1: fcp@fea2f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea2f000 0 0x200>; + clocks = <&cpg CPG_MOD 602>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 602>; + }; + + vspd2: vsp@fea30000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea30000 0 0x4000>; + interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 621>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 621>; + + renesas,fcp = <&fcpvd2>; + }; + + fcpvd2: fcp@fea37000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea37000 0 0x200>; + clocks = <&cpg CPG_MOD 601>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 601>; + }; + + vspd3: vsp@fea38000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea38000 0 0x4000>; + interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 620>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 620>; + + renesas,fcp = <&fcpvd3>; + }; + + fcpvd3: fcp@fea3f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea3f000 0 0x200>; + clocks = <&cpg CPG_MOD 600>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 600>; + }; + + fdp1@fe940000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe940000 0 0x2400>; + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 119>; + power-domains = <&sysc R8A7795_PD_A3VP>; + resets = <&cpg 119>; + renesas,fcp = <&fcpf0>; + }; + + fdp1@fe944000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe944000 0 0x2400>; + interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 118>; + power-domains = <&sysc R8A7795_PD_A3VP>; + resets = <&cpg 118>; + renesas,fcp = <&fcpf1>; + }; + + fdp1@fe948000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe948000 0 0x2400>; + interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 117>; + power-domains = <&sysc R8A7795_PD_A3VP>; + resets = <&cpg 117>; + renesas,fcp = <&fcpf2>; + }; + + du: display@feb00000 { + compatible = "renesas,du-r8a7795"; + reg = <0 0xfeb00000 0 0x80000>, + <0 0xfeb90000 0 0x14>; + reg-names = "du", "lvds.0"; + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 722>, + <&cpg CPG_MOD 721>, + <&cpg CPG_MOD 727>; + clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0"; + status = "disabled"; + + vsps = <&vspd0 &vspd1 &vspd2 &vspd3>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_hdmi0: endpoint { + }; + }; + port@2 { + reg = <2>; + du_out_hdmi1: endpoint { + }; + }; + port@3 { + reg = <3>; + du_out_lvds0: endpoint { + }; + }; + }; + }; + + tsc: thermal@e6198000 { + compatible = "renesas,r8a7795-thermal"; + reg = <0 0xe6198000 0 0x68>, + <0 0xe61a0000 0 0x5c>, + <0 0xe61a8000 0 0x5c>; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 522>; + #thermal-sensor-cells = <1>; + status = "okay"; + }; + + thermal-zones { + sensor_thermal1: sensor-thermal1 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 0>; + + trips { + sensor1_crit: sensor1-crit { + temperature = <120000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + sensor_thermal2: sensor-thermal2 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 1>; + + trips { + sensor2_crit: sensor2-crit { + temperature = <120000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + sensor_thermal3: sensor-thermal3 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 2>; + + trips { + sensor3_crit: sensor3-crit { + temperature = <120000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/r8a7796-m3ulcb.dts b/arch/arm/dts/r8a7796-m3ulcb.dts new file mode 100644 index 0000000000..372b2a9447 --- /dev/null +++ b/arch/arm/dts/r8a7796-m3ulcb.dts @@ -0,0 +1,188 @@ +/* + * Device Tree Source for the M3ULCB (R-Car Starter Kit Pro) board + * + * Copyright (C) 2016 Renesas Electronics Corp. + * Copyright (C) 2016 Cogent Embedded, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r8a7796.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + model = "Renesas M3ULCB board based on r8a7796"; + compatible = "renesas,m3ulcb", "renesas,r8a7796"; + + aliases { + serial0 = &scif2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x38000000>; + }; + + leds { + compatible = "gpio-leds"; + + led5 { + gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; + }; + led6 { + gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; + }; + }; + + keyboard { + compatible = "gpio-keys"; + + key-1 { + linux,code = <KEY_1>; + label = "SW3"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + }; + }; + + reg_1p8v: regulator0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator1 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_sdhi0: regulator-vcc-sdhi0 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; +}; + +&extal_clk { + clock-frequency = <16666666>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + scif2_pins: scif2 { + groups = "scif2_data_a"; + function = "scif2"; + }; + + scif_clk_pins: scif_clk { + groups = "scif_clk_a"; + function = "scif_clk"; + }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <3300>; + }; + + sdhi0_pins_uhs: sd0_uhs { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <1800>; + }; + + sdhi2_pins: sd2 { + groups = "sdhi2_data8", "sdhi2_ctrl"; + function = "sdhi2"; + power-source = <3300>; + }; + + sdhi2_pins_uhs: sd2_uhs { + groups = "sdhi2_data8", "sdhi2_ctrl"; + function = "sdhi2"; + power-source = <1800>; + }; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi0>; + vqmmc-supply = <&vccq_sdhi0>; + cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + sd-uhs-sdr50; + status = "okay"; +}; + +&sdhi2 { + /* used for on-board 8bit eMMC */ + pinctrl-0 = <&sdhi2_pins>; + pinctrl-1 = <&sdhi2_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&scif2 { + pinctrl-0 = <&scif2_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&scif_clk { + clock-frequency = <14745600>; +}; + +&wdt0 { + timeout-sec = <60>; + status = "okay"; +}; diff --git a/arch/arm/dts/r8a7796-salvator-x.dts b/arch/arm/dts/r8a7796-salvator-x.dts new file mode 100644 index 0000000000..c9f59b6ce3 --- /dev/null +++ b/arch/arm/dts/r8a7796-salvator-x.dts @@ -0,0 +1,269 @@ +/* + * Device Tree Source for the Salvator-X board + * + * Copyright (C) 2016 Renesas Electronics Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r8a7796.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Renesas Salvator-X board based on r8a7796"; + compatible = "renesas,salvator-x", "renesas,r8a7796"; + + aliases { + serial0 = &scif2; + serial1 = &scif1; + ethernet0 = &avb; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial0:115200n8"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x78000000>; + }; + + memory@600000000 { + device_type = "memory"; + reg = <0x6 0x00000000 0x0 0x80000000>; + }; + + reg_1p8v: regulator0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator1 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_sdhi0: regulator-vcc-sdhi0 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; + + vcc_sdhi3: regulator-vcc-sdhi3 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI3 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi3: regulator-vccq-sdhi3 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI3 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; +}; + +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + avb_pins: avb { + groups = "avb_mdc"; + function = "avb"; + }; + + scif1_pins: scif1 { + groups = "scif1_data_a", "scif1_ctrl"; + function = "scif1"; + }; + + scif2_pins: scif2 { + groups = "scif2_data_a"; + function = "scif2"; + }; + scif_clk_pins: scif_clk { + groups = "scif_clk_a"; + function = "scif_clk"; + }; + + i2c2_pins: i2c2 { + groups = "i2c2_a"; + function = "i2c2"; + }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <3300>; + }; + + sdhi0_pins_uhs: sd0_uhs { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <1800>; + }; + + sdhi2_pins: sd2 { + groups = "sdhi2_data8", "sdhi2_ctrl"; + function = "sdhi2"; + power-source = <3300>; + }; + + sdhi2_pins_uhs: sd2_uhs { + groups = "sdhi2_data8", "sdhi2_ctrl"; + function = "sdhi2"; + power-source = <1800>; + }; + + sdhi3_pins: sd3 { + groups = "sdhi3_data4", "sdhi3_ctrl"; + function = "sdhi3"; + power-source = <3300>; + }; + + sdhi3_pins_uhs: sd3_uhs { + groups = "sdhi3_data4", "sdhi3_ctrl"; + function = "sdhi3"; + power-source = <1800>; + }; +}; + +&avb { + pinctrl-0 = <&avb_pins>; + pinctrl-names = "default"; + renesas,no-ether-link; + phy-handle = <&phy0>; + status = "okay"; + + phy0: ethernet-phy@0 { + rxc-skew-ps = <1500>; + reg = <0>; + interrupt-parent = <&gpio2>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&extal_clk { + clock-frequency = <16666666>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi0>; + vqmmc-supply = <&vccq_sdhi0>; + cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; + bus-width = <4>; + sd-uhs-sdr50; + status = "okay"; +}; + +&sdhi2 { + /* used for on-board 8bit eMMC */ + pinctrl-0 = <&sdhi2_pins>; + pinctrl-1 = <&sdhi2_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&sdhi3 { + pinctrl-0 = <&sdhi3_pins>; + pinctrl-1 = <&sdhi3_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi3>; + vqmmc-supply = <&vccq_sdhi3>; + cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; + bus-width = <4>; + sd-uhs-sdr50; + status = "okay"; +}; + +&scif1 { + pinctrl-0 = <&scif1_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; +}; + +&scif2 { + pinctrl-0 = <&scif2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&scif_clk { + clock-frequency = <14745600>; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&wdt0 { + timeout-sec = <60>; + status = "okay"; +}; + +&i2c_dvfs { + status = "okay"; +}; diff --git a/arch/arm/dts/r8a7796.dtsi b/arch/arm/dts/r8a7796.dtsi new file mode 100644 index 0000000000..2ec1ed5f49 --- /dev/null +++ b/arch/arm/dts/r8a7796.dtsi @@ -0,0 +1,1037 @@ +/* + * Device Tree Source for the r8a7796 SoC + * + * Copyright (C) 2016 Renesas Electronics Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include <dt-bindings/clock/r8a7796-cpg-mssr.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/power/r8a7796-sysc.h> + +/ { + compatible = "renesas,r8a7796"; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c_dvfs; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + a57_0: cpu@0 { + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x0>; + device_type = "cpu"; + power-domains = <&sysc R8A7796_PD_CA57_CPU0>; + next-level-cache = <&L2_CA57>; + enable-method = "psci"; + }; + + a57_1: cpu@1 { + compatible = "arm,cortex-a57","arm,armv8"; + reg = <0x1>; + device_type = "cpu"; + power-domains = <&sysc R8A7796_PD_CA57_CPU1>; + next-level-cache = <&L2_CA57>; + enable-method = "psci"; + }; + + a53_0: cpu@100 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x100>; + device_type = "cpu"; + power-domains = <&sysc R8A7796_PD_CA53_CPU0>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + + a53_1: cpu@101 { + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x101>; + device_type = "cpu"; + power-domains = <&sysc R8A7796_PD_CA53_CPU1>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + + a53_2: cpu@102 { + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x102>; + device_type = "cpu"; + power-domains = <&sysc R8A7796_PD_CA53_CPU2>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + + a53_3: cpu@103 { + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x103>; + device_type = "cpu"; + power-domains = <&sysc R8A7796_PD_CA53_CPU3>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + + L2_CA57: cache-controller-0 { + compatible = "cache"; + power-domains = <&sysc R8A7796_PD_CA57_SCU>; + cache-unified; + cache-level = <2>; + }; + + L2_CA53: cache-controller-1 { + compatible = "cache"; + power-domains = <&sysc R8A7796_PD_CA53_SCU>; + cache-unified; + cache-level = <2>; + }; + }; + + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + extalr_clk: extalr { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + /* External CAN clock - to be overridden by boards that provide it */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* External SCIF clock - to be overridden by boards that provide it */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@f1010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1010000 0 0x1000>, + <0x0 0xf1020000 0 0x20000>, + <0x0 0xf1040000 0 0x20000>, + <0x0 0xf1060000 0 0x20000>; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 + (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 + (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 + (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; + }; + + wdt0: watchdog@e6020000 { + compatible = "renesas,r8a7796-wdt", + "renesas,rcar-gen3-wdt"; + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; + }; + + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a7796", + "renesas,gpio-rcar"; + reg = <0 0xe6050000 0 0x50>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 16>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 912>; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a7796", + "renesas,gpio-rcar"; + reg = <0 0xe6051000 0 0x50>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 29>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 911>; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a7796", + "renesas,gpio-rcar"; + reg = <0 0xe6052000 0 0x50>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 15>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 910>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a7796", + "renesas,gpio-rcar"; + reg = <0 0xe6053000 0 0x50>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 16>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 909>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a7796", + "renesas,gpio-rcar"; + reg = <0 0xe6054000 0 0x50>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 18>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 908>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a7796", + "renesas,gpio-rcar"; + reg = <0 0xe6055000 0 0x50>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 907>; + }; + + gpio6: gpio@e6055400 { + compatible = "renesas,gpio-r8a7796", + "renesas,gpio-rcar"; + reg = <0 0xe6055400 0 0x50>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 906>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 906>; + }; + + gpio7: gpio@e6055800 { + compatible = "renesas,gpio-r8a7796", + "renesas,gpio-rcar"; + reg = <0 0xe6055800 0 0x50>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 224 4>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 905>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 905>; + }; + + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a7796"; + reg = <0 0xe6060000 0 0x50c>; + }; + + pmu_a57 { + compatible = "arm,cortex-a57-pmu"; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&a57_0>, + <&a57_1>; + }; + + pmu_a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&a53_0>, + <&a53_1>, + <&a53_2>, + <&a53_3>; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7796-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a7796-rst"; + reg = <0 0xe6160000 0 0x0200>; + }; + + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7796-sysc"; + reg = <0 0xe6180000 0 0x0400>; + #power-domain-cells = <1>; + }; + + i2c_dvfs: i2c@e60b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7796", + "renesas,rcar-gen3-iic", + "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 926>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 926>; + status = "disabled"; + }; + + i2c0: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7796", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6500000 0 0x40>; + interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 931>; + dmas = <&dmac1 0x91>, <&dmac1 0x90>, + <&dmac2 0x91>, <&dmac2 0x90>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c1: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7796", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 930>; + dmas = <&dmac1 0x93>, <&dmac1 0x92>, + <&dmac2 0x93>, <&dmac2 0x92>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c2: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7796", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6510000 0 0x40>; + interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 929>; + dmas = <&dmac1 0x95>, <&dmac1 0x94>, + <&dmac2 0x95>, <&dmac2 0x94>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c3: i2c@e66d0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7796", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d0000 0 0x40>; + interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 928>; + dmas = <&dmac0 0x97>, <&dmac0 0x96>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c4: i2c@e66d8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7796", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d8000 0 0x40>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 927>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 927>; + dmas = <&dmac0 0x99>, <&dmac0 0x98>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c5: i2c@e66e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7796", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66e0000 0 0x40>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 919>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 919>; + dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c6: i2c@e66e8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7796", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66e8000 0 0x40>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 918>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 918>; + dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + can0: can@e6c30000 { + compatible = "renesas,can-r8a7796", + "renesas,rcar-gen3-can"; + reg = <0 0xe6c30000 0 0x1000>; + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A7796_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 916>; + status = "disabled"; + }; + + can1: can@e6c38000 { + compatible = "renesas,can-r8a7796", + "renesas,rcar-gen3-can"; + reg = <0 0xe6c38000 0 0x1000>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A7796_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 915>; + status = "disabled"; + }; + + canfd: can@e66c0000 { + compatible = "renesas,r8a7796-canfd", + "renesas,rcar-gen3-canfd"; + reg = <0 0xe66c0000 0 0x8000>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 914>, + <&cpg CPG_CORE R8A7796_CLK_CANFD>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 914>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + + channel1 { + status = "disabled"; + }; + }; + + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a7796", + "renesas,etheravb-rcar-gen3"; + reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 812>; + phy-mode = "rgmii-txid"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hscif0: serial@e6540000 { + compatible = "renesas,hscif-r8a7796", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6540000 0 0x60>; + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 520>, + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x31>, <&dmac1 0x30>, + <&dmac2 0x31>, <&dmac2 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 520>; + status = "disabled"; + }; + + hscif1: serial@e6550000 { + compatible = "renesas,hscif-r8a7796", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6550000 0 0x60>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 519>, + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x33>, <&dmac1 0x32>, + <&dmac2 0x33>, <&dmac2 0x32>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 519>; + status = "disabled"; + }; + + hscif2: serial@e6560000 { + compatible = "renesas,hscif-r8a7796", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6560000 0 0x60>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 518>, + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x35>, <&dmac1 0x34>, + <&dmac2 0x35>, <&dmac2 0x34>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 518>; + status = "disabled"; + }; + + hscif3: serial@e66a0000 { + compatible = "renesas,hscif-r8a7796", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe66a0000 0 0x60>; + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 517>, + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x37>, <&dmac0 0x36>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 517>; + status = "disabled"; + }; + + hscif4: serial@e66b0000 { + compatible = "renesas,hscif-r8a7796", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe66b0000 0 0x60>; + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 516>, + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x38>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 516>; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7796", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 207>, + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x51>, <&dmac1 0x50>, + <&dmac2 0x51>, <&dmac2 0x50>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 207>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7796", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 206>, + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x53>, <&dmac1 0x52>, + <&dmac2 0x53>, <&dmac2 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 206>; + status = "disabled"; + }; + + scif2: serial@e6e88000 { + compatible = "renesas,scif-r8a7796", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e88000 0 64>; + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 310>, + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 310>; + status = "disabled"; + }; + + scif3: serial@e6c50000 { + compatible = "renesas,scif-r8a7796", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c50000 0 64>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 204>, + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x57>, <&dmac0 0x56>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 204>; + status = "disabled"; + }; + + scif4: serial@e6c40000 { + compatible = "renesas,scif-r8a7796", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c40000 0 64>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 203>, + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x59>, <&dmac0 0x58>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 203>; + status = "disabled"; + }; + + scif5: serial@e6f30000 { + compatible = "renesas,scif-r8a7796", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6f30000 0 64>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 202>, + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, + <&dmac2 0x5b>, <&dmac2 0x5a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 202>; + status = "disabled"; + }; + + msiof0: spi@e6e90000 { + compatible = "renesas,msiof-r8a7796", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6e90000 0 0x0064>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 211>; + dmas = <&dmac1 0x41>, <&dmac1 0x40>, + <&dmac2 0x41>, <&dmac2 0x40>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 211>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof1: spi@e6ea0000 { + compatible = "renesas,msiof-r8a7796", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6ea0000 0 0x0064>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 210>; + dmas = <&dmac1 0x43>, <&dmac1 0x42>, + <&dmac2 0x43>, <&dmac2 0x42>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 210>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof2: spi@e6c00000 { + compatible = "renesas,msiof-r8a7796", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c00000 0 0x0064>; + interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 209>; + dmas = <&dmac0 0x45>, <&dmac0 0x44>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 209>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof3: spi@e6c10000 { + compatible = "renesas,msiof-r8a7796", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c10000 0 0x0064>; + interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x47>, <&dmac0 0x46>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 208>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a7796", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x10000>; + interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <16>; + }; + + dmac1: dma-controller@e7300000 { + compatible = "renesas,dmac-r8a7796", + "renesas,rcar-dmac"; + reg = <0 0xe7300000 0 0x10000>; + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <16>; + }; + + dmac2: dma-controller@e7310000 { + compatible = "renesas,dmac-r8a7796", + "renesas,rcar-dmac"; + reg = <0 0xe7310000 0 0x10000>; + interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 217>; + clock-names = "fck"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 217>; + #dma-cells = <1>; + dma-channels = <16>; + }; + + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a7796"; + reg = <0 0xee100000 0 0x2000>; + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 314>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; + + sdhi1: sd@ee120000 { + compatible = "renesas,sdhi-r8a7796"; + reg = <0 0xee120000 0 0x2000>; + interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 313>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 313>; + status = "disabled"; + }; + + sdhi2: sd@ee140000 { + compatible = "renesas,sdhi-r8a7796"; + reg = <0 0xee140000 0 0x2000>; + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 312>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; + }; + + sdhi3: sd@ee160000 { + compatible = "renesas,sdhi-r8a7796"; + reg = <0 0xee160000 0 0x2000>; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 311>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 311>; + status = "disabled"; + }; + + tsc: thermal@e6198000 { + compatible = "renesas,r8a7796-thermal"; + reg = <0 0xe6198000 0 0x68>, + <0 0xe61a0000 0 0x5c>, + <0 0xe61a8000 0 0x5c>; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 522>; + #thermal-sensor-cells = <1>; + status = "okay"; + }; + + thermal-zones { + sensor_thermal1: sensor-thermal1 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 0>; + + trips { + sensor1_crit: sensor1-crit { + temperature = <120000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + sensor_thermal2: sensor-thermal2 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 1>; + + trips { + sensor2_crit: sensor2-crit { + temperature = <120000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + sensor_thermal3: sensor-thermal3 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 2>; + + trips { + sensor3_crit: sensor3-crit { + temperature = <120000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/rk3036-sdk-u-boot.dtsi b/arch/arm/dts/rk3036-sdk-u-boot.dtsi new file mode 100644 index 0000000000..6f15f4a8ec --- /dev/null +++ b/arch/arm/dts/rk3036-sdk-u-boot.dtsi @@ -0,0 +1,11 @@ +&uart2 { + u-boot,dm-pre-reloc; +}; + +&grf { + u-boot,dm-pre-reloc; +}; + +&pinctrl { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3229-evb.dts b/arch/arm/dts/rk3229-evb.dts index ccdac1c79a..64f1c2d7da 100644 --- a/arch/arm/dts/rk3229-evb.dts +++ b/arch/arm/dts/rk3229-evb.dts @@ -72,6 +72,21 @@ status = "okay"; }; +&sdmmc { + status = "okay"; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; + num-slots = <1>; + supports-sd; +}; + &uart2 { status = "okay"; }; + +&usb20_otg { + status = "okay"; +}; diff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi index 7237da431d..22324f97b3 100644 --- a/arch/arm/dts/rk322x.dtsi +++ b/arch/arm/dts/rk322x.dtsi @@ -21,6 +21,8 @@ serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; + mmc0 = &emmc; + mmc1 = &sdmmc; }; cpus { @@ -383,12 +385,38 @@ status = "disabled"; }; + sdmmc: dwmmc@30000000 { + compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x30000000 0x4000>; + max-frequency = <150000000>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + fifo-depth = <0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; + status = "disabled"; + }; + + sdio: dwmmc@30010000 { + compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x30010000 0x4000>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; + clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; + fifo-depth = <0x100>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>; + status = "disabled"; + }; + emmc: dwmmc@30020000 { compatible = "rockchip,rk3288-dw-mshc"; reg = <0x30020000 0x4000>; + max-frequency = <150000000>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <37500000>; - max-frequency = <37500000>; clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; clock-names = "biu", "ciu", "ciu_drv", "ciu_sample"; @@ -403,6 +431,16 @@ status = "disabled"; }; + usb20_otg: usb@30040000 { + compatible = "rockchip,rk3229-usb", "rockchip,rk3288-usb", + "snps,dwc2"; + reg = <0x30040000 0x40000>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + hnp-srp-disable; + dr_mode = "otg"; + status = "disabled"; + }; + gmac: ethernet@30200000 { compatible = "rockchip,rk3228-gmac"; reg = <0x30200000 0x10000>; @@ -510,6 +548,40 @@ drive-strength = <12>; }; + sdmmc { + sdmmc_clk: sdmmc-clk { + rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; + }; + + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, + <1 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, + <1 20 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, + <1 21 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; + }; + }; + + sdio { + sdio_clk: sdio-clk { + rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; + }; + + sdio_cmd: sdio-cmd { + rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; + }; + + sdio_bus4: sdio-bus4 { + rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, + <3 3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, + <3 4 RK_FUNC_1 &pcfg_pull_none_drv_12ma>, + <3 5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>; + }; + }; + emmc { emmc_clk: emmc-clk { rockchip,pins = <2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>; diff --git a/arch/arm/dts/rk3288-phycore-som.dtsi b/arch/arm/dts/rk3288-phycore-som.dtsi index fd463f4d98..02d11968cb 100644 --- a/arch/arm/dts/rk3288-phycore-som.dtsi +++ b/arch/arm/dts/rk3288-phycore-som.dtsi @@ -61,6 +61,7 @@ aliases { rtc0 = &i2c_rtc; rtc1 = &rk818; + eeprom0 = &i2c_eeprom_id; }; ext_gmac: external-gmac-clock { @@ -383,6 +384,13 @@ pagesize = <32>; }; + /* M24C32-D Identification page */ + i2c_eeprom_id: eeprom@58 { + compatible = "atmel,24c32"; + reg = <0x58>; + pagesize = <32>; + }; + vdd_cpu: regulator@60 { compatible = "fcs,fan53555"; reg = <0x60>; diff --git a/arch/arm/dts/rk3368-geekbox-u-boot.dtsi b/arch/arm/dts/rk3368-geekbox-u-boot.dtsi new file mode 100644 index 0000000000..764b3e4cb4 --- /dev/null +++ b/arch/arm/dts/rk3368-geekbox-u-boot.dtsi @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +&pinctrl { + u-boot,dm-pre-reloc; +}; + +&service_msch { + u-boot,dm-pre-reloc; +}; + +&dmc { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&pmugrf { + u-boot,dm-pre-reloc; +}; + +&cru { + u-boot,dm-pre-reloc; +}; + +&grf { + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3368-lion-u-boot.dtsi b/arch/arm/dts/rk3368-lion-u-boot.dtsi new file mode 100644 index 0000000000..6052e8a8d3 --- /dev/null +++ b/arch/arm/dts/rk3368-lion-u-boot.dtsi @@ -0,0 +1,93 @@ +/* + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +/ { + config { + u-boot,spl-payload-offset = <0x40000>; /* @ 256KB */ + u-boot,mmc-env-offset = <0x4000>; /* @ 16KB */ + }; + + chosen { + stdout-path = "serial0:115200n8"; + u-boot,spl-boot-order = &emmc, &sdmmc; + }; + +}; + +&pinctrl { + u-boot,dm-pre-reloc; +}; + +&service_msch { + u-boot,dm-pre-reloc; +}; + +&dmc { + u-boot,dm-pre-reloc; + + /* + * Validation of throughput using SPEC2000 shows the following + * relative performance for the different memory schedules: + * - CBDR: 30.1 + * - CBRD: 29.8 + * - CRBD: 29.9 + * Note that the best performance for any given application workload + * may vary from the default configured here (e.g. 164.gzip is fastest + * with CBRD, whereas 252.eon and 186.crafty are fastest with CRBD). + * + * See doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt for + * details on the 'rockchip,memory-schedule' property and how it + * affects the physical-address to device-address mapping. + */ + rockchip,memory-schedule = <DMC_MSCH_CBDR>; + rockchip,ddr-frequency = <800000000>; + rockchip,ddr-speed-bin = <DDR3_1600K>; + + status = "okay"; +}; + +&pmugrf { + u-boot,dm-pre-reloc; +}; + +&sgrf { + u-boot,dm-pre-reloc; +}; + +&cru { + u-boot,dm-pre-reloc; +}; + +&grf { + u-boot,dm-pre-reloc; +}; + +&uart0 { + u-boot,dm-pre-reloc; +}; + +&emmc { + u-boot,dm-pre-reloc; +}; + +&sdmmc { + u-boot,dm-pre-reloc; +}; + +&spi1 { + u-boot,dm-pre-reloc; + + spiflash: w25q32dw@0 { + u-boot,dm-pre-reloc; + }; +}; + +&timer0 { + u-boot,dm-pre-reloc; + clock-frequency = <24000000>; +}; + + diff --git a/arch/arm/dts/rk3368-lion.dts b/arch/arm/dts/rk3368-lion.dts new file mode 100644 index 0000000000..850db500e4 --- /dev/null +++ b/arch/arm/dts/rk3368-lion.dts @@ -0,0 +1,195 @@ +/* + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +/dts-v1/; +#include "rk3368.dtsi" +#include "rk3368-lion-u-boot.dtsi" +#include <dt-bindings/input/input.h> + +/ { + model = "Theobroma Systems RK3368-uQ7 SoM"; + compatible = "tsd,rk3368-uq7", "tsd,lion", "rockchip,rk3368"; + + aliases { + mmc0 = &emmc; + mmc1 = &sdmmc; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>; + }; + + ext_gmac: gmac-clk { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + #clock-cells = <0>; + }; + + vcc_sys: vcc-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&uart0 { + status = "okay"; +}; + +&emmc { + status = "okay"; + bus-width = <8>; + cap-mmc-highspeed; + clock-frequency = <150000000>; + disable-wp; + keep-power-in-suspend; + non-removable; + num-slots = <1>; + vmmc-supply = <&vcc33_io>; + vqmmc-supply = <&vcc18_io>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>; +}; + +&sdmmc { + status = "okay"; +}; + +&gmac { + status = "okay"; + phy-supply = <&vcc33_io>; + phy-mode = "rgmii"; + clock_in_out = "input"; + snps,reset-gpio = <&gpio3 11 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <2 10000 50000>; + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>; + tx_delay = <0x10>; + rx_delay = <0x10>; +}; + +&i2c0 { + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio0>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + rockchip,system-power-controller; + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_sys>; + vcc9-supply = <&vcc_sys>; + vcc10-supply = <&vcc_sys>; + vcc11-supply = <&vcc_sys>; + vcc12-supply = <&vcc_sys>; + clock-output-names = "xin32k", "rk808-clkout2"; + #clock-cells = <1>; + + regulators { + vdd_cpu: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd_cpu"; + }; + + vdd_log: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vdd_log"; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + }; + + vcc33_io: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc33_io"; + }; + + vcc33_video: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc33_video"; + }; + + vdd10_pll: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd10_pll"; + }; + + vcc18_io: LDO_REG4 { + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_io"; + }; + + vdd10_video: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd10_video"; + }; + + vcc18_video: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_video"; + }; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&spi1 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + spiflash: w25q32dw@0 { + compatible = "spi-flash"; + reg = <0>; + spi-max-frequency = <49500000>; + spi-cpol; + spi-cpha; + }; +}; diff --git a/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi new file mode 100644 index 0000000000..3a5e30ea55 --- /dev/null +++ b/arch/arm/dts/rk3368-px5-evb-u-boot.dtsi @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +&pinctrl { + u-boot,dm-pre-reloc; +}; + +&service_msch { + u-boot,dm-pre-reloc; +}; + +&dmc { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&pmugrf { + u-boot,dm-pre-reloc; +}; + +&cru { + u-boot,dm-pre-reloc; +}; + +&grf { + u-boot,dm-pre-reloc; +}; + +&uart4 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3368-sheep-u-boot.dtsi b/arch/arm/dts/rk3368-sheep-u-boot.dtsi new file mode 100644 index 0000000000..764b3e4cb4 --- /dev/null +++ b/arch/arm/dts/rk3368-sheep-u-boot.dtsi @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH + * + * SPDX-License-Identifier: GPL-2.0+ X11 + */ + +&pinctrl { + u-boot,dm-pre-reloc; +}; + +&service_msch { + u-boot,dm-pre-reloc; +}; + +&dmc { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&pmugrf { + u-boot,dm-pre-reloc; +}; + +&cru { + u-boot,dm-pre-reloc; +}; + +&grf { + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/rk3368.dtsi b/arch/arm/dts/rk3368.dtsi index 9daf765430..b4f4f6139d 100644 --- a/arch/arm/dts/rk3368.dtsi +++ b/arch/arm/dts/rk3368.dtsi @@ -46,6 +46,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/pinctrl/rockchip.h> #include <dt-bindings/thermal/thermal.h> +#include <dt-bindings/memory/rk3368-dmc.h> / { compatible = "rockchip,rk3368"; @@ -227,6 +228,21 @@ #clock-cells = <0>; }; + dmc: dmc@ff610000 { + compatible = "rockchip,rk3368-dmc", "syscon"; + rockchip,cru = <&cru>; + rockchip,grf = <&grf>; + rockchip,msch = <&service_msch>; + reg = <0 0xff610000 0 0x400 + 0 0xff620000 0 0x400>; + }; + + service_msch: syscon@ffac0000 { + compatible = "rockchip,rk3368-msch", "syscon"; + reg = <0x0 0xffac0000 0x0 0x2000>; + status = "okay"; + }; + sdmmc: dwmmc@ff0c0000 { compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x0 0xff0c0000 0x0 0x4000>; @@ -546,12 +562,6 @@ status = "disabled"; }; - dmc: dmc@ff610000 { - u-boot,dm-pre-reloc; - compatible = "rockchip,rk3368-dmc", "syscon"; - reg = <0x0 0xff610000 0x0 0x1000>; - }; - i2c0: i2c@ff650000 { compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; reg = <0x0 0xff650000 0x0 0x1000>; @@ -647,11 +657,15 @@ }; pmugrf: syscon@ff738000 { - u-boot,dm-pre-reloc; compatible = "rockchip,rk3368-pmugrf", "syscon"; reg = <0x0 0xff738000 0x0 0x1000>; }; + sgrf: syscon@ff740000 { + compatible = "rockchip,rk3368-sgrf", "syscon"; + reg = <0x0 0xff740000 0x0 0x1000>; + }; + cru: clock-controller@ff760000 { compatible = "rockchip,rk3368-cru"; reg = <0x0 0xff760000 0x0 0x1000>; @@ -673,7 +687,7 @@ status = "disabled"; }; - timer@ff810000 { + timer0: timer@ff810000 { compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer"; reg = <0x0 0xff810000 0x0 0x20>; interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/dts/rk3399-firefly.dts b/arch/arm/dts/rk3399-firefly.dts index 91d3193c85..3d3f507934 100644 --- a/arch/arm/dts/rk3399-firefly.dts +++ b/arch/arm/dts/rk3399-firefly.dts @@ -8,7 +8,7 @@ #include <dt-bindings/pwm/pwm.h> #include <dt-bindings/pinctrl/rockchip.h> #include "rk3399.dtsi" -#include "rk3399-sdram-ddr3-1333.dtsi" +#include "rk3399-sdram-ddr3-1600.dtsi" / { model = "Firefly-RK3399 Board"; @@ -157,8 +157,9 @@ regulator-name = "vdd_log"; regulator-always-on; regulator-boot-on; - regulator-min-microvolt = <800000>; + regulator-min-microvolt = <430000>; regulator-max-microvolt = <1400000>; + regulator-init-microvolt = <950000>; }; vccadc_ref: vccadc-ref { diff --git a/arch/arm/dts/rk3399-puma.dtsi b/arch/arm/dts/rk3399-puma.dtsi index 1aad6c508e..dd1baea704 100644 --- a/arch/arm/dts/rk3399-puma.dtsi +++ b/arch/arm/dts/rk3399-puma.dtsi @@ -12,7 +12,9 @@ compatible = "tsd,rk3399-q7", "tsd,puma", "rockchip,rk3399"; config { - u-boot,spl-payload-offset = <0x40000>; /* 256kbyte */ + u-boot,spl-payload-offset = <0x40000>; /* @ 256KB */ + u-boot,mmc-env-offset = <0x4000>; /* @ 16KB */ + u-boot,efi-partition-entries-offset = <0x200000>; /* 2MB */ u-boot,boot-led = "module_led"; }; diff --git a/arch/arm/dts/sun7i-a20-pcduino3.dts b/arch/arm/dts/sun7i-a20-pcduino3.dts index 1a8b39be1d..37b1e0ee9b 100644 --- a/arch/arm/dts/sun7i-a20-pcduino3.dts +++ b/arch/arm/dts/sun7i-a20-pcduino3.dts @@ -164,7 +164,7 @@ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; vmmc-supply = <®_vcc3v3>; bus-width = <4>; - cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ + cd-gpios = <&pio 7 1 GPIO_ACTIVE_LOW>; /* PH1 */ cd-inverted; status = "okay"; }; diff --git a/arch/arm/dts/tegra124-nyan-big.dts b/arch/arm/dts/tegra124-nyan-big.dts index 62f89d0f1a..f1c97052a8 100644 --- a/arch/arm/dts/tegra124-nyan-big.dts +++ b/arch/arm/dts/tegra124-nyan-big.dts @@ -8,7 +8,6 @@ aliases { console = &uarta; - stdout-path = &uarta; i2c0 = "/i2c@7000d000"; i2c1 = "/i2c@7000c000"; i2c2 = "/i2c@7000c400"; @@ -26,6 +25,10 @@ usb2 = "/usb@7d004000"; }; + chosen { + stdout-path = &uarta; + }; + host1x@50000000 { dc@54200000 { display-timings { diff --git a/arch/arm/dts/usb_a9263.dts b/arch/arm/dts/usb_a9263.dts new file mode 100644 index 0000000000..bfc48a2724 --- /dev/null +++ b/arch/arm/dts/usb_a9263.dts @@ -0,0 +1,144 @@ +/* + * usb_a9263.dts - Device Tree file for Caloa USB A9293 board + * + * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + * + * Licensed under GPLv2 only + */ +/dts-v1/; +#include "at91sam9263.dtsi" + +/ { + model = "Calao USB A9263"; + compatible = "atmel,usb-a9263", "atmel,at91sam9263", "atmel,at91sam9"; + + chosen { + bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs"; + }; + + memory { + reg = <0x20000000 0x4000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + ahb { + apb { + dbgu: serial@ffffee00 { + status = "okay"; + }; + + macb0: ethernet@fffbc000 { + phy-mode = "rmii"; + status = "okay"; + }; + + usb1: gadget@fff78000 { + atmel,vbus-gpio = <&pioB 11 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + spi0: spi@fffa4000 { + cs-gpios = <&pioB 15 GPIO_ACTIVE_HIGH>; + status = "okay"; + mtd_dataflash@0 { + compatible = "atmel,at45", "atmel,dataflash"; + reg = <0>; + spi-max-frequency = <15000000>; + }; + }; + + shdwc@fffffd10 { + atmel,wakeup-counter = <10>; + atmel,wakeup-rtt-timer; + }; + }; + + nand0: nand@40000000 { + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + status = "okay"; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x20000>; + }; + + barebox@20000 { + label = "barebox"; + reg = <0x20000 0x40000>; + }; + + bareboxenv@60000 { + label = "bareboxenv"; + reg = <0x60000 0x20000>; + }; + + bareboxenv2@80000 { + label = "bareboxenv2"; + reg = <0x80000 0x20000>; + }; + + oftree@80000 { + label = "oftree"; + reg = <0xa0000 0x20000>; + }; + + kernel@a0000 { + label = "kernel"; + reg = <0xc0000 0x400000>; + }; + + rootfs@4a0000 { + label = "rootfs"; + reg = <0x4c0000 0x7800000>; + }; + + data@7ca0000 { + label = "data"; + reg = <0x7cc0000 0x8340000>; + }; + }; + + usb0: ohci@00a00000 { + num-ports = <2>; + status = "okay"; + }; + }; + + leds { + compatible = "gpio-leds"; + + user_led { + label = "user_led"; + gpios = <&pioB 21 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + user_pb { + label = "user_pb"; + gpios = <&pioB 10 GPIO_ACTIVE_LOW>; + linux,code = <28>; + wakeup-source; + }; + }; + + i2c-gpio-0 { + status = "okay"; + }; +}; diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index 34fc6e5f89..f993e19ef2 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -38,6 +38,14 @@ }; }; + fpga_full: fpga-full { + compatible = "fpga-region"; + fpga-mgr = <&devcfg>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + }; + pmu@f8891000 { compatible = "arm,cortex-a9-pmu"; interrupts = <0 5 4>, <0 6 4>; diff --git a/arch/arm/dts/zynq-zturn-myir.dts b/arch/arm/dts/zynq-zturn-myir.dts new file mode 100644 index 0000000000..a5ecfcc1d7 --- /dev/null +++ b/arch/arm/dts/zynq-zturn-myir.dts @@ -0,0 +1,161 @@ +/* + * Copyright (C) 2015 Andrea Merello <adnrea.merello@gmail.com> + * Copyright (C) 2017 Alexander Graf <agraf@suse.de> + * + * Based on zynq-zed.dts which is: + * Copyright (C) 2011 - 2014 Xilinx + * Copyright (C) 2012 National Instruments Corp. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +/dts-v1/; +/include/ "zynq-7000.dtsi" + +/ { + model = "Zynq Z-Turn MYIR Board"; + compatible = "xlnx,zynq-7000"; + + aliases { + ethernet0 = &gem0; + serial0 = &uart1; + serial1 = &uart0; + spi0 = &qspi; + mmc0 = &sdhci0; + }; + + memory { + device_type = "memory"; + reg = <0x0 0x40000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + led_r { + label = "led_r"; + gpios = <&gpio0 0x72 0x1>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led_g { + label = "led_g"; + gpios = <&gpio0 0x73 0x1>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led_b { + label = "led_b"; + gpios = <&gpio0 0x74 0x1>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + usr_led1 { + label = "usr_led1"; + gpios = <&gpio0 0x0 0x1>; + default-state = "off"; + linux,default-trigger = "none"; + }; + + usr_led2 { + label = "usr_led2"; + gpios = <&gpio0 0x9 0x1>; + default-state = "off"; + linux,default-trigger = "none"; + }; + }; + + gpio-beep { + compatible = "gpio-beeper"; + label = "pl-beep"; + gpios = <&gpio0 0x75 0x0>; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <0x1>; + #size-cells = <0x0>; + autorepeat; + K1 { + label = "K1"; + gpios = <&gpio0 0x32 0x1>; + linux,code = <0x66>; + gpio-key,wakeup; + autorepeat; + }; + }; +}; + +&clkc { + ps-clk-frequency = <33333333>; + fclk-enable = <0xf>; +}; + +&qspi { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@0 { + reg = <0x0>; + }; +}; + +&sdhci0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&uart1 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; +}; + +&can0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + stlm75@49 { + status = "okay"; + compatible = "lm75"; + reg = <0x49>; + }; + + adxl345@53 { + compatible = "adi,adxl34x", "adxl34x"; + reg = <0x53>; + interrupt-parent = <&intc>; + interrupts = <0x0 0x1e 0x4>; + }; +}; diff --git a/arch/arm/dts/zynqmp-zcu102.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index 0e9150e6b1..d8ac008f2b 100644 --- a/arch/arm/dts/zynqmp-zcu102.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -16,7 +16,7 @@ / { model = "ZynqMP ZCU102 RevA"; - compatible = "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; + compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; aliases { ethernet0 = &gem3; diff --git a/arch/arm/dts/zynqmp-zcu102-revB.dts b/arch/arm/dts/zynqmp-zcu102-revB.dts index 765108e437..82337332f9 100644 --- a/arch/arm/dts/zynqmp-zcu102-revB.dts +++ b/arch/arm/dts/zynqmp-zcu102-revB.dts @@ -8,7 +8,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include "zynqmp-zcu102.dts" +#include "zynqmp-zcu102-revA.dts" / { model = "ZynqMP ZCU102 RevB"; diff --git a/arch/arm/include/asm/arch-bcmcygnus/configs.h b/arch/arm/include/asm/arch-bcmcygnus/configs.h index af7f3bff57..92b1c5e2d6 100644 --- a/arch/arm/include/asm/arch-bcmcygnus/configs.h +++ b/arch/arm/include/asm/arch-bcmcygnus/configs.h @@ -1,5 +1,5 @@ /* - * Copyright 2014 Broadcom Corporation. + * Copyright 2014-2017 Broadcom. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -23,10 +23,6 @@ #define CONFIG_SYS_NS16550_COM3 0x18023000 /* Ethernet */ -#define CONFIG_BCM_SF2_ETH -#define CONFIG_BCM_SF2_ETH_GMAC - -#define CONFIG_PHYLIB #define CONFIG_PHY_BROADCOM #define CONFIG_PHY_RESET_DELAY 10000 /* PHY reset delay in us*/ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 8ad199f60a..4afc338b8e 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -35,6 +35,7 @@ #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000) #define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000) #define CONFIG_SYS_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000) +#define CONFIG_SYS_EHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x07600000) #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/mp.h b/arch/arm/include/asm/arch-fsl-layerscape/mp.h index fd3f851b53..88f40c0897 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/mp.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/mp.h @@ -13,7 +13,7 @@ * uint64_t entry_addr; * uint64_t status; * uint64_t lpid; -* uint64_t os_arch; +* uint64_t arch_comp; * }; * we pad this struct to 64 bytes so each entry is in its own cacheline * the actual spin table is an array of these structures @@ -21,10 +21,16 @@ #define SPIN_TABLE_ELEM_ENTRY_ADDR_IDX 0 #define SPIN_TABLE_ELEM_STATUS_IDX 1 #define SPIN_TABLE_ELEM_LPID_IDX 2 -#define SPIN_TABLE_ELEM_OS_ARCH_IDX 3 +/* compare os arch and cpu arch */ +#define SPIN_TABLE_ELEM_ARCH_COMP_IDX 3 #define WORDS_PER_SPIN_TABLE_ENTRY 8 /* pad to 64 bytes */ #define SPIN_TABLE_ELEM_SIZE 64 +/* os arch is same as cpu arch */ +#define OS_ARCH_SAME 0 +/* os arch is different from cpu arch */ +#define OS_ARCH_DIFF 1 + #define id_to_core(x) ((x & 3) | (x >> 6)) #ifndef __ASSEMBLY__ extern u64 __spin_table[]; @@ -43,7 +49,4 @@ int is_core_online(u64 cpu_id); u32 cpu_pos_mask(void); #endif -#define IH_ARCH_ARM 2 /* ARM */ -#define IH_ARCH_ARM64 22 /* ARM64 */ - #endif /* _FSL_LAYERSCAPE_MP_H */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 497afe7b15..aeb12739aa 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -65,8 +65,8 @@ struct cpu_type { #define SVR_LS2084A 0x870910 #define SVR_LS2048A 0x870920 #define SVR_LS2044A 0x870930 -#define SVR_LS2081A 0x870919 -#define SVR_LS2041A 0x870915 +#define SVR_LS2081A 0x870918 +#define SVR_LS2041A 0x870914 #define SVR_DEV_LS2080A 0x8701 diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index 0c99bbdc93..dbe340d23e 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -236,8 +236,21 @@ #define VDD_MPU_ES2_HIGH 1250 #define VDD_MM_ES2_OD 1120 -#define VDD_MPU_ES2_LOW 880 -#define VDD_MM_ES2_LOW 880 +/* Efuse register offsets for OMAP5 platform */ +#define OMAP5_ES2_EFUSE_BASE 0x4A002000 +#define OMAP5_ES2_PROD_REGBITS 16 + +/* CONTROL_STD_FUSE_OPP_VDD_CORE_3 */ +#define OMAP5_ES2_PROD_CORE_OPNO_VMIN (OMAP5_ES2_EFUSE_BASE + 0x1D8) + +/* CONTROL_STD_FUSE_OPP_VDD_MM_4 */ +#define OMAP5_ES2_PROD_MM_OPNO_VMIN (OMAP5_ES2_EFUSE_BASE + 0x1A4) +/* CONTROL_STD_FUSE_OPP_VDD_MM_5 */ +#define OMAP5_ES2_PROD_MM_OPOD_VMIN (OMAP5_ES2_EFUSE_BASE + 0x1A8) +/* CONTROL_STD_FUSE_OPP_VDD_MPU_6 */ +#define OMAP5_ES2_PROD_MPU_OPNO_VMIN (OMAP5_ES2_EFUSE_BASE + 0x1C4) +/* CONTROL_STD_FUSE_OPP_VDD_MPU_7 */ +#define OMAP5_ES2_PROD_MPU_OPHI_VMIN (OMAP5_ES2_EFUSE_BASE + 0x1C8) /* DRA74x/75x/72x voltage settings in mv for OPP_NOM per DM */ #define VDD_MPU_DRA7_NOM 1150 diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 2f005dd3ad..b047f0d650 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -224,8 +224,8 @@ struct s32ktimer { #define OMAP_ABB_GPU_TXDONE_MASK (0x1 << 28) /* ABB efuse masks */ -#define OMAP5_ABB_FUSE_VSET_MASK (0x1F << 24) -#define OMAP5_ABB_FUSE_ENABLE_MASK (0x1 << 29) +#define OMAP5_PROD_ABB_FUSE_VSET_MASK (0x1F << 20) +#define OMAP5_PROD_ABB_FUSE_ENABLE_MASK (0x1 << 25) #define DRA7_ABB_FUSE_VSET_MASK (0x1F << 20) #define DRA7_ABB_FUSE_ENABLE_MASK (0x1 << 25) #define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK (0x1 << 10) diff --git a/arch/arm/include/asm/arch-rockchip/boot0.h b/arch/arm/include/asm/arch-rockchip/boot0.h index 7346876dc2..72d264bcbe 100644 --- a/arch/arm/include/asm/arch-rockchip/boot0.h +++ b/arch/arm/include/asm/arch-rockchip/boot0.h @@ -1,3 +1,4 @@ + /* * Copyright 2017 Theobroma Systems Design und Consulting GmbH * @@ -13,7 +14,17 @@ */ #ifdef CONFIG_SPL_BUILD - .space 0x4 /* space for the 'RK33' */ + /* + * We need to add 4 bytes of space for the 'RK33' at the + * beginning of the executable. However, as we want to keep + * this generic and make it applicable to builds that are like + * the RK3368 (TPL needs this, SPL doesn't) or the RK3399 (no + * TPL, but extra space needed in the SPL), we simply repeat + * the 'b reset' with the expectation that the first one will + * be overwritten, if this is the first stage contained in the + * final image created with mkimage)... + */ + b reset /* may be overwritten --- should be 'nop' or a 'b reset' */ #endif b reset diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h index cb0a935edc..c7e21bd605 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h @@ -85,7 +85,7 @@ enum { EMMC_PLL_SELECT_24MHZ, EMMC_DIV_SHIFT = 8, - EMMC_DIV_MASK = 0x3f < EMMC_DIV_SHIFT, + EMMC_DIV_MASK = 0x3f << EMMC_DIV_SHIFT, SDIO0_PLL_SHIFT = 6, SDIO0_PLL_MASK = 3 << SDIO0_PLL_SHIFT, diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h index 4910ee7387..2b1197fd46 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3368.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3368.h @@ -51,8 +51,6 @@ check_member(rk3368_cru, emmc_con[1], 0x41c); struct rk3368_clk_priv { struct rk3368_cru *cru; - ulong rate; - bool has_bwadj; }; enum { @@ -91,19 +89,26 @@ enum { MCU_CLK_DIV_SHIFT = 0, MCU_CLK_DIV_MASK = GENMASK(4, 0), + /* CLKSEL43_CON */ + GMAC_MUX_SEL_EXTCLK = BIT(8), + /* CLKSEL51_CON */ MMC_PLL_SEL_SHIFT = 8, MMC_PLL_SEL_MASK = GENMASK(9, 8), - MMC_PLL_SEL_CPLL = 0, - MMC_PLL_SEL_GPLL, - MMC_PLL_SEL_USBPHY_480M, - MMC_PLL_SEL_24M, + MMC_PLL_SEL_CPLL = (0 << MMC_PLL_SEL_SHIFT), + MMC_PLL_SEL_GPLL = (1 << MMC_PLL_SEL_SHIFT), + MMC_PLL_SEL_USBPHY_480M = (2 << MMC_PLL_SEL_SHIFT), + MMC_PLL_SEL_24M = (3 << MMC_PLL_SEL_SHIFT), MMC_CLK_DIV_SHIFT = 0, MMC_CLK_DIV_MASK = GENMASK(6, 0), /* SOFTRST1_CON */ MCU_PO_SRST_MASK = BIT(13), MCU_SYS_SRST_MASK = BIT(12), + DMA1_SRST_REQ = BIT(2), + + /* SOFTRST4_CON */ + DMA2_SRST_REQ = BIT(0), /* GLB_RST_CON */ PMU_GLB_SRST_CTRL_SHIFT = 2, diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h index cf830d04ea..033f067122 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3399.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3399.h @@ -12,12 +12,10 @@ /* Private data for the clock driver - used by rockchip_get_cru() */ struct rk3399_clk_priv { struct rk3399_cru *cru; - ulong rate; }; struct rk3399_pmuclk_priv { struct rk3399_pmucru *pmucru; - ulong rate; }; struct rk3399_pmucru { diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h b/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h new file mode 100644 index 0000000000..4e2b2337f2 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3368.h @@ -0,0 +1,187 @@ +/* + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __ASM_ARCH_DDR_RK3368_H__ +#define __ASM_ARCH_DDR_RK3368_H__ + +/* + * The RK3368 DDR PCTL differs from the incarnation in the RK3288 only + * in a few details. Most notably, it has an additional field to track + * tREFI in controller cycles (i.e. trefi_mem_ddr3). + */ +struct rk3368_ddr_pctl { + u32 scfg; + u32 sctl; + u32 stat; + u32 intrstat; + u32 reserved0[12]; + u32 mcmd; + u32 powctl; + u32 powstat; + u32 cmdtstat; + u32 cmdtstaten; + u32 reserved1[3]; + u32 mrrcfg0; + u32 mrrstat0; + u32 mrrstat1; + u32 reserved2[4]; + u32 mcfg1; + u32 mcfg; + u32 ppcfg; + u32 mstat; + u32 lpddr2zqcfg; + u32 reserved3; + u32 dtupdes; + u32 dtuna; + u32 dtune; + u32 dtuprd0; + u32 dtuprd1; + u32 dtuprd2; + u32 dtuprd3; + u32 dtuawdt; + u32 reserved4[3]; + u32 togcnt1u; + u32 tinit; + u32 trsth; + u32 togcnt100n; + u32 trefi; + u32 tmrd; + u32 trfc; + u32 trp; + u32 trtw; + u32 tal; + u32 tcl; + u32 tcwl; + u32 tras; + u32 trc; + u32 trcd; + u32 trrd; + u32 trtp; + u32 twr; + u32 twtr; + u32 texsr; + u32 txp; + u32 txpdll; + u32 tzqcs; + u32 tzqcsi; + u32 tdqs; + u32 tcksre; + u32 tcksrx; + u32 tcke; + u32 tmod; + u32 trstl; + u32 tzqcl; + u32 tmrr; + u32 tckesr; + u32 tdpd; + u32 trefi_mem_ddr3; + u32 reserved5[45]; + u32 dtuwactl; + u32 dturactl; + u32 dtucfg; + u32 dtuectl; + u32 dtuwd0; + u32 dtuwd1; + u32 dtuwd2; + u32 dtuwd3; + u32 dtuwdm; + u32 dturd0; + u32 dturd1; + u32 dturd2; + u32 dturd3; + u32 dtulfsrwd; + u32 dtulfsrrd; + u32 dtueaf; + u32 dfitctrldelay; + u32 dfiodtcfg; + u32 dfiodtcfg1; + u32 dfiodtrankmap; + u32 dfitphywrdata; + u32 dfitphywrlat; + u32 reserved7[2]; + u32 dfitrddataen; + u32 dfitphyrdlat; + u32 reserved8[2]; + u32 dfitphyupdtype0; + u32 dfitphyupdtype1; + u32 dfitphyupdtype2; + u32 dfitphyupdtype3; + u32 dfitctrlupdmin; + u32 dfitctrlupdmax; + u32 dfitctrlupddly; + u32 reserved9; + u32 dfiupdcfg; + u32 dfitrefmski; + u32 dfitctrlupdi; + u32 reserved10[4]; + u32 dfitrcfg0; + u32 dfitrstat0; + u32 dfitrwrlvlen; + u32 dfitrrdlvlen; + u32 dfitrrdlvlgateen; + u32 dfiststat0; + u32 dfistcfg0; + u32 dfistcfg1; + u32 reserved11; + u32 dfitdramclken; + u32 dfitdramclkdis; + u32 dfistcfg2; + u32 dfistparclr; + u32 dfistparlog; + u32 reserved12[3]; + u32 dfilpcfg0; + u32 reserved13[3]; + u32 dfitrwrlvlresp0; + u32 dfitrwrlvlresp1; + u32 dfitrwrlvlresp2; + u32 dfitrrdlvlresp0; + u32 dfitrrdlvlresp1; + u32 dfitrrdlvlresp2; + u32 dfitrwrlvldelay0; + u32 dfitrwrlvldelay1; + u32 dfitrwrlvldelay2; + u32 dfitrrdlvldelay0; + u32 dfitrrdlvldelay1; + u32 dfitrrdlvldelay2; + u32 dfitrrdlvlgatedelay0; + u32 dfitrrdlvlgatedelay1; + u32 dfitrrdlvlgatedelay2; + u32 dfitrcmd; + u32 reserved14[46]; + u32 ipvr; + u32 iptr; +}; +check_member(rk3368_ddr_pctl, iptr, 0x03fc); + +struct rk3368_ddrphy { + u32 reg[0x100]; +}; +check_member(rk3368_ddrphy, reg[0xff], 0x03fc); + +struct rk3368_msch { + u32 coreid; + u32 revisionid; + u32 ddrconf; + u32 ddrtiming; + u32 ddrmode; + u32 readlatency; + u32 reserved1[8]; + u32 activate; + u32 devtodev; +}; +check_member(rk3368_msch, devtodev, 0x003c); + +/* GRF_SOC_CON0 */ +enum { + NOC_RSP_ERR_STALL = BIT(9), + MOBILE_DDR_SEL = BIT(4), + DDR0_16BIT_EN = BIT(3), + MSCH0_MAINDDR3_DDR3 = BIT(2), + MSCH0_MAINPARTIALPOP = BIT(1), + UPCTL_C_ACTIVE = BIT(0), +}; + +#endif diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h index 93c4e7d4e1..6b6651acab 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3368.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3368.h @@ -1,4 +1,6 @@ -/* (C) Copyright 2016 Rockchip Electronics Co., Ltd +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH * * SPDX-License-Identifier: GPL-2.0+ */ @@ -74,8 +76,11 @@ struct rk3368_grf { u32 soc_con15; u32 soc_con16; u32 soc_con17; + u32 reserved5[0x6e]; + u32 ddrc0_con0; }; check_member(rk3368_grf, soc_con17, 0x444); +check_member(rk3368_grf, ddrc0_con0, 0x600); struct rk3368_pmu_grf { u32 gpio0a_iomux; @@ -92,323 +97,11 @@ struct rk3368_pmu_grf { u32 gpio0d_drv; u32 gpio0l_sr; u32 gpio0h_sr; - u32 reserved[(0x200 - 0x34) / 4 - 1]; + u32 reserved[0x72]; u32 os_reg[4]; }; -check_member(rk3368_pmu_grf, os_reg[3], 0x20c); - -/*GRF_GPIO0C_IOMUX*/ -enum { - GPIO0C7_SHIFT = 14, - GPIO0C7_MASK = 3 << GPIO0C7_SHIFT, - GPIO0C7_GPIO = 0, - GPIO0C7_LCDC_D19, - GPIO0C7_TRACE_D9, - GPIO0C7_UART1_RTSN, - - GPIO0C6_SHIFT = 12, - GPIO0C6_MASK = 3 << GPIO0C6_SHIFT, - GPIO0C6_GPIO = 0, - GPIO0C6_LCDC_D18, - GPIO0C6_TRACE_D8, - GPIO0C6_UART1_CTSN, - - GPIO0C5_SHIFT = 10, - GPIO0C5_MASK = 3 << GPIO0C5_SHIFT, - GPIO0C5_GPIO = 0, - GPIO0C5_LCDC_D17, - GPIO0C5_TRACE_D7, - GPIO0C5_UART1_SOUT, - - GPIO0C4_SHIFT = 8, - GPIO0C4_MASK = 3 << GPIO0C4_SHIFT, - GPIO0C4_GPIO = 0, - GPIO0C4_LCDC_D16, - GPIO0C4_TRACE_D6, - GPIO0C4_UART1_SIN, - - GPIO0C3_SHIFT = 6, - GPIO0C3_MASK = 3 << GPIO0C3_SHIFT, - GPIO0C3_GPIO = 0, - GPIO0C3_LCDC_D15, - GPIO0C3_TRACE_D5, - GPIO0C3_MCU_JTAG_TDO, - - GPIO0C2_SHIFT = 4, - GPIO0C2_MASK = 3 << GPIO0C2_SHIFT, - GPIO0C2_GPIO = 0, - GPIO0C2_LCDC_D14, - GPIO0C2_TRACE_D4, - GPIO0C2_MCU_JTAG_TDI, - - GPIO0C1_SHIFT = 2, - GPIO0C1_MASK = 3 << GPIO0C1_SHIFT, - GPIO0C1_GPIO = 0, - GPIO0C1_LCDC_D13, - GPIO0C1_TRACE_D3, - GPIO0C1_MCU_JTAG_TRTSN, - - GPIO0C0_SHIFT = 0, - GPIO0C0_MASK = 3 << GPIO0C0_SHIFT, - GPIO0C0_GPIO = 0, - GPIO0C0_LCDC_D12, - GPIO0C0_TRACE_D2, - GPIO0C0_MCU_JTAG_TDO, -}; - -/*GRF_GPIO0D_IOMUX*/ -enum { - GPIO0D7_SHIFT = 14, - GPIO0D7_MASK = 3 << GPIO0D7_SHIFT, - GPIO0D7_GPIO = 0, - GPIO0D7_LCDC_DCLK, - GPIO0D7_TRACE_CTL, - GPIO0D7_PMU_DEBUG5, - - GPIO0D6_SHIFT = 12, - GPIO0D6_MASK = 3 << GPIO0D6_SHIFT, - GPIO0D6_GPIO = 0, - GPIO0D6_LCDC_DEN, - GPIO0D6_TRACE_CLK, - GPIO0D6_PMU_DEBUG4, - - GPIO0D5_SHIFT = 10, - GPIO0D5_MASK = 3 << GPIO0D5_SHIFT, - GPIO0D5_GPIO = 0, - GPIO0D5_LCDC_VSYNC, - GPIO0D5_TRACE_D15, - GPIO0D5_PMU_DEBUG3, - - GPIO0D4_SHIFT = 8, - GPIO0D4_MASK = 3 << GPIO0D4_SHIFT, - GPIO0D4_GPIO = 0, - GPIO0D4_LCDC_HSYNC, - GPIO0D4_TRACE_D14, - GPIO0D4_PMU_DEBUG2, - - GPIO0D3_SHIFT = 6, - GPIO0D3_MASK = 3 << GPIO0D3_SHIFT, - GPIO0D3_GPIO = 0, - GPIO0D3_LCDC_D23, - GPIO0D3_TRACE_D13, - GPIO0D3_UART4_SIN, - - GPIO0D2_SHIFT = 4, - GPIO0D2_MASK = 3 << GPIO0D2_SHIFT, - GPIO0D2_GPIO = 0, - GPIO0D2_LCDC_D22, - GPIO0D2_TRACE_D12, - GPIO0D2_UART4_SOUT, - - GPIO0D1_SHIFT = 2, - GPIO0D1_MASK = 3 << GPIO0D1_SHIFT, - GPIO0D1_GPIO = 0, - GPIO0D1_LCDC_D21, - GPIO0D1_TRACE_D11, - GPIO0D1_UART4_RTSN, - - GPIO0D0_SHIFT = 0, - GPIO0D0_MASK = 3 << GPIO0D0_SHIFT, - GPIO0D0_GPIO = 0, - GPIO0D0_LCDC_D20, - GPIO0D0_TRACE_D10, - GPIO0D0_UART4_CTSN, -}; - -/*GRF_GPIO2A_IOMUX*/ -enum { - GPIO2A7_SHIFT = 14, - GPIO2A7_MASK = 3 << GPIO2A7_SHIFT, - GPIO2A7_GPIO = 0, - GPIO2A7_SDMMC0_D2, - GPIO2A7_JTAG_TCK, - - GPIO2A6_SHIFT = 12, - GPIO2A6_MASK = 3 << GPIO2A6_SHIFT, - GPIO2A6_GPIO = 0, - GPIO2A6_SDMMC0_D1, - GPIO2A6_UART2_SIN, - - GPIO2A5_SHIFT = 10, - GPIO2A5_MASK = 3 << GPIO2A5_SHIFT, - GPIO2A5_GPIO = 0, - GPIO2A5_SDMMC0_D0, - GPIO2A5_UART2_SOUT, - - GPIO2A4_SHIFT = 8, - GPIO2A4_MASK = 3 << GPIO2A4_SHIFT, - GPIO2A4_GPIO = 0, - GPIO2A4_FLASH_DQS, - GPIO2A4_EMMC_CLKO, - - GPIO2A3_SHIFT = 6, - GPIO2A3_MASK = 3 << GPIO2A3_SHIFT, - GPIO2A3_GPIO = 0, - GPIO2A3_FLASH_CSN3, - GPIO2A3_EMMC_RSTNO, - - GPIO2A2_SHIFT = 4, - GPIO2A2_MASK = 3 << GPIO2A2_SHIFT, - GPIO2A2_GPIO = 0, - GPIO2A2_FLASH_CSN2, - - GPIO2A1_SHIFT = 2, - GPIO2A1_MASK = 3 << GPIO2A1_SHIFT, - GPIO2A1_GPIO = 0, - GPIO2A1_FLASH_CSN1, - - GPIO2A0_SHIFT = 0, - GPIO2A0_MASK = 3 << GPIO2A0_SHIFT, - GPIO2A0_GPIO = 0, - GPIO2A0_FLASH_CSN0, -}; - -/*GRF_GPIO2D_IOMUX*/ -enum { - GPIO2D7_SHIFT = 14, - GPIO2D7_MASK = 3 << GPIO2D7_SHIFT, - GPIO2D7_GPIO = 0, - GPIO2D7_SDIO0_D3, - - GPIO2D6_SHIFT = 12, - GPIO2D6_MASK = 3 << GPIO2D6_SHIFT, - GPIO2D6_GPIO = 0, - GPIO2D6_SDIO0_D2, - - GPIO2D5_SHIFT = 10, - GPIO2D5_MASK = 3 << GPIO2D5_SHIFT, - GPIO2D5_GPIO = 0, - GPIO2D5_SDIO0_D1, - - GPIO2D4_SHIFT = 8, - GPIO2D4_MASK = 3 << GPIO2D4_SHIFT, - GPIO2D4_GPIO = 0, - GPIO2D4_SDIO0_D0, - - GPIO2D3_SHIFT = 6, - GPIO2D3_MASK = 3 << GPIO2D3_SHIFT, - GPIO2D3_GPIO = 0, - GPIO2D3_UART0_RTS0, - - GPIO2D2_SHIFT = 4, - GPIO2D2_MASK = 3 << GPIO2D2_SHIFT, - GPIO2D2_GPIO = 0, - GPIO2D2_UART0_CTS0, - - GPIO2D1_SHIFT = 2, - GPIO2D1_MASK = 3 << GPIO2D1_SHIFT, - GPIO2D1_GPIO = 0, - GPIO2D1_UART0_SOUT, - - GPIO2D0_SHIFT = 0, - GPIO2D0_MASK = 3 << GPIO2D0_SHIFT, - GPIO2D0_GPIO = 0, - GPIO2D0_UART0_SIN, -}; - -/*GRF_GPIO3C_IOMUX*/ -enum { - GPIO3C7_SHIFT = 14, - GPIO3C7_MASK = 3 << GPIO3C7_SHIFT, - GPIO3C7_GPIO = 0, - GPIO3C7_EDPHDMI_CECINOUT, - GPIO3C7_ISP_FLASHTRIGIN, - - GPIO3C6_SHIFT = 12, - GPIO3C6_MASK = 3 << GPIO3C6_SHIFT, - GPIO3C6_GPIO = 0, - GPIO3C6_MAC_CLK, - GPIO3C6_ISP_SHUTTERTRIG, - - GPIO3C5_SHIFT = 10, - GPIO3C5_MASK = 3 << GPIO3C5_SHIFT, - GPIO3C5_GPIO = 0, - GPIO3C5_MAC_RXER, - GPIO3C5_ISP_PRELIGHTTRIG, - - GPIO3C4_SHIFT = 8, - GPIO3C4_MASK = 3 << GPIO3C4_SHIFT, - GPIO3C4_GPIO = 0, - GPIO3C4_MAC_RXDV, - GPIO3C4_ISP_FLASHTRIGOUT, - - GPIO3C3_SHIFT = 6, - GPIO3C3_MASK = 3 << GPIO3C3_SHIFT, - GPIO3C3_GPIO = 0, - GPIO3C3_MAC_RXDV, - GPIO3C3_EMMC_RSTNO, - - GPIO3C2_SHIFT = 4, - GPIO3C2_MASK = 3 << GPIO3C2_SHIFT, - GPIO3C2_MAC_MDC = 0, - GPIO3C2_ISP_SHUTTEREN, - - GPIO3C1_SHIFT = 2, - GPIO3C1_MASK = 3 << GPIO3C1_SHIFT, - GPIO3C1_GPIO = 0, - GPIO3C1_MAC_RXD2, - GPIO3C1_UART3_RTSN, - - GPIO3C0_SHIFT = 0, - GPIO3C0_MASK = 3 << GPIO3C0_SHIFT, - GPIO3C0_GPIO = 0, - GPIO3C0_MAC_RXD1, - GPIO3C0_UART3_CTSN, - GPIO3C0_GPS_RFCLK, -}; - -/*GRF_GPIO3D_IOMUX*/ -enum { - GPIO3D7_SHIFT = 14, - GPIO3D7_MASK = 3 << GPIO3D7_SHIFT, - GPIO3D7_GPIO = 0, - GPIO3D7_SC_VCC18V, - GPIO3D7_I2C2_SDA, - GPIO3D7_GPUJTAG_TCK, - - GPIO3D6_SHIFT = 12, - GPIO3D6_MASK = 3 << GPIO3D6_SHIFT, - GPIO3D6_GPIO = 0, - GPIO3D6_IR_TX, - GPIO3D6_UART3_SOUT, - GPIO3D6_PWM3, - - GPIO3D5_SHIFT = 10, - GPIO3D5_MASK = 3 << GPIO3D5_SHIFT, - GPIO3D5_GPIO = 0, - GPIO3D5_IR_RX, - GPIO3D5_UART3_SIN, - - GPIO3D4_SHIFT = 8, - GPIO3D4_MASK = 3 << GPIO3D4_SHIFT, - GPIO3D4_GPIO = 0, - GPIO3D4_MAC_TXCLKOUT, - GPIO3D4_SPI1_CSN1, - - GPIO3D3_SHIFT = 6, - GPIO3D3_MASK = 3 << GPIO3D3_SHIFT, - GPIO3D3_GPIO = 0, - GPIO3D3_HDMII2C_SCL, - GPIO3D3_I2C5_SCL, - - GPIO3D2_SHIFT = 4, - GPIO3D2_MASK = 3 << GPIO3D2_SHIFT, - GPIO3D2_GPIO = 0, - GPIO3D2_HDMII2C_SDA, - GPIO3D2_I2C5_SDA, - - GPIO3D1_SHIFT = 2, - GPIO3D1_MASK = 3 << GPIO3D1_SHIFT, - GPIO3D1_GPIO = 0, - GPIO3D1_MAC_RXCLKIN, - GPIO3D1_I2C4_SCL, - - GPIO3D0_SHIFT = 0, - GPIO3D0_MASK = 3 << GPIO3D0_SHIFT, - GPIO3D0_GPIO = 0, - GPIO3D0_MAC_MDIO, - GPIO3D0_I2C4_SDA, -}; +check_member(rk3368_pmu_grf, gpio0h_sr, 0x34); +check_member(rk3368_pmu_grf, os_reg[0], 0x200); /*GRF_SOC_CON11/12/13*/ enum { @@ -439,4 +132,5 @@ enum { MCU_CODE_BASE_BIT31_BIT28_SHIFT = 0, MCU_CODE_BASE_BIT31_BIT28_MASK = GENMASK(3, 0), }; + #endif diff --git a/arch/arm/include/asm/arch-rockchip/pwm.h b/arch/arm/include/asm/arch-rockchip/pwm.h index 08ff94591c..b1d8047691 100644 --- a/arch/arm/include/asm/arch-rockchip/pwm.h +++ b/arch/arm/include/asm/arch-rockchip/pwm.h @@ -25,9 +25,11 @@ check_member(rk3288_pwm, ctrl, 0xc); #define PWM_DUTY_POSTIVE (1 << 3) #define PWM_DUTY_NEGATIVE (0 << 3) +#define PWM_DUTY_MASK (1 << 3) #define PWM_INACTIVE_POSTIVE (1 << 4) #define PWM_INACTIVE_NEGATIVE (0 << 4) +#define PWM_INACTIVE_MASK (1 << 4) #define PWM_OUTPUT_LEFT (0 << 5) #define PWM_OUTPUT_CENTER (1 << 5) diff --git a/arch/arm/include/asm/arch-rockchip/timer.h b/arch/arm/include/asm/arch-rockchip/timer.h index 1d044bbda5..c23c5093b7 100644 --- a/arch/arm/include/asm/arch-rockchip/timer.h +++ b/arch/arm/include/asm/arch-rockchip/timer.h @@ -8,12 +8,12 @@ #define __ASM_ARCH_TIMER_H struct rk_timer { - unsigned int timer_load_count0; - unsigned int timer_load_count1; - unsigned int timer_curr_value0; - unsigned int timer_curr_value1; - unsigned int timer_ctrl_reg; - unsigned int timer_int_status; + u32 timer_load_count0; + u32 timer_load_count1; + u32 timer_curr_value0; + u32 timer_curr_value1; + u32 timer_ctrl_reg; + u32 timer_int_status; }; void rockchip_timer_init(void); diff --git a/arch/arm/include/asm/arch-stm32f1/gpio.h b/arch/arm/include/asm/arch-stm32f1/gpio.h deleted file mode 100644 index 8e8712fecc..0000000000 --- a/arch/arm/include/asm/arch-stm32f1/gpio.h +++ /dev/null @@ -1,118 +0,0 @@ -/* - * (C) Copyright 2011 - * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com - * - * (C) Copyright 2015 - * Kamil Lulko, <kamil.lulko@gmail.com> - * - * Copyright 2015 ATS Advanced Telematics Systems GmbH - * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _STM32_GPIO_H_ -#define _STM32_GPIO_H_ - -enum stm32_gpio_port { - STM32_GPIO_PORT_A = 0, - STM32_GPIO_PORT_B, - STM32_GPIO_PORT_C, - STM32_GPIO_PORT_D, - STM32_GPIO_PORT_E, - STM32_GPIO_PORT_F, - STM32_GPIO_PORT_G, -}; - -enum stm32_gpio_pin { - STM32_GPIO_PIN_0 = 0, - STM32_GPIO_PIN_1, - STM32_GPIO_PIN_2, - STM32_GPIO_PIN_3, - STM32_GPIO_PIN_4, - STM32_GPIO_PIN_5, - STM32_GPIO_PIN_6, - STM32_GPIO_PIN_7, - STM32_GPIO_PIN_8, - STM32_GPIO_PIN_9, - STM32_GPIO_PIN_10, - STM32_GPIO_PIN_11, - STM32_GPIO_PIN_12, - STM32_GPIO_PIN_13, - STM32_GPIO_PIN_14, - STM32_GPIO_PIN_15 -}; - -enum stm32_gpio_icnf { - STM32_GPIO_ICNF_AN = 0, - STM32_GPIO_ICNF_IN_FLT, - STM32_GPIO_ICNF_IN_PUD, - STM32_GPIO_ICNF_RSVD -}; - -enum stm32_gpio_ocnf { - STM32_GPIO_OCNF_GP_PP = 0, - STM32_GPIO_OCNF_GP_OD, - STM32_GPIO_OCNF_AF_PP, - STM32_GPIO_OCNF_AF_OD -}; - -enum stm32_gpio_pupd { - STM32_GPIO_PUPD_DOWN = 0, - STM32_GPIO_PUPD_UP, -}; - -enum stm32_gpio_mode { - STM32_GPIO_MODE_IN = 0, - STM32_GPIO_MODE_OUT_10M, - STM32_GPIO_MODE_OUT_2M, - STM32_GPIO_MODE_OUT_50M -}; - -enum stm32_gpio_af { - STM32_GPIO_AF0 = 0, - STM32_GPIO_AF1, - STM32_GPIO_AF2, - STM32_GPIO_AF3, - STM32_GPIO_AF4, - STM32_GPIO_AF5, - STM32_GPIO_AF6, - STM32_GPIO_AF7, - STM32_GPIO_AF8, - STM32_GPIO_AF9, - STM32_GPIO_AF10, - STM32_GPIO_AF11, - STM32_GPIO_AF12, - STM32_GPIO_AF13, - STM32_GPIO_AF14, - STM32_GPIO_AF15 -}; - -struct stm32_gpio_dsc { - enum stm32_gpio_port port; - enum stm32_gpio_pin pin; -}; - -struct stm32_gpio_ctl { - enum stm32_gpio_icnf icnf; - enum stm32_gpio_ocnf ocnf; - enum stm32_gpio_mode mode; - enum stm32_gpio_pupd pupd; - enum stm32_gpio_af af; -}; - -static inline unsigned stm32_gpio_to_port(unsigned gpio) -{ - return gpio / 16; -} - -static inline unsigned stm32_gpio_to_pin(unsigned gpio) -{ - return gpio % 16; -} - -int stm32_gpio_config(const struct stm32_gpio_dsc *gpio_dsc, - const struct stm32_gpio_ctl *gpio_ctl); -int stm32_gpout_set(const struct stm32_gpio_dsc *gpio_dsc, int state); - -#endif /* _STM32_GPIO_H_ */ diff --git a/arch/arm/include/asm/arch-stm32f1/stm32.h b/arch/arm/include/asm/arch-stm32f1/stm32.h deleted file mode 100644 index 1af73c5428..0000000000 --- a/arch/arm/include/asm/arch-stm32f1/stm32.h +++ /dev/null @@ -1,124 +0,0 @@ -/* - * (C) Copyright 2011 - * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com - * - * (C) Copyright 2015 - * Kamil Lulko, <kamil.lulko@gmail.com> - * - * Copyright 2015 ATS Advanced Telematics Systems GmbH - * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _MACH_STM32_H_ -#define _MACH_STM32_H_ - -/* - * Peripheral memory map - */ -#define STM32_PERIPH_BASE 0x40000000 -#define STM32_APB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00000000) -#define STM32_APB2PERIPH_BASE (STM32_PERIPH_BASE + 0x00010000) -#define STM32_AHB1PERIPH_BASE (STM32_PERIPH_BASE + 0x00018000) - -#define STM32_BUS_MASK 0xFFFF0000 - -#define STM32_GPIOA_BASE (STM32_APB2PERIPH_BASE + 0x0800) -#define STM32_GPIOB_BASE (STM32_APB2PERIPH_BASE + 0x0C00) -#define STM32_GPIOC_BASE (STM32_APB2PERIPH_BASE + 0x1000) -#define STM32_GPIOD_BASE (STM32_APB2PERIPH_BASE + 0x1400) -#define STM32_GPIOE_BASE (STM32_APB2PERIPH_BASE + 0x1800) -#define STM32_GPIOF_BASE (STM32_APB2PERIPH_BASE + 0x1C00) -#define STM32_GPIOG_BASE (STM32_APB2PERIPH_BASE + 0x2000) - -/* - * Register maps - */ -struct stm32_des_regs { - u16 flash_size; - u16 pad1; - u32 pad2; - u32 uid0; - u32 uid1; - u32 uid2; -}; - -struct stm32_rcc_regs { - u32 cr; /* RCC clock control */ - u32 cfgr; /* RCC clock configuration */ - u32 cir; /* RCC clock interrupt */ - u32 apb2rstr; /* RCC APB2 peripheral reset */ - u32 apb1rstr; /* RCC APB1 peripheral reset */ - u32 ahbenr; /* RCC AHB peripheral clock enable */ - u32 apb2enr; /* RCC APB2 peripheral clock enable */ - u32 apb1enr; /* RCC APB1 peripheral clock enable */ - u32 bdcr; /* RCC Backup domain control */ - u32 csr; /* RCC clock control & status */ -}; - -struct stm32_pwr_regs { - u32 cr; - u32 csr; -}; - -struct stm32_flash_regs { - u32 acr; - u32 keyr; - u32 optkeyr; - u32 sr; - u32 cr; - u32 ar; - u32 rsvd1; /* Reserved */ - u32 obr; - u32 wrpr; - u32 rsvd2[8]; /* Reserved */ - u32 keyr2; - u32 rsvd3; - u32 sr2; - u32 cr2; - u32 ar2; -}; - -/* Per bank register set for XL devices */ -struct stm32_flash_bank_regs { - u32 keyr; - u32 rsvd; /* Reserved */ - u32 sr; - u32 cr; - u32 ar; -}; - -/* - * Registers access macros - */ -#define STM32_DES_BASE (0x1ffff7e0) -#define STM32_DES ((struct stm32_des_regs *)STM32_DES_BASE) - -#define STM32_RCC_BASE (STM32_AHB1PERIPH_BASE + 0x9000) -#define STM32_RCC ((struct stm32_rcc_regs *)STM32_RCC_BASE) - -#define STM32_PWR_BASE (STM32_APB1PERIPH_BASE + 0x7000) -#define STM32_PWR ((struct stm32_pwr_regs *)STM32_PWR_BASE) - -#define STM32_FLASH_BASE (STM32_AHB1PERIPH_BASE + 0xa000) -#define STM32_FLASH ((struct stm32_flash_regs *)STM32_FLASH_BASE) - -#define STM32_FLASH_SR_BSY (1 << 0) - -#define STM32_FLASH_CR_PG (1 << 0) -#define STM32_FLASH_CR_PER (1 << 1) -#define STM32_FLASH_CR_STRT (1 << 6) -#define STM32_FLASH_CR_LOCK (1 << 7) - -enum clock { - CLOCK_CORE, - CLOCK_AHB, - CLOCK_APB1, - CLOCK_APB2 -}; - -int configure_clocks(void); -unsigned long clock_get(enum clock clck); - -#endif /* _MACH_STM32_H_ */ diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h index f62b2a4378..92180db321 100644 --- a/arch/arm/include/asm/arch-tegra/clock.h +++ b/arch/arm/include/asm/arch-tegra/clock.h @@ -266,7 +266,7 @@ void clock_ll_start_uart(enum periph_id periph_id); * @param node Node to look at * @return peripheral ID, or PERIPH_ID_NONE if none */ -enum periph_id clock_decode_periph_id(const void *blob, int node); +int clock_decode_periph_id(struct udevice *dev); /** * Checks if the oscillator bypass is enabled (XOBP bit) diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h index 3add1b3c09..3b9711d28e 100644 --- a/arch/arm/include/asm/arch-tegra/tegra.h +++ b/arch/arm/include/asm/arch-tegra/tegra.h @@ -97,6 +97,11 @@ enum { TEGRA_SOC_UNKNOWN = -1, }; +/* Tegra system controller (SYSCON) devices */ +enum { + TEGRA_SYSCON_PMC, +}; + #else /* __ASSEMBLY__ */ #define PRM_RSTCTRL NV_PA_PMC_BASE #endif diff --git a/arch/arm/include/asm/arch-tegra/xusb-padctl.h b/arch/arm/include/asm/arch-tegra/xusb-padctl.h index b4b4c8ba4d..deccdf455d 100644 --- a/arch/arm/include/asm/arch-tegra/xusb-padctl.h +++ b/arch/arm/include/asm/arch-tegra/xusb-padctl.h @@ -15,7 +15,7 @@ struct tegra_xusb_phy; */ struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type); -void tegra_xusb_padctl_init(const void *fdt); +void tegra_xusb_padctl_init(void); int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy); int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy); int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy); diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h index cf187f3111..cab29ba036 100644 --- a/arch/arm/include/asm/arch-zynqmp/hardware.h +++ b/arch/arm/include/asm/arch-zynqmp/hardware.h @@ -48,18 +48,9 @@ struct crlapb_regs { #define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR) #define ZYNQMP_IOU_SCNTR_SECURE 0xFF260000 -#define ZYNQMP_IOU_SCNTR 0xFF250000 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN 0x1 #define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2 -struct iou_scntr { - u32 counter_control_register; - u32 reserved0[7]; - u32 base_frequency_id_register; -}; - -#define iou_scntr ((struct iou_scntr *)ZYNQMP_IOU_SCNTR) - struct iou_scntr_secure { u32 counter_control_register; u32 reserved0[7]; @@ -153,4 +144,7 @@ struct pmu_regs { #define pmu_base ((struct pmu_regs *)ZYNQMP_PMU_BASEADDR) +#define ZYNQMP_CSU_IDCODE_ADDR 0xFFCA0040 +#define ZYNQMP_CSU_VER_ADDR 0xFFCA0044 + #endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-zynqmp/sys_proto.h b/arch/arm/include/asm/arch-zynqmp/sys_proto.h index d91d98a119..e52abd71a5 100644 --- a/arch/arm/include/asm/arch-zynqmp/sys_proto.h +++ b/arch/arm/include/asm/arch-zynqmp/sys_proto.h @@ -10,6 +10,25 @@ #define PAYLOAD_ARG_CNT 5 +#define ZYNQMP_CSU_SILICON_VER_MASK 0xF + +enum { + IDCODE, + VERSION, +}; + +enum { + ZYNQMP_SILICON_V1, + ZYNQMP_SILICON_V2, + ZYNQMP_SILICON_V3, + ZYNQMP_SILICON_V4, +}; + +enum { + TCM_LOCK, + TCM_SPLIT, +}; + int zynq_slcr_get_mio_pin_status(const char *periph); unsigned int zynqmp_get_silicon_version(void); @@ -24,4 +43,8 @@ int zynqmp_mmio_read(const u32 address, u32 *value); int invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3, u32 *ret_payload); +void initialize_tcm(bool mode); + +int chip_id(unsigned char id); + #endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/arch/arm/include/asm/ehci-omap.h b/arch/arm/include/asm/ehci-omap.h index 5a53e403a6..9dbb2c4c66 100644 --- a/arch/arm/include/asm/ehci-omap.h +++ b/arch/arm/include/asm/ehci-omap.h @@ -19,11 +19,7 @@ enum usbhs_omap_port_mode { OMAP_EHCI_PORT_MODE_HSIC, }; -#ifdef CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS -#define OMAP_HS_USB_PORTS CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS -#else #define OMAP_HS_USB_PORTS 3 -#endif #define is_ehci_phy_mode(x) ((x) == OMAP_EHCI_PORT_MODE_PHY) #define is_ehci_tll_mode(x) ((x) == OMAP_EHCI_PORT_MODE_TLL) diff --git a/arch/arm/include/asm/spl.h b/arch/arm/include/asm/spl.h index 0e674704ab..df45511699 100644 --- a/arch/arm/include/asm/spl.h +++ b/arch/arm/include/asm/spl.h @@ -30,6 +30,7 @@ enum { BOOT_DEVICE_BOARD, BOOT_DEVICE_DFU, BOOT_DEVICE_XIP, + BOOT_DEVICE_BOOTROM, BOOT_DEVICE_NONE }; #endif diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 704849bd0c..5c62d9c144 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -216,7 +216,7 @@ static void do_nonsec_virt_switch(void) /* Subcommand: PREP */ static void boot_prep_linux(bootm_headers_t *images) { - char *commandline = getenv("bootargs"); + char *commandline = env_get("bootargs"); if (IMAGE_ENABLE_OF_LIBFDT && images->ft_len) { #ifdef CONFIG_OF_LIBFDT @@ -273,7 +273,7 @@ __weak bool armv7_boot_nonsec_default(void) #ifdef CONFIG_ARMV7_NONSEC bool armv7_boot_nonsec(void) { - char *s = getenv("bootm_boot_mode"); + char *s = env_get("bootm_boot_mode"); bool nonsec = armv7_boot_nonsec_default(); if (s && !strcmp(s, "sec")) @@ -361,7 +361,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) ulong addr = (ulong)kernel_entry | 1; kernel_entry = (void *)addr; #endif - s = getenv("machid"); + s = env_get("machid"); if (s) { if (strict_strtoul(s, 16, &machid) < 0) { debug("strict_strtoul failed!\n"); diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S index 57e728f9f2..62fad452b2 100644 --- a/arch/arm/lib/crt0_64.S +++ b/arch/arm/lib/crt0_64.S @@ -69,7 +69,9 @@ ENTRY(_main) /* * Set up initial C runtime environment and call board_init_f(0). */ -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) +#if defined(CONFIG_TPL_BUILD) && defined(CONFIG_TPL_NEEDS_SEPARATE_STACK) + ldr x0, =(CONFIG_TPL_STACK) +#elif defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) ldr x0, =(CONFIG_SPL_STACK) #else ldr x0, =(CONFIG_SYS_INIT_SP_ADDR) diff --git a/arch/arm/lib/semihosting.c b/arch/arm/lib/semihosting.c index 415ac89de9..bcd16ee591 100644 --- a/arch/arm/lib/semihosting.c +++ b/arch/arm/lib/semihosting.c @@ -200,7 +200,7 @@ static int do_smhload(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /* Optionally save returned end to the environment */ if (argc == 4) { sprintf(end_str, "0x%08lx", end_addr); - setenv(argv[3], end_str); + env_set(argv[3], end_str); } } else { return CMD_RET_USAGE; diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 033c1efd2b..20f7eeaf09 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -36,6 +36,7 @@ config TARGET_GURNARD config TARGET_AT91SAM9261EK bool "Atmel at91sam9261 reference board" select CPU_ARM926EJS + select BOARD_EARLY_INIT_F config TARGET_PM9261 bool "Ronetix pm9261 board" @@ -198,4 +199,8 @@ source "board/siemens/corvus/Kconfig" source "board/siemens/taurus/Kconfig" source "board/siemens/smartweb/Kconfig" +config SPL_LDSCRIPT + default "arch/arm/mach-at91/arm926ejs/u-boot-spl.lds" if CPU_ARM926EJS + default "arch/arm/mach-at91/armv7/u-boot-spl.lds" if CPU_V7 + endif diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 4757f2496d..35e4e9bcea 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -53,4 +53,8 @@ source "board/davinci/ea20/Kconfig" source "board/omicron/calimain/Kconfig" source "board/lego/ev3/Kconfig" +config SPL_LDSCRIPT + default "board/$(BOARDDIR)/u-boot-spl-ipam390.lds" if TARGET_IPAM390 + default "board/$(BOARDDIR)/u-boot-spl-da850evm.lds" + endif diff --git a/arch/arm/mach-davinci/misc.c b/arch/arm/mach-davinci/misc.c index ec331ba6bb..461ff778c2 100644 --- a/arch/arm/mach-davinci/misc.c +++ b/arch/arm/mach-davinci/misc.c @@ -90,7 +90,7 @@ void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr) uint8_t env_enetaddr[6]; int ret; - ret = eth_getenv_enetaddr_by_index("eth", 0, env_enetaddr); + ret = eth_env_get_enetaddr_by_index("eth", 0, env_enetaddr); if (!ret) { /* * There is no MAC address in the environment, so we @@ -99,7 +99,7 @@ void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr) debug("### Setting environment from EEPROM MAC address = " "\"%pM\"\n", env_enetaddr); - ret = !eth_setenv_enetaddr("ethaddr", rom_enetaddr); + ret = !eth_env_set_enetaddr("ethaddr", rom_enetaddr); } if (!ret) printf("Failed to set mac address from EEPROM: %d\n", ret); diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index d1aa68db20..2fb84f9453 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -8,7 +8,6 @@ config ARCH_EXYNOS4 bool "Exynos4 SoC family" select CPU_V7 select BOARD_EARLY_INIT_F - imply ENV_IS_IN_MMC help Samsung Exynos4 SoC family are based on ARM Cortex-A9 CPU. There are multiple SoCs in this family including Exynos4210, Exynos4412, @@ -161,4 +160,7 @@ source "board/samsung/smdk5250/Kconfig" source "board/samsung/smdk5420/Kconfig" source "board/samsung/espresso7420/Kconfig" +config SPL_LDSCRIPT + default "board/samsung/common/exynos-uboot-spl.lds" if ARCH_EXYNOS5 || ARCH_EXYNOS4 + endif diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index d1990602f8..a1aa36bc22 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -38,7 +38,6 @@ config MX6SL config MX6SX select ROM_UNIFIED_SECTIONS bool - imply ENV_IS_IN_MMC config MX6SLL select ROM_UNIFIED_SECTIONS @@ -153,6 +152,7 @@ config TARGET_GW_VENTANA bool "gw_ventana" select SUPPORT_SPL imply CMD_SATA + imply CMD_SPL config TARGET_KOSAGI_NOVENA bool "Kosagi Novena" diff --git a/arch/arm/mach-imx/mx6/opos6ul.c b/arch/arm/mach-imx/mx6/opos6ul.c index 22b244079b..f8d7e8ee68 100644 --- a/arch/arm/mach-imx/mx6/opos6ul.c +++ b/arch/arm/mach-imx/mx6/opos6ul.c @@ -132,7 +132,7 @@ int board_late_init(void) /* In bootstrap don't use the env vars */ if (((reg & 0x3000000) >> 24) == 0x1) { set_default_env(NULL); - setenv("preboot", ""); + env_set("preboot", ""); } return opos6ul_board_late_init(); diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig index 7053697f9b..aea85265ef 100644 --- a/arch/arm/mach-imx/mx7/Kconfig +++ b/arch/arm/mach-imx/mx7/Kconfig @@ -13,7 +13,6 @@ config MX7D select ROM_UNIFIED_SECTIONS imply CMD_FUSE bool - imply ENV_IS_IN_MMC choice prompt "MX7 board select" diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c index ec74b4c820..87bf105f38 100644 --- a/arch/arm/mach-imx/mx7/soc.c +++ b/arch/arm/mach-imx/mx7/soc.c @@ -257,9 +257,9 @@ int arch_misc_init(void) { #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG if (is_mx7d()) - setenv("soc", "imx7d"); + env_set("soc", "imx7d"); else - setenv("soc", "imx7s"); + env_set("soc", "imx7s"); #endif return 0; diff --git a/arch/arm/mach-imx/video.c b/arch/arm/mach-imx/video.c index 55242f0eaa..c670c5dfc9 100644 --- a/arch/arm/mach-imx/video.c +++ b/arch/arm/mach-imx/video.c @@ -10,7 +10,7 @@ int board_video_skip(void) { int i; int ret; - char const *panel = getenv("panel"); + char const *panel = env_get("panel"); if (!panel) { for (i = 0; i < display_count; i++) { diff --git a/arch/arm/mach-integrator/Kconfig b/arch/arm/mach-integrator/Kconfig index 5146e51f9c..d506ee5b39 100644 --- a/arch/arm/mach-integrator/Kconfig +++ b/arch/arm/mach-integrator/Kconfig @@ -11,13 +11,11 @@ config ARCH_INTEGRATOR_AP config ARCH_INTEGRATOR_CP bool "Support Integrator/CP platform" select ARCH_CINTEGRATOR - imply ENV_IS_IN_FLASH endchoice config ARCH_CINTEGRATOR bool - imply ENV_IS_IN_FLASH choice prompt "Integrator core module select" diff --git a/arch/arm/mach-keystone/ddr3.c b/arch/arm/mach-keystone/ddr3.c index 4cad6a2d81..b2f5414a5c 100644 --- a/arch/arm/mach-keystone/ddr3.c +++ b/arch/arm/mach-keystone/ddr3.c @@ -331,7 +331,7 @@ void ddr3_check_ecc_int(u32 base) int ecc_test = 0; u32 value = __raw_readl(base + KS2_DDR3_ECC_INT_STATUS_OFFSET); - env = getenv("ecc_test"); + env = env_get("ecc_test"); if (env) ecc_test = simple_strtol(env, NULL, 0); diff --git a/arch/arm/mach-keystone/keystone.c b/arch/arm/mach-keystone/keystone.c index beb8a767c4..fcabfbd5c3 100644 --- a/arch/arm/mach-keystone/keystone.c +++ b/arch/arm/mach-keystone/keystone.c @@ -46,7 +46,7 @@ int misc_init_r(void) char *env; long ks2_debug = 0; - env = getenv("ks2_debug"); + env = env_get("ks2_debug"); if (env) ks2_debug = simple_strtol(env, NULL, 0); diff --git a/arch/arm/mach-kirkwood/cpu.c b/arch/arm/mach-kirkwood/cpu.c index 4c9d3fde47..db2ff0311c 100644 --- a/arch/arm/mach-kirkwood/cpu.c +++ b/arch/arm/mach-kirkwood/cpu.c @@ -129,7 +129,7 @@ int kw_config_adr_windows(void) static void kw_sysrst_action(void) { int ret; - char *s = getenv("sysrstcmd"); + char *s = env_get("sysrstcmd"); if (!s) { debug("Error.. %s failed, check sysrstcmd\n", @@ -153,7 +153,7 @@ static void kw_sysrst_check(void) /* * no action if sysrstdelay environment variable is not defined */ - s = getenv("sysrstdelay"); + s = env_get("sysrstdelay"); if (s == NULL) return; diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index 1b12b33060..01d700bf2e 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -32,7 +32,6 @@ config ARMADA_38X config ARMADA_XP bool select ARMADA_32BIT - imply ENV_IS_IN_SPI_FLASH # ARMv8 SoCs... config ARMADA_3700 diff --git a/arch/arm/mach-mvebu/include/mach/config.h b/arch/arm/mach-mvebu/include/mach/config.h index 1b35e0802b..2dc9b1dea3 100644 --- a/arch/arm/mach-mvebu/include/mach/config.h +++ b/arch/arm/mach-mvebu/include/mach/config.h @@ -78,10 +78,8 @@ #define CONFIG_MII /* expose smi ove miiphy interface */ #if !defined(CONFIG_ARMADA_375) #define CONFIG_MVNETA /* Enable Marvell Gbe Controller Driver */ -#define CONFIG_PHYLIB #endif #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ -#define CONFIG_PHY_GIGE /* GbE speed/duplex detect */ #define CONFIG_ARP_TIMEOUT 200 #define CONFIG_NET_RETRY_COUNT 50 #endif /* CONFIG_CMD_NET */ diff --git a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c index b0e193b78c..525576a4fc 100644 --- a/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c +++ b/arch/arm/mach-mvebu/serdes/axp/high_speed_env_lib.c @@ -354,16 +354,16 @@ int serdes_phy_config(void) } info = board_serdes_cfg_get(PEX_MODE_GET(satr11)); - DEBUG_INIT_FULL_S("info->line0_7= 0x"); - DEBUG_INIT_FULL_D(info->line0_7, 8); - DEBUG_INIT_FULL_S(" info->line8_15= 0x"); - DEBUG_INIT_FULL_D(info->line8_15, 8); - DEBUG_INIT_FULL_S("\n"); if (info == NULL) { DEBUG_INIT_S("Hight speed PHY Error #1\n"); return MV_ERROR; } + DEBUG_INIT_FULL_S("info->line0_7= 0x"); + DEBUG_INIT_FULL_D(info->line0_7, 8); + DEBUG_INIT_FULL_S(" info->line8_15= 0x"); + DEBUG_INIT_FULL_D(info->line8_15, 8); + DEBUG_INIT_FULL_S("\n"); if (config_module & ETM_MODULE_DETECT) { /* step 0.9 ETM */ DEBUG_INIT_FULL_S("ETM module detect Step 0.9:\n"); diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 013586edd9..72832ad099 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -22,6 +22,7 @@ config OMAP34XX imply SPL_NAND_SUPPORT imply SPL_POWER_SUPPORT imply SPL_SERIAL_SUPPORT + imply SYS_I2C_OMAP24XX imply SYS_THUMB_BUILD imply TWL4030_POWER @@ -40,6 +41,7 @@ config OMAP44XX imply SPL_NAND_SUPPORT imply SPL_POWER_SUPPORT imply SPL_SERIAL_SUPPORT + imply SYS_I2C_OMAP24XX imply SYS_THUMB_BUILD config OMAP54XX @@ -59,6 +61,7 @@ config OMAP54XX imply SPL_NAND_SUPPORT imply SPL_POWER_SUPPORT imply SPL_SERIAL_SUPPORT + imply SYS_I2C_OMAP24XX config TI814X bool "TI814X SoC" @@ -82,6 +85,7 @@ config AM43XX imply SPL_OF_TRANSLATE imply SPL_SEPARATE_BSS imply SPL_SYS_MALLOC_SIMPLE + imply SYS_I2C_OMAP24XX imply SYS_THUMB_BUILD help Support for AM43xx SOC from Texas Instruments. @@ -92,6 +96,7 @@ config AM43XX config AM33XX bool "AM33XX SoC" + imply SYS_I2C_OMAP24XX imply SYS_THUMB_BUILD imply USE_TINY_PRINTF help @@ -165,4 +170,7 @@ source "board/ti/am335x/Kconfig" source "board/compulab/cm_t335/Kconfig" source "board/compulab/cm_t43/Kconfig" +config SPL_LDSCRIPT + default "arch/arm/mach-omap2/u-boot-spl.lds" + endif diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig index d8abba992a..7260d27877 100644 --- a/arch/arm/mach-omap2/am33xx/Kconfig +++ b/arch/arm/mach-omap2/am33xx/Kconfig @@ -81,6 +81,7 @@ config TARGET_AM335X_SHC select DM select DM_SERIAL select DM_GPIO + imply CMD_SPL config TARGET_AM335X_SL50 bool "Support am335x_sl50" diff --git a/arch/arm/mach-omap2/boot-common.c b/arch/arm/mach-omap2/boot-common.c index 700e6c2f79..26245aa169 100644 --- a/arch/arm/mach-omap2/boot-common.c +++ b/arch/arm/mach-omap2/boot-common.c @@ -10,6 +10,7 @@ #include <common.h> #include <ahci.h> +#include <environment.h> #include <spl.h> #include <asm/omap_common.h> #include <asm/arch/omap.h> @@ -240,8 +241,8 @@ void arch_preboot_os(void) int fb_set_reboot_flag(void) { printf("Setting reboot to fastboot flag ...\n"); - setenv("dofastboot", "1"); - saveenv(); + env_set("dofastboot", "1"); + env_save(); return 0; } #endif diff --git a/arch/arm/mach-omap2/omap3/clock.c b/arch/arm/mach-omap2/omap3/clock.c index 006969e780..3daae61e1d 100644 --- a/arch/arm/mach-omap2/omap3/clock.c +++ b/arch/arm/mach-omap2/omap3/clock.c @@ -772,7 +772,7 @@ void per_clocks_enable(void) setbits_le32(&prcm_base->iclken_per, 0x00020000); #endif -#ifdef CONFIG_SYS_I2C_OMAP34XX +#ifdef CONFIG_SYS_I2C_OMAP24XX /* Turn on all 3 I2C clocks */ setbits_le32(&prcm_base->fclken1_core, 0x00038000); setbits_le32(&prcm_base->iclken1_core, 0x00038000); /* I2C1,2,3 = on */ diff --git a/arch/arm/mach-omap2/omap3/emif4.c b/arch/arm/mach-omap2/omap3/emif4.c index d540cf08d2..8197e7b032 100644 --- a/arch/arm/mach-omap2/omap3/emif4.c +++ b/arch/arm/mach-omap2/omap3/emif4.c @@ -76,7 +76,7 @@ static void do_emif4_init(void) regval |= (1<<10); writel(regval, &emif4_base->sdram_iodft_tlgc); /*Wait till that bit clears*/ - while ((readl(&emif4_base->sdram_iodft_tlgc) & (1<<10)) == 0x1); + while ((readl(&emif4_base->sdram_iodft_tlgc) & (1<<10)) != 0x0); /*Re-verify the DDR PHY status*/ while ((readl(&emif4_base->sdram_sts) & (1<<2)) == 0x0); diff --git a/arch/arm/mach-omap2/omap5/abb.c b/arch/arm/mach-omap2/omap5/abb.c index 3bf88979e5..1882c49e7d 100644 --- a/arch/arm/mach-omap2/omap5/abb.c +++ b/arch/arm/mach-omap2/omap5/abb.c @@ -28,8 +28,8 @@ s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb) { u32 vset; - u32 fuse_enable_mask = OMAP5_ABB_FUSE_ENABLE_MASK; - u32 fuse_vset_mask = OMAP5_ABB_FUSE_VSET_MASK; + u32 fuse_enable_mask = OMAP5_PROD_ABB_FUSE_ENABLE_MASK; + u32 fuse_vset_mask = OMAP5_PROD_ABB_FUSE_VSET_MASK; if (!is_omap54xx()) { /* DRA7 */ diff --git a/arch/arm/mach-omap2/omap5/hw_data.c b/arch/arm/mach-omap2/omap5/hw_data.c index a8a6b8a869..4ad6b530d2 100644 --- a/arch/arm/mach-omap2/omap5/hw_data.c +++ b/arch/arm/mach-omap2/omap5/hw_data.c @@ -329,6 +329,15 @@ struct vcores_data omap5430_volts_es2 = { .mm.addr = SMPS_REG_ADDR_45_IVA, .mm.pmic = &palmas, .mm.abb_tx_done_mask = OMAP_ABB_MM_TXDONE_MASK, + + .mpu.efuse.reg[OPP_NOM] = OMAP5_ES2_PROD_MPU_OPNO_VMIN, + .mpu.efuse.reg_bits = OMAP5_ES2_PROD_REGBITS, + + .core.efuse.reg[OPP_NOM] = OMAP5_ES2_PROD_CORE_OPNO_VMIN, + .core.efuse.reg_bits = OMAP5_ES2_PROD_REGBITS, + + .mm.efuse.reg[OPP_NOM] = OMAP5_ES2_PROD_MM_OPNO_VMIN, + .mm.efuse.reg_bits = OMAP5_ES2_PROD_REGBITS, }; /* diff --git a/arch/arm/mach-omap2/sec-common.c b/arch/arm/mach-omap2/sec-common.c index 030b36f332..2d54a3165e 100644 --- a/arch/arm/mach-omap2/sec-common.c +++ b/arch/arm/mach-omap2/sec-common.c @@ -112,8 +112,8 @@ int secure_boot_verify_image(void **image, size_t *size) /* Perform cache writeback on input buffer */ flush_dcache_range( - (u32)*image, - (u32)*image + roundup(*size, ARCH_DMA_MINALIGN)); + rounddown((u32)*image, ARCH_DMA_MINALIGN), + roundup((u32)*image + *size, ARCH_DMA_MINALIGN)); cert_addr = (uint32_t)*image; sig_addr = find_sig_start((char *)*image, *size); @@ -151,8 +151,8 @@ int secure_boot_verify_image(void **image, size_t *size) /* Perform cache writeback on output buffer */ flush_dcache_range( - (u32)*image, - (u32)*image + roundup(*size, ARCH_DMA_MINALIGN)); + rounddown((u32)*image, ARCH_DMA_MINALIGN), + roundup((u32)*image + *size, ARCH_DMA_MINALIGN)); auth_exit: if (result != 0) { diff --git a/arch/arm/mach-omap2/sysinfo-common.c b/arch/arm/mach-omap2/sysinfo-common.c index 1dc7051ab3..4dab12a8d7 100644 --- a/arch/arm/mach-omap2/sysinfo-common.c +++ b/arch/arm/mach-omap2/sysinfo-common.c @@ -16,6 +16,15 @@ */ u32 get_device_type(void) { +#if defined(CONFIG_OMAP34XX) + /* + * On OMAP3 systems we call this early enough that we must just + * use the direct offset for safety. + */ + return (readl(OMAP34XX_CTRL_BASE + 0x2f0) & DEVICE_TYPE_MASK) >> + DEVICE_TYPE_SHIFT; +#else return (readl((*ctrl)->control_status) & DEVICE_TYPE_MASK) >> DEVICE_TYPE_SHIFT; +#endif } diff --git a/arch/arm/mach-omap2/utils.c b/arch/arm/mach-omap2/utils.c index 1946641eb9..0b0bf1837c 100644 --- a/arch/arm/mach-omap2/utils.c +++ b/arch/arm/mach-omap2/utils.c @@ -40,7 +40,7 @@ static void omap_set_fastboot_cpu(void) printf("Warning: fastboot.cpu: unknown CPU rev: %u\n", cpu_rev); } - setenv("fastboot.cpu", cpu); + env_set("fastboot.cpu", cpu); } static void omap_set_fastboot_secure(void) @@ -63,18 +63,18 @@ static void omap_set_fastboot_secure(void) printf("Warning: fastboot.secure: unknown CPU sec: %u\n", dev); } - setenv("fastboot.secure", secure); + env_set("fastboot.secure", secure); } static void omap_set_fastboot_board_rev(void) { const char *board_rev; - board_rev = getenv("board_rev"); + board_rev = env_get("board_rev"); if (board_rev == NULL) printf("Warning: fastboot.board_rev: unknown board revision\n"); - setenv("fastboot.board_rev", board_rev); + env_set("fastboot.board_rev", board_rev); } #ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV @@ -118,7 +118,7 @@ static void omap_set_fastboot_userdata_size(void) sprintf(buf, "%u", sz_kb); } - setenv("fastboot.userdata_size", buf); + env_set("fastboot.userdata_size", buf); } #else static inline void omap_set_fastboot_userdata_size(void) @@ -169,11 +169,11 @@ void omap_die_id_serial(void) omap_die_id((unsigned int *)&die_id); - if (!getenv("serial#")) { + if (!env_get("serial#")) { snprintf(serial_string, sizeof(serial_string), "%08x%08x", die_id[0], die_id[3]); - setenv("serial#", serial_string); + env_set("serial#", serial_string); } } @@ -182,7 +182,7 @@ void omap_die_id_get_board_serial(struct tag_serialnr *serialnr) char *serial_string; unsigned long long serial; - serial_string = getenv("serial#"); + serial_string = env_get("serial#"); if (serial_string) { serial = simple_strtoull(serial_string, NULL, 16); @@ -202,7 +202,7 @@ void omap_die_id_usbethaddr(void) omap_die_id((unsigned int *)&die_id); - if (!getenv("usbethaddr")) { + if (!env_get("usbethaddr")) { /* * Create a fake MAC address from the processor ID code. * First byte is 0x02 to signify locally administered. @@ -214,7 +214,7 @@ void omap_die_id_usbethaddr(void) mac[4] = die_id[0] & 0xff; mac[5] = (die_id[0] >> 8) & 0xff; - eth_setenv_enetaddr("usbethaddr", mac); + eth_env_set_enetaddr("usbethaddr", mac); } } diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig index 7644b8dc85..2984a3edda 100644 --- a/arch/arm/mach-orion5x/Kconfig +++ b/arch/arm/mach-orion5x/Kconfig @@ -15,4 +15,7 @@ config SYS_SOC source "board/LaCie/edminiv2/Kconfig" +config SPL_LDSCRIPT + default "$(CPUDIR)/orion5x/u-boot-spl.lds" if ORION5X + endif diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64 index 5db93ac8d6..c79b39ded6 100644 --- a/arch/arm/mach-rmobile/Kconfig.64 +++ b/arch/arm/mach-rmobile/Kconfig.64 @@ -20,11 +20,17 @@ config TARGET_SALVATOR_X help Support for Renesas R-Car Gen3 platform +config TARGET_ULCB + bool "ULCB board" + help + Support for Renesas R-Car Gen3 ULCB platform + endchoice config SYS_SOC default "rmobile" source "board/renesas/salvator-x/Kconfig" +source "board/renesas/ulcb/Kconfig" endif diff --git a/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h b/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h index c197642fe4..39726355e6 100644 --- a/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h +++ b/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h @@ -75,6 +75,8 @@ #define CONFIG_SYS_SH_SDHI3_BASE 0xEE160000 /* PFC */ +#define PFC_PUEN5 0xE6060414 +#define PUEN_SSI_SDATA4 BIT(17) #define PFC_PUEN6 0xE6060418 #define PUEN_USB1_OVC (1 << 2) #define PUEN_USB1_PWEN (1 << 1) diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index bb44c61566..d9b25d5de4 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -67,14 +67,42 @@ config ROCKCHIP_RK3328 config ROCKCHIP_RK3368 bool "Support Rockchip RK3368" select ARM64 + select SUPPORT_SPL + select SUPPORT_TPL + select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL + select TPL_NEEDS_SEPARATE_STACK if TPL + imply SPL_SEPARATE_BSS + imply SPL_SERIAL_SUPPORT + imply TPL_SERIAL_SUPPORT + select ENABLE_ARM_SOC_BOOT0_HOOK + select DEBUG_UART_BOARD_INIT select SYS_NS16550 help - The Rockchip RK3328 is a ARM-based SoC with a octa-core Cortex-A53. - including NEON and GPU, 512KB L2 cache for big cluster and 256 KB - L2 cache for little cluser, PowerVR G6110 based graphics, one video - output processor supporting LVDS、HDMI、eDP, several DDR3 options - and video codec support. Peripherals include Gigabit Ethernet, - USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. + The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised + into a big and little cluster with 4 cores each) Cortex-A53 including + AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache + (for the little cluster), PowerVR G6110 based graphics, one video + output processor supporting LVDS/HDMI/eDP, several DDR3 options and + video codec support. + + On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, + I2S, UARTs, SPI, I2C and PWMs. + +if ROCKCHIP_RK3368 + +config TPL_LDSCRIPT + default "arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds" + +config TPL_TEXT_BASE + default 0xff8c1000 + +config TPL_MAX_SIZE + default 28672 + +config TPL_STACK + default 0xff8cffff + +endif config ROCKCHIP_RK3399 bool "Support Rockchip RK3399" @@ -82,6 +110,8 @@ config ROCKCHIP_RK3399 select SUPPORT_SPL select SPL select SPL_SEPARATE_BSS + select SPL_SERIAL_SUPPORT + select SPL_DRIVERS_MISC_SUPPORT select ENABLE_ARM_SOC_BOOT0_HOOK select DEBUG_UART_BOARD_INIT help @@ -99,10 +129,21 @@ config ROCKCHIP_RV1108 The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7 and a DSP. -config ROCKCHIP_SPL_BACK_TO_BROM +config SPL_ROCKCHIP_BACK_TO_BROM bool "SPL returns to bootrom" default y if ROCKCHIP_RK3036 select ROCKCHIP_BROM_HELPER + depends on SPL + help + Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled, + SPL will return to the boot rom, which will then load the U-Boot + binary to keep going on. + +config TPL_ROCKCHIP_BACK_TO_BROM + bool "TPL returns to bootrom" + default y if ROCKCHIP_RK3368 + select ROCKCHIP_BROM_HELPER + depends on TPL help Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled, SPL will return to the boot rom, which will then load the U-Boot @@ -120,7 +161,7 @@ config ROCKCHIP_BROM_HELPER bool config SPL_MMC_SUPPORT - default y if !ROCKCHIP_SPL_BACK_TO_BROM + default y if !SPL_ROCKCHIP_BACK_TO_BROM source "arch/arm/mach-rockchip/rk3036/Kconfig" source "arch/arm/mach-rockchip/rk3188/Kconfig" diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index cb8d3efe4b..79e9704a2c 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -4,39 +4,50 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o - -ifdef CONFIG_TPL_BUILD -obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-tpl.o -obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += save_boot_param.o -else ifdef CONFIG_SPL_BUILD -obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o -obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o -obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o -obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o -obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o -obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += save_boot_param.o -else +# We don't want the bootrom-helper present in a full U-Boot build, as +# this may have entered from ATF with the stack-pointer pointing to +# inaccessible/protected memory (and the bootrom-helper assumes that +# the stack-pointer is valid before switching to the U-Boot stack). +obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o save_boot_param.o +obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o save_boot_param.o + +obj-tpl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-tpl.o +obj-tpl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-tpl.o + +obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o +obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o +obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o +obj-spl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o +obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o spl-boot-order.o +obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o spl-boot-order.o + +ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TPL_BUILD),) obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board.o obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o -ifdef CONFIG_RAM -obj-y += sdram_common.o -endif endif + +obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o + ifndef CONFIG_ARM64 obj-y += rk_timer.o endif -obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/ +obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/ ifndef CONFIG_TPL_BUILD obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/ endif - obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x/ obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/ obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/ obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/ obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/ obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108/ + +# Clear out SPL objects, in case this is a TPL build +obj-spl-$(CONFIG_TPL_BUILD) = + +# Now add SPL/TPL objects back into the main build +obj-$(CONFIG_SPL_BUILD) += $(obj-spl-y) +obj-$(CONFIG_TPL_BUILD) += $(obj-tpl-y) diff --git a/arch/arm/mach-rockchip/bootrom.c b/arch/arm/mach-rockchip/bootrom.c index da36f92697..8380e4e006 100644 --- a/arch/arm/mach-rockchip/bootrom.c +++ b/arch/arm/mach-rockchip/bootrom.c @@ -9,8 +9,8 @@ void back_to_bootrom(void) { -#if defined(CONFIG_SPL_LIBGENERIC_SUPPORT) && !defined(CONFIG_TPL_BUILD) - printf("Returning to boot ROM..."); +#if CONFIG_IS_ENABLED(LIBCOMMON_SUPPORT) + puts("Returning to boot ROM...\n"); #endif _back_to_bootrom_s(); } diff --git a/arch/arm/mach-rockchip/rk3036-board-spl.c b/arch/arm/mach-rockchip/rk3036-board-spl.c index 7b8d0ee653..9458201bd3 100644 --- a/arch/arm/mach-rockchip/rk3036-board-spl.c +++ b/arch/arm/mach-rockchip/rk3036-board-spl.c @@ -53,9 +53,3 @@ void board_init_r(gd_t *id, ulong dest_addr) while (1) ; } - -void hang(void) -{ - while (1) - ; -} diff --git a/arch/arm/mach-rockchip/rk3036-board.c b/arch/arm/mach-rockchip/rk3036-board.c index 26ea23b014..a3457f3914 100644 --- a/arch/arm/mach-rockchip/rk3036-board.c +++ b/arch/arm/mach-rockchip/rk3036-board.c @@ -34,11 +34,11 @@ static void setup_boot_mode(void) switch (boot_mode) { case BOOT_FASTBOOT: printf("enter fastboot!\n"); - setenv("preboot", "setenv preboot; fastboot usb0"); + env_set("preboot", "setenv preboot; fastboot usb0"); break; case BOOT_UMS: printf("enter UMS!\n"); - setenv("preboot", "setenv preboot; ums mmc 0"); + env_set("preboot", "setenv preboot; ums mmc 0"); break; } } diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c b/arch/arm/mach-rockchip/rk3188-board-spl.c index c3e174db9e..d3866bf029 100644 --- a/arch/arm/mach-rockchip/rk3188-board-spl.c +++ b/arch/arm/mach-rockchip/rk3188-board-spl.c @@ -167,8 +167,7 @@ void board_init_f(ulong dummy) } setup_arm_clock(); - -#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) +#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) back_to_bootrom(); #endif } @@ -229,7 +228,7 @@ void spl_board_init(void) } preloader_console_init(); -#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM +#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) back_to_bootrom(); #endif return; diff --git a/arch/arm/mach-rockchip/rk3188-board.c b/arch/arm/mach-rockchip/rk3188-board.c index 3e76100ad1..622e046dc0 100644 --- a/arch/arm/mach-rockchip/rk3188-board.c +++ b/arch/arm/mach-rockchip/rk3188-board.c @@ -39,7 +39,7 @@ int board_late_init(void) int board_init(void) { -#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) +#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) struct udevice *pinctrl; int ret; diff --git a/arch/arm/mach-rockchip/rk3188/Kconfig b/arch/arm/mach-rockchip/rk3188/Kconfig index d129fcda99..2bb35662d1 100644 --- a/arch/arm/mach-rockchip/rk3188/Kconfig +++ b/arch/arm/mach-rockchip/rk3188/Kconfig @@ -30,9 +30,6 @@ config TPL_LIBCOMMON_SUPPORT config TPL_LIBGENERIC_SUPPORT default y -config TPL_SERIAL_SUPPORT - default y - source "board/radxa/rock/Kconfig" endif diff --git a/arch/arm/mach-rockchip/rk322x-board-spl.c b/arch/arm/mach-rockchip/rk322x-board-spl.c index 15216c74b0..4ddb8ba065 100644 --- a/arch/arm/mach-rockchip/rk322x-board-spl.c +++ b/arch/arm/mach-rockchip/rk322x-board-spl.c @@ -41,6 +41,8 @@ static struct rk322x_grf * const grf = (void *)GRF_BASE; CON_IOMUX_UART2SEL_MASK, CON_IOMUX_UART2SEL_21 << CON_IOMUX_UART2SEL_SHIFT); } + +#define SGRF_DDR_CON0 0x10150000 void board_init_f(ulong dummy) { struct udevice *dev; @@ -71,6 +73,8 @@ void board_init_f(ulong dummy) return; } + /* Disable the ddr secure region setting to make it non-secure */ + rk_clrreg(SGRF_DDR_CON0, 0x4000); #if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) back_to_bootrom(); #endif diff --git a/arch/arm/mach-rockchip/rk322x-board.c b/arch/arm/mach-rockchip/rk322x-board.c index b6543a5108..1e79c19309 100644 --- a/arch/arm/mach-rockchip/rk322x-board.c +++ b/arch/arm/mach-rockchip/rk322x-board.c @@ -30,11 +30,11 @@ static void setup_boot_mode(void) switch (boot_mode) { case BOOT_FASTBOOT: printf("enter fastboot!\n"); - setenv("preboot", "setenv preboot; fastboot usb0"); + env_set("preboot", "setenv preboot; fastboot usb0"); break; case BOOT_UMS: printf("enter UMS!\n"); - setenv("preboot", "setenv preboot; ums mmc 0"); + env_set("preboot", "setenv preboot; ums mmc 0"); break; } } diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c index 5668fd28a0..6b7bf85d8d 100644 --- a/arch/arm/mach-rockchip/rk3288-board-spl.c +++ b/arch/arm/mach-rockchip/rk3288-board-spl.c @@ -249,7 +249,7 @@ void board_init_f(ulong dummy) debug("DRAM init failed: %d\n", ret); return; } -#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) +#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) back_to_bootrom(); #endif } @@ -316,7 +316,7 @@ void spl_board_init(void) } preloader_console_init(); -#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM +#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) back_to_bootrom(); #endif return; diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c index 613967c307..74c6cc14a1 100644 --- a/arch/arm/mach-rockchip/rk3288-board.c +++ b/arch/arm/mach-rockchip/rk3288-board.c @@ -37,11 +37,11 @@ static void setup_boot_mode(void) switch (boot_mode) { case BOOT_FASTBOOT: printf("enter fastboot!\n"); - setenv("preboot", "setenv preboot; fastboot usb0"); + env_set("preboot", "setenv preboot; fastboot usb0"); break; case BOOT_UMS: printf("enter UMS!\n"); - setenv("preboot", "setenv preboot; if mmc dev 0;" + env_set("preboot", "setenv preboot; if mmc dev 0;" "then ums mmc 0; else ums mmc 1;fi"); break; } @@ -78,7 +78,7 @@ int board_late_init(void) return rk_board_late_init(); } -#ifndef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM +#if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) static int veyron_init(void) { struct udevice *dev; @@ -115,7 +115,7 @@ static int veyron_init(void) int board_init(void) { -#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM +#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) struct udevice *pinctrl; int ret; diff --git a/arch/arm/mach-rockchip/rk3368-board-spl.c b/arch/arm/mach-rockchip/rk3368-board-spl.c new file mode 100644 index 0000000000..cabf344486 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3368-board-spl.c @@ -0,0 +1,78 @@ +/* + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <debug_uart.h> +#include <dm.h> +#include <dm/pinctrl.h> +#include <ram.h> +#include <spl.h> +#include <asm/io.h> +#include <asm/arch/cru_rk3368.h> +#include <asm/arch/grf_rk3368.h> +#include <asm/arch/hardware.h> +#include <asm/arch/periph.h> +#include <asm/arch/timer.h> + +DECLARE_GLOBAL_DATA_PTR; + +void board_debug_uart_init(void) +{ +} + +void board_init_f(ulong dummy) +{ + struct udevice *pinctrl; + struct udevice *dev; + int ret; + + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + + /* Set up our preloader console */ + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); + if (ret) { + error("%s: pinctrl init failed: %d\n", __func__, ret); + hang(); + } + + ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART0); + if (ret) { + error("%s: failed to set up console UART\n", __func__); + hang(); + } + + preloader_console_init(); + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + return; + } +} + +u32 spl_boot_mode(const u32 boot_device) +{ + return MMCSD_MODE_RAW; +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_MMC1; +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif diff --git a/arch/arm/mach-rockchip/rk3368-board-tpl.c b/arch/arm/mach-rockchip/rk3368-board-tpl.c new file mode 100644 index 0000000000..b3e6ffa781 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3368-board-tpl.c @@ -0,0 +1,157 @@ +/* + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/clock.h> +#include <debug_uart.h> +#include <dm.h> +#include <ram.h> +#include <spl.h> +#include <asm/io.h> +#include <asm/arch/bootrom.h> +#include <asm/arch/cru_rk3368.h> +#include <asm/arch/grf_rk3368.h> +#include <asm/arch/hardware.h> +#include <asm/arch/timer.h> +#include <syscon.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * The SPL (and also the full U-Boot stage on the RK3368) will run in + * secure mode (i.e. EL3) and an ATF will eventually be booted before + * starting up the operating system... so we can initialize the SGRF + * here and rely on the ATF installing the final (secure) policy + * later. + */ +static inline uintptr_t sgrf_soc_con_addr(unsigned no) +{ + const uintptr_t SGRF_BASE = + (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF); + + return SGRF_BASE + sizeof(u32) * no; +} + +static inline uintptr_t sgrf_busdmac_addr(unsigned no) +{ + const uintptr_t SGRF_BASE = + (uintptr_t)syscon_get_first_range(ROCKCHIP_SYSCON_SGRF); + const uintptr_t SGRF_BUSDMAC_OFFSET = 0x100; + const uintptr_t SGRF_BUSDMAC_BASE = SGRF_BASE + SGRF_BUSDMAC_OFFSET; + + return SGRF_BUSDMAC_BASE + sizeof(u32) * no; +} + +static void sgrf_init(void) +{ + struct rk3368_cru * const cru = + (struct rk3368_cru * const)rockchip_get_cru(); + const u16 SGRF_SOC_CON_SEC = GENMASK(15, 0); + const u16 SGRF_BUSDMAC_CON0_SEC = BIT(2); + const u16 SGRF_BUSDMAC_CON1_SEC = GENMASK(15, 12); + + /* Set all configurable IP to 'non secure'-mode */ + rk_setreg(sgrf_soc_con_addr(5), SGRF_SOC_CON_SEC); + rk_setreg(sgrf_soc_con_addr(6), SGRF_SOC_CON_SEC); + rk_setreg(sgrf_soc_con_addr(7), SGRF_SOC_CON_SEC); + + /* + * From rockchip-uboot/arch/arm/cpu/armv8/rk33xx/cpu.c + * Original comment: "ddr space set no secure mode" + */ + rk_clrreg(sgrf_soc_con_addr(8), SGRF_SOC_CON_SEC); + rk_clrreg(sgrf_soc_con_addr(9), SGRF_SOC_CON_SEC); + rk_clrreg(sgrf_soc_con_addr(10), SGRF_SOC_CON_SEC); + + /* Set 'secure dma' to 'non secure'-mode */ + rk_setreg(sgrf_busdmac_addr(0), SGRF_BUSDMAC_CON0_SEC); + rk_setreg(sgrf_busdmac_addr(1), SGRF_BUSDMAC_CON1_SEC); + + dsb(); /* barrier */ + + rk_setreg(&cru->softrst_con[1], DMA1_SRST_REQ); + rk_setreg(&cru->softrst_con[4], DMA2_SRST_REQ); + + dsb(); /* barrier */ + udelay(10); + + rk_clrreg(&cru->softrst_con[1], DMA1_SRST_REQ); + rk_clrreg(&cru->softrst_con[4], DMA2_SRST_REQ); +} + +void board_debug_uart_init(void) +{ + /* + * N.B.: This is called before the device-model has been + * initialised. For this reason, we can not access + * the GRF address range using the syscon API. + */ + struct rk3368_grf * const grf = + (struct rk3368_grf * const)0xff770000; + + enum { + GPIO2D1_MASK = GENMASK(3, 2), + GPIO2D1_GPIO = 0, + GPIO2D1_UART0_SOUT = (1 << 2), + + GPIO2D0_MASK = GENMASK(1, 0), + GPIO2D0_GPIO = 0, + GPIO2D0_UART0_SIN = (1 << 0), + }; + +#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000) + /* Enable early UART0 on the RK3368 */ + rk_clrsetreg(&grf->gpio2d_iomux, + GPIO2D0_MASK, GPIO2D0_UART0_SIN); + rk_clrsetreg(&grf->gpio2d_iomux, + GPIO2D1_MASK, GPIO2D1_UART0_SOUT); +#endif +} + +void board_init_f(ulong dummy) +{ + struct udevice *dev; + int ret; + +#define EARLY_UART +#ifdef EARLY_UART + /* + * Debug UART can be used from here if required: + * + * debug_uart_init(); + * printch('a'); + * printhex8(0x1234); + * printascii("string"); + */ + debug_uart_init(); + printascii("U-Boot TPL board init\n"); +#endif + + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + + /* Reset security, so we can use DMA in the MMC drivers */ + sgrf_init(); + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + return; + } +} + +void board_return_to_bootrom(void) +{ + back_to_bootrom(); +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_BOOTROM; +} diff --git a/arch/arm/mach-rockchip/rk3368/Kconfig b/arch/arm/mach-rockchip/rk3368/Kconfig index 6d32068920..7c9b722b00 100644 --- a/arch/arm/mach-rockchip/rk3368/Kconfig +++ b/arch/arm/mach-rockchip/rk3368/Kconfig @@ -3,6 +3,26 @@ if ROCKCHIP_RK3368 choice prompt "RK3368 board" +config TARGET_LION_RK3368 + bool "Theobroma Systems RK3368-uQ7 (Lion) module" + help + The RK3368-uQ7 is a micro-Qseven form-factor (40mm x 70mm, + MXM-230 connector) system-on-module designed by Theobroma + Systems for industrial applications. + + It provides the following features: + - 8x Cortex-A53 (in 2 clusters of 4 cores each) + - (on-module) up to 4GB of DDR3 memory + - (on-module) SPI-NOR flash + - (on-module) eMMC + - Gigabit Ethernet (with an on-module KSZ9031 PHY) + - USB + - HDMI + - MIPI-DSI/single-channel LVDS (muxed on the 'LVDS-A' pin-group) + - various 'slow' interfaces (e.g. UART, SPI, I2C, I2S, ...) + - on-module STM32 providing CAN, RTC and fan-control + - (optional on-module) EAL4+-certified security module + config TARGET_SHEEP bool "Sheep board" help @@ -25,8 +45,12 @@ endchoice config SYS_SOC default "rockchip" +source "board/theobroma-systems/lion_rk3368/Kconfig" source "board/rockchip/sheep_rk3368/Kconfig" source "board/geekbuying/geekbox/Kconfig" source "board/rockchip/evb_px5/Kconfig" +config SPL_LDSCRIPT + default "arch/arm/cpu/armv8/u-boot-spl.lds" + endif diff --git a/arch/arm/mach-rockchip/rk3368/Makefile b/arch/arm/mach-rockchip/rk3368/Makefile index 0390716410..46798c2e93 100644 --- a/arch/arm/mach-rockchip/rk3368/Makefile +++ b/arch/arm/mach-rockchip/rk3368/Makefile @@ -5,5 +5,4 @@ # obj-y += clk_rk3368.o obj-y += rk3368.o -obj-y += sdram_rk3368.o obj-y += syscon_rk3368.o diff --git a/arch/arm/mach-rockchip/rk3368/sdram_rk3368.c b/arch/arm/mach-rockchip/rk3368/sdram_rk3368.c deleted file mode 100644 index d0d090087b..0000000000 --- a/arch/arm/mach-rockchip/rk3368/sdram_rk3368.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd. - * - * SPDX-License-Identifier: GPL-2.0 - */ - -#include <common.h> -#include <dm.h> -#include <ram.h> -#include <syscon.h> -#include <asm/arch/clock.h> -#include <asm/arch/grf_rk3368.h> -#include <asm/arch/sdram_common.h> - -DECLARE_GLOBAL_DATA_PTR; -struct dram_info { - struct ram_info info; - struct rk3368_pmu_grf *pmugrf; -}; - -static int rk3368_dmc_probe(struct udevice *dev) -{ - struct dram_info *priv = dev_get_priv(dev); - - priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); - debug("%s: grf=%p\n", __func__, priv->pmugrf); - priv->info.base = CONFIG_SYS_SDRAM_BASE; - priv->info.size = rockchip_sdram_size( - (phys_addr_t)&priv->pmugrf->os_reg[2]); - - return 0; -} - -static int rk3368_dmc_get_info(struct udevice *dev, struct ram_info *info) -{ - struct dram_info *priv = dev_get_priv(dev); - - *info = priv->info; - - return 0; -} - -static struct ram_ops rk3368_dmc_ops = { - .get_info = rk3368_dmc_get_info, -}; - - -static const struct udevice_id rk3368_dmc_ids[] = { - { .compatible = "rockchip,rk3368-dmc" }, - { } -}; - -U_BOOT_DRIVER(dmc_rk3368) = { - .name = "rockchip_rk3368_dmc", - .id = UCLASS_RAM, - .of_match = rk3368_dmc_ids, - .ops = &rk3368_dmc_ops, - .probe = rk3368_dmc_probe, - .priv_auto_alloc_size = sizeof(struct dram_info), -}; diff --git a/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c b/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c index 03e97eb629..99d51f0edc 100644 --- a/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c +++ b/arch/arm/mach-rockchip/rk3368/syscon_rk3368.c @@ -1,6 +1,8 @@ /* * (C) Copyright 2017 Rockchip Electronics Co., Ltd * Author: Andy Yan <andy.yan@rock-chips.com> + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH + * * SPDX-License-Identifier: GPL-2.0+ */ @@ -14,6 +16,10 @@ static const struct udevice_id rk3368_syscon_ids[] = { .data = ROCKCHIP_SYSCON_GRF }, { .compatible = "rockchip,rk3368-pmugrf", .data = ROCKCHIP_SYSCON_PMUGRF }, + { .compatible = "rockchip,rk3368-msch", + .data = ROCKCHIP_SYSCON_MSCH }, + { .compatible = "rockchip,rk3368-sgrf", + .data = ROCKCHIP_SYSCON_SGRF }, { } }; @@ -22,3 +28,41 @@ U_BOOT_DRIVER(syscon_rk3368) = { .id = UCLASS_SYSCON, .of_match = rk3368_syscon_ids, }; + +#if CONFIG_IS_ENABLED(OF_PLATDATA) +static int rk3368_syscon_bind_of_platdata(struct udevice *dev) +{ + dev->driver_data = dev->driver->of_match->data; + debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data); + + return 0; +} + +U_BOOT_DRIVER(rockchip_rk3368_grf) = { + .name = "rockchip_rk3368_grf", + .id = UCLASS_SYSCON, + .of_match = rk3368_syscon_ids, + .bind = rk3368_syscon_bind_of_platdata, +}; + +U_BOOT_DRIVER(rockchip_rk3368_pmugrf) = { + .name = "rockchip_rk3368_pmugrf", + .id = UCLASS_SYSCON, + .of_match = rk3368_syscon_ids + 1, + .bind = rk3368_syscon_bind_of_platdata, +}; + +U_BOOT_DRIVER(rockchip_rk3368_msch) = { + .name = "rockchip_rk3368_msch", + .id = UCLASS_SYSCON, + .of_match = rk3368_syscon_ids + 2, + .bind = rk3368_syscon_bind_of_platdata, +}; + +U_BOOT_DRIVER(rockchip_rk3368_sgrf) = { + .name = "rockchip_rk3368_sgrf", + .id = UCLASS_SYSCON, + .of_match = rk3368_syscon_ids + 3, + .bind = rk3368_syscon_bind_of_platdata, +}; +#endif diff --git a/arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds b/arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds new file mode 100644 index 0000000000..cc59844735 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3368/u-boot-tpl.lds @@ -0,0 +1,13 @@ +/* + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#undef CONFIG_SPL_TEXT_BASE +#define CONFIG_SPL_TEXT_BASE CONFIG_TPL_TEXT_BASE + +#undef CONFIG_SPL_MAX_SIZE +#define CONFIG_SPL_MAX_SIZE CONFIG_TPL_MAX_SIZE + +#include "../../cpu/armv8/u-boot-spl.lds" diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c index e050affac0..a13b717bbd 100644 --- a/arch/arm/mach-rockchip/rk3399-board-spl.c +++ b/arch/arm/mach-rockchip/rk3399-board-spl.c @@ -8,9 +8,6 @@ #include <debug_uart.h> #include <dm.h> #include <fdtdec.h> -#include <led.h> -#include <malloc.h> -#include <mmc.h> #include <ram.h> #include <spl.h> #include <asm/gpio.h> @@ -21,111 +18,10 @@ #include <asm/arch/sdram.h> #include <asm/arch/timer.h> #include <dm/pinctrl.h> -#include <dm/root.h> -#include <dm/test.h> -#include <dm/util.h> #include <power/regulator.h> DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_OF_CONTROL) -static int spl_node_to_boot_device(int node) -{ - struct udevice *parent; - - /* - * This should eventually move into the SPL code, once SPL becomes - * aware of the block-device layer. Until then (and to avoid unneeded - * delays in getting this feature out, it lives at the board-level). - */ - if (!uclass_get_device_by_of_offset(UCLASS_MMC, node, &parent)) { - struct udevice *dev; - struct blk_desc *desc = NULL; - - for (device_find_first_child(parent, &dev); - dev; - device_find_next_child(&dev)) { - if (device_get_uclass_id(dev) == UCLASS_BLK) { - desc = dev_get_uclass_platdata(dev); - break; - } - } - - if (!desc) - return -ENOENT; - - switch (desc->devnum) { - case 0: - return BOOT_DEVICE_MMC1; - case 1: - return BOOT_DEVICE_MMC2; - default: - return -ENOSYS; - } - } - - /* - * SPL doesn't differentiate SPI flashes, so we keep the detection - * brief and inaccurate... hopefully, the common SPL layer can be - * extended with awareness of the BLK layer (and matching OF_CONTROL) - * soon. - */ - if (!uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node, &parent)) - return BOOT_DEVICE_SPI; - - return -1; -} - -void board_boot_order(u32 *spl_boot_list) -{ - const void *blob = gd->fdt_blob; - int chosen_node = fdt_path_offset(blob, "/chosen"); - int idx = 0; - int elem; - int boot_device; - int node; - const char *conf; - - if (chosen_node < 0) { - debug("%s: /chosen not found, using spl_boot_device()\n", - __func__); - spl_boot_list[0] = spl_boot_device(); - return; - } - - for (elem = 0; - (conf = fdt_stringlist_get(blob, chosen_node, - "u-boot,spl-boot-order", elem, NULL)); - elem++) { - /* First check if the list element is an alias */ - const char *alias = fdt_get_alias(blob, conf); - if (alias) - conf = alias; - - /* Try to resolve the config item (or alias) as a path */ - node = fdt_path_offset(blob, conf); - if (node < 0) { - debug("%s: could not find %s in FDT", __func__, conf); - continue; - } - - /* Try to map this back onto SPL boot devices */ - boot_device = spl_node_to_boot_device(node); - if (boot_device < 0) { - debug("%s: could not map node @%x to a boot-device\n", - __func__, node); - continue; - } - - spl_boot_list[idx++] = boot_device; - } - - /* If we had no matches, fall back to spl_boot_device */ - if (idx == 0) - spl_boot_list[0] = spl_boot_device(); -} -#endif - u32 spl_boot_device(void) { return BOOT_DEVICE_MMC1; @@ -263,7 +159,7 @@ void spl_board_init(void) } preloader_console_init(); -#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM +#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) back_to_bootrom(); #endif diff --git a/arch/arm/mach-rockchip/rk_timer.c b/arch/arm/mach-rockchip/rk_timer.c index ae5123d73b..853b986646 100644 --- a/arch/arm/mach-rockchip/rk_timer.c +++ b/arch/arm/mach-rockchip/rk_timer.c @@ -4,9 +4,9 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include <common.h> #include <asm/arch/timer.h> #include <asm/io.h> -#include <common.h> #include <linux/types.h> struct rk_timer * const timer_ptr = (void *)CONFIG_SYS_TIMER_BASE; diff --git a/arch/arm/mach-rockchip/save_boot_param.S b/arch/arm/mach-rockchip/save_boot_param.S index 5e6c8dba13..50fce207a5 100644 --- a/arch/arm/mach-rockchip/save_boot_param.S +++ b/arch/arm/mach-rockchip/save_boot_param.S @@ -1,11 +1,47 @@ /* * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH * * SPDX-License-Identifier: GPL-2.0+ */ #include <linux/linkage.h> +#if defined(CONFIG_ARM64) +.globl SAVE_SP_ADDR +SAVE_SP_ADDR: + .quad 0 + +ENTRY(save_boot_params) + sub sp, sp, #0x60 + stp x29, x30, [sp, #0x50] + stp x27, x28, [sp, #0x40] + stp x25, x26, [sp, #0x30] + stp x23, x24, [sp, #0x20] + stp x21, x22, [sp, #0x10] + stp x19, x20, [sp, #0] + ldr x8, =SAVE_SP_ADDR + mov x9, sp + str x9, [x8] + b save_boot_params_ret /* back to my caller */ +ENDPROC(save_boot_params) + +.globl _back_to_bootrom_s +ENTRY(_back_to_bootrom_s) + ldr x0, =SAVE_SP_ADDR + ldr x0, [x0] + mov sp, x0 + ldp x29, x30, [sp, #0x50] + ldp x27, x28, [sp, #0x40] + ldp x25, x26, [sp, #0x30] + ldp x23, x24, [sp, #0x20] + ldp x21, x22, [sp, #0x10] + ldp x19, x20, [sp] + add sp, sp, #0x60 + mov x0, xzr + ret +ENDPROC(_back_to_bootrom_s) +#else .globl SAVE_SP_ADDR SAVE_SP_ADDR: .word 0 @@ -30,3 +66,4 @@ ENTRY(_back_to_bootrom_s) mov r0, #0 pop {r1-r12, pc} ENDPROC(_back_to_bootrom_s) +#endif diff --git a/arch/arm/mach-rockchip/spl-boot-order.c b/arch/arm/mach-rockchip/spl-boot-order.c new file mode 100644 index 0000000000..4f78c72720 --- /dev/null +++ b/arch/arm/mach-rockchip/spl-boot-order.c @@ -0,0 +1,108 @@ +/* + * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <mmc.h> +#include <spl.h> + +#if CONFIG_IS_ENABLED(OF_CONTROL) +static int spl_node_to_boot_device(int node) +{ + struct udevice *parent; + + /* + * This should eventually move into the SPL code, once SPL becomes + * aware of the block-device layer. Until then (and to avoid unneeded + * delays in getting this feature out, it lives at the board-level). + */ + if (!uclass_get_device_by_of_offset(UCLASS_MMC, node, &parent)) { + struct udevice *dev; + struct blk_desc *desc = NULL; + + for (device_find_first_child(parent, &dev); + dev; + device_find_next_child(&dev)) { + if (device_get_uclass_id(dev) == UCLASS_BLK) { + desc = dev_get_uclass_platdata(dev); + break; + } + } + + if (!desc) + return -ENOENT; + + switch (desc->devnum) { + case 0: + return BOOT_DEVICE_MMC1; + case 1: + return BOOT_DEVICE_MMC2; + default: + return -ENOSYS; + } + } + + /* + * SPL doesn't differentiate SPI flashes, so we keep the detection + * brief and inaccurate... hopefully, the common SPL layer can be + * extended with awareness of the BLK layer (and matching OF_CONTROL) + * soon. + */ + if (!uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node, &parent)) + return BOOT_DEVICE_SPI; + + return -1; +} + +void board_boot_order(u32 *spl_boot_list) +{ + const void *blob = gd->fdt_blob; + int chosen_node = fdt_path_offset(blob, "/chosen"); + int idx = 0; + int elem; + int boot_device; + int node; + const char *conf; + + if (chosen_node < 0) { + debug("%s: /chosen not found, using spl_boot_device()\n", + __func__); + spl_boot_list[0] = spl_boot_device(); + return; + } + + for (elem = 0; + (conf = fdt_stringlist_get(blob, chosen_node, + "u-boot,spl-boot-order", elem, NULL)); + elem++) { + /* First check if the list element is an alias */ + const char *alias = fdt_get_alias(blob, conf); + if (alias) + conf = alias; + + /* Try to resolve the config item (or alias) as a path */ + node = fdt_path_offset(blob, conf); + if (node < 0) { + debug("%s: could not find %s in FDT", __func__, conf); + continue; + } + + /* Try to map this back onto SPL boot devices */ + boot_device = spl_node_to_boot_device(node); + if (boot_device < 0) { + debug("%s: could not map node @%x to a boot-device\n", + __func__, node); + continue; + } + + spl_boot_list[idx++] = boot_device; + } + + /* If we had no matches, fall back to spl_boot_device */ + if (idx == 0) + spl_boot_list[0] = spl_boot_device(); +} +#endif diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 41b779c5ca..286bfef8ca 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -9,7 +9,6 @@ obj-y += board.o obj-y += clock_manager.o -obj-y += fpga_manager.o obj-y += misc.o obj-y += reset_manager.o obj-y += timer.o @@ -21,6 +20,7 @@ obj-y += reset_manager_gen5.o obj-y += scan_manager.o obj-y += system_manager_gen5.o obj-y += wrap_pll_config.o +obj-y += fpga_manager.o endif ifdef CONFIG_TARGET_SOCFPGA_ARRIA10 diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager.h b/arch/arm/mach-socfpga/include/mach/fpga_manager.h index a077e2284e..a21c71665c 100644 --- a/arch/arm/mach-socfpga/include/mach/fpga_manager.h +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2012 Altera Corporation <www.altera.com> + * Copyright (C) 2012-2017 Altera Corporation <www.altera.com> * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -10,58 +10,11 @@ #include <altera.h> -struct socfpga_fpga_manager { - /* FPGA Manager Module */ - u32 stat; /* 0x00 */ - u32 ctrl; - u32 dclkcnt; - u32 dclkstat; - u32 gpo; /* 0x10 */ - u32 gpi; - u32 misci; /* 0x18 */ - u32 _pad_0x1c_0x82c[517]; - - /* Configuration Monitor (MON) Registers */ - u32 gpio_inten; /* 0x830 */ - u32 gpio_intmask; - u32 gpio_inttype_level; - u32 gpio_int_polarity; - u32 gpio_intstatus; /* 0x840 */ - u32 gpio_raw_intstatus; - u32 _pad_0x848; - u32 gpio_porta_eoi; - u32 gpio_ext_porta; /* 0x850 */ - u32 _pad_0x854_0x85c[3]; - u32 gpio_1s_sync; /* 0x860 */ - u32 _pad_0x864_0x868[2]; - u32 gpio_ver_id_code; - u32 gpio_config_reg2; /* 0x870 */ - u32 gpio_config_reg1; -}; - -#define FPGAMGRREGS_STAT_MODE_MASK 0x7 -#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8 -#define FPGAMGRREGS_STAT_MSEL_LSB 3 - -#define FPGAMGRREGS_CTRL_CFGWDTH_MASK 0x200 -#define FPGAMGRREGS_CTRL_AXICFGEN_MASK 0x100 -#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK 0x4 -#define FPGAMGRREGS_CTRL_NCE_MASK 0x2 -#define FPGAMGRREGS_CTRL_EN_MASK 0x1 -#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6 - -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK 0x8 -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK 0x4 -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK 0x2 -#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK 0x1 - -/* FPGA Mode */ -#define FPGAMGRREGS_MODE_FPGAOFF 0x0 -#define FPGAMGRREGS_MODE_RESETPHASE 0x1 -#define FPGAMGRREGS_MODE_CFGPHASE 0x2 -#define FPGAMGRREGS_MODE_INITPHASE 0x3 -#define FPGAMGRREGS_MODE_USERMODE 0x4 -#define FPGAMGRREGS_MODE_UNKNOWN 0x5 +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +#include <asm/arch/fpga_manager_gen5.h> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#include <asm/arch/fpga_manager_arria10.h> +#endif /* FPGA CD Ratio Value */ #define CDRATIO_x1 0x0 @@ -69,9 +22,14 @@ struct socfpga_fpga_manager { #define CDRATIO_x4 0x2 #define CDRATIO_x8 0x3 -/* SoCFPGA support functions */ -int fpgamgr_test_fpga_ready(void); -int fpgamgr_poll_fpga_ready(void); +#ifndef __ASSEMBLY__ + +/* Common prototypes */ int fpgamgr_get_mode(void); +int fpgamgr_poll_fpga_ready(void); +void fpgamgr_program_write(const void *rbf_data, size_t rbf_size); +int fpgamgr_test_fpga_ready(void); +int fpgamgr_dclkcnt_set(unsigned long cnt); +#endif /* __ASSEMBLY__ */ #endif /* _FPGA_MANAGER_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h new file mode 100644 index 0000000000..9cbf696830 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h @@ -0,0 +1,100 @@ +/* + * Copyright (C) 2017 Intel Corporation <www.intel.com> + * All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _FPGA_MANAGER_ARRIA10_H_ +#define _FPGA_MANAGER_ARRIA10_H_ + +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK BIT(0) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK BIT(1) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK BIT(2) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK BIT(3) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK BIT(4) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_OE_SET_MSK BIT(5) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK BIT(6) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK BIT(7) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_SET_MSK BIT(8) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_READY_SET_MSK BIT(9) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_SET_MSK BIT(10) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_SET_MSK BIT(11) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK BIT(12) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_SET_MSK BIT(13) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK BIT(16) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK BIT(17) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK BIT(18) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD (\ + ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK |\ + ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK |\ + ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOEMPTY_SET_MSK BIT(24) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOFULL_SET_MSK BIT(25) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_JTAGM_SET_MSK BIT(28) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EMR_SET_MSK BIT(29) +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB 16 + +#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK BIT(0) +#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK BIT(1) +#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK BIT(2) +#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK BIT(8) +#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK BIT(16) +#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK BIT(24) + +#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK BIT(0) +#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK BIT(16) +#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK BIT(24) + +#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK BIT(0) +#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK BIT(8) +#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK 0x00030000 +#define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK BIT(24) +#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB 16 + +#ifndef __ASSEMBLY__ + +struct socfpga_fpga_manager { + u32 _pad_0x0_0x7[2]; + u32 dclkcnt; + u32 dclkstat; + u32 gpo; + u32 gpi; + u32 misci; + u32 _pad_0x1c_0x2f[5]; + u32 emr_data0; + u32 emr_data1; + u32 emr_data2; + u32 emr_data3; + u32 emr_data4; + u32 emr_data5; + u32 emr_valid; + u32 emr_en; + u32 jtag_config; + u32 jtag_status; + u32 jtag_kick; + u32 _pad_0x5c_0x5f; + u32 jtag_data_w; + u32 jtag_data_r; + u32 _pad_0x68_0x6f[2]; + u32 imgcfg_ctrl_00; + u32 imgcfg_ctrl_01; + u32 imgcfg_ctrl_02; + u32 _pad_0x7c_0x7f; + u32 imgcfg_stat; + u32 intr_masked_status; + u32 intr_mask; + u32 intr_polarity; + u32 dma_config; + u32 imgcfg_fifo_status; +}; + +/* Functions */ +int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size); +int fpgamgr_program_finish(void); +int is_fpgamgr_user_mode(void); +int fpgamgr_wait_early_user_mode(void); + +#endif /* __ASSEMBLY__ */ + +#endif /* _FPGA_MANAGER_ARRIA10_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/fpga_manager_gen5.h new file mode 100644 index 0000000000..2de7a117f9 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_gen5.h @@ -0,0 +1,68 @@ +/* + * Copyright (C) 2012-2017 Altera Corporation <www.altera.com> + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef _FPGA_MANAGER_GEN5_H_ +#define _FPGA_MANAGER_GEN5_H_ + +#define FPGAMGRREGS_STAT_MODE_MASK 0x7 +#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8 +#define FPGAMGRREGS_STAT_MSEL_LSB 3 + +#define FPGAMGRREGS_CTRL_CFGWDTH_MASK BIT(9) +#define FPGAMGRREGS_CTRL_AXICFGEN_MASK BIT(8) +#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK BIT(2) +#define FPGAMGRREGS_CTRL_NCE_MASK BIT(1) +#define FPGAMGRREGS_CTRL_EN_MASK BIT(0) +#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6 + +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK BIT(3) +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK BIT(2) +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK BIT(1) +#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK BIT(0) + +/* FPGA Mode */ +#define FPGAMGRREGS_MODE_FPGAOFF 0x0 +#define FPGAMGRREGS_MODE_RESETPHASE 0x1 +#define FPGAMGRREGS_MODE_CFGPHASE 0x2 +#define FPGAMGRREGS_MODE_INITPHASE 0x3 +#define FPGAMGRREGS_MODE_USERMODE 0x4 +#define FPGAMGRREGS_MODE_UNKNOWN 0x5 + +#ifndef __ASSEMBLY__ + +struct socfpga_fpga_manager { + /* FPGA Manager Module */ + u32 stat; /* 0x00 */ + u32 ctrl; + u32 dclkcnt; + u32 dclkstat; + u32 gpo; /* 0x10 */ + u32 gpi; + u32 misci; /* 0x18 */ + u32 _pad_0x1c_0x82c[517]; + + /* Configuration Monitor (MON) Registers */ + u32 gpio_inten; /* 0x830 */ + u32 gpio_intmask; + u32 gpio_inttype_level; + u32 gpio_int_polarity; + u32 gpio_intstatus; /* 0x840 */ + u32 gpio_raw_intstatus; + u32 _pad_0x848; + u32 gpio_porta_eoi; + u32 gpio_ext_porta; /* 0x850 */ + u32 _pad_0x854_0x85c[3]; + u32 gpio_1s_sync; /* 0x860 */ + u32 _pad_0x864_0x868[2]; + u32 gpio_ver_id_code; + u32 gpio_config_reg2; /* 0x870 */ + u32 gpio_config_reg1; +}; + +#endif /* __ASSEMBLY__ */ + +#endif /* _FPGA_MANAGER_GEN5_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h index 7922db815c..b6d7f4f6f9 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h @@ -17,7 +17,7 @@ int socfpga_reset_deassert_bridges_handoff(void); void socfpga_reset_assert_fpga_connected_peripherals(void); void socfpga_reset_deassert_osc1wd0(void); void socfpga_reset_uart(int assert); -int socfpga_bridges_reset(int enable); +int socfpga_bridges_reset(void); struct socfpga_reset_manager { u32 stat; diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 49b26b3570..2f1da740fb 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -219,9 +219,9 @@ int arch_misc_init(void) { const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7; const int fpga_id = socfpga_fpga_id(0); - setenv("bootmode", bsel_str[bsel].mode); + env_set("bootmode", bsel_str[bsel].mode); if (fpga_id >= 0) - setenv("fpgatype", socfpga_fpga_model[fpga_id].var); + env_set("fpgatype", socfpga_fpga_model[fpga_id].var); return socfpga_eth_reset(); } #endif diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c b/arch/arm/mach-socfpga/reset_manager_arria10.c index d8c858c833..66f1ec21f1 100644 --- a/arch/arm/mach-socfpga/reset_manager_arria10.c +++ b/arch/arm/mach-socfpga/reset_manager_arria10.c @@ -318,13 +318,13 @@ void socfpga_per_reset_all(void) } #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET) -int socfpga_bridges_reset(int enable) +int socfpga_bridges_reset(void) { /* For SoCFPGA-VT, this is NOP. */ return 0; } #else -int socfpga_bridges_reset(int enable) +int socfpga_bridges_reset(void) { int ret; diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig index 8f4371429f..f70f5ec965 100644 --- a/arch/arm/mach-stm32/Kconfig +++ b/arch/arm/mach-stm32/Kconfig @@ -3,9 +3,6 @@ if STM32 config STM32F4 bool "stm32f4 family" -config STM32F1 - bool "stm32f1 family" - config STM32F7 bool "stm32f7 family" select SUPPORT_SPL @@ -29,7 +26,6 @@ config STM32F7 select SPL_XIP_SUPPORT source "arch/arm/mach-stm32/stm32f4/Kconfig" -source "arch/arm/mach-stm32/stm32f1/Kconfig" source "arch/arm/mach-stm32/stm32f7/Kconfig" endif diff --git a/arch/arm/mach-stm32/Makefile b/arch/arm/mach-stm32/Makefile index ffc537f35b..6b7694471f 100644 --- a/arch/arm/mach-stm32/Makefile +++ b/arch/arm/mach-stm32/Makefile @@ -5,6 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_STM32F1) += stm32f1/ obj-$(CONFIG_STM32F4) += stm32f4/ obj-$(CONFIG_STM32F7) += stm32f7/ diff --git a/arch/arm/mach-stm32/stm32f1/Kconfig b/arch/arm/mach-stm32/stm32f1/Kconfig deleted file mode 100644 index f627fd2541..0000000000 --- a/arch/arm/mach-stm32/stm32f1/Kconfig +++ /dev/null @@ -1,3 +0,0 @@ -if STM32F1 - -endif diff --git a/arch/arm/mach-stm32/stm32f1/Makefile b/arch/arm/mach-stm32/stm32f1/Makefile deleted file mode 100644 index e2081dbf9e..0000000000 --- a/arch/arm/mach-stm32/stm32f1/Makefile +++ /dev/null @@ -1,14 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2015 -# Kamil Lulko, <kamil.lulko@gmail.com> -# -# Copyright 2015 ATS Advanced Telematics Systems GmbH -# Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com> -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += soc.o clock.o timer.o flash.o diff --git a/arch/arm/mach-stm32/stm32f1/clock.c b/arch/arm/mach-stm32/stm32f1/clock.c deleted file mode 100644 index 28208485d4..0000000000 --- a/arch/arm/mach-stm32/stm32f1/clock.c +++ /dev/null @@ -1,196 +0,0 @@ -/* - * (C) Copyright 2015 - * Kamil Lulko, <kamil.lulko@gmail.com> - * - * Copyright 2015 ATS Advanced Telematics Systems GmbH - * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com> - * - * (C) Copyright 2014 - * STMicroelectronics - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/stm32.h> - -#define RCC_CR_HSION (1 << 0) -#define RCC_CR_HSEON (1 << 16) -#define RCC_CR_HSERDY (1 << 17) -#define RCC_CR_HSEBYP (1 << 18) -#define RCC_CR_CSSON (1 << 19) -#define RCC_CR_PLLON (1 << 24) -#define RCC_CR_PLLRDY (1 << 25) - -#define RCC_CFGR_PLLMUL_MASK 0x3C0000 -#define RCC_CFGR_PLLMUL_SHIFT 18 -#define RCC_CFGR_PLLSRC_HSE (1 << 16) - -#define RCC_CFGR_AHB_PSC_MASK 0xF0 -#define RCC_CFGR_APB1_PSC_MASK 0x700 -#define RCC_CFGR_APB2_PSC_MASK 0x3800 -#define RCC_CFGR_SW0 (1 << 0) -#define RCC_CFGR_SW1 (1 << 1) -#define RCC_CFGR_SW_MASK 0x3 -#define RCC_CFGR_SW_HSI 0 -#define RCC_CFGR_SW_HSE RCC_CFGR_SW0 -#define RCC_CFGR_SW_PLL RCC_CFGR_SW1 -#define RCC_CFGR_SWS0 (1 << 2) -#define RCC_CFGR_SWS1 (1 << 3) -#define RCC_CFGR_SWS_MASK 0xC -#define RCC_CFGR_SWS_HSI 0 -#define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0 -#define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1 -#define RCC_CFGR_HPRE_SHIFT 4 -#define RCC_CFGR_PPRE1_SHIFT 8 -#define RCC_CFGR_PPRE2_SHIFT 11 - -#define RCC_APB1ENR_PWREN (1 << 28) - -#define PWR_CR_VOS0 (1 << 14) -#define PWR_CR_VOS1 (1 << 15) -#define PWR_CR_VOS_MASK 0xC000 -#define PWR_CR_VOS_SCALE_MODE_1 (PWR_CR_VOS0 | PWR_CR_VOS1) -#define PWR_CR_VOS_SCALE_MODE_2 (PWR_CR_VOS1) -#define PWR_CR_VOS_SCALE_MODE_3 (PWR_CR_VOS0) - -#define FLASH_ACR_WS(n) n -#define FLASH_ACR_PRFTEN (1 << 8) -#define FLASH_ACR_ICEN (1 << 9) -#define FLASH_ACR_DCEN (1 << 10) - -struct psc { - u8 ahb_psc; - u8 apb1_psc; - u8 apb2_psc; -}; - -#define AHB_PSC_1 0 -#define AHB_PSC_2 0x8 -#define AHB_PSC_4 0x9 -#define AHB_PSC_8 0xA -#define AHB_PSC_16 0xB -#define AHB_PSC_64 0xC -#define AHB_PSC_128 0xD -#define AHB_PSC_256 0xE -#define AHB_PSC_512 0xF - -#define APB_PSC_1 0 -#define APB_PSC_2 0x4 -#define APB_PSC_4 0x5 -#define APB_PSC_8 0x6 -#define APB_PSC_16 0x7 - -#if !defined(CONFIG_STM32_HSE_HZ) -#error "CONFIG_STM32_HSE_HZ not defined!" -#else -#if (CONFIG_STM32_HSE_HZ == 8000000) -#define RCC_CFGR_PLLMUL_CFG 0x7 -struct psc psc_hse = { - .ahb_psc = AHB_PSC_1, - .apb1_psc = APB_PSC_2, - .apb2_psc = APB_PSC_1 -}; -#else -#error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists" -#endif -#endif - -int configure_clocks(void) -{ - /* Reset RCC configuration */ - setbits_le32(&STM32_RCC->cr, RCC_CR_HSION); - writel(0, &STM32_RCC->cfgr); /* Reset CFGR */ - clrbits_le32(&STM32_RCC->cr, (RCC_CR_HSEON | RCC_CR_CSSON - | RCC_CR_PLLON)); - clrbits_le32(&STM32_RCC->cr, RCC_CR_HSEBYP); - writel(0, &STM32_RCC->cir); /* Disable all interrupts */ - - /* Configure for HSE+PLL operation */ - setbits_le32(&STM32_RCC->cr, RCC_CR_HSEON); - while (!(readl(&STM32_RCC->cr) & RCC_CR_HSERDY)) - ; - - /* Enable high performance mode, System frequency up to 168 MHz */ - setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_PWREN); - writel(PWR_CR_VOS_SCALE_MODE_1, &STM32_PWR->cr); - - setbits_le32(&STM32_RCC->cfgr, - RCC_CFGR_PLLMUL_CFG << RCC_CFGR_PLLMUL_SHIFT); - setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_PLLSRC_HSE); - setbits_le32(&STM32_RCC->cfgr, (( - psc_hse.ahb_psc << RCC_CFGR_HPRE_SHIFT) - | (psc_hse.apb1_psc << RCC_CFGR_PPRE1_SHIFT) - | (psc_hse.apb2_psc << RCC_CFGR_PPRE2_SHIFT))); - - setbits_le32(&STM32_RCC->cr, RCC_CR_PLLON); - - while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY)) - ; - - /* 5 wait states, Prefetch enabled, D-Cache enabled, I-Cache enabled */ - writel(FLASH_ACR_WS(5) | FLASH_ACR_PRFTEN | FLASH_ACR_ICEN - | FLASH_ACR_DCEN, &STM32_FLASH->acr); - - clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1)); - setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL); - - while ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) != - RCC_CFGR_SWS_PLL) - ; - - return 0; -} - -unsigned long clock_get(enum clock clck) -{ - u32 sysclk = 0; - u32 shift = 0; - /* PLL table lookups for clock computation */ - u8 pll_mul_table[16] = { - 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16 - }; - /* Prescaler table lookups for clock computation */ - u8 ahb_psc_table[16] = { - 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9 - }; - u8 apb_psc_table[8] = { - 0, 0, 0, 0, 1, 2, 3, 4 - }; - - if ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) == - RCC_CFGR_SWS_PLL) { - u16 pll; - pll = ((readl(&STM32_RCC->cfgr) & RCC_CFGR_PLLMUL_MASK) - >> RCC_CFGR_PLLMUL_SHIFT); - sysclk = CONFIG_STM32_HSE_HZ * pll_mul_table[pll]; - } - - switch (clck) { - case CLOCK_CORE: - return sysclk; - break; - case CLOCK_AHB: - shift = ahb_psc_table[( - (readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK) - >> RCC_CFGR_HPRE_SHIFT)]; - return sysclk >>= shift; - break; - case CLOCK_APB1: - shift = apb_psc_table[( - (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB1_PSC_MASK) - >> RCC_CFGR_PPRE1_SHIFT)]; - return sysclk >>= shift; - break; - case CLOCK_APB2: - shift = apb_psc_table[( - (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB2_PSC_MASK) - >> RCC_CFGR_PPRE2_SHIFT)]; - return sysclk >>= shift; - break; - default: - return 0; - break; - } -} diff --git a/arch/arm/mach-stm32/stm32f1/flash.c b/arch/arm/mach-stm32/stm32f1/flash.c deleted file mode 100644 index 7d41f63733..0000000000 --- a/arch/arm/mach-stm32/stm32f1/flash.c +++ /dev/null @@ -1,180 +0,0 @@ -/* - * (C) Copyright 2015 - * Kamil Lulko, <kamil.lulko@gmail.com> - * - * Copyright 2015 ATS Advanced Telematics Systems GmbH - * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/stm32.h> - -#define STM32_FLASH_KEY1 0x45670123 -#define STM32_FLASH_KEY2 0xcdef89ab - -#define STM32_NUM_BANKS 2 -#define STM32_MAX_BANK 0x200 - -flash_info_t flash_info[STM32_NUM_BANKS]; -static struct stm32_flash_bank_regs *flash_bank[STM32_NUM_BANKS]; - -static void stm32f1_flash_lock(u8 bank, u8 lock) -{ - if (lock) { - setbits_le32(&flash_bank[bank]->cr, STM32_FLASH_CR_LOCK); - } else { - writel(STM32_FLASH_KEY1, &flash_bank[bank]->keyr); - writel(STM32_FLASH_KEY2, &flash_bank[bank]->keyr); - } -} - -/* Only XL devices are supported (2 KiB sector size) */ -unsigned long flash_init(void) -{ - u8 i, banks; - u16 j, size; - - /* Set up accessors for XL devices with wonky register layout */ - flash_bank[0] = (struct stm32_flash_bank_regs *)&STM32_FLASH->keyr; - flash_bank[1] = (struct stm32_flash_bank_regs *)&STM32_FLASH->keyr2; - - /* - * Get total flash size (in KiB) and configure number of banks - * present and sector count per bank. - */ - size = readw(&STM32_DES->flash_size); - if (size <= STM32_MAX_BANK) { - banks = 1; - flash_info[0].sector_count = size >> 1; - } else if (size > STM32_MAX_BANK) { - banks = 2; - flash_info[0].sector_count = STM32_MAX_BANK >> 1; - flash_info[1].sector_count = (size - STM32_MAX_BANK) >> 1; - } - - /* Configure start/size for all sectors */ - for (i = 0; i < banks; i++) { - flash_info[i].flash_id = FLASH_STM32F1; - flash_info[i].start[0] = CONFIG_SYS_FLASH_BASE + (i << 19); - flash_info[i].size = 2048; - for (j = 1; (j < flash_info[i].sector_count); j++) { - flash_info[i].start[j] = flash_info[i].start[j - 1] - + 2048; - flash_info[i].size += 2048; - } - } - - return size << 10; -} - -void flash_print_info(flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf("Missing or unknown FLASH type\n"); - return; - } else if (info->flash_id == FLASH_STM32F1) { - printf("STM32F1 Embedded Flash\n"); - } - - printf(" Size: %ld MB in %d Sectors\n", - info->size >> 10, info->sector_count); - - printf(" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf("\n "); - printf(" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " "); - } - printf("\n"); - return; -} - -int flash_erase(flash_info_t *info, int first, int last) -{ - u8 bank = 0xff; - int i; - - for (i = 0; i < STM32_NUM_BANKS; i++) { - if (info == &flash_info[i]) { - bank = i; - break; - } - } - if (bank == 0xff) - return -1; - - stm32f1_flash_lock(bank, 0); - - for (i = first; i <= last; i++) { - while (readl(&flash_bank[bank]->sr) & STM32_FLASH_SR_BSY) - ; - - setbits_le32(&flash_bank[bank]->cr, STM32_FLASH_CR_PER); - - writel(info->start[i], &flash_bank[bank]->ar); - - setbits_le32(&flash_bank[bank]->cr, STM32_FLASH_CR_STRT); - - while (readl(&flash_bank[bank]->sr) & STM32_FLASH_SR_BSY) - ; - } - - clrbits_le32(&flash_bank[bank]->cr, STM32_FLASH_CR_PER); - - stm32f1_flash_lock(bank, 1); - - return 0; -} - -int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong i; - u8 bank = 0xff; - - if (addr & 1) { - printf("Flash address must be half word aligned\n"); - return -1; - } - - if (cnt & 1) { - printf("Flash length must be half word aligned\n"); - return -1; - } - - for (i = 0; i < 2; i++) { - if (info == &flash_info[i]) { - bank = i; - break; - } - } - - if (bank == 0xff) - return -1; - - while (readl(&flash_bank[bank]->sr) & STM32_FLASH_SR_BSY) - ; - - stm32f1_flash_lock(bank, 0); - - setbits_le32(&flash_bank[bank]->cr, STM32_FLASH_CR_PG); - - /* STM32F1 requires half word writes */ - for (i = 0; i < cnt >> 1; i++) { - *(u16 *)(addr + i * 2) = ((u16 *)src)[i]; - while (readl(&flash_bank[bank]->sr) & STM32_FLASH_SR_BSY) - ; - } - - clrbits_le32(&flash_bank[bank]->cr, STM32_FLASH_CR_PG); - - stm32f1_flash_lock(bank, 1); - - return 0; -} diff --git a/arch/arm/mach-stm32/stm32f1/soc.c b/arch/arm/mach-stm32/stm32f1/soc.c deleted file mode 100644 index 4438621b9a..0000000000 --- a/arch/arm/mach-stm32/stm32f1/soc.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * (C) Copyright 2015 - * Kamil Lulko, <kamil.lulko@gmail.com> - * - * Copyright 2015 ATS Advanced Telematics Systems GmbH - * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/armv7m.h> -#include <asm/arch/stm32.h> - -u32 get_cpu_rev(void) -{ - return 0; -} - -int arch_cpu_init(void) -{ - configure_clocks(); - - /* - * Configure the memory protection unit (MPU) to allow full access to - * the whole 4GB address space. - */ - writel(0, &V7M_MPU->rnr); - writel(0, &V7M_MPU->rbar); - writel((V7M_MPU_RASR_AP_RW_RW | V7M_MPU_RASR_SIZE_4GB - | V7M_MPU_RASR_EN), &V7M_MPU->rasr); - writel(V7M_MPU_CTRL_ENABLE | V7M_MPU_CTRL_HFNMIENA, &V7M_MPU->ctrl); - - return 0; -} diff --git a/arch/arm/mach-stm32/stm32f1/timer.c b/arch/arm/mach-stm32/stm32f1/timer.c deleted file mode 100644 index 6a261986e9..0000000000 --- a/arch/arm/mach-stm32/stm32f1/timer.c +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2015 - * Kamil Lulko, <kamil.lulko@gmail.com> - * - * Copyright 2015 ATS Advanced Telematics Systems GmbH - * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/armv7m.h> -#include <asm/arch/stm32.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define STM32_TIM2_BASE (STM32_APB1PERIPH_BASE + 0x0000) - -#define RCC_APB1ENR_TIM2EN (1 << 0) - -struct stm32_tim2_5 { - u32 cr1; - u32 cr2; - u32 smcr; - u32 dier; - u32 sr; - u32 egr; - u32 ccmr1; - u32 ccmr2; - u32 ccer; - u32 cnt; - u32 psc; - u32 arr; - u32 reserved1; - u32 ccr1; - u32 ccr2; - u32 ccr3; - u32 ccr4; - u32 reserved2; - u32 dcr; - u32 dmar; - u32 or; -}; - -#define TIM_CR1_CEN (1 << 0) - -#define TIM_EGR_UG (1 << 0) - -int timer_init(void) -{ - struct stm32_tim2_5 *tim = (struct stm32_tim2_5 *)STM32_TIM2_BASE; - - setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN); - - if (clock_get(CLOCK_AHB) == clock_get(CLOCK_APB1)) - writel((clock_get(CLOCK_APB1) / CONFIG_SYS_HZ_CLOCK) - 1, - &tim->psc); - else - writel(((clock_get(CLOCK_APB1) * 2) / CONFIG_SYS_HZ_CLOCK) - 1, - &tim->psc); - - writel(0xFFFFFFFF, &tim->arr); - writel(TIM_CR1_CEN, &tim->cr1); - setbits_le32(&tim->egr, TIM_EGR_UG); - - gd->arch.tbl = 0; - gd->arch.tbu = 0; - gd->arch.lastinc = 0; - - return 0; -} - -ulong get_timer(ulong base) -{ - return (get_ticks() / (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)) - base; -} - -unsigned long long get_ticks(void) -{ - struct stm32_tim2_5 *tim = (struct stm32_tim2_5 *)STM32_TIM2_BASE; - u32 now; - - now = readl(&tim->cnt); - - if (now >= gd->arch.lastinc) - gd->arch.tbl += (now - gd->arch.lastinc); - else - gd->arch.tbl += (0xFFFFFFFF - gd->arch.lastinc) + now; - - gd->arch.lastinc = now; - - return gd->arch.tbl; -} - -void reset_timer(void) -{ - struct stm32_tim2_5 *tim = (struct stm32_tim2_5 *)STM32_TIM2_BASE; - - gd->arch.lastinc = readl(&tim->cnt); - gd->arch.tbl = 0; -} - -/* delay x useconds */ -void __udelay(ulong usec) -{ - unsigned long long start; - - start = get_ticks(); /* get current timestamp */ - while ((get_ticks() - start) < usec) - ; /* loop till time has passed */ -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk(void) -{ - return CONFIG_SYS_HZ_CLOCK; -} diff --git a/arch/arm/mach-stm32/stm32f4/soc.c b/arch/arm/mach-stm32/stm32f4/soc.c index 3f45a25cea..9eb655a681 100644 --- a/arch/arm/mach-stm32/stm32f4/soc.c +++ b/arch/arm/mach-stm32/stm32f4/soc.c @@ -21,13 +21,15 @@ int arch_cpu_init(void) { 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW, STRONG_ORDER, REGION_4GB }, }; + int i; + configure_clocks(); /* * Configure the memory protection unit (MPU) to allow full access to * the whole 4GB address space. */ disable_mpu(); - for (int i = 0; i < ARRAY_SIZE(stm32_region_config); i++) + for (i = 0; i < ARRAY_SIZE(stm32_region_config); i++) mpu_config(&stm32_region_config[i]); enable_mpu(); diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 94412bac0c..2cd7bae078 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -1,5 +1,8 @@ if ARCH_SUNXI +config SPL_LDSCRIPT + default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64 + config IDENT_STRING default " Allwinner Technology" @@ -59,7 +62,6 @@ config MACH_SUNXI_H3_H5 select SUNXI_DRAM_DW_32BIT select SUNXI_GEN_SUN6I select SUPPORT_SPL - imply ENV_IS_IN_MMC choice prompt "Sunxi SoC Variant" @@ -71,7 +73,6 @@ config MACH_SUN4I select ARM_CORTEX_CPU_IS_UP select SUNXI_GEN_SUN4I select SUPPORT_SPL - imply ENV_IS_IN_MMC config MACH_SUN5I bool "sun5i (Allwinner A13)" @@ -89,7 +90,6 @@ config MACH_SUN6I select SUNXI_GEN_SUN6I select SUPPORT_SPL select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT - imply ENV_IS_IN_MMC config MACH_SUN7I bool "sun7i (Allwinner A20)" @@ -100,7 +100,6 @@ config MACH_SUN7I select SUNXI_GEN_SUN4I select SUPPORT_SPL select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT - imply ENV_IS_IN_MMC config MACH_SUN8I_A23 bool "sun8i (Allwinner A23)" @@ -111,7 +110,6 @@ config MACH_SUN8I_A23 select SUNXI_GEN_SUN6I select SUPPORT_SPL select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT - imply ENV_IS_IN_MMC config MACH_SUN8I_A33 bool "sun8i (Allwinner A33)" @@ -137,7 +135,6 @@ config MACH_SUN8I_H3 select ARCH_SUPPORT_PSCI select MACH_SUNXI_H3_H5 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT - imply ENV_IS_IN_MMC config MACH_SUN8I_R40 bool "sun8i (Allwinner R40)" diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 48387589d5..51e50907d2 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -60,7 +60,6 @@ config TEGRA_ARMV8_COMMON bool "Tegra 64-bit common options" select ARM64 select TEGRA_COMMON - imply ENV_IS_IN_MMC choice prompt "Tegra SoC select" @@ -78,7 +77,6 @@ config TEGRA30 select ARM_ERRATA_743622 select ARM_ERRATA_751472 select TEGRA_ARMV7_COMMON - imply ENV_IS_IN_MMC config TEGRA114 bool "Tegra114 family" @@ -87,7 +85,8 @@ config TEGRA114 config TEGRA124 bool "Tegra124 family" select TEGRA_ARMV7_COMMON - imply ENV_IS_IN_MMC + imply REGMAP + imply SYSCON config TEGRA210 bool "Tegra210 family" diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 6b5fa7df62..0426b7a95a 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -29,7 +29,6 @@ #ifdef CONFIG_TEGRA_CLOCK_SCALING #include <asm/arch/emc.h> #endif -#include <power/as3722.h> #include "emc.h" DECLARE_GLOBAL_DATA_PTR; @@ -142,11 +141,6 @@ int board_init(void) debug("Memory controller init failed: %d\n", err); # endif # endif /* CONFIG_TEGRA_PMU */ -#ifdef CONFIG_PMIC_AS3722 - err = as3722_init(NULL); - if (err && err != -ENODEV) - return err; -#endif #endif /* CONFIG_SYS_I2C_TEGRA */ #ifdef CONFIG_USB_EHCI_TEGRA @@ -166,7 +160,7 @@ int board_init(void) pin_mux_nand(); #endif - tegra_xusb_padctl_init(gd->fdt_blob); + tegra_xusb_padctl_init(); #ifdef CONFIG_TEGRA_LP0 /* save Sdram params to PMC 2, 4, and 24 for WB0 */ @@ -220,9 +214,9 @@ int board_late_init(void) #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) if (tegra_cpu_is_non_secure()) { printf("CPU is in NS mode\n"); - setenv("cpu_ns_mode", "1"); + env_set("cpu_ns_mode", "1"); } else { - setenv("cpu_ns_mode", ""); + env_set("cpu_ns_mode", ""); } #endif start_cpu_fan(); diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c index 668bbd20c1..dc58b3027d 100644 --- a/arch/arm/mach-tegra/clock.c +++ b/arch/arm/mach-tegra/clock.c @@ -655,14 +655,13 @@ void clock_ll_start_uart(enum periph_id periph_id) } #if CONFIG_IS_ENABLED(OF_CONTROL) -int clock_decode_periph_id(const void *blob, int node) +int clock_decode_periph_id(struct udevice *dev) { enum periph_id id; u32 cell[2]; int err; - err = fdtdec_get_int_array(blob, node, "clocks", cell, - ARRAY_SIZE(cell)); + err = dev_read_u32_array(dev, "clocks", cell, ARRAY_SIZE(cell)); if (err) return -1; id = clk_id_to_periph_id(cell[1]); diff --git a/arch/arm/mach-tegra/spl.c b/arch/arm/mach-tegra/spl.c index 41c88cb2b4..189b3da026 100644 --- a/arch/arm/mach-tegra/spl.c +++ b/arch/arm/mach-tegra/spl.c @@ -7,6 +7,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> +#include <debug_uart.h> #include <spl.h> #include <asm/io.h> @@ -32,6 +33,9 @@ void spl_board_init(void) gpio_early_init_uart(); clock_early_init(); +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif preloader_console_init(); } diff --git a/arch/arm/mach-tegra/tegra124/Makefile b/arch/arm/mach-tegra/tegra124/Makefile index c00de6151e..d275dafdc4 100644 --- a/arch/arm/mach-tegra/tegra124/Makefile +++ b/arch/arm/mach-tegra/tegra124/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_SPL_BUILD) += cpu.o obj-y += clock.o obj-y += funcmux.o obj-y += pinmux.o +obj-y += pmc.o obj-y += xusb-padctl.o obj-y += ../xusb-padctl-common.o diff --git a/arch/arm/mach-tegra/tegra124/pmc.c b/arch/arm/mach-tegra/tegra124/pmc.c new file mode 100644 index 0000000000..be82acf11e --- /dev/null +++ b/arch/arm/mach-tegra/tegra124/pmc.c @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2017 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <syscon.h> + +static const struct udevice_id tegra124_syscon_ids[] = { + { .compatible = "nvidia,tegra124-pmc", .data = TEGRA_SYSCON_PMC }, +}; + +U_BOOT_DRIVER(syscon_tegra124) = { + .name = "tegra124_syscon", + .id = UCLASS_SYSCON, + .of_match = tegra124_syscon_ids, +}; diff --git a/arch/arm/mach-tegra/tegra124/xusb-padctl.c b/arch/arm/mach-tegra/tegra124/xusb-padctl.c index 76af924b94..d326a6ae57 100644 --- a/arch/arm/mach-tegra/tegra124/xusb-padctl.c +++ b/arch/arm/mach-tegra/tegra124/xusb-padctl.c @@ -8,6 +8,8 @@ #include <common.h> #include <errno.h> +#include <dm/of_access.h> +#include <dm/ofnode.h> #include "../xusb-padctl-common.h" @@ -317,13 +319,33 @@ static const struct tegra_xusb_padctl_soc tegra124_socdata = { .num_phys = ARRAY_SIZE(tegra124_phys), }; -void tegra_xusb_padctl_init(const void *fdt) +void tegra_xusb_padctl_init(void) { - int count, nodes[1]; + ofnode nodes[1]; + int count = 0; + int ret; + + debug("%s: start\n", __func__); + if (of_live_active()) { + struct device_node *np = of_find_compatible_node(NULL, NULL, + "nvidia,tegra124-xusb-padctl"); + + debug("np=%p\n", np); + if (np) { + nodes[0] = np_to_ofnode(np); + count = 1; + } + } else { + int node_offsets[1]; + int i; + + count = fdtdec_find_aliases_for_id(gd->fdt_blob, "padctl", + COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL, + node_offsets, ARRAY_SIZE(node_offsets)); + for (i = 0; i < count; i++) + nodes[i] = offset_to_ofnode(node_offsets[i]); + } - count = fdtdec_find_aliases_for_id(fdt, "padctl", - COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL, - nodes, ARRAY_SIZE(nodes)); - if (tegra_xusb_process_nodes(fdt, nodes, count, &tegra124_socdata)) - return; + ret = tegra_xusb_process_nodes(nodes, count, &tegra124_socdata); + debug("%s: done, ret=%d\n", __func__, ret); } diff --git a/arch/arm/mach-tegra/tegra186/nvtboot_board.c b/arch/arm/mach-tegra/tegra186/nvtboot_board.c index feb935f0d9..b94eb424aa 100644 --- a/arch/arm/mach-tegra/tegra186/nvtboot_board.c +++ b/arch/arm/mach-tegra/tegra186/nvtboot_board.c @@ -15,7 +15,7 @@ static int set_fdt_addr(void) { int ret; - ret = setenv_hex("fdt_addr", nvtboot_boot_x0); + ret = env_set_hex("fdt_addr", nvtboot_boot_x0); if (ret) { printf("Failed to set fdt_addr to point at DTB: %d\n", ret); return ret; @@ -35,7 +35,7 @@ static int set_ethaddr_from_nvtboot(void) const u32 *prop; /* Already a valid address in the environment? If so, keep it */ - if (getenv("ethaddr")) + if (env_get("ethaddr")) return 0; node = fdt_path_offset(nvtboot_blob, "/chosen"); @@ -49,7 +49,7 @@ static int set_ethaddr_from_nvtboot(void) return -ENOENT; } - ret = setenv("ethaddr", (void *)prop); + ret = env_set("ethaddr", (void *)prop); if (ret) { printf("Failed to set ethaddr from nvtboot DTB: %d\n", ret); return ret; diff --git a/arch/arm/mach-tegra/tegra210/xusb-padctl.c b/arch/arm/mach-tegra/tegra210/xusb-padctl.c index 9ec93e7c4c..bf85e075de 100644 --- a/arch/arm/mach-tegra/tegra210/xusb-padctl.c +++ b/arch/arm/mach-tegra/tegra210/xusb-padctl.c @@ -8,6 +8,8 @@ #include <common.h> #include <errno.h> +#include <dm/of_access.h> +#include <dm/ofnode.h> #include "../xusb-padctl-common.h" @@ -15,6 +17,8 @@ #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> +DECLARE_GLOBAL_DATA_PTR; + enum tegra210_function { TEGRA210_FUNC_SNPS, TEGRA210_FUNC_XUSB, @@ -421,17 +425,33 @@ static const struct tegra_xusb_padctl_soc tegra210_socdata = { .num_phys = ARRAY_SIZE(tegra210_phys), }; -void tegra_xusb_padctl_init(const void *fdt) +void tegra_xusb_padctl_init(void) { - int count, nodes[1]; - - debug("> %s(fdt=%p)\n", __func__, fdt); - - count = fdtdec_find_aliases_for_id(fdt, "padctl", - COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL, - nodes, ARRAY_SIZE(nodes)); - if (tegra_xusb_process_nodes(fdt, nodes, count, &tegra210_socdata)) - return; + ofnode nodes[1]; + int count = 0; + int ret; + + debug("%s: start\n", __func__); + if (of_live_active()) { + struct device_node *np = of_find_compatible_node(NULL, NULL, + "nvidia,tegra210-xusb-padctl"); + + debug("np=%p\n", np); + if (np) { + nodes[0] = np_to_ofnode(np); + count = 1; + } + } else { + int node_offsets[1]; + int i; + + count = fdtdec_find_aliases_for_id(gd->fdt_blob, "padctl", + COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL, + node_offsets, ARRAY_SIZE(node_offsets)); + for (i = 0; i < count; i++) + nodes[i] = offset_to_ofnode(node_offsets[i]); + } - debug("< %s()\n", __func__); + ret = tegra_xusb_process_nodes(nodes, count, &tegra210_socdata); + debug("%s: done, ret=%d\n", __func__, ret); } diff --git a/arch/arm/mach-tegra/xusb-padctl-common.c b/arch/arm/mach-tegra/xusb-padctl-common.c index 43f5bb7da6..37b5b8fb5b 100644 --- a/arch/arm/mach-tegra/xusb-padctl-common.c +++ b/arch/arm/mach-tegra/xusb-padctl-common.c @@ -75,14 +75,14 @@ tegra_xusb_padctl_find_lane(struct tegra_xusb_padctl *padctl, const char *name) static int tegra_xusb_padctl_group_parse_dt(struct tegra_xusb_padctl *padctl, struct tegra_xusb_padctl_group *group, - const void *fdt, int node) + ofnode node) { unsigned int i; - int len; + int len, ret; - group->name = fdt_get_name(fdt, node, &len); + group->name = ofnode_get_name(node); - len = fdt_stringlist_count(fdt, node, "nvidia,lanes"); + len = ofnode_read_string_count(node, "nvidia,lanes"); if (len < 0) { error("failed to parse \"nvidia,lanes\" property"); return -EINVAL; @@ -91,9 +91,9 @@ tegra_xusb_padctl_group_parse_dt(struct tegra_xusb_padctl *padctl, group->num_pins = len; for (i = 0; i < group->num_pins; i++) { - group->pins[i] = fdt_stringlist_get(fdt, node, "nvidia,lanes", - i, NULL); - if (!group->pins[i]) { + ret = ofnode_read_string_index(node, "nvidia,lanes", i, + &group->pins[i]); + if (ret) { error("failed to read string from \"nvidia,lanes\" property"); return -EINVAL; } @@ -101,13 +101,14 @@ tegra_xusb_padctl_group_parse_dt(struct tegra_xusb_padctl *padctl, group->num_pins = len; - group->func = fdt_stringlist_get(fdt, node, "nvidia,function", 0, NULL); - if (!group->func) { + ret = ofnode_read_string_index(node, "nvidia,function", 0, + &group->func); + if (ret) { error("failed to parse \"nvidia,func\" property"); return -EINVAL; } - group->iddq = fdtdec_get_int(fdt, node, "nvidia,iddq", -1); + group->iddq = ofnode_read_u32_default(node, "nvidia,iddq", -1); return 0; } @@ -217,20 +218,21 @@ tegra_xusb_padctl_config_apply(struct tegra_xusb_padctl *padctl, static int tegra_xusb_padctl_config_parse_dt(struct tegra_xusb_padctl *padctl, struct tegra_xusb_padctl_config *config, - const void *fdt, int node) + ofnode node) { - int subnode; + ofnode subnode; - config->name = fdt_get_name(fdt, node, NULL); + config->name = ofnode_get_name(node); - fdt_for_each_subnode(subnode, fdt, node) { + for (subnode = ofnode_first_subnode(node); + ofnode_valid(subnode); + subnode = ofnode_next_subnode(subnode)) { struct tegra_xusb_padctl_group *group; int err; group = &config->groups[config->num_groups]; - err = tegra_xusb_padctl_group_parse_dt(padctl, group, fdt, - subnode); + err = tegra_xusb_padctl_group_parse_dt(padctl, group, subnode); if (err < 0) { error("failed to parse group %s", group->name); return err; @@ -243,20 +245,24 @@ tegra_xusb_padctl_config_parse_dt(struct tegra_xusb_padctl *padctl, } static int tegra_xusb_padctl_parse_dt(struct tegra_xusb_padctl *padctl, - const void *fdt, int node) + ofnode node) { - int subnode, err; + ofnode subnode; + int err; - err = fdt_get_resource(fdt, node, "reg", 0, &padctl->regs); + err = ofnode_read_resource(node, 0, &padctl->regs); if (err < 0) { error("registers not found"); return err; } - fdt_for_each_subnode(subnode, fdt, node) { + for (subnode = ofnode_first_subnode(node); + ofnode_valid(subnode); + subnode = ofnode_next_subnode(subnode)) { struct tegra_xusb_padctl_config *config = &padctl->config; - err = tegra_xusb_padctl_config_parse_dt(padctl, config, fdt, + debug("%s: subnode=%s\n", __func__, ofnode_get_name(subnode)); + err = tegra_xusb_padctl_config_parse_dt(padctl, config, subnode); if (err < 0) { error("failed to parse entry %s: %d", @@ -264,25 +270,28 @@ static int tegra_xusb_padctl_parse_dt(struct tegra_xusb_padctl *padctl, continue; } } + debug("%s: done\n", __func__); return 0; } struct tegra_xusb_padctl padctl; -int tegra_xusb_process_nodes(const void *fdt, int nodes[], unsigned int count, - const struct tegra_xusb_padctl_soc *socdata) +int tegra_xusb_process_nodes(ofnode nodes[], unsigned int count, + const struct tegra_xusb_padctl_soc *socdata) { unsigned int i; int err; + debug("%s: count=%d\n", __func__, count); for (i = 0; i < count; i++) { - if (!fdtdec_get_is_enabled(fdt, nodes[i])) + debug("%s: i=%d, node=%p\n", __func__, i, nodes[i].np); + if (!ofnode_is_available(nodes[i])) continue; padctl.socdata = socdata; - err = tegra_xusb_padctl_parse_dt(&padctl, fdt, nodes[i]); + err = tegra_xusb_padctl_parse_dt(&padctl, nodes[i]); if (err < 0) { error("failed to parse DT: %d", err); continue; @@ -300,6 +309,7 @@ int tegra_xusb_process_nodes(const void *fdt, int nodes[], unsigned int count, /* only a single instance is supported */ break; } + debug("%s: done\n", __func__); return 0; } diff --git a/arch/arm/mach-tegra/xusb-padctl-common.h b/arch/arm/mach-tegra/xusb-padctl-common.h index f44790a650..68365883c7 100644 --- a/arch/arm/mach-tegra/xusb-padctl-common.h +++ b/arch/arm/mach-tegra/xusb-padctl-common.h @@ -9,9 +9,11 @@ #include <common.h> #include <fdtdec.h> +#include <dm/ofnode.h> #include <asm/io.h> #include <asm/arch-tegra/xusb-padctl.h> +#include <linux/ioport.h> struct tegra_xusb_padctl_lane { const char *name; @@ -77,7 +79,7 @@ struct tegra_xusb_padctl_config { struct tegra_xusb_padctl { const struct tegra_xusb_padctl_soc *socdata; struct tegra_xusb_padctl_config config; - struct fdt_resource regs; + struct resource regs; unsigned int enable; }; @@ -95,7 +97,7 @@ static inline void padctl_writel(struct tegra_xusb_padctl *padctl, writel(value, padctl->regs.start + offset); } -int tegra_xusb_process_nodes(const void *fdt, int nodes[], unsigned int count, - const struct tegra_xusb_padctl_soc *socdata); +int tegra_xusb_process_nodes(ofnode nodes[], unsigned int count, + const struct tegra_xusb_padctl_soc *socdata); #endif diff --git a/arch/arm/mach-tegra/xusb-padctl-dummy.c b/arch/arm/mach-tegra/xusb-padctl-dummy.c index 65f8d2ea96..856d712512 100644 --- a/arch/arm/mach-tegra/xusb-padctl-dummy.c +++ b/arch/arm/mach-tegra/xusb-padctl-dummy.c @@ -34,6 +34,6 @@ int __weak tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy) return -ENOSYS; } -void __weak tegra_xusb_padctl_init(const void *fdt) +void __weak tegra_xusb_padctl_init(void) { } diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig index 1aed55a539..3147db76cb 100644 --- a/arch/arm/mach-uniphier/Kconfig +++ b/arch/arm/mach-uniphier/Kconfig @@ -9,6 +9,7 @@ config ARCH_UNIPHIER_32BIT select CPU_V7_HAS_NONSEC select ARMV7_NONSEC select ARCH_SUPPORT_PSCI + imply NAND choice prompt "UniPhier SoC select" diff --git a/arch/arm/mach-uniphier/board_late_init.c b/arch/arm/mach-uniphier/board_late_init.c index 4bfa10b374..b9a2cbe148 100644 --- a/arch/arm/mach-uniphier/board_late_init.c +++ b/arch/arm/mach-uniphier/board_late_init.c @@ -37,7 +37,7 @@ static int uniphier_set_fdt_file(void) char dtb_name[256]; int buf_len = sizeof(dtb_name); - if (getenv("fdt_file")) + if (env_get("fdt_file")) return 0; /* do nothing if it is already set */ compat = fdt_stringlist_get(gd->fdt_blob, 0, "compatible", 0, NULL); @@ -55,7 +55,7 @@ static int uniphier_set_fdt_file(void) strncat(dtb_name, ".dtb", buf_len); - return setenv("fdt_file", dtb_name); + return env_set("fdt_file", dtb_name); } int board_late_init(void) @@ -65,20 +65,20 @@ int board_late_init(void) switch (uniphier_boot_device_raw()) { case BOOT_DEVICE_MMC1: printf("eMMC Boot"); - setenv("bootmode", "emmcboot"); + env_set("bootmode", "emmcboot"); break; case BOOT_DEVICE_NAND: printf("NAND Boot"); - setenv("bootmode", "nandboot"); + env_set("bootmode", "nandboot"); nand_denali_wp_disable(); break; case BOOT_DEVICE_NOR: printf("NOR Boot"); - setenv("bootmode", "norboot"); + env_set("bootmode", "norboot"); break; case BOOT_DEVICE_USB: printf("USB Boot"); - setenv("bootmode", "usbboot"); + env_set("bootmode", "usbboot"); break; default: printf("Unknown"); diff --git a/arch/arm/mach-uniphier/mmc-first-dev.c b/arch/arm/mach-uniphier/mmc-first-dev.c index 8c45229a89..acc859a6c3 100644 --- a/arch/arm/mach-uniphier/mmc-first-dev.c +++ b/arch/arm/mach-uniphier/mmc-first-dev.c @@ -35,7 +35,7 @@ static int do_mmcsetn(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (dev < 0) return CMD_RET_FAILURE; - setenv_ulong("mmc_first_dev", dev); + env_set_ulong("mmc_first_dev", dev); return CMD_RET_SUCCESS; } diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig index c428ce5cc7..b9cd45ba09 100644 --- a/arch/arm/mach-zynq/Kconfig +++ b/arch/arm/mach-zynq/Kconfig @@ -1,5 +1,8 @@ if ARCH_ZYNQ +config SPL_LDSCRIPT + default "arch/arm/mach-zynq/u-boot-spl.lds" + config SPL_FAT_SUPPORT default y diff --git a/arch/arm/mach-zynq/u-boot.lds b/arch/arm/mach-zynq/u-boot.lds index 4dc9bb0102..86559cb6aa 100644 --- a/arch/arm/mach-zynq/u-boot.lds +++ b/arch/arm/mach-zynq/u-boot.lds @@ -42,6 +42,35 @@ SECTIONS . = ALIGN(4); + .__efi_runtime_start : { + *(.__efi_runtime_start) + } + + .efi_runtime : { + *(efi_runtime_text) + *(efi_runtime_data) + } + + .__efi_runtime_stop : { + *(.__efi_runtime_stop) + } + + .efi_runtime_rel_start : + { + *(.__efi_runtime_rel_start) + } + + .efi_runtime_rel : { + *(.relefi_runtime_text) + *(.relefi_runtime_data) + } + + .efi_runtime_rel_stop : + { + *(.__efi_runtime_rel_stop) + } + + . = ALIGN(4); .image_copy_end : { *(.__image_copy_end) diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig index 88e7d6a7b6..26509b73c6 100644 --- a/arch/m68k/Kconfig +++ b/arch/m68k/Kconfig @@ -10,7 +10,6 @@ config MCF520x config MCF52x2 bool - imply ENV_IS_IN_FLASH config MCF523x bool @@ -23,7 +22,6 @@ config MCF5301x config MCF532x bool - imply ENV_IS_IN_FLASH config MCF537x bool @@ -39,7 +37,6 @@ config MCF5227x config MCF547x_8x bool - imply ENV_IS_IN_FLASH # processor type config M5208 @@ -73,7 +70,6 @@ config M5275 config M5282 bool select MCF52x2 - imply ENV_IS_IN_FLASH config M5307 bool @@ -111,12 +107,10 @@ config M52277 config M547x bool select MCF547x_8x - imply ENV_IS_IN_FLASH config M548x bool select MCF547x_8x - imply ENV_IS_IN_FLASH choice prompt "Target select" @@ -197,12 +191,10 @@ config TARGET_M54455EVB config TARGET_M5475EVB bool "Support M5475EVB" select M547x - imply ENV_IS_IN_FLASH config TARGET_M5485EVB bool "Support M5485EVB" select M548x - imply ENV_IS_IN_FLASH config TARGET_AMCORE bool "Support AMCORE" diff --git a/arch/m68k/lib/bootm.c b/arch/m68k/lib/bootm.c index fa9c493081..c976904fa9 100644 --- a/arch/m68k/lib/bootm.c +++ b/arch/m68k/lib/bootm.c @@ -113,7 +113,8 @@ static void set_clocks_in_mhz (bd_t *kbd) { char *s; - if ((s = getenv("clocks_in_mhz")) != NULL) { + s = env_get("clocks_in_mhz"); + if (s) { /* convert all clock information to MHz */ kbd->bi_intfreq /= 1000000L; kbd->bi_busfreq /= 1000000L; diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig index 20fa25b5cc..f791c0081e 100644 --- a/arch/microblaze/Kconfig +++ b/arch/microblaze/Kconfig @@ -21,4 +21,7 @@ endchoice source "board/xilinx/microblaze-generic/Kconfig" +config SPL_LDSCRIPT + default "arch/microblaze/cpu/u-boot-spl.lds" + endmenu diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S index 79dc0cfc27..baf4f5103f 100644 --- a/arch/microblaze/cpu/start.S +++ b/arch/microblaze/cpu/start.S @@ -31,8 +31,8 @@ _start: mts rshr, r1 addi r1, r1, -4 /* Decrement SP to top of memory */ #else -#if defined(CONFIG_SYS_MALLOC_F_LEN) - addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET - CONFIG_SYS_MALLOC_F_LEN +#if CONFIG_VAL(SYS_MALLOC_F_LEN) + addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET - CONFIG_VAL(SYS_MALLOC_F_LEN) #else addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET #endif @@ -162,14 +162,14 @@ clear_bss: #ifndef CONFIG_SPL_BUILD or r5, r0, r0 /* flags - empty */ addi r31, r0, _gd -#if defined(CONFIG_SYS_MALLOC_F_LEN) +#if CONFIG_VAL(SYS_MALLOC_F_LEN) addi r6, r0, CONFIG_SYS_INIT_SP_OFFSET swi r6, r31, GD_MALLOC_BASE #endif brai board_init_f #else addi r31, r0, _gd -#if defined(CONFIG_SYS_MALLOC_F_LEN) +#if CONFIG_VAL(SYS_MALLOC_F_LEN) addi r6, r0, CONFIG_SPL_STACK_ADDR swi r6, r31, GD_MALLOC_BASE #endif diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c index 2732203b93..0a286e82c2 100644 --- a/arch/microblaze/lib/bootm.c +++ b/arch/microblaze/lib/bootm.c @@ -27,7 +27,7 @@ int do_bootm_linux(int flag, int argc, char * const argv[], { /* First parameter is mapped to $r5 for kernel boot args */ void (*thekernel) (char *, ulong, ulong); - char *commandline = getenv("bootargs"); + char *commandline = env_get("bootargs"); ulong rd_data_start, rd_data_end; /* diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index b53206bf8e..d07b92d1b4 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -21,7 +21,6 @@ config TARGET_QEMU_MIPS select SUPPORTS_CPU_MIPS64_R1 select SUPPORTS_CPU_MIPS64_R2 select ROM_EXCEPTION_VECTORS - imply ENV_IS_IN_FLASH config TARGET_MALTA bool "Support malta" @@ -43,7 +42,6 @@ config TARGET_MALTA select SWAP_IO_SPACE select MIPS_L1_CACHE_SHIFT_6 select ROM_EXCEPTION_VECTORS - imply ENV_IS_IN_FLASH config TARGET_VCT bool "Support vct" @@ -85,7 +83,6 @@ config ARCH_BMIPS select CPU select RAM select SYSRESET - imply ENV_IS_NOWHERE config MACH_PIC32 bool "Support Microchip PIC32" @@ -110,7 +107,6 @@ config TARGET_BOSTON select SUPPORTS_CPU_MIPS64_R2 select SUPPORTS_CPU_MIPS64_R6 select ROM_EXCEPTION_VECTORS - imply ENV_IS_IN_FLASH config TARGET_XILFPGA bool "Support Imagination Xilfpga" @@ -200,7 +196,6 @@ config CPU_MIPS64_R2 bool "MIPS64 Release 2" depends on SUPPORTS_CPU_MIPS64_R2 select 64BIT - imply ENV_IS_IN_FLASH help Choose this option to build a kernel for release 2 through 5 of the MIPS64 architecture. diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index 952c57afd7..42af9def69 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -60,8 +60,8 @@ sp, sp, GD_SIZE # reserve space for gd and sp, sp, t0 # force 16 byte alignment move k0, sp # save gd pointer -#ifdef CONFIG_SYS_MALLOC_F_LEN - li t2, CONFIG_SYS_MALLOC_F_LEN +#if CONFIG_VAL(SYS_MALLOC_F_LEN) + li t2, CONFIG_VAL(SYS_MALLOC_F_LEN) PTR_SUBU \ sp, sp, t2 # reserve space for early malloc and sp, sp, t0 # force 16 byte alignment @@ -75,7 +75,7 @@ blt t0, t1, 1b PTR_ADDIU t0, PTRSIZE -#ifdef CONFIG_SYS_MALLOC_F_LEN +#if CONFIG_VAL(SYS_MALLOC_F_LEN) PTR_S sp, GD_MALLOC_BASE(k0) # gd->malloc_base offset #endif .endm diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c index 2b6790524c..5a9a2811ff 100644 --- a/arch/mips/lib/bootm.c +++ b/arch/mips/lib/bootm.c @@ -80,7 +80,7 @@ static void linux_cmdline_legacy(bootm_headers_t *images) linux_cmdline_init(); - bootargs = getenv("bootargs"); + bootargs = env_get("bootargs"); if (!bootargs) return; @@ -202,11 +202,11 @@ static void linux_env_legacy(bootm_headers_t *images) sprintf(env_buf, "0x%X", (uint) (gd->bd->bi_flashsize)); linux_env_set("flash_size", env_buf); - cp = getenv("ethaddr"); + cp = env_get("ethaddr"); if (cp) linux_env_set("ethaddr", cp); - cp = getenv("eth1addr"); + cp = env_get("eth1addr"); if (cp) linux_env_set("eth1addr", cp); diff --git a/arch/nds32/lib/bootm.c b/arch/nds32/lib/bootm.c index 21aadf284f..e834329e0b 100644 --- a/arch/nds32/lib/bootm.c +++ b/arch/nds32/lib/bootm.c @@ -50,7 +50,7 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) void (*theKernel)(int zero, int arch, uint params); #ifdef CONFIG_CMDLINE_TAG - char *commandline = getenv("bootargs"); + char *commandline = env_get("bootargs"); #endif /* @@ -64,7 +64,7 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) theKernel = (void (*)(int, int, uint))images->ep; - s = getenv("machid"); + s = env_get("machid"); if (s) { machid = simple_strtoul(s, NULL, 16); printf("Using machid 0x%x from environment\n", machid); diff --git a/arch/nios2/lib/bootm.c b/arch/nios2/lib/bootm.c index 4e5c269193..00ade2c573 100644 --- a/arch/nios2/lib/bootm.c +++ b/arch/nios2/lib/bootm.c @@ -12,7 +12,7 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *images) { void (*kernel)(int, int, int, char *) = (void *)images->ep; - char *commandline = getenv("bootargs"); + char *commandline = env_get("bootargs"); ulong initrd_start = images->rd_start; ulong initrd_end = images->rd_end; char *of_flat_tree = NULL; diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 8094416e4a..e4b3043fa2 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -28,10 +28,11 @@ config MPC86xx bool "MPC86xx" select SYS_FSL_DDR select SYS_FSL_DDR_BE - imply ENV_IS_IN_FLASH + imply CMD_REGINFO config 8xx bool "MPC8xx" + imply CMD_REGINFO endchoice diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index b5b26f9b3a..a3779734c1 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -13,7 +13,6 @@ config TARGET_MPC8308_P1M config TARGET_SBC8349 bool "Support sbc8349" - imply ENV_IS_IN_FLASH config TARGET_VE8313 bool "Support ve8313" @@ -40,7 +39,6 @@ config TARGET_MPC8323ERDB config TARGET_MPC832XEMDS bool "Support MPC832XEMDS" select BOARD_EARLY_INIT_F - imply ENV_IS_IN_FLASH config TARGET_MPC8349EMDS bool "Support MPC8349EMDS" @@ -52,7 +50,6 @@ config TARGET_MPC8349EMDS config TARGET_MPC8349ITX bool "Support MPC8349ITX" imply CMD_IRQ - imply ENV_IS_IN_FLASH config TARGET_MPC837XEMDS bool "Support MPC837XEMDS" @@ -77,13 +74,11 @@ config TARGET_SUVD3 bool "Support suvd3" imply CMD_CRAMFS imply FS_CRAMFS - imply ENV_IS_IN_FLASH config TARGET_TUXX1 bool "Support tuxx1" imply CMD_CRAMFS imply FS_CRAMFS - imply ENV_IS_IN_FLASH config TARGET_TQM834X bool "Support TQM834x" @@ -95,7 +90,7 @@ config TARGET_HRCON config TARGET_STRIDER bool "Support strider" select SYS_FSL_ERRATUM_ESDHC111 - imply ENV_IS_IN_FLASH + imply CMD_PCA953X endchoice diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index d99ae27a65..d2fced8aba 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -264,14 +264,14 @@ in_flash: cmplw r3, r4 bne 1b -#ifdef CONFIG_SYS_MALLOC_F_LEN +#if CONFIG_VAL(SYS_MALLOC_F_LEN) -#if CONFIG_SYS_MALLOC_F_LEN + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE -#error "CONFIG_SYS_MALLOC_F_LEN too large to fit into initial RAM." +#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE +#error "SYS_MALLOC_F_LEN too large to fit into initial RAM." #endif /* r3 = new stack pointer / pre-reloc malloc area */ - subi r3, r3, CONFIG_SYS_MALLOC_F_LEN + subi r3, r3, CONFIG_VAL(SYS_MALLOC_F_LEN) /* Set pointer to pre-reloc malloc area in GD */ stw r3, GD_MALLOC_BASE(r4) diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 0c74f1d35b..92187d371b 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -19,7 +19,6 @@ choice config TARGET_SBC8548 bool "Support sbc8548" select ARCH_MPC8548 - imply ENV_IS_IN_FLASH config TARGET_SOCRATES bool "Support socrates" @@ -105,7 +104,6 @@ config TARGET_MPC8544DS config TARGET_MPC8548CDS bool "Support MPC8548CDS" select ARCH_MPC8548 - imply ENV_IS_IN_FLASH config TARGET_MPC8555CDS bool "Support MPC8555CDS" @@ -426,6 +424,8 @@ config ARCH_B4420 select SYS_PPC64 select FSL_IFC imply CMD_EEPROM + imply CMD_NAND + imply CMD_REGINFO config ARCH_B4860 bool @@ -452,6 +452,8 @@ config ARCH_B4860 select SYS_PPC64 select FSL_IFC imply CMD_EEPROM + imply CMD_NAND + imply CMD_REGINFO config ARCH_BSC9131 bool @@ -466,6 +468,8 @@ config ARCH_BSC9131 select SYS_FSL_SEC_COMPAT_4 select FSL_IFC imply CMD_EEPROM + imply CMD_NAND + imply CMD_REGINFO config ARCH_BSC9132 bool @@ -485,6 +489,9 @@ config ARCH_BSC9132 select FSL_IFC imply CMD_EEPROM imply CMD_MTDPARTS + imply CMD_NAND + imply CMD_PCI + imply CMD_REGINFO config ARCH_C29X bool @@ -498,6 +505,9 @@ config ARCH_C29X select SYS_FSL_SEC_COMPAT_6 select SYS_PPC_E500_USE_DEBUG_TLB select FSL_IFC + imply CMD_NAND + imply CMD_PCI + imply CMD_REGINFO config ARCH_MPC8536 bool @@ -511,7 +521,9 @@ config ARCH_MPC8536 select SYS_FSL_SEC_COMPAT_2 select SYS_PPC_E500_USE_DEBUG_TLB select FSL_ELBC + imply CMD_NAND imply CMD_SATA + imply CMD_REGINFO config ARCH_MPC8540 bool @@ -551,7 +563,7 @@ config ARCH_MPC8548 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2 select SYS_PPC_E500_USE_DEBUG_TLB - imply ENV_IS_IN_FLASH + imply CMD_REGINFO config ARCH_MPC8555 bool @@ -584,6 +596,7 @@ config ARCH_MPC8569 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_2 select FSL_ELBC + imply CMD_NAND config ARCH_MPC8572 bool @@ -599,7 +612,7 @@ config ARCH_MPC8572 select SYS_FSL_SEC_COMPAT_2 select SYS_PPC_E500_USE_DEBUG_TLB select FSL_ELBC - imply ENV_IS_IN_FLASH + imply CMD_NAND config ARCH_P1010 bool @@ -623,7 +636,10 @@ config ARCH_P1010 select FSL_IFC imply CMD_EEPROM imply CMD_MTDPARTS + imply CMD_NAND imply CMD_SATA + imply CMD_PCI + imply CMD_REGINFO config ARCH_P1011 bool @@ -652,7 +668,10 @@ config ARCH_P1020 select SYS_FSL_SEC_COMPAT_2 select SYS_PPC_E500_USE_DEBUG_TLB select FSL_ELBC + imply CMD_NAND imply CMD_SATA + imply CMD_PCI + imply CMD_REGINFO config ARCH_P1021 bool @@ -667,7 +686,10 @@ config ARCH_P1021 select SYS_FSL_SEC_COMPAT_2 select SYS_PPC_E500_USE_DEBUG_TLB select FSL_ELBC + imply CMD_REGINFO + imply CMD_NAND imply CMD_SATA + imply CMD_REGINFO config ARCH_P1022 bool @@ -711,7 +733,10 @@ config ARCH_P1024 select SYS_PPC_E500_USE_DEBUG_TLB select FSL_ELBC imply CMD_EEPROM + imply CMD_NAND imply CMD_SATA + imply CMD_PCI + imply CMD_REGINFO config ARCH_P1025 bool @@ -727,6 +752,7 @@ config ARCH_P1025 select SYS_PPC_E500_USE_DEBUG_TLB select FSL_ELBC imply CMD_SATA + imply CMD_REGINFO config ARCH_P2020 bool @@ -743,6 +769,8 @@ config ARCH_P2020 select SYS_PPC_E500_USE_DEBUG_TLB select FSL_ELBC imply CMD_EEPROM + imply CMD_NAND + imply CMD_REGINFO config ARCH_P2041 bool @@ -765,6 +793,7 @@ config ARCH_P2041 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select FSL_ELBC + imply CMD_NAND config ARCH_P3041 bool @@ -789,7 +818,9 @@ config ARCH_P3041 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select FSL_ELBC + imply CMD_NAND imply CMD_SATA + imply CMD_REGINFO config ARCH_P4080 bool @@ -826,6 +857,7 @@ config ARCH_P4080 select SYS_FSL_SEC_COMPAT_4 select FSL_ELBC imply CMD_SATA + imply CMD_REGINFO config ARCH_P5020 bool @@ -848,6 +880,7 @@ config ARCH_P5020 select SYS_PPC64 select FSL_ELBC imply CMD_SATA + imply CMD_REGINFO config ARCH_P5040 bool @@ -870,6 +903,7 @@ config ARCH_P5040 select SYS_PPC64 select FSL_ELBC imply CMD_SATA + imply CMD_REGINFO config ARCH_QEMU_E500 bool @@ -891,6 +925,8 @@ config ARCH_T1023 select SYS_FSL_SEC_COMPAT_5 select FSL_IFC imply CMD_EEPROM + imply CMD_NAND + imply CMD_REGINFO config ARCH_T1024 bool @@ -909,7 +945,9 @@ config ARCH_T1024 select SYS_FSL_SEC_COMPAT_5 select FSL_IFC imply CMD_EEPROM + imply CMD_NAND imply CMD_MTDPARTS + imply CMD_REGINFO config ARCH_T1040 bool @@ -929,7 +967,9 @@ config ARCH_T1040 select SYS_FSL_SEC_COMPAT_5 select FSL_IFC imply CMD_MTDPARTS + imply CMD_NAND imply CMD_SATA + imply CMD_REGINFO config ARCH_T1042 bool @@ -949,7 +989,9 @@ config ARCH_T1042 select SYS_FSL_SEC_COMPAT_5 select FSL_IFC imply CMD_MTDPARTS + imply CMD_NAND imply CMD_SATA + imply CMD_REGINFO config ARCH_T2080 bool @@ -973,6 +1015,8 @@ config ARCH_T2080 select SYS_PPC64 select FSL_IFC imply CMD_SATA + imply CMD_NAND + imply CMD_REGINFO config ARCH_T2081 bool @@ -993,6 +1037,8 @@ config ARCH_T2081 select SYS_FSL_SEC_COMPAT_4 select SYS_PPC64 select FSL_IFC + imply CMD_NAND + imply CMD_REGINFO config ARCH_T4160 bool @@ -1015,6 +1061,8 @@ config ARCH_T4160 select SYS_PPC64 select FSL_IFC imply CMD_SATA + imply CMD_NAND + imply CMD_REGINFO config ARCH_T4240 bool @@ -1040,6 +1088,8 @@ config ARCH_T4240 select SYS_PPC64 select FSL_IFC imply CMD_SATA + imply CMD_NAND + imply CMD_REGINFO config BOOKE bool @@ -1053,6 +1103,7 @@ config E500 config E500MC bool + imply CMD_PCI help Enble PowerPC E500MC core diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index a3076d8d71..ea46e49853 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -256,7 +256,7 @@ static void enable_tdm_law(void) * is not setup properly yet. Search for tdm entry in * hwconfig. */ - ret = getenv_f("hwconfig", buffer, sizeof(buffer)); + ret = env_get_f("hwconfig", buffer, sizeof(buffer)); if (ret > 0) { tdm_hwconfig_enabled = hwconfig_f("tdm", buffer); /* If tdm is defined in hwconfig, set law for tdm workaround */ @@ -280,7 +280,7 @@ void enable_cpc(void) cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; /* Extract hwconfig from environment */ - ret = getenv_f("hwconfig", buffer, sizeof(buffer)); + ret = env_get_f("hwconfig", buffer, sizeof(buffer)); if (ret > 0) { /* * If "en_cpc" is not defined in hwconfig then by default all @@ -754,7 +754,7 @@ int cpu_init_r(void) char *buf = NULL; int n, res; - n = getenv_f("hwconfig", buffer, sizeof(buffer)); + n = env_get_f("hwconfig", buffer, sizeof(buffer)); if (n > 0) buf = buffer; @@ -794,7 +794,7 @@ int cpu_init_r(void) #endif #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP) - spin = getenv("spin_table_compat"); + spin = env_get("spin_table_compat"); if (spin && (*spin == 'n')) spin_table_compat = 0; else @@ -845,7 +845,7 @@ int cpu_init_r(void) #ifdef CONFIG_SYS_SRIO srio_init(); #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER - char *s = getenv("bootmaster"); + char *s = env_get("bootmaster"); if (s) { if (!strcmp(s, "SRIO1")) { srio_boot_master(1); diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index a9ea947305..297dc4af48 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -92,7 +92,7 @@ void ft_fixup_cpu(void *blob, u64 memory_limit) * Extract hwconfig from environment. * Search for tdm entry in hwconfig. */ - ret = getenv_f("hwconfig", buffer, sizeof(buffer)); + ret = env_get_f("hwconfig", buffer, sizeof(buffer)); if (ret > 0) tdm_hwconfig_enabled = hwconfig_f("tdm", buffer); @@ -580,7 +580,7 @@ static void fdt_fixup_l2_switch(void *blob) return; /* Get MAC address for the l2switch from "l2switchaddr"*/ - if (!eth_getenv_enetaddr("l2switchaddr", l2swaddr)) { + if (!eth_env_get_enetaddr("l2switchaddr", l2swaddr)) { printf("Warning: MAC address for l2switch not found\n"); memset(l2swaddr, 0, sizeof(l2swaddr)); } @@ -770,8 +770,15 @@ int ft_verify_fdt(void *fdt) /* First check the CCSR base address */ off = fdt_node_offset_by_prop_value(fdt, -1, "device_type", "soc", 4); - if (off > 0) - addr = fdt_get_base_address(fdt, off); + if (off > 0) { + int size; + u32 naddr; + const fdt32_t *prop; + + naddr = fdt_address_cells(fdt, off); + prop = fdt_getprop(fdt, off, "ranges", &size); + addr = fdt_translate_address(fdt, off, prop + naddr); + } if (!addr) { printf("Warning: could not determine base CCSR address in " diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index 1bc0c64cfc..79d6544a09 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -514,7 +514,7 @@ void fsl_serdes_init(void) * Extract hwconfig from environment since we have not properly setup * the environment but need it for ddr config params */ - if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0) + if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0) buf = buffer; #endif if (serdes_prtcl_map & (1 << NONE)) diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c index 0addf8493c..2ea9f5c7be 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.c +++ b/arch/powerpc/cpu/mpc85xx/mp.c @@ -31,7 +31,7 @@ u32 get_my_id() int hold_cores_in_reset(int verbose) { /* Default to no, overridden by 'y', 'yes', 'Y', 'Yes', or '1' */ - if (getenv_yesno("mp_holdoff") == 1) { + if (env_get_yesno("mp_holdoff") == 1) { if (verbose) { puts("Secondary cores are being held in reset.\n"); puts("See 'mp_holdoff' environment variable\n"); diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index f03e1a0bfe..0f016f0370 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -1183,14 +1183,13 @@ _start_cont: lis r3,(CONFIG_SYS_INIT_RAM_ADDR)@h ori r3,r3,((CONFIG_SYS_INIT_SP_OFFSET-16)&~0xf)@l /* Align to 16 */ -#ifdef CONFIG_SYS_MALLOC_F_LEN - -#if CONFIG_SYS_MALLOC_F_LEN + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE -#error "CONFIG_SYS_MALLOC_F_LEN too large to fit into initial RAM." +#if CONFIG_VAL(SYS_MALLOC_F_LEN) +#if CONFIG_VAL(SYS_MALLOC_F_LEN) + GENERATED_GBL_DATA_SIZE > CONFIG_SYS_INIT_RAM_SIZE +#error "SYS_MALLOC_F_LEN too large to fit into initial RAM." #endif /* Leave 16+ byte for back chain termination and NULL return address */ - subi r3,r3,((CONFIG_SYS_MALLOC_F_LEN+16+15)&~0xf) + subi r3,r3,((CONFIG_VAL(SYS_MALLOC_F_LEN)+16+15)&~0xf) #endif /* End of RAM */ @@ -1204,7 +1203,7 @@ _start_cont: cmplw r4,r3 bne 1b -#ifdef CONFIG_SYS_MALLOC_F_LEN +#if CONFIG_VAL(SYS_MALLOC_F_LEN) lis r4,(CONFIG_SYS_INIT_RAM_ADDR)@h ori r4,r4,(CONFIG_SYS_GBL_DATA_OFFSET)@l diff --git a/arch/powerpc/cpu/mpc86xx/Kconfig b/arch/powerpc/cpu/mpc86xx/Kconfig index fe56efdf55..2cc180da38 100644 --- a/arch/powerpc/cpu/mpc86xx/Kconfig +++ b/arch/powerpc/cpu/mpc86xx/Kconfig @@ -40,7 +40,6 @@ config ARCH_MPC8641 select FSL_LAW select SYS_FSL_HAS_DDR1 select SYS_FSL_HAS_DDR2 - imply ENV_IS_IN_FLASH config FSL_LAW bool diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index eaa23d2edf..6aec815c71 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -74,16 +74,11 @@ /* The TSEC driver uses the PHYLIB infrastructure */ #ifndef CONFIG_PHYLIB #if defined(CONFIG_TSEC_ENET) -#define CONFIG_PHYLIB - #include <config_phylib_all_drivers.h> #endif /* TSEC_ENET */ #endif /* !CONFIG_PHYLIB */ /* The FMAN driver uses the PHYLIB infrastructure */ -#if defined(CONFIG_FMAN_ENET) -#define CONFIG_PHYLIB -#endif /* All PPC boards must swap IDE bytes */ #define CONFIG_IDE_SWAP_IO diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c index 0e204027af..b9ae24dc98 100644 --- a/arch/powerpc/lib/bootm.c +++ b/arch/powerpc/lib/bootm.c @@ -86,7 +86,7 @@ static void boot_jump_linux(bootm_headers_t *images) debug (" Booting using OF flat tree...\n"); WATCHDOG_RESET (); (*kernel) ((bd_t *)of_flat_tree, 0, 0, EPAPR_MAGIC, - getenv_bootm_mapsize(), 0, 0); + env_get_bootm_mapsize(), 0, 0); /* does not return */ } else #endif @@ -121,8 +121,8 @@ void arch_lmb_reserve(struct lmb *lmb) phys_size_t bootm_size; ulong size, sp, bootmap_base; - bootmap_base = getenv_bootm_low(); - bootm_size = getenv_bootm_size(); + bootmap_base = env_get_bootm_low(); + bootm_size = env_get_bootm_size(); #ifdef DEBUG if (((u64)bootmap_base + bootm_size) > @@ -275,7 +275,8 @@ static void set_clocks_in_mhz (bd_t *kbd) { char *s; - if ((s = getenv ("clocks_in_mhz")) != NULL) { + s = env_get("clocks_in_mhz"); + if (s) { /* convert all clock information to MHz */ kbd->bi_intfreq /= 1000000L; kbd->bi_busfreq /= 1000000L; @@ -339,6 +340,6 @@ void boot_jump_vxworks(bootm_headers_t *images) ((void (*)(void *, ulong, ulong, ulong, ulong, ulong, ulong))images->ep)(images->ft_addr, - 0, 0, EPAPR_MAGIC, getenv_bootm_mapsize(), 0, 0); + 0, 0, EPAPR_MAGIC, env_get_bootm_mapsize(), 0, 0); } #endif diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c index 7243bfc1b1..22d6aab534 100644 --- a/arch/sandbox/cpu/os.c +++ b/arch/sandbox/cpu/os.c @@ -413,17 +413,6 @@ int os_get_filesize(const char *fname, loff_t *size) return 0; } -void os_putc(int ch) -{ - putchar(ch); -} - -void os_puts(const char *str) -{ - while (*str) - os_putc(*str++); -} - int os_write_ram_buf(const char *fname) { struct sandbox_state *state = state_get_current(); diff --git a/arch/sandbox/cpu/start.c b/arch/sandbox/cpu/start.c index f605d4d61e..00742fd95e 100644 --- a/arch/sandbox/cpu/start.c +++ b/arch/sandbox/cpu/start.c @@ -310,7 +310,7 @@ int main(int argc, char *argv[]) memset(&data, '\0', sizeof(data)); gd = &data; -#ifdef CONFIG_SYS_MALLOC_F_LEN +#if CONFIG_VAL(SYS_MALLOC_F_LEN) gd->malloc_base = CONFIG_MALLOC_F_ADDR; #endif setup_ram_buf(state); diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 1d40fe6845..d20761e66c 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -3,16 +3,13 @@ menu "SuperH architecture" config CPU_SH2 bool - imply ENV_IS_IN_FLASH config CPU_SH2A bool select CPU_SH2 - imply ENV_IS_IN_FLASH config CPU_SH3 bool - imply ENV_IS_IN_FLASH config CPU_SH4 bool @@ -128,6 +125,8 @@ config SYS_CPU default "sh3" if CPU_SH3 default "sh4" if CPU_SH4 +source "arch/sh/lib/Kconfig" + source "board/alphaproject/ap_sh4a_4a/Kconfig" source "board/espt/Kconfig" source "board/mpr2/Kconfig" diff --git a/arch/sh/cpu/u-boot.lds b/arch/sh/cpu/u-boot.lds index bbf9ff485f..7fc91bc4aa 100644 --- a/arch/sh/cpu/u-boot.lds +++ b/arch/sh/cpu/u-boot.lds @@ -33,9 +33,9 @@ SECTIONS KEEP(CONFIG_BOARDDIR/lowlevel_init.o (.text .spiboot1.text)) KEEP(*(.spiboot2.text)) . = ALIGN(8192); - common/env_embedded.o (.ppcenv) + env/embedded.o (.ppcenv) . = ALIGN(8192); - common/env_embedded.o (.ppcenvr) + env/embedded.o (.ppcenvr) . = ALIGN(8192); *(.text) . = ALIGN(4); diff --git a/arch/sh/lib/Kconfig b/arch/sh/lib/Kconfig new file mode 100644 index 0000000000..cec8d09cc3 --- /dev/null +++ b/arch/sh/lib/Kconfig @@ -0,0 +1,6 @@ +config CMD_SH_ZIMAGEBOOT + bool "zimageboot - Boot a zImage on SH" + default y + help + This is special SH-specific command to boot a zImage (compressed + Linux image) on SH-architecture boards. diff --git a/arch/sh/lib/bootm.c b/arch/sh/lib/bootm.c index 8a0010be23..09fbd5e5df 100644 --- a/arch/sh/lib/bootm.c +++ b/arch/sh/lib/bootm.c @@ -61,7 +61,7 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima char *cmdline = (char *)param + COMMAND_LINE; /* PAGE_SIZE */ unsigned long size = images->ep - (unsigned long)param; - char *bootargs = getenv("bootargs"); + char *bootargs = env_get("bootargs"); /* * allow the PREP bootm subcommand, it is required for bootm to work diff --git a/arch/sh/lib/zimageboot.c b/arch/sh/lib/zimageboot.c index 3fea5f5b53..cd4abba10a 100644 --- a/arch/sh/lib/zimageboot.c +++ b/arch/sh/lib/zimageboot.c @@ -42,7 +42,7 @@ int do_sh_zimageboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /* Linux kernel command line */ cmdline = (char *)param + COMMAND_LINE; - bootargs = getenv("bootargs"); + bootargs = env_get("bootargs"); /* Clear zero page */ /* cppcheck-suppress nullPointer */ diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 0cd981e73e..c26710b484 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -114,6 +114,7 @@ source "arch/x86/cpu/ivybridge/Kconfig" source "arch/x86/cpu/qemu/Kconfig" source "arch/x86/cpu/quark/Kconfig" source "arch/x86/cpu/queensbay/Kconfig" +source "arch/x86/cpu/tangier/Kconfig" # architecture-specific options below @@ -541,6 +542,19 @@ config VGA_BIOS_ADDR address of 0xfff90000 indicates that the image will be put at offset 0x90000 from the beginning of a 1MB flash device. +config ROM_TABLE_ADDR + hex + default 0xf0000 + help + All x86 tables happen to like the address range from 0x0f0000 + to 0x100000. We use 0xf0000 as the starting address to store + those tables, including PIRQ routing table, Multi-Processor + table and ACPI table. + +config ROM_TABLE_SIZE + hex + default 0x10000 + menu "System tables" depends on !EFI && !SYS_COREBOOT diff --git a/arch/x86/config.mk b/arch/x86/config.mk index 74b87ceac5..8835dcf36f 100644 --- a/arch/x86/config.mk +++ b/arch/x86/config.mk @@ -10,8 +10,7 @@ CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000 PLATFORM_CPPFLAGS += -fno-strict-aliasing PLATFORM_CPPFLAGS += -fomit-frame-pointer PF_CPPFLAGS_X86 := $(call cc-option, -fno-toplevel-reorder, \ - $(call cc-option, -fno-unit-at-a-time)) \ - $(call cc-option, -mpreferred-stack-boundary=2) + $(call cc-option, -fno-unit-at-a-time)) PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_X86) PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm @@ -27,7 +26,7 @@ endif ifeq ($(IS_32BIT),y) PLATFORM_CPPFLAGS += -march=i386 -m32 else -PLATFORM_CPPFLAGS += $(if $(CONFIG_SPL_BUILD),,-fpic) -fno-common +PLATFORM_CPPFLAGS += $(if $(CONFIG_SPL_BUILD),,-fpic) -fno-common -m64 endif PLATFORM_RELFLAGS += -ffunction-sections -fvisibility=hidden diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index e1c84ce097..999429e62b 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_QEMU) += qemu/ obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/ obj-$(CONFIG_INTEL_QUARK) += quark/ obj-$(CONFIG_INTEL_QUEENSBAY) += queensbay/ +obj-$(CONFIG_INTEL_TANGIER) += tangier/ obj-y += lapic.o ioapic.o obj-y += irq.o ifndef CONFIG_$(SPL_)X86_64 diff --git a/arch/x86/cpu/baytrail/Kconfig b/arch/x86/cpu/baytrail/Kconfig index 4e7d4a4e25..75dbbc27f1 100644 --- a/arch/x86/cpu/baytrail/Kconfig +++ b/arch/x86/cpu/baytrail/Kconfig @@ -7,7 +7,23 @@ config INTEL_BAYTRAIL bool select HAVE_FSP if !EFI - imply ENV_IS_IN_SPI_FLASH + select ARCH_MISC_INIT if !EFI + imply HAVE_INTEL_ME if !EFI + imply ENABLE_MRC_CACHE + imply AHCI_PCI + imply ICH_SPI + imply INTEL_ICH6_GPIO + imply MMC + imply MMC_PCI + imply MMC_SDHCI + imply MMC_SDHCI_SDMA + imply SCSI + imply SPI_FLASH + imply SYS_NS16550 + imply USB + imply USB_EHCI_HCD + imply USB_XHCI_HCD + imply VIDEO_VESA if INTEL_BAYTRAIL config INTERNAL_UART diff --git a/arch/x86/cpu/baytrail/acpi.c b/arch/x86/cpu/baytrail/acpi.c index 55ed7de781..cbefdf871d 100644 --- a/arch/x86/cpu/baytrail/acpi.c +++ b/arch/x86/cpu/baytrail/acpi.c @@ -11,8 +11,6 @@ #include <asm/acpi_s3.h> #include <asm/acpi_table.h> #include <asm/io.h> -#include <asm/ioapic.h> -#include <asm/mpspec.h> #include <asm/tables.h> #include <asm/arch/global_nvs.h> #include <asm/arch/iomap.h> @@ -141,33 +139,6 @@ void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs, header->checksum = table_compute_checksum(fadt, header->length); } -static int acpi_create_madt_irq_overrides(u32 current) -{ - struct acpi_madt_irqoverride *irqovr; - u16 sci_flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH; - int length = 0; - - irqovr = (void *)current; - length += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0); - - irqovr = (void *)(current + length); - length += acpi_create_madt_irqoverride(irqovr, 0, 9, 9, sci_flags); - - return length; -} - -u32 acpi_fill_madt(u32 current) -{ - current += acpi_create_madt_lapics(current); - - current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current, - io_apic_read(IO_APIC_ID) >> 24, IO_APIC_ADDR, 0); - - current += acpi_create_madt_irq_overrides(current); - - return current; -} - void acpi_create_gnvs(struct acpi_global_nvs *gnvs) { struct udevice *dev; diff --git a/arch/x86/cpu/baytrail/valleyview.c b/arch/x86/cpu/baytrail/valleyview.c index 87ba849c1c..c58f6a86a8 100644 --- a/arch/x86/cpu/baytrail/valleyview.c +++ b/arch/x86/cpu/baytrail/valleyview.c @@ -11,18 +11,6 @@ #include <asm/mrccache.h> #include <asm/post.h> -static struct pci_device_id mmc_supported[] = { - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_SDIO }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_SD }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_EMMC2 }, - {}, -}; - -int cpu_mmc_init(bd_t *bis) -{ - return pci_mmc_init("ValleyView SDHCI", mmc_supported); -} - #ifndef CONFIG_EFI_APP int arch_cpu_init(void) { diff --git a/arch/x86/cpu/broadwell/Kconfig b/arch/x86/cpu/broadwell/Kconfig index 1ce3848be3..bc2dba2bd7 100644 --- a/arch/x86/cpu/broadwell/Kconfig +++ b/arch/x86/cpu/broadwell/Kconfig @@ -6,6 +6,17 @@ config INTEL_BROADWELL bool select CACHE_MRC_BIN + select ARCH_EARLY_INIT_R + imply HAVE_INTEL_ME + imply ENABLE_MRC_CACHE + imply AHCI_PCI + imply ICH_SPI + imply INTEL_BROADWELL_GPIO + imply SCSI + imply SPI_FLASH + imply USB + imply USB_EHCI_HCD + imply VIDEO_BROADWELL_IGD if INTEL_BROADWELL diff --git a/arch/x86/cpu/broadwell/refcode.c b/arch/x86/cpu/broadwell/refcode.c index 436c6c49c3..4fa4de3525 100644 --- a/arch/x86/cpu/broadwell/refcode.c +++ b/arch/x86/cpu/broadwell/refcode.c @@ -56,7 +56,17 @@ struct rmodule_header { uint32_t padding[4]; } __packed; -int cpu_run_reference_code(void) +/** + * cpu_run_reference_code() - Run the platform reference code + * + * Some platforms require a binary blob to be executed once SDRAM is + * available. This is used to set up various platform features, such as the + * platform controller hub (PCH). This function should be implemented by the + * CPU-specific code. + * + * @return 0 on success, -ve on failure + */ +static int cpu_run_reference_code(void) { struct pei_data _pei_data __aligned(8); struct pei_data *pei_data = &_pei_data; @@ -111,3 +121,8 @@ int cpu_run_reference_code(void) return 0; } + +int arch_early_init_r(void) +{ + return cpu_run_reference_code(); +} diff --git a/arch/x86/cpu/coreboot/Kconfig b/arch/x86/cpu/coreboot/Kconfig index 9820651931..60eb45f9d0 100644 --- a/arch/x86/cpu/coreboot/Kconfig +++ b/arch/x86/cpu/coreboot/Kconfig @@ -3,6 +3,19 @@ if TARGET_COREBOOT config SYS_COREBOOT bool default y + imply AHCI_PCI + imply E1000 + imply ICH_SPI + imply MMC + imply MMC_PCI + imply MMC_SDHCI + imply MMC_SDHCI_SDMA + imply SPI_FLASH + imply SYS_NS16550 + imply USB + imply USB_EHCI_HCD + imply USB_XHCI_HCD + imply VIDEO_COREBOOT imply CMD_CBFS imply FS_CBFS diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c index 658b900f0b..df5ad13821 100644 --- a/arch/x86/cpu/coreboot/coreboot.c +++ b/arch/x86/cpu/coreboot/coreboot.c @@ -29,11 +29,6 @@ int arch_cpu_init(void) return x86_cpu_init_f(); } -int board_early_init_f(void) -{ - return 0; -} - int checkcpu(void) { return 0; @@ -90,8 +85,3 @@ int misc_init_r(void) { return 0; } - -int arch_misc_init(void) -{ - return 0; -} diff --git a/arch/x86/cpu/efi/efi.c b/arch/x86/cpu/efi/efi.c index 741613f615..d82147be47 100644 --- a/arch/x86/cpu/efi/efi.c +++ b/arch/x86/cpu/efi/efi.c @@ -13,11 +13,6 @@ int arch_cpu_init(void) return 0; } -int board_early_init_f(void) -{ - return 0; -} - int checkcpu(void) { return 0; @@ -36,8 +31,3 @@ int misc_init_r(void) { return 0; } - -int arch_misc_init(void) -{ - return 0; -} diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig index e23d01a08f..c214ea0efe 100644 --- a/arch/x86/cpu/ivybridge/Kconfig +++ b/arch/x86/cpu/ivybridge/Kconfig @@ -8,6 +8,16 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE bool select CACHE_MRC_BIN if HAVE_MRC + imply HAVE_INTEL_ME + imply ENABLE_MRC_CACHE + imply AHCI_PCI + imply ICH_SPI + imply INTEL_ICH6_GPIO + imply SCSI + imply SPI_FLASH + imply USB + imply USB_EHCI_HCD + imply VIDEO_VESA if NORTHBRIDGE_INTEL_IVYBRIDGE diff --git a/arch/x86/cpu/ivybridge/sata.c b/arch/x86/cpu/ivybridge/sata.c index 462b7c09dd..7febb8cf88 100644 --- a/arch/x86/cpu/ivybridge/sata.c +++ b/arch/x86/cpu/ivybridge/sata.c @@ -236,7 +236,7 @@ static int bd82x6x_sata_probe(struct udevice *dev) bd82x6x_sata_enable(dev); else { bd82x6x_sata_init(dev, pch); - ret = ahci_probe_scsi(dev); + ret = ahci_probe_scsi_pci(dev); if (ret) return ret; } diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index 643d804e35..1cdbe479fd 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -233,7 +233,6 @@ static int sdram_find(struct udevice *dev) uint32_t tseg_base, uma_size, tolud; uint64_t tom, me_base, touud; uint64_t uma_memory_base = 0; - uint64_t uma_memory_size; unsigned long long tomk; uint16_t ggc; u32 val; @@ -298,7 +297,6 @@ static int sdram_find(struct udevice *dev) tolud += uma_size << 10; /* UMA starts at old TOLUD */ uma_memory_base = tomk * 1024ULL; - uma_memory_size = uma_size * 1024ULL; debug("ME UMA base %llx size %uM\n", me_base, uma_size >> 10); } @@ -312,13 +310,11 @@ static int sdram_find(struct udevice *dev) debug("%uM UMA", uma_size >> 10); tomk -= uma_size; uma_memory_base = tomk * 1024ULL; - uma_memory_size += uma_size * 1024ULL; /* GTT Graphics Stolen Memory Size (GGMS) */ uma_size = ((ggc >> 8) & 0x3) * 1024ULL; tomk -= uma_size; uma_memory_base = tomk * 1024ULL; - uma_memory_size += uma_size * 1024ULL; debug(" and %uM GTT\n", uma_size >> 10); } @@ -327,7 +323,6 @@ static int sdram_find(struct udevice *dev) uma_size = (uma_memory_base - tseg_base) >> 10; tomk -= uma_size; uma_memory_base = tomk * 1024ULL; - uma_memory_size += uma_size * 1024ULL; debug("TSEG base 0x%08x size %uM\n", tseg_base, uma_size >> 10); debug("Available memory below 4GB: %lluM\n", tomk >> 10); diff --git a/arch/x86/cpu/qemu/Kconfig b/arch/x86/cpu/qemu/Kconfig index 6808c9a6b9..da378128fe 100644 --- a/arch/x86/cpu/qemu/Kconfig +++ b/arch/x86/cpu/qemu/Kconfig @@ -6,6 +6,13 @@ config QEMU bool + select ARCH_EARLY_INIT_R + imply AHCI_PCI + imply E1000 + imply SYS_NS16550 + imply USB + imply USB_EHCI_HCD + imply VIDEO_VESA if QEMU diff --git a/arch/x86/cpu/quark/Kconfig b/arch/x86/cpu/quark/Kconfig index 163caac660..0ed724813d 100644 --- a/arch/x86/cpu/quark/Kconfig +++ b/arch/x86/cpu/quark/Kconfig @@ -7,6 +7,20 @@ config INTEL_QUARK bool select HAVE_RMU + select ARCH_EARLY_INIT_R + select ARCH_MISC_INIT + imply ENABLE_MRC_CACHE + imply ETH_DESIGNWARE + imply ICH_SPI + imply INTEL_ICH6_GPIO + imply MMC + imply MMC_PCI + imply MMC_SDHCI + imply MMC_SDHCI_SDMA + imply SPI_FLASH + imply SYS_NS16550 + imply USB + imply USB_EHCI_HCD if INTEL_QUARK diff --git a/arch/x86/cpu/quark/acpi.c b/arch/x86/cpu/quark/acpi.c index 3968f7a8bf..5717a620b5 100644 --- a/arch/x86/cpu/quark/acpi.c +++ b/arch/x86/cpu/quark/acpi.c @@ -6,8 +6,6 @@ #include <common.h> #include <asm/acpi_table.h> -#include <asm/ioapic.h> -#include <asm/mpspec.h> #include <asm/tables.h> #include <asm/arch/global_nvs.h> #include <asm/arch/iomap.h> @@ -136,33 +134,6 @@ void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs, header->checksum = table_compute_checksum(fadt, header->length); } -static int acpi_create_madt_irq_overrides(u32 current) -{ - struct acpi_madt_irqoverride *irqovr; - u16 sci_flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH; - int length = 0; - - irqovr = (void *)current; - length += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0); - - irqovr = (void *)(current + length); - length += acpi_create_madt_irqoverride(irqovr, 0, 9, 9, sci_flags); - - return length; -} - -u32 acpi_fill_madt(u32 current) -{ - current += acpi_create_madt_lapics(current); - - current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current, - io_apic_read(IO_APIC_ID) >> 24, IO_APIC_ADDR, 0); - - current += acpi_create_madt_irq_overrides(current); - - return current; -} - void acpi_create_gnvs(struct acpi_global_nvs *gnvs) { /* quark is a uni-processor */ diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c index 0c2cea4ee9..c36a5892d5 100644 --- a/arch/x86/cpu/quark/quark.c +++ b/arch/x86/cpu/quark/quark.c @@ -16,11 +16,6 @@ #include <asm/arch/msg_port.h> #include <asm/arch/quark.h> -static struct pci_device_id mmc_supported[] = { - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_SDIO }, - {}, -}; - static void quark_setup_mtrr(void) { u32 base, mask; @@ -328,11 +323,6 @@ int arch_early_init_r(void) return 0; } -int cpu_mmc_init(bd_t *bis) -{ - return pci_mmc_init("Quark SDHCI", mmc_supported); -} - int arch_misc_init(void) { #ifdef CONFIG_ENABLE_MRC_CACHE diff --git a/arch/x86/cpu/queensbay/Kconfig b/arch/x86/cpu/queensbay/Kconfig index 6136d75422..835de85268 100644 --- a/arch/x86/cpu/queensbay/Kconfig +++ b/arch/x86/cpu/queensbay/Kconfig @@ -8,6 +8,21 @@ config INTEL_QUEENSBAY bool select HAVE_FSP select HAVE_CMC + select ARCH_EARLY_INIT_R + imply AHCI_PCI + imply ICH_SPI + imply INTEL_ICH6_GPIO + imply MMC + imply MMC_PCI + imply MMC_SDHCI + imply MMC_SDHCI_SDMA + imply PCH_GBE + imply SCSI + imply SPI_FLASH + imply SYS_NS16550 + imply USB + imply USB_EHCI_HCD + imply VIDEO_VESA if INTEL_QUEENSBAY diff --git a/arch/x86/cpu/queensbay/Makefile b/arch/x86/cpu/queensbay/Makefile index af3ffad385..c0681995bd 100644 --- a/arch/x86/cpu/queensbay/Makefile +++ b/arch/x86/cpu/queensbay/Makefile @@ -5,4 +5,4 @@ # obj-y += fsp_configs.o irq.o -obj-y += tnc.o topcliff.o +obj-y += tnc.o diff --git a/arch/x86/cpu/queensbay/topcliff.c b/arch/x86/cpu/queensbay/topcliff.c deleted file mode 100644 index b76dd7de69..0000000000 --- a/arch/x86/cpu/queensbay/topcliff.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <mmc.h> -#include <pci_ids.h> - -static struct pci_device_id mmc_supported[] = { - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_0 }, - { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_1 }, - {}, -}; - -int cpu_mmc_init(bd_t *bis) -{ - return pci_mmc_init("Topcliff SDHCI", mmc_supported); -} diff --git a/arch/x86/cpu/tangier/Kconfig b/arch/x86/cpu/tangier/Kconfig new file mode 100644 index 0000000000..86a334047c --- /dev/null +++ b/arch/x86/cpu/tangier/Kconfig @@ -0,0 +1,32 @@ +# +# Copyright (c) 2017 Intel Corporation +# +# SPDX-License-Identifier: GPL-2.0+ +# + +config INTEL_TANGIER + bool + depends on INTEL_MID + imply INTEL_MID_SERIAL + imply MMC + imply MMC_SDHCI + imply MMC_SDHCI_SDMA + imply MMC_SDHCI_TANGIER + imply TANGIER_WATCHDOG + imply USB + imply USB_DWC3 + +config SYS_CAR_ADDR + hex + default 0x19200000 + +config SYS_CAR_SIZE + hex + default 0x4000 + help + Space in bytes in eSRAM used as Cache-As-RAM (CAR). + Note this size must not exceed eSRAM's total size. + +config SYS_USB_OTG_BASE + hex + default 0xf9100000 diff --git a/arch/x86/cpu/tangier/Makefile b/arch/x86/cpu/tangier/Makefile new file mode 100644 index 0000000000..d146b3f5c2 --- /dev/null +++ b/arch/x86/cpu/tangier/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (c) 2017 Intel Corporation +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += car.o tangier.o sdram.o diff --git a/arch/x86/cpu/tangier/car.S b/arch/x86/cpu/tangier/car.S new file mode 100644 index 0000000000..6982106c19 --- /dev/null +++ b/arch/x86/cpu/tangier/car.S @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2010-2011 + * Graeme Russ, <graeme.russ@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +.section .text + +.globl car_init +car_init: + jmp car_init_ret diff --git a/arch/x86/cpu/tangier/sdram.c b/arch/x86/cpu/tangier/sdram.c new file mode 100644 index 0000000000..5743077431 --- /dev/null +++ b/arch/x86/cpu/tangier/sdram.c @@ -0,0 +1,206 @@ +/* + * Copyright (c) 2017 Intel Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/e820.h> +#include <asm/global_data.h> +#include <asm/sfi.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * SFI tables are part of the first stage bootloader. + * + * U-Boot finds the System Table by searching 16-byte boundaries between + * physical address 0x000E0000 and 0x000FFFFF. U-Boot shall search this region + * starting at the low address and shall stop searching when the 1st valid SFI + * System Table is found. + */ +#define SFI_BASE_ADDR 0x000E0000 +#define SFI_LENGTH 0x00020000 +#define SFI_TABLE_LENGTH 16 + +static int sfi_table_check(struct sfi_table_header *sbh) +{ + char chksum = 0; + char *pos = (char *)sbh; + u32 i; + + if (sbh->len < SFI_TABLE_LENGTH) + return -ENXIO; + + if (sbh->len > SFI_LENGTH) + return -ENXIO; + + for (i = 0; i < sbh->len; i++) + chksum += *pos++; + + if (chksum) + error("sfi: Invalid checksum\n"); + + /* Checksum is OK if zero */ + return chksum ? -EILSEQ : 0; +} + +static int sfi_table_is_type(struct sfi_table_header *sbh, const char *signature) +{ + return !strncmp(sbh->sig, signature, SFI_SIGNATURE_SIZE) && + !sfi_table_check(sbh); +} + +static struct sfi_table_simple *sfi_get_table_by_sig(unsigned long addr, + const char *signature) +{ + struct sfi_table_simple *sb; + u32 i; + + for (i = 0; i < SFI_LENGTH; i += SFI_TABLE_LENGTH) { + sb = (struct sfi_table_simple *)(addr + i); + if (sfi_table_is_type(&sb->header, signature)) + return sb; + } + + return NULL; +} + +static struct sfi_table_simple *sfi_search_mmap(void) +{ + struct sfi_table_header *sbh; + struct sfi_table_simple *sb; + u32 sys_entry_cnt; + u32 i; + + /* Find SYST table */ + sb = sfi_get_table_by_sig(SFI_BASE_ADDR, SFI_SIG_SYST); + if (!sb) { + error("sfi: failed to locate SYST table\n"); + return NULL; + } + + sys_entry_cnt = (sb->header.len - sizeof(*sbh)) / 8; + + /* Search through each SYST entry for MMAP table */ + for (i = 0; i < sys_entry_cnt; i++) { + sbh = (struct sfi_table_header *)(unsigned long)sb->pentry[i]; + + if (sfi_table_is_type(sbh, SFI_SIG_MMAP)) + return (struct sfi_table_simple *)sbh; + } + + error("sfi: failed to locate SFI MMAP table\n"); + return NULL; +} + +#define sfi_for_each_mentry(i, sb, mentry) \ + for (i = 0, mentry = (struct sfi_mem_entry *)sb->pentry; \ + i < SFI_GET_NUM_ENTRIES(sb, struct sfi_mem_entry); \ + i++, mentry++) \ + +static unsigned sfi_setup_e820(unsigned max_entries, struct e820entry *entries) +{ + struct sfi_table_simple *sb; + struct sfi_mem_entry *mentry; + unsigned long long start, end, size; + int type, total = 0; + u32 i; + + sb = sfi_search_mmap(); + if (!sb) + return 0; + + sfi_for_each_mentry(i, sb, mentry) { + start = mentry->phys_start; + size = mentry->pages << 12; + end = start + size; + + if (start > end) + continue; + + /* translate SFI mmap type to E820 map type */ + switch (mentry->type) { + case SFI_MEM_CONV: + type = E820_RAM; + break; + case SFI_MEM_UNUSABLE: + case SFI_RUNTIME_SERVICE_DATA: + continue; + default: + type = E820_RESERVED; + } + + if (total == E820MAX) + break; + entries[total].addr = start; + entries[total].size = size; + entries[total].type = type; + + total++; + } + + return total; +} + +static int sfi_get_bank_size(void) +{ + struct sfi_table_simple *sb; + struct sfi_mem_entry *mentry; + int bank = 0; + u32 i; + + sb = sfi_search_mmap(); + if (!sb) + return 0; + + sfi_for_each_mentry(i, sb, mentry) { + if (mentry->type != SFI_MEM_CONV) + continue; + + gd->bd->bi_dram[bank].start = mentry->phys_start; + gd->bd->bi_dram[bank].size = mentry->pages << 12; + bank++; + } + + return bank; +} + +static phys_size_t sfi_get_ram_size(void) +{ + struct sfi_table_simple *sb; + struct sfi_mem_entry *mentry; + phys_size_t ram = 0; + u32 i; + + sb = sfi_search_mmap(); + if (!sb) + return 0; + + sfi_for_each_mentry(i, sb, mentry) { + if (mentry->type != SFI_MEM_CONV) + continue; + + ram += mentry->pages << 12; + } + + debug("sfi: RAM size %llu\n", ram); + return ram; +} + +unsigned install_e820_map(unsigned max_entries, struct e820entry *entries) +{ + return sfi_setup_e820(max_entries, entries); +} + +int dram_init_banksize(void) +{ + sfi_get_bank_size(); + return 0; +} + +int dram_init(void) +{ + gd->ram_size = sfi_get_ram_size(); + return 0; +} diff --git a/arch/x86/cpu/tangier/tangier.c b/arch/x86/cpu/tangier/tangier.c new file mode 100644 index 0000000000..20d6c6039b --- /dev/null +++ b/arch/x86/cpu/tangier/tangier.c @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2017 Intel Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/scu.h> +#include <asm/u-boot-x86.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Miscellaneous platform dependent initializations + */ +int arch_cpu_init(void) +{ + return x86_cpu_init_f(); +} + +int checkcpu(void) +{ + return 0; +} + +int print_cpuinfo(void) +{ + return default_print_cpuinfo(); +} + +void reset_cpu(ulong addr) +{ + scu_ipc_simple_command(IPCMSG_COLD_RESET, 0); +} diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile index 3f534ad40a..6589495f23 100644 --- a/arch/x86/dts/Makefile +++ b/arch/x86/dts/Makefile @@ -10,6 +10,7 @@ dtb-y += bayleybay.dtb \ cougarcanyon2.dtb \ crownbay.dtb \ dfi-bt700-q7x-151.dtb \ + edison.dtb \ efi.dtb \ galileo.dtb \ minnowmax.dtb \ diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts index ae11ccc25a..9c068709ee 100644 --- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts +++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts @@ -258,6 +258,9 @@ fsp,enable-spi; fsp,enable-sata; fsp,sata-mode = <SATA_MODE_AHCI>; +#ifdef CONFIG_USB_XHCI_HCD + fsp,enable-xhci; +#endif fsp,lpe-mode = <LPE_MODE_PCI>; fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>; fsp,enable-dma0; diff --git a/arch/x86/dts/dfi-bt700.dtsi b/arch/x86/dts/dfi-bt700.dtsi index 04aa95ad52..b62e00ff1f 100644 --- a/arch/x86/dts/dfi-bt700.dtsi +++ b/arch/x86/dts/dfi-bt700.dtsi @@ -47,6 +47,15 @@ pad-offset = <0x3a0>; mode-func = <1>; }; + + xhci_hub_reset: usb_ulpi_stp@0 { + gpio-offset = <0xa0 10>; + pad-offset = <0x23b0>; + mode-func = <0>; + mode-gpio; + output-value = <1>; + direction = <PIN_OUTPUT>; + }; }; chosen { @@ -261,6 +270,9 @@ fsp,enable-spi; fsp,enable-sata; fsp,sata-mode = <SATA_MODE_AHCI>; +#ifdef CONFIG_USB_XHCI_HCD + fsp,enable-xhci; +#endif fsp,lpe-mode = <LPE_MODE_PCI>; fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>; fsp,enable-dma0; diff --git a/arch/x86/dts/edison.dts b/arch/x86/dts/edison.dts new file mode 100644 index 0000000000..0b04984c6e --- /dev/null +++ b/arch/x86/dts/edison.dts @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2017 Intel Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include <dt-bindings/gpio/x86-gpio.h> +#include <dt-bindings/interrupt-router/intel-irq.h> + +/include/ "skeleton.dtsi" +/include/ "rtc.dtsi" +/include/ "tsc_timer.dtsi" + +/ { + model = "Intel Edison"; + compatible = "intel,edison"; + + aliases { + serial0 = &serial0; + }; + + chosen { + stdout-path = &serial0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "cpu-x86"; + reg = <0>; + intel,apic-id = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "cpu-x86"; + reg = <1>; + intel,apic-id = <2>; + }; + }; + + pci { + compatible = "pci-x86"; + #address-cells = <3>; + #size-cells = <2>; + u-boot,dm-pre-reloc; + ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000 + 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 + 0x01000000 0x0 0x2000 0x2000 0 0xe000>; + }; + + serial0: serial@ff010180 { + compatible = "intel,mid-uart"; + reg = <0xff010180 0x100>; + reg-shift = <0>; + clock-frequency = <29491200>; + current-speed = <115200>; + }; + + emmc: mmc@ff3fc000 { + compatible = "intel,sdhci-tangier"; + reg = <0xff3fc000 0x1000>; + }; + +/* + * FIXME: For now U-Boot DM model doesn't allow to power up this controller. + * Enabling it will make U-Boot hang. + * + sdcard: mmc@ff3fa000 { + compatible = "intel,sdhci-tangier"; + reg = <0xff3fa000 0x1000>; + }; + */ + + pmu: power@ff00b000 { + compatible = "intel,pmu-mid"; + reg = <0xff00b000 0x1000>; + }; + + scu: ipc@ff009000 { + compatible = "intel,scu-ipc"; + reg = <0xff009000 0x1000>; + }; +}; diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index 4c0a8fe26f..a0ad03ce23 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -272,6 +272,9 @@ fsp,enable-spi; fsp,enable-sata; fsp,sata-mode = <SATA_MODE_AHCI>; +#ifdef CONFIG_USB_XHCI_HCD + fsp,enable-xhci; +#endif fsp,lpe-mode = <LPE_MODE_PCI>; fsp,lpss-sio-mode = <LPSS_SIO_MODE_PCI>; fsp,enable-dma0; diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h index dd7a946b6c..80038504dd 100644 --- a/arch/x86/include/asm/acpi_table.h +++ b/arch/x86/include/asm/acpi_table.h @@ -178,9 +178,8 @@ struct __packed acpi_fadt { u32 flags; struct acpi_gen_regaddr reset_reg; u8 reset_value; - u8 res3; - u8 res4; - u8 res5; + u16 arm_boot_arch; + u8 minor_revision; u32 x_firmware_ctl_l; u32 x_firmware_ctl_h; u32 x_dsdt_l; @@ -315,6 +314,9 @@ int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride, int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi, u8 cpu, u16 flags, u8 lint); u32 acpi_fill_madt(u32 current); +int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig, u32 base, + u16 seg_nr, u8 start, u8 end); +u32 acpi_fill_mcfg(u32 current); void acpi_create_gnvs(struct acpi_global_nvs *gnvs); /** * enter_acpi_mode() - enter into ACPI mode diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h index c00687a20a..bc2c4ffd9f 100644 --- a/arch/x86/include/asm/cpu.h +++ b/arch/x86/include/asm/cpu.h @@ -288,16 +288,4 @@ u32 cpu_get_family_model(void); */ u32 cpu_get_stepping(void); -/** - * cpu_run_reference_code() - Run the platform reference code - * - * Some platforms require a binary blob to be executed once SDRAM is - * available. This is used to set up various platform features, such as the - * platform controller hub (PCH). This function should be implemented by the - * CPU-specific code. - * - * @return 0 on success, -ve on failure - */ -int cpu_run_reference_code(void); - #endif diff --git a/arch/x86/include/asm/dma-mapping.h b/arch/x86/include/asm/dma-mapping.h new file mode 100644 index 0000000000..7de4c08e36 --- /dev/null +++ b/arch/x86/include/asm/dma-mapping.h @@ -0,0 +1,41 @@ +/* + * (C) Copyright 2007 + * Stelian Pop <stelian@popies.net> + * Lead Tech Design <www.leadtechdesign.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __ASM_X86_DMA_MAPPING_H +#define __ASM_X86_DMA_MAPPING_H + +#define dma_mapping_error(x, y) 0 + +enum dma_data_direction { + DMA_BIDIRECTIONAL = 0, + DMA_TO_DEVICE = 1, + DMA_FROM_DEVICE = 2, +}; + +static inline void *dma_alloc_coherent(size_t len, unsigned long *handle) +{ + *handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len); + return (void *)*handle; +} + +static inline void dma_free_coherent(void *addr) +{ + free(addr); +} + +static inline unsigned long dma_map_single(volatile void *vaddr, size_t len, + enum dma_data_direction dir) +{ + return (unsigned long)vaddr; +} + +static inline void dma_unmap_single(volatile void *vaddr, size_t len, + unsigned long paddr) +{ +} + +#endif /* __ASM_X86_DMA_MAPPING_H */ diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h index 3156781dd3..a72daf2263 100644 --- a/arch/x86/include/asm/io.h +++ b/arch/x86/include/asm/io.h @@ -1,3 +1,10 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + #ifndef _ASM_IO_H #define _ASM_IO_H @@ -118,71 +125,6 @@ #define setbits_8(addr, set) setbits(8, addr, set) #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) -/* - * ISA space is 'always mapped' on a typical x86 system, no need to - * explicitly ioremap() it. The fact that the ISA IO space is mapped - * to PAGE_OFFSET is pure coincidence - it does not mean ISA values - * are physical addresses. The following constant pointer can be - * used as the IO-area pointer (it can be iounmapped as well, so the - * analogy with PCI is quite large): - */ -#define isa_readb(a) readb((a)) -#define isa_readw(a) readw((a)) -#define isa_readl(a) readl((a)) -#define isa_writeb(b,a) writeb(b,(a)) -#define isa_writew(w,a) writew(w,(a)) -#define isa_writel(l,a) writel(l,(a)) -#define isa_memset_io(a,b,c) memset_io((a),(b),(c)) -#define isa_memcpy_fromio(a,b,c) memcpy_fromio((a),(b),(c)) -#define isa_memcpy_toio(a,b,c) memcpy_toio((a),(b),(c)) - - -static inline int check_signature(unsigned long io_addr, - const unsigned char *signature, int length) -{ - int retval = 0; - do { - if (readb(io_addr) != *signature) - goto out; - io_addr++; - signature++; - length--; - } while (length); - retval = 1; -out: - return retval; -} - -/** - * isa_check_signature - find BIOS signatures - * @io_addr: mmio address to check - * @signature: signature block - * @length: length of signature - * - * Perform a signature comparison with the ISA mmio address io_addr. - * Returns 1 on a match. - * - * This function is deprecated. New drivers should use ioremap and - * check_signature. - */ - - -static inline int isa_check_signature(unsigned long io_addr, - const unsigned char *signature, int length) -{ - int retval = 0; - do { - if (isa_readb(io_addr) != *signature) - goto out; - io_addr++; - signature++; - length--; - } while (length); - retval = 1; -out: - return retval; -} - #endif /* __KERNEL__ */ #ifdef SLOW_IO_BY_JUMPING @@ -325,4 +267,4 @@ static inline phys_addr_t virt_to_phys(void * vaddr) #define __iormb() dmb() #define __iowmb() dmb() -#endif +#endif /* _ASM_IO_H */ diff --git a/arch/x86/include/asm/sfi.h b/arch/x86/include/asm/sfi.h index d6c44c978a..6c6ebeade8 100644 --- a/arch/x86/include/asm/sfi.h +++ b/arch/x86/include/asm/sfi.h @@ -60,6 +60,25 @@ struct __packed sfi_mem_entry { u64 attrib; }; +/* Memory type definitions */ +enum sfi_mem_type { + SFI_MEM_RESERVED, + SFI_LOADER_CODE, + SFI_LOADER_DATA, + SFI_BOOT_SERVICE_CODE, + SFI_BOOT_SERVICE_DATA, + SFI_RUNTIME_SERVICE_CODE, + SFI_RUNTIME_SERVICE_DATA, + SFI_MEM_CONV, + SFI_MEM_UNUSABLE, + SFI_ACPI_RECLAIM, + SFI_ACPI_NVS, + SFI_MEM_MMIO, + SFI_MEM_IOPORT, + SFI_PAL_CODE, + SFI_MEM_TYPEMAX, +}; + struct __packed sfi_cpu_table_entry { u32 apic_id; }; diff --git a/arch/x86/include/asm/tables.h b/arch/x86/include/asm/tables.h index 9e8208ba2b..c784a2aeec 100644 --- a/arch/x86/include/asm/tables.h +++ b/arch/x86/include/asm/tables.h @@ -9,13 +9,8 @@ #include <tables_csum.h> -/* - * All x86 tables happen to like the address range from 0xf0000 to 0x100000. - * We use 0xf0000 as the starting address to store those tables, including - * PIRQ routing table, Multi-Processor table and ACPI table. - */ -#define ROM_TABLE_ADDR 0xf0000 -#define ROM_TABLE_END 0xfffff +#define ROM_TABLE_ADDR CONFIG_ROM_TABLE_ADDR +#define ROM_TABLE_END (CONFIG_ROM_TABLE_ADDR + CONFIG_ROM_TABLE_SIZE - 1) #define ROM_TABLE_ALIGN 1024 diff --git a/arch/x86/lib/acpi_s3.c b/arch/x86/lib/acpi_s3.c index 3175da828b..182379b439 100644 --- a/arch/x86/lib/acpi_s3.c +++ b/arch/x86/lib/acpi_s3.c @@ -8,6 +8,7 @@ #include <asm/acpi_s3.h> #include <asm/acpi_table.h> #include <asm/post.h> +#include <linux/linkage.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index 01d5b6fff0..3eb101105b 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -11,10 +11,13 @@ #include <cpu.h> #include <dm.h> #include <dm/uclass-internal.h> +#include <version.h> #include <asm/acpi/global_nvs.h> #include <asm/acpi_table.h> #include <asm/io.h> +#include <asm/ioapic.h> #include <asm/lapic.h> +#include <asm/mpspec.h> #include <asm/tables.h> #include <asm/arch/global_nvs.h> @@ -60,6 +63,7 @@ void acpi_fill_header(struct acpi_table_header *header, char *signature) memcpy(header->signature, signature, 4); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, OEM_TABLE_ID, 8); + header->oem_revision = U_BOOT_BUILD_DATE; memcpy(header->aslc_id, ASLC_ID, 4); } @@ -239,6 +243,33 @@ int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi, return lapic_nmi->length; } +static int acpi_create_madt_irq_overrides(u32 current) +{ + struct acpi_madt_irqoverride *irqovr; + u16 sci_flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH; + int length = 0; + + irqovr = (void *)current; + length += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0); + + irqovr = (void *)(current + length); + length += acpi_create_madt_irqoverride(irqovr, 0, 9, 9, sci_flags); + + return length; +} + +__weak u32 acpi_fill_madt(u32 current) +{ + current += acpi_create_madt_lapics(current); + + current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current, + io_apic_read(IO_APIC_ID) >> 24, IO_APIC_ADDR, 0); + + current += acpi_create_madt_irq_overrides(current); + + return current; +} + static void acpi_create_madt(struct acpi_madt *madt) { struct acpi_table_header *header = &(madt->header); @@ -262,8 +293,8 @@ static void acpi_create_madt(struct acpi_madt *madt) header->checksum = table_compute_checksum((void *)madt, header->length); } -static int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig, - u32 base, u16 seg_nr, u8 start, u8 end) +int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig, u32 base, + u16 seg_nr, u8 start, u8 end) { memset(mmconfig, 0, sizeof(*mmconfig)); mmconfig->base_address_l = base; @@ -275,7 +306,7 @@ static int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig, return sizeof(struct acpi_mcfg_mmconfig); } -static u32 acpi_fill_mcfg(u32 current) +__weak u32 acpi_fill_mcfg(u32 current) { current += acpi_create_mcfg_mmconfig ((struct acpi_mcfg_mmconfig *)current, @@ -432,6 +463,10 @@ ulong write_acpi_tables(ulong start) debug("ACPI: done\n"); + /* Don't touch ACPI hardware on HW reduced platforms */ + if (fadt->flags & ACPI_FADT_HW_REDUCED_ACPI) + return current; + /* * Other than waiting for OSPM to request us to switch to ACPI mode, * do it by ourselves, since SMI will not be triggered. diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c index aafbeb01f9..00172dc7c1 100644 --- a/arch/x86/lib/zimage.c +++ b/arch/x86/lib/zimage.c @@ -48,15 +48,15 @@ static void build_command_line(char *command_line, int auto_boot) command_line[0] = '\0'; - env_command_line = getenv("bootargs"); + env_command_line = env_get("bootargs"); /* set console= argument if we use a serial console */ if (!strstr(env_command_line, "console=")) { - if (!strcmp(getenv("stdout"), "serial")) { + if (!strcmp(env_get("stdout"), "serial")) { /* We seem to use serial console */ sprintf(command_line, "console=ttyS0,%s ", - getenv("baudrate")); + env_get("baudrate")); } } @@ -285,7 +285,7 @@ int do_zboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) /* argv[1] holds the address of the bzImage */ s = argv[1]; } else { - s = getenv("fileaddr"); + s = env_get("fileaddr"); } if (s) diff --git a/arch/xtensa/lib/bootm.c b/arch/xtensa/lib/bootm.c index 1604bb9536..16961acba5 100644 --- a/arch/xtensa/lib/bootm.c +++ b/arch/xtensa/lib/bootm.c @@ -136,7 +136,7 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) { struct bp_tag *params, *params_start; ulong initrd_start, initrd_end; - char *commandline = getenv("bootargs"); + char *commandline = env_get("bootargs"); if (!(flag & (BOOTM_STATE_OS_GO | BOOTM_STATE_OS_FAKE_GO))) return 0; |