diff options
Diffstat (limited to 'arch')
69 files changed, 2149 insertions, 97 deletions
diff --git a/arch/arc/include/asm/global_data.h b/arch/arc/include/asm/global_data.h index 8f9c83d3c2..e35a26f1eb 100644 --- a/arch/arc/include/asm/global_data.h +++ b/arch/arc/include/asm/global_data.h @@ -6,8 +6,6 @@ #ifndef __ASM_ARC_GLOBAL_DATA_H #define __ASM_ARC_GLOBAL_DATA_H -#include <config.h> - #ifndef __ASSEMBLY__ /* Architecture-specific global data */ struct arch_global_data { diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 31d687ea01..0448787b8b 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1491,6 +1491,24 @@ config TARGET_PG_WCOM_SELI8 SELI8 is a QorIQ LS1021a based service unit card used in XMC20 and FOX615 product families. +config TARGET_PG_WCOM_EXPU1 + bool "Support Hitachi-Powergrids EXPU1 service unit card" + select ARCH_LS1021A + select ARCH_SUPPORT_PSCI + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + select CPU_V7A + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT + select SYS_FSL_DDR + select FSL_DDR_INTERACTIVE + select VENDOR_KM + imply SCSI + help + Support for Hitachi-Powergrids EXPU1 service unit card. + EXPU1 is a QorIQ LS1021a based service unit card used + in XMC20 and FOX615 product families. + config TARGET_LS1021ATSN bool "Support ls1021atsn" select ARCH_LS1021A @@ -2008,6 +2026,7 @@ source "board/hisilicon/poplar/Kconfig" source "board/isee/igep003x/Kconfig" source "board/kontron/sl28/Kconfig" source "board/myir/mys_6ulx/Kconfig" +source "board/seeed/npi_imx6ull/Kconfig" source "board/spear/spear300/Kconfig" source "board/spear/spear310/Kconfig" source "board/spear/spear320/Kconfig" diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 9d1ba4c771..9c58f69dbd 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -223,7 +223,9 @@ config ARCH_LX2162A select SYS_FSL_DDR_VER_50 select SYS_FSL_EC1 select SYS_FSL_EC2 - select SYS_FSL_ERRATUM_A050106 + select SYS_FSL_ERRATUM_A050204 + select SYS_FSL_ERRATUM_A011334 + select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND select SYS_FSL_HAS_RGMII select SYS_FSL_HAS_SEC select SYS_FSL_HAS_CCN508 @@ -253,7 +255,9 @@ config ARCH_LX2160A select SYS_FSL_DDR_VER_50 select SYS_FSL_EC1 select SYS_FSL_EC2 - select SYS_FSL_ERRATUM_A050106 + select SYS_FSL_ERRATUM_A050204 + select SYS_FSL_ERRATUM_A011334 + select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND select SYS_FSL_HAS_RGMII select SYS_FSL_HAS_SEC select SYS_FSL_HAS_CCN508 @@ -371,8 +375,8 @@ config SYS_FSL_ERRATUM_A009008 config SYS_FSL_ERRATUM_A009798 bool "Workaround for USB PHY erratum A009798" -config SYS_FSL_ERRATUM_A050106 - bool "Workaround for USB PHY erratum A050106" +config SYS_FSL_ERRATUM_A050204 + bool "Workaround for USB PHY erratum A050204" help USB3.0 Receiver needs to enable fixed equalization for each of PHY instances in an SOC. This is similar diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 270a72e550..d0103fc881 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1063,7 +1063,7 @@ int cpu_eth_init(struct bd_info *bis) return error; } -static inline int check_psci(void) +int check_psci(void) { unsigned int psci_ver; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.h b/arch/arm/cpu/armv8/fsl-layerscape/cpu.h index dca5fd0f7d..45da95831e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.h +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.h @@ -6,3 +6,4 @@ int fsl_qoriq_core_to_cluster(unsigned int core); u32 initiator_type(u32 cluster, int init_id); u32 cpu_mask(void); +int check_psci(void); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 7f29aa4725..f1624ff30a 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014-2015 Freescale Semiconductor, Inc. - * Copyright 2020 NXP + * Copyright 2020-2021 NXP */ #include <common.h> @@ -478,6 +478,151 @@ static bool crypto_is_disabled(unsigned int svr) return false; } +#ifdef CONFIG_FSL_PFE +void pfe_set_firmware_in_fdt(void *blob, int pfenode, void *pfw, char *pename, + unsigned int len) +{ + int rc, fwnode; + unsigned int phandle; + char subnode_str[32], prop_str[32], phandle_str[32], s[64]; + + sprintf(subnode_str, "pfe-%s-firmware", pename); + sprintf(prop_str, "fsl,pfe-%s-firmware", pename); + sprintf(phandle_str, "fsl,%s-firmware", pename); + + /*Add PE FW to fdt.*/ + /* Increase the size of the fdt to make room for the node. */ + rc = fdt_increase_size(blob, len); + if (rc < 0) { + printf("Unable to make room for %s firmware: %s\n", pename, + fdt_strerror(rc)); + return; + } + + /* Create the firmware node. */ + fwnode = fdt_add_subnode(blob, pfenode, subnode_str); + if (fwnode < 0) { + fdt_get_path(blob, pfenode, s, sizeof(s)); + printf("Could not add firmware node to %s: %s\n", s, + fdt_strerror(fwnode)); + return; + } + + rc = fdt_setprop_string(blob, fwnode, "compatible", prop_str); + if (rc < 0) { + fdt_get_path(blob, fwnode, s, sizeof(s)); + printf("Could not add compatible property to node %s: %s\n", s, + fdt_strerror(rc)); + return; + } + + rc = fdt_setprop_u32(blob, fwnode, "length", len); + if (rc < 0) { + fdt_get_path(blob, fwnode, s, sizeof(s)); + printf("Could not add compatible property to node %s: %s\n", s, + fdt_strerror(rc)); + return; + } + + /*create phandle and set the property*/ + phandle = fdt_create_phandle(blob, fwnode); + if (!phandle) { + fdt_get_path(blob, fwnode, s, sizeof(s)); + printf("Could not add phandle property to node %s: %s\n", s, + fdt_strerror(rc)); + return; + } + + rc = fdt_setprop(blob, fwnode, phandle_str, pfw, len); + if (rc < 0) { + fdt_get_path(blob, fwnode, s, sizeof(s)); + printf("Could not add firmware property to node %s: %s\n", s, + fdt_strerror(rc)); + return; + } +} + +void fdt_fixup_pfe_firmware(void *blob) +{ + int pfenode; + unsigned int len_class = 0, len_tmu = 0, len_util = 0; + const char *p; + void *pclassfw, *ptmufw, *putilfw; + + /* The first PFE we find, will contain the actual firmware. */ + pfenode = fdt_node_offset_by_compatible(blob, -1, "fsl,pfe"); + if (pfenode < 0) + /* Exit silently if there are no PFE devices */ + return; + + /* If we already have a firmware node, then also exit silently. */ + if (fdt_node_offset_by_compatible(blob, -1, + "fsl,pfe-class-firmware") > 0) + return; + + /* If the environment variable is not set, then exit silently */ + p = env_get("class_elf_firmware"); + if (!p) + return; + + pclassfw = (void *)simple_strtoul(p, NULL, 16); + if (!pclassfw) + return; + + p = env_get("class_elf_size"); + if (!p) + return; + len_class = simple_strtoul(p, NULL, 16); + + /* If the environment variable is not set, then exit silently */ + p = env_get("tmu_elf_firmware"); + if (!p) + return; + + ptmufw = (void *)simple_strtoul(p, NULL, 16); + if (!ptmufw) + return; + + p = env_get("tmu_elf_size"); + if (!p) + return; + len_tmu = simple_strtoul(p, NULL, 16); + + if (len_class == 0 || len_tmu == 0) { + printf("PFE FW corrupted. CLASS FW size %d, TMU FW size %d\n", + len_class, len_tmu); + return; + } + + /*Add CLASS FW to fdt.*/ + pfe_set_firmware_in_fdt(blob, pfenode, pclassfw, "class", len_class); + + /*Add TMU FW to fdt.*/ + pfe_set_firmware_in_fdt(blob, pfenode, ptmufw, "tmu", len_tmu); + + /* Util PE firmware is handled separately as it is not a usual case*/ + p = env_get("util_elf_firmware"); + if (!p) + return; + + putilfw = (void *)simple_strtoul(p, NULL, 16); + if (!putilfw) + return; + + p = env_get("util_elf_size"); + if (!p) + return; + len_util = simple_strtoul(p, NULL, 16); + + if (len_util) { + printf("PFE Util PE firmware is not added to FDT.\n"); + return; + } + + pfe_set_firmware_in_fdt(blob, pfenode, putilfw, "util", len_util); +} +#endif + void ft_cpu_setup(void *blob, struct bd_info *bd) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); @@ -534,6 +679,9 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) #ifdef CONFIG_SYS_DPAA_FMAN fdt_fixup_fman_firmware(blob); #endif +#ifdef CONFIG_FSL_PFE + fdt_fixup_pfe_firmware(blob); +#endif #ifndef CONFIG_ARCH_LS1012A fsl_fdt_disable_usb(blob); #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c index 5ac545f9df..730d7663d0 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c @@ -10,10 +10,12 @@ #include <asm/cache.h> #include <asm/global_data.h> #include <asm/io.h> +#include <asm/ptrace.h> #include <asm/system.h> #include <asm/arch/mp.h> #include <asm/arch/soc.h> #include <linux/delay.h> +#include <linux/psci.h> #include "cpu.h" #include <asm/arch-fsl-layerscape/soc.h> #include <efi_loader.h> @@ -301,24 +303,41 @@ int cpu_release(u32 nr, int argc, char *const argv[]) u64 *table = get_spin_tbl_addr(); int pos; - pos = core_to_pos(nr); - if (pos <= 0) - return -1; - - table += pos * WORDS_PER_SPIN_TABLE_ENTRY; boot_addr = simple_strtoull(argv[0], NULL, 16); - table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX] = boot_addr; - flush_dcache_range((unsigned long)table, + + if (check_psci()) { + /* SPIN Table is used */ + pos = core_to_pos(nr); + if (pos <= 0) + return -1; + + table += pos * WORDS_PER_SPIN_TABLE_ENTRY; + table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX] = boot_addr; + flush_dcache_range((unsigned long)table, (unsigned long)table + SPIN_TABLE_ELEM_SIZE); - asm volatile("dsb st"); + asm volatile("dsb st"); - /* - * The secondary CPUs polling the spin-table above for a non-zero - * value. To save power "wfe" is called. Thus call "sev" here to - * wake the CPUs and let them check the spin-table again (see - * slave_cpu loop in lowlevel.S) - */ - asm volatile("sev"); + /* + * The secondary CPUs polling the spin-table above for a non-zero + * value. To save power "wfe" is called. Thus call "sev" here to + * wake the CPUs and let them check the spin-table again (see + * slave_cpu loop in lowlevel.S) + */ + asm volatile("sev"); + } else { + /* Use PSCI to kick the core */ + struct pt_regs regs; + + printf("begin to kick cpu core #%d to address %llx\n", + nr, boot_addr); + regs.regs[0] = PSCI_0_2_FN64_CPU_ON; + regs.regs[1] = nr; + regs.regs[2] = boot_addr; + regs.regs[3] = 0; + smc_call(®s); + if (regs.regs[0]) + return -1; + } return 0; } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 7553b5bce2..c3cd6c7ac7 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014-2015 Freescale Semiconductor - * Copyright 2019-2020 NXP + * Copyright 2019-2021 NXP */ #include <common.h> @@ -218,7 +218,7 @@ static void erratum_a009007(void) } #if defined(CONFIG_FSL_LSCH3) -static void erratum_a050106(void) +static void erratum_a050204(void) { #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) void __iomem *dcsr = (void __iomem *)DCSR_BASE; @@ -378,7 +378,7 @@ void fsl_lsch3_early_init_f(void) erratum_a009798(); erratum_a008997(); erratum_a009007(); - erratum_a050106(); + erratum_a050204(); #ifdef CONFIG_CHAIN_OF_TRUST /* In case of Secure Boot, the IBR configures the SMMU * to allow only Secure transactions. diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9918e46633..f6fc9de4e2 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -414,6 +414,7 @@ dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \ ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \ ls1021a-iot-duart.dtb ls1021a-tsn.dtb dtb-$(CONFIG_TARGET_PG_WCOM_SELI8) += ls1021a-pg-wcom-seli8.dtb +dtb-$(CONFIG_TARGET_PG_WCOM_EXPU1) += ls1021a-pg-wcom-expu1.dtb dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ fsl-ls2080a-qds-42-x.dtb \ @@ -813,6 +814,7 @@ dtb-$(CONFIG_MX6ULL) += \ imx6ull-14x14-evk.dtb \ imx6ull-colibri.dtb \ imx6ull-myir-mys-6ulx-eval.dtb \ + imx6ull-seeed-npi-imx6ull-dev-board.dtb \ imx6ull-phytec-segin-ff-rdk-emmc.dtb \ imx6ull-dart-6ul.dtb \ imx6ull-somlabs-visionsom.dtb \ @@ -822,6 +824,12 @@ dtb-$(CONFIG_ARCH_MX6) += \ imx6-apalis.dtb \ imx6-colibri.dtb +dtb-$(CONFIG_O4_IMX_NANO) += \ + o4-imx-nano.dtb + +dtb-$(CONFIG_EV_IMX280_NANO_X_MB) += \ + ev-imx280-nano-x-mb.dtb + dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \ imx7d-sdb-qspi.dtb \ imx7-cm.dtb \ @@ -830,8 +838,8 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \ imx7s-warp.dtb \ imx7d-meerkat96.dtb \ imx7d-pico-pi.dtb \ - imx7d-pico-hobbit.dtb - + imx7d-pico-hobbit.dtb \ + imx7d-smegw01.dtb dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-com.dtb \ imx7ulp-evk.dtb @@ -839,6 +847,7 @@ dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-com.dtb \ dtb-$(CONFIG_ARCH_IMX8) += \ fsl-imx8qm-apalis.dtb \ fsl-imx8qm-mek.dtb \ + imx8qm-cgtqmx8.dtb \ imx8qm-rom7720-a1.dtb \ fsl-imx8qxp-ai_ml.dtb \ fsl-imx8qxp-colibri.dtb \ diff --git a/arch/arm/dts/armada-3720-turris-mox.dts b/arch/arm/dts/armada-3720-turris-mox.dts index 8e0ebf508d..f47ced05c5 100644 --- a/arch/arm/dts/armada-3720-turris-mox.dts +++ b/arch/arm/dts/armada-3720-turris-mox.dts @@ -11,6 +11,8 @@ /dts-v1/; #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> #include "armada-372x.dtsi" / { @@ -34,6 +36,28 @@ reg = <0x00000000 0x00000000 0x00000000 0x20000000>; }; + leds { + compatible = "gpio-leds"; + + led { + gpios = <&gpiosb 21 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_ACTIVITY; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + reset { + compatible = "gpio-keys"; + label = "reset"; + linux,code = <KEY_RESTART>; + gpios = <&gpiosb 20 GPIO_ACTIVE_LOW>; + debounce-interval = <60>; + }; + }; + reg_usb3_vbus: usb3_vbus@0 { compatible = "regulator-fixed"; regulator-name = "usb3-vbus"; @@ -140,6 +164,37 @@ reg = <0>; spi-max-frequency = <20000000>; m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "secure-firmware"; + reg = <0x0 0x20000>; + }; + + partition@20000 { + label = "a53-firmware"; + reg = <0x20000 0x160000>; + }; + + partition@180000 { + label = "u-boot-env"; + reg = <0x180000 0x10000>; + }; + + partition@190000 { + label = "Rescue system"; + reg = <0x190000 0x660000>; + }; + + partition@7f0000 { + label = "dtb"; + reg = <0x7f0000 0x10000>; + }; + }; }; moxtet@1 { diff --git a/arch/arm/dts/ev-imx280-nano-x-mb.dts b/arch/arm/dts/ev-imx280-nano-x-mb.dts new file mode 100644 index 0000000000..7aec076af3 --- /dev/null +++ b/arch/arm/dts/ev-imx280-nano-x-mb.dts @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (C) 2021 Oleh Kravchenko <oleg@kaa.org.ua> + +/dts-v1/; + +#include "o4-imx6ull-nano.dtsi" + +/ { + model = "EV-iMX280-NANO-X-MB"; + compatible = "evodbg,ev-imx280-nano-x-mb", + "out4,o4-imx6ull-nano", + "fsl,imx6ull"; + + aliases { + mmc1 = &usdhc1; + }; + + chosen { + stdout-path = &uart1; + }; +}; + +&iomuxc { + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10069 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 0x03029 + >; + }; + + pinctrl_mdio: mdiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0xb0b0 /* RST */ + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; +}; + +&uart1 { + pinctrl-0 = <&pinctrl_uart1>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usdhc1 { + bus-width = <4>; + no-1-8-v; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-names = "default"; + status = "okay"; + wakeup-source; +}; + +&fec1 { + phy-handle = <&phy0>; + phy-mode = "rmii"; + phy-reset-duration = <250>; + phy-reset-post-delay = <100>; + phy-reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_fec1 &pinctrl_mdio>; + pinctrl-names = "default"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + interrupt-parent = <&gpio5>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + pinctrl-0 = <&pinctrl_phy0_irq>; + pinctrl-names = "default"; + reg = <0>; + }; + }; +}; + +&usbotg1 { + dr_mode = "otg"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts index fe708bdbfa..33d85ed83a 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts @@ -41,8 +41,9 @@ qca,clk-out-frequency = <125000000>; qca,clk-out-strength = <AR803X_STRENGTH_FULL>; + qca,keep-pll-enabled; - vddio-supply = <&vddh>; + vddio-supply = <&vddio>; vddio: vddio-regulator { regulator-name = "VDDIO"; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts index 33b16303ad..b95e082b70 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts @@ -32,8 +32,9 @@ qca,clk-out-frequency = <125000000>; qca,clk-out-strength = <AR803X_STRENGTH_FULL>; + qca,keep-pll-enabled; - vddio-supply = <&vddh>; + vddio-supply = <&vddio>; vddio: vddio-regulator { regulator-name = "VDDIO"; diff --git a/arch/arm/dts/fsl-ls1028a-rdb.dts b/arch/arm/dts/fsl-ls1028a-rdb.dts index 3432fca352..82a8c0a0cd 100644 --- a/arch/arm/dts/fsl-ls1028a-rdb.dts +++ b/arch/arm/dts/fsl-ls1028a-rdb.dts @@ -15,12 +15,12 @@ compatible = "fsl,ls1028a-rdb", "fsl,ls1028a"; aliases { spi0 = &fspi; - eth0 = &enetc0; - eth1 = &enetc2; - eth2 = &mscc_felix_port0; - eth3 = &mscc_felix_port1; - eth4 = &mscc_felix_port2; - eth5 = &mscc_felix_port3; + ethernet0 = &enetc0; + ethernet1 = &enetc2; + ethernet2 = &mscc_felix_port0; + ethernet3 = &mscc_felix_port1; + ethernet4 = &mscc_felix_port2; + ethernet5 = &mscc_felix_port3; }; }; diff --git a/arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi b/arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi index 60f5a4ee43..d1e4a8567f 100644 --- a/arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi +++ b/arch/arm/dts/fsl-lx2162a-qds-sd1-17.dtsi @@ -5,7 +5,7 @@ * Some assumptions are made: * * mezzanine card M8 is connected to IO SLOT1 (25g-aui for DPMAC 3,4,5,6) * - * Copyright 2020 NXP + * Copyright 2020-2021 NXP * */ @@ -56,3 +56,9 @@ reg = <0x3>; }; }; + +&esdhc1 { + mmc-hs200-1_8v; + mmc-hs400-1_8v; + bus-width = <8>; +}; diff --git a/arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi b/arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi index 8e11b0680a..e9a743b3a2 100644 --- a/arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi +++ b/arch/arm/dts/fsl-lx2162a-qds-sd1-18.dtsi @@ -6,7 +6,7 @@ * * mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC 3,4) * * mezzanine card M13/M8 is connected to IO SLOT6 (25g-aui for DPMAC 5,6) * - * Copyright 2020 NXP + * Copyright 2020-2021 NXP * */ @@ -59,3 +59,9 @@ reg = <0x1>; }; }; + +&esdhc1 { + mmc-hs200-1_8v; + mmc-hs400-1_8v; + bus-width = <8>; +}; diff --git a/arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi b/arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi index faf4285eab..d9ad1c6a4b 100644 --- a/arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi +++ b/arch/arm/dts/fsl-lx2162a-qds-sd1-20.dtsi @@ -6,7 +6,7 @@ * * Mezzanine card M8 is connected to IO SLOT1 * (xlaui4 for DPMAC 1) * - * Copyright 2020 NXP + * Copyright 2020-2021 NXP * */ @@ -24,3 +24,9 @@ reg = <0x0>; }; }; + +&esdhc1 { + mmc-hs200-1_8v; + mmc-hs400-1_8v; + bus-width = <8>; +}; diff --git a/arch/arm/dts/fsl-lx2162a-qds.dts b/arch/arm/dts/fsl-lx2162a-qds.dts index 341610ccf4..0ca30df862 100644 --- a/arch/arm/dts/fsl-lx2162a-qds.dts +++ b/arch/arm/dts/fsl-lx2162a-qds.dts @@ -2,7 +2,7 @@ /* * NXP LX2162AQDS device tree source * - * Copyright 2020 NXP + * Copyright 2020-2021 NXP * */ @@ -135,3 +135,9 @@ reg = <2>; }; }; + +&esdhc1 { + mmc-hs200-1_8v; + mmc-hs400-1_8v; + bus-width = <8>; +}; diff --git a/arch/arm/dts/imx6qdl-gw51xx.dtsi b/arch/arm/dts/imx6qdl-gw51xx.dtsi index 2a21c6731e..7e28463084 100644 --- a/arch/arm/dts/imx6qdl-gw51xx.dtsi +++ b/arch/arm/dts/imx6qdl-gw51xx.dtsi @@ -129,6 +129,8 @@ pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <100>; status = "okay"; }; diff --git a/arch/arm/dts/imx6qdl-gw52xx.dtsi b/arch/arm/dts/imx6qdl-gw52xx.dtsi index 6eedf8d40d..f1d9ba1fac 100644 --- a/arch/arm/dts/imx6qdl-gw52xx.dtsi +++ b/arch/arm/dts/imx6qdl-gw52xx.dtsi @@ -195,6 +195,8 @@ pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <100>; status = "okay"; }; diff --git a/arch/arm/dts/imx6qdl-gw53xx.dtsi b/arch/arm/dts/imx6qdl-gw53xx.dtsi index 9deec7e352..172a45ba17 100644 --- a/arch/arm/dts/imx6qdl-gw53xx.dtsi +++ b/arch/arm/dts/imx6qdl-gw53xx.dtsi @@ -188,6 +188,8 @@ pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <100>; status = "okay"; }; @@ -597,6 +599,7 @@ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 >; }; diff --git a/arch/arm/dts/imx6qdl-gw54xx.dtsi b/arch/arm/dts/imx6qdl-gw54xx.dtsi index a30ba4848e..e09fad6068 100644 --- a/arch/arm/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/dts/imx6qdl-gw54xx.dtsi @@ -225,6 +225,8 @@ pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <100>; status = "okay"; }; @@ -675,6 +677,7 @@ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 >; }; diff --git a/arch/arm/dts/imx6qdl-gw560x.dtsi b/arch/arm/dts/imx6qdl-gw560x.dtsi index 0786b0d546..bfe65fd3c0 100644 --- a/arch/arm/dts/imx6qdl-gw560x.dtsi +++ b/arch/arm/dts/imx6qdl-gw560x.dtsi @@ -279,6 +279,8 @@ pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <100>; status = "okay"; }; diff --git a/arch/arm/dts/imx6qdl-gw5903.dtsi b/arch/arm/dts/imx6qdl-gw5903.dtsi index 78f9ec90b7..6ebf6aef2f 100644 --- a/arch/arm/dts/imx6qdl-gw5903.dtsi +++ b/arch/arm/dts/imx6qdl-gw5903.dtsi @@ -223,6 +223,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; + phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <100>; status = "okay"; }; diff --git a/arch/arm/dts/imx6qdl-gw5904.dtsi b/arch/arm/dts/imx6qdl-gw5904.dtsi index 5b7bd56932..9adbd728dc 100644 --- a/arch/arm/dts/imx6qdl-gw5904.dtsi +++ b/arch/arm/dts/imx6qdl-gw5904.dtsi @@ -200,6 +200,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; + phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <100>; status = "okay"; fixed-link { diff --git a/arch/arm/dts/imx6qdl-gw5907.dtsi b/arch/arm/dts/imx6qdl-gw5907.dtsi index c8b29246b7..58f73a141e 100644 --- a/arch/arm/dts/imx6qdl-gw5907.dtsi +++ b/arch/arm/dts/imx6qdl-gw5907.dtsi @@ -131,6 +131,8 @@ pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <100>; status = "okay"; }; diff --git a/arch/arm/dts/imx6qdl-gw5910.dtsi b/arch/arm/dts/imx6qdl-gw5910.dtsi index 248e077a56..446c1043a7 100644 --- a/arch/arm/dts/imx6qdl-gw5910.dtsi +++ b/arch/arm/dts/imx6qdl-gw5910.dtsi @@ -146,6 +146,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; + phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <100>; status = "okay"; }; diff --git a/arch/arm/dts/imx6qdl-gw5912.dtsi b/arch/arm/dts/imx6qdl-gw5912.dtsi index 7593872c07..88234a6f13 100644 --- a/arch/arm/dts/imx6qdl-gw5912.dtsi +++ b/arch/arm/dts/imx6qdl-gw5912.dtsi @@ -141,6 +141,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; + phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <100>; status = "okay"; }; @@ -426,6 +429,7 @@ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 >; }; diff --git a/arch/arm/dts/imx6qdl-gw5913.dtsi b/arch/arm/dts/imx6qdl-gw5913.dtsi index 9fae4cccd7..f4c2b2189f 100644 --- a/arch/arm/dts/imx6qdl-gw5913.dtsi +++ b/arch/arm/dts/imx6qdl-gw5913.dtsi @@ -121,6 +121,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; + phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; + phy-reset-duration = <10>; + phy-reset-post-delay = <100>; status = "okay"; }; diff --git a/arch/arm/dts/imx6ull-seeed-npi-imx6ull-dev-board.dts b/arch/arm/dts/imx6ull-seeed-npi-imx6ull-dev-board.dts new file mode 100644 index 0000000000..ce03ddfd21 --- /dev/null +++ b/arch/arm/dts/imx6ull-seeed-npi-imx6ull-dev-board.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 Linumiz + * Author: Navin Sankar Velliangiri <navin@linumiz.com> + */ + +/dts-v1/; +#include "imx6ull.dtsi" +#include "imx6ull-seeed-npi-imx6ull.dtsi" +#include "imx6ull-seeed-npi-imx6ull-u-boot.dtsi" + +/ { + model = "Seeed NPi iMX6ULL Dev Board with NAND"; + compatible = "seeed,imx6ull-seeed-npi-imx6ull", "fsl,imx6ull"; +}; + +&gpmi { + status = "okay"; +}; diff --git a/arch/arm/dts/imx6ull-seeed-npi-imx6ull-u-boot.dtsi b/arch/arm/dts/imx6ull-seeed-npi-imx6ull-u-boot.dtsi new file mode 100644 index 0000000000..054e1aa94b --- /dev/null +++ b/arch/arm/dts/imx6ull-seeed-npi-imx6ull-u-boot.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 Linumiz + * Author: Navin Sankar Velliangiri <navin@linumiz.com> + */ + +&pinctrl_uart1 { + u-boot,dm-pre-reloc; +}; + +&gpmi { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&usdhc1 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&usdhc2 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/imx6ull-seeed-npi-imx6ull.dtsi b/arch/arm/dts/imx6ull-seeed-npi-imx6ull.dtsi new file mode 100644 index 0000000000..b019474dba --- /dev/null +++ b/arch/arm/dts/imx6ull-seeed-npi-imx6ull.dtsi @@ -0,0 +1,271 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 Linumiz + * Author: Navin Sankar Velliangiri <navin@linumiz.com> + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pwm/pwm.h> + +/ { + model = "Seeed NPi-iMX6ULL Dev Board"; + compatible = "fsl,imx6ull"; + + chosen { + stdout-path = &uart1; + }; + + leds { + compatible = "gpio-leds"; + + user-led { + label = "User"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpios>; + gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + status = "disabled"; +}; + +&uart1 { + pinctrl-name = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + bus-width = <8>; + non-removable; + keep-power-in-suspend; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <2>; + micrel,led-mode = <1>; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + micrel,led-mode = <1>; + clocks = <&clks IMX6UL_CLK_ENET2_REF>; + clock-names = "rmii-ref"; + }; + }; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpios>; + + pinctrl_uart1: uart1grp { + fsl,pin = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pin = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6UL_PAD_NAND_DQS__RAWNAND_DQS 0x0b0b1 + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1 + MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0x0b0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + >; + }; + + pinctrl_gpios: gpiosgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0b0b0 + >; + }; +}; diff --git a/arch/arm/dts/imx7d-smegw01.dts b/arch/arm/dts/imx7d-smegw01.dts new file mode 100644 index 0000000000..aefc654ad8 --- /dev/null +++ b/arch/arm/dts/imx7d-smegw01.dts @@ -0,0 +1,190 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// +// Copyright (C) 2020 PHYTEC Messtechnik GmbH +// Author: Jens Lang <J.Lang@phytec.de> +// Copyright (C) 2021 Fabio Estevam <festevam@denx.de> + +/dts-v1/; +#include "imx7d.dtsi" + +/ { + model = "Storopack SMEGW01 board"; + compatible = "storopack,imx7d-smegw01", "fsl,imx7d"; + + aliases { + mmc0 = &usdhc1; + mmc1 = &usdhc3; + }; + + chosen { + stdout-path = &uart1; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + status = "okay"; + + mdio: mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + no-1-8-v; + enable-sdio-wakeup; + keep-power-in-suspend; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; + assigned-clock-rates = <400000000>; + max-frequency = <200000000>; + bus-width = <8>; + fsl,tuning-step = <1>; + non-removable; + cap-sd-highspeed; + cap-mmc-highspeed; + cap-mmc-hw-reset; + mmc-hs200-1_8v; + mmc-ddr-1_8v; + sd-uhs-ddr50; + sd-uhs-sdr104; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_enet1: enet1grp { + fsl,pins = < + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x5 + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x5 + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x5 + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x5 + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x5 + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x5 + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x5 + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x5 + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x5 + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x5 + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x5 + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x5 + MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x7 + MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x7 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x74 + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x7c + >; + }; + + pinctrl_usdhc1: usdhc1 { + fsl,pins = < + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + >; + }; + + pinctrl_usdhc3: usdhc3 { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5d + MX7D_PAD_SD3_CLK__SD3_CLK 0x1d + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5d + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5d + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5d + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5d + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5d + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5d + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5d + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5d + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1d + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3_100mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5e + MX7D_PAD_SD3_CLK__SD3_CLK 0x1e + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5e + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5e + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5e + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5e + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5e + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5e + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5e + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5e + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1e + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3_200mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5f + MX7D_PAD_SD3_CLK__SD3_CLK 0x0f + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5f + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5f + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5f + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5f + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5f + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5f + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5f + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5f + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1f + >; + }; +}; + +&iomuxc_lpsr { + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 + >; + }; +}; diff --git a/arch/arm/dts/imx8qm-cgtqmx8.dts b/arch/arm/dts/imx8qm-cgtqmx8.dts new file mode 100644 index 0000000000..555c357f6f --- /dev/null +++ b/arch/arm/dts/imx8qm-cgtqmx8.dts @@ -0,0 +1,404 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP + * Copyright 2017 congatec AG + * Copyright (C) 2019 Oliver Graute <oliver.graute@kococonnector.com> + */ + +/dts-v1/; + +/* First 128KB is for PSCI ATF. */ +/memreserve/ 0x80000000 0x00020000; + +#include "fsl-imx8qm.dtsi" + +/ { + model = "Congatec QMX8 Qseven series"; + compatible = "fsl,imx8qm-qmx8", "fsl,imx8qm"; + + chosen { + bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; + stdout-path = &lpuart0; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usdhc2_vmmc: usdhc2_vmmc { + compatible = "regulator-fixed"; + regulator-name = "sw-3p3-sd1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <3000>; + }; + + reg_usdhc3_vmmc: usdhc3_vmmc { + compatible = "regulator-fixed"; + regulator-name = "sw-3p3-sd2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <3000>; + }; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii"; + phy-handle = <ðphy0>; + fsl,magic-packet; + fsl,rgmii_txc_dly; + fsl,rgmii_rxc_dly; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@6 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <6>; + at803x,eee-disabled; + at803x,vddio-1p8v; + }; + }; +}; + +&gpio2 { + status = "okay"; +}; + +&gpio5 { + status = "okay"; +}; + +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + rtc_ext: m41t62@68 { + compatible = "st,m41t62"; + reg = <0x68>; + }; +}; + +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + status = "okay"; + + wm8904: wm8904@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + + clocks = <&clk IMX8QM_AUD_MCLKOUT0>; + clock-names = "mclk"; + wlf,shared-lrclk; + /* power-domains = <&pd_mclk_out0>; */ + + assigned-clocks = <&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QM_AUD_MCLKOUT0>; + + assigned-clock-rates = <786432000>, <49152000>, <24576000>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx8qm-qmx8 { + + pinctrl_hog: hoggrp{ + fsl,pins = < + SC_P_M40_GPIO0_01_LSIO_GPIO0_IO09 0x00000021 + SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x00000021 + SC_P_M40_GPIO0_00_LSIO_GPIO0_IO08 0x00000021 + SC_P_ESAI1_SCKT_LSIO_GPIO2_IO07 0x00000021 + SC_P_SPDIF0_TX_LSIO_GPIO2_IO15 0x00000021 + SC_P_FLEXCAN1_RX_LSIO_GPIO3_IO31 0x00000021 + SC_P_ESAI1_TX0_LSIO_GPIO2_IO08 0x00000021 + SC_P_FLEXCAN1_TX_LSIO_GPIO4_IO00 0x00000021 + SC_P_ESAI1_TX1_LSIO_GPIO2_IO09 0x00000021 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 + >; + }; + + pinctrl_lpi2c0: lpi2c0grp { + fsl,pins = < + SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0xc600004c + SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0xc600004c + >; + }; + + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + SC_P_GPT0_CLK_DMA_I2C1_SCL 0xc600004c + SC_P_GPT0_CAPTURE_DMA_I2C1_SDA 0xc600004c + >; + }; + + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_RX_DMA_UART0_RX 0x06000020 + SC_P_UART0_TX_DMA_UART0_TX 0x06000020 + >; + }; + + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + SC_P_UART1_RX_DMA_UART1_RX 0x06000020 + SC_P_UART1_TX_DMA_UART1_TX 0x06000020 + SC_P_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020 + SC_P_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020 + >; + }; + + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + SC_P_M41_GPIO0_00_DMA_UART3_RX 0x06000020 + SC_P_M41_GPIO0_01_DMA_UART3_TX 0x06000020 + >; + }; + + pinctrl_mlb: mlbgrp { + fsl,pins = < + SC_P_MLB_SIG_CONN_MLB_SIG 0x21 + SC_P_MLB_CLK_CONN_MLB_CLK 0x21 + SC_P_MLB_DATA_CONN_MLB_DATA 0x21 + >; + }; + + pinctrl_isl29023: isl29023grp { + fsl,pins = < + SC_P_ADC_IN2_LSIO_GPIO3_IO20 0x00000021 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2grpgpio { + fsl,pins = < + SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021 + SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021 + SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc3_gpio: usdhc3grpgpio { + fsl,pins = < + SC_P_USDHC2_RESET_B_LSIO_GPIO4_IO09 0x00000021 + SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021 + SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020 + SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020 + SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020 + >; + }; + }; +}; + +&lpuart0 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; + status = "okay"; +}; + +&lpuart1 { /* Q7 connector */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; + status = "okay"; +}; + +&pd_dma_lpuart0 { + debug_console; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + bus-width = <4>; + cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_usdhc2_vmmc>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>; + bus-width = <4>; + cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc3_vmmc>; + fsl,tuning-start-tap = <20>; + fsl,tuning-step= <2>; + status = "okay"; +}; diff --git a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi index d32c98de9c..121665a2d2 100644 --- a/arch/arm/dts/imxrt1020-evk-u-boot.dtsi +++ b/arch/arm/dts/imxrt1020-evk-u-boot.dtsi @@ -8,6 +8,42 @@ chosen { u-boot,dm-spl; }; + + clocks { + u-boot,dm-spl; + }; + + soc { + u-boot,dm-spl; + }; +}; + +&osc { + u-boot,dm-spl; +}; + +&clks { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&gpt1 { + u-boot,dm-spl; }; &lpuart1 { /* console */ @@ -15,6 +51,8 @@ }; &semc { + u-boot,dm-spl; + bank1: bank@0 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imxrt1020-evk.dts b/arch/arm/dts/imxrt1020-evk.dts index ece13601bd..2da79e5c20 100644 --- a/arch/arm/dts/imxrt1020-evk.dts +++ b/arch/arm/dts/imxrt1020-evk.dts @@ -16,9 +16,11 @@ chosen { bootargs = "root=/dev/ram"; stdout-path = "serial0:115200n8"; + tick-timer = &gpt1; }; memory { + device_type = "memory"; reg = <0x80000000 0x2000000>; }; }; @@ -186,6 +188,10 @@ }; }; +&gpt1 { + status = "okay"; +}; + &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; pinctrl-0 = <&pinctrl_usdhc0>; diff --git a/arch/arm/dts/imxrt1020.dtsi b/arch/arm/dts/imxrt1020.dtsi index 97f3cec9f3..5ba314f995 100644 --- a/arch/arm/dts/imxrt1020.dtsi +++ b/arch/arm/dts/imxrt1020.dtsi @@ -23,7 +23,6 @@ }; clocks { - u-boot,dm-spl; ckil { compatible = "fsl,imx-ckil", "fixed-clock"; #clock-cells = <0>; @@ -36,8 +35,7 @@ clock-frequency = <0>; }; - osc { - u-boot,dm-spl; + osc: osc { compatible = "fsl,imx-osc", "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; @@ -45,10 +43,7 @@ }; soc { - u-boot,dm-spl; - semc: semc@402f0000 { - u-boot,dm-spl; compatible = "fsl,imxrt-semc"; reg = <0x402f0000 0x4000>; clocks = <&clks IMXRT1020_CLK_SEMC>; @@ -73,7 +68,6 @@ }; clks: ccm@400fc000 { - u-boot,dm-spl; compatible = "fsl,imxrt1020-ccm"; reg = <0x400fc000 0x4000>; interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, @@ -82,7 +76,6 @@ }; usdhc1: usdhc@402c0000 { - u-boot,dm-spl; compatible = "fsl,imxrt-usdhc"; reg = <0x402c0000 0x10000>; interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; @@ -95,7 +88,6 @@ }; gpio1: gpio@401b8000 { - u-boot,dm-spl; compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; reg = <0x401b8000 0x4000>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, @@ -107,7 +99,6 @@ }; gpio2: gpio@401bc000 { - u-boot,dm-spl; compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; reg = <0x401bc000 0x4000>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, @@ -119,7 +110,6 @@ }; gpio3: gpio@401c0000 { - u-boot,dm-spl; compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; reg = <0x401c0000 0x4000>; interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, @@ -129,5 +119,24 @@ interrupt-controller; #interrupt-cells = <2>; }; + + gpio5: gpio@400c0000 { + compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; + reg = <0x400c0000 0x4000>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpt1: gpt1@401ec000 { + compatible = "fsl,imxrt-gpt"; + reg = <0x401ec000 0x4000>; + interrupts = <100>; + clocks = <&osc>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi index fb4f7f6f9d..3168c2df2c 100644 --- a/arch/arm/dts/imxrt1050-evk-u-boot.dtsi +++ b/arch/arm/dts/imxrt1050-evk-u-boot.dtsi @@ -8,6 +8,46 @@ chosen { u-boot,dm-spl; }; + + clocks { + u-boot,dm-spl; + }; + + soc { + u-boot,dm-spl; + }; +}; + +&osc { + u-boot,dm-spl; +}; + +&clks { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&gpt1 { + u-boot,dm-spl; }; &lpuart1 { /* console */ @@ -15,6 +55,8 @@ }; &semc { + u-boot,dm-spl; + bank1: bank@0 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/imxrt1050-evk.dts b/arch/arm/dts/imxrt1050-evk.dts index b5e781275e..324cf7af96 100644 --- a/arch/arm/dts/imxrt1050-evk.dts +++ b/arch/arm/dts/imxrt1050-evk.dts @@ -16,9 +16,11 @@ chosen { bootargs = "root=/dev/ram"; stdout-path = "serial0:115200n8"; + tick-timer = &gpt1; }; memory { + device_type = "memory"; reg = <0x80000000 0x2000000>; }; }; @@ -187,7 +189,6 @@ }; pinctrl_lcdif: lcdifgrp { - u-boot,dm-spl; fsl,pins = < MXRT1050_IOMUXC_GPIO_B0_00_LCD_CLK 0x1b0b1 MXRT1050_IOMUXC_GPIO_B0_01_LCD_ENABLE 0x1b0b1 @@ -215,6 +216,10 @@ }; }; +&gpt1 { + status = "okay"; +}; + &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; pinctrl-0 = <&pinctrl_usdhc0>; @@ -232,9 +237,6 @@ display = <&display0>; status = "okay"; - assigned-clocks = <&clks IMXRT1050_CLK_LCDIF_SEL>; - assigned-clock-parents = <&clks IMXRT1050_CLK_PLL5_VIDEO>; - display0: display0 { bits-per-pixel = <16>; bus-width = <16>; @@ -258,3 +260,8 @@ }; }; }; + +&usbotg1 { + dr_mode = "host"; + status = "okay"; +}; diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi index a9281001e5..6560a3827f 100644 --- a/arch/arm/dts/imxrt1050.dtsi +++ b/arch/arm/dts/imxrt1050.dtsi @@ -23,13 +23,11 @@ gpio4 = &gpio5; mmc0 = &usdhc1; serial0 = &lpuart1; + usbphy0 = &usbphy1; }; clocks { - u-boot,dm-spl; - - osc { - u-boot,dm-spl; + osc: osc { compatible = "fsl,imx-osc", "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; @@ -37,10 +35,7 @@ }; soc { - u-boot,dm-spl; - semc: semc@402f0000 { - u-boot,dm-spl; compatible = "fsl,imxrt-semc"; reg = <0x402f0000 0x4000>; clocks = <&clks IMXRT1050_CLK_SEMC>; @@ -65,7 +60,6 @@ }; clks: ccm@400fc000 { - u-boot,dm-spl; compatible = "fsl,imxrt1050-ccm"; reg = <0x400fc000 0x4000>; interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, @@ -74,7 +68,6 @@ }; usdhc1: usdhc@402c0000 { - u-boot,dm-spl; compatible = "fsl,imxrt-usdhc"; reg = <0x402c0000 0x10000>; interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; @@ -87,7 +80,6 @@ }; gpio1: gpio@401b8000 { - u-boot,dm-spl; compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; reg = <0x401b8000 0x4000>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, @@ -99,7 +91,6 @@ }; gpio2: gpio@401bc000 { - u-boot,dm-spl; compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; reg = <0x401bc000 0x4000>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, @@ -111,7 +102,6 @@ }; gpio3: gpio@401c0000 { - u-boot,dm-spl; compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; reg = <0x401c0000 0x4000>; interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, @@ -123,7 +113,6 @@ }; gpio4: gpio@401c4000 { - u-boot,dm-spl; compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; reg = <0x401c4000 0x4000>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, @@ -135,7 +124,6 @@ }; gpio5: gpio@400c0000 { - u-boot,dm-spl; compatible = "fsl,imxrt-gpio", "fsl,imx35-gpio"; reg = <0x400c0000 0x4000>; interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, @@ -150,8 +138,45 @@ compatible = "fsl,imxrt-lcdif"; reg = <0x402b8000 0x4000>; interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMXRT1050_CLK_LCDIF>; - clock-names = "per"; + clocks = <&clks IMXRT1050_CLK_LCDIF_PIX>, + <&clks IMXRT1050_CLK_LCDIF_APB>; + clock-names = "pix", "axi"; + assigned-clocks = <&clks IMXRT1050_CLK_LCDIF_SEL>; + assigned-clock-parents = <&clks IMXRT1050_CLK_PLL5_VIDEO>; + status = "disabled"; + }; + + gpt1: gpt1@401ec000 { + compatible = "fsl,imxrt-gpt"; + reg = <0x401ec000 0x4000>; + interrupts = <100>; + clocks = <&osc>; + status = "disabled"; + }; + + usbphy1: usbphy@400d9000 { + compatible = "fsl,imxrt-usbphy"; + reg = <0x400d9000 0x1000>; + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + }; + + usbmisc: usbmisc@402e0800 { + #index-cells = <1>; + compatible = "fsl,imxrt-usbmisc"; + reg = <0x402e0800 0x200>; + clocks = <&clks IMXRT1050_CLK_USBOH3>; + }; + + usbotg1: usb@402e0000 { + compatible = "fsl,imxrt-usb", "fsl,imx27-usb"; + reg = <0x402e0000 0x200>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMXRT1050_CLK_USBOH3>; + fsl,usbphy = <&usbphy1>; + fsl,usbmisc = <&usbmisc 0>; + ahb-burst-config = <0x0>; + tx-burst-size-dword = <0x10>; + rx-burst-size-dword = <0x10>; status = "disabled"; }; }; diff --git a/arch/arm/dts/ls1021a-pg-wcom-expu1.dts b/arch/arm/dts/ls1021a-pg-wcom-expu1.dts new file mode 100644 index 0000000000..33456b7c38 --- /dev/null +++ b/arch/arm/dts/ls1021a-pg-wcom-expu1.dts @@ -0,0 +1,130 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Hitachi ABB Power Grids EXPU1 board device tree source + * + * Copyright 2020 Hitachi ABB Power Grids + * + * Copyright 2013-2015 Freescale Semiconductor, Inc. + */ + +/dts-v1/; +#include "ls1021a.dtsi" + +/ { + model = "EXPU1 Service Unit for XMC and FOX"; + + aliases { + enet2-rgmii-debug-phy = &debug_phy; + }; + + chosen { + stdout-path = &uart0; + }; +}; + +&enet0 { + status = "okay"; + tbi-handle = <&tbi0>; + phy-connection-type = "sgmii"; + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&enet1 { + status = "okay"; + tbi-handle = <&tbi1>; + phy-connection-type = "sgmii"; + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&enet2 { + phy-handle = <&debug_phy>; + phy-connection-type = "rgmii-id"; + max-speed = <100>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&dspi1 { + bus-num = <0>; + status = "okay"; + zl30343@0 { + compatible = "gen,spidev", "zarlink,zl30343"; + reg = <0>; + spi-max-frequency = <8000000>; + }; +}; + +&ifc { + #address-cells = <2>; + #size-cells = <1>; + /* NOR Flash on board */ + ranges = <0x0 0x0 0x60000000 0x04000000>; + status = "okay"; + + nor@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x4000000>; + bank-width = <2>; + device-width = <1>; + + partition@0 { + label = "rcw"; + reg = <0x0 0x20000>; + read-only; + }; + partition@20000 { + label = "qe"; + reg = <0x20000 0x20000>; + }; + /* ZL30343 init data to be added here */ + partition@40000 { + label = "envred"; + reg = <0x40000 0x20000>; + }; + partition@60000 { + label = "env"; + reg = <0x60000 0x20000>; + }; + partition@100000 { + label = "u-boot"; + reg = <0x100000 0x100000>; + }; + partition@200000 { + label = "ubi0"; + reg = <0x200000 0x3E00000>; + }; + }; +}; + +&mdio0 { + debug_phy: ethernet-phy@11 { + reg = <0x11>; + }; + + tbi0: tbi-phy@0xb { + reg = <0xb>; + device_type = "tbi-phy"; + }; +}; + +&mdio1 { + tbi1: tbi-phy@0xd { + reg = <0xd>; + device_type = "tbi-phy"; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi index 7b99ce02b3..7ba2dd2269 100644 --- a/arch/arm/dts/ls1021a.dtsi +++ b/arch/arm/dts/ls1021a.dtsi @@ -100,7 +100,7 @@ gpio0: gpio@2300000 { compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2300000 0x0 0x10000>; + reg = <0x2300000 0x10000>; interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; @@ -110,7 +110,7 @@ gpio1: gpio@2310000 { compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2310000 0x0 0x10000>; + reg = <0x2310000 0x10000>; interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; @@ -120,7 +120,7 @@ gpio2: gpio@2320000 { compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2320000 0x0 0x10000>; + reg = <0x2320000 0x10000>; interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; @@ -130,7 +130,7 @@ gpio3: gpio@2330000 { compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; - reg = <0x0 0x2330000 0x0 0x10000>; + reg = <0x2330000 0x10000>; interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; gpio-controller; #gpio-cells = <2>; diff --git a/arch/arm/dts/o4-imx-nano.dts b/arch/arm/dts/o4-imx-nano.dts new file mode 100644 index 0000000000..54d32f9dd4 --- /dev/null +++ b/arch/arm/dts/o4-imx-nano.dts @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (C) 2021 Oleh Kravchenko <oleg@kaa.org.ua> + +/dts-v1/; + +#include <dt-bindings/leds/common.h> + +#include "o4-imx6ull-nano.dtsi" + +/ { + model = "O4-iMX-NANO"; + compatible = "out4,o4-imx-nano", + "out4,o4-imx6ull-nano", + "fsl,imx6ull"; + + aliases { + mmc1 = &usdhc1; + }; + + chosen { + stdout-path = &uart1; + }; + + leds { + compatible = "gpio-leds"; + + led0 { + color = <LED_COLOR_ID_RED>; + gpios = <&pcf8574a 0 GPIO_ACTIVE_LOW>; + }; + + led1{ + color = <LED_COLOR_ID_GREEN>; + gpios = <&pcf8574a 1 GPIO_ACTIVE_LOW>; + }; + + led2 { + gpios = <&pcf8574a 2 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_BLUE>; + }; + + led3 { + color = <LED_COLOR_ID_RED>; + gpios = <&pcf8574a 3 GPIO_ACTIVE_LOW>; + }; + + led4{ + color = <LED_COLOR_ID_GREEN>; + gpios = <&pcf8574a 4 GPIO_ACTIVE_LOW>; + }; + + led5 { + color = <LED_COLOR_ID_BLUE>; + gpios = <&pcf8574a 5 GPIO_ACTIVE_LOW>; + }; + }; + + usbotg1_vbus: reg_usbotg1_vbus { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&pcf8574a 6 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "usb0"; + }; + + usbotg2_vbus: reg_usbotg2_vbus { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&pcf8574a 7 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "usb1"; + }; +}; + +&iomuxc { + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10069 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 0x03029 + >; + }; + + pinctrl_mdio: mdiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0xb0b0 /* RST */ + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_CSI_HSYNC__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_CSI_VSYNC__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x1b8b0 + MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x1b8b0 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x1b020 + MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x1b020 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1 + >; + }; +}; + +&uart1 { + pinctrl-0 = <&pinctrl_uart1>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usdhc1 { + bus-width = <4>; + no-1-8-v; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-names = "default"; + status = "okay"; + wakeup-source; +}; + +&fec1 { + phy-handle = <&phy0>; + phy-mode = "rmii"; + pinctrl-0 = <&pinctrl_fec1>; + pinctrl-names = "default"; + status = "okay"; +}; + +&fec2 { + phy-handle = <&phy1>; + phy-mode = "rmii"; + phy-reset-duration = <250>; + phy-reset-post-delay = <100>; + phy-reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_fec2 &pinctrl_mdio>; + pinctrl-names = "default"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + clocks = <&clks IMX6UL_CLK_ENET_REF>; + clock-names = "rmii-ref"; + interrupt-parent = <&gpio5>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + pinctrl-0 = <&pinctrl_phy0_irq>; + pinctrl-names = "default"; + reg = <0>; + }; + + phy1: ethernet-phy@1 { + clocks = <&clks IMX6UL_CLK_ENET2_REF>; + clock-names = "rmii-ref"; + interrupt-parent = <&gpio5>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + pinctrl-0 = <&pinctrl_phy1_irq>; + pinctrl-names = "default"; + reg = <1>; + }; + }; +}; + +&usbotg1 { + dr_mode = "host"; + status = "okay"; + vbus-supply = <&usbotg1_vbus>; +}; + +&usbotg2 { + dr_mode = "host"; + status = "okay"; + vbus-supply = <&usbotg2_vbus>; +}; + +&i2c2 { + clock_frequency = <100000>; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + pinctrl-names = "default", "gpio"; + scl-gpios = <&gpio4 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio4 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pcf8574a: gpio@38 { + compatible = "nxp,pcf8574a"; + #gpio-cells = <2>; + gpio-controller; + reg = <0x38>; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + status = "okay"; +}; + +&uart2 { + linux,rs485-enabled-at-boot-time; + pinctrl-0 = <&pinctrl_uart2>; + pinctrl-names = "default"; + status = "okay"; + uart-has-rtscts; +}; diff --git a/arch/arm/dts/o4-imx6ull-nano.dtsi b/arch/arm/dts/o4-imx6ull-nano.dtsi new file mode 100644 index 0000000000..3fefa80eae --- /dev/null +++ b/arch/arm/dts/o4-imx6ull-nano.dtsi @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (C) 2021 Oleh Kravchenko <oleg@kaa.org.ua> + +/dts-v1/; + +#include "imx6ull.dtsi" + +/ { + model = "O4-iMX6ULL-NANO"; + compatible = "out4,o4-imx6ull-nano", "fsl,imx6ull"; + + aliases { + mmc0 = &usdhc2; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; +}; + +&iomuxc { + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + >; + }; + + pinctrl_fec2: fec2grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + >; + }; + + pinctrl_phy0_irq: phy0grp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x79 + >; + }; + + pinctrl_phy1_irq: phy1grp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79 + >; + }; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + non-removable; + keep-power-in-suspend; + wakeup-source; + bus-width = <8>; + status = "okay"; +}; diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index bb13e07b66..267a094e5a 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -50,6 +50,8 @@ #define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */ #define MXC_CPU_IMX8QM 0x91 /* dummy ID */ #define MXC_CPU_IMX8QXP 0x92 /* dummy ID */ +#define MXC_CPU_IMXRT1020 0xB4 /* dummy ID */ +#define MXC_CPU_IMXRT1050 0xB6 /* dummy ID */ #define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */ #define MXC_CPU_VF610 0xF6 /* dummy ID */ @@ -57,6 +59,7 @@ #define MXC_SOC_MX7 0x70 #define MXC_SOC_IMX8M 0x80 #define MXC_SOC_IMX8 0x90 /* dummy */ +#define MXC_SOC_IMXRT 0xB0 /* dummy */ #define MXC_SOC_MX7ULP 0xE0 /* dummy */ #define CHIP_REV_1_0 0x10 diff --git a/arch/arm/include/asm/arch-imxrt/imx-regs.h b/arch/arm/include/asm/arch-imxrt/imx-regs.h index 44c95dcd11..d01e6ca2e0 100644 --- a/arch/arm/include/asm/arch-imxrt/imx-regs.h +++ b/arch/arm/include/asm/arch-imxrt/imx-regs.h @@ -23,4 +23,8 @@ #include <asm/mach-imx/regs-lcdif.h> #endif +#define USB_BASE_ADDR 0x402E0000 +#define USB_PHY0_BASE_ADDR 0x400D9000 +#define USB_PHY1_BASE_ADDR 0x400DA000 + #endif /* __ASM_ARCH_IMX_REGS_H__ */ diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 2aff1c467c..79432f3bbd 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -9,6 +9,8 @@ #ifndef __ASSEMBLY__ +#include <config.h> + #include <asm/types.h> #include <linux/types.h> diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index c7668ffc4d..b612189849 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -31,6 +31,7 @@ struct bd_info; #define is_mx7() (is_soc_type(MXC_SOC_MX7)) #define is_imx8m() (is_soc_type(MXC_SOC_IMX8M)) #define is_imx8() (is_soc_type(MXC_SOC_IMX8)) +#define is_imxrt() (is_soc_type(MXC_SOC_IMXRT)) #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)) #define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) @@ -78,6 +79,9 @@ struct bd_info; #define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP)) +#define is_imxrt1020() (is_cpu_type(MXC_CPU_IMXRT1020)) +#define is_imxrt1050() (is_cpu_type(MXC_CPU_IMXRT1050)) + #ifdef CONFIG_MX6 #define IMX6_SRC_GPR10_BMODE BIT(28) #define IMX6_SRC_GPR10_PERSIST_SECONDARY_BOOT BIT(30) diff --git a/arch/arm/lib/crt0_64.S b/arch/arm/lib/crt0_64.S index 9d2319c0e8..680e674fa3 100644 --- a/arch/arm/lib/crt0_64.S +++ b/arch/arm/lib/crt0_64.S @@ -112,6 +112,11 @@ ENTRY(_main) ldr x9, _TEXT_BASE /* x9 <- Linked value of _start */ sub x9, x9, x0 /* x9 <- Run-vs-link offset */ add lr, lr, x9 +#if defined(CONFIG_SYS_RELOC_GD_ENV_ADDR) + ldr x0, [x18, #GD_ENV_ADDR] /* x0 <- gd->env_addr */ + add x0, x0, x9 + str x0, [x18, #GD_ENV_ADDR] +#endif #endif /* Add in link-vs-relocation offset */ ldr x9, [x18, #GD_RELOC_OFF] /* x9 <- gd->reloc_off */ diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig index 4e76612d05..71221d8d06 100644 --- a/arch/arm/mach-imx/imx8/Kconfig +++ b/arch/arm/mach-imx/imx8/Kconfig @@ -86,6 +86,12 @@ config TARGET_IMX8QM_MEK select BOARD_LATE_INIT select IMX8QM +config TARGET_CONGA_QMX8 + bool "Support congatec conga-QMX8 board" + select BOARD_LATE_INIT + select SUPPORT_SPL + select IMX8QM + config TARGET_IMX8QM_ROM7720_A1 bool "Support i.MX8QM ROM-7720-A1" select BOARD_LATE_INIT @@ -101,6 +107,7 @@ endchoice source "board/freescale/imx8qm_mek/Kconfig" source "board/freescale/imx8qxp_mek/Kconfig" +source "board/congatec/cgtqmx8/Kconfig" source "board/advantech/imx8qm_rom7720_a1/Kconfig" source "board/toradex/apalis-imx8/Kconfig" source "board/toradex/colibri-imx8x/Kconfig" diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index 65d476e037..f8e4ec0d90 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -54,7 +54,7 @@ static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = { PLL_1443X_RATE(600000000U, 300, 3, 2, 0), PLL_1443X_RATE(594000000U, 99, 1, 2, 0), PLL_1443X_RATE(400000000U, 300, 9, 1, 0), - PLL_1443X_RATE(266666667U, 400, 9, 2, 0), + PLL_1443X_RATE(266000000U, 400, 9, 2, 0), PLL_1443X_RATE(167000000U, 334, 3, 4, 0), PLL_1443X_RATE(100000000U, 300, 9, 3, 0), }; @@ -72,7 +72,7 @@ static int fracpll_configure(enum pll_clocks pll, u32 freq) } if (i == ARRAY_SIZE(imx8mm_fracpll_tbl)) { - printf("No matched freq table %u\n", freq); + printf("%s: No matched freq table %u\n", __func__, freq); return -EINVAL; } @@ -148,7 +148,7 @@ void dram_enable_bypass(ulong clk_val) } if (i == ARRAY_SIZE(imx8mm_dram_bypass_tbl)) { - printf("No matched freq table %lu\n", clk_val); + printf("%s: No matched freq table %lu\n", __func__, clk_val); return; } @@ -646,7 +646,7 @@ static u32 decode_fracpll(enum clk_root_src frac_pll) pll_fdiv_ctl1 = readl(&ana_pll->video_pll1_fdiv_ctl1); break; default: - printf("Not supported\n"); + printf("Unsupported clk_root_src %d\n", frac_pll); return 0; } diff --git a/arch/arm/mach-imx/imxrt/soc.c b/arch/arm/mach-imx/imxrt/soc.c index 8e7d15160d..ba015992ee 100644 --- a/arch/arm/mach-imx/imxrt/soc.c +++ b/arch/arm/mach-imx/imxrt/soc.c @@ -8,13 +8,14 @@ #include <init.h> #include <asm/io.h> #include <asm/armv7_mpu.h> +#include <asm/mach-imx/sys_proto.h> #include <linux/bitops.h> int arch_cpu_init(void) { int i; - struct mpu_region_config imxrt1050_region_config[] = { + struct mpu_region_config imxrt_region_config[] = { { 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW, STRONG_ORDER, REGION_4GB }, { PHYS_SDRAM, REGION_1, XN_DIS, PRIV_RW_USR_RW, @@ -29,9 +30,20 @@ int arch_cpu_init(void) * the whole 4GB address space. */ disable_mpu(); - for (i = 0; i < ARRAY_SIZE(imxrt1050_region_config); i++) - mpu_config(&imxrt1050_region_config[i]); + for (i = 0; i < ARRAY_SIZE(imxrt_region_config); i++) + mpu_config(&imxrt_region_config[i]); enable_mpu(); return 0; } + +u32 get_cpu_rev(void) +{ +#if defined(CONFIG_IMXRT1020) + return MXC_CPU_IMXRT1020 << 12; +#elif defined(CONFIG_IMXRT1050) + return MXC_CPU_IMXRT1050 << 12; +#else +#error This IMXRT SoC is not supported +#endif +} diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 9450e6a683..23cab3932b 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -453,6 +453,17 @@ config TARGET_NITROGEN6X imply USB_ETHER_SMSC95XX imply USB_HOST_ETHER +config TARGET_NPI_IMX6ULL + bool "Seeed NPI-IMX6ULL" + depends on MX6ULL + select DM + select DM_ETH + select DM_MMC + select DM_GPIO + select DM_SERIAL + select DM_THERMAL + select SUPPORT_SPL + config TARGET_OPOS6ULDEV bool "Armadeus OPOS6ULDev board" depends on MX6UL @@ -619,6 +630,18 @@ config TARGET_BRPPT2 Support B&R BRPPT2 platform based on Freescale's iMX6 SoC + +config TARGET_O4_IMX6ULL_NANO + bool "O4-iMX6ULL-NANO" + depends on MX6ULL + select BOARD_LATE_INIT + select DM + select DM_THERMAL + imply CMD_DM + help + Support for www.out4.ru O4-iMX6UL-NANO platform + based on Freescale's i.MX6UL/i.MX6ULL SoC. + endchoice config SYS_SOC @@ -668,5 +691,6 @@ source "board/udoo/neo/Kconfig" source "board/wandboard/Kconfig" source "board/warp/Kconfig" source "board/BuR/brppt2/Kconfig" +source "board/out4/o4-imx6ull-nano/Kconfig" endif diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig index 5c6fe426ef..adedc01164 100644 --- a/arch/arm/mach-imx/mx7/Kconfig +++ b/arch/arm/mach-imx/mx7/Kconfig @@ -70,6 +70,14 @@ config TARGET_PICO_IMX7D select SUPPORT_SPL imply CMD_DM +config TARGET_SMEGW01 + bool "smegw01" + select BOARD_LATE_INIT + select DM + select DM_THERMAL + select MX7D + imply CMD_DM + config TARGET_WARP7 bool "warp7" select BOARD_LATE_INIT @@ -94,6 +102,7 @@ source "board/compulab/cl-som-imx7/Kconfig" source "board/ronetix/imx7-cm/Kconfig" source "board/freescale/mx7dsabresd/Kconfig" source "board/novtech/meerkat96/Kconfig" +source "board/storopack/smegw01/Kconfig" source "board/technexion/pico-imx7d/Kconfig" source "board/toradex/colibri_imx7/Kconfig" source "board/warp7/Kconfig" diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64 index 3f7ec05379..c621f8a544 100644 --- a/arch/arm/mach-rmobile/Kconfig.64 +++ b/arch/arm/mach-rmobile/Kconfig.64 @@ -69,16 +69,19 @@ choice config TARGET_BEACON_RZG2H bool "Beacon EmbeddedWorks RZ/G2H Dev Kit" select R8A774E1 + select RZ_G2 select PINCTRL_PFC_R8A774E1 config TARGET_BEACON_RZG2M bool "Beacon EmbeddedWorks RZ/G2M Dev Kit" select R8A774A1 + select RZ_G2 select PINCTRL_PFC_R8A774A1 config TARGET_BEACON_RZG2N bool "Beacon EmbeddedWorks RZ/G2N Dev Kit" select R8A774B1 + select RZ_G2 select PINCTRL_PFC_R8A774B1 config TARGET_CONDOR diff --git a/arch/arm/mach-zynqmp/include/mach/hardware.h b/arch/arm/mach-zynqmp/include/mach/hardware.h index 3d3c48e247..a798aa0eb9 100644 --- a/arch/arm/mach-zynqmp/include/mach/hardware.h +++ b/arch/arm/mach-zynqmp/include/mach/hardware.h @@ -19,6 +19,11 @@ #define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT 0 #define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT 8 +#define ZYNQMP_AMS_PS_SYSMON_BASEADDR 0XFFA50800 +#define ZYNQMP_AMS_PS_SYSMON_ANALOG_BUS ((ZYNQMP_AMS_PS_SYSMON_BASEADDR) \ + + 0x00000114) +#define ZYNQMP_PS_SYSMON_ANALOG_BUS_VAL 0x00003210 + #define PS_MODE0 BIT(0) #define PS_MODE1 BIT(1) #define PS_MODE2 BIT(2) diff --git a/arch/m68k/include/asm/global_data.h b/arch/m68k/include/asm/global_data.h index 188055e9d3..273e843c4a 100644 --- a/arch/m68k/include/asm/global_data.h +++ b/arch/m68k/include/asm/global_data.h @@ -7,6 +7,8 @@ #ifndef __ASM_GBL_DATA_H #define __ASM_GBL_DATA_H +#include <config.h> + /* Architecture-specific global data */ struct arch_global_data { #ifdef CONFIG_SYS_I2C_FSL diff --git a/arch/nds32/include/asm/global_data.h b/arch/nds32/include/asm/global_data.h index be04a18857..297481beaa 100644 --- a/arch/nds32/include/asm/global_data.h +++ b/arch/nds32/include/asm/global_data.h @@ -17,6 +17,8 @@ #ifndef __ASM_GBL_DATA_H #define __ASM_GBL_DATA_H +#include <config.h> + /* Architecture-specific global data */ struct arch_global_data { }; diff --git a/arch/powerpc/dts/t2080rdb.dts b/arch/powerpc/dts/t2080rdb.dts index 25f8c978c6..4de814ea8d 100644 --- a/arch/powerpc/dts/t2080rdb.dts +++ b/arch/powerpc/dts/t2080rdb.dts @@ -77,10 +77,17 @@ reg = <0x0>; }; +#ifdef CONFIG_T2080RDB_REV_D + xg_aq1202_phy4: ethernet-phy@8 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x8>; + }; +#else xg_aq1202_phy4: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c45"; reg = <0x1>; }; +#endif }; }; }; diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index 192a02d347..90bf5a2aea 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -8,7 +8,7 @@ #ifndef __ASM_GBL_DATA_H #define __ASM_GBL_DATA_H -#include "config.h" +#include <config.h> #include "asm/types.h" /* Architecture-specific global data */ diff --git a/arch/powerpc/lib/traps.c b/arch/powerpc/lib/traps.c index ab8ca269a5..c7bce82a44 100644 --- a/arch/powerpc/lib/traps.c +++ b/arch/powerpc/lib/traps.c @@ -4,7 +4,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include <common.h> #include <init.h> #include <asm/global_data.h> diff --git a/arch/riscv/dts/ae350-u-boot.dtsi b/arch/riscv/dts/ae350-u-boot.dtsi new file mode 100644 index 0000000000..0d4201cfae --- /dev/null +++ b/arch/riscv/dts/ae350-u-boot.dtsi @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/ { + cpus { + u-boot,dm-spl; + CPU0: cpu@0 { + u-boot,dm-spl; + CPU0_intc: interrupt-controller { + u-boot,dm-spl; + }; + }; + CPU1: cpu@1 { + u-boot,dm-spl; + CPU1_intc: interrupt-controller { + u-boot,dm-spl; + }; + }; + CPU2: cpu@2 { + u-boot,dm-spl; + CPU2_intc: interrupt-controller { + u-boot,dm-spl; + }; + }; + CPU3: cpu@3 { + u-boot,dm-spl; + CPU3_intc: interrupt-controller { + u-boot,dm-spl; + }; + }; + }; + + memory@0 { + u-boot,dm-spl; + }; + + soc { + u-boot,dm-spl; + + plic1: interrupt-controller@e6400000 { + u-boot,dm-spl; + }; + + plmt0@e6000000 { + u-boot,dm-spl; + }; + }; + + serial0: serial@f0300000 { + u-boot,dm-spl; + }; + +}; diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts index a0ab5e9be2..083f676333 100644 --- a/arch/riscv/dts/ae350_32.dts +++ b/arch/riscv/dts/ae350_32.dts @@ -1,6 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + /dts-v1/; #include "binman.dtsi" +#include "ae350-u-boot.dtsi" / { #address-cells = <1>; @@ -14,7 +17,7 @@ }; chosen { - bootargs = "console=ttyS0,38400n8 debug loglevel=7"; + bootargs = "console=ttyS0,38400n8 debug loglevel=7"; stdout-path = "uart0:38400n8"; }; @@ -133,8 +136,7 @@ plic0: interrupt-controller@e4000000 { compatible = "riscv,plic0"; - #address-cells = <1>; - #interrupt-cells = <1>; + #interrupt-cells = <2>; interrupt-controller; reg = <0xe4000000 0x2000000>; riscv,ndev=<71>; @@ -146,7 +148,6 @@ plic1: interrupt-controller@e6400000 { compatible = "riscv,plic1"; - #address-cells = <1>; #interrupt-cells = <1>; interrupt-controller; reg = <0xe6400000 0x400000>; diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts index f654f4809a..74cff9122d 100644 --- a/arch/riscv/dts/ae350_64.dts +++ b/arch/riscv/dts/ae350_64.dts @@ -1,6 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + /dts-v1/; #include "binman.dtsi" +#include "ae350-u-boot.dtsi" / { #address-cells = <2>; @@ -14,7 +17,7 @@ }; chosen { - bootargs = "console=ttyS0,38400n8 debug loglevel=7"; + bootargs = "console=ttyS0,38400n8 debug loglevel=7"; stdout-path = "uart0:38400n8"; }; @@ -133,7 +136,6 @@ plic0: interrupt-controller@e4000000 { compatible = "riscv,plic0"; - #address-cells = <2>; #interrupt-cells = <2>; interrupt-controller; reg = <0x0 0xe4000000 0x0 0x2000000>; @@ -146,7 +148,6 @@ plic1: interrupt-controller@e6400000 { compatible = "riscv,plic1"; - #address-cells = <2>; #interrupt-cells = <2>; interrupt-controller; reg = <0x0 0xe6400000 0x0 0x400000>; diff --git a/arch/riscv/lib/andes_plic.c b/arch/riscv/lib/andes_plic.c index 221a5fe324..5e113ee8c9 100644 --- a/arch/riscv/lib/andes_plic.c +++ b/arch/riscv/lib/andes_plic.c @@ -105,9 +105,11 @@ int riscv_clear_ipi(int hart) int riscv_get_ipi(int hart, int *pending) { + unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart)); + *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic, gd->arch.boot_hart)); - *pending = !!(*pending & SEND_IPI_TO_HART(hart)); + *pending = !!(*pending & ipi); return 0; } diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 5ca3bc502a..8e7eaf2d15 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -14,11 +14,11 @@ aliases { console = &uart0; - eth0 = "/eth@10002000"; - eth2 = &swp_0; - eth3 = ð_3; - eth4 = &dsa_eth0; - eth5 = ð_5; + ethernet0 = "/eth@10002000"; + ethernet2 = &swp_0; + ethernet3 = ð_3; + ethernet4 = &dsa_eth0; + ethernet5 = ð_5; gpio1 = &gpio_a; gpio2 = &gpio_b; gpio3 = &gpio_c; diff --git a/arch/x86/cpu/u-boot-64.lds b/arch/x86/cpu/u-boot-64.lds index 98c7f8e9c5..ee0812aefb 100644 --- a/arch/x86/cpu/u-boot-64.lds +++ b/arch/x86/cpu/u-boot-64.lds @@ -107,4 +107,5 @@ SECTIONS /DISCARD/ : { *(.plt*) } /DISCARD/ : { *(.interp*) } /DISCARD/ : { *(.gnu*) } + /DISCARD/ : { *(.note.gnu.property) } } diff --git a/arch/x86/cpu/u-boot-spl.lds b/arch/x86/cpu/u-boot-spl.lds index 4a655bf9b5..346f60bdac 100644 --- a/arch/x86/cpu/u-boot-spl.lds +++ b/arch/x86/cpu/u-boot-spl.lds @@ -82,6 +82,7 @@ SECTIONS /DISCARD/ : { *(.plt*) } /DISCARD/ : { *(.interp*) } /DISCARD/ : { *(.gnu*) } + /DISCARD/ : { *(.note.gnu.property) } #if defined(CONFIG_SPL_X86_16BIT_INIT) || defined(CONFIG_TPL_X86_16BIT_INIT) /* diff --git a/arch/x86/cpu/u-boot.lds b/arch/x86/cpu/u-boot.lds index a283c290ee..22fde01e74 100644 --- a/arch/x86/cpu/u-boot.lds +++ b/arch/x86/cpu/u-boot.lds @@ -105,6 +105,7 @@ SECTIONS /DISCARD/ : { *(.plt*) } /DISCARD/ : { *(.interp*) } /DISCARD/ : { *(.gnu*) } + /DISCARD/ : { *(.note.gnu.property) } #ifdef CONFIG_X86_16BIT_INIT /* |