diff options
Diffstat (limited to 'arch')
28 files changed, 833 insertions, 460 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2d3303bdae..d7a9b11c76 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -656,6 +656,7 @@ config TARGET_VEXPRESS64_JUNO config TARGET_LS2080A_EMU bool "Support ls2080a_emu" + select ARCH_LS2080A select ARM64 select ARMV8_MULTIENTRY help @@ -666,6 +667,7 @@ config TARGET_LS2080A_EMU config TARGET_LS2080A_SIMU bool "Support ls2080a_simu" + select ARCH_LS2080A select ARM64 select ARMV8_MULTIENTRY help @@ -676,6 +678,7 @@ config TARGET_LS2080A_SIMU config TARGET_LS2080AQDS bool "Support ls2080aqds" + select ARCH_LS2080A select ARM64 select ARMV8_MULTIENTRY select SUPPORT_SPL @@ -687,6 +690,7 @@ config TARGET_LS2080AQDS config TARGET_LS2080ARDB bool "Support ls2080ardb" + select ARCH_LS2080A select ARM64 select ARMV8_MULTIENTRY select SUPPORT_SPL @@ -740,6 +744,8 @@ config TARGET_LS1012AFRDM config TARGET_LS1021AQDS bool "Support ls1021aqds" select CPU_V7 + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT select SUPPORT_SPL select ARCH_LS1021A select ARCH_SUPPORT_PSCI @@ -748,6 +754,8 @@ config TARGET_LS1021AQDS config TARGET_LS1021ATWR bool "Support ls1021atwr" select CPU_V7 + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT select SUPPORT_SPL select ARCH_LS1021A select ARCH_SUPPORT_PSCI @@ -817,6 +825,7 @@ config ARCH_UNIPHIER select DM_GPIO select DM_I2C select DM_MMC + select DM_RESET select DM_SERIAL select DM_USB select OF_CONTROL diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 0d4bfbc55b..c1eeefd5dd 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -12,7 +12,7 @@ obj-y += cache_v7.o cache_v7_asm.o obj-y += cpu.o cp15.o obj-y += syslib.o -ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_MX7)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI)$(CONFIG_ARCH_SOCFPGA),) +ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_MX7)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI)$(CONFIG_ARCH_SOCFPGA)$(CONFIG_LS102XA),) ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y) obj-y += lowlevel_init.o endif diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 920eb4ad98..28bf778d9c 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -1,6 +1,89 @@ config ARCH_LS1021A - bool "Freescale Layerscape LS1021A SoC" + bool select SYS_FSL_ERRATUM_A010315 + select SYS_FSL_SRDS_1 + select SYS_HAS_SERDES + select SYS_FSL_DDR_BE + select SYS_FSL_DDR_VER_50 + +menu "LS102xA architecture" + depends on ARCH_LS1021A config LS1_DEEP_SLEEP - bool "Freescale Layerscape 1 deep sleep" + bool "Deep sleep" + depends on ARCH_LS1021A + +config MAX_CPUS + int "Maximum number of CPUs permitted for LS102xA" + depends on ARCH_LS1021A + default 2 + help + Set this number to the maximum number of possible CPUs in the SoC. + SoCs may have multiple clusters with each cluster may have multiple + ports. If some ports are reserved but higher ports are used for + cores, count the reserved ports. This will allocate enough memory + in spin table to properly handle all cores. + +config NUM_DDR_CONTROLLERS + int "Maximum DDR controllers" + default 1 + +config SYS_FSL_ERRATUM_A010315 + bool "Workaround for PCIe erratum A010315" + +config SYS_FSL_SRDS_1 + bool + +config SYS_FSL_SRDS_2 + bool + +config SYS_HAS_SERDES + bool + +config SYS_FSL_DDR + bool "Freescale DDR driver" + help + Select Freescale General DDR driver, shared between most Freescale + PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM- + based Layerscape SoCs (such as ls2080a). + +config SYS_FSL_DDR_BE + bool + default y + help + Access DDR registers in big-endian. + +config SYS_FSL_DDR_VER + int + default 50 if SYS_FSL_DDR_VER_50 + +config SYS_FSL_DDR_VER_50 + bool + +config SYS_FSL_DDRC_ARM_GEN3 + bool + +config SYS_FSL_DDRC_GEN4 + bool + +config SYS_FSL_DDR3 + bool "Freescale DDR3 controller" + depends on !SYS_FSL_DDR4 + select SYS_FSL_DDR + select SYS_FSL_DDRC_ARM_GEN3 + help + Enable Freescale DDR3 controller on ARM-based SoCs. + +config SYS_FSL_DDR4 + bool "Freescale DDR4 controller" + select SYS_FSL_DDR + select SYS_FSL_DDRC_GEN4 + help + Enable Freescale DDR4 controller. + +config SYS_FSL_IFC_BANK_COUNT + int "Maximum banks of Integrated flash controller" + depends on ARCH_LS1021A + default 8 + +endmenu diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index 31f00cbd69..52fb6f8d51 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -60,6 +60,10 @@ unsigned int get_soc_major_rev(void) return major; } +void s_init(void) +{ +} + #ifdef CONFIG_SYS_FSL_ERRATUM_A010315 void erratum_a010315(void) { diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index f8057baa03..94ec8d502b 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -1,17 +1,138 @@ config ARCH_LS1012A - bool "Freescale Layerscape LS1012A SoC" + bool + select FSL_LSCH2 + select SYS_FSL_DDR_BE select SYS_FSL_MMDC select SYS_FSL_ERRATUM_A010315 config ARCH_LS1043A - bool "Freescale Layerscape LS1043A SoC" + bool + select FSL_LSCH2 + select SYS_FSL_DDR_BE + select SYS_FSL_DDR_VER_50 select SYS_FSL_ERRATUM_A010315 + select SYS_FSL_ERRATUM_A010539 config ARCH_LS1046A - bool "Freescale Layerscape LS1046A SoC" + bool + select FSL_LSCH2 + select SYS_FSL_DDR_BE + select SYS_FSL_DDR4 + select SYS_FSL_DDR_VER_50 + select SYS_FSL_ERRATUM_A010539 + select SYS_FSL_SRDS_2 + +config ARCH_LS2080A + bool + select FSL_LSCH3 + select SYS_FSL_DDR4 + select SYS_FSL_DDR_LE + select SYS_FSL_DDR_VER_50 + select SYS_FSL_HAS_DP_DDR + select SYS_FSL_SRDS_2 + +config FSL_LSCH2 + bool + select SYS_FSL_SRDS_1 + select SYS_HAS_SERDES + +config FSL_LSCH3 + bool + select SYS_FSL_SRDS_1 + select SYS_HAS_SERDES + +menu "Layerscape architecture" + depends on FSL_LSCH2 || FSL_LSCH3 config SYS_FSL_MMDC - bool "Freescale Multi Mode DDR Controller" + bool config SYS_FSL_ERRATUM_A010315 bool "Workaround for PCIe erratum A010315" + +config SYS_FSL_ERRATUM_A010539 + bool "Workaround for PIN MUX erratum A010539" + +config MAX_CPUS + int "Maximum number of CPUs permitted for Layerscape" + default 4 if ARCH_LS1043A + default 4 if ARCH_LS1046A + default 16 if ARCH_LS2080A + default 1 + help + Set this number to the maximum number of possible CPUs in the SoC. + SoCs may have multiple clusters with each cluster may have multiple + ports. If some ports are reserved but higher ports are used for + cores, count the reserved ports. This will allocate enough memory + in spin table to properly handle all cores. + +config NUM_DDR_CONTROLLERS + int "Maximum DDR controllers" + default 3 if ARCH_LS2080A + default 1 + +config SYS_FSL_IFC_BANK_COUNT + int "Maximum banks of Integrated flash controller" + depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A + default 4 if ARCH_LS1043A + default 4 if ARCH_LS1046A + default 8 if ARCH_LS2080A + +config SYS_FSL_HAS_DP_DDR + bool + +config SYS_FSL_SRDS_1 + bool + +config SYS_FSL_SRDS_2 + bool + +config SYS_HAS_SERDES + bool + +config SYS_FSL_DDR + bool "Freescale DDR driver" + help + Select Freescale General DDR driver, shared between most Freescale + PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM- + based Layerscape SoCs (such as ls2080a). + +config SYS_FSL_DDR_BE + bool + help + Access DDR registers in big-endian. + +config SYS_FSL_DDR_LE + bool + help + Access DDR registers in little-endian. + +config SYS_FSL_DDR_VER + int + default 50 if SYS_FSL_DDR_VER_50 + +config SYS_FSL_DDR_VER_50 + bool + +config SYS_FSL_DDRC_ARM_GEN3 + bool + +config SYS_FSL_DDRC_GEN4 + bool + +config SYS_FSL_DDR3 + bool "Freescale DDR3 controller" + depends on !SYS_FSL_DDR4 + select SYS_FSL_DDR + select SYS_FSL_DDRC_ARM_GEN3 + help + Enable Freescale DDR3 controller on ARM-based SoCs. + +config SYS_FSL_DDR4 + bool "Freescale DDR4 controller" + select SYS_FSL_DDR + select SYS_FSL_DDRC_GEN4 + help + Enable Freescale DDR4 controller. + +endmenu diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index f865373df3..b7a2e0c946 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -44,6 +44,9 @@ void cpu_name(char *name) if (IS_E_PROCESSOR(svr)) strcat(name, "E"); + + sprintf(name + strlen(name), " Rev%d.%d", + SVR_MAJ(svr), SVR_MIN(svr)); break; } @@ -200,6 +203,27 @@ static inline u32 initiator_type(u32 cluster, int init_id) return 0; } +u32 cpu_pos_mask(void) +{ + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + int i = 0; + u32 cluster, type, mask = 0; + + do { + int j; + + cluster = gur_in32(&gur->tp_cluster[i].lower); + for (j = 0; j < TP_INIT_PER_CLUSTER; j++) { + type = initiator_type(cluster, j); + if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)) + mask |= 1 << (i * TP_INIT_PER_CLUSTER + j); + } + i++; + } while ((cluster & TP_CLUSTER_EOC) == 0x0); + + return mask; +} + u32 cpu_mask(void) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 40d6a761e8..1a8321b0e4 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -108,6 +108,24 @@ remove_psci_node: } #endif +void fsl_fdt_disable_usb(void *blob) +{ + int off; + /* + * SYSCLK is used as a reference clock for USB. When the USB + * controller is used, SYSCLK must meet the additional requirement + * of 100 MHz. + */ + if (CONFIG_SYS_CLK_FREQ != 100000000) { + off = fdt_node_offset_by_compatible(blob, -1, "snps,dwc3"); + while (off != -FDT_ERR_NOTFOUND) { + fdt_status_disabled(blob, off); + off = fdt_node_offset_by_compatible(blob, off, + "snps,dwc3"); + } + } +} + void ft_cpu_setup(void *blob, bd_t *bd) { #ifdef CONFIG_FSL_LSCH2 @@ -150,4 +168,6 @@ void ft_cpu_setup(void *blob, bd_t *bd) #ifdef CONFIG_SYS_DPAA_FMAN fdt_fixup_fman_firmware(blob); #endif + fsl_fdt_disable_usb(blob); + } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c index df7ffb88f6..f607c3900a 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c @@ -104,6 +104,11 @@ int is_core_valid(unsigned int core) return !!((1 << core) & cpu_mask()); } +static int is_pos_valid(unsigned int pos) +{ + return !!((1 << pos) & cpu_pos_mask()); +} + int is_core_online(u64 cpu_id) { u64 *table; @@ -126,9 +131,9 @@ int cpu_disable(int nr) return 0; } -int core_to_pos(int nr) +static int core_to_pos(int nr) { - u32 cores = cpu_mask(); + u32 cores = cpu_pos_mask(); int i, count = 0; if (nr == 0) { @@ -139,14 +144,17 @@ int core_to_pos(int nr) } for (i = 1; i < 32; i++) { - if (is_core_valid(i)) { + if (is_pos_valid(i)) { count++; if (count == nr) break; } } - return count; + if (count != nr) + return -1; + + return i; } int cpu_status(int nr) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 463d1e30d2..d68eeba349 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -233,9 +233,8 @@ int sata_init(void) out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000); #endif out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); - out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG); - out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG); out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); + out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG); ahci_init((void __iomem *)CONFIG_SYS_SATA); scsi_scan(0); @@ -321,6 +320,19 @@ void erratum_a010315(void) } #endif +static void erratum_a010539(void) +{ +#if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT) + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + u32 porsr1; + + porsr1 = in_be32(&gur->porsr1); + porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK; + out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), + porsr1); +#endif +} + void fsl_lsch2_early_init_f(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; @@ -339,7 +351,9 @@ void fsl_lsch2_early_init_f(void) #endif /* Make SEC reads and writes snoopable */ setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP | - SCFG_SNPCNFGCR_SECWRSNP); + SCFG_SNPCNFGCR_SECWRSNP | + SCFG_SNPCNFGCR_SATARDSNP | + SCFG_SNPCNFGCR_SATAWRSNP); /* * Enable snoop requests and DVM message requests for @@ -352,6 +366,7 @@ void fsl_lsch2_early_init_f(void) erratum_a008850_early(); /* part 1 of 2 */ erratum_a009929(); erratum_a009660(); + erratum_a010539(); } #endif diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi index a8bffbafa7..f038f96171 100644 --- a/arch/arm/dts/fsl-ls1043a.dtsi +++ b/arch/arm/dts/fsl-ls1043a.dtsi @@ -215,5 +215,26 @@ big-endian; status = "disabled"; }; + + usb0: usb3@2f00000 { + compatible = "fsl,layerscape-dwc3"; + reg = <0x0 0x2f00000 0x0 0x10000>; + interrupts = <0 60 0x4>; + dr_mode = "host"; + }; + + usb1: usb3@3000000 { + compatible = "fsl,layerscape-dwc3"; + reg = <0x0 0x3000000 0x0 0x10000>; + interrupts = <0 61 0x4>; + dr_mode = "host"; + }; + + usb2: usb3@3100000 { + compatible = "fsl,layerscape-dwc3"; + reg = <0x0 0x3100000 0x0 0x10000>; + interrupts = <0 63 0x4>; + dr_mode = "host"; + }; }; }; diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi index b308c8b982..f76e981c54 100644 --- a/arch/arm/dts/fsl-ls2080a.dtsi +++ b/arch/arm/dts/fsl-ls2080a.dtsi @@ -75,4 +75,18 @@ reg-names = "QuadSPI", "QuadSPI-memory"; num-cs = <4>; }; + + usb0: usb3@3100000 { + compatible = "fsl,layerscape-dwc3"; + reg = <0x0 0x3100000 0x0 0x10000>; + interrupts = <0 80 0x4>; /* Level high type */ + dr_mode = "host"; + }; + + usb1: usb3@3110000 { + compatible = "fsl,layerscape-dwc3"; + reg = <0x0 0x3110000 0x0 0x10000>; + interrupts = <0 81 0x4>; /* Level high type */ + dr_mode = "host"; + }; }; diff --git a/arch/arm/dts/tegra20-colibri.dts b/arch/arm/dts/tegra20-colibri.dts index 777f63e5bd..89adfb6041 100644 --- a/arch/arm/dts/tegra20-colibri.dts +++ b/arch/arm/dts/tegra20-colibri.dts @@ -14,42 +14,35 @@ i2c0 = "/i2c@7000d000"; i2c1 = "/i2c@7000c000"; i2c2 = "/i2c@7000c400"; - usb0 = "/usb@c5008000"; - usb1 = "/usb@c5000000"; - usb2 = "/usb@c5004000"; mmc0 = "/sdhci@c8000600"; + usb0 = "/usb@c5000000"; + usb1 = "/usb@c5004000"; /* on-module only, for ASIX */ + usb2 = "/usb@c5008000"; }; host1x@50000000 { - status = "okay"; dc@54200000 { - status = "okay"; rgb { status = "okay"; nvidia,panel = <&lcd_panel>; + display-timings { + timing@0 { + /* VESA VGA */ + clock-frequency = <25175000>; + hactive = <640>; + vactive = <480>; + hback-porch = <48>; + hfront-porch = <16>; + hsync-len = <96>; + vback-porch = <31>; + vfront-porch = <11>; + vsync-len = <2>; + }; + }; }; }; }; - usb@c5000000 { - statuc = "okay"; - dr_mode = "otg"; - }; - - usb@c5004000 { - statuc = "okay"; - /* VBUS_LAN */ - nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) - GPIO_ACTIVE_LOW>; - nvidia,vbus-gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>; - }; - - usb@c5008000 { - statuc = "okay"; - /* USBH_PEN */ - nvidia,vbus-gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; - }; - nand-controller@70008000 { nvidia,wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>; nvidia,width = <8>; @@ -61,6 +54,10 @@ }; }; + pwm@7000a000 { + status = "okay"; + }; + /* * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier * board) @@ -86,12 +83,45 @@ clock-frequency = <100000>; }; + /* EHCI instance 0: USB1_DP/N -> USBC_P/N */ + usb@c5000000 { + status = "okay"; + dr_mode = "otg"; + }; + + /* EHCI instance 1: ULPI -> USB3340 -> AX88772B */ + usb@c5004000 { + status = "okay"; + /* VBUS_LAN */ + nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>; + nvidia,vbus-gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>; + }; + + /* EHCI instance 2: USB3_DP/N -> USBH_P/N */ + usb@c5008000 { + status = "okay"; + /* USBH_PEN */ + nvidia,vbus-gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; + }; + sdhci@c8000600 { status = "okay"; bus-width = <4>; cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>; }; + backlight: backlight { + compatible = "pwm-backlight"; + + brightness-levels = <255 128 64 32 16 8 4 0>; + default-brightness-level = <6>; + /* BL_ON */ + enable-gpios = <&gpio TEGRA_GPIO(T, 4) GPIO_ACTIVE_HIGH>; + power-supply = <®_3v3>; + /* PWM<A> */ + pwms = <&pwm 0 5000000>; + }; + clocks { compatible = "simple-bus"; #address-cells = <1>; @@ -105,25 +135,28 @@ }; }; - pwm: pwm@7000a000 { - status = "okay"; + lcd_panel: panel { + /* + * edt,et057090dhu: EDT 5.7" LCD TFT + * edt,et070080dh6: EDT 7.0" LCD TFT + */ + compatible = "edt,et057090dhu", "simple-panel"; + + backlight = <&backlight>; }; - lcd_panel: panel { - clock = <25175000>; - xres = <640>; - yres = <480>; - left-margin = <48>; /* horizontal back porch */ - right-margin = <16>; /* horizontal front porch */ - hsync-len = <96>; - lower-margin = <11>; /* vertical front porch */ - upper-margin = <31>; /* vertical back porch */ - vsync-len = <2>; - hsync-active-high; - vsync-active-high; - nvidia,bits-per-pixel = <16>; - nvidia,pwm = <&pwm 0 0>; - nvidia,backlight-enable-gpios = <&gpio TEGRA_GPIO(T, 4) GPIO_ACTIVE_HIGH>; - nvidia,panel-timings = <0 0 0 0>; + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_3v3: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; }; }; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index a5c6c4cd26..4201e0fbec 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -12,17 +12,6 @@ #define CONFIG_STANDALONE_LOAD_ADDR 0x80300000 -#ifdef CONFIG_SYS_FSL_DDR4 -#define CONFIG_SYS_FSL_DDRC_GEN4 -#else -#define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */ -#endif - -#ifndef CONFIG_ARCH_LS1012A -#define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */ -#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 -#endif - /* * Reserve secure memory * To be aligned with MMU block size @@ -30,14 +19,8 @@ #define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */ #ifdef CONFIG_LS2080A -#define CONFIG_MAX_CPUS 16 -#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 -#define CONFIG_NUM_DDR_CONTROLLERS 3 -#define CONFIG_SYS_FSL_HAS_DP_DDR /* Runtime check to confirm */ #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } #define SRDS_MAX_LANES 8 -#define CONFIG_SYS_FSL_SRDS_1 -#define CONFIG_SYS_FSL_SRDS_2 #define CONFIG_SYS_PAGE_SIZE 0x10000 #ifndef L1_CACHE_BYTES #define L1_CACHE_SHIFT 6 @@ -48,7 +31,6 @@ #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */ /* DDR */ -#define CONFIG_SYS_FSL_DDR_LE #define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE @@ -152,7 +134,6 @@ #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #elif defined(CONFIG_FSL_LSCH2) -#define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FSL_SEC_COMPAT 5 #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */ @@ -167,17 +148,12 @@ #define CONFIG_SYS_FSL_PEX_LUT_BE #define CONFIG_SYS_FSL_SEC_BE -#define CONFIG_SYS_FSL_SRDS_1 - /* SoC related */ #ifdef CONFIG_LS1043A -#define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_FMAN_V3 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 7 #define CONFIG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 -#define CONFIG_SYS_FSL_DDR_BE #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE @@ -206,23 +182,18 @@ #define CONFIG_SYS_FSL_ERRATUM_A009660 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #elif defined(CONFIG_ARCH_LS1012A) -#define CONFIG_MAX_CPUS 1 #undef CONFIG_SYS_FSL_DDRC_ARM_GEN3 #define GICD_BASE 0x01401000 #define GICC_BASE 0x01402000 #elif defined(CONFIG_ARCH_LS1046A) -#define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_FMAN_V3 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 8 #define CONFIG_SYS_NUM_FM1_10GEC 2 -#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 -#define CONFIG_SYS_FSL_DDR_BE #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE -#define CONFIG_SYS_FSL_SRDS_2 #define CONFIG_SYS_FSL_IFC_BE #define CONFIG_SYS_FSL_SFP_VER_3_2 #define CONFIG_SYS_FSL_SNVS_LE diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index df5187195d..d88543d063 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -168,6 +168,8 @@ struct sys_info { (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET) /* Device Configuration and Pin Control */ +#define DCFG_DCSR_PORCR1 0x0 + struct ccsr_gur { u32 porsr1; /* POR status 1 */ #define FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK 0xFF800000 @@ -335,6 +337,8 @@ struct ccsr_gur { #define SCFG_SNPCNFGCR_SECRDSNP 0x80000000 #define SCFG_SNPCNFGCR_SECWRSNP 0x40000000 +#define SCFG_SNPCNFGCR_SATARDSNP 0x00800000 +#define SCFG_SNPCNFGCR_SATAWRSNP 0x00400000 /* Supplemental Configuration Unit */ struct ccsr_scfg { diff --git a/arch/arm/include/asm/arch-fsl-layerscape/mp.h b/arch/arm/include/asm/arch-fsl-layerscape/mp.h index e46e076f16..f7306ff266 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/mp.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/mp.h @@ -34,5 +34,6 @@ void *get_spin_tbl_addr(void); phys_addr_t determine_mp_bootpg(void); void secondary_boot_func(void); int is_core_online(u64 cpu_id); +u32 cpu_pos_mask(void); #endif #endif /* _FSL_LAYERSCAPE_MP_H */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h index 4512732f79..58e90d8d88 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h @@ -60,9 +60,8 @@ struct cpu_type { /* ahci port register default value */ #define AHCI_PORT_PHY_1_CFG 0xa003fffe -#define AHCI_PORT_PHY_2_CFG 0x28184d1f -#define AHCI_PORT_PHY_3_CFG 0x0e081509 #define AHCI_PORT_TRANS_CFG 0x08000029 +#define AHCI_PORT_AXICC_CFG 0x3fffffff /* AHCI (sata) register map */ struct ccsr_ahci { diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index fab8774028..ec65cc0bb2 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -94,14 +94,7 @@ #define CONFIG_SYS_FSL_ERRATUM_A008407 #ifdef CONFIG_DDR_SPD -#define CONFIG_SYS_FSL_DDR_BE #define CONFIG_VERY_BIG_RAM -#ifdef CONFIG_SYS_FSL_DDR4 -#define CONFIG_SYS_FSL_DDRC_GEN4 -#else -#define CONFIG_SYS_FSL_DDRC_ARM_GEN3 -#endif -#define CONFIG_SYS_FSL_DDR #define CONFIG_SYS_LS1_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS1_DDR_BLOCK1_SIZE #endif @@ -120,13 +113,7 @@ #define DCU_LAYER_MAX_NUM 16 -#define CONFIG_SYS_FSL_SRDS_1 - #ifdef CONFIG_LS102XA -#define CONFIG_MAX_CPUS 2 -#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 -#define CONFIG_NUM_DDR_CONTROLLERS 1 -#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 #define CONFIG_SYS_FSL_SEC_COMPAT 5 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 #define CONFIG_SYS_FSL_ERRATUM_A008378 diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index 9205b1e164..9c24921b5c 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -10,6 +10,9 @@ config TARGET_OPENRD config TARGET_DREAMPLUG bool "DreamPlug Board" +config TARGET_DS109 + bool "Synology DS109" + config TARGET_GURUPLUG bool "GuruPlug Board" @@ -59,6 +62,7 @@ config SYS_SOC source "board/Marvell/openrd/Kconfig" source "board/Marvell/dreamplug/Kconfig" +source "board/Synology/ds109/Kconfig" source "board/Marvell/guruplug/Kconfig" source "board/Marvell/sheevaplug/Kconfig" source "board/buffalo/lsxl/Kconfig" diff --git a/arch/arm/mach-sunxi/dram_sun8i_h3.c b/arch/arm/mach-sunxi/dram_sun8i_h3.c index 2020d75fd1..b08b8e67cc 100644 --- a/arch/arm/mach-sunxi/dram_sun8i_h3.c +++ b/arch/arm/mach-sunxi/dram_sun8i_h3.c @@ -217,35 +217,57 @@ static void mctl_zq_calibration(struct dram_para *para) struct sunxi_mctl_ctl_reg * const mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; - int i; - u16 zq_val[6]; - u8 val; + if ((readl(SUNXI_SRAMC_BASE + 0x24) & 0xff) == 0 && + (readl(SUNXI_SRAMC_BASE + 0xf0) & 0x1) == 0) { + u32 reg_val; - writel(0x0a0a0a0a, &mctl_ctl->zqdr[2]); - - for (i = 0; i < 6; i++) { - u8 zq = (CONFIG_DRAM_ZQ >> (i * 4)) & 0xf; - - writel((zq << 20) | (zq << 16) | (zq << 12) | - (zq << 8) | (zq << 4) | (zq << 0), - &mctl_ctl->zqcr); + clrsetbits_le32(&mctl_ctl->zqcr, 0xffff, + CONFIG_DRAM_ZQ & 0xffff); writel(PIR_CLRSR, &mctl_ctl->pir); mctl_phy_init(PIR_ZCAL); - zq_val[i] = readl(&mctl_ctl->zqdr[0]) & 0xff; - writel(REPEAT_BYTE(zq_val[i]), &mctl_ctl->zqdr[2]); + reg_val = readl(&mctl_ctl->zqdr[0]); + reg_val &= (0x1f << 16) | (0x1f << 0); + reg_val |= reg_val << 8; + writel(reg_val, &mctl_ctl->zqdr[0]); - writel(PIR_CLRSR, &mctl_ctl->pir); - mctl_phy_init(PIR_ZCAL); + reg_val = readl(&mctl_ctl->zqdr[1]); + reg_val &= (0x1f << 16) | (0x1f << 0); + reg_val |= reg_val << 8; + writel(reg_val, &mctl_ctl->zqdr[1]); + writel(reg_val, &mctl_ctl->zqdr[2]); + } else { + int i; + u16 zq_val[6]; + u8 val; - val = readl(&mctl_ctl->zqdr[0]) >> 24; - zq_val[i] |= bin_to_mgray(mgray_to_bin(val) - 1) << 8; - } + writel(0x0a0a0a0a, &mctl_ctl->zqdr[2]); + + for (i = 0; i < 6; i++) { + u8 zq = (CONFIG_DRAM_ZQ >> (i * 4)) & 0xf; + + writel((zq << 20) | (zq << 16) | (zq << 12) | + (zq << 8) | (zq << 4) | (zq << 0), + &mctl_ctl->zqcr); - writel((zq_val[1] << 16) | zq_val[0], &mctl_ctl->zqdr[0]); - writel((zq_val[3] << 16) | zq_val[2], &mctl_ctl->zqdr[1]); - writel((zq_val[5] << 16) | zq_val[4], &mctl_ctl->zqdr[2]); + writel(PIR_CLRSR, &mctl_ctl->pir); + mctl_phy_init(PIR_ZCAL); + + zq_val[i] = readl(&mctl_ctl->zqdr[0]) & 0xff; + writel(REPEAT_BYTE(zq_val[i]), &mctl_ctl->zqdr[2]); + + writel(PIR_CLRSR, &mctl_ctl->pir); + mctl_phy_init(PIR_ZCAL); + + val = readl(&mctl_ctl->zqdr[0]) >> 24; + zq_val[i] |= bin_to_mgray(mgray_to_bin(val) - 1) << 8; + } + + writel((zq_val[1] << 16) | zq_val[0], &mctl_ctl->zqdr[0]); + writel((zq_val[3] << 16) | zq_val[2], &mctl_ctl->zqdr[1]); + writel((zq_val[5] << 16) | zq_val[4], &mctl_ctl->zqdr[2]); + } } static void mctl_set_cr(struct dram_para *para) diff --git a/arch/arm/mach-tegra/arm64-mmu.c b/arch/arm/mach-tegra/arm64-mmu.c index 7b1d258ed8..a79a5192e0 100644 --- a/arch/arm/mach-tegra/arm64-mmu.c +++ b/arch/arm/mach-tegra/arm64-mmu.c @@ -23,7 +23,7 @@ static struct mm_region tegra_mem_map[] = { }, { .virt = 0x80000000UL, .phys = 0x80000000UL, - .size = 0xff80000000UL, + .size = 0x80000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { diff --git a/arch/arm/mach-uniphier/board_init.c b/arch/arm/mach-uniphier/board_init.c index b9be52f6cb..8c7864cb85 100644 --- a/arch/arm/mach-uniphier/board_init.c +++ b/arch/arm/mach-uniphier/board_init.c @@ -134,6 +134,13 @@ int board_init(void) #endif #if defined(CONFIG_ARCH_UNIPHIER_LD20) case SOC_UNIPHIER_LD20: + /* ES1 errata: increase VDD09 supply to suppress VBO noise */ + if (uniphier_get_soc_revision() == 1) { + writel(0x00000003, 0x6184e004); + writel(0x00000100, 0x6184e040); + writel(0x0000b500, 0x6184e024); + writel(0x00000001, 0x6184e000); + } uniphier_nand_pin_init(false); sg_set_pinsel(149, 14, 8, 4); /* XIRQ0 -> XIRQ0 */ sg_set_iectrl(149); diff --git a/arch/arm/mach-uniphier/clk/pll-ld11.c b/arch/arm/mach-uniphier/clk/pll-ld11.c index 8a4a748cfd..7746deb72d 100644 --- a/arch/arm/mach-uniphier/clk/pll-ld11.c +++ b/arch/arm/mach-uniphier/clk/pll-ld11.c @@ -23,6 +23,7 @@ void uniphier_ld11_pll_init(void) uniphier_ld20_sscpll_ssc_en(SC_CPLLCTRL); uniphier_ld20_sscpll_ssc_en(SC_MPLLCTRL); uniphier_ld20_sscpll_ssc_en(SC_VSPLLCTRL); + uniphier_ld20_sscpll_ssc_en(SC_DPLLCTRL); uniphier_ld20_vpll27_init(SC_VPLL27FCTRL); uniphier_ld20_vpll27_init(SC_VPLL27ACTRL); diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h b/arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h index 02b3aaba5a..0c11b65e46 100644 --- a/arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h +++ b/arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h @@ -7,7 +7,12 @@ #ifndef _DDRPHY_LD20_REGS_H #define _DDRPHY_LD20_REGS_H +#include <linux/bitops.h> + #define PHY_REG_SHIFT 2 +#define PHY_SLV_DLY_WIDTH 6 +#define PHY_BITLVL_DLY_WIDTH 6 +#define PHY_MAS_DLY_WIDTH 8 #define PHY_SCL_START (0x40 << (PHY_REG_SHIFT)) #define PHY_SCL_DATA_0 (0x41 << (PHY_REG_SHIFT)) @@ -17,8 +22,19 @@ #define PHY_SCL_CONFIG_2 (0x47 << (PHY_REG_SHIFT)) #define PHY_PAD_CTRL (0x48 << (PHY_REG_SHIFT)) #define PHY_DLL_RECALIB (0x49 << (PHY_REG_SHIFT)) +#define PHY_DLL_RECALIB_TRIM_MASK GENMASK(PHY_SLV_DLY_WIDTH - 1, 0) +#define PHY_DLL_RECALIB_INCR BIT(27) #define PHY_DLL_ADRCTRL (0x4A << (PHY_REG_SHIFT)) +#define PHY_DLL_ADRCTRL_TRIM_MASK GENMASK(PHY_SLV_DLY_WIDTH - 1, 0) +#define PHY_DLL_ADRCTRL_INCR BIT(9) +#define PHY_DLL_ADRCTRL_MDL_SHIFT 24 +#define PHY_DLL_ADRCTRL_MDL_MASK (GENMASK(PHY_MAS_DLY_WIDTH - 1, 0) << \ + PHY_DLL_ADRCTRL_MDL_SHIFT) #define PHY_LANE_SEL (0x4B << (PHY_REG_SHIFT)) +#define PHY_LANE_SEL_LANE_SHIFT 0 +#define PHY_LANE_SEL_LANE_WIDTH 8 +#define PHY_LANE_SEL_BIT_SHIFT 8 +#define PHY_LANE_SEL_BIT_WIDTH 4 #define PHY_DLL_TRIM_1 (0x4C << (PHY_REG_SHIFT)) #define PHY_DLL_TRIM_2 (0x4D << (PHY_REG_SHIFT)) #define PHY_DLL_TRIM_3 (0x4E << (PHY_REG_SHIFT)) @@ -34,9 +50,23 @@ #define PHY_UNIQUIFY_TSMC_IO_1 (0x5C << (PHY_REG_SHIFT)) #define PHY_SCL_START_ADDR (0x62 << (PHY_REG_SHIFT)) #define PHY_IP_DQ_DQS_BITWISE_TRIM (0x65 << (PHY_REG_SHIFT)) +#define PHY_IP_DQ_DQS_BITWISE_TRIM_MASK \ + GENMASK(PHY_BITLVL_DLY_WIDTH - 1, 0) +#define PHY_IP_DQ_DQS_BITWISE_TRIM_INC \ + BIT(PHY_BITLVL_DLY_WIDTH) +#define PHY_IP_DQ_DQS_BITWISE_TRIM_OVERRIDE \ + BIT(PHY_BITLVL_DLY_WIDTH + 1) #define PHY_DSCL_CNT (0x67 << (PHY_REG_SHIFT)) #define PHY_OP_DQ_DM_DQS_BITWISE_TRIM (0x68 << (PHY_REG_SHIFT)) +#define PHY_OP_DQ_DM_DQS_BITWISE_TRIM_MASK \ + GENMASK(PHY_BITLVL_DLY_WIDTH - 1, 0) +#define PHY_OP_DQ_DM_DQS_BITWISE_TRIM_INC \ + BIT(PHY_BITLVL_DLY_WIDTH) +#define PHY_OP_DQ_DM_DQS_BITWISE_TRIM_OVERRIDE \ + BIT(PHY_BITLVL_DLY_WIDTH + 1) #define PHY_DLL_TRIM_CLK (0x69 << (PHY_REG_SHIFT)) +#define PHY_DLL_TRIM_CLK_MASK GENMASK(PHY_SLV_DLY_WIDTH, 0) +#define PHY_DLL_TRIM_CLK_INCR BIT(PHY_SLV_DLY_WIDTH + 1) #define PHY_DYNAMIC_BIT_LVL (0x6B << (PHY_REG_SHIFT)) #define PHY_SCL_WINDOW_TRIM (0x6D << (PHY_REG_SHIFT)) #define PHY_DISABLE_GATING_FOR_SCL (0x6E << (PHY_REG_SHIFT)) @@ -45,11 +75,4 @@ #define PHY_VREF_TRAINING (0x72 << (PHY_REG_SHIFT)) #define PHY_SCL_GATE_TIMING (0x78 << (PHY_REG_SHIFT)) -/* MASK */ -#define MSK_OP_DQ_DM_DQS_BITWISE_TRIM 0x0000007F -#define MSK_IP_DQ_DQS_BITWISE_TRIM 0x0000007F -#define MSK_OVERRIDE 0x00000080 - -#define PHY_BITLVL_DLY_WIDTH 6 - #endif /* _DDRPHY_LD20_REGS_H */ diff --git a/arch/arm/mach-uniphier/dram/umc-ld20.c b/arch/arm/mach-uniphier/dram/umc-ld20.c index 1fdd119a3f..4e1fbde7a6 100644 --- a/arch/arm/mach-uniphier/dram/umc-ld20.c +++ b/arch/arm/mach-uniphier/dram/umc-ld20.c @@ -1,7 +1,7 @@ /* * Copyright (C) 2016 Socionext Inc. * - * based on commit a3c28918e86ad57127cf07bf8b32950cab20c03c of Diag + * based on commit 9073035a9860f892f8d1345dfb0ea862b5021145 of Diag * * SPDX-License-Identifier: GPL-2.0+ */ @@ -18,7 +18,6 @@ #include "umc64-regs.h" #define DRAM_CH_NR 3 -#define CONFIG_DDR_FREQ 1866 enum dram_freq { DRAM_FREQ_1866M, @@ -39,311 +38,196 @@ enum dram_board { /* board type */ DRAM_BOARD_NR, }; -#define MSK_PHY_LANE_SEL 0x000000FF -#define MSK_BIT_SEL 0x00000F00 -#define MSK_DLL_MAS_DLY 0xFF000000 -#define MSK_MAS_DLY 0x7F000000 -#define MSK_DLLS_TRIM_CLK 0x000000FF - -#define PHY_DLL_MAS_DLY_WIDTH 8 -#define PHY_SLV_DLY_WIDTH 6 - -static void ddrphy_maskwritel(u32 data, u32 mask, void *addr) -{ - u32 value; - - value = (readl(addr) & ~mask) | (data & mask); - writel(value, addr); -} - -static u32 ddrphy_maskreadl(u32 mask, void *addr) -{ - return readl(addr) & mask; -} - -/* set phy_lane_sel.phy_lane_sel */ -static void ddrphy_set_phy_lane_sel(int val, void __iomem *phy_base) -{ - ddrphy_maskwritel(val, MSK_PHY_LANE_SEL, phy_base + PHY_LANE_SEL); -} - -/* set phy_lane_sel.bit_sel */ -static void ddrphy_set_bit_sel(int bit, void __iomem *phy_base) -{ - ddrphy_maskwritel(bit << 8, MSK_BIT_SEL, phy_base + PHY_LANE_SEL); -} - -/* Calculating step for PUB-byte */ -static int ddrphy_hpstep(int delay, void __iomem *phy_base) -{ - int mdl, freq; - - freq = CONFIG_DDR_FREQ; /* FIXME */ - mdl = ddrphy_maskreadl(MSK_DLL_MAS_DLY, phy_base + PHY_DLL_ADRCTRL) >> 24; - - return DIV_ROUND_CLOSEST(freq * delay * mdl, 2 * 1000000); -} - -static void ddrphy_set_dll_trim_clk(int delay_ckoffset, void __iomem *phy_base) -{ - u8 ck_step; /* ckoffset_step for clock */ - u32 ck_step_all; - - /* CK-Offset */ - if (delay_ckoffset >= 0) { - /* shift + direction */ - ck_step = min(ddrphy_hpstep(delay_ckoffset, phy_base), 127); - ck_step_all = ((0x1<<(PHY_SLV_DLY_WIDTH + 1))|ck_step); - } else{ - /* shift - direction */ - ck_step = min(ddrphy_hpstep(-1*delay_ckoffset, phy_base), 127); - ck_step_all = ck_step; - } - - ddrphy_set_phy_lane_sel(0, phy_base); - ddrphy_maskwritel(ck_step_all, MSK_DLLS_TRIM_CLK, phy_base + PHY_DLL_TRIM_CLK); -} - -static void ddrphy_set_dll_recalib(int delay_qoffset, u32 recalib_cnt, - u8 disable_recalib, u8 ctr_start_val, - void __iomem *phy_base) -{ - u8 dlls_trim_adrctrl_ma, incr_dly_adrctrl_ma; /* qoffset_step and flag for inc/dec */ - u32 recalib_all; /* all fields of register dll_recalib */ - - /* Q-Offset */ - if (delay_qoffset >= 0) { - dlls_trim_adrctrl_ma = min(ddrphy_hpstep(delay_qoffset, phy_base), 63); - incr_dly_adrctrl_ma = 0x1; - } else { - dlls_trim_adrctrl_ma = min(ddrphy_hpstep(-1*delay_qoffset, phy_base), 63); - incr_dly_adrctrl_ma = 0x0; - } - - recalib_all = ((ctr_start_val & 0xf) << 28) | - (incr_dly_adrctrl_ma << 27) | - ((disable_recalib & 0x1) << 26) | - ((recalib_cnt & 0x3ffff) << 8) | - (dlls_trim_adrctrl_ma & 0x3f); - - /* write value for all bits other than bit[7:6] */ - ddrphy_maskwritel(recalib_all, ~0xc0, phy_base + PHY_DLL_RECALIB); -} - -static void ddrphy_set_dll_adrctrl(int delay_qoffset, u8 override_adrctrl, - void __iomem *phy_base) -{ - u8 dlls_trim_adrctrl, incr_dly_adrctrl; /* qoffset_step for clock */ - u32 adrctrl_all; - - if (delay_qoffset >= 0) { - dlls_trim_adrctrl = min(ddrphy_hpstep(delay_qoffset, phy_base), 63); - incr_dly_adrctrl = 0x1; - } else { - dlls_trim_adrctrl = min(ddrphy_hpstep(-delay_qoffset, phy_base), 63); - incr_dly_adrctrl = 0x0; - } - - adrctrl_all = (incr_dly_adrctrl << 9) | - ((override_adrctrl & 0x1) << 8) | - dlls_trim_adrctrl; - - ddrphy_maskwritel(adrctrl_all, 0x33f, phy_base + PHY_DLL_ADRCTRL); -} - -/* dio */ -static int dio_adrctrl_0[DRAM_BOARD_NR][DRAM_CH_NR] = { - {268-262, 268-263, 268-378}, /* LD20 reference */ - {268-262, 268-263, 268-378}, /* LD20 TV */ - {268-212, 268-268, 0}, /* LD21 reference */ - {268-212, 268-268, 0}, /* LD21 TV */ +/* PHY */ +static const int ddrphy_adrctrl[DRAM_BOARD_NR][DRAM_CH_NR] = { + {268 - 262, 268 - 263, 268 - 378}, /* LD20 reference */ + {268 - 262, 268 - 263, 268 - 378}, /* LD20 TV */ + {268 - 212, 268 - 268, /* No CH2 */}, /* LD21 reference */ + {268 - 212, 268 - 268, /* No CH2 */}, /* LD21 TV */ }; -static int dio_dlltrimclk_0[DRAM_BOARD_NR][DRAM_CH_NR] = { + +static const int ddrphy_dlltrimclk[DRAM_BOARD_NR][DRAM_CH_NR] = { {268, 268, 268}, /* LD20 reference */ {268, 268, 268}, /* LD20 TV */ - {268, 268+252, 0}, /* LD21 reference */ - {268, 268+202, 0}, /* LD21 TV */ + {268, 268 + 252, /* No CH2 */}, /* LD21 reference */ + {268, 268 + 202, /* No CH2 */}, /* LD21 TV */ }; -static int dio_dllrecalib_0[DRAM_BOARD_NR][DRAM_CH_NR] = { - {268-378, 268-263, 268-378}, /* LD20 reference */ - {268-378, 268-263, 268-378}, /* LD20 TV */ - {268-212, 268-536, 0}, /* LD21 reference */ - {268-212, 268-536, 0}, /* LD21 TV */ + +static const int ddrphy_dllrecalib[DRAM_BOARD_NR][DRAM_CH_NR] = { + {268 - 378, 268 - 263, 268 - 378}, /* LD20 reference */ + {268 - 378, 268 - 263, 268 - 378}, /* LD20 TV */ + {268 - 212, 268 - 536, /* No CH2 */}, /* LD21 reference */ + {268 - 212, 268 - 536, /* No CH2 */}, /* LD21 TV */ }; -static u32 dio_phy_pad_ctrl[DRAM_BOARD_NR][DRAM_CH_NR] = { +static const u32 ddrphy_phy_pad_ctrl[DRAM_BOARD_NR][DRAM_CH_NR] = { {0x50B840B1, 0x50B840B1, 0x50B840B1}, /* LD20 reference */ {0x50BB40B1, 0x50BB40B1, 0x50BB40B1}, /* LD20 TV */ - {0x50BB40B4, 0x50B840B1, 0x50BB40B1}, /* LD21 reference */ - {0x50BB40B4, 0x50B840B1, 0x50BB40B1}, /* LD21 TV */ + {0x50BB40B4, 0x50B840B1, /* No CH2 */}, /* LD21 reference */ + {0x50BB40B4, 0x50B840B1, /* No CH2 */}, /* LD21 TV */ }; -static u32 dio_scl_gate_timing[DRAM_CH_NR] = {0x00000140, 0x00000180, 0x00000140}; +static const u32 ddrphy_scl_gate_timing[DRAM_CH_NR] = { + 0x00000140, 0x00000180, 0x00000140 +}; -static int dio_op_dq_shift_val[DRAM_BOARD_NR][DRAM_CH_NR][32] = { +static const int ddrphy_op_dq_shift_val[DRAM_BOARD_NR][DRAM_CH_NR][32] = { { /* LD20 reference */ { - 2, 1, 0, 1, 2, 1, 1, 1, 2, 1, 1, 2, 1, 1, 1, 1, - 1, 2, 1, 1, 1, 2, 1, 1, 2, 2, 0, 1, 1, 2, 2, 1, + 2, 1, 0, 1, 2, 1, 1, 1, + 2, 1, 1, 2, 1, 1, 1, 1, + 1, 2, 1, 1, 1, 2, 1, 1, + 2, 2, 0, 1, 1, 2, 2, 1, }, { - 1, 1, 0, 1, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 0, 0, 1, 1, 0, 0, 0, 1, 1, 1, 2, 1, 2, 1, + 1, 1, 0, 1, 2, 2, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 0, 0, 1, 1, 0, 0, + 0, 1, 1, 1, 2, 1, 2, 1, }, { - 2, 2, 0, 2, 1, 1, 2, 1, 1, 1, 0, 1, 1, -1, 1, 1, - 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 2, 2, 1, 2, + 2, 2, 0, 2, 1, 1, 2, 1, + 1, 1, 0, 1, 1, -1, 1, 1, + 2, 2, 2, 2, 1, 1, 1, 1, + 1, 1, 1, 0, 2, 2, 1, 2, }, }, { /* LD20 TV */ { - 2, 1, 0, 1, 2, 1, 1, 1, 2, 1, 1, 2, 1, 1, 1, 1, - 1, 2, 1, 1, 1, 2, 1, 1, 2, 2, 0, 1, 1, 2, 2, 1, + 2, 1, 0, 1, 2, 1, 1, 1, + 2, 1, 1, 2, 1, 1, 1, 1, + 1, 2, 1, 1, 1, 2, 1, 1, + 2, 2, 0, 1, 1, 2, 2, 1, }, { - 1, 1, 0, 1, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 0, 0, 1, 1, 0, 0, 0, 1, 1, 1, 2, 1, 2, 1, + 1, 1, 0, 1, 2, 2, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 0, 0, 1, 1, 0, 0, + 0, 1, 1, 1, 2, 1, 2, 1, }, { - 2, 2, 0, 2, 1, 1, 2, 1, 1, 1, 0, 1, 1, -1, 1, 1, - 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 2, 2, 1, 2, + 2, 2, 0, 2, 1, 1, 2, 1, + 1, 1, 0, 1, 1, -1, 1, 1, + 2, 2, 2, 2, 1, 1, 1, 1, + 1, 1, 1, 0, 2, 2, 1, 2, }, }, { /* LD21 reference */ { - 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 2, - 1, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 1, - }, - { 1, 0, 2, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, - 1, 0, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 0, 0, + 1, 1, 0, 1, 1, 1, 1, 1, + 1, 0, 0, 0, 1, 1, 0, 2, + 1, 1, 0, 0, 1, 1, 1, 1, + 1, 0, 0, 0, 1, 0, 0, 1, }, - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { 1, 0, 2, 1, 1, 1, 1, 0, + 1, 0, 0, 1, 0, 1, 0, 0, + 1, 0, 1, 0, 1, 1, 1, 0, + 1, 1, 1, 1, 0, 1, 0, 0, }, + /* No CH2 */ }, { /* LD21 TV */ { - 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 2, - 1, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 1, - }, - { 1, 0, 2, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, - 1, 0, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 0, 0, + 1, 1, 0, 1, 1, 1, 1, 1, + 1, 0, 0, 0, 1, 1, 0, 2, + 1, 1, 0, 0, 1, 1, 1, 1, + 1, 0, 0, 0, 1, 0, 0, 1, }, - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + { 1, 0, 2, 1, 1, 1, 1, 0, + 1, 0, 0, 1, 0, 1, 0, 0, + 1, 0, 1, 0, 1, 1, 1, 0, + 1, 1, 1, 1, 0, 1, 0, 0, }, + /* No CH2 */ }, }; -static int dio_ip_dq_shift_val[DRAM_BOARD_NR][DRAM_CH_NR][32] = { + +static int ddrphy_ip_dq_shift_val[DRAM_BOARD_NR][DRAM_CH_NR][32] = { { /* LD20 reference */ { - 3, 3, 3, 2, 3, 2, 0, 2, 2, 3, 3, 1, 2, 2, 2, 2, - 2, 2, 2, 2, 0, 1, 1, 1, 2, 2, 2, 2, 3, 0, 2, 2, + 3, 3, 3, 2, 3, 2, 0, 2, + 2, 3, 3, 1, 2, 2, 2, 2, + 2, 2, 2, 2, 0, 1, 1, 1, + 2, 2, 2, 2, 3, 0, 2, 2, }, { - 2, 2, 1, 1, -1, 1, 1, 1, 2, 0, 2, 2, 2, 1, 0, 2, - 2, 1, 2, 1, 0, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, + 2, 2, 1, 1, -1, 1, 1, 1, + 2, 0, 2, 2, 2, 1, 0, 2, + 2, 1, 2, 1, 0, 1, 1, 1, + 2, 2, 2, 2, 2, 2, 2, 2, }, { - 2, 2, 3, 2, 1, 2, 2, 2, 2, 3, 4, 2, 3, 4, 3, 3, - 2, 2, 1, 2, 1, 1, 1, 1, 2, 2, 2, 2, 1, 2, 2, 1, + 2, 2, 3, 2, 1, 2, 2, 2, + 2, 3, 4, 2, 3, 4, 3, 3, + 2, 2, 1, 2, 1, 1, 1, 1, + 2, 2, 2, 2, 1, 2, 2, 1, }, }, { /* LD20 TV */ { - 3, 3, 3, 2, 3, 2, 0, 2, 2, 3, 3, 1, 2, 2, 2, 2, - 2, 2, 2, 2, 0, 1, 1, 1, 2, 2, 2, 2, 3, 0, 2, 2, + 3, 3, 3, 2, 3, 2, 0, 2, + 2, 3, 3, 1, 2, 2, 2, 2, + 2, 2, 2, 2, 0, 1, 1, 1, + 2, 2, 2, 2, 3, 0, 2, 2, }, { - 2, 2, 1, 1, -1, 1, 1, 1, 2, 0, 2, 2, 2, 1, 0, 2, - 2, 1, 2, 1, 0, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, + 2, 2, 1, 1, -1, 1, 1, 1, + 2, 0, 2, 2, 2, 1, 0, 2, + 2, 1, 2, 1, 0, 1, 1, 1, + 2, 2, 2, 2, 2, 2, 2, 2, }, { - 2, 2, 3, 2, 1, 2, 2, 2, 2, 3, 4, 2, 3, 4, 3, 3, - 2, 2, 1, 2, 1, 1, 1, 1, 2, 2, 2, 2, 1, 2, 2, 1, + 2, 2, 3, 2, 1, 2, 2, 2, + 2, 3, 4, 2, 3, 4, 3, 3, + 2, 2, 1, 2, 1, 1, 1, 1, + 2, 2, 2, 2, 1, 2, 2, 1, }, }, { /* LD21 reference */ { - 2, 2, 2, 2, 1, 2, 2, 2, 2, 3, 3, 2, 2, 2, 2, 2, - 2, 1, 2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 1, 2, 2, 2, - }, - { - 3, 4, 4, 1, 0, 1, 1, 1, 1, 2, 1, 2, 2, 3, 3, 2, - 1, 0, 2, 1, 1, 0, 1, 0, 0, 1, 0, 0, 1, 1, 0, 1, + 2, 2, 2, 2, 1, 2, 2, 2, + 2, 3, 3, 2, 2, 2, 2, 2, + 2, 1, 2, 2, 1, 1, 1, 1, + 2, 2, 2, 3, 1, 2, 2, 2, }, { - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 3, 4, 4, 1, 0, 1, 1, 1, + 1, 2, 1, 2, 2, 3, 3, 2, + 1, 0, 2, 1, 1, 0, 1, 0, + 0, 1, 0, 0, 1, 1, 0, 1, }, + /* No CH2 */ }, { /* LD21 TV */ { - 2, 2, 2, 2, 1, 2, 2, 2, 2, 3, 3, 2, 2, 2, 2, 2, - 2, 1, 2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 1, 2, 2, 2, - }, - { - 3, 4, 4, 1, 0, 1, 1, 1, 1, 2, 1, 2, 2, 3, 3, 2, - 1, 0, 2, 1, 1, 0, 1, 0, 0, 1, 0, 0, 1, 1, 0, 1, + 2, 2, 2, 2, 1, 2, 2, 2, + 2, 3, 3, 2, 2, 2, 2, 2, + 2, 1, 2, 2, 1, 1, 1, 1, + 2, 2, 2, 3, 1, 2, 2, 2, }, { - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 3, 4, 4, 1, 0, 1, 1, 1, + 1, 2, 1, 2, 2, 3, 3, 2, + 1, 0, 2, 1, 1, 0, 1, 0, + 0, 1, 0, 0, 1, 1, 0, 1, }, + /* No CH2 */ }, }; -/* umc */ -static u32 umc_initctla[DRAM_FREQ_NR] = {0x71016D11}; -static u32 umc_initctlb[DRAM_FREQ_NR] = {0x07E390AC}; -static u32 umc_initctlc[DRAM_FREQ_NR] = {0x00FF00FF}; -static u32 umc_drmmr0[DRAM_FREQ_NR] = {0x00000114}; -static u32 umc_drmmr2[DRAM_FREQ_NR] = {0x000002a0}; - -static u32 umc_memconf0a[DRAM_FREQ_NR][DRAM_SZ_NR] = { - /* 256MB 512MB */ - {0x00000601, 0x00000801}, /* 1866 MHz */ -}; -static u32 umc_memconf0b[DRAM_FREQ_NR][DRAM_SZ_NR] = { - /* 256MB 512MB */ - {0x00000120, 0x00000130}, /* 1866 MHz */ -}; -static u32 umc_memconfch[DRAM_FREQ_NR][DRAM_SZ_NR] = { - /* 256MB 512MB */ - {0x00033603, 0x00033803}, /* 1866 MHz */ -}; -static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060D0D20}; -static u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x2D211C08}; -static u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00150C04}; -static u32 umc_cmdctle[DRAM_FREQ_NR][DRAM_SZ_NR] = { - /* 256MB 512MB */ - {0x0049071D, 0x0078071D}, /* 1866 MHz */ -}; - -static u32 umc_rdatactl_d0[DRAM_FREQ_NR] = {0x00000610}; -static u32 umc_rdatactl_d1[DRAM_FREQ_NR] = {0x00000610}; -static u32 umc_wdatactl_d0[DRAM_FREQ_NR] = {0x00000204}; -static u32 umc_wdatactl_d1[DRAM_FREQ_NR] = {0x00000204}; -static u32 umc_odtctl_d0[DRAM_FREQ_NR] = {0x02000002}; -static u32 umc_odtctl_d1[DRAM_FREQ_NR] = {0x02000002}; -static u32 umc_dataset[DRAM_FREQ_NR] = {0x04000000}; - -static u32 umc_flowctla[DRAM_FREQ_NR] = {0x0081E01E}; -static u32 umc_directbusctrla[DRAM_CH_NR] = { - 0x00000000, 0x00000001, 0x00000001 -}; - -/* polling function for PHY Init Complete */ -static void ddrphy_init_complete(void __iomem *dc_base) +/* DDR PHY */ +static void ddrphy_select_lane(void __iomem *phy_base, unsigned int lane, + unsigned int bit) { - /* Wait for PHY Init Complete */ - while (!(readl(dc_base + UMC_DFISTCTLC) & BIT(0))) - cpu_relax(); + WARN_ON(lane >= (1 << PHY_LANE_SEL_LANE_WIDTH)); + WARN_ON(bit >= (1 << PHY_LANE_SEL_BIT_WIDTH)); + + writel((bit << PHY_LANE_SEL_BIT_SHIFT) | + (lane << PHY_LANE_SEL_LANE_SHIFT), + phy_base + PHY_LANE_SEL); } -/* DDR PHY */ -static void ddrphy_init(void __iomem *phy_base, void __iomem *dc_base, - enum dram_freq freq, enum dram_board board, int ch) +static void ddrphy_init(void __iomem *phy_base, enum dram_board board, int ch) { writel(0x0C001001, phy_base + PHY_UNIQUIFY_TSMC_IO_1); while (!(readl(phy_base + PHY_UNIQUIFY_TSMC_IO_1) & BIT(1))) @@ -352,100 +236,148 @@ static void ddrphy_init(void __iomem *phy_base, void __iomem *dc_base, writel(0x00000000, phy_base + PHY_DLL_INCR_TRIM_3); writel(0x00000000, phy_base + PHY_DLL_INCR_TRIM_1); - writel(0x00000000, phy_base + PHY_LANE_SEL); + ddrphy_select_lane(phy_base, 0, 0); writel(0x00000005, phy_base + PHY_DLL_TRIM_1); writel(0x0000000a, phy_base + PHY_DLL_TRIM_3); - writel(0x00000006, phy_base + PHY_LANE_SEL); + ddrphy_select_lane(phy_base, 6, 0); writel(0x00000005, phy_base + PHY_DLL_TRIM_1); writel(0x0000000a, phy_base + PHY_DLL_TRIM_3); - writel(0x0000000c, phy_base + PHY_LANE_SEL); + ddrphy_select_lane(phy_base, 12, 0); writel(0x00000005, phy_base + PHY_DLL_TRIM_1); writel(0x0000000a, phy_base + PHY_DLL_TRIM_3); - writel(0x00000012, phy_base + PHY_LANE_SEL); + ddrphy_select_lane(phy_base, 18, 0); writel(0x00000005, phy_base + PHY_DLL_TRIM_1); writel(0x0000000a, phy_base + PHY_DLL_TRIM_3); writel(0x00000001, phy_base + PHY_SCL_WINDOW_TRIM); writel(0x00000000, phy_base + PHY_UNQ_ANALOG_DLL_1); - writel(dio_phy_pad_ctrl[board][ch], phy_base + PHY_PAD_CTRL); + writel(ddrphy_phy_pad_ctrl[board][ch], phy_base + PHY_PAD_CTRL); writel(0x00000070, phy_base + PHY_VREF_TRAINING); writel(0x01000075, phy_base + PHY_SCL_CONFIG_1); writel(0x00000501, phy_base + PHY_SCL_CONFIG_2); writel(0x00000000, phy_base + PHY_SCL_CONFIG_3); writel(0x000261c0, phy_base + PHY_DYNAMIC_WRITE_BIT_LVL); writel(0x00000000, phy_base + PHY_SCL_CONFIG_4); - writel(dio_scl_gate_timing[ch], phy_base + PHY_SCL_GATE_TIMING); + writel(ddrphy_scl_gate_timing[ch], phy_base + PHY_SCL_GATE_TIMING); writel(0x02a000a0, phy_base + PHY_WRLVL_DYN_ODT); writel(0x00840004, phy_base + PHY_WRLVL_ON_OFF); writel(0x0000020d, phy_base + PHY_DLL_ADRCTRL); - writel(0x00000000, phy_base + PHY_LANE_SEL); + ddrphy_select_lane(phy_base, 0, 0); writel(0x0000008d, phy_base + PHY_DLL_TRIM_CLK); writel(0xa800100d, phy_base + PHY_DLL_RECALIB); writel(0x00005076, phy_base + PHY_SCL_LATENCY); +} - ddrphy_init_complete(dc_base); +static int ddrphy_to_dly_step(void __iomem *phy_base, unsigned int freq, + int delay) +{ + int mdl; + + mdl = (readl(phy_base + PHY_DLL_ADRCTRL) & PHY_DLL_ADRCTRL_MDL_MASK) >> + PHY_DLL_ADRCTRL_MDL_SHIFT; - ddrphy_set_dll_adrctrl(dio_adrctrl_0[board][ch], 0, phy_base); - ddrphy_set_dll_trim_clk(dio_dlltrimclk_0[board][ch], phy_base); - ddrphy_set_dll_recalib(dio_dllrecalib_0[board][ch], 0x10, 0, 0xa, - phy_base); + return DIV_ROUND_CLOSEST((long)freq * delay * mdl, 2 * 1000000L); } -static void ddrphy_shift_dq(u32 reg_mask, u32 reg_addr, int shift_val, - void __iomem *phy_base) +static void ddrphy_set_delay(void __iomem *phy_base, unsigned int reg, + u32 mask, u32 incr, int dly_step) { - u32 reg_val; - int dq_val; + u32 tmp; - reg_val = ddrphy_maskreadl(reg_mask, phy_base + reg_addr) & 0x7f; - dq_val = reg_val & 0x3f; + tmp = readl(phy_base + reg); + tmp &= ~mask; + tmp |= min_t(u32, abs(dly_step), mask); - if ((reg_val & 0x40) == 0x00) - dq_val = -1 * dq_val; + if (dly_step >= 0) + tmp |= incr; + else + tmp &= ~incr; - /* value shift*/ - dq_val = dq_val + shift_val; + writel(tmp, phy_base + reg); +} - if (dq_val >= 0) - reg_val = 0x40 + (dq_val & 0x3f); - else - reg_val = ((-1 * dq_val) & 0x3f); +static void ddrphy_set_dll_recalib(void __iomem *phy_base, int dly_step) +{ + ddrphy_set_delay(phy_base, PHY_DLL_RECALIB, + PHY_DLL_RECALIB_TRIM_MASK, PHY_DLL_RECALIB_INCR, + dly_step); +} - ddrphy_maskwritel(reg_val, reg_mask, phy_base + reg_addr); +static void ddrphy_set_dll_adrctrl(void __iomem *phy_base, int dly_step) +{ + ddrphy_set_delay(phy_base, PHY_DLL_ADRCTRL, + PHY_DLL_ADRCTRL_TRIM_MASK, PHY_DLL_ADRCTRL_INCR, + dly_step); } -static void ddrphy_shift(void __iomem *phy_base, enum dram_board board, int ch) +static void ddrphy_set_dll_trim_clk(void __iomem *phy_base, int dly_step) { - u32 dx, bit; + ddrphy_select_lane(phy_base, 0, 0); + + ddrphy_set_delay(phy_base, PHY_DLL_TRIM_CLK, + PHY_DLL_TRIM_CLK_MASK, PHY_DLL_TRIM_CLK_INCR, + dly_step); +} - /* set override = 1 */ - ddrphy_maskwritel(MSK_OVERRIDE, MSK_OVERRIDE, - phy_base + PHY_OP_DQ_DM_DQS_BITWISE_TRIM); - ddrphy_maskwritel(MSK_OVERRIDE, MSK_OVERRIDE, - phy_base + PHY_IP_DQ_DQS_BITWISE_TRIM); +static void ddrphy_init_tail(void __iomem *phy_base, enum dram_board board, + unsigned int freq, int ch) +{ + int step; - for (dx = 0; dx < 4; dx++) { - /* set byte to PHY_LANE_SEL.phy_lane_sel= dx * (PHY_BITLVL_DLY_WIDTH+1) */ - ddrphy_set_phy_lane_sel(dx * (PHY_BITLVL_DLY_WIDTH + 1), - phy_base); + step = ddrphy_to_dly_step(phy_base, freq, ddrphy_adrctrl[board][ch]); + ddrphy_set_dll_adrctrl(phy_base, step); + step = ddrphy_to_dly_step(phy_base, freq, ddrphy_dlltrimclk[board][ch]); + ddrphy_set_dll_trim_clk(phy_base, step); + + step = ddrphy_to_dly_step(phy_base, freq, ddrphy_dllrecalib[board][ch]); + ddrphy_set_dll_recalib(phy_base, step); +} + +static void ddrphy_shift_one_dq(void __iomem *phy_base, unsigned int reg, + u32 mask, u32 incr, int shift_val) +{ + u32 tmp; + int val; + + tmp = readl(phy_base + reg); + + val = tmp & mask; + if (!(tmp & incr)) + val = -val; + + val += shift_val; + + tmp &= ~(incr | mask); + tmp |= min_t(u32, abs(val), mask); + if (val >= 0) + tmp |= incr; + + writel(tmp, phy_base + reg); +} + +static void ddrphy_shift_dq(void __iomem *phy_base, unsigned int reg, + u32 mask, u32 incr, u32 override, + const int *shift_val_array) +{ + u32 tmp; + int dx, bit; + + tmp = readl(phy_base + reg); + tmp |= override; + writel(tmp, phy_base + reg); + + for (dx = 0; dx < 4; dx++) { for (bit = 0; bit < 8; bit++) { - ddrphy_set_bit_sel(bit, phy_base); - - /* shift write reg value*/ - ddrphy_shift_dq(MSK_OP_DQ_DM_DQS_BITWISE_TRIM, - PHY_OP_DQ_DM_DQS_BITWISE_TRIM, - dio_op_dq_shift_val[board][ch][dx * 8 + bit], - phy_base); - /* shift read reg value */ - ddrphy_shift_dq(MSK_IP_DQ_DQS_BITWISE_TRIM, - PHY_IP_DQ_DQS_BITWISE_TRIM, - dio_ip_dq_shift_val[board][ch][dx * 8 + bit], - phy_base); - } + ddrphy_select_lane(phy_base, + (PHY_BITLVL_DLY_WIDTH + 1) * dx, + bit); + ddrphy_shift_one_dq(phy_base, reg, mask, incr, + shift_val_array[dx * 8 + bit]); + } } - ddrphy_set_phy_lane_sel(0, phy_base); - ddrphy_set_bit_sel(0, phy_base); + + ddrphy_select_lane(phy_base, 0, 0); } static int ddrphy_training(void __iomem *phy_base, enum dram_board board, @@ -493,16 +425,90 @@ static int ddrphy_training(void __iomem *phy_base, enum dram_board board, writel(0x00003270, phy_base + PHY_DYNAMIC_BIT_LVL); writel(0x011BD0C4, phy_base + PHY_DSCL_CNT); - /* shift ip_dq, op_dq trim */ - ddrphy_shift(phy_base, board, ch); + /* shift ip_dq trim */ + ddrphy_shift_dq(phy_base, + PHY_IP_DQ_DQS_BITWISE_TRIM, + PHY_IP_DQ_DQS_BITWISE_TRIM_MASK, + PHY_IP_DQ_DQS_BITWISE_TRIM_INC, + PHY_IP_DQ_DQS_BITWISE_TRIM_OVERRIDE, + ddrphy_ip_dq_shift_val[board][ch]); + + /* shift op_dq trim */ + ddrphy_shift_dq(phy_base, + PHY_OP_DQ_DM_DQS_BITWISE_TRIM, + PHY_OP_DQ_DM_DQS_BITWISE_TRIM_MASK, + PHY_OP_DQ_DM_DQS_BITWISE_TRIM_INC, + PHY_OP_DQ_DM_DQS_BITWISE_TRIM_OVERRIDE, + ddrphy_op_dq_shift_val[board][ch]); + return 0; } -static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq, +/* UMC */ +static u32 umc_initctla[DRAM_FREQ_NR] = {0x71016D11}; +static u32 umc_initctlb[DRAM_FREQ_NR] = {0x07E390AC}; +static u32 umc_initctlc[DRAM_FREQ_NR] = {0x00FF00FF}; +static u32 umc_drmmr0[DRAM_FREQ_NR] = {0x00000114}; +static u32 umc_drmmr2[DRAM_FREQ_NR] = {0x000002a0}; + +static u32 umc_memconf0a[DRAM_FREQ_NR][DRAM_SZ_NR] = { + /* 256MB 512MB */ + {0x00000601, 0x00000801}, /* 1866 MHz */ +}; + +static u32 umc_memconf0b[DRAM_FREQ_NR][DRAM_SZ_NR] = { + /* 256MB 512MB */ + {0x00000120, 0x00000130}, /* 1866 MHz */ +}; + +static u32 umc_memconfch[DRAM_FREQ_NR][DRAM_SZ_NR] = { + /* 256MB 512MB */ + {0x00033603, 0x00033803}, /* 1866 MHz */ +}; + +static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060D0D20}; +static u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x2D211C08}; +static u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00150C04}; +static u32 umc_cmdctle[DRAM_FREQ_NR][DRAM_SZ_NR] = { + /* 256MB 512MB */ + {0x0049071D, 0x0078071D}, /* 1866 MHz */ +}; + +static u32 umc_rdatactl_d0[DRAM_FREQ_NR] = {0x00000610}; +static u32 umc_rdatactl_d1[DRAM_FREQ_NR] = {0x00000610}; +static u32 umc_wdatactl_d0[DRAM_FREQ_NR] = {0x00000204}; +static u32 umc_wdatactl_d1[DRAM_FREQ_NR] = {0x00000204}; +static u32 umc_odtctl_d0[DRAM_FREQ_NR] = {0x02000002}; +static u32 umc_odtctl_d1[DRAM_FREQ_NR] = {0x02000002}; +static u32 umc_dataset[DRAM_FREQ_NR] = {0x04000000}; + +static u32 umc_flowctla[DRAM_FREQ_NR] = {0x0081E01E}; +static u32 umc_directbusctrla[DRAM_CH_NR] = { + 0x00000000, 0x00000001, 0x00000001 +}; + +static void umc_poll_phy_init_complete(void __iomem *dc_base) +{ + /* Wait for PHY Init Complete */ + while (!(readl(dc_base + UMC_DFISTCTLC) & BIT(0))) + cpu_relax(); +} + +static int umc_dc_init(void __iomem *dc_base, unsigned int freq, unsigned long size, int ch) { + enum dram_freq freq_e; enum dram_size size_e; + switch (freq) { + case 1866: + freq_e = DRAM_FREQ_1866M; + break; + default: + pr_err("unsupported DRAM frequency %ud MHz\n", freq); + return -EINVAL; + } + switch (size) { case 0: return 0; @@ -521,40 +527,40 @@ static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq, writel(0x00000001, dc_base + UMC_DFICSOVRRD); writel(0x00000000, dc_base + UMC_DFITURNOFF); - writel(umc_initctla[freq], dc_base + UMC_INITCTLA); - writel(umc_initctlb[freq], dc_base + UMC_INITCTLB); - writel(umc_initctlc[freq], dc_base + UMC_INITCTLC); + writel(umc_initctla[freq_e], dc_base + UMC_INITCTLA); + writel(umc_initctlb[freq_e], dc_base + UMC_INITCTLB); + writel(umc_initctlc[freq_e], dc_base + UMC_INITCTLC); - writel(umc_drmmr0[freq], dc_base + UMC_DRMMR0); + writel(umc_drmmr0[freq_e], dc_base + UMC_DRMMR0); writel(0x00000004, dc_base + UMC_DRMMR1); - writel(umc_drmmr2[freq], dc_base + UMC_DRMMR2); + writel(umc_drmmr2[freq_e], dc_base + UMC_DRMMR2); writel(0x00000000, dc_base + UMC_DRMMR3); - writel(umc_memconf0a[freq][size_e], dc_base + UMC_MEMCONF0A); - writel(umc_memconf0b[freq][size_e], dc_base + UMC_MEMCONF0B); - writel(umc_memconfch[freq][size_e], dc_base + UMC_MEMCONFCH); + writel(umc_memconf0a[freq_e][size_e], dc_base + UMC_MEMCONF0A); + writel(umc_memconf0b[freq_e][size_e], dc_base + UMC_MEMCONF0B); + writel(umc_memconfch[freq_e][size_e], dc_base + UMC_MEMCONFCH); writel(0x00000008, dc_base + UMC_MEMMAPSET); - writel(umc_cmdctla[freq], dc_base + UMC_CMDCTLA); - writel(umc_cmdctlb[freq], dc_base + UMC_CMDCTLB); - writel(umc_cmdctlc[freq], dc_base + UMC_CMDCTLC); - writel(umc_cmdctle[freq][size_e], dc_base + UMC_CMDCTLE); + writel(umc_cmdctla[freq_e], dc_base + UMC_CMDCTLA); + writel(umc_cmdctlb[freq_e], dc_base + UMC_CMDCTLB); + writel(umc_cmdctlc[freq_e], dc_base + UMC_CMDCTLC); + writel(umc_cmdctle[freq_e][size_e], dc_base + UMC_CMDCTLE); - writel(umc_rdatactl_d0[freq], dc_base + UMC_RDATACTL_D0); - writel(umc_rdatactl_d1[freq], dc_base + UMC_RDATACTL_D1); + writel(umc_rdatactl_d0[freq_e], dc_base + UMC_RDATACTL_D0); + writel(umc_rdatactl_d1[freq_e], dc_base + UMC_RDATACTL_D1); - writel(umc_wdatactl_d0[freq], dc_base + UMC_WDATACTL_D0); - writel(umc_wdatactl_d1[freq], dc_base + UMC_WDATACTL_D1); - writel(umc_odtctl_d0[freq], dc_base + UMC_ODTCTL_D0); - writel(umc_odtctl_d1[freq], dc_base + UMC_ODTCTL_D1); - writel(umc_dataset[freq], dc_base + UMC_DATASET); + writel(umc_wdatactl_d0[freq_e], dc_base + UMC_WDATACTL_D0); + writel(umc_wdatactl_d1[freq_e], dc_base + UMC_WDATACTL_D1); + writel(umc_odtctl_d0[freq_e], dc_base + UMC_ODTCTL_D0); + writel(umc_odtctl_d1[freq_e], dc_base + UMC_ODTCTL_D1); + writel(umc_dataset[freq_e], dc_base + UMC_DATASET); writel(0x00400020, dc_base + UMC_DCCGCTL); writel(0x00000003, dc_base + UMC_ACSSETA); writel(0x00000103, dc_base + UMC_FLOWCTLG); writel(0x00010200, dc_base + UMC_ACSSETB); - writel(umc_flowctla[freq], dc_base + UMC_FLOWCTLA); + writel(umc_flowctla[freq_e], dc_base + UMC_FLOWCTLA); writel(0x00004444, dc_base + UMC_FLOWCTLC); writel(0x00000000, dc_base + UMC_DFICUPDCTLA); @@ -577,7 +583,7 @@ static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq, } static int umc_ch_init(void __iomem *umc_ch_base, void __iomem *phy_ch_base, - enum dram_freq freq, enum dram_board board, + enum dram_board board, unsigned int freq, unsigned long size, int ch) { void __iomem *dc_base = umc_ch_base + 0x00011000; @@ -591,7 +597,11 @@ static int umc_ch_init(void __iomem *umc_ch_base, void __iomem *phy_ch_base, writel(UMC_DIOCTLA_CTL_NRST | UMC_DIOCTLA_CFG_NRST, dc_base + UMC_DIOCTLA); - ddrphy_init(phy_base, dc_base, freq, board, ch); + ddrphy_init(phy_base, board, ch); + + umc_poll_phy_init_complete(dc_base); + + ddrphy_init_tail(phy_base, board, freq, ch); ret = umc_dc_init(dc_base, freq, size, ch); if (ret) @@ -624,19 +634,9 @@ int uniphier_ld20_umc_init(const struct uniphier_board_data *bd) void __iomem *um_base = (void __iomem *)0x5b600000; void __iomem *umc_ch_base = (void __iomem *)0x5b800000; void __iomem *phy_ch_base = (void __iomem *)0x6e200000; - enum dram_freq freq; enum dram_board board; int ch, ret; - switch (bd->dram_freq) { - case 1866: - freq = DRAM_FREQ_1866M; - break; - default: - pr_err("unsupported DRAM frequency %d MHz\n", bd->dram_freq); - return -EINVAL; - } - switch (UNIPHIER_BD_BOARD_GET_TYPE(bd->flags)) { case UNIPHIER_BD_BOARD_LD20_REF: board = DRAM_BOARD_LD20_REF; @@ -660,8 +660,8 @@ int uniphier_ld20_umc_init(const struct uniphier_board_data *bd) unsigned long size = bd->dram_ch[ch].size; unsigned int width = bd->dram_ch[ch].width; - ret = umc_ch_init(umc_ch_base, phy_ch_base, freq, board, - size / (width / 16), ch); + ret = umc_ch_init(umc_ch_base, phy_ch_base, board, + bd->dram_freq, size / (width / 16), ch); if (ret) { pr_err("failed to initialize UMC ch%d\n", ch); return ret; diff --git a/arch/arm/mach-uniphier/init/init-ld11.c b/arch/arm/mach-uniphier/init/init-ld11.c index e324c94700..fdb2838503 100644 --- a/arch/arm/mach-uniphier/init/init-ld11.c +++ b/arch/arm/mach-uniphier/init/init-ld11.c @@ -15,7 +15,9 @@ int uniphier_ld11_init(const struct uniphier_board_data *bd) { uniphier_sbc_init_savepin(bd); uniphier_pxs2_sbc_init(bd); - uniphier_pin_init("system_bus_grp"); + /* pins for NAND and System Bus are multiplexed */ + if (spl_boot_device() != BOOT_DEVICE_NAND) + uniphier_pin_init("system_bus_grp"); support_card_reset(); diff --git a/arch/arm/mach-uniphier/init/init-ld20.c b/arch/arm/mach-uniphier/init/init-ld20.c index cb05421252..37b860a8b4 100644 --- a/arch/arm/mach-uniphier/init/init-ld20.c +++ b/arch/arm/mach-uniphier/init/init-ld20.c @@ -15,7 +15,9 @@ int uniphier_ld20_init(const struct uniphier_board_data *bd) { uniphier_sbc_init_savepin(bd); uniphier_pxs2_sbc_init(bd); - uniphier_pin_init("system_bus_grp"); + /* pins for NAND and System Bus are multiplexed */ + if (spl_boot_device() != BOOT_DEVICE_NAND) + uniphier_pin_init("system_bus_grp"); support_card_reset(); diff --git a/arch/arm/mach-uniphier/micro-support-card.c b/arch/arm/mach-uniphier/micro-support-card.c index 04e6558e9b..e53bcdf8e3 100644 --- a/arch/arm/mach-uniphier/micro-support-card.c +++ b/arch/arm/mach-uniphier/micro-support-card.c @@ -60,9 +60,8 @@ void support_card_init(void) /* * After power on, we need to keep the LAN controller in reset state * for a while. (200 usec) - * Fortunately, enough wait time is already inserted in pll_init() - * function. So we do not have to wait here. */ + udelay(200); support_card_reset_deassert(); } diff --git a/arch/blackfin/include/asm/config.h b/arch/blackfin/include/asm/config.h index 3d98a00e9b..de3c97931d 100644 --- a/arch/blackfin/include/asm/config.h +++ b/arch/blackfin/include/asm/config.h @@ -171,7 +171,6 @@ } #endif -#define CONFIG_DISPLAY_CPUINFO #define CONFIG_ARCH_MISC_INIT #define CONFIG_CPU CONFIG_BFIN_CPU |