diff options
Diffstat (limited to 'arch')
25 files changed, 214 insertions, 43 deletions
diff --git a/arch/Kconfig b/arch/Kconfig index 96db5c5088b..afa1d6c2d78 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -18,7 +18,7 @@ config ARC config ARM bool "ARM architecture" - select HAVE_PRIVATE_LIBGCC + select HAVE_PRIVATE_LIBGCC if !ARM64 select HAVE_GENERIC_BOARD select SUPPORT_OF_CONTROL diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 192d9cf3f07..9908b430d62 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -589,10 +589,6 @@ config TARGET_TBS2910 bool "Support tbs2910" select CPU_V7 -config TARGET_TQMA6 - bool "TQ Systems TQMa6 board" - select CPU_V7 - config TARGET_OT1200 bool "Bachmann OT1200" select CPU_V7 @@ -976,7 +972,6 @@ source "board/ti/ti816x/Kconfig" source "board/timll/devkit3250/Kconfig" source "board/toradex/colibri_pxa270/Kconfig" source "board/toradex/colibri_vf/Kconfig" -source "board/tqc/tqma6/Kconfig" source "board/trizepsiv/Kconfig" source "board/ttcontrol/vision2/Kconfig" source "board/udoo/Kconfig" diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig index 1282be3418c..10908c4c4a2 100644 --- a/arch/arm/cpu/armv7/mx6/Kconfig +++ b/arch/arm/cpu/armv7/mx6/Kconfig @@ -33,11 +33,16 @@ config TARGET_SECOMX6 bool "Support secomx6 boards" select CPU_V7 +config TARGET_TQMA6 + bool "TQ Systems TQMa6 board" + select CPU_V7 + endchoice config SYS_SOC default "mx6" source "board/seco/Kconfig" +source "board/tqc/tqma6/Kconfig" endif diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index b21bd03a8aa..29de6243dc9 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -62,6 +62,7 @@ u32 get_cpu_rev(void) struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; u32 reg = readl(&anatop->digprog_sololite); u32 type = ((reg >> 16) & 0xff); + u32 major; if (type != MXC_CPU_MX6SL) { reg = readl(&anatop->digprog); @@ -79,8 +80,9 @@ u32 get_cpu_rev(void) } } + major = ((reg >> 8) & 0xff); reg &= 0xff; /* mx6 silicon revision */ - return (type << 12) | (reg + 0x10); + return (type << 12) | (reg + (0x10 * (major + 1))); } /* diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 5ed0f45a266..1c7e6f01f94 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -22,10 +22,9 @@ * * Startup Code (reset vector) * - * do important init only if we don't start from memory! - * setup Memory and board specific bits prior to relocation. - * relocate armboot to ram - * setup stack + * Do important init only if we don't start from memory! + * Setup memory and board specific bits prior to relocation. + * Relocate armboot to ram. Setup stack. * *************************************************************************/ diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index 03443629bcd..5f39aa07cfb 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -45,11 +45,11 @@ static int gpio_init(void) sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT); #endif #if defined(CONFIG_MACH_SUN8I) - sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0_TX); - sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0_RX); + sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0); #else - sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0_TX); - sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0_RX); + sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0); #endif sunxi_gpio_set_pull(SUNXI_GPF(4), 1); #elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)) @@ -64,6 +64,10 @@ static int gpio_init(void) sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0); sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP); +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33) + sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0); + sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0); + sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP); #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I) sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0); sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0); diff --git a/arch/arm/cpu/armv7/sunxi/rsb.c b/arch/arm/cpu/armv7/sunxi/rsb.c index f115a9cac41..6fd11f15298 100644 --- a/arch/arm/cpu/armv7/sunxi/rsb.c +++ b/arch/arm/cpu/armv7/sunxi/rsb.c @@ -60,11 +60,12 @@ int rsb_init(void) struct sunxi_rsb_reg * const rsb = (struct sunxi_rsb_reg *)SUNXI_RSB_BASE; - rsb_cfg_io(); - /* Enable RSB and PIO clk, and de-assert their resets */ prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_RSB); + /* Setup external pins */ + rsb_cfg_io(); + writel(RSB_CTRL_SOFT_RST, &rsb->ctrl); rsb_set_clk(); diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9c735c672ab..19e1de67a0b 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -128,7 +128,8 @@ dtb-$(CONFIG_MACH_SUN8I_A23) += \ dtb-$(CONFIG_MACH_SUN8I_A33) += \ sun8i-a33-et-q8-v1.6.dtb \ sun8i-a33-ga10h-v1.1.dtb \ - sun8i-a33-ippo-q8h-v1.2-lcd1024x600.dtb + sun8i-a33-ippo-q8h-v1.2.dtb \ + sun8i-a33-sinlinx-sina33.dtb dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ sun9i-a80-cubieboard4.dtb diff --git a/arch/arm/dts/sun8i-a23-a33.dtsi b/arch/arm/dts/sun8i-a23-a33.dtsi index faea94e45ee..7abd0ae3143 100644 --- a/arch/arm/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/dts/sun8i-a23-a33.dtsi @@ -366,6 +366,16 @@ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; }; + mmc2_8bit_pins: mmc2_8bit { + allwinner,pins = "PC5", "PC6", "PC8", + "PC9", "PC10", "PC11", + "PC12", "PC13", "PC14", + "PC15"; + allwinner,function = "mmc2"; + allwinner,drive = <SUN4I_PINCTRL_30_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + i2c0_pins_a: i2c0@0 { allwinner,pins = "PH2", "PH3"; allwinner,function = "i2c0"; diff --git a/arch/arm/dts/sun8i-a33-ippo-q8h-v1.2-lcd1024x600.dts b/arch/arm/dts/sun8i-a33-ippo-q8h-v1.2.dts index 97771495c21..97771495c21 100644 --- a/arch/arm/dts/sun8i-a33-ippo-q8h-v1.2-lcd1024x600.dts +++ b/arch/arm/dts/sun8i-a33-ippo-q8h-v1.2.dts diff --git a/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts b/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts new file mode 100644 index 00000000000..5788c29cb56 --- /dev/null +++ b/arch/arm/dts/sun8i-a33-sinlinx-sina33.dts @@ -0,0 +1,129 @@ +/* + * Copyright 2015 Chen-Yu Tsai + * + * Chen-Yu Tsai <wens@csie.org> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a33.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/sun4i-a10.h> + +/ { + model = "Sinlinx SinA33"; + compatible = "sinlinx,sina33", "allwinner,sun8i-a33"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&lradc { + vref-supply = <®_vcc3v0>; + status = "okay"; + + button@200 { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + channel = <0>; + voltage = <191011>; + }; + + button@400 { + label = "Volume Down"; + linux,code = <KEY_VOLUMEDOWN>; + channel = <0>; + voltage = <391304>; + }; + + button@600 { + label = "Home"; + linux,code = <KEY_HOME>; + channel = <0>; + voltage = <600000>; + }; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_sina33>; + vmmc-supply = <®_vcc3v0>; + bus-width = <4>; + cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ + cd-inverted; + status = "okay"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc3v0>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&mmc2_8bit_pins { + /* eMMC is missing pull-ups */ + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; +}; + +&pio { + mmc0_cd_pin_sina33: mmc0_cd_pin@0 { + allwinner,pins = "PB4"; + allwinner,function = "gpio_in"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_b>; + status = "okay"; +}; diff --git a/arch/arm/dts/sun8i-a33.dtsi b/arch/arm/dts/sun8i-a33.dtsi index 9b43bc6e792..85ee08098b7 100644 --- a/arch/arm/dts/sun8i-a33.dtsi +++ b/arch/arm/dts/sun8i-a33.dtsi @@ -86,4 +86,12 @@ compatible = "allwinner,sun8i-a33-pinctrl"; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + + uart0_pins_b: uart0@1 { + allwinner,pins = "PB0", "PB1"; + allwinner,function = "uart0"; + allwinner,drive = <SUN4I_PINCTRL_10_MA>; + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; + }; + }; diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c index e5229904539..c12556addfc 100644 --- a/arch/arm/imx-common/timer.c +++ b/arch/arm/imx-common/timer.c @@ -44,8 +44,8 @@ static inline int gpt_has_clk_source_osc(void) { #if defined(CONFIG_MX6) if (((is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) && - (is_soc_rev(CHIP_REV_1_0) > 0)) || is_cpu_type(MXC_CPU_MX6DL) || - is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX)) + (soc_rev() > CHIP_REV_1_0)) || is_cpu_type(MXC_CPU_MX6DL) || + is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX)) return 1; return 0; diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index f059d0f664b..5f0e1e63467 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -9,6 +9,8 @@ #define ARCH_MXC +#define CONFIG_SYS_CACHELINE_SIZE 64 + #if defined(CONFIG_MX51) #define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */ #define IPU_SOC_BASE_ADDR 0x40000000 diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 0d38d450daa..35a324cd532 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -312,6 +312,7 @@ #define CHIP_REV_1_0 0x10 #define CHIP_REV_1_2 0x12 #define CHIP_REV_1_5 0x15 +#define CHIP_REV_2_0 0x20 #ifndef CONFIG_MX6SX #define IRAM_SIZE 0x00040000 #else diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h index c5832912b42..28c77a498ea 100644 --- a/arch/arm/include/asm/arch-mx6/sys_proto.h +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h @@ -12,7 +12,7 @@ #include "../arch-imx/cpu.h" #define soc_rev() (get_cpu_rev() & 0xFF) -#define is_soc_rev(rev) (soc_rev() - rev) +#define is_soc_rev(rev) (soc_rev() == rev) u32 get_nr_cpus(void); u32 get_cpu_rev(void); @@ -20,7 +20,7 @@ u32 get_cpu_speed_grade_hz(void); u32 get_cpu_temp_grade(int *minc, int *maxc); /* returns MXC_CPU_ value */ -#define cpu_type(rev) (((rev) >> 12)&0xff) +#define cpu_type(rev) (((rev) >> 12) & 0xff) /* both macros return/take MXC_CPU_ constants */ #define get_cpu_type() (cpu_type(get_cpu_rev())) @@ -30,6 +30,10 @@ const char *get_imx_type(u32 imxtype); unsigned imx_ddr_size(void); void set_chipselect_size(int const); +#define is_mx6dqp() ((is_cpu_type(MXC_CPU_MX6Q) || \ + is_cpu_type(MXC_CPU_MX6D)) && \ + (soc_rev() >= CHIP_REV_2_0)) + /* * Initializes on-chip ethernet controllers. * to override, implement board_eth_init() diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index 496295d3573..8e67b3bcb87 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -156,6 +156,7 @@ enum sunxi_gpio_number { #define SUN4I_GPB_UART0 2 #define SUN5I_GPB_UART0 2 #define SUN8I_GPB_UART2 2 +#define SUN8I_A33_GPB_UART0 3 #define SUNXI_GPC_SDC2 3 #define SUN6I_GPC_SDC3 4 diff --git a/arch/arm/include/asm/u-boot.h b/arch/arm/include/asm/u-boot.h index ae4c21bf36a..43cc4946838 100644 --- a/arch/arm/include/asm/u-boot.h +++ b/arch/arm/include/asm/u-boot.h @@ -49,8 +49,4 @@ typedef struct bd_info { #define IH_ARCH_DEFAULT IH_ARCH_ARM64 #endif -#if defined(CONFIG_USE_PRIVATE_LIBGCC) && defined(CONFIG_SYS_THUMB_BUILD) -#error Thumb build does not work with private libgcc. -#endif - #endif /* _U_BOOT_H_ */ diff --git a/arch/arm/lib/_ashldi3.S b/arch/arm/lib/_ashldi3.S index 2c26f84ac70..9c34c212cb0 100644 --- a/arch/arm/lib/_ashldi3.S +++ b/arch/arm/lib/_ashldi3.S @@ -4,6 +4,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include <linux/linkage.h> + #ifdef __ARMEB__ #define al r1 #define ah r0 @@ -13,9 +15,8 @@ #endif .globl __ashldi3 -.globl __aeabi_llsl __ashldi3: -__aeabi_llsl: +ENTRY(__aeabi_llsl) subs r3, r2, #32 rsb ip, r2, #32 @@ -24,3 +25,4 @@ __aeabi_llsl: orrmi ah, ah, al, lsr ip mov al, al, lsl r2 mov pc, lr +ENDPROC(__aeabi_llsl) diff --git a/arch/arm/lib/_ashrdi3.S b/arch/arm/lib/_ashrdi3.S index 4d93c8a5e6c..c74fd644993 100644 --- a/arch/arm/lib/_ashrdi3.S +++ b/arch/arm/lib/_ashrdi3.S @@ -4,6 +4,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include <linux/linkage.h> + #ifdef __ARMEB__ #define al r1 #define ah r0 @@ -13,9 +15,8 @@ #endif .globl __ashrdi3 -.globl __aeabi_lasr __ashrdi3: -__aeabi_lasr: +ENTRY(__aeabi_lasr) subs r3, r2, #32 rsb ip, r2, #32 @@ -24,3 +25,4 @@ __aeabi_lasr: orrmi al, al, ah, lsl ip mov ah, ah, asr r2 mov pc, lr +ENDPROC(__aeabi_lasr) diff --git a/arch/arm/lib/_divsi3.S b/arch/arm/lib/_divsi3.S index 601549304e0..c463c68f85e 100644 --- a/arch/arm/lib/_divsi3.S +++ b/arch/arm/lib/_divsi3.S @@ -1,3 +1,5 @@ +#include <linux/linkage.h> + .macro ARM_DIV_BODY dividend, divisor, result, curbit #if __LINUX_ARM_ARCH__ >= 5 @@ -95,9 +97,8 @@ .align 5 .globl __divsi3 -.globl __aeabi_idiv __divsi3: -__aeabi_idiv: +ENTRY(__aeabi_idiv) cmp r1, #0 eor ip, r0, r1 @ save the sign of the result. beq Ldiv0 @@ -139,3 +140,4 @@ Ldiv0: bl __div0 mov r0, #0 @ About as wrong as it could be. ldr pc, [sp], #4 +ENDPROC(__aeabi_idiv) diff --git a/arch/arm/lib/_lshrdi3.S b/arch/arm/lib/_lshrdi3.S index 33296a0a93e..1f9b9164649 100644 --- a/arch/arm/lib/_lshrdi3.S +++ b/arch/arm/lib/_lshrdi3.S @@ -4,6 +4,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include <linux/linkage.h> + #ifdef __ARMEB__ #define al r1 #define ah r0 @@ -13,9 +15,8 @@ #endif .globl __lshrdi3 -.globl __aeabi_llsr __lshrdi3: -__aeabi_llsr: +ENTRY(__aeabi_llsr) subs r3, r2, #32 rsb ip, r2, #32 @@ -24,3 +25,4 @@ __aeabi_llsr: orrmi al, al, ah, lsl ip mov ah, ah, lsr r2 mov pc, lr +ENDPROC(__aeabi_llsr) diff --git a/arch/arm/lib/_modsi3.S b/arch/arm/lib/_modsi3.S index 3d31a559f84..c5e1c229dfb 100644 --- a/arch/arm/lib/_modsi3.S +++ b/arch/arm/lib/_modsi3.S @@ -1,3 +1,5 @@ +#include <linux/linkage.h> + .macro ARM_MOD_BODY dividend, divisor, order, spare #if __LINUX_ARM_ARCH__ >= 5 @@ -69,8 +71,7 @@ .endm .align 5 -.globl __modsi3 -__modsi3: +ENTRY(__modsi3) cmp r1, #0 beq Ldiv0 rsbmi r1, r1, #0 @ loops below use unsigned. @@ -88,7 +89,7 @@ __modsi3: 10: cmp ip, #0 rsbmi r0, r0, #0 mov pc, lr - +ENDPROC(__modsi3) Ldiv0: diff --git a/arch/arm/lib/_udivsi3.S b/arch/arm/lib/_udivsi3.S index 13098026104..3b653bed99d 100644 --- a/arch/arm/lib/_udivsi3.S +++ b/arch/arm/lib/_udivsi3.S @@ -1,3 +1,5 @@ +#include <linux/linkage.h> + /* # 1 "libgcc1.S" */ @ libgcc1 routines for ARM cpu. @ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk) @@ -72,8 +74,7 @@ Ldiv0: ldmia sp!, {pc} .size __udivsi3 , . - __udivsi3 -.globl __aeabi_uidivmod -__aeabi_uidivmod: +ENTRY(__aeabi_uidivmod) stmfd sp!, {r0, r1, ip, lr} bl __aeabi_uidiv @@ -81,9 +82,9 @@ __aeabi_uidivmod: mul r3, r0, r2 sub r1, r1, r3 mov pc, lr +ENDPROC(__aeabi_uidivmod) -.globl __aeabi_idivmod -__aeabi_idivmod: +ENTRY(__aeabi_idivmod) stmfd sp!, {r0, r1, ip, lr} bl __aeabi_idiv @@ -91,3 +92,4 @@ __aeabi_idivmod: mul r3, r0, r2 sub r1, r1, r3 mov pc, lr +ENDPROC(__aeabi_idivmod) diff --git a/arch/arm/lib/_umodsi3.S b/arch/arm/lib/_umodsi3.S index 8465ef09d23..b1667376c58 100644 --- a/arch/arm/lib/_umodsi3.S +++ b/arch/arm/lib/_umodsi3.S @@ -1,3 +1,5 @@ +#include <linux/linkage.h> + /* # 1 "libgcc1.S" */ @ libgcc1 routines for ARM cpu. @ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk) @@ -11,10 +13,9 @@ curbit .req r3 /* lr .req r14 */ /* pc .req r15 */ .text - .globl __umodsi3 .type __umodsi3 ,function .align 0 - __umodsi3 : + ENTRY(__umodsi3) cmp divisor, #0 beq Ldiv0 mov curbit, #1 @@ -86,3 +87,4 @@ Ldiv0: /* # 456 "libgcc1.S" */ /* # 500 "libgcc1.S" */ /* # 580 "libgcc1.S" */ +ENDPROC(__umodsi3) |