diff options
Diffstat (limited to 'arch')
22 files changed, 185 insertions, 85 deletions
diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile b/arch/arm/cpu/armv7/ls102xa/Makefile index f8300c77754..0c1596f3308 100644 --- a/arch/arm/cpu/armv7/ls102xa/Makefile +++ b/arch/arm/cpu/armv7/ls102xa/Makefile @@ -10,7 +10,6 @@ obj-y += timer.o obj-y += fsl_epu.o obj-y += soc.o -obj-$(CONFIG_SCSI_AHCI_PLAT) += ls102xa_sata.o obj-$(CONFIG_OF_LIBFDT) += fdt.o obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o obj-$(CONFIG_SPL) += spl.o diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c index af413f8622c..bb169aaaf4b 100644 --- a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c +++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c @@ -73,6 +73,7 @@ static void __secure ls1_deepsleep_irq_cfg(void) * read, that is why we don't read it from register ippdexpcr1 itself. */ ippdexpcr1 = in_le32(&scfg->sparecr[7]); + out_be32(&rcpm->ippdexpcr1, ippdexpcr1); if (ippdexpcr0 & RCPM_IPPDEXPCR0_ETSEC) pmcintecr |= SCFG_PMCINTECR_ETSECRXG0 | @@ -192,6 +193,9 @@ static void __secure ls1_deep_sleep(u32 entry_point) setbits_be32(&scfg->dpslpcr, SCFG_DPSLPCR_WDRR_EN); setbits_be32(&gur->crstsr, DCFG_CRSTSR_WDRFR); + /* Disable QE */ + setbits_be32(&gur->devdisr, CCSR_DEVDISR1_QE); + ls1_deepsleep_irq_cfg(); psci_v7_flush_dcache_all(); diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c deleted file mode 100644 index c9fe7522fb1..00000000000 --- a/arch/arm/cpu/armv7/ls102xa/ls102xa_sata.c +++ /dev/null @@ -1,41 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - */ -#include <common.h> -#include <asm/io.h> -#include <asm/arch/immap_ls102xa.h> -#include <ahci.h> -#include <scsi.h> - -/* port register default value */ -#define AHCI_PORT_PHY_1_CFG 0xa003fffe -#define AHCI_PORT_PHY_2_CFG 0x28183414 -#define AHCI_PORT_PHY_3_CFG 0x0e080e06 -#define AHCI_PORT_PHY_4_CFG 0x064a080b -#define AHCI_PORT_PHY_5_CFG 0x2aa86470 -#define AHCI_PORT_TRANS_CFG 0x08000029 - -#define SATA_ECC_REG_ADDR 0x20220520 -#define SATA_ECC_DISABLE 0x00020000 - -int ls1021a_sata_init(void) -{ - struct ccsr_ahci __iomem *ccsr_ahci = (void *)AHCI_BASE_ADDR; - -#ifdef CONFIG_SYS_FSL_ERRATUM_A008407 - out_le32((void *)SATA_ECC_REG_ADDR, SATA_ECC_DISABLE); -#endif - - out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); - out_le32(&ccsr_ahci->pp2c, AHCI_PORT_PHY_2_CFG); - out_le32(&ccsr_ahci->pp3c, AHCI_PORT_PHY_3_CFG); - out_le32(&ccsr_ahci->pp4c, AHCI_PORT_PHY_4_CFG); - out_le32(&ccsr_ahci->pp5c, AHCI_PORT_PHY_5_CFG); - out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); - - ahci_init((void __iomem *)AHCI_BASE_ADDR); - scsi_scan(false); - - return 0; -} diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index 5d6f68aad67..91fdbad8be0 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -29,6 +29,7 @@ endif ifneq ($(CONFIG_ARCH_LS1043A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o obj-$(CONFIG_ARMV8_PSCI) += ls1043a_psci.o +obj-y += icid.o ls1043_ids.o endif ifneq ($(CONFIG_ARCH_LS1012A),) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index 653c6dddcaf..bc268e207c8 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -192,6 +192,16 @@ int get_dspi_freq(ulong dummy) return get_bus_freq(0) / CONFIG_SYS_FSL_DSPI_CLK_DIV; } +#ifdef CONFIG_FSL_ESDHC +int get_sdhc_freq(ulong dummy) +{ + if (!gd->arch.sdhc_clk) + get_clocks(); + + return gd->arch.sdhc_clk; +} +#endif + int get_serial_clock(void) { return get_bus_freq(0) / CONFIG_SYS_FSL_DUART_CLK_DIV; @@ -202,6 +212,10 @@ unsigned int mxc_get_clock(enum mxc_clock clk) switch (clk) { case MXC_I2C_CLK: return get_i2c_freq(0); +#if defined(CONFIG_FSL_ESDHC) + case MXC_ESDHC_CLK: + return get_sdhc_freq(0); +#endif case MXC_DSPI_CLK: return get_dspi_freq(0); default: diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c new file mode 100644 index 00000000000..0e8649427e9 --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include <common.h> +#include <asm/arch-fsl-layerscape/immap_lsch2.h> +#include <asm/arch-fsl-layerscape/fsl_icid.h> +#include <asm/arch-fsl-layerscape/fsl_portals.h> +#include <fsl_sec.h> + +#ifdef CONFIG_SYS_DPAA_QBMAN +struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), + SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0), +}; +#endif + +struct icid_id_table icid_tbl[] = { +#ifdef CONFIG_SYS_DPAA_QBMAN + SET_QMAN_ICID(FSL_DPAA1_STREAM_ID_START), + SET_BMAN_ICID(FSL_DPAA1_STREAM_ID_START + 1), +#endif + + SET_SDHC_ICID(FSL_SDHC_STREAM_ID), + + SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID), + SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID), + SET_USB_ICID(3, "snps,dwc3", FSL_USB3_STREAM_ID), + + SET_SATA_ICID("fsl,ls1043a-ahci", FSL_SATA_STREAM_ID), + SET_QDMA_ICID("fsl,ls1043a-qdma", FSL_QDMA_STREAM_ID), + SET_EDMA_ICID(FSL_EDMA_STREAM_ID), + SET_ETR_ICID(FSL_ETR_STREAM_ID), + SET_DEBUG_ICID(FSL_DEBUG_STREAM_ID), + SET_QE_ICID(FSL_QE_STREAM_ID), +#ifdef CONFIG_FSL_CAAM + SET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_START + 2), + SET_SEC_JR_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 3), + SET_SEC_JR_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 4), + SET_SEC_JR_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 5), + SET_SEC_JR_ICID_ENTRY(3, FSL_DPAA1_STREAM_ID_START + 6), + SET_SEC_RTIC_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 7), + SET_SEC_RTIC_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 8), + SET_SEC_RTIC_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 9), + SET_SEC_RTIC_ICID_ENTRY(3, FSL_DPAA1_STREAM_ID_START + 10), + SET_SEC_DECO_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 11), + SET_SEC_DECO_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 12), +#endif +}; + +int icid_tbl_sz = ARRAY_SIZE(icid_tbl); + +#ifdef CONFIG_SYS_DPAA_FMAN +struct fman_icid_id_table fman_icid_tbl[] = { + /* port id, icid */ + SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x03, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x04, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x05, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x06, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x07, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x08, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x09, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x0a, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x0b, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x0c, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x0d, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x28, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x29, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x2a, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x2b, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x2c, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x2d, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x10, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x11, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x30, FSL_DPAA1_STREAM_ID_END), + SET_FMAN_ICID_ENTRY(0x31, FSL_DPAA1_STREAM_ID_END), +}; + +int fman_icid_tbl_sz = ARRAY_SIZE(fman_icid_tbl); +#endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c index a31c4d93ab2..d391f930415 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c @@ -99,7 +99,7 @@ int ppa_init(void) cnt = DIV_ROUND_UP(fdt_header_len, 512); debug("%s: MMC read PPA FIT header: dev # %u, block # %u, count %u\n", __func__, dev, blk, cnt); - ret = mmc->block_dev.block_read(&mmc->block_dev, blk, cnt, fitp); + ret = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, fitp); if (ret != cnt) { free(fitp); printf("MMC/SD read of PPA FIT header at offset 0x%x failed\n", @@ -123,7 +123,7 @@ int ppa_init(void) blk = CONFIG_SYS_LS_PPA_ESBC_ADDR >> 9; cnt = DIV_ROUND_UP(CONFIG_LS_PPA_ESBC_HDR_SIZE, 512); - ret = mmc->block_dev.block_read(&mmc->block_dev, blk, cnt, ppa_hdr_ddr); + ret = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, ppa_hdr_ddr); if (ret != cnt) { free(ppa_hdr_ddr); printf("MMC/SD read of PPA header failed\n"); @@ -149,8 +149,7 @@ int ppa_init(void) cnt = DIV_ROUND_UP(fw_length, 512); debug("%s: MMC read PPA FIT image: dev # %u, block # %u, count %u\n", __func__, dev, blk, cnt); - ret = mmc->block_dev.block_read(&mmc->block_dev, - blk, cnt, ppa_fit_addr); + ret = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, ppa_fit_addr); if (ret != cnt) { free(ppa_fit_addr); printf("MMC/SD read of PPA FIT header at offset 0x%x failed\n", diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 3f15cb08ffb..54fb0745f90 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -634,7 +634,7 @@ void fsl_lsch2_early_init_f(void) erratum_a008997(); erratum_a009007(); -#ifdef CONFIG_ARCH_LS1046A +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) set_icids(); #endif } diff --git a/arch/arm/dts/fsl-ls1043a-qds.dtsi b/arch/arm/dts/fsl-ls1043a-qds.dtsi index addb9abfb93..3841aee11e4 100644 --- a/arch/arm/dts/fsl-ls1043a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1043a-qds.dtsi @@ -174,3 +174,7 @@ &lpuart0 { status = "okay"; }; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi index ff401222ff2..bb70992f9e7 100644 --- a/arch/arm/dts/fsl-ls1043a.dtsi +++ b/arch/arm/dts/fsl-ls1043a.dtsi @@ -70,6 +70,14 @@ status = "disabled"; }; + esdhc: esdhc@1560000 { + compatible = "fsl,esdhc"; + reg = <0x0 0x1560000 0x0 0x10000>; + interrupts = <0 62 0x4>; + big-endian; + bus-width = <4>; + }; + ifc: ifc@1530000 { compatible = "fsl,ifc", "simple-bus"; reg = <0x0 0x1530000 0x0 0x10000>; @@ -279,5 +287,13 @@ ranges = <0x81000000 0x0 0x00000000 0x50 0x00020000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ }; + + sata: sata@3200000 { + compatible = "fsl,ls1043a-ahci"; + reg = <0x0 0x3200000 0x0 0x10000>; + interrupts = <0 69 4>; + clocks = <&clockgen 4 0>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi index 4acbaf78e80..7687d12091b 100644 --- a/arch/arm/dts/fsl-ls1046a.dtsi +++ b/arch/arm/dts/fsl-ls1046a.dtsi @@ -70,6 +70,14 @@ status = "disabled"; }; + esdhc: esdhc@1560000 { + compatible = "fsl,esdhc"; + reg = <0x0 0x1560000 0x0 0x10000>; + interrupts = <0 62 0x4>; + big-endian; + bus-width = <4>; + }; + ifc: ifc@1530000 { compatible = "fsl,ifc", "simple-bus"; reg = <0x0 0x1530000 0x0 0x10000>; diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi index 077caf3cc21..72d755a18ce 100644 --- a/arch/arm/dts/fsl-ls1088a.dtsi +++ b/arch/arm/dts/fsl-ls1088a.dtsi @@ -74,6 +74,15 @@ reg-names = "QuadSPI", "QuadSPI-memory"; num-cs = <4>; }; + + esdhc: esdhc@2140000 { + compatible = "fsl,esdhc"; + reg = <0x0 0x2140000 0x0 0x10000>; + interrupts = <0 28 0x4>; /* Level high type */ + little-endian; + bus-width = <4>; + }; + ifc: ifc@1530000 { compatible = "fsl,ifc", "simple-bus"; reg = <0x0 0x2240000 0x0 0x20000>; diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi index b0f85170b0c..2d537ae6060 100644 --- a/arch/arm/dts/fsl-ls2080a.dtsi +++ b/arch/arm/dts/fsl-ls2080a.dtsi @@ -75,6 +75,14 @@ num-cs = <4>; }; + esdhc: esdhc@0 { + compatible = "fsl,esdhc"; + reg = <0x0 0x2140000 0x0 0x10000>; + interrupts = <0 28 0x4>; /* Level high type */ + little-endian; + bus-width = <4>; + }; + usb0: usb3@3100000 { compatible = "fsl,layerscape-dwc3"; reg = <0x0 0x3100000 0x0 0x10000>; diff --git a/arch/arm/dts/ls1021a-qds.dtsi b/arch/arm/dts/ls1021a-qds.dtsi index fb1af1568bc..47c128f16ff 100644 --- a/arch/arm/dts/ls1021a-qds.dtsi +++ b/arch/arm/dts/ls1021a-qds.dtsi @@ -212,3 +212,7 @@ &uart1 { status = "okay"; }; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/dts/ls1021a-twr.dtsi b/arch/arm/dts/ls1021a-twr.dtsi index 63f2079ed35..14e0ceafe78 100644 --- a/arch/arm/dts/ls1021a-twr.dtsi +++ b/arch/arm/dts/ls1021a-twr.dtsi @@ -103,3 +103,7 @@ &uart1 { status = "okay"; }; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi index 5b3fc6ad44d..7670a39617c 100644 --- a/arch/arm/dts/ls1021a.dtsi +++ b/arch/arm/dts/ls1021a.dtsi @@ -96,7 +96,6 @@ sdhci,auto-cmd12; big-endian; bus-width = <4>; - status = "disabled"; }; scfg: scfg@1570000 { @@ -404,5 +403,12 @@ ranges = <0x81000000 0x0 0x00000000 0x34020000 0x0 0x00010000 /* downstream I/O */ 0x82000000 0x0 0x38000000 0x38000000 0x0 0x08000000>; /* non-prefetchable memory */ }; + + sata: sata@3200000 { + compatible = "fsl,ls1021a-ahci"; + reg = <0x3200000 0x10000>; + interrupts = <0 101 4>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 8a051481365..bd4ca88e166 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -195,6 +195,7 @@ /* SoC related */ #ifdef CONFIG_ARCH_LS1043A #define CONFIG_SYS_FMAN_V3 +#define CONFIG_SYS_FSL_QMAN_V3 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 7 #define CONFIG_SYS_NUM_FM1_10GEC 1 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h index a70c866651a..a3f473fe28b 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h @@ -68,6 +68,10 @@ void fdt_fixup_icid(void *blob); #define SET_DEBUG_ICID(streamid) \ SET_SCFG_ICID(NULL, streamid, debug_icid, 0) +#define SET_QE_ICID(streamid) \ + SET_SCFG_ICID("fsl,qe", streamid, qe_icid,\ + QE_BASE_ADDR) + #define SET_QMAN_ICID(streamid) \ SET_ICID_ENTRY("fsl,qman", streamid, streamid, \ offsetof(struct ccsr_qman, liodnr) + \ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index be0a6ae363f..8c10526a6cf 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -85,6 +85,8 @@ #define GPIO3_BASE_ADDR (CONFIG_SYS_IMMR + 0x1320000) #define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x1330000) +#define QE_BASE_ADDR (CONFIG_SYS_IMMR + 0x1400000) + #define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000) #define EDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x01c00000) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h index afea9b8da85..8d002da3eda 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -35,6 +35,9 @@ * -DPAA2 * -u-boot will allocate a range of stream IDs to be used by the Management * Complex for containers and will set these values in the MC DPC image. + * -u-boot will fixup the iommu-map property in the fsl-mc node in the + * device tree (see Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt + * for more info on the msi-map definition) * -the MC is responsible for allocating and setting up 'isolation context * IDs (ICIDs) based on the allocated stream IDs for all DPAA2 devices. * diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h index 13a282ffe1b..137cd618049 100644 --- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h @@ -86,6 +86,8 @@ struct sys_info { unsigned long freq_localbus; }; +#define CCSR_DEVDISR1_QE 0x00000001 + /* Device Configuration and Pin Control */ struct ccsr_gur { u32 porsr1; /* POR status 1 */ @@ -389,33 +391,6 @@ struct ccsr_serdes { u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */ }; - - -/* AHCI (sata) register map */ -struct ccsr_ahci { - u32 res1[0xa4/4]; /* 0x0 - 0xa4 */ - u32 pcfg; /* port config */ - u32 ppcfg; /* port phy1 config */ - u32 pp2c; /* port phy2 config */ - u32 pp3c; /* port phy3 config */ - u32 pp4c; /* port phy4 config */ - u32 pp5c; /* port phy5 config */ - u32 paxic; /* port AXI config */ - u32 axicc; /* AXI cache control */ - u32 axipc; /* AXI PROT control */ - u32 ptc; /* port Trans Config */ - u32 pts; /* port Trans Status */ - u32 plc; /* port link config */ - u32 plc1; /* port link config1 */ - u32 plc2; /* port link config2 */ - u32 pls; /* port link status */ - u32 pls1; /* port link status1 */ - u32 pcmdc; /* port CMD config */ - u32 ppcs; /* port phy control status */ - u32 pberr; /* port 0/1 BIST error */ - u32 cmds; /* port 0/1 CMD status error */ -}; - #define RCPM_POWMGTCSR 0x130 #define RCPM_POWMGTCSR_SERDES_PW 0x80000000 #define RCPM_POWMGTCSR_LPM20_REQ 0x00100000 diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_sata.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_sata.h deleted file mode 100644 index 3acc5af6f2e..00000000000 --- a/arch/arm/include/asm/arch-ls102xa/ls102xa_sata.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - */ - -#ifndef __FSL_SATA_H_ -#define __FSL_SATA_H_ - -int ls1021a_sata_init(void); -#endif |