diff options
Diffstat (limited to 'arch/x86/include/asm')
-rw-r--r-- | arch/x86/include/asm/arch-coreboot/gpio.h | 5 | ||||
-rw-r--r-- | arch/x86/include/asm/arch-ivybridge/pch.h | 16 | ||||
-rw-r--r-- | arch/x86/include/asm/global_data.h | 1 | ||||
-rw-r--r-- | arch/x86/include/asm/gpio.h | 142 |
4 files changed, 158 insertions, 6 deletions
diff --git a/arch/x86/include/asm/arch-coreboot/gpio.h b/arch/x86/include/asm/arch-coreboot/gpio.h index 3ec18168339..4951a8c9574 100644 --- a/arch/x86/include/asm/arch-coreboot/gpio.h +++ b/arch/x86/include/asm/arch-coreboot/gpio.h @@ -7,9 +7,4 @@ #ifndef _X86_ARCH_GPIO_H_ #define _X86_ARCH_GPIO_H_ -struct ich6_bank_platdata { - uint32_t base_addr; - const char *bank_name; -}; - #endif /* _X86_ARCH_GPIO_H_ */ diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h index 290a737b020..ae338e3d92a 100644 --- a/arch/x86/include/asm/arch-ivybridge/pch.h +++ b/arch/x86/include/asm/arch-ivybridge/pch.h @@ -142,6 +142,22 @@ #define FD2 0x3428 /* 32bit */ #define CG 0x341c /* 32bit */ +/* ICH7 GPIOBASE */ +#define GPIO_USE_SEL 0x00 +#define GP_IO_SEL 0x04 +#define GP_LVL 0x0c +#define GPO_BLINK 0x18 +#define GPI_INV 0x2c +#define GPIO_USE_SEL2 0x30 +#define GP_IO_SEL2 0x34 +#define GP_LVL2 0x38 +#define GPIO_USE_SEL3 0x40 +#define GP_IO_SEL3 0x44 +#define GP_LVL3 0x48 +#define GP_RST_SEL1 0x60 +#define GP_RST_SEL2 0x64 +#define GP_RST_SEL3 0x68 + /* ICH7 PMBASE */ #define PM1_STS 0x00 #define WAK_STS (1 << 15) diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index ff9574c4cd8..4ea46d79eb2 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -33,6 +33,7 @@ struct arch_global_data { uint32_t bist; /* Built-in self test value */ struct pci_controller *hose; /* PCI hose for early use */ enum pei_boot_mode_t pei_boot_mode; + const struct pch_gpio_map *gpio_map; /* board GPIO map */ }; #endif diff --git a/arch/x86/include/asm/gpio.h b/arch/x86/include/asm/gpio.h index 8bda414dbd7..5540d422b4a 100644 --- a/arch/x86/include/asm/gpio.h +++ b/arch/x86/include/asm/gpio.h @@ -1,12 +1,152 @@ /* * Copyright (c) 2012, Google Inc. All rights reserved. - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _X86_GPIO_H_ #define _X86_GPIO_H_ +#include <linux/compiler.h> #include <asm/arch/gpio.h> #include <asm-generic/gpio.h> +struct ich6_bank_platdata { + uint32_t base_addr; + const char *bank_name; +}; + +#define GPIO_MODE_NATIVE 0 +#define GPIO_MODE_GPIO 1 +#define GPIO_MODE_NONE 1 + +#define GPIO_DIR_OUTPUT 0 +#define GPIO_DIR_INPUT 1 + +#define GPIO_NO_INVERT 0 +#define GPIO_INVERT 1 + +#define GPIO_LEVEL_LOW 0 +#define GPIO_LEVEL_HIGH 1 + +#define GPIO_NO_BLINK 0 +#define GPIO_BLINK 1 + +#define GPIO_RESET_PWROK 0 +#define GPIO_RESET_RSMRST 1 + +struct pch_gpio_set1 { + u32 gpio0:1; + u32 gpio1:1; + u32 gpio2:1; + u32 gpio3:1; + u32 gpio4:1; + u32 gpio5:1; + u32 gpio6:1; + u32 gpio7:1; + u32 gpio8:1; + u32 gpio9:1; + u32 gpio10:1; + u32 gpio11:1; + u32 gpio12:1; + u32 gpio13:1; + u32 gpio14:1; + u32 gpio15:1; + u32 gpio16:1; + u32 gpio17:1; + u32 gpio18:1; + u32 gpio19:1; + u32 gpio20:1; + u32 gpio21:1; + u32 gpio22:1; + u32 gpio23:1; + u32 gpio24:1; + u32 gpio25:1; + u32 gpio26:1; + u32 gpio27:1; + u32 gpio28:1; + u32 gpio29:1; + u32 gpio30:1; + u32 gpio31:1; +} __packed; + +struct pch_gpio_set2 { + u32 gpio32:1; + u32 gpio33:1; + u32 gpio34:1; + u32 gpio35:1; + u32 gpio36:1; + u32 gpio37:1; + u32 gpio38:1; + u32 gpio39:1; + u32 gpio40:1; + u32 gpio41:1; + u32 gpio42:1; + u32 gpio43:1; + u32 gpio44:1; + u32 gpio45:1; + u32 gpio46:1; + u32 gpio47:1; + u32 gpio48:1; + u32 gpio49:1; + u32 gpio50:1; + u32 gpio51:1; + u32 gpio52:1; + u32 gpio53:1; + u32 gpio54:1; + u32 gpio55:1; + u32 gpio56:1; + u32 gpio57:1; + u32 gpio58:1; + u32 gpio59:1; + u32 gpio60:1; + u32 gpio61:1; + u32 gpio62:1; + u32 gpio63:1; +} __packed; + +struct pch_gpio_set3 { + u32 gpio64:1; + u32 gpio65:1; + u32 gpio66:1; + u32 gpio67:1; + u32 gpio68:1; + u32 gpio69:1; + u32 gpio70:1; + u32 gpio71:1; + u32 gpio72:1; + u32 gpio73:1; + u32 gpio74:1; + u32 gpio75:1; +} __packed; + +/* + * This hilariously complex structure came from Coreboot. The + * setup_pch_gpios() function uses it. It could be move to device tree, or + * adjust to use masks instead of bitfields. + */ +struct pch_gpio_map { + struct { + const struct pch_gpio_set1 *mode; + const struct pch_gpio_set1 *direction; + const struct pch_gpio_set1 *level; + const struct pch_gpio_set1 *reset; + const struct pch_gpio_set1 *invert; + const struct pch_gpio_set1 *blink; + } set1; + struct { + const struct pch_gpio_set2 *mode; + const struct pch_gpio_set2 *direction; + const struct pch_gpio_set2 *level; + const struct pch_gpio_set2 *reset; + } set2; + struct { + const struct pch_gpio_set3 *mode; + const struct pch_gpio_set3 *direction; + const struct pch_gpio_set3 *level; + const struct pch_gpio_set3 *reset; + } set3; +}; + +void ich_gpio_set_gpio_map(const struct pch_gpio_map *map); + #endif /* _X86_GPIO_H_ */ |